EA3059C

3 通道同步降压整合型 开关电源转换器 EA3059C 规格书 概述 EA3059C是一款整合了3通道同步降压电路的整合型开关电源转换器，适合5V适配器输入及单颗锂电 池输入之应用。其输入电压范围为2.7V至5.5V，无论是在轻载或重载之工作环境下皆能提供很高的 输出效率。EA3059C内置3通道功率开关管和同步整流开关管以及内部补偿线路，能够减少外围元器 件进而降低设计成本，各自独立的致能控制脚能够提供各通道电源启动时序安排的最大灵活性。 EA3059C使用24 pin QFN 4mm x 4mm封装，能够提供最佳散热性及减少PCB板面积。 特性     2.7V 至 5.5V 输入电压范围 3通道降压转换器 可调输出电压范围 0.6V 至输入电压 通道1/通道2/通道3 最大持续工作电流： 3A/2A/2A (3通道总输出功率需低于10W) 通道1/通道2/通道3 最大瞬间负载电流： 3.5A/2.5A/2.5A 180° 开关相位差架构 恒定开关频率1.5MHz 允许低压差工作，占空比高达100% 独立致能脚位控制 内置补偿线路 逐周期电流限制保护 短路保护 自动回复过温保护 24-pin 4mm x 4mm QFN 封装 应用    机顶盒 智能型手机 无线路由器 脚位图 GND1 NC FB1 NC 18 17 16 15 14 13 2 NC AGND (上视图) NC 19 12 VCC 20 11 VIN1 AGND 21 10 EN1 EN3 22 9 EN2 VIN3 23 8 VIN2 LX3 24 7 LX2 LX1 2 3 4 5 6 VCC AGND FB2 GND2 GND3 1 FB3 25 QFN 4x4-24 1 版权所有© 2014 申风集成电路设计(上海)有限公司 Ver. 1.1 EA3059C 3 通道整合型电源管理芯片 规格书 脚位定义 脚位名 GND3 功能描述 脚位号 Power ground pin of CH3. 1 FB3 Feedback input of CH3. Connect to output voltage with a resistor divider. 2 VCC Input supply pin for internal control circuit. AGND FB2 Analog ground pin. 3, 20 4, 18, 21 Feedback input of CH2. Connect to output voltage with a resistor divider. 5 Power ground pin of CH2. 6 LX2 Internal MOSFET switching output of CH2. Connect LX2 pin with a low pass filter circuit to obtain a stable DC output voltage. 7 VIN2 Power input pin of CH2. Recommended to use a 10uF MLCC capacitor between VIN2 pin and PGND2 pin. 8 EN2 CH2 turns on/turns off control input. Don’t leave this pin floating. 9 EN1 CH1 turns on/turns off control input. Don’t leave this pin floating. 10 VIN1 Power input pin of CH1. Recommended to use a 10uF MLCC capacitor between VIN1 pin and PGND1 pin. 11 LX1 Internal MOSFET switching output of CH1. Connect LX1 pin with a low pass filter circuit to obtain a stable DC output voltage. 12 Power ground pin of CH1. 13 FB1 Feedback input of CH1. Connect to output voltage with a resistor divider. 14 NC No connect. EN3 CH3 turns on/turns off control input. VIN3 Power input pin of CH3. Recommended to use a 10uF MLCC capacitor between VIN3 pin and PGND3 pin. 23 LX3 Internal MOSFET switching output of CH3. Connect LX3 pin with a low pass filter circuit to obtain a stable DC output voltage. 24 Exposed Pad The Exposed Pad must be soldered to a large PCB copper plane and connected to GND for appropriate dissipation. 25 GND2 GND1 Ver. 1.1 15, 16, 17, 19 Don’t leave this pin floating. 版权所有© 2014 申风集成电路设计(上海)有限公司 22 2 EA3059C 3 通道整合型电源管理芯片 规格书 内部架构框图 VIN1 HSMOSFET LX1 Buck Converter 1 VCC EN1 LSMOSFET PGND1 VIN2 HSMOSFET LX2 Buck Converter 2 EN2 LSMOSFET PGND2 VIN3 HSMOSFET LX3 Buck Converter 3 LSMOSFET EN3 PGND3 AGND 图 1. EA3059C 内部功能模块框图 3 版权所有© 2014 申风集成电路设计(上海)有限公司 Ver. 1.1 EA3059C 3 通道整合型电源管理芯片 规格书 绝对最大额定参数 参数 Input Voltage (VVIN1, VVIN2, VVIN3, VVCC) LX Pin Voltage (VLX1, VLX2, VLX3) All Other Pins Voltage 范围 -0.3V to +6.5V -0.3V to VVINX+0.3V -0.3V to +6.5V Ambient Temperature operating Range (TA) -40°C to +85°C Maximum Junction Temperature (TJmax) +150°C Lead Temperature (Soldering, 10 sec) +260°C Storage Temperature Range (TS) -65°C to +150°C Note (1):Stresses beyond those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to “Absolute Maximum Ratings” conditions for extended periods may affect device reliability and lifetime. 封装热特性 参数 数值 QFN 4x4-24 Thermal Resistance (θJC) 7.5°C/W QFN 4x4-24 Thermal Resistance (θJA) 50°C/W QFN 4x4-24 Power Dissipation at TA=25°C (PDmax) 2.5W Note (1): PDmax is calculated according to the formula: PDMAX=(TJMAX-TA)/ θJA. 建议工作条件 参数 Input Voltage (VVIN1, VVIN2, VVIN3, VVCC) Junction Temperature Range (TJ) Ver. 1.1 版权所有© 2014 申风集成电路设计(上海)有限公司 范围 +2.7V to +5.5V -40°C to +125°C 4 EA3059C 3 通道整合型电源管理芯片 规格书 电气特性 VVINX=3.6V, VVCC=3.6V, TA=25°C, unless otherwise noted 参数 符号 测试条件 最小 值 典型 值 最大 值 单位 Input Supply Voltage Input Voltage Control Circuit Input Voltage VINX 2.7 5.5 V VVCC 2.7 5.5 V Buck Regulator 1 Shutdown Supply Current ISD VEN = 0V 0.1 1 uA Quiescent Current IQ Non-switching, No Load 40 80 uA 2.1 2.3 V UVLO Threshold VUVLO UVLO Hysteresis VUV-HYST Output Load Current ILOAD Reference Voltage VREF Switching Frequency FSW Short Frequency FSW-SHORT PMOS Current Limit VVIN Rising 1.9 0.1 ILOAD = 100mA 3 A 0.588 0.6 0.612 V 1 1.5 2 MHz VOUT = 0V ILIM-P V 4 300 KHz 5 A PMOS On-Resistance RDS(ON)-P ILOAD = 100mA 90 mΩ NMOS On-Resistance RDS(ON)-N ILOAD = 100mA 85 mΩ Enable Pin Input Low Voltage VEN-L Enable Pin Input High Voltage VEN-H 2 V Maximum Duty Cycle DMAX 100 % 0.4 V Buck Regulator 2, 3 Shutdown Supply Current ISD VEN = 0V 0.1 1 uA Quiescent Current IQ Non-switching, No Load 40 80 uA 2.1 2.3 V UVLO Threshold VUVLO UVLO Hysteresis VUV-HYST Output Load Current ILOAD Reference Voltage VREF Switching Frequency FSW 5 VVIN Rising 1.9 0.1 ILOAD = 100mA V 2 A 0.588 0.6 0.612 V 1 1.5 2 MHz 版权所有© 2014 申风集成电路设计(上海)有限公司 Ver. 1.1 EA3059C 3 通道整合型电源管理芯片 规格书 电气特性 VVINX=3.6V, VVCC=3.6V, TA=25°C, unless otherwise noted 参数 Short Frequency PMOS Current Limit 符号 FSW-SHORT 测试条件 最小 值 VOUT = 0V ILIM-P 4 典型 值 最大 值 单位 300 KHz 5 A PMOS On-Resistance RDS(ON)-P ILOAD = 100mA 100 mΩ NMOS On-Resistance RDS(ON)-N ILOAD = 100mA 90 mΩ Enable Pin Input Low Voltage VEN-L Enable Pin Input High Voltage VEN-H 2 V Maximum Duty Cycle DMAX 100 % 0.4 V Thermal Shutdown Thermal Shutdown Threshold TOTP 165 °C Thermal Shutdown Hysteresis THYST 30 °C Note (1): MOSFET on-resistance specifications are guaranteed by correlation to wafer level measurements. (2): Thermal shutdown specifications are guaranteed by correlation to the design and characteristics analysis. Ver. 1.1 版权所有© 2014 申风集成电路设计(上海)有限公司 6 EA3059C 3 通道整合型电源管理芯片 规格书 应用线路参考 L1 1.5uH VOUT1 1.2V/3A C4 22uF x2 R1 100KΩ C7 220pF C2 10uF VIN3 LX2 1.5V/2A C5 22uF R3 150KΩ R4 100KΩ C8 220pF C3 10uF VCC FB2 C4 1uF L3 1.5uH VOUT3 3.3V/2A VIN2 L2 1.5uH VOUT2 LX3 C6 22uF R5 510KΩ C9 220pF 5V C1 10uF x2 FB1 R2 100KΩ VIN VIN1 LX1 EN1 ON OFF EN2 ON OFF EN3 ON OFF FB3 R6 110KΩ AGND PGND1 PGND2 PGND3 EA3059C 图 2. 典型应用线路图 订货需知 型号 封装 包装 EA3059CQDR QFN 4mm x 4mm-24 Tape & Reel / 3000 Note (1): “QD”: Package type code. (2): “R”: Tape & Reel. 7 版权所有© 2014 申风集成电路设计(上海)有限公司 Ver. 1.1 EA3059C 3 通道整合型电源管理芯片 规格书 性能测试 VIN=5V, VVCC=5V, VOUT1=1.2V, VOUT2=1.5V, VOUT3=3.3V, L1=1.5uH, L2=1.5uH, L3=1.5uH, TA=25°C, unless otherwise noted Efficiency vs. Load Current 95 90 90 Efficiency (%) Efficiency (%) Efficiency vs. Load Current 95 85 80 75 70 65 VOUT=1.2V VIN = 5V 85 80 75 70 65 60 VIN = 5V 60 10 100 ILOAD (mA) 1000 10 85 80 75 70 VOUT=3.3V VIN = 5V 65 Output Voltage (V) Efficiency (%) 90 60 3.0 100 ILOAD (mA) VOUT=1.5V 2.0 VOUT=3.3V 1.5 100 VOUT=1.2V VOUT=1.5V VOUT=3.3V 1.5 1.0 -40-30-20-10 0 10 20 30 40 50 60 70 80 90 TA (°C) Switching Frequency (MHz) VIN = 5V 500 900 1300 1700 2100 2500 Load Current (mA) Freq. vs. Ambient Temp. VOUT vs. Ambient Temp. Output Voltage (V) VOUT=1.2V 2.5 1000 3.5 Ver. 1.1 VIN = 5V 1.0 10 2.0 1000 3.5 95 2.5 100 ILOAD (mA) Load Regulation Efficiency vs. Load Current 100 3.0 VOUT=1.5V 1.70 1.65 1.60 1.55 1.50 1.45 VIN = 5V ILOAD = 1A each 1.40 -20 -10 0 10 20 30 40 50 60 70 80 90 TA (°C) 版权所有© 2014 申风集成电路设计(上海)有限公司 8 EA3059C 3 通道整合型电源管理芯片 规格书 性能测试 VIN=5V, VVCC=5V, VOUT1=1.2V, VOUT2=1.5V, VOUT3=3.3V, L1=1.5uH, L2=1.5uH, L3=1.5uH, TA=25°C, unless otherwise noted ILOAD1=2.5A ILOAD2=2A ILOAD3=2A ILOAD=0A each VIN VIN VOUT1 VOUT1 VOUT2 VOUT2 VOUT3 VOUT3 VIN Power On Waveform VIN Power On Waveform ILOAD1=2.5A ILOAD2=2A ILOAD3=2A ILOAD=0A each VENX VENX VOUT1 VOUT1 VOUT2 VOUT2 VOUT3 VOUT3 EN Power On Waveform EN Power On Waveform ILOAD1=2.5A ILOAD2=2A ILOAD3=2A ILOAD=0A each VENX VENX VOUT1 VOUT1 VOUT2 VOUT2 VOUT3 VOUT3 EN Power Off Waveform 9 EN Power Off Waveform 版权所有© 2014 申风集成电路设计(上海)有限公司 Ver. 1.1 EA3059C 3 通道整合型电源管理芯片 规格书 性能测试 VIN=5V, VVCC=5V, VOUT1=1.2V, VOUT2=1.5V, VOUT3=3.3V, L1=1.5uH, L2=1.5uH, L3=1.5uH, TA=25°C, unless otherwise noted ILOAD1=2.5A ILOAD2=2A ILOAD3=2A ILOAD3=0A VLX1 VLX2 VLX3 VLX3 VLX1,2,3 Switching Waveform VLX3 Switching Waveform ILOAD=0A each VOUT1 (AC) VOUT1 (AC) VOUT2 (AC) VOUT2 (AC) VOUT3 (AC) VOUT3 (AC) Output Ripple Waveform Ver. 1.1 ILOAD1=2.5A ILOAD2=2A ILOAD3=2A Output Ripple Waveform 版权所有© 2014 申风集成电路设计(上海)有限公司 10 EA3059C 3 通道整合型电源管理芯片 规格书 功能描述 PFM/PWM Operation Each of the buck regulators can be operated at PFM/PWM mode. If the output current is less than 150mA (typ.), the regulators automatically enters the PFM mode. The output voltages and output ripples at PFM mode are higher than the output voltages and output ripples at PWM mode. But at very light load, the PFM mode operation provides higher efficiency than PWM mode operation. Enable Control The EA3059C is a high efficiency Power Management IC which is designed for IPC applications. It incorporates three 1A synchronous buck regulators and can be controlled by individual EN pins. The start-up time for each channel can be programmed by using the circuit shown as below: VINX 5V VINx 100KΩ ENx 10nF~100nF GND EA3059C 180° Phases Shifted Architecture In order to reduce the input ripple current, the EA3059C applied 180° phases shifted architecture. Buck1 and Buck3 have the same phase and Buck2 is 180° out of phase. This architecture allows the system board has less ripple current, and thus can reduce EMI. Over Current Protection The EA3059C internal three regulators have their own cycle-by-cycle current limit circuits. When the inductor peak current exceeds the current limit threshold, the output voltage starts to drop until FB pin voltage is below the threshold, typically 30% below the reference. Once the threshold is triggered, the switching frequency is reduced to 300KHz (typ.). Thermal Shutdown The EA3059C will automatically disabled if the die temperature is higher than the thermal shutdown threshold point. To avoid unstable operation, the hysteresis of thermal shutdown is about 30°C. 11 版权所有© 2014 申风集成电路设计(上海)有限公司 Ver. 1.1 EA3059C 3 通道整合型电源管理芯片 规格书 使用说明 Output Voltage Setting Each of the regulators output voltage can be set via a resistor divider (ex. R1, R2). The output voltage is calculated by following equation: R1 VOUT1  0.6   0.6 V R2 VOUT1 L1 1.5uH LX1 1.2V R1 100KΩ C10 220pF R2 100KΩ FB1 GND EA3059C The following table lists common output voltage and the corresponding R1, R2 resistance value for reference. 输出电压 分压电阻 R1 分压电阻 R2 精度 3.3V 510KΩ 110KΩ 1% 1.8V 200KΩ 100KΩ 1% 1.5V 150KΩ 100KΩ 1% 1.2V 100KΩ 100KΩ 1% Input / Output Capacitors Selection The input capacitors are used to suppress the noise amplitude of the input voltage and provide a stable and clean DC input to the device. Because the ceramic capacitor has low ESR characteristic, so it is suitable for input capacitor use. It is recommended to use X5R or X7R MLCC capacitors in order to have better temperature performance and smaller capacitance tolerance. In order to suppress the output voltage ripple, the MLCC capacitor is also the best choice. The suggested part numbers of input / output capacitors are as follows: 厂商 型号 容值 耐压值 特性参数 尺寸 TDK C2012X5R1A106M 10uF 10V X5R 0805 TDK C3216X5R1A106M 10uF 10V X5R 1206 TDK C2012X5R1A226M 22uF 10V X5R 0805 TDK C3216X5R1A226M 22uF 10V X5R 1206 Output Inductor Selection The output inductor selection mainly depends on the amount of ripple current through the inductor ∆IL. Large ∆IL will cause larger output voltage ripple and loss, but the user can use a smaller inductor to save cost and space. On the contrary, the larger inductance can get smaller ∆IL and Ver. 1.1 版权所有© 2014 申风集成电路设计(上海)有限公司 12 EA3059C 规格书 3 通道整合型电源管理芯片 thus the smaller output voltage ripple and loss. But it will increase the space and the cost. inductor value can be calculated as: VPWR  VOUT VOUT L  ΔIL  FSW VPWR For most applications, 1.0uH to 2.2uH inductors are suitable for EA3059C. The Power Dissipation The total output power dissipation of EA3059C should not to exceed the maximum 6W range. The total output power dissipation can be calculated as: PD  total  VOUT1  IOUT1  VOUT2  IOUT2  VOUT3  IOUT3 PCB Layout Recommendations Layout is very critical for PMIC designs. For EA3059C PCB layout considerations, please refer to the following suggestions to get best performance.  It is suggested to use 4-layer PCB layout and place LX plane and output plane on the top layer, place VIN plane in the inner layer.  The top layer SMD input and output capacitors ground plane should be connected to the internal ground layer and bottom ground plane individually by using vias.  The AGND should be connected to inner ground layer directly by using via.  High current path traces need to be widened.  Place the input capacitors as close as possible to the VINx pin to reduce noise interference.  Keep the feedback path (from VOUTX to FBx) away from the noise node (ex. LXx). LXx is a high current noise node. Complete the layout by using short and wide traces.  The top layer exposed pad ground plane should be connected to the internal ground layer and bottom ground plane by using a number of vias to improve thermal performance.  Place the input capacitors as close as possible to the VINx pin to reduce noise interference. 13 版权所有© 2014 申风集成电路设计(上海)有限公司 Ver. 1.1 EA3059C 3 通道整合型电源管理芯片 规格书 封装讯息 QFN 4mm x 4mm-24 Package R D M N S E P Q O Top View Recommended Layout Pattern D1 L 1 H E1 H1 H2 C A Bottom View Side View Unit: mm M 尺寸 典型值 2.60 0.55 N 2.60 3.95 4.05 O 0.30 E 3.95 4.05 P 0.80 D1 2.30 2.70 Q 0.50 E1 2.30 2.70 R 4.70 L 0.35 0.45 S 4.70 H 0.70 0.90 H1 0.17 0.25 H2 0.00 0.05 符号 尺寸 A 最小值 0.18 最大值 0.30 C 0.45 D Ver. 1.1 符号 版权所有© 2014 申风集成电路设计(上海)有限公司 14