SCT63140
SILICONCONTENT
TECHNOLOGY
15W High-Integration, High-Efficiency PMIC for Wireless Power Transmitter
FEATURES
DESCRIPTION
•
•
•
•
The SCT63140 is a highly integrated Power
Management IC allows achieving high performance,
high efficiency and cost effectiveness of wireless
power transmitter system compliant with WPC
specification to support up to 15W power transfer,
working with a wireless application specific controller
or a general MCU based transmitter controller.
•
•
•
•
•
•
•
•
•
VIN Input Voltage Range: 4.2V-20V
PVIN Input Voltage Range: 1V-15V
Up to 15W Power Transfer
Integrated Full-Bridge Power Stage with 16-mΩ
Rdson of Power MOSFETs
Integrated 5V-100mA LDO
Optimized for EMI Reduction
Build-in 3.3V-100mA LDO
Integrated Lossless Input Current Sensor with
±2% accuracy for FOD and current
Demodulation
3.3V and 5V PWM Signal Logic Compatible
Input Under-Voltage Lockout
Over Current Protection
Over Temperature Protection
3mm*3mm QFN-15L Package
APPLICATIONS
•
•
•
WPC Compliant Wireless Chargers of 5W to
15W Systems for Mobiles, Tablets and Wearable
Devices
General Wireless Power Transmitters for
Consumer, Industrial and Medical Equipment
Proprietary Wireless Chargers and Transmitters
This device integrates a 4-MOSFETs full bridge
power stage，gate drivers, a 5V LDO, a 3.3V LDO
and input current sensor for both system efficiency
and easy-to-use.
The proprietary gate driving scheme optimizes the
performance of EMI reduction to save the system
cost and design. The proprietary lossless current
sensing circuitry with ±2% accuracy monitors input
current of full bridge to support Foreign Object
Detection FOD and current demodulation. The buildin 5V and 3.3V low dropout regulator LDO can
provide power supplies to transmitter controller and
external circuitries.
The SCT63140 features input Under-Voltage Lockout UVLO, over current, short circuit protection, and
over temperature protection.
The SCT63140 is available in a compact 3mm*3mm
QFN package.
TYPICAL APPLICATION
PVIN
Power Transfer Efficiency with 10W RX @ Vout=9V
PVIN1
C1
PGND
C2
PVIN2
90.00
BST1
SW1
C8
80.00
70.00
VIN
C3
VIN
GND
SW2
BST2
C9
5V
VDD
C10
EN
PWM1
3.3V
V3P3
C11
PWM2
ISNS
Efficiency(%)
SCT63140
60.00
50.00
40.00
30.00
20.00
10.00
Vout=9V
0.00
0
2
4
6
8
10
Output Power(W)
For more information www.silicontent.com © 2019 Silicon Content Technology Co., Ltd.
All Rights Reserved
SCT63140
DEVICE ORDER INFORMATION
PART NUMBER
PACKAGE MARKING
(1)
SCT63140FMA
(1) For Tape & Reel, Add Suffix R (e.g. SCT63140FMAR)
PACKAGE DISCRIPTION
3140
QFN-15L
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(1)
Over operating free-air temperature unless otherwise noted
DESCRIPTION
MIN
MAX
UNIT
VIN
-0.3
24
V
PVIN1, PVIN2
-0.3
17
V
SW1,SW2
-1
17
V
BST1,BST2
-0.3
23
V
BST1-SW1,BST2-SW2
VDD, V3P3, ISNS, EN
PWM1, PWM2
(2)
Operating junction temperature TJ
-0.3
6
V
-0.3
6
V
-40
125
°C
PWM1 PWM2
15
Storage temperature TSTG
-65
150
PGND
PVIN2
EN
13
12
1
11
BST1
10
SW1
9
SW2
8
BST2
2
3
°C
CONFIDEN TIAL P relimi nary D atashe et
(1)
PVIN1
14
ISNS
4
5
6
7
VIN
GND
V3V
VDD
Figure 1. Top view 15-Lead QFN 3mm*3mm
Stresses beyond those listed under Absolute Maximum Rating may cause device permanent damage. The device is not guaranteed to
function outside of its Recommended Operation Conditions.
The IC includes over temperature protection to protect the device during overload conditions. Junction temperature will exceed 150°C
when over temperature protection is active. Continuous operation above the specified maximum operating junction temperature will
reduce lifetime.
(2)
PIN FUNCTIONS
NAME
NO.
PVIN1
1
PGND
2
PVIN2
3
VIN
4
GND
V3P3
5
6
PIN FUNCTION
Input supply voltage of half-bridge FETs Q1 and Q2. Connected to the drain of high
side FET Q1. a local bypass capacitor from PVIN1 pin to PGND pin should be added.
Path from PVIN1 pin to high frequency bypass capacitor and PGND must be as short
as possible.
PGND is the common power ground of the full bridge, connected to the source
terminal of low side FETs Q2 and Q4 internally.
Input supply voltage of half-bridge FETs Q3 and Q4. Connected to the drain of high
side FET Q1. Local bypass capacitor from PVIN1 pin to PGND pin should be added.
Path from PVIN1 pin to high frequency bypass capacitor and PGND must be as short
as possible.
Input supply voltage of the 5V LDO. Add a local bypass capacitor from VIN pin to GND
pin. Path from VIN pin to high frequency bypass capacitor and GND must be as short
as possible.
Ground.
3.3V LDO output. Connect 2.2uF capacitor to ground.
2 For more information www.silicontent.com© 2019 Silicon Content Technology Co., Ltd.
All Rights Reserved
SCT63140
VDD
7
BST2
8
SW2
9
SW1
10
BST1
11
EN
12
ISNS
13
PWM2
14
PWM1
15
Output voltage of the 5V LDO. Connect 2.2uF capacitor from this pin to GND pin. VDD
is also the input power supply for gate driver of power stage and the 3.3V LDO.
Power supply bias for the high-side power MOSFET gate driver of Q3 as shown in the
block diagram. Connect a 0.1uF capacitor from BST2 pin to SW2 pin.
Switching node of the half-bridge FETs Q3 and Q4.
Switching node of the half-bridge FETs Q1 and Q2.
Power supply bias for the high-side power MOSFET gate driver of Q1 as shown in the
block diagram. Connect a 0.1uF capacitor from BST1 pin to SW1 pin.
Enable pin. Pull the pin high or keep it floating to enable the IC. When the device is
enabled, 5V LDO will start to work if VIN higher than UVLO threshold. After VDD is
established, power stage responds to PWM input logic then.
Current detection output. The voltage of the pin is proportional to the input current.
PWM logic input to the FET Q3 and Q4 as shown in the Block Diagram. Logic HIGH
turns off the low-side FET Q4, and turns on the high-side FET Q3. Logic LOW turns off
the high-side FET Q3 and turns on the low-side FET Q4. When PWM input is in the tristate mode, both Q3 and Q4 are turned off.
PWM logic input to the FET Q1 and Q2 as shown in the Block Diagram. Logic HIGH
turns off the low-side FET Q2, and turns on the high-side FET Q1. Logic LOW turns off
the high-side FET Q1 and turns on the low-side FET Q2. When PWM input is in the tristate mode, both Q1 and Q2 are turned off.
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range unless otherwise noted
PARAMETER
VIN
DEFINITION
CONFIDEN TIAL P relimi anry D atashe et
Input voltage range
Input voltage range
Operating junction temperature
PVIN
TJ
MIN
MAX
UNIT
4.2
1
-40
20
15
125
V
V
°C
MIN
MAX
UNIT
-2
+2
kV
-1
+1
kV
ESD RATINGS
PARAMETER
VESD
DEFINITION
Human Body Model(HBM), per ANSI-JEDEC-JS-001-2014
(1)
specification, all pins
Charged Device Model(CDM), per ANSI-JEDEC-JS-002(2)
2014specification, all pins
(1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.
THERMAL INFORMATION
PARAMETER
THERMAL METRIC
RθJA
Junction to ambient thermal resistance
RθJC
Junction to case thermal resistance
(1)
(1)
DFN-19L
48
45
UNIT
°C/W
(1) SCT provides RθJA and RθJC numbers only as reference to estimate junction temperatures of the devices. RθJA and RθJC are not a
characteristic of package itself, but of many other system level characteristics such as the design and layout of the printed circuit
board (PCB) on which the SCT63140 is mounted, thermal pad size, and external environmental factors. The PCB board is a heat sink
that is soldered to the leads of the SCT63140. Changing the design or configuration of the PCB board changes the efficiency of the
heat sink and therefore the actual RθJA and RθJC.
For more information www.silicontent.com© 2019 Silicon Content Technology Co., Ltd. All Rights Reserved 3
SCT63140
ELECTRICAL CHARACTERISTICS
VPVIN1=VPIN2=12V, VDD=5V, typical value is tested under 25°C.
SYMBOL
PARAMETER
TEST CONDITION
Input supplies and UVLO
VIN
Operating input voltage
PVIN
ISHDN
ISHDN_PVIN
Shutdown current from PVIN1,PVIN2
IVINQ
Quiescent current from VIN pin
IPVINQ
Quiescent current from PVIN1, PVIN2
VIN_UVLO
VDD_UVLO
TYP
4.2
Operating input voltage
VIN UVLO Threshold
Hysteresis
VDD UVLO Threshold
Hysteresis
Shutdown current from VIN pin
MIN
1
VIN rising
VDD rising
EN=0V, VIN=12V
EN=0V, PVIN=12V
EN floating, VDD=5V, no
loading on LDO
EN floating, VDD=5V, no
loading on LDO
MAX
UNIT
20
V
15
V
3.6
400
3.8
440
1
3
V
mV
V
mV
μA
1
3
uA
300
uA
50
uA
ENABLE INPUTS and PWM logic
VEN_H
Enable high threshold
1.18
V
VEN_L
Enable low threshold
1.1
V
VIH
PWM1, PWM2 Logic level high
V3P3=3.3V, VDD=5V
VIL
PWM1, PWM2 Logic level low
V3P3=3.3V, VDD=5V
VTS
PWM1, PWM2 Tri-state voltage
2.65
V
1.2
0.55
V
2
V
CONFIDEN TIAL P relimi nary D atashe et
Power Stage
VBST1-VSW1=5V, VBST2VSW2=5V
VDD=5V
RDSON_Q1 Q3
High-side MOSFET Q1 Q3 on-resistance
RDSON_Q2 Q4
Low-side MOSFET Q2 Q4 on-resistance
ILIM
How-side current limit threshold
5V LDO
VDD
Output voltage
IDD
Output current Capability
3.3V LDO
V3P3
Output voltage
Cout=1uF, VDD=5V
I3P3
Output current Capability
VDD=5V
ISC
Short current
16
mΩ
16
mΩ
12.5
Cout=10uF
4.95
5
A
5.05
100
3.267
3.3
V
mA
3.333
V
100
mA
50
mA
Current Sense
VISNS0
Voltage with no input current
RISNS
Input current to output voltage gain
IPGND=0A ,Tj=25℃
PWM1=PWM2=0V
VISNS=VISNS0+IPGND*RISNS
VISNS1
Voltage with 0.6A input current
VISNS2
0.585
0.6
0.615
V
0.98
1
1.02
V/A
IPVIN=0.6A, Tj=25℃
1.176
1.2
1.224
V
Voltage with 1A input current
IPVIN=1A, Tj=25℃
1.568
1.6
1.632
V
Thermal shutdown threshold
Hysteresis
TJ rising
Protection
TSD
4 For more information www.silicontent.com© 2019 Silicon Content Technology Co., Ltd.
155
35
All Rights Reserved
°C
°C
SCT63140
90.00
90.00
80.00
80.00
70.00
70.00
60.00
60.00
Efficiency(%)
Efficiency(%)
TYPICAL CHARACTERISTICS
50.00
40.00
30.00
50.00
40.00
30.00
20.00
20.00
10.00
10.00
Vout=5V
Vout=9V
0.00
0.00
0
1
2
3
4
0
5
2
4
Figure 2. Transfer Efficiency with 5W RX@ Vout=5V
10
6
80.00
5
70.00
4
60.00
Vout(V)
Efficiency(%)
8
Figure 3. Transfer Efficiency with 10W RX@ Vout=9V
90.00
50.00
CONFIDEN TIAL P relimi anry D atashe et
40.00
3
2
30.00
20.00
1
10.00
Vout=12V
0
0.00
0
3
6
9
12
0
15
0.02
0.04
0.06
0.08
0.1
0.12
0.1
Iout(A)
Output Power(W)
Figure 5. 5V LDO Iout vs Vout
Figure 4. Transfer Efficiency with 15W RX@ Vout=12V
3.5
3
3
2.7
2.4
Vsense(V)
2.5
Vout(V)
6
Output Power(W)
Output Power(W)
2
1.5
1
2.1
1.8
1.5
1.2
0.5
0.9
0.6
0
0
0.05
0.1
0.15
0.2
Iout(A)
Figure 6. 3.3V LDO Iout vs Vout
0.25
0.3
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
2.2
Iin(A)
Figure 7. Current Sense Output Voltage vs Iin
For more information www.silicontent.com© 2019 Silicon Content Technology Co., Ltd. All Rights Reserved 5
SCT63140
FUNCTIONAL BLOCK DIAGRAM
VIN
VDD
5V
LDO
Enable
BIAS
EN logic
VIN UVLO
Reference
EN
GND
V3P3
VDD
UVLO
3.3V
LDO
3-stage
logic
PWM1
3-stage
logic
PWM2
CONFIDEN TIAL P relimi nary D atashe et
PVN2
PVN1
Over Current
Detection
Over Current
Detection
BST2
BST1
Q1
Q3
SW1
VDD
PWM1
Control
PWM2
Control
Q2
SW2
VD
D
Current sense
I/V
ISNS
PGND
Figure 8. Functional Block Diagram
6 For more information www.silicontent.com© 2019 Silicon Content Technology Co., Ltd.
All Rights Reserved
Q4
SCT63140
OPERATION
Overview
The SCT63140 is a highly integrated power management unit optimized for wireless power transmitter
applications. This device integrates the power functions required to a wireless power transmitter including 5V
output LDO as power supply for external transmitter controller, full bridge power stage to convert DC input power
to AC output for driving LC resonant circuit, lossless current sensing with ±2% accuracy, 3.3V output LDO for
powering MCU.
The SCT63140 has three power input pins. VIN is connected to the power FETs of 5V LDO. PVIN1 and PVIN2
are connected to the power FETs of the full bridge and conducts high currents for power transfer.
VIN and PVIN1, PVIN2 can be powered separately for more flexibility of system power design. The operating
voltage range for VIN is from 4.2V to 20V. An Under-voltage Lockout(UVLO) circuit monitors the voltage of VIN
pin and disable the IC operation when VIN voltage falls below the UVLO threshold of 3.2V typically. The maximum
operating voltage for PVIN is up to 15V while the minimum voltage accepted can be down to 1V. Another UVLO
circuit also supervise the VDD voltage which is the power supply for gate drivers of full bridge MOSFETs. Full
bridge will work when VDD UVLO release.
Two independent PWM signals control two separate half bridge MOSFETs with internal adaptive non-overlap
circuitry to prevent the shoot-through of MOSFETs in each bridge. PWM logics are compatible for both 3.3V and
5V IOs so the SCT63140 can accept PWM signal from the controller with using either 3.3V or 5V power supply.
The full bridge of power MOSFETs includes proprietary designed gate driver scheme to resist switching node
ringing without sacrificing MOSFET turn-on and turn-off time, which further erases high frequency radiation EMI
noise caused by the MOSFETs hard switching. This allows the user to reduce the system cost and design effort
for EMI reduction.
CONFIDEN TIAL P relimi anry D atashe et
The SCT63140 full protection features include VIN and VDD under-voltage lockout, over current protection with
cycle-by-cycle current limit and hiccup mode, output hard short protection for 4-MOSFETs full bridge, current limit
and current fold back at hard short for two LDOs and whole chip thermal shutdown protection.
Enable and Start up Sequence
When the VIN pin voltage rises above 3.6V and the EN pin voltage exceeds the enable threshold of 1.18V, the 5V
output LDO enables at once. And the device disables when the VIN pin voltage falls below 3.2V or when the EN
pin voltage is below 1.1V. VDD ramp up after 5V LDO works, and also the V3V. Once VDD rise up to 3.8V and
V3V is higher than 3V, 4-MOSFETs full bridge allows PWM signal to control for switching. PWM input cannot
control full bridge of MOSFETs if VDD drop to 3.36V or V3V drop to 2.7V.
An internal 1.5uA pull up current source to EN pin allows the device enable when EN pin is floating to simply the
system design. If an application requires a higher system under voltage lockout threshold, two external resistors
divider(R1 and R2) in Figure 9 can be used to achieve an expected system UVLO. The UVLO rising and falling
threshold can be calculated by Equation 1 and Equation 2 respectively.
VIN
Vrise = 1.18 ∗ �1 +
Vfall
R1
� − 1.5uA ∗ R
R2
R1
= 1.1 ∗ �1 + � − 5.5uA ∗ R1
R2
1.5uA
(1)
EN
(2)
4uA
R1
R2
20K
+
1.21V
Figure 9. System UVLO by enable divider
For more information www.silicontent.com© 2019 Silicon Content Technology Co., Ltd. All Rights Reserved 7
SCT63140
5V LDO
The SCT63140 has an integrated low-dropout voltage regulator which powered from VIN and supply regulated 5V
voltage on VDD pin. The output current capability is 100mA. This LDO can be used to bias the supply voltage of
external transmitter controller directly.
It is recommended to connect a decoupling ceramic capacitor of 1uF to 10uF to the VDD pin. Capacitor values
outside of the range may cause instability of the internal linear regulator.
Full bridge and PWM Control
The SCT63140 integrate full bridge power stage with only 16mohm on-resistance for each power MOSFET
optimized for wireless power transmitter driving the LC resonant circuit. This full bridge is able to operate in a wide
switching frequency range from 20KHz to 400KHz for different applications which is completely compatible with
WPC's frequency requirement from 100KHz to 205KHz.
PWM1 input controls the half bridge comprised of high side MOSFET Q1 and low side MOSFET Q2, and PWM2
input controls the half bridge comprised of high side MOSFET Q3 and low side MOSFET Q4 as shown in block
diagram. The PWM1 and PWM2 independently control the SW1 and SW2 duty cycle and frequency. Logic HIGH
will turn off low side FET and turn on high side FET, and logic LOW will turn off high side FET and turn on low side
FET.
PWM1 and PWM2 also support tri-state input. When PWM input logic first enters tri-state either from logic HIGH
or logic LOW, the states of its controlled FETs stay the same. If the PWM input stays in the tri-state for more than
60ns, its controlled FETs are all turned off, and the corresponding SW output becomes high impedance. The FETs
stay off until the PWM logic reaches logic HIGH or logic LOW threshold.
An external 100nF ceramic bootstrap capacitor between BST1 and SW1 pin powers floating high-side power
MOSFET Q1's gate driver, and the other 100nF bootstrap capacitor between BST2 and SW2 pin powers for the
Q2's. When low side FET is on which means SW is low, the bootstrap capacitor is charged through internal path
by VDD power supply rail.
CONFIDEN TIAL P relimi nary D atashe et
PWM cannot been kept as high level for more than 2ms since the voltage of bootstrap capacitor will be
discharged by internal leakage current if high side FET keeps on.
Full Bridge Over Current Protection
The SCT63140 integrates cycle-by-cycle current limit and hiccup mode for over-current protection. The current of
the high side FET Q1 和 Q3 is sensed and compared to the current limit threshold during each switching cycle. If
the current exceeds the threshold, 12.5A typical, the high side FET turns off immediately in present cycle to avoid
current increasing even PWM signal is still kept in high level. The over current counter is incremented. If one high
side FET occurs over current in 5 consecutive cycles, then all 4 internal FETs are turned off regardless of the
PWM inputs. The full bridge enters hiccup mode and will attempt to restart after a time-out period of 24ms typically.
Current Sense
The SCT63140 has a proprietary lossless average current sensing circuit that measures the average input current
of full bridge with ±2% accuracy and reports a proportional voltage directly to the ISNS pin. This voltage
information on ISNS pin can be send to specialized controller or general MCU for Foreign Object Detection FOD
and current demodulation.
When the full bridge of MOSFETs does not work, no current flows to PGND. The DC bias voltage on ISNS pin is
600mV.This DC bias helps set up a suitable voltage bias for the following analog to digital converter in MCU or
amplifier for current demodulation. The average input current to voltage conversion gain on ISNS is 1V/A. The
equation 3 represent the corresponding relation for the output voltage on ISNS pin and average current to PGND
from full bridge.
VISNS = 600mV + IPGND ∗ 1V/A
(3)
8 For more information www.silicontent.com© 2019 Silicon Content Technology Co., Ltd.
All Rights Reserved
SCT63140
3.3V LDO
The SCT63140 has an integrated low-dropout voltage regulator which powered from VDD and supply regulated
3.3V voltage on V3V pin. The output current capability is 100mA. This LDO can be used to bias the supply voltage
of MCU directly.
It is recommended to connect a decoupling ceramic capacitor of 1uF to 10uF to the V3V pin. Capacitor values
outside of the range may cause instability of the internal linear regulator.
Thermal Shutdown
The SCT63140 protects the device from the damage during excessive heat and power dissipation condition.
Once the junction temperature exceeds 155C, the thermal sensing circuit stops two LDOs and full bridge of 4MOSFETs' working. When the junction temperature falls below 120C, then the device restarts.
CONFIDEN TIAL P relimi anry D atashe et
For more information www.silicontent.com© 2019 Silicon Content Technology Co., Ltd. All Rights Reserved 9
SCT63140
APPLICATION INFORMATION
Typical Application
VIN=4.2V~15V
4
C6
10uF
C5
0.1uF 5
VIN
PVIN1
GND
PGND
PVIN2
BST1
7
5V
C7
2.2uF
6
3.3V
C8
2.2uF
SW1
VDD
C2
22uF
3
C3
0.1uF
C4
22uF
11
C10
0.1uF
R4
C12
10
V3P3
SW2
9
8
R3
C11
EN
15
ISNS
PWM1
14
R1
100K
C1
0.1uF
C9
0.1uF
12
PWM2
2
SCT63140
BST2
PWM1
1
13
PWM2
R2
100K
CONFIDEN TIAL P relimi nary D atashe et
Figure 10. Same Input to VIN and PVIN
VIN=4.2V~20V
4
C6
10uF
C5
0.1uF 5
PVIN1
VIN
GND
PGND
PVIN2
BST1
7
5V
C7
2.2uF
6
3.3V
C8
2.2uF
VDD
SW1
15
PWM1
14
PWM2
R1
100K
2
C1
0.1uF
C2
22uF
3
C3
0.1uF
C4
22uF
11
C10
0.1uF
R4
C12
10
SCT63140
V3P3
SW2
BST2
12
PVIN=1V~15V
1
9
8
C9
0.1uF
R3
C11
EN
PWM1
ISNS
13
PWM2
R2
100K
Figure 11. Separate Input to VIN and PVIN
10 For more information www.silicontent.com© 2019 Silicon Content Technology Co., Ltd.
All Rights Reserved
SCT63140
Application Waveforms
Figure 12. Power Up
Figure 13. Power Up
CONFIDEN TIAL P relimi anry D atashe et
Figure 14. Power Down
Figure 15. Power Down
Figure 16. Full bridge @Vin=5V, RX=5W
Figure 17. Full bridge @Vin=9V, RX=10W
For more information www.silicontent.com© 2019 Silicon Content Technology Co., Ltd. All Rights Reserved 11
SCT63140
Layout Guideline
Proper PCB layout is a critical for SCT63140’s stable and efficient operation. For better results, follow these
guidelines as below:
1.
2.
3.
4.
5.
Bypass capacitors from PVIN to PGND should put next to PVIN and PGND pin as close as possible
especially for the two small capacitors.
PGND connect to bottom layer by via between capacitors.
Bypass capacitors from VIN to GND should put next to VIN and GND pin as close as possible especially for
the small capacitor.
Bypass capacitor for VDD place next to VDD pin.
Bypass capacitor for V3V place next to V3V pin.
EN
PWM2
ISNS
PWM1
BST1
PVIN1
SW1
PVIN
PGND
SW2
PVIN2
CONFIDEN TIAL P relimi nary D atashe et
VDD
V3V
VIN
GND
BST2
VIN
GND
Figure 18. PCB Layout Example
12 For more information www.silicontent.com© 2019 Silicon Content Technology Co., Ltd.
All Rights Reserved
SCT63140
PACKAGE INFORMATION
FCQFN-15L (3x3) Package Outline Dimensions
Symbol
TOTAL THICKNESS
STAND OFF
MOLD THICKNESS
L/F THICKNESS
LEAD WIDTH
BODY SIZE
X
Y
LEAD PITCH
LEAD LENGTH
PACKAGE EDGE TOLERANCE
MOLD FLATNESS
COPLANARITY
LEAD OFFSET
A
A1
A2
A3
b
b1
D
E
e
e1
e2
L
L1
L2
L3
aaa
ccc
eee
bbb
Min.
0.70
0
CONFIDEN TIAL P relimi anry D atashe et
0.20
0.25
0.30
0.225
1.65
0.90
Dimensions in Millimeters
Nom.
0.75
0.02
0.55
0.203 REF
0.25
0.30
3.00 BSC
3.00 BSC
0.50 BSC
0.775 BSC
0.525 BSC
0.40
0.325
1.75
1.00
0.1
0.1
0.08
0.1
Max.
0.80
0.05
0.30
0.35
0.50
0.425
1.85
1.10
NOTE:
1.
2.
3.
4.
5.
6.
Drawing proposed to be made a JEDEC package outline MO-220 variation.
Drawing not to scale.
All linear dimensions are in millimeters.
Thermal pad shall be soldered on the board.
Dimensions of exposed pad on bottom of package do not include mold flash.
Contact PCB board fabrication for minimum solder mask web tolerances between the pins.
For more information www.silicontent.com© 2019 Silicon Content Technology Co., Ltd. All Rights Reserved 13
SCT63140
TAPE AND REEL INFORMATION
Orderable Device
SCT63140FMAR
Package Type
QFN 3mmx3mm
Pins
15
SPQ
5000
CONFIDEN TIAL P relimi nary D atashe et
14 For more information www.silicontent.com© 2019 Silicon Content Technology Co., Ltd.
All Rights Reserved
SCT63140
RELATED PARTS
PN
DESCRIPTION
SCT63240
COMMENTS
•
•
•
•
•
20W High-Integration, HighEfficiency PMIC for Wireless
Power Transmitter
Integrate a 5V-1A Step-down
DC/DC converter compared with
SC63140.
•
•
•
•
•
•
•
•
VIN=4.2V~20V
4
C6
10uF
7
C8
22uF
L1
5V
C5
0.1uF 5
C7
0.1uF
6
10uH
VIN Input Voltage Range: 4.2V-20V
PVIN Input Voltage Range: 1V-17V
Up to 20W Power Transfer
Integrated High Efficiency Full-Bridge Power Stage
Integrated High Efficiency 5V-1A Step-down DC/DC
Converter
Optimized for EMI
Build in 3.3V-200mA LDO
Provide 2.5V Voltage Reference
Integrated Input Current sense with ±2% accuracy for
FOD and modulation
3.3V and 5V PWM Signal compatible
Input Under-Voltage Lockout
Over current protection
3mm*4mm QFN-19L Package
PVIN1
VIN
GND
PGND
BST3
PVIN2
VDD=5V
8
VDD
C9
1uF
9
3.3V
2
C1
0.1uF
C2
22uF
3
C3
0.1uF
C4
22uF
SW3
BST1
SW1
PVIN=1V~17V
1
13
R2
0ohm
18
17
PWM2
R5
100K
C14
12
V3P3
SW2
BST2
11
10
R1
0ohm
PWM1
R4
SCT63240
C10
1uF
19
C12
0.1uF
EN
PWM1
PWM2
ISNS
VREF
AGND
C11
0.1uF
R3
C13
15
14
16
2.5V
C15
1uF
R6
100K
Figure 19. SCT63240 Typical Application
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee the third
party Intellectual Property rights are not infringed upon when integrating Silicon Content Technology (SCT) products into any
application. SCT will not assume any legal responsibility for any said applications.
15
Silicon Content Technology Co., Ltd.
#1 Floor 2 Building 15, Yard 33 Dijin Road, Haidian District, Beijing 100095
TEL：(8610) 64779806 FAX: (8610) 64779806 www.silicontent.com© Silicon Content Technology
工商网监
湘ICP备2023018690号
