ES8396

ES8396 FEATURES Low Power Stereo Audio CODEC DAC • • System • • • • • • • • • • • • High performance and low power multibit delta-sigma stereo ADC and DAC Two independent I2S/PCM master or slave serial data port Three pairs of analog input Four pairs of analog output 2x0.9W stereo or 1.8W mono class D speaker driver Ground centered headphone driver Mono ear speaker driver 256/384Fs, USB 12/24 MHz, fractional PLL for wide range of system clocks Sophisticated analog input and output routing, mixing and gain Support analog and digital microphone GPIO I2C interface • • DSP • • • • • • • • Flexible digital signal routing and mixing Asynchronous sample rate conversion Six programmable digital filters for PEQ and noise reduction Stereo enhancement Support u/A law Low Power • • ADC • • 24-bit, 8 to 96 kHz sampling frequency 95 dB dynamic range, 95 dB signal to noise ratio, -85 dB THD+N Digital peak limiter (DPL) Pop and click noise suppression 1.8V to 3.3V operation 7 mW playback; 16 mW playback and record APPLICATIONS 24-bit, 8 to 96 kHz sampling frequency 95 dB dynamic range, 95 dB signal to noise ratio, -85 dB THD+N Low noise pre-amplifier Auto level control (ALC) and noise gate Microphone bias • • • MID/Phoblet Smart Phone Digital amplifier ORDERING INFORMATION ES8396 -40°C ~ +85°C QFN-48 1 Everest Semiconductor Confidential ES8396 1. BLOCK DIAGRAM ADCDAT2 DACDAT2 LRCK2 BCLK2 ADCDAT1 DACDAT1 LRCK1 BCLK1 2 IC GPIO2/DMIC_SCL2 GPIO1/DMIC_SCL1 SDA SCL MCLK PLL Clock Mgr 2 GPIO L/R Line Mixer Out L/R Aux Mixer Out L/R Mono Mixer Out I S/PCM 1 Stereo ADC PGA L/R ADC PGA Out 2 I S/PCM 2 DSP ASRC Mixing ADC ALC DAC DPL Programmable Filters PEQ SE u/A Law Stereo DAC L/R DAC Out AINL/AINR MONOP/MONON L/R Line Mixer Out Line Mixer AINL/AINR MONOP/MONON MIC1P/MIC1N MIC2P/MIC2N MICP/MICN D2S Preamp Charge Pump L/R Mono Mixer Out Mono Mixer L/R HP Mixer Out HP Mixer L/R, P/N SPK Mixer Out SPK Mixer Aux Driver MONOUTP/MONOUTN Mono Driver HPLOUT/HPROUT HP Driver SPKLOUTP/SPKLOUTN SPK Driver SPKROUTP/SPKROUTN Analog Reference Power Supply and LDO DCVDD DPVDD DGND AVDD AVDDLDO AGND SPKVDD1 SPKVDD2 SPKLDO SPKGND ADCVRP DACVRP VMID MICBIAS CPVDD CPGND CPTOP CPBOT CPVSSP Revision 5.0 Mic Bias L/R Aux Mixer Out Aux Mixer LOUT1/ROUT1 (LOUT1N) Line Driver 2 March 2018 Everest Semiconductor Confidential ES8396 2. PIN OUT AND DESCRIPTION CPGND CPBOT HPROUT HPLOUT SPKLDO SPKGND SPKLOUTP SPKVDD1 SPKLOUTN SPKROUTN SPKVDD2 SPKROUTP 37 38 39 40 41 42 43 44 45 46 47 48 GPIO1 DACDAT1 ADCDAT1 BCLK1 LRCK1 SDA SCL DPVDD DGND DCVDD MCLK GPIO2 1 2 3 4 5 6 7 8 9 10 11 12 ES8396 QFN 48 36 35 34 33 32 31 30 29 28 27 26 25 CPVSSP CPTOP CPVDD DACVRP MONOUTN MONOUTP AVDDLDO AVDD AGND VMID ADCVRP MICN 24 23 22 21 20 19 18 17 16 15 14 13 MICP AINL AINR MONON MONOP MICBIAS LOUT ROUT ADCDAT2 DACDAT2 LRCK2 BCLK2 Name Type MCLK SDA SCL GPIO1 GPIO2 DI DIO DI DIO DIO Master clock I2C data I2C clock GPIO (digital mic clock, ADC LRCK, etc) GPIO (digital mic clock, ADC LRCK, etc) ADCDAT1/AD0 DACDAT1 LRCK1 BCLK1 ADCDAT2 DACDAT2 LRCK2 BCLK2 DIO DI DIO DIO DIO DI DIO DIO I2S/PCM serial data out; Also used as I2C address I2S/PCM serial data in I2S/PCM left and right clock I2S/PCM bit clock I2S/PCM serial data out I2S/PCM serial data in I2S/PCM left and right clock I2S/PCM bit clock AINL/JD1 AINR/JD2 MONOP MONON MICP MICN/DMIC_SDA AI AI AI AI AI AI Left analog line input or jack detect 1 Right analog line input or jack detect 2 Mono positive input or left analog line input Mono negative input or right analog line input Mic positive input or left analog line input Mic negative input or right analog line input or digital mic data Revision 5.0 Description 3 March 2018 Everest Semiconductor LOUT ROUT/LOUTN MONOUTP MONOUTN HPLOUT HPROUT SPKLOUTP SPKLOUTN SPKROUTP SPKROUTN AO AO AO AO AO AO AO AO AO AO Left line out Right line out or negative left line out Mono positive output Mono negative output Left headphone out Right headphone out Positive left speaker out Negative left speaker out Positive right speaker out Negative right speaker out AO Mic bias ADCVRP DACVRP VMID ADC reference filtering DAC reference filtering Common mode filtering DCVDD DPVDD DGND AVDD AVDDLDO AGND SPKVDD1 SPKVDD2 SPKLDO SPKGND Digital core power supply Digital IO power supply Digital ground Analog power supply Analog LDO power supply Analog ground Speaker driver power supply Speaker driver power supply Speaker driver LDO power supply Speaker driver ground Revision 5.0 ES8396 Charge pump power supply Charge pump ground Charge pump capacitor top Charge pump capacitor bottom Charge pump filtering CPVDD CPGND CPTOP CPBOT CPVSSP MICBIAS Confidential 4 March 2018 Everest Semiconductor Confidential ES8396 3. TYPICAL APPLICATION CIRCUIT SPKR_P 8OHMRSPEAKER SPK_GND AGND DGND SPKR_N SPKL_N 8OHMLSPEAKER SPKL_P HP_L HP_R VP_DUT 5 4 3 2 6 1 VSPK_DUT(+2.5V - 4.3V) 10K 10uF 0.1uF 10uF 0.1uF VP_DUT I2CA0 SPK_GND HPDETECT 10uF 1 I2C_SDA I2S1_ALRCK_GPIO I2S1_DACDAT I2S1_ADCDAT I2S1_BCLK I2S1_LRCK I2C_SCL VP_DUT(+1.8V- +3.3V) 10uF 0 I2CA0 0.1uF DGND 10uF 1 2 3 4 5 6 7 8 9 10 11 12 0 48 47 46 45 44 43 42 41 40 39 38 37 AGND AGND 33 ADCLRCK/GPIO DACDAT1 ADCDAT1 BCLK1 LRCK1 SDA SCL DPVDD DGND DCVDD MCLK ADCLRCK2/GPIO CPVSSP CPTOP CPVDD DACVRP MONOOUTN MONOOUTP AVDDLDO AVDD AGND VMID ADCVRP MICN ES8396 0.01uF 0.01uF MOUT_P AGND AGND VCP_DUT(+1.8V) 10uF AGND 0.1uF 10uF 0.1uF VA_DUT(+3.3V) AGND AGND 0.1uF 0.1uF 10uF 10uF 10uF 0.1uF AGND AGND 13 14 15 16 17 18 19 20 21 22 23 24 DGND 33 10uF 0.1uF 36 35 34 33 32 31 30 29 28 27 26 25 MOUT_N Receiver earpiece 10uF 0.1uF BCLK2 LRCK2 DACDAT2 ADCDAT2 ROUT LOUT MICBIAS MONOP MONON AINR AINL MICP 0.1uF 1 VD_DUT(+1.8V- +3.3V) MCLK I2S2_ALRCK 49 SPK_GND THERMAL 10K Headphone 0.1uF SPK_GND SPKROUTP SPKVDD2 SPKROUTN SPKLOUTN SPKVDD1 SPKLOUTP SPKGND SPKLDO HPLOUT HPROUT CPBOT CPGND VP_DUT 10K 10K 4.7uF I2S2_SCLK I2S2_LRCK I2S2_DACDAT I2S2_ADCDAT 0.1uF AGND 4.7uF ROUT_N 4.7uF 10K MONOIN_P 4.7uF MONOIN_N 4.7uF AIN_R 4.7uF AIN_L 4.7uF MICBIAS 10uF AGND 0.1uF 2.2K 4.7uF 4.7uF MICP AGND 10K MICROPHONE 2.2K MICN LOUT_P AGND Revision 5.0 5 March 2018 Everest Semiconductor Confidential ES8396 4. CLOCK MODES AND SAMPLING FREQUENCIES The device supports three types of clocking: standard audio clocks (256Fs, 384Fs, 512Fs, etc), USB clocks (12/24 MHz), and an on-chip 22-bit fractional PLL clock. According to the serial audio data sampling frequency (Fs), the device can work in two speed modes: single speed mode or double speed mode. In single speed mode, Fs normally ranges from 8 kHz to 48 kHz, and in double speed mode, Fs normally range from 64 kHz to 96 kHz. The device can work either in master clock mode or slave clock mode. In slave mode, LRCK and SCLK are supplied externally, and LRCK and SCLK must be synchronously derived from the system clock with specific rates. In master mode, LRCK and SCLK are derived internally from device master clock. 5. MICRO-CONTROLLER CONFIGURATION INTERFACE The device supports standard I2C micro-controller configuration interface. External microcontroller can completely configure the device through writing to internal configuration registers. I2C interface is a bi-directional serial bus that uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. The timing diagram for data transfer of this interface is given in Figure 1. Data are transmitted synchronously to SCL clock on the SDA line on a byte-by-byte basis. Each bit in a byte is sampled during SCL high with MSB bit being transmitted firstly. Each transferred byte is followed by an acknowledge bit from receiver to pull the SDA low. The transfer rate of this interface can be up to 100 kbps. Figure 1 Data Transfer for I2C Interface A master controller initiates the transmission by sending a “start” signal, which is defined as a high-to-low transition at SDA while SCL is high. The first byte transferred is the slave address. It is a seven-bit chip address followed by a RW bit. The chip address must be 001000x, where x equals AD0. The RW bit indicates the slave data transfer direction. Once an acknowledge bit is received, the data transfer starts to proceed on a byte-by-byte basis in the direction specified by the RW bit. The master can terminate the communication by generating a “stop” signal, which is defined as a low-to-high transition at SDA while SCL is high. Revision 5.0 6 March 2018 Everest Semiconductor Confidential ES8396 In I2C interface mode, the registers can be written and read. The formats of “write” and “read” instructions are shown in Table 1 and Table 2. Please note that, to read data from a register, you must set R/W bit to 0 to access the register address and then set R/W to 1 to read data from the register. There are no acknowledge bit after data to be written or read, this is the only difference from the I2C protocol. Table 1 Write Data to Register in I2C Interface Mode Chip Address 001000 AD0 R/W 0 Register Address RAM ACK ACK Data to be written DATA Table 2 Read Data from Register in I2C Interface Mode Chip Address 001000 Chip Address 001000 AD0 AD0 R/W 0 R/W 1 Register Address RAM Data to be read Data ACK ACK 6. DIGITAL AUDIO INTERFACE The device provides many formats of serial audio data interface to the input of the DAC or output from the ADC through LRCK, BCLK (SCLK) and DACDAT/ADCDAT pins. These formats are I2S, left justified, right justified, DSP/PCM and TDM mode. DAC input DACDAT is sampled by the device on the rising edge of SCLK. ADC data is out at ADCDAT on the falling edge of SCLK. The relationship of SDATA (DACDAT/ADCDAT), SCLK and LRCK with these formats are shown through Figure 2 to Figure 6. 1 SCLK SDATA 1 2 1 SCLK 3 n-2 n-1 MSB n 1 LSB MSB 2 3 n-2 n-1 n LSB SCLK LEFT CHANNEL LRCK RIGHT CHANNEL Figure 2 I2S Serial Audio Data Format Up To 24-bit SDATA 1 2 3 n-2 n-1 MSB n 1 LSB MSB 2 3 n-2 n-1 n LSB SCLK LRCK RIGHT CHANNEL LEFT CHANNEL Figure 3 Left Justified Serial Audio Data Format Up To 24-bit Revision 5.0 7 March 2018 Everest Semiconductor SDATA Confidential 1 2 n-2 n-1 3 MSB ES8396 n 1 LSB MSB 2 3 n-2 n-1 n LSB SCLK LRCK RIGHT CHANNEL LEFT CHANNEL Figure 4 Right Justified Serial Audio Data Format Up To 24-bit Figure 5 DSP/PCM Mode A Figure 6 DSP/PCM Mode B Revision 5.0 8 March 2018 Everest Semiconductor Confidential ES8396 7. ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Continuous operation at or beyond these conditions may permanently damage the device. PARAMETER Analog Supply Voltage Level Digital Supply Voltage Level Input Voltage Range Operating Temperature Range Storage Temperature MIN -0.3V -0.3V DGND-0.3V -40°C -65°C MAX +4.5V +5.0V DVDD+0.3V +85°C +150°C RECOMMENDED OPERATING CONDITIONS PARAMETER Analog Supply Voltage Level Analog Supply Voltage Level – Class D Digital Supply Voltage Level – DCVDD Digital Supply Voltage Level – DPVDD (recommend to be the same as DCVDD) MIN 2.0 2.5 1.6 1.6 TYP 3.3 4.0 3.3 3.3 MAX 3.6 4.3 3.6 3.6 UNIT V V V V ADC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS Test conditions are as the following unless otherwise specify: AVDD=3.3V, DCVDD=1.8V, AGND=0V, DGND=0V, Ambient temperature=25°C, Fs=48 KHz, 96 KHz or 192 KHz, MCLK/LRCK=256. PARAMETER ADC Performance Signal to Noise ratio (A-weigh) THD+N Channel Separation (1KHz) Interchannel Gain Mismatch Gain Error Filter Frequency Response – Single Speed Passband Stopband Passband Ripple Stopband Attenuation Filter Frequency Response – Double Speed Passband Stopband Passband Ripple Stopband Attenuation Analog Input Full Scale Input Level Input Impedance Revision 5.0 MIN TYP MAX UNIT 85 -88 80 95 -85 85 0.1 98 -75 90 dB dB dB dB % 0 0.5465 0.4535 ±0.05 50 0 0.5833 0.4167 ±0.005 50 AVDD/3.3 20 9 ±5 Fs Fs dB dB Fs Fs dB dB Vrms KΩ March 2018 Everest Semiconductor Confidential ES8396 DAC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS Test conditions are as the following unless otherwise specify: AVDD=3.3V, DCVDD=1.8V, AGND=0V, DGND=0V, Ambient temperature=25°C, Fs=48 KHz, 96 KHz or 192 KHz, MCLK/LRCK=256. PARAMETER MIN DAC Performance Signal to Noise ratio (A-weigh) 83 THD+N -85 Channel Separation (1KHz) 80 Interchannel Gain Mismatch Filter Frequency Response – Single Speed Passband 0 Stopband 0.5465 Passband Ripple Stopband Attenuation 40 Filter Frequency Response – Double Speed Passband 0 Stopband 0.5833 Passband Ripple Stopband Attenuation 40 De-emphasis Error at 1 KHz (Single Speed Mode Only) Fs = 32KHz Fs = 44.1KHz Fs = 48KHz Analog Output Full Scale Output Level TYP MAX UNIT 96 -83 85 0.05 98 -75 90 dB dB dB dB 0.4535 Fs Fs dB dB ±0.05 0.4167 ±0.005 0.002 0.013 0.0009 AVDD/3.3 Fs Fs dB dB dB Vrms POWER CONSUMPTION CHARACTERISTICS PARAMETER Normal Operation Mode DVDD=1.8V, AVDD=1.8V: Play back Play back and record DVDD=3.3V, AVDD=3.3V: Play back Play back and record Power Down Mode DVDD=1.8V, AVDD=1.8V DVDD=3.3V, AVDD=3.3V MIN TYP MAX UNIT mW 7 16 31 59 TBD TBD mW SERIAL AUDIO PORT SWITCHING SPECIFICATIONS PARAMETER MCLK frequency MCLK duty cycle LRCK frequency Revision 5.0 Symbol MIN 40 10 MAX 51.2 60 200 UNIT MHz % KHz March 2018 Everest Semiconductor Confidential LRCK duty cycle SCLK frequency SCLK pulse width low SCLK Pulse width high SCLK falling to LRCK edge SCLK falling to SDOUT valid SDIN valid to SCLK rising setup time SCLK rising to SDIN hold time ES8396 40 TSCLKL TSCLKH TSLR TSDO TSDIS TSDIH 15 15 –10 0 10 10 60 26 10 % MHz ns ns ns ns ns ns Figure 8 Serial Audio Port Timing I2C SWITCHING SPECIFICATIONS PARAMETER SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of SCL Fall Time SCL Revision 5.0 Symbol FSCL TTWID TTWSTH TTWCL TTWCH TTWSTS TTWDH TTWDS TTWR TTWF 11 MIN 1.3 0.6 1.3 0.4 0.6 100 MAX 400 900 300 300 UNIT KHz us us us us us ns ns ns ns March 2018 Everest Semiconductor Confidential ES8396 SDA TTWSTS TTWSTH TTWCL SCL TTWDH TTWID TTWDS TTWCH S TTWF TTWR P S Figure 10 I2C Timing Revision 5.0 12 March 2018 Everest Semiconductor Confidential ES8396 8. PACKAGE 9. CORPORATE INFORMATION Everest Semiconductor Co., Ltd. 苏州工业园区金鸡湖大道 1355 号国际科技园, 邮编 215021 Email: info@everest-semi.com Revision 5.0 13 March 2018