GD32F450IKH6

GD32F450xx GigaDevice Semiconductor Inc. GD32F450xx ARM® Cortex®-M4 32-bit MCU Datasheet 0 / 66 GD32F450xx Table of Contents List of Figures ............................................................................................................................. 3 List of Tables ............................................................................................................................... 4 1 Introduction ...................................................................................................................... 6 2 Device overview ............................................................................................................... 7 2.1 Device information .............................................................................................................................. 7 2.2 Block diagram ...................................................................................................................................... 8 2.3 Pinouts and pin assignment .............................................................................................................. 9 2.4 Memory map ...................................................................................................................................... 12 2.5 Clock tree ........................................................................................................................................... 15 2.6 Pin definitions .................................................................................................................................... 16 Functional description .................................................................................................. 36 3 4 3.1 ARM® Cortex®-M4 core .................................................................................................................... 36 3.2 On-chip memory................................................................................................................................ 36 3.3 Clock, reset and supply management ........................................................................................... 37 3.4 Boot modes ........................................................................................................................................ 38 3.5 Power saving modes ........................................................................................................................ 38 3.6 Analog to digital converter (ADC) ................................................................................................... 39 3.7 Digital to analog converter (DAC) ................................................................................................... 39 3.8 DMA .................................................................................................................................................... 40 3.9 General-purpose inputs/outputs (GPIOs) ...................................................................................... 40 3.10 Timers and PWM generation........................................................................................................... 41 3.11 Real time clock (RTC) and backup registers ................................................................................ 42 3.12 Inter-integrated circuit (I2C) ............................................................................................................. 42 3.13 Serial peripheral interface (SPI)...................................................................................................... 43 3.14 Universal synchronous/asynchronous receiver transmitter (USART/UART) ........................... 43 3.15 Inter-IC sound (I2S) .......................................................................................................................... 43 3.16 Universal serial bus on-the-go full-speed (USB OTG FS) .......................................................... 44 3.17 Universal serial bus on-the-go high-speed (USB OTG HS) ....................................................... 44 3.18 Controller area network (CAN) ........................................................................................................ 44 3.19 Ethernet MAC interface .................................................................................................................... 45 3.20 External memory controller (EXMC) .............................................................................................. 45 3.21 Secure digital input and output card interface (SDIO) ................................................................. 45 3.22 TFT LCD interface (TLI) ................................................................................................................... 46 3.23 Image processing accelerator (IPA) ............................................................................................... 46 3.24 Digital camera interface (DCI) ......................................................................................................... 46 3.25 Debug mode ...................................................................................................................................... 47 3.26 Package and operation temperature.............................................................................................. 47 Electrical characteristics .............................................................................................. 48 1 / 66 GD32F450xx 4.1 Absolute maximum ratings .............................................................................................................. 48 4.2 Recommended DC characteristics ................................................................................................. 48 4.3 Power consumption .......................................................................................................................... 49 4.4 EMC characteristics .......................................................................................................................... 50 4.5 Power supply supervisor characteristics ....................................................................................... 51 4.6 Electrical sensitivity........................................................................................................................... 51 4.7 External clock characteristics .......................................................................................................... 52 4.8 Internal clock characteristics ........................................................................................................... 53 4.9 PLL characteristics ........................................................................................................................... 54 4.10 Memory characteristics .................................................................................................................... 55 4.11 GPIO characteristics......................................................................................................................... 56 4.12 ADC characteristics .......................................................................................................................... 57 4.13 DAC characteristics .......................................................................................................................... 59 4.14 SPI characteristics ............................................................................................................................ 60 4.15 I2C characteristics ............................................................................................................................ 60 4.16 USART characteristics ..................................................................................................................... 60 Package information ..................................................................................................... 61 5 5.1 LQFP package outline dimensions ................................................................................................ 61 5.2 BGA package outline dimensions .................................................................................................. 63 6 Ordering information ..................................................................................................... 64 7 Revision history ............................................................................................................. 65 2 / 66 GD32F450xx List of Figures Figure 1. GD32F450xx block diagram ...................................................................................................................... 8 Figure 2. GD32F450Ix BGA176 pinouts .................................................................................................................. 9 Figure 3. GD32F450Zx LQFP144 pinouts ............................................................................................................. 10 Figure 4. GD32F450Vx LQFP100 pinouts ............................................................................................................. 11 Figure 5. GD32F450xx memory map ..................................................................................................................... 12 Figure 6. GD32F450xx clock tree............................................................................................................................ 15 Figure 7. LQFP package outline .............................................................................................................................. 61 Figure 8. BGA package outline ................................................................................................................................ 63 3 / 66 GD32F450xx List of Tables Table 1. GD32F450xx devices features and peripheral list................................................................................... 7 Table 2. GD32F450xx pin definitions ...................................................................................................................... 16 Table 3. Port A alternate functions summary ......................................................................................................... 27 Table 4. Port B alternate functions summary ......................................................................................................... 28 Table 5. Port C alternate functions summary......................................................................................................... 29 Table 6. Port D alternate functions summary......................................................................................................... 30 Table 7. Port E alternate functions summary ......................................................................................................... 31 Table 8. Port F alternate functions summary ......................................................................................................... 32 Table 9. Port G alternate functions summary ........................................................................................................ 33 Table 10. Port H alternate functions summary ...................................................................................................... 34 Table 11. Port I alternate functions summary ........................................................................................................ 35 Table 12. Absolute maximum ratings ...................................................................................................................... 48 Table 13. DC operating conditions .......................................................................................................................... 48 Table 14. Power consumption characteristics ....................................................................................................... 49 Table 15. EMS characteristics ................................................................................................................................. 50 Table 16. EMI characteristics................................................................................................................................... 50 Table 17. Power supply supervisor characteristics .............................................................................................. 51 Table 18. ESD characteristics.................................................................................................................................. 51 Table 19. Static latch-up characteristics ................................................................................................................ 51 Table 20. High speed external clock (HXTAL) generated from a crystal/ceramic characteristics ................. 52 Table 21. Low speed external clock (LXTAL) generated from a crystal/ceramic characteristics ................... 52 Table 22. High speed internal clock (IRC16M) characteristics ........................................................................... 53 Table 23. High speed internal clock (IRC48M) characteristics ........................................................................... 53 Table 24. Low speed internal clock (IRC32K) characteristics ............................................................................. 54 Table 25. PLL characteristics ................................................................................................................................... 54 Table 26. PLL spread spectrum clock generation (SSCG) characteristics ....................................................... 54 Table 27. Flash memory characteristics ................................................................................................................. 55 Table 28. I/O port characteristics ............................................................................................................................. 56 Table 29. ADC characteristics .................................................................................................................................. 57 Table 30. ADC RAIN max for fADC=40MHz ................................................................................................................. 57 Table 31. ADC dynamic accuracy at fADC = 30 MHz ............................................................................................. 58 Table 32. ADC dynamic accuracy at fADC = 30 MHz ............................................................................................. 58 Table 33. ADC dynamic accuracy at fADC = 36 MHz ............................................................................................. 58 Table 34. ADC dynamic accuracy at fADC = 40 MHz ............................................................................................. 58 Table 35. ADC static accuracy at fADC = 15 MHz .................................................................................................. 58 Table 36. DAC characteristics ................................................................................................................................. 59 Table 37. SPI characteristics .................................................................................................................................... 60 Table 38. I2C characteristics .................................................................................................................................... 60 Table 39. USART characteristics ............................................................................................................................ 60 Table 40. LQFP package dimensions ..................................................................................................................... 62 Table 41. BGA package dimensions ....................................................................................................................... 63 4 / 66 GD32F450xx Table 42. Part ordering code for GD32F450xx devices ....................................................................................... 64 Table 43. Revision history......................................................................................................................................... 65 5 / 66 GD32F450xx 1 Introduction The GD32F450xx device belongs to the stretch performance line of GD32 MCU Family. It is a new 32-bit general-purpose microcontroller based on the ARM® Cortex®-M4 RISC core with best cost-performance ratio in terms of enhanced processing capacity, reduced power consumption and peripheral set. The Cortex®-M4 core features a Floating Point Unit (FPU) that accelerates single precision floating point math operations and supports all ARM® single precision instructions and data types. It implements a full set of DSP instructions to address digital signal control markets that demand an efficient, easy-to-use blend of control and signal processing capabilities. It also provides a Memory Protection Unit (MPU) and powerful trace technology for enhanced application security and advanced debug support. The GD32F450xx device incorporates the ARM® Cortex®-M4 32-bit processor core operating at 200 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up to 3072 KB on-chip Flash memory and 512 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up to three 12-bit 2.6M SPS ADCs, two 12-bit DACs, up to eight general-purpose 16-bit timers, two 16-bit PWM advanced-control timers , two 32-bit general-purpose timers, and two 16-bit basic timers, as well as standard and advanced communication interfaces: up to six SPIs, three I2Cs, four USARTs and four UARTs, two I2Ss, two CANs, a SDIO, USB device/host/OTG FS and HS, and an Ethernet MAC. Additional peripherals as Digital camera interface (DCI), EXMC interface with SDRAM extension support, TFT-LCD Interface (TLI) and Image Processing Accelerator (IPA) are included. The device operates from a 2.6 to 3.6V power supply and available in –40 to +85 °C temperature range. Three power saving modes provide the flexibility for maximum optimization of power consumption, an especially important consideration in low power applications. The above features make GD32F450xx devices suitable for a wide range of interconnection and advanced applications, especially in areas such as industrial control, consumer and handheld equipment, embedded modules, human machine interface, security and alarm systems, graphic display, automotive navigation, drone, IoT and so on. 6 / 66 GD32F450xx 2 Device overview 2.1 Device information Table 1. GD32F450xx devices features and peripheral list GD32F450xx Flash Part Number VE VG VI VK ZE ZG ZI ZK IG II IK Code Area (KB) 512 512 256 512 512 512 256 512 512 256 512 Data Area (KB) 0 512 1792 2560 0 512 1792 2560 512 1792 2560 Total (KB) 512 1024 2048 3072 512 1024 2048 3072 1024 2048 3072 256 256 512 256 256 256 512 256 256 512 256 16-bit GPTM 8 8 8 8 8 8 8 8 8 8 8 32-bit GPTM 2 2 2 2 2 2 2 2 2 2 2 Adv. 16-bit TM 2 2 2 2 2 2 2 2 2 2 2 Basic TM 2 2 2 2 2 2 2 2 2 2 2 SysTick 1 1 1 1 1 1 1 1 1 1 1 Watchdog 2 2 2 2 2 2 2 2 2 2 2 RTC 1 1 1 1 1 1 1 1 1 1 1 USART+UART 4+4 4+4 4+4 4+4 4+4 4+4 4+4 4+4 4+4 4+4 4+4 I2C 3 3 3 3 3 3 3 3 3 3 3 SPI/I2S 5/2 5/2 5/2 5/2 6/2 6/2 6/2 6/2 6/2 6/2 6/2 SDIO 1 1 1 1 1 1 1 1 1 1 1 CAN 2.0B 2 2 2 2 2 2 2 2 2 2 2 Connectivity Timers SRAM (KB) USB OTG FS+HS FS+HS FS+HS FS+HS FS+HS FS+HS FS+HS FS+HS FS+HS FS+HS FS+HS Ethernet MAC 1 1 1 1 1 1 1 1 1 1 1 TFT-LCD 1 1 1 1 1 1 1 1 1 1 1 Digital Camera 1 1 1 1 1 1 1 1 1 1 1 GPIO 82 82 82 82 114 114 114 114 140 140 140 EXMC/SDRAM 1/0 1/0 1/0 1/0 1/1 1/1 1/1 1/1 1/1 1/1 1/1 ADC Unit (CHs) 3(16) 3(16) 3(16) 3(16) 3(24) 3(24) 3(24) 3(24) 3(24) 3(24) 3(24) DAC 2 2 2 2 2 2 2 2 2 2 2 Package LQFP100 LQFP144 BGA176 7 / 66 GD32F450xx Block diagram Figure 1. GD32F450xx block diagram Powered By LDO (1.2V) Flash Memory master DBUS master SBUS SW/JTA G IBUS TPIU master slave FMC Powered By V DDA slave M master P master M master P master DMA0 DMA1 ENET master TLI master AHB Interconnect Matrix (Fmax=200MHz) ARM Cortex-M4 Processor Fmax: 200MHz slave TCMSRAM slave SRAM0 slave SRAM1 slave SRAM2 slave ADDSRAM slave EXMC DAC BKP SRAM CRC LVD PLLs IRC16M IRC32K GPIO RCU slave AHB1 Per ipheral s USBHS master IPA master TRNG DCI USBFS slave AHB2 Per ipheral s SDIO SPI5 SPI4 SPI3 SPI0 SYS CFG CTC DAC TIMER10 IVREF CAN1 TIMER9 TIMER13 CAN0 TIMER8 TIMER12 UART7 TIMER7 TIMER11 UART6 TIMER0 TIMER6 UART4 USART5 TIMER5 UART3 USART0 TIMER4 USART2 TIMER3 TIMER2 TIMER1 WWDG T SAR ADC Powered By V DDA POR/ PDR USART1 I2C2 I2C1 I2C0 I2S2_add SPI2/I2S2 SPI1/I2S1 LDO FWDG T HXTAL APB1 (Fmax=50MHz) ADC0~2 APB2 (Fmax=100MHz) EXTI slave AHB Interconnect Matrix (Fmax=200MHz) slave 2.2 I2S1_add PMU Powered By V DD LXTAL RTC Powered By V B AT 8 / 66 GD32F450xx 2.3 Pinouts and pin assignment Figure 2. GD32F450Ix BGA176 pinouts 1 2 3 4 5 6 7 8 9 10 11 12 A PE3 PE2 PE1 PE0 PB8 PB5 PG14 PG13 PB4 PB3 PD7 PC12 PA15 PA14 PA13 B PE4 PE5 PE6 PB9 PB7 PB6 PG15 PG12 PG11 PG10 PD6 PD0 PC11 PC10 C VBAT PI7 PI6 PI5 VDD PDR_ON VDD VDD VDD PG9 PD5 PD1 PI3 PI2 PA11 D PC13 PI8 PI9 PI4 VSS BOOT0 VSS VSS VSS PD4 PD3 PD2 PH15 PI1 PA10 E PC14 PF0 PI10 PI11 PH13 PH14 PI0 PA9 F PC15 VSS VDD PH2 VSS VSS VSS VSS VSS VSS NC PC9 PA8 G PH0 VSS VDD PH3 VSS VSS VSS VSS VSS VSS VDD PC8 PC7 H PH1 PF2 PF1 PH4 VSS VSS VSS VSS VSS VSS VDD PG8 PC6 J NRST PF3 PF4 PH5 VSS VSS VSS VSS VSS VDD VDD PG7 PG6 K PF7 PF6 PF5 VDD VSS VSS VSS VSS VSS PH12 PG5 PG4 PG3 L PF10 PF9 PF8 NC PH11 PH10 PD15 PG2 M VSSA PC0 PC1 PC2 PC3 PB2 PG1 VSS VSS NC PH6 PH8 PH9 N VREF- PA1 PA0 PA4 PC4 PF13 PG0 VDD VDD VDD PE13 PH7 PD12 PD11 PD10 P VREF+ PA2 PA6 PA5 PC5 PF12 PF15 PE8 PE9 PE11 PE14 PB12 PB13 PD9 PD8 R VDDA PA3 PA7 PB1 PB0 PF11 PF14 PE7 PE10 PE12 PE15 PB10 PB11 PB14 PB15 GigaDevice GD32F450Ix BGA176 13 14 15 PA12 PD14 PD13 9 / 66 GD32F450xx Figure 3. GD32F450Zx LQFP144 pinouts PA14 PA15 PC10 PC11 PC12 PD0 PD1 PD2 PD3 PD4 PD5 VSS VDD PD6 PD7 PG9 PG11 PG10 PG12 PG13 PG14 VDD VSS PG15 PB4 PB3 PB5 PB6 PB7 BOOT0 PB8 PB9 PE0 PE1 VDD PDR_ON 144143142141140139138137136135134133 132131130129128127126125124123122121120 119118117116115114113112111110109 PE2 1 108 PE3 PE4 2 107 VSS 3 106 NC PE5 PE6 4 105 PA13 5 104 PA12 VBAT 6 103 PA11 PC13-TAMPER-RTC PC14-OSC32_IN 7 102 PA10 8 101 PA9 PC15-OSC32_OUT 9 100 PA8 PF0 10 99 PC9 PC8 VDD PF1 11 98 PF2 12 97 PC7 PF3 PF4 13 96 PC6 14 95 VDD PF5 15 94 VSS VSS 16 93 PG8 92 PG7 91 PG6 90 PG5 89 PG4 88 PG3 VDD 17 PF6 18 PF7 19 PF8 20 PF9 21 PF10 22 87 PG2 PH0-OSC_IN 23 86 PD15 PH0-OSC_OUT 24 85 PD14 NRST 25 84 VDD PC0 26 83 VSS PC1 27 82 PD13 PC2 28 81 PD12 PC3 VDD 29 80 PD11 30 79 PD10 VSSA VREF+ 31 78 PD9 32 77 PD8 VDDA 33 76 PB15 PA0_WKUP 34 75 PB14 PA1 35 74 PB13 PA2 36 73 PB12 GigaDevice GD32F450Zx LQFP144 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 NC VDD PB11 PB10 PE15 PE13 PE14 PE12 PE11 VDD PE10 VSS PE9 PE7 PE8 PG1 PG0 PF15 PF13 PF14 VSS VDD PF12 PB2 PF11 PB1 PC5 PB0 PA7 PC4 PA6 PA5 PA4 VSS VDD PA3 10 / 66 GD32F450xx Figure 4. GD32F450Vx LQFP100 pinouts PA14 PA15 PC10 PC11 PC12 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PB4 PB3 PB5 PB6 PB7 BOOT0 PB8 PB9 PE0 PE1 VSS VDD PE2 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 PE3 PE4 2 74 VSS 3 73 NC PE5 PE6 4 72 PA13 5 71 PA12 VBAT 6 PC13-TAMPER-RTC PC14-OSC32_IN 7 70 69 PA10 8 68 PA9 PC15-OSC32_OUT 9 67 PA8 VSS 10 66 PC9 65 PC8 64 PC7 63 PC6 VDD PA11 VDD 11 PH0-OSC_IN 12 PH1-OSC_OUT 13 NRST PC0 14 62 PD15 15 61 PD14 PC1 16 60 PD13 PC2 PC3 17 59 PD12 18 58 PD11 VDD 19 57 PD10 VSSA VREF+ 20 56 PD9 21 55 PD8 VDDA 22 54 PB15 PA0-WKUP 23 53 PB14 PA1 24 52 PB13 PA2 25 51 PB12 GigaDevice GD32F450Vx LQFP100 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VDD PB11 NC PB10 PE15 PE14 PE13 PE11 PE12 PE10 PE9 PE8 PB2 PE7 PB1 PC5 PB0 PA7 PC4 PA6 PA5 PA4 VSS VDD PA3 11 / 66 GD32F450xx 2.4 Memory map Figure 5. GD32F450xx memory map Pre-defined Regions Bus Address Peripherals 0xC000 0000 - 0xDFFF FFFF EXMC - SDRAM 0xA000 1000 - 0xBFFF FFFF Reserved AHB 0xA000 0000 - 0xA000 0FFF EXMC - SWREG matrix 0x9000 0000 - 0x9FFF FFFF EXMC - PC CARD 0x7000 0000 - 0x8FFF FFFF EXMC - NAND 0x6000 0000 - 0x6FFF FFFF EXMC - NOR/PSRAM/SRAM 0x5006 0C00 - 0x5FFF FFFF Reserved 0x5006 0800 - 0x5006 0BFF TRNG 0x5005 0400 - 0x5006 07FF Reserved 0x5005 0000 - 0x5005 03FF DCI 0x5004 0000 - 0x5004 FFFF Reserved 0x5000 0000 - 0x5003 FFFF USBFS 0x4008 0000 - 0x4FFF FFFF Reserved 0x4004 0000 - 0x4007 FFFF USBHS 0x4002 BC00 - 0x4003 FFFF Reserved 0x4002 B000 - 0x4002 BBFF IPA 0x4002 A000 - 0x4002 AFFF Reserved 0x4002 8000 - 0x4002 9FFF ENET 0x4002 6800 - 0x4002 7FFF Reserved 0x4002 6400 - 0x4002 67FF DMA1 0x4002 6000 - 0x4002 63FF DMA0 0x4002 5000 - 0x4002 5FFF Reserved 0x4002 4000 - 0x4002 4FFF BKPSRAM 0x4002 3C00 - 0x4002 3FFF FMC 0x4002 3800 - 0x4002 3BFF RCU 0x4002 3400 - 0x4002 37FF Reserved 0x4002 3000 - 0x4002 33FF CRC 0x4002 2400 - 0x4002 2FFF Reserved 0x4002 2000 - 0x4002 23FF GPIOI 0x4002 1C00 - 0x4002 1FFF GPIOH 0x4002 1800 - 0x4002 1BFF GPIOG 0x4002 1400 - 0x4002 17FF GPIOF 0x4002 1000 - 0x4002 13FF GPIOE 0x4002 0C00 - 0x4002 0FFF GPIOD 0x4002 0800 - 0x4002 0BFF GPIOC 0x4002 0400 - 0x4002 07FF GPIOB 0x4002 0000 - 0x4002 03FF GPIOA External Device External RAM AHB2 Peripheral AHB1 12 / 66 GD32F450xx Pre-defined Regions Bus APB2 APB1 Address Peripherals 0x4001 6C00 - 0x4001 FFFF Reserved 0x4001 6800 - 0x4001 6BFF TLI 0x4001 5800 - 0x4001 67FF Reserved 0x4001 5400 - 0x4001 57FF SPI5 0x4001 5000 - 0x4001 53FF SPI4 0x4001 4C00 - 0x4001 4FFF Reserved 0x4001 4800 - 0x4001 4BFF TIMER10 0x4001 4400 - 0x4001 47FF TIMER9 0x4001 4000 - 0x4001 43FF TIMER8 0x4001 3C00 - 0x4001 3FFF EXTI 0x4001 3800 - 0x4001 3BFF SYSCFG 0x4001 3400 - 0x4001 37FF SPI3 0x4001 3000 - 0x4001 33FF SPI0 0x4001 2C00 - 0x4001 2FFF SDIO 0x4001 2400 - 0x4001 2BFF Reserved 0x4001 2000 - 0x4001 23FF ADC 0x4001 1800 - 0x4001 1FFF Reserved 0x4001 1400 - 0x4001 17FF USART5 0x4001 1000 - 0x4001 13FF USART0 0x4001 0800 - 0x4001 0FFF Reserved 0x4001 0400 - 0x4001 07FF TIMER7 0x4001 0000 - 0x4001 03FF TIMER0 0x4000 C800 - 0x4000 FFFF Reserved 0x4000 C400 - 0x4000 C7FF IVREF 0x4000 8000 - 0x4000 C3FF Reserved 0x4000 7C00 - 0x4000 7FFF UART7 0x4000 7800 - 0x4000 7BFF UART6 0x4000 7400 - 0x4000 77FF DAC 0x4000 7000 - 0x4000 73FF PMU 0x4000 6C00 - 0x4000 6FFF CTC 0x4000 6800 - 0x4000 6BFF CAN1 0x4000 6400 - 0x4000 67FF CAN0 0x4000 6000 - 0x4000 63FF Reserved 0x4000 5C00 - 0x4000 5FFF I2C2 0x4000 5800 - 0x4000 5BFF I2C1 0x4000 5400 - 0x4000 57FF I2C0 0x4000 5000 - 0x4000 53FF UART4 0x4000 4C00 - 0x4000 4FFF UART3 0x4000 4800 - 0x4000 4BFF USART2 0x4000 4400 - 0x4000 47FF USART1 13 / 66 GD32F450xx Pre-defined Regions SRAM Code Bus AHB matrix AHB matrix Address Peripherals 0x4000 4000 - 0x4000 43FF I2S2_add 0x4000 3C00 - 0x4000 3FFF SPI2/I2S2 0x4000 3800 - 0x4000 3BFF SPI1/I2S1 0x4000 3400 - 0x4000 37FF I2S1_add 0x4000 3000 - 0x4000 33FF FWDGT 0x4000 2C00 - 0x4000 2FFF WWDGT 0x4000 2800 - 0x4000 2BFF RTC 0x4000 2400 - 0x4000 27FF Reserved 0x4000 2000 - 0x4000 23FF TIMER13 0x4000 1C00 - 0x4000 1FFF TIMER12 0x4000 1800 - 0x4000 1BFF TIMER11 0x4000 1400 - 0x4000 17FF TIMER6 0x4000 1000 - 0x4000 13FF TIMER5 0x4000 0C00 - 0x4000 0FFF TIMER4 0x4000 0800 - 0x4000 0BFF TIMER3 0x4000 0400 - 0x4000 07FF TIMER2 0x4000 0000 - 0x4000 03FF TIMER1 0x2007 0000 - 0x3FFF FFFF Reserved 0x2003 0000 - 0x2006 FFFF SRAM3(256KB) 0x2002 0000 - 0x2002 FFFF SRAM2(64KB) 0x2001 C000 - 0x2001 FFFF SRAM1(16KB) 0x2000 0000 - 0x2001 BFFF SRAM0(112KB) 0x1FFF C010 - 0x1FFF FFFF Reserved 0x1FFF C000 - 0x1FFF C00F Option bytes(Bank 0) 0x1FFF 7A10 - 0x1FFF BFFF Reserved 0x1FFF 7800 - 0x1FFF 7A0F OTP(528B) 0x1FFF 0000 - 0x1FFF 77FF Boot loader(30KB) 0x1FFE C010 - 0x1FFE FFFF Reserved 0x1FFE C000 - 0x1FFE C00F Option bytes(Bank 1) 0x1001 0000 - 0x1FFE BFFF Reserved 0x1000 0000 - 0x1000 FFFF TCMSRAM(64KB) 0x0830 0000 - 0x0FFF FFFF Reserved 0x0800 0000 - 0x082F FFFF Main Flash(3072KB) 0x0000 0000 - 0x07FF FFFF Aliased to the boot device 14 / 66 GD32F450xx 2.5 Clock tree Figure 6. GD32F450xx clock tree CK_HXTAL /2 to /31 11 32.768 KHz LXTAL OSC CK_RTC 01 (to RTC) 10 RTCSRC[1:0] CK_FWDGT 32 KHz IRC32K (to FWDGT) CK_OUT1 00 01 10 11 CKOUT1DIV ÷1,2,3,4,5 CK_SYS CK_PLLI2SR CK_HXTAL CK_PLLP CKOUT1SEL[1:0] HCLK (to AHB bus,CortexM4,SRAM,DMA,peripherals) AHB enable CK_OUT0 00 01 10 11 CKOUT0DIV ÷1,2,3,4,5 CK_IRC16M CK_LXTAL CK_HXTAL CK_CST ÷8 (to Cortex-M4 SysTick) FCLK CK_PLLP (free running clock) APB1 Prescaler ÷1,2,4,8,16 CKOUT0SEL[1:0] SCS[1:0] CK_IRC16M 16 MHz IRC16M 01 CK_SYS 200 MHz max AHB Prescaler ÷1,2...512 CK_AHB APB2 Prescaler ÷1,2,4,8,16 10 Clock Monitor 200 MHz max CK_TIMERx TIMERx enable to TIMER1,2,3,4, 5,6,11,12,13 CK_APB2 PCLK2 to APB2 peripherals 100 MHz max Peripheral enable TIMER0,7,8, 9,10 CK_APB2 x1 x2 or x4 PLLSEL CTC 0 TIMER1,2,3,4,5,6, 11,12,13 CK_APB1 x1 x2 or x4 200 MHz max CK_PLLP /PSC PCLK1 to APB1 peripherals Peripheral enable 00 CK_HXTAL 4-32 MHz HXTAL CK_APB1 50 MHz max 200 MHz max CK_TIMERx TIMERx enable to TIMER0,7, 8,9,10 1 VCO /P /Q xN /R PLL CK_CTC 48 MHz IRC48M ADC Prescaler CK_ADCX to ADC0,1,2 40 MHz max CK48MSEL PLL48MSEL 0 VCO I2SSEL /P /Q xN PLLI2S VCO 1 CK48M 0 Peripheral enable 1 to USBFS USBHS TRNG SDIO 1 /R CK_I2Sx 0 Peripheral enable I2S_CKIN to I2S /P /Q xN /R /DIV PLLSAI CK_TLI Peripheral enable ENET_TX_CLK /2 or /20 0 1 Peripheral enable ENET_PHY_SEL 1 ENET_RX_CLK to TLI CK_ENETTX to ENET TX CK_ENETRX 0 EMBPHY Peripheral enable to ENET RX USB HS PHY clock 24Mhz to 60Mhz 0 CK48M 1 CK_USBHS_ULPI Peripheral enable to USBHS ULPI Legend: HXTAL: High speed crystal oscillator LXTAL: Low speed crystal oscillator IRC16M: Internal 16M RC oscillators IRC48M: Internal 48M RC oscillators IRC32K: Internal 32K RC oscillator 15 / 66 GD32F450xx 2.6 Pin definitions I/O(2) Level LQFP100 LQFP144 Pin Name BGA176 Pins Pin Type(1) Table 2. GD32F450xx pin definitions Functions description Default: PE2 PE2 A2 1 1 I/O 5VT Alternate: TRACECLK, SPI3_SCK, ETH_MII_TXD3, EXMC_A23, EVENTOUT Default: PE3 PE3 A1 2 2 I/O 5VT PE4 B1 3 3 I/O 5VT Alternate:TRACED1, SPI3_NSS, EXMC_A20, DCI_D4, TLI_B0, Alternate:TRACED0, EXMC_A19, EVENTOUT Default: PE4 EVENTOUT Default: PE5 PE5 B2 4 4 I/O 5VT Alternate:TRACED2, TIMER8_CH0, SPI3_MISO, EXMC_A21, DCI_D6, TLI_G0, EVENTOUT Default: PE6 PE6 B3 5 5 I/O 5VT Alternate:TRACED3, TIMER8_CH1, SPI3_MOSI, EXMC_A22, DCI_D7, TLI_G1, EVENTOUT VBAT C1 6 6 P - Default: VBAT Default: PI8 PI8 D2 - - I/O 5VT Alternate: EVENTOUT Additional:RTC_TAMP1, RTC_TAMP0, RTC_TS PC13TAMPER- Default: PC13 D1 7 7 I/O 5VT Alternate: EVENTOUT Additional: RTC_TAMP0, RTC_OUT, RTC_TS RTC PC14OSC32IN PC15OSC32OUT Default: PC14 E1 8 8 I/O 5VT Alternate: EVENTOUT Additional: OSC32IN Default: PC15 F1 9 9 I/O 5VT Alternate: EVENTOUT Additional: OSC32OUT Default: PI9 PI9 D3 - - I/O 5VT PI10 E3 - - I/O 5VT PI11 E4 - - I/O 5VT VSS F2 - - P - Default: VSS VDD F3 - - P - Default: VDD PF0 E2 10 - I/O 5VT PF1 H3 11 - I/O 5VT Default: PF1 Alternate: CAN0_RX, EXMC_D30, TLI_VSYNC, EVENTOUT Default: PI10 Alternate: ETH_MII_RX_ER, EXMC_D31, TLI_HSYNC, EVENTOUT Default: PI11 Alternate: USBHS_ULPI_DIR, EVENTOUT Default: PF0 Alternate: I2C1_SDA, EXMC_A0, EVENTOUT, CTC_SYNC 16 / 66 I/O(2) Level LQFP100 LQFP144 Pin Name BGA176 Pins Pin Type(1) GD32F450xx Functions description Alternate: I2C1_SCL, EXMC_A1, EVENTOUT Default: PF2 PF2 H2 12 - I/O 5VT PF3 J2 13 - I/O 5VT Alternate: EXMC_A3, EVENTOUT, I2C1_TXFRAME Alternate: I2C1_SMBA, EXMC_A2, EVENTOUT Default: PF3 Additional: ADC2_IN9 Default: PF4 PF4 J3 14 - I/O 5VT Alternate: EXMC_A4, EVENTOUT Additional: ADC2_IN14 Default: PF5 PF5 K3 15 - I/O 5VT Alternate: EXMC_A5, EVENTOUT Additional: ADC2_IN15 VSS G2 16 10 P - Default: VSS VDD G3 17 11 P - Default: VDD Default: PF6 PF6 K2 18 - I/O 5VT Alternate:TIMER9_CH0, SPI4_NSS, UART6_RX, EXMC_NIORD, EVENTOUT Additional: ADC2_IN4 Default: PF7 PF7 K1 19 - I/O 5VT Alternate:TIMER10_CH0, SPI4_SCK, UART6_TX, EXMC_NREG, EVENTOUT Additional: ADC2_IN5 Default: PF8 PF8 L3 20 - I/O 5VT Alternate:SPI4_MISO, TIMER12_CH0, EXMC_NIOWR, EVENTOUT Additional: ADC2_IN6 Default: PF9 PF9 L2 21 - I/O 5VT Alternate: SPI4_MOSI, TIMER13_CH0, EXMC_CD, EVENTOUT Additional: ADC2_IN7 Default: PF10 PF10 L1 22 - I/O 5VT Alternate: EXMC_INTR, DCI_D11, TLI_DE, EVENTOUT Additional: ADC2_IN8 Default: PH0, OSCIN PH0 G1 23 12 I/O 5VT Alternate: EVENTOUT Additional: OSCIN Default: PH1, OSCOUT PH1 H1 24 13 I/O 5VT Alternate: EVENTOUT Additional: OSCOUT NRST J1 25 14 PC0 M2 26 15 - - Default: NRST Default: PC0 I/O 5VT Alternate: USBHS_ULPI_STP, EXMC_SDNWE, EVENTOUT Additional: ADC012_IN10 PC1 M3 27 16 I/O 5VT Default: PC1 Alternate:SPI2_MOSI, I2S2_SD, SPI1_MOSI, I2S1_SD, ETH_MDC, 17 / 66 I/O(2) Level LQFP100 LQFP144 Pin Name BGA176 Pins Pin Type(1) GD32F450xx Functions description EVENTOUT Additional: ADC012_IN11 Default: PC2 PC2 M4 28 17 I/O 5VT Alternate:SPI1_MISO, I2S1_ADD_SD, USBHS_ULPI_DIR, ETH_MII_TXD2, EXMC_SDNE0, EVENTOUT Additional: ADC012_IN12 Default: PC3 PC3 M5 29 18 I/O 5VT Alternate:SPI1_MOSI, I2S1_SD, USBHS_ULPI_NXT, ETH_MII_TX_CLK, EXMC_SDCKE0, EVENTOUT Additional: ADC012_IN13 VDD G3 30 19 P - Default: VDD VSSA M1 31 20 P - Default: VSSA VREFN N1 - - P - Default: VREF- VREFP P1 32 21 P - Default: VREF+ VDDA R1 33 22 P - Default: VDDA Default: PA0 PA0-WKUP N3 34 23 I/O 5VT Alternate:TIMER1_CH0, TIMER1_ETI, TIMER4_CH0, TIMER7_ETI, USART1_CTS, UART3_TX, ETH_MII_CRS, EVENTOUT Additional: ADC012_IN0, WKUP Default: PA1 PA1 N2 35 24 I/O 5VT Alternate:TIMER1_CH1, TIMER4_CH1, SPI3_MOSI, USART1_RTS, UART3_RX, ETH_MII_RX_CLK, ETH_RMII_REF_CLK, EVENTOUT Additional: ADC012_IN1 Default: PA2 PA2 P2 36 25 I/O 5VT Alternate:TIMER1_CH2, TIMER4_CH2, TIMER8_CH0, I2S_CKIN, USART1_TX, ETH_MDIO, EVENTOUT Additional: ADC012_IN2 PH2 F4 - - I/O 5VT Default: PH2 Alternate: ETH_MII_CRS, EXMC_SDCKE0, TLI_R0, EVENTOUT Default: PH3 PH3 G4 - - I/O 5VT Alternate: ETH_MII_COL, EXMC_SDNE0, TLI_R1, EVENTOUT, I2C1_TXFRAME PH4 H4 - - I/O 5VT PH5 J4 - - I/O 5VT Default: PH4 Alternate: I2C1_SCL, USBHS_ULPI_NXT, EVENTOUT Default: PH5 Alternate: I2C1_SDA, SPI4_NSS, EXMC_SDNWE, EVENTOUT Default: PA3 I/O 5VT Alternate:TIMER1_CH3, TIMER4_CH3, TIMER8_CH1, I2S1_MCK, PA3 R2 37 26 VSS - 38 27 P - Default: VSS NC L4 - - - - - USART1_RX, USBHS_ULPI_D0, ETH_MII_COL, TLI_B5, EVENTOUT Additional: ADC012_IN3 18 / 66 K4 39 28 I/O(2) Level LQFP100 VDD LQFP144 Pin Name BGA176 Pins Pin Type(1) GD32F450xx P - Functions description Default: VDD Default: PA4 PA4 N4 40 29 I/O TTa Alternate:SPI0_NSS, SPI2_NSS, I2S2_WS, USART1_CK, USBHS_SOF, DCI_HSYNC, TLI_VSYNC, EVENTOUT Additional: ADC01_IN4, DAC_OUT0 Default: PA5 PA5 P4 41 30 I/O TTa Alternate:TIMER1_CH0, TIMER1_ETI, TIMER7_CH0_ON, SPI0_SCK, USBHS_ULPI_CK, EVENTOUT Additional: ADC01_IN5, DAC_OUT1 Default: PA6 Alternate:TIMER0_BRKIN, TIMER2_CH0, TIMER7_BRKIN, SPI0_MISO, PA6 P3 42 31 I/O 5VT I2S1_MCK, TIMER12_CH0, SDIO_CMD, DCI_PIXCLK, TLI_G2, EVENTOUT Additional: ADC01_IN6 Default: PA7 Alternate:TIMER0_CH0_ON, TIMER2_CH1, TIMER7_CH0_ON, PA7 R3 43 32 I/O 5VT SPI0_MOSI, TIMER13_CH0, ETH_MII_RX_DV, ETH_RMII_CRS_DV, EXMC_SDNWE, EVENTOUT Additional: ADC01_IN7 Default: PC4 PC4 N5 44 33 I/O 5VT Alternate: ETH_MII_RXD0, ETH_RMII_RXD0, EXMC_SDNE0, EVENTOUT Additional: ADC01_IN14 Default: PC5 PC5 P5 45 34 I/O 5VT Alternate:USART2_RX, ETH_MII_RXD1, ETH_RMII_RXD1, EXMC_SDCKE0, EVENTOUT Additional: ADC01_IN15 Default: PB0 Alternate:TIMER0_CH1_ON, TIMER2_CH2, TIMER7_CH1_ON, PB0 R5 46 35 I/O 5VT SPI4_SCK, SPI2_MOSI, I2S2_SD, TLI_R3, USBHS_ULPI_D1, ETH_MII_RXD2, SDIO_D1, EVENTOUT Additional: ADC01_IN8, IREF Default: PB1 Alternate:TIMER0_CH2_ON, TIMER2_CH3, TIMER7_CH2_ON, PB1 R4 47 36 I/O 5VT SPI4_NSS, TLI_R6, USBHS_ULPI_D2, ETH_MII_RXD3, SDIO_D2, EVENTOUT Additional: ADC01_IN9 Default: PB2, BOOT1 PB2 M6 48 37 I/O 5VT Alternate:TIMER1_CH3, SPI2_MOSI, I2S2_SD, USBHS_ULPI_D4, SDIO_CK, EVENTOUT Default: PF11 PF11 R6 49 - I/O 5VT PF12 P6 50 - I/O 5VT Default: PF12 Alternate: SPI4_MOSI, EXMC_SDNRAS, DCI_D12, EVENTOUT 19 / 66 I/O(2) Level LQFP100 LQFP144 Pin Name BGA176 Pins Pin Type(1) GD32F450xx Functions description Alternate: EXMC_A6, EVENTOUT VSS M8 51 - P - Default: VSS VDD N8 52 - P - Default: VDD PF13 N6 53 - I/O 5VT PF14 R7 54 - I/O 5VT PF15 P7 55 - I/O 5VT PG0 N7 56 - I/O 5VT PG1 M7 57 - I/O 5VT PE7 R8 58 38 I/O 5VT PE8 P8 59 39 I/O 5VT PE9 P9 60 40 I/O 5VT Default: PF13 Alternate: EXMC_A7, EVENTOUT Default: PF14 Alternate: EXMC_A8, EVENTOUT Default: PF15 Alternate: EXMC_A9, EVENTOUT Default: PG0 Alternate: EXMC_A10, EVENTOUT Default: PG1 Alternate: EXMC_A11, EVENTOUT Default: PE7 Alternate: TIMER0_ETI, UART6_RX, EXMC_D4, EVENTOUT Default: PE8 Alternate: TIMER0_CH0_ON, UART6_TX, EXMC_D5, EVENTOUT Default: PE9 Alternate: TIMER0_CH0, EXMC_D6, EVENTOUT VSS M9 61 - P - Default: VSS VDD N9 62 - P - Default: VDD PE10 R9 63 41 I/O 5VT Default: PE10 Alternate: TIMER0_CH1_ON, EXMC_D7, EVENTOUT Default: PE11 PE11 P10 64 42 I/O 5VT Alternate:TIMER0_CH1, SPI3_NSS, SPI4_NSS, EXMC_D8, TLI_G3, EVENTOUT Default: PE12 PE12 R10 65 43 I/O 5VT Alternate:TIMER0_CH2_ON, SPI3_SCK, SPI4_SCK, EXMC_D9, TLI_B4, EVENTOUT Default: PE13 PE13 N11 66 44 I/O 5VT Alternate:TIMER0_CH2, SPI3_MISO, SPI4_MISO, EXMC_D10, TLI_DE, EVENTOUT Default: PE14 PE14 P11 67 45 I/O 5VT Alternate:TIMER0_CH3, SPI3_MOSI, SPI4_MOSI, EXMC_D11, TLI_PIXCLK, EVENTOUT PE15 R11 68 46 I/O 5VT Default: PE15 Alternate: TIMER0_BRKIN, EXMC_D12, TLI_R7, EVENTOUT Default: PB10 PB10 R12 69 47 I/O 5VT Alternate:TIMER1_CH2, I2C1_SCL, SPI1_SCK, I2S1_CK, I2S2_MCK, USART2_TX, USBHS_ULPI_D3, ETH_MII_RX_ER, SDIO_D7, TLI_G4, EVENTOUT PB11 R13 70 48 I/O 5VT Default: PB11 Alternate:TIMER1_CH3, I2C1_SDA, I2S_CKIN, USART2_RX, 20 / 66 I/O(2) Level LQFP100 LQFP144 Pin Name BGA176 Pins Pin Type(1) GD32F450xx Functions description USBHS_ULPI_D4, ETH_MII_TX_EN, ETH_RMII_TX_EN, TLI_G5, EVENTOUT NC M10 71 49 P - Default: VCORE VDD N10 72 50 P - Default: VDD PH6 M11 - - Default: PH6 I/O 5VT Alternate:I2C1_SMBA, SPI4_SCK, TIMER11_CH0, ETH_MII_RXD2, EXMC_SDNE1, DCI_D8, EVENTOUT Default: PH7 PH7 N12 - - I/O 5VT Alternate:I2C2_SCL, SPI4_MISO, ETH_MII_RXD3, EXMC_SDCKE1, DCI_D9, EVENTOUT PH8 M12 - - I/O 5VT Default: PH8 Alternate: I2C2_SDA, EXMC_D16, DCI_HSYNC, TLI_R2, EVENTOUT Default: PH9 PH9 M13 - - I/O 5VT Alternate:I2C2_SMBA, TIMER11_CH1, EXMC_D17, DCI_D0, TLI_R3, EVENTOUT Default: PH10 PH10 L13 - - I/O 5VT Alternate:TIMER4_CH0, EXMC_D18, DCI_D1, TLI_R4, EVENTOUT, I2C2_TXFRAME Default: PH11 PH11 L12 - - I/O 5VT PH12 K12 - - I/O 5VT VSS H12 - - P - Default: VSS VDD J12 - - P - Default: VDD Alternate: TIMER4_CH1, EXMC_D19, DCI_D2, TLI_R5, EVENTOUT Default: PH12 Alternate: TIMER4_CH2, EXMC_D20, DCI_D3, TLI_R6, EVENTOUT Default: PB12 PB12 P12 73 51 I/O 5VT Alternate:TIMER0_BRKIN, I2C1_SMBA, SPI1_NSS, I2S1_WS, SPI3_NSS, USART2_CK, CAN1_RX, USBHS_ULPI_D5, ETH_MII_TXD0, ETH_RMII_TXD0, USBHS_ID, EVENTOUT Default: PB13 Alternate:TIMER0_CH0_ON, SPI1_SCK, I2S1_CK, SPI3_SCK, PB13 P13 74 52 I/O 5VT USART2_CTS, CAN1_TX, USBHS_ULPI_D6, ETH_MII_TXD1, ETH_RMII_TXD1, EVENTOUT, I2C1_TXFRAME Additional: USBHS_VBUS Default: PB14 PB14 R14 75 53 I/O 5VT Alternate:TIMER0_CH1_ON, TIMER7_CH1_ON, SPI1_MISO, I2S1_ADD_SD, USART2_RTS, TIMER11_CH0, USBHS_DM, EVENTOUT Default: PB15 PB15 R15 76 54 I/O 5VT Alternate: RTC_REFIN, TIMER0_CH2_ON, TIMER7_CH2_ON, SPI1_MOSI, I2S1_SD, TIMER11_CH1, USBHS_DP, EVENTOUT Default: PD8 PD8 P15 77 55 I/O 5VT PD9 P14 78 56 I/O 5VT Default: PD9 Alternate: USART2_TX, EXMC_D13, EVENTOUT 21 / 66 I/O(2) Level LQFP100 LQFP144 Pin Name BGA176 Pins Pin Type(1) GD32F450xx Functions description Alternate: USART2_RX, EXMC_D14, EVENTOUT Default: PD10 PD10 N15 79 57 I/O 5VT PD11 N14 80 58 I/O 5VT PD12 N13 81 59 I/O 5VT PD13 M15 82 60 I/O 5VT VSS - 83 - P - Default: VSS VDD J13 84 - P - Default: VDD PD14 M14 85 61 I/O 5VT PD15 L14 86 62 I/O 5VT PG2 L15 87 - I/O 5VT PG3 K15 88 - I/O 5VT PG4 K14 89 - I/O 5VT PG5 K13 90 - I/O 5VT PG6 J15 91 - I/O 5VT PG7 J14 92 - I/O 5VT Alternate: USART5_CK, EXMC_INT2, DCI_D13, TLI_PIXCLK, Alternate: USART2_CK, EXMC_D15, TLI_B3, EVENTOUT Default: PD11 Alternate: USART2_CTS, EXMC_A16, EVENTOUT Default: PD12 Alternate: TIMER3_CH0, USART2_RTS, EXMC_A17, EVENTOUT Default: PD13 Alternate: TIMER3_CH1, EXMC_A18, EVENTOUT Default: PD14 Alternate: TIMER3_CH2, EXMC_D0, EVENTOUT Default: PD15 Alternate: TIMER3_CH3, EXMC_D1, EVENTOUT, CTC_SYNC Default: PG2 Alternate:EXMC_A12, EVENTOUT Default: PG3 Alternate: EXMC_A13, EVENTOUT Default: PG4 Alternate: EXMC_A14, EVENTOUT Default: PG5 Alternate: EXMC_A15, EVENTOUT Default: PG6 Alternate: EXMC_INT1, DCI_D12, TLI_R7, EVENTOUT Default: PG7 EVENTOUT Default: PG8 PG8 H14 93 - I/O 5VT Alternate:SPI5_NSS, USART5_RTS, ETH_PPS_OUT, EXMC_SDCLK, EVENTOUT VSS G12 94 - P - Default: VSS VDD H13 95 - P - Default: VDD PC6 H15 96 63 Default: PC6 I/O 5VT Alternate:TIMER2_CH0, TIMER7_CH0, I2S1_MCK, USART5_TX, SDIO_D6, DCI_D0, TLI_HSYNC, EVENTOUT Default: PC7 PC7 G15 97 64 I/O 5VT Alternate:TIMER2_CH1, TIMER7_CH1, SPI1_SCK, I2S1_CK, I2S2_MCK, USART5_RX, SDIO_D7, DCI_D1, TLI_G6, EVENTOUT Default: PC8 PC8 G14 98 65 I/O 5VT Alternate:TRACED0, TIMER2_CH2, TIMER7_CH2, USART5_CK, SDIO_D0, DCI_D2, EVENTOUT PC9 F14 99 66 I/O 5VT Default: PC9 22 / 66 I/O(2) Level LQFP100 LQFP144 Pin Name BGA176 Pins Pin Type(1) GD32F450xx Functions description Alternate:CK_OUT1, TIMER2_CH3, TIMER7_CH3, I2C2_SDA, I2S_CKIN, SDIO_D1, DCI_D3, EVENTOUT Default: PA8 PA8 F15 100 67 I/O 5VT Alternate: CK_OUT0, TIMER0_CH0, I2C2_SCL, USART0_CK, USBFS_SOF, SDIO_D1, TLI_R6, EVENTOUT, CTC_SYNC Default: PA9 PA9 E15 101 68 I/O 5VT Alternate:TIMER0_CH1, I2C2_SMBA, SPI1_SCK, I2S1_CK, USART0_TX, SDIO_D2, DCI_D0, EVENTOUT Additional: USBFS_VBUS Default: PA10 PA10 D15 102 69 I/O 5VT Alternate:TIMER0_CH2, SPI4_MOSI, USART0_RX, USBFS_ID, DCI_D1, EVENTOUT, I2C2_TXFRAME Default: PA11 PA11 C15 103 70 I/O 5VT Alternate:TIMER0_CH3, SPI3_MISO, USART0_CTS, USART5_TX, CAN0_RX, USBFS_DM, TLI_R4, EVENTOUT Default: PA12 PA12 B15 104 71 I/O 5VT Alternate:TIMER0_ETI, SPI4_MISO, USART0_RTS, USART5_RX, CAN0_TX, USBFS_DP, TLI_R5, EVENTOUT PA13 A15 105 72 I/O 5VT Default: JTMS, SWDIO, PA13 Alternate: EVENTOUT NC F13 106 73 - - - VSS F12 107 74 P - Default: VSS VDD G13 108 75 P - Default: VDD Default: PH13 PH13 E12 - - I/O 5VT Alternate: TIMER7_CH0_ON, CAN0_TX, EXMC_D21, TLI_G2, EVENTOUT PH14 E13 - - I/O 5VT Default: PH14 Alternate: TIMER7_CH1_ON, EXMC_D22, DCI_D4, TLI_G3, EVENTOUT Default: PH15 PH15 D13 - - I/O 5VT Alternate: TIMER7_CH2_ON, EXMC_D23, DCI_D11,TLI_G4, EVENTOUT Default: PI0 PI0 E14 - I/O 5VT Alternate:TIMER4_CH3, SPI1_NSS, I2S1_WS, EXMC_D24, DCI_D13, TLI_G5, EVENTOUT Default: PI1 PI1 D14 - - I/O 5VT Alternate:SPI1_SCK, I2S1_CK, EXMC_D25, DCI_D8, TLI_G6, EVENTOUT Default: PI2 PI2 C14 - - I/O 5VT Alternate:TIMER7_CH3, SPI1_MISO, I2S1_ADD_SD, EXMC_D26, DCI_D9, TLI_G7, EVENTOUT Default: PI3 PI3 C13 - - I/O 5VT Alternate:TIMER7_ETI, SPI1_MOSI, I2S1_SD, EXMC_D27, DCI_D10, EVENTOUT 23 / 66 GD32F450xx BGA176 LQFP144 LQFP100 Pin Type(1) I/O(2) Level Pins VSS D9 - - P - Default: VSS VDD C9 - - P - Default: VDD Pin Name Functions description Default: JTCK, SWCLK, PA14 PA14 A14 109 76 I/O 5VT PA15 A13 110 77 I/O 5VT Alternate:TIMER1_CH0, TIMER1_ETI, SPI0_NSS, SPI2_NSS, I2S2_WS, Alternate: EVENTOUT Default: JTDI, PA15 USART0_TX, EVENTOUT Default: PC10 PC10 B14 111 78 I/O 5VT Alternate:SPI2_SCK, I2S2_CK, USART2_TX, UART3_TX, SDIO_D2, DCI_D8, TLI_R2, EVENTOUT Default: PC11 PC11 B13 112 79 I/O 5VT Alternate:I2S2_ADD_SD, SPI2_MISO, USART2_RX, UART3_RX, SDIO_D3, DCI_D4, EVENTOUT Default: PC12 PC12 A12 113 80 I/O 5VT Alternate:I2C1_SDA, SPI2_MOSI, I2S2_SD, USART2_CK, UART4_TX, SDIO_CK, DCI_D9, EVENTOUT Default: PD0 PD0 B12 114 81 I/O 5VT Alternate:SPI3_MISO, SPI2_MOSI, I2S2_SD, CAN0_RX, EXMC_D2, EVENTOUT PD1 C12 115 82 I/O 5VT PD2 D12 116 83 I/O 5VT Default: PD1 Alternate: SPI1_NSS, I2S1_WS, CAN0_TX, EXMC_D3, EVENTOUT Default: PD2 Alternate: TIMER2_ETI, UART4_RX, SDIO_CMD, DCI_D11, EVENTOUT Default: PD3 PD3 D11 117 84 I/O 5VT Alternate:TRACED1, SPI1_SCK, I2S1_CK, USART1_CTS, EXMC_CLK, DCI_D5, TLI_G7, EVENTOUT Default: PD4 PD4 D10 118 85 I/O 5VT PD5 C11 119 86 I/O 5VT VSS D8 120 - P - Default: VSS VDD C8 121 - P - Default: VDD PD6 B11 122 87 Alternate: USART1_RTS, EXMC_NOE, EVENTOUT Default: PD5 Alternate: USART1_TX, EXMC_NWE, EVENTOUT Default: PD6 I/O 5VT Alternate:SPI2_MOSI, I2S2_SD, USART1_RX, EXMC_NWAIT, DCI_D10, TLI_B2, EVENTOUT PD7 A11 123 88 PG9 C10 124 I/O 5VT Default: PD7 Alternate: USART1_CK, EXMC_NE0, EXMC_NCE1, EVENTOUT Default: PG9 - I/O 5VT Alternate:USART5_RX, EXMC_NE1, EXMC_NCE2, DCI_VSYNC, EVENTOUT Default: PG10 PG10 B10 125 - I/O 5VT Alternate:SPI5_IO2, TLI_G3, EXMC_NCE3_0, EXMC_NE2, DCI_D2, TLI_B2, EVENTOUT 24 / 66 I/O(2) Level LQFP100 LQFP144 Pin Name BGA176 Pins Pin Type(1) GD32F450xx Functions description Default: PG11 PG11 B9 126 - I/O 5VT Alternate:SPI5_IO3, SPI3_SCK, ETH_MII_TX_EN, ETH_RMII_TX_EN, EXMC_NCE3_1, DCI_D3, TLI_B3, EVENTOUT Default: PG12 PG12 B8 127 - I/O 5VT Alternate:SPI5_MISO, SPI3_MISO, USART5_RTS, TLI_B4, EXMC_NE3, TLI_B1, EVENTOUT Default: PG13 PG13 A8 128 - I/O 5VT Alternate:TRACED2, SPI5_SCK, SPI3_MOSI, USART5_CTS, ETH_MII_TXD0, ETH_RMII_TXD0, EXMC_A24, EVENTOUT Default: PG14 PG14 A7 129 - I/O 5VT Alternate:TRACED3, SPI5_MOSI, SPI3_NSS, USART5_TX, ETH_MII_TXD1, ETH_RMII_TXD1, EXMC_A25, EVENTOUT VSS D7 130 - P - Default: VSS VDD C7 131 - P - Default: VDD PG15 B7 132 - I/O 5VT Default: PG15 Alternate: USART5_CTS, EXMC_SDNCAS, DCI_D13, EVENTOUT Default: JTDO, PB3 PB3 A10 133 89 I/O 5VT Alternate: TRACESWO, TIMER1_CH1, SPI0_SCK, SPI2_SCK, I2S2_CK, USART0_RX, I2C1_SDA, EVENTOUT Default: JNTRST, PB4 PB4 A9 134 90 I/O 5VT Alternate:TIMER2_CH0, SPI0_MISO, SPI2_MISO, I2S2_ADD_SD, I2C2_SDA, SDIO_D0, EVENTOUT, I2C0_TXFRAME Default: PB5 PB5 A6 135 91 I/O 5VT Alternate:TIMER2_CH1, I2C0_SMBA, SPI0_MOSI, SPI2_MOSI, I2S2_SD, CAN1_RX, USBHS_ULPI_D7, ETH_PPS_OUT, EXMC_SDCKE1, DCI_D10, EVENTOUT Default: PB6 PB6 B6 136 92 I/O 5VT Alternate:TIMER3_CH0, I2C0_SCL, USART0_TX, CAN1_TX, EXMC_SDNE1, DCI_D5, EVENTOUT Default: PB7 PB7 B5 137 93 I/O 5VT Alternate:TIMER3_CH1, I2C0_SDA, USART0_RX, EXMC_NL, DCI_VSYNC, EVENTOUT BOOT0 D6 138 94 I/O 5VT Default: BOOT0 Default: PB8 PB8 A5 139 95 I/O 5VT Alternate:TIMER1_CH0, TIMER1_ETI, TIMER3_CH2, TIMER9_CH0, I2C0_SCL, SPI4_MOSI, CAN0_RX, ETH_MII_TXD3, SDIO_D4, DCI_D6, TLI_B6, EVENTOUT Default: PB9 PB9 B4 140 96 I/O 5VT Alternate:TIMER1_CH1, TIMER3_CH3, TIMER10_CH0, I2C0_SDA, SPI1_NSS, I2S1_WS, CAN0_TX, SDIO_D5, DCI_D7, TLI_B7, EVENTOUT PE0 A4 141 97 I/O 5VT Default: PE0 Alternate: TIMER3_ETI, UART7_RX, EXMC_NBL0, DCI_D2, EVENTOUT 25 / 66 I/O(2) Level LQFP100 LQFP144 Pin Name BGA176 Pins Pin Type(1) GD32F450xx Functions description Default: PE1 PE1 A3 142 98 I/O 5VT Alternate: TIMER0_CH1_ON, UART7_TX, EXMC_NBL1, DCI_D3, EVENTOUT VSS D5 - 99 P - Default: VSS PDR_ON C6 143 - P - Default: PDR_ON VDD C5 144 100 P - Default: VDD PI4 D4 - - I/O 5VT Default: PI4 Alternate: TIMER7_BRKIN, EXMC_NBL2, DCI_D5, TLI_B4, EVENTOUT Default: PI5 PI5 C4 - - I/O 5VT Alternate: TIMER7_CH0, EXMC_NBL3, DCI_VSYNC, TLI_B5, EVENTOUT PI6 C3 - - I/O 5VT PI7 C2 - - I/O 5VT Default: PI6 Alternate: TIMER7_CH1, EXMC_D28, DCI_D6, TLI_B6, EVENTOUT Default: PI7 Alternate: TIMER7_CH2, EXMC_D29, DCI_D7, TLI_B7, EVENTOUT Notes: 1. Type: I = input, O = output, P = power. 2. I/O Level: 5VT = 5 V tolerant. 26 / 66 GD32F450xx Table 3. Port A alternate functions summary Pin Name AF0 AF1 AF2 AF3 PA0 TIMER1_CH0 TIMER4_ TIMER7_E /TIMER1_ETI CH0 TI PA1 TIMER1_CH1 PA2 TIMER1_CH2 AF4 SPI3_M OSI TIMER4_ CH1 PA6 PA7 USART1_ UART3_R RTS X SPI0_M OSI TIMER13_ CH0 TIMER0_CH1 PA10 TIMER0_CH2 PA11 TIMER0_CH3 PA12 TIMER0_ETI I2C2_SCL USART0_ CK AF11 AF12 AF13 AF14 AF15 EVENTOUT EVENTOUT ETH_MDIO EVENTOUT USBHS_U ETH_MII_C LPI_D0 OL TLI_B5 EVENTOUT USBHS_ DCI_HSY TLI_VS EVENTOUT SOF NC YNC USBHS_U LPI_CK EVENTOUT SDIO_C DCI_PIXC TLI_G2 EVENTOUT MD LK ETH_MII_R X_DV/ETH_ EXMC_S RMII_CRS_ DNWE DV CTC_SYN USBFS_S SDIO_D C OF 1 SPI1_S I2C2_SMB USART0_ CK/I2S1 A TX _CK I2C2_TXF USART0_ SPI4_MOSI USBFS_ID RAME RX USART0_ USART5_ USBFS_D SPI3_MISO CAN0_RX CTS TX M USART0_ USART5_ USBFS_D SPI4_MISO CAN0_TX RTS RX P JTMS/S WDIO JTCK/S WCLK JTDI AF10 ETH_MII_C RS ETH_MII_R X_CLK/ETH _RMII_REF _CLK TIMER0_CH0 TIMER2_ TIMER7_C _ON CH1 H0_ON PA9 PA15 AF9 TIMER12_ CH0 CK_OUT TIMER0_CH0 0 PA14 AF8 TIMER1_CH0 TIMER7_C /TIMER1_ETI H0_ON TIMER0_BR TIMER2_ TIMER7_B KIN CH0 RKIN PA8 PA13 AF7 I2S_CKI USART1_ N TX I2S1_M USART1_ CK RX SPI0_N SPI2_NSS/I2 USART1_ SS S2_WS CK SPI0_S CK SPI0_MI I2S1_MCK SO PA4 PA5 AF6 USART1_ UART3_T CTS X TIMER4_ TIMER8_C CH2 H0 TIMER4_ TIMER8_C TIMER1_CH3 CH3 H1 PA3 AF5 SDIO_D 2 EVENTOUT TLI_R6 DCI_D0 EVENTOUT EVENTOUT DCI_D1 EVENTOUT TLI_R4 EVENTOUT TLI_R5 EVENTOUT EVENTOUT EVENTOUT TIMER1_CH0 /TIMER1_ETI SPI0_N SPI2_NSS/I2 USART0_ SS S2_WS TX EVENTOUT 27 / 66 GD32F450xx Table 4. Port B alternate functions summary Pin Name PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 TIMER0_C TIMER2_C TIMER7_C SPI2_MOSI SPI4_SCK H1_ON H2 H1_ON /I2S2_SD TIMER0_C TIMER2_C TIMER7_C SPI4_NSS H2_ON H3 H2_ON TIMER1_C SPI2_MOSI H3 /I2S2_SD JTDO/TRA TIMER1_C SPI2_SCK USART0_R SPI0_SCK CESWO H1 /I2S2_CK X TIMER2_C I2C0_TXF SPI0_MIS SPI2_MIS I2S2_ADD_ JNTRST H0 RAME O O SD SPI2_MO I2C0_SMB SPI0_MO TIMER2_C SI/I2S2_S A SI H1 D TIMER3_C USART0_T I2C0_SCL H0 X TIMER3_C USART0_R I2C0_SDA H1 X TIMER1_C SPI4_MO TIMER3_C TIMER9_C H0/TIMER I2C0_SCL SI H2 H0 1_ETI TIMER1_C TIMER3_C TIMER10_ SPI1_NSS I2C0_SDA H1 H3 CH0 /I2S1_WS TIMER1_C SPI1_SCK USART2_T I2C1_SCL I2S2_MCK H2 /I2S1_CK X AF8 AF9 TLI_R3 TLI_R6 AF10 AF12 AF13 AF14 EVENTOUT EVENTOUT EVENTOUT SDIO_D 0 I2C2_SDA CAN1_RX EVENTOUT USBHS_U ETH_PPS_ EXMC_S DCI_D10 LPI_D7 OUT DCKE1 EVENTOUT EXMC_S DCI_D5 DNE1 EXMC_N DCI_VSY L NC CAN1_TX ETH_MII_T SDIO_D XD3 4 CAN0_RX TIMER11_ CH0 SDIO_D 5 ETH_MII_R SDIO_D X_ER 7 ETH_MII_T X_EN/ETH_ RMII_TX_E N ETH_MII_T USBHS_ XD0/ETH_R ID MII_TXD0 ETH_MII_T XD1/ETH_R MII_TXD1 USBHS_ DM TIMER11_ CH1 USBHS_ DP CAN0_TX USBHS_U LPI_D3 USBHS_U LPI_D4 USART2_R X AF15 EVENTOUT I2C1_SDA PB11 TIMER1_C H3 I2C1_SDA I2S_CKIN PB12 TIMER0_B RKIN I2C1_SMB SPI1_NSS USART2_C SPI3_NSS A /I2S1_WS K CAN1_RX USBHS_U LPI_D5 PB13 TIMER0_C H0_ON I2C1_TXF SPI1_SCK USART2_C SPI3_SCK RAME /I2S1_CK TS CAN1_TX USBHS_U LPI_D6 PB14 TIMER0_C H1_ON TIMER7_C H1_ON PB15 RTC_REFI TIMER0_C N H2_ON TIMER7_C H2_ON SPI1_MIS I2S1_ADD USART2_R O _SD TS SPI1_MO SI/I2S1_S D AF11 USBHS_U ETH_MII_R SDIO_D LPI_D1 XD2 1 USBHS_U ETH_MII_R SDIO_D LPI_D2 XD3 2 USBHS_U SDIO_C LPI_D4 K EVENTOUT EVENTOUT DCI_D6 TLI_B6 EVENTOUT DCI_D7 TLI_B7 EVENTOUT TLI_G4 EVENTOUT TLI_G5 EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT 28 / 66 GD32F450xx Table 5. Port C alternate functions summary Pin Name AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 SPI2_MO SPI1_MOSI SI/I2S2_S /I2S1_SD D SPI1_MIS I2S1_ADD O _SD SPI1_MO SI/I2S1_S D PC1 PC2 PC3 USART2_R X PC5 PC6 PC7 PC8 TRACED0 PC9 CK_OUT1 PC12 AF11 TIMER2_C H0 TIMER2_C H1 TIMER2_C H2 TIMER2_C H3 TIMER7_C H0 TIMER7_C H1 TIMER7_C H2 TIMER7_C I2C2_SDA H3 AF12 AF13 AF14 EXMC_SD NWE AF15 EVENTOUT ETH_MDC EVENTOUT USBHS_U ETH_MII_ EXMC_SD LPI_DIR TXD2 NE0 EVENTOUT USBHS_U ETH_MII_ EXMC_SD LPI_NXT TX_CLK CKE0 EVENTOUT ETH_MII_ RXD0/ETH EXMC_SD _RMII_RX NE0 D0 ETH_MII_ RXD1/ETH EXMC_SD _RMII_RX CKE0 D1 PC4 PC11 AF10 USBHS_U LPI_STP PC0 PC10 AF9 EVENTOUT EVENTOUT I2S1_MCK USART5_TX SDIO_D6 DCI_D0 TLI_HS EVENTOUT YNC SPI1_SCK I2S2_MCK /I2S1_CK USART5_RX SDIO_D7 DCI_D1 TLI_G6 EVENTOUT USART5_CK SDIO_D0 DCI_D2 EVENTOUT SDIO_D1 DCI_D3 EVENTOUT SDIO_D2 DCI_D8 SDIO_D3 DCI_D4 EVENTOUT SDIO_CK DCI_D9 EVENTOUT I2S_CKIN SPI2_SCK USART2_T UART3_TX /I2S2_CK X I2S2_ADD SPI2_MIS USART2_R UART3_RX _SD O X SPI2_MO USART2_C UART4_TX I2C1_SDA SI/I2S2_S K D TLI_R2 EVENTOUT PC13 EVENTOUT PC14 EVENTOUT PC15 EVENTOUT 29 / 66 GD32F450xx Table 6. Port D alternate functions summary Pin Name AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 SPI2_MOS SPI3_MISO I/I2S2_SD PD0 SPI1_NSS /I2S1_WS PD1 PD2 UART4_RX AF10 AF11 AF12 AF13 AF14 AF15 EXMC_D2 EVENTOUT CAN0_T X EXMC_D3 EVENTOUT SDIO_CMD DCI_D11 EVENTOUT USART1_ CTS EXMC_CLK DCI_D5 TLI_G7 EVENTOUT PD4 USART1_ RTS EXMC_NOE EVENTOUT PD5 USART1_ TX EXMC_NWE EVENTOUT USART1_ RX EXMC_NWAI DCI_D10 T PD7 USART1_ CK EXMC_NE0/ EXMC_NCE1 EVENTOUT PD8 USART2_ TX EXMC_D13 EVENTOUT PD9 USART2_ RX EXMC_D14 EVENTOUT PD10 USART2_ CK EXMC_D15 PD11 USART2_ CTS EXMC_A16 EVENTOUT USART2_ RTS EXMC_A17 EVENTOUT PD3 TIMER2_ETI AF9 CAN0_R X SPI1_SCK/ I2S1_CK TRACED1 SPI2_MOSI /I2S2_SD PD6 TLI_B2 TLI_B3 EVENTOUT EVENTOUT PD12 TIMER3_CH0 PD13 TIMER3_CH1 EXMC_A18 EVENTOUT PD14 TIMER3_CH2 EXMC_D0 EVENTOUT TIMER3_CH3 EXMC_D1 EVENTOUT PD15 CTC_SYN C 30 / 66 GD32F450xx Table 7. Port E alternate functions summary Pin Name AF0 AF1 AF2 AF3 AF4 AF5 AF6 TIMER 3_ETI PE0 TIMER0_CH1 _ON PE1 PE2 TRACECLK PE3 TRACED0 PE4 TRACED1 PE5 TRACED2 PE6 TRACED3 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART7_RX EXMC_NBL0 DCI_D2 EVENTOUT UART7_TX EXMC_NBL1 DCI_D3 EVENTOUT ETH_MII _TXD3 SPI3_SCK EXMC_A23 EVENTOUT EXMC_A19 EVENTOUT SPI3_NSS EXMC_A20 DCI_D4 TLI_B0 EVENTOUT TIMER8_CH0 SPI3_MISO EXMC_A21 DCI_D6 TLI_G0 EVENTOUT TIMER8_CH1 SPI3_MOSI EXMC_A22 DCI_D7 TLI_G1 EVENTOUT PE7 TIMER0_ETI UART6_RX EXMC_D4 EVENTOUT PE8 TIMER0_CH0 _ON UART6_TX EXMC_D5 EVENTOUT PE9 TIMER0_CH0 EXMC_D6 EVENTOUT PE10 TIMER0_CH1 _ON EXMC_D7 EVENTOUT PE11 TIMER0_CH1 SPI3_NSS SPI4_NSS EXMC_D8 TLI_G3 EVENTOUT PE12 TIMER0_CH2 _ON SPI3_SCK SPI4_SCK EXMC_D9 TLI_B4 EVENTOUT PE13 TIMER0_CH2 SPI3_MISO SPI4_MISO EXMC_D10 TLI_DE EVENTOUT PE14 TIMER0_CH3 SPI3_MOSI SPI4_MOSI EXMC_D11 TLI_PIXCLK EVENTOUT PE15 TIMER0_BR KIN EXMC_D12 TLI_R7 EVENTOUT 31 / 66 GD32F450xx Table 8. Port F alternate functions summary Pin Name AF0 PF0 CTC_SYN C AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 I2C1_SDA EXMC_A0 EVENTOUT PF1 I2C1_SCL EXMC_A1 EVENTOUT PF2 I2C1_SMB A EXMC_A2 EVENTOUT PF3 I2C1_TXF RAME EXMC_A3 EVENTOUT PF4 EXMC_A4 EVENTOUT PF5 EXMC_A5 EVENTOUT PF6 TIMER9_C H0 SPI4_NSS UART6_R X EXMC_NIORD EVENTOUT PF7 TIMER10_ CH0 SPI4_SCK UART6_T X EXMC_NREG EVENTOUT PF8 SPI4_MISO TIMER12_ CH0 EXMC_NIOWR EVENTOUT PF9 SPI4_MOSI TIMER13_ CH0 EXMC_CD EVENTOUT PF10 PF11 EXMC_INTR SPI4_MOSI DCI_D11 TLI_DE EVENTOUT EXMC_SDNRAS DCI_D12 EVENTOUT PF12 EXMC_A6 EVENTOUT PF13 EXMC_A7 EVENTOUT PF14 EXMC_A8 EVENTOUT PF15 EXMC_A9 EVENTOUT 32 / 66 GD32F450xx Table 9. Port G alternate functions summary Pin Name AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 PG0 PG1 PG2 PG3 PG4 PG5 PG6 USART5_ CK USART5_ RTS PG7 PG8 SPI5_NSS USART5_ RX PG9 PG10 SPI5_IO2 PG11 SPI5_IO3 SPI3_SCK PG12 TLI_G3 SPI5_MISO SPI3_MIS O USART5_ RTS PG13 TRACED2 SPI5_SCK SPI3_MO SI USART5_ CTS PG14 TRACED3 SPI5_MOSI SPI3_NSS USART5_ TX PG15 USART5_ CTS TLI_B4 AF10 AF11 AF12 AF13 AF14 AF15 EXMC_A1 EVENTOUT 0 EXMC_A1 EVENTOUT 1 EXMC_A1 EVENTOUT 2 EXMC_A1 EVENTOUT 3 EXMC_A1 EVENTOUT 4 EXMC_A1 EVENTOUT 5 EXMC_IN DCI_D12 TLI_R7 EVENTOUT T1 EXMC_IN TLI_PIX DCI_D13 EVENTOUT T2 CLK ETH_PPS EXMC_SD EVENTOUT _OUT CLK EXMC_NE DCI_VSY EVENTOUT 1/EXMC_ NC NCE2 EXMC_NC E3_0/EXM DCI_D2 TLI_B2 EVENTOUT C_NE2 ETH_MII_ TX_EN/ET EXMC_NC DCI_D3 TLI_B3 EVENTOUT H_RMII_T E3_1 X_EN EXMC_NE TLI_B1 EVENTOUT 3 ETH_MII_ TXD0/ETH EXMC_A2 EVENTOUT _RMII_TX 4 D0 ETH_MII_ TXD1/ETH EXMC_A2 EVENTOUT _RMII_TX 5 D1 EXMC_SD DCI_D13 EVENTOUT NCAS 33 / 66 GD32F450xx Table 10. Port H alternate functions summary Pin Name AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 PH0 EVENTOUT PH1 EVENTOUT PH2 PH3 I2C1_TXFRA ME PH4 I2C1_SCL PH5 I2C1_SDA PH6 I2C2_SCL PH8 I2C2_SDA PH9 I2C2_SMBA TLI_R0 EVENTOUT ETH_MII_ EXMC_SDN COL E0 TLI_R1 EVENTOUT USBHS_U LPI_NXT EVENTOUT EXMC_SDN WE SPI4_NSS I2C1_SMBA SPI4_SCK PH7 ETH_MII_ EXMC_SDC CRS KE0 TIMER11_CH0 SPI4_MISO ETH_MII_ EXMC_SDN DCI_D8 RXD2 E1 EVENTOUT ETH_MII_ EXMC_SDC DCI_D9 RXD3 KE1 EVENTOUT DCI_HS TLI_R2 YNC EVENTOUT EXMC_D17 DCI_D0 TLI_R3 EVENTOUT EXMC_D18 DCI_D1 TLI_R4 EVENTOUT EXMC_D16 TIMER11_CH1 I2C2_TXFRA ME EVENTOUT PH10 TIMER4_CH0 PH11 TIMER4_CH1 EXMC_D19 DCI_D2 TLI_R5 EVENTOUT PH12 TIMER4_CH2 EXMC_D20 DCI_D3 TLI_R6 EVENTOUT PH13 TIMER7_C H0_ON PH14 TIMER7_C H1_ON EXMC_D22 DCI_D4 TLI_G3 EVENTOUT PH15 TIMER7_C H2_ON EXMC_D23 CAN0_TX EXMC_D21 TLI_G2 EVENTOUT DCI_D1 TLI_G4 EVENTOUT 1 34 / 66 GD32F450xx Table 11. Port I alternate functions summary Pin Name PI0 AF0 AF1 AF2 AF3 TIMER4_C H3 PI1 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SPI1_NSS /I2S1_WS EXMC_D24 DCI_D13 TLI_G5 EVENTOUT SPI1_SCK /I2S1_CK EXMC_D25 DCI_D8 TLI_G6 EVENTOUT PI2 TIMER7_C H3 SPI1_MIS I2S1_ADD O _SD EXMC_D26 DCI_D9 TLI_G7 EVENTOUT PI3 TIMER7_E TI SPI1_MO SI/I2S1_S D EXMC_D27 DCI_D10 EVENTOUT PI4 TIMER7_B RKIN EXMC_NB L2 TLI_B4 EVENTOUT PI5 TIMER7_C H0 EXMC_NB DCI_VSY TLI_B5 L3 NC EVENTOUT PI6 TIMER7_C H1 EXMC_D28 DCI_D6 TLI_B6 EVENTOUT PI7 TIMER7_C H2 EXMC_D29 DCI_D7 TLI_B7 EVENTOUT PI8 PI9 EVENTOUT CAN0_RX PI10 PI11 DCI_D5 USBHS_U LPI_DIR EXMC_D30 TLI_VS EVENTOUT YNC ETH_MII_ EXMC_D31 RX_ER TLI_HS EVENTOUT YNC EVENTOUT 35 / 66 GD32F450xx 3 Functional description 3.1 ARM® Cortex®-M4 core The ARM® Cortex®-M4 processor is a high performance embedded processor with DSP instructions which allow efficient signal processing and complex algorithm execution. It brings an efficient, easy-to-use blend of control and signal processing capabilities to meet the digital signal control markets demand. The processor is highly configurable enabling a wide range of implementations from those requiring floating point operations, memory protection and powerful trace technology to cost sensitive devices requiring minimal area, while delivering outstanding computational performance and an advanced system response to interrupts. 32-bit ARM® Cortex®-M4 processor core  Up to 200 MHz operation frequency  Single-cycle multiplication and hardware divider  Floating Point Unit (FPU)  Integrated DSP instructions  Integrated Nested Vectored Interrupt Controller (NVIC)  24-bit SysTick timer The Cortex®-M4 processor is based on the ARMv7-M architecture and supports both Thumb and Thumb-2 instruction sets. Some system peripherals listed below are also provided by Cortex®-M4:  Internal Bus Matrix connected with ICode bus, DCode bus, system bus, Private Peripheral Bus (PPB) and debug accesses (AHB-AP) 3.2  Nested Vectored Interrupt Controller (NVIC)  Flash Patch and Breakpoint (FPB)  Data Watchpoint and Trace (DWT)  Instrument Trace Macrocell (ITM)  Memory Protection Unit (MPU)  Serial Wire JTAG Debug Port (SWJ-DP)  Trace Port Interface Unit (TPIU) On-chip memory  Up to 3072 Kbytes of Flash memory, including code Flash and data Flash  512B of OTP (one-time programmable) memory  256 KB to 512 KB of SRAM The ARM® Cortex®-M4 processor is structured in Harvard architecture which can use separate buses to fetch instructions and load/store data. 3072 Kbytes of inner Flash at most, which includes code Flash and data Flash is available for storing programs and data, and 36 / 66 GD32F450xx accessed (R/W) at CPU clock speed with zero wait states. Up to 512 Kbytes of inner SRAM is composed of SRAM0 (112KB), SRAM1 (16KB), and SRAM2 (64KB) and SRAM3 (256KB) that can be accessed at same time, and including 64 KB of TCM (tightly-coupled memory) data RAM that can be accessed only by the data bus of the Cortex®-M4 core. The additional 4KB of backup SRAM (BKP SRAM) is implemented in the backup domain, which can keep its content even when the VDD power supply is down. The Figure of GD32F450xx memory map shows the memory map of the GD32F450xx series of devices, including Flash, SRAM, peripheral, and other pre-defined regions. 3.3 Clock, reset and supply management  Internal 16 MHz factory-trimmed RC and external 4 to 32 MHz crystal oscillator  Internal 48 MHz RC oscillator  Internal 32 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator  Integrated system clock PLL  2.6 to 3.6 V application supply and I/Os  Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage detector (LVD) The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These include internal RC oscillator and external crystal oscillator, high speed and low speed two types. Several prescalers allow the frequency configuration of the AHB and two APB domains. The maximum frequency of the two AHB domains are 200 MHz. The maximum frequency of the two APB domains including APB1 is 50 MHz and APB2 is 100 MHz. See Figure 6 for details on the clock tree. The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from 2.4 V and down to 1.8V. The device remains in reset mode when VDD is below a specified threshold. The embedded low voltage detector (LVD) monitors the power supply, compares it to the voltage threshold and generates an interrupt as a warning message for leading the MCU into security. Power supply schemes:  VDD range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator. Provided externally through VDD pins.  VSSA, VDDA range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.  VBAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. 37 / 66 GD32F450xx 3.4 Boot modes At startup, boot pins are used to select one of three boot options:  Boot from main Flash memory (default)  Boot from system memory  Boot from on-chip SRAM The boot loader is located in the internal 30KB of information blocks for the boot ROM memory (system memory). It is used to reprogram the Flash memory by using USART0, USART2, and USB Device FS in device mode. It also can be used to transfer and update the Flash memory code, the data and the vector table sections. In default condition, boot from bank 0 of Flash memory is selected. It also supports to boot from bank 1 of Flash memory by setting a bit in option bytes. 3.5 Power saving modes The MCU supports three kinds of power saving modes to achieve even lower power consumption. They are Sleep mode, Deep-sleep mode, and Standby mode. These operating modes reduce the power consumption and allow the application to achieve the best balance between the CPU operating time, speed and power consumption.  Sleep mode In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and any interrupt/event can wake up the system.  Deep-sleep mode In Deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed crystal oscillator (IRC16M, HXTAL) and PLL are disabled. Only the contents of SRAM and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the system from the Deep-sleep mode including the 23 external lines, the RTC alarm, the LVD output, and USB wakeup. When exiting the Deep-sleep mode, the IRC16M is selected as the system clock.  Standby mode In Standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of IRC16M, HXTAL and PLL are disabled. The contents of SRAM and registers (except Backup Registers) are lost. There are four wakeup sources for the Standby mode, including the external reset from NRST pin, the RTC, the FWDG reset, and the rising edge on WKUP pin. 38 / 66 GD32F450xx 3.6 Analog to digital converter (ADC)  12-bit SAR ADC's conversion rate is up to 2.6MSPS  12-bit, 10-bit, 8-bit or 6-bit configurable resolution  Hardware oversampling ratio adjustable from 2 to 256x improves resolution to 16-bit  Input voltage range: VSSA to VDDA (2.6 to 3.6 V)  Temperature sensor Up to three 12-bit 2.6MSPS multi-channel ADCs are integrated in the device. It has a total of 19 multiplexed channels: 16 external channels, 1 channel for internal temperature sensor (VSENSE), 1 channel for internal reference voltage (VREFINT) and 1 channel for external battery power supply (VBAT). The input voltage range is between 2.6 V and 3.6 V. An on-chip hardware oversampling scheme improves performance while off-loading the related computational burden from the CPU. An analog watchdog block can be used to detect the channels, which are required to remain within a specific threshold window. A configurable channel management block can be used to perform conversions in single, continuous, scan or discontinuous mode to support more advanced use. The ADC can be triggered from the events generated by the general-purpose level 0 timers (TMx) and the advanced-control timers (TM0 and TM7) with internal connection. The temperature sensor can be used to generate a voltage that varies linearly with temperature. It is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage in a digital value. 3.7 Digital to analog converter (DAC)  Two 12-bit DAC converter of independent output channel  8-bit or 12-bit mode in conjunction with the DMA controller The 12-bit buffered DAC channel is used to generate variable analog outputs. The DACs are designed with integrated resistor strings structure. The DAC channels can be triggered by the timer update outputs or EXTI with DMA support. The maximum output value of the DAC is VREF+. 39 / 66 GD32F450xx 3.8 DMA  16 channels DMA controller and each channel are configurable (8 for DMA0 and 8 for DMA1)  Support independent 8, 16, 32-bit memory and peripheral transfer  Peripherals supported: Timers, ADC, SPIs, I2Cs, USARTs, DAC, I2S, SDIO and DCI The flexible general-purpose DMA controllers provide a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Three types of access method are supported: peripheral to memory, memory to peripheral, memory to memory Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel requests are determined by software configuration and hardware channel number. Transfer size of source and destination are independent and configurable. 3.9 General-purpose inputs/outputs (GPIOs)  Up to 140 fast GPIOs, all mappable on 16 external interrupt vectors (EXTI)  Analog input/output configurable  Alternate function input/output configurable There are up to 140 general purpose I/O pins (GPIO) in GD32F450xx, named PA0 ~ PA15, PB0 ~ PB15, PC0 ~ PC15, PD0 ~ PD15, PE0 ~ PE15, PF0 ~ PF15, PG0 ~ PG15, PH0 ~ PH15 and PI0 ~ PI11 to implement logic input/output functions. Each of the GPIO ports has related control and configuration registers to satisfy the requirements of specific applications. The external interrupts on the GPIO pins of the device have related control and configuration registers in the External Interrupt Control Unit (EXTI). The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility on the package pins. Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current capable except for analog inputs. 40 / 66 GD32F450xx 3.10 Timers and PWM generation  Two 16-bit advanced-control timer (TM0 & TM7), eight 16-bit general-purpose timers (TM2, TM3, TM8 ~ TM13), two 32-bit general-purpose timers (TM1 & TM4) and two 16bit basic timer (TM5 & TM6)  Up to 4 independent channels of PWM, output compare or input capture for each generalpurpose timer (GPTM) and external trigger input  16-bit, motor control PWM advanced-control timer with programmable dead-time generation for output match  Encoder interface controller with two inputs using quadrature decoder  24-bit SysTick timer down counter  2 watchdog timers (Free watchdog and window watchdog) The advanced-control timer (TM0 & TM7) can be used as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable dead-time generation. It can also be used as a complete general-purpose timer. The 4 independent channels can be used for input capture, output compare, PWM generation (edge- or center-aligned counting modes) and single pulse mode output. If configured as a general-purpose 16-bit timer, it has the same functions as the TMx timer. It can be synchronized with external signals or to interconnect with other GPTMs together which have the same architecture and features. The general-purpose timer (GPTM), can be used for a variety of purposes including general time, input signal pulse width measurement or output waveform generation such as a single pulse generation or PWM output, up to 4 independent channels for input capture/output compare. TM1 & TM4 is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TM2 & TM3 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. TM9 ~ TM13 is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. The GPTM also supports an encoder interface with two inputs using quadrature decoder. The basic timer, known as TM5 & TM6, are mainly used for DAC trigger generation. They can also be used as a simple 16-bit time base. The GD32F450xx have two watchdog peripherals, free watchdog and window watchdog. They offer a combination of high safety level, flexibility of use and timing accuracy. The free watchdog timer includes a 12-bit down-counting counter and a 8-bit prescaler, It is clocked from an independent 32 kHz internal RC and as it operates independently of the main clock, it can operate in deep sleep and standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. The window watchdog is based on a 7-bit down counter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 41 / 66 GD32F450xx The SysTick timer is dedicated for OS, but could also be used as a standard down counter. It features: 3.11  A 24-bit down counter  Auto reload capability  Maskable system interrupt generation when the counter reaches 0  Programmable clock source Real time clock (RTC) and backup registers  Independent binary-coded decimal (BCD) format timer/counter with twenty 32-bit backup registers.  Calendar with subsecond, seconds, minutes, hours, week day, date, year and month automatically correction  Alarm function with wake up from deep-sleep and standby mode capability  On-the-fly correction for synchronization with master clock. Digital calibration with 1 ppm resolution for compensation of quartz crystal inaccuracy. The real time clock is an independent timer which provides a set of continuously running counters in backup registers to provide a real calendar function, and provides an alarm interrupt or an expected interrupt. It is not reset by a system or power reset, or when the device wakes up from standby mode. A prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz from external crystal oscillator. 3.12 Inter-integrated circuit (I2C)  Up to three I2C bus interfaces can support both master and slave mode with a frequency up to 400 kHz (Fast mode)  Provide arbitration function, optional PEC (packet error checking) generation and checking  Supports 7-bit and 10-bit addressing mode and general call addressing mode The I2C interface is an internal circuit allowing communication with an external I2C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line (SCL). The I2C module provides two data transfer rates: 100 kHz of standard mode or 400 kHz of the fast mode. The I2C module also has an arbitration detect function to prevent the situation where more than one master attempts to transmit data to the I2C bus at the same time. A CRC-8 calculator is also provided in I2C interface to perform packet error checking for I2C data. 42 / 66 GD32F450xx 3.13 Serial peripheral interface (SPI)  Up to six SPI interfaces with a frequency of up to 30 MHz  Support both master and slave mode  Hardware CRC calculation and transmit automatic CRC error checking  Quad wire configuration available in master mode (only in SPI5) The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO & MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by the DMA controller. The SPI interface may be used for a variety of purposes, including simplex synchronous transfers on two lines with a possible bidirectional data line or reliable communication using CRC checking. Quad-SPI master mode is also supported in SPI5 (SPI5 is not available in GD32F450Vx series). 3.14 Universal synchronous/asynchronous receiver transmitter (USART/UART)  Up to four USARTs and four UARTs with operating frequency up to 9 MHz  Supports both asynchronous and clocked synchronous serial communication modes  IrDA SIR encoder and decoder support  LIN break generation and detection  ISO 7816-3 compliant smart card interface The USART (USART0, USART1, USART2, USART5) and UART (UART3, UART4, UART6, UART7) are used to translate data between parallel and serial interfaces, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232 standard communication. The USART/UART includes a programmable baud rate generator which is capable of dividing the system clock to produce a dedicated clock for the USART/UART transmitter and receiver. The USART/UART also supports DMA function for high speed data communication. 3.15 Inter-IC sound (I2S)  Two I2S bus Interfaces with sampling frequency from 8 kHz to 192 kHz, multiplexed with SPI1 and SPI2  Support either master or slave mode Audio  Sampling frequencies from 8 kHz up to 192 kHz are supported. The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio applications by 4-wire serial lines. GD32F450xx contain an I2S-bus interface that can be operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI1 and SPI2. The audio sampling frequencies from 8 kHz to 192 kHz is supported. 43 / 66 GD32F450xx 3.16 Universal serial bus on-the-go full-speed (USB OTG FS)  One USB device/host/OTG full-speed Interface with frequency up to 12 Mbit/s  Internal 48 MHz oscillator support crystal-less operation  Internal main PLL for USB CLK compliantly  Internal USB OTG FS PHY support The Universal Serial Bus (USB) is a 4-wire bus with 4 bidirectional endpoints. The device controller enables 12 Mbit/s data exchange with integrated transceivers. Transaction formatting is performed by the hardware, including CRC generation and checking. It supports both host and device modes, as well as OTG mode with Host Negotiation Protocol (HNP) and Session Request Protocol (SRP). The controller contains a full-speed USB PHY internal. For full-speed or low-speed operation, no more external PHY chip is needed. It supports all the four types of transfer (control, bulk, Interrupt and isochronous) defined in USB 2.0 protocol. The required precise 48 MHz clock which can be generated from the internal main PLL (the clock source must use an HXTAL crystal oscillator) or by the internal 48 MHz oscillator in automatic trimming mode that allows crystal-less operation. 3.17 Universal serial bus on-the-go high-speed (USB OTG HS)  One USB device/host/OTG high-speed Interface with frequency up to 480 Mbit/s  An external PHY device connected to the ULPI is required when using in HS mode USB OTG HS supports both host and device modes, as well as OTG mode with Host Negotiation Protocol (HNP) and Session Request Protocol (SRP). The controller provides ULPI interface for external USB PHY integration and it also contains a full-speed USB PHY internal. For full-speed or low-speed operation, no more external PHY chip is needed. It supports all the four types of transfer (control, bulk, Interrupt and isochronous) defined in USB 2.0 protocol. HUB connection is supported when USB HS operates at high-speed in host mode. There is also a DMA engine operating as an AHB bus master in USBHS to speed up the data transfer between USB HS and system. 3.18 Controller area network (CAN)  Two CAN2.0B interface with communication frequency up to 1 Mbit/s  Internal main PLL for CAN CLK compliantly Controller area network (CAN) is a method for enabling serial communication in field bus. The CAN protocol has been used extensively in industrial automation and automotive applications. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three mailboxes for transmission and two FIFOs of three message deep for reception. It also provides 28 scalable/configurable identifier filter banks for selecting the incoming messages needed and discarding the others. 44 / 66 GD32F450xx 3.19 Ethernet MAC interface  IEEE 802.3 compliant media access controller (MAC) for Ethernet LAN  10/100 Mbit/s rates with dedicated DMA controller and SRAM  Support hardware precision time protocol (PTP) with conformity to IEEE 1588 The Ethernet media access controller (MAC) conforms to IEEE 802.3 specifications and fully supports IEEE 1588 standards. The embedded MAC provides the interface to the required external network physical interface (PHY) for LAN bus connection via an internal media independent interface (MII) or a reduced media independent interface (RMII). The number of MII signals provided up to 16 with 25 MHz output and RMII up to 7 with 50 MHz output. The function of 32-bit CRC checking is also available. 3.20 External memory controller (EXMC)  Supported external memory: SRAM, PSRAM, ROM and NOR-Flash, NAND Flash and CF card, SDRAM with up to 32-bit data bus  Provide ECC calculating hardware module for NAND Flash memory block  Two SDRAM banks with independent configuration, up to 13-bits Row Address, 11-bits Column Address, 2-bits internal banks address  SDRAM Memory size: 4x16Mx32bit (256 MB), 4x16Mx16bit (128 MB), 4x16Mx8bit (64 MB) External memory controller (EXMC) is an abbreviation of external memory controller. It is divided in to several sub-banks for external device support, each sub-bank has its own chip selection signal but at one time, only one bank can be accessed. The EXMC supports code execution from external memory except NAND Flash and CF card. The EXMC also can be configured to interface with the most common LCD module of Motorola 6800 and Intel 8080 series and reduce the system cost and complexity. The EXMC of GD32F450xx in LQFP144 & BGA176 package also supports synchronous dynamic random access memory (SDRAM). It translates AHB transactions into the appropriate SDRAM protocol, and meanwhile, makes sure the access time requirements of the external SDRAM devices are satisfied. 3.21 Secure digital input and output card interface (SDIO)  Support SD2.0/SDIO2.0/MMC4.2 host interface The Secure Digital Input and Output Card Interface (SDIO) provides access to external SD memory cards specifications version 2.0, SDIO card specification version 2.0 and multi-media card system specification version 4.2 with DMA supported. In addition, this interface is also compliant with CE-ATA digital protocol rev1.1. 45 / 66 GD32F450xx 3.22 TFT LCD interface (TLI)  24-bit RGB Parallel Pixel Output; 8 bits-per-pixel (RGB888)  Supports up to XVGA (1024x768) resolution  2 display layers with dedicated FIFO (64x32-bit) The TFT LCD interface provides a parallel digital RGB (Red, Green and Blue) and signals for horizontal, vertical synchronization, Pixel Clock and Data Enable as output to interface directly to a variety of LCD (Liquid Crystal Display) and TFT (Thin Film Transistor) panels. A built-in DMA engine continuously move data from system memory to TLI and then, output to an external LCD display. Two separate layers are supported in TLI, as well as layer window and blending function. 3.23 Image processing accelerator (IPA)  Copy one source image to the destination image  Convert one source image to the destination image with specific pixel format  Convert and blend two source images to the destination image with specific pixel format  Fill up the destination image with a specific color The Image processing accelerator (IPA) provides a configurable and flexible image format conversion from one or two source image to the destination image. Eleven pixel formats from 4-bit up to 32-bit per pixel independently for the two source images and five pixel formats from 16-bit up to 32-bit per pixel for the destination image are supported. Two 256*32 bits LookUp Tables (LUT) separately for the two source images are implemented for the indirect pixel formats. 3.24 Digital camera interface (DCI)  Digital video/picture capture  8/10/12/14 data width supported  High transfer efficiency with DMA interface  Video/picture crop supported  Various pixel formats supported including JPEG/YCrCb/RGB  Hard/embedded synchronous signals supported DCI is an 8-bit to 14-bit parallel interface that able to capture video or picture from a camera via Digital Camera Interface. It supports 8/10/12/14 bits data width through DMA operation. 46 / 66 GD32F450xx 3.25 Debug mode  Serial wire JTAG debug port (SWJ-DP) The ARM® SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. 3.26 Package and operation temperature  BGA176 (GD32F450Ix), LQFP144 (GD32F450Zx) and LQFP100 (GD32F450Vx)  Operation temperature range: -40°C to +85°C (industrial level) 47 / 66 GD32F450xx 4 Electrical characteristics 4.1 Absolute maximum ratings The maximum ratings are the limits to which the device can be subjected without permanently damaging the device. Note that the device is not guaranteed to operate properly at the maximum ratings. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Table 12. Absolute maximum ratings Symbol Min Max Unit VDD External voltage range VSS - 0.3 VSS + 3.6 V VDDA External analog supply voltage VSSA - 0.3 VSSA + 3.6 V VBAT External battery supply voltage VSS - 0.3 VSS + 3.6 V Input voltage on 5V tolerant pin VSS - 0.3 VDD + 4.0 V Input voltage on other I/O VSS - 0.3 4.0 V VIN IIO Maximum current for GPIO pins — 25 mA TA Operating temperature range -40 +85 °C Storage temperature range -55 +150 °C Maximum junction temperature — 125 °C TSTG TJ 4.2 Parameter Recommended DC characteristics Table 13. DC operating conditions Symbol Parameter Conditions Min Typ Max Unit VDD Supply voltage — 2.6 3.3 3.6 V VDDA Analog supply voltage Same as VDD 2.6 3.3 3.6 V VBAT Battery supply voltage — 1.8 — 3.6 V 48 / 66 GD32F450xx 4.3 Power consumption The power measurements specified in the tables represent that code with data executing from on-chip Flash with the following specifications. Table 14. Power consumption characteristics Symbol Parameter Conditions VDD=VDDA=3.3V, HXTAL=25MHz, System Min Typ Max Unit — 99.2 — mA — 60.1 — mA -— 56.3 — mA — 35.2 — mA — 67.9 — mA — 30 — mA — 1.57 — mA — 1.55 — mA — 5.36 — μA — 5.03 — μA — 4.45 — μA — 2.03 — μA — 1.73 — μA — 1.43 — μA — 1.43 — μA clock=200MHz, All peripherals enabled VDD=VDDA=3.3V, HXTAL =25MHz, System Supply current clock =200MHz, All peripherals disabled (Run mode) VDD=VDDA=3.3V, HXTAL =25MHz, System clock =108MHz, All peripherals enabled VDD=VDDA=3.3V, HXTAL =25MHz, System Clock =108MHz, All peripherals disabled VDD=VDDA=3.3V, HXTAL =25MHz, CPU clock off, System clock=200MHz, All Supply current peripherals enabled (Sleep mode) VDD=VDDA=3.3V, HXTAL =25MHz, CPU clock off, System clock=200MHz, All IDD peripherals disabled VDD=VDDA=3.3V, Regulator in run mode, Supply current (Deep-Sleep mode) IRC32K on, RTC on, All GPIOs analog mode VDD=VDDA=3.3V, Regulator in low power mode, IRC32K on, RTC on, All GPIOs analog mode VDD=VDDA=3.3V, LXTAL off, IRC32K on, RTC on Supply current VDD=VDDA=3.3V, LXTAL off, IRC32K on, (Standby mode) RTC off VDD=VDDA=3.3V, LXTAL off, IRC32K off, RTC off VDD not available, VBAT=3.6 V, LXTAL on with external crystal, RTC on, Higher driving VDD not available, VBAT=3.3 V, LXTAL on with external crystal, RTC on, Higher IBAT Battery supply current driving VDD not available, VBAT=2.6 V, LXTAL on with external crystal, RTC on, Higher driving VDD not available, VBAT=3.6 V, LXTAL on with external crystal, RTC on, Lower driving 49 / 66 GD32F450xx Symbol Parameter Conditions Min Typ — 1.15 — μA — 0.83 — μA VDD not available, VBAT=3.3 V, LXTAL on with external crystal, RTC on, Lower driving VDD not available, VBAT=2.6 V, LXTAL on with external crystal, RTC on, Lower driving 4.4 Max Unit EMC characteristics EMS (electromagnetic susceptibility) includes ESD (Electrostatic discharge, positive and negative) and FTB (Burst of Fast Transient voltage, positive and negative) testing result is given in the following table, based on the EMS levels and classes compliant with IEC 61000 series standard. Table 15. EMS characteristics Symbol VESD Parameter Conditions Voltage applied to all device pins to VDD = 3.3 V, TA = +25 °C induce a functional disturbance conforms to IEC 61000-4-2 Fast transient voltage burst applied to VFTB induce a functional disturbance through 100 pF on VDD and VSS pins Level/Class 3B VDD = 3.3 V, TA = +25 °C 4A conforms to IEC 61000-4-4 EMI (Electromagnetic Interference) emission testing result is given in the following table, compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 16. EMI characteristics Symbol Parameter Conditions VDD = 5.0 V, SEMI Peak level TA = +25 °C, compliant with IEC 61967-2 Tested frequency band Conditions Unit 24M 48M 0.1 to 2 MHz