74HCT259D

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT259 8-bit addressable latch Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification 8-bit addressable latch 74HC/HCT259 capable of storing single-line data in eight addressable latches, and also 3-to-8 decoder and demultiplexer, with active HIGH outputs (Q0 to Q7), functions are available. FEATURES • Combines demultiplexer and 8-bit latch • Serial-to-parallel capability The “259” also incorporates an active LOW common reset (MR) for resetting all latches, as well as, an active LOW enable input (LE). • Output from each storage bit available • Random (addressable) data entry • Easily expandable The “259” has four modes of operation as shown in the mode select table. In the addressable latch mode, data on the data line (D) is written into the addressed latch. The addressed latch will follow the data input with all non-addressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. • Common reset input • Useful as a 3-to-8 active HIGH decoder • Output capability: standard • ICC category: MSI GENERAL DESCRIPTION In the 3-to-8 decoding or demultiplexing mode, the addressed output follows the state of the D input with all other outputs in the LOW state. In the reset mode all outputs are LOW and unaffected by the address (A0 to A2) and data (D) input. When operating the “259” as an addressable latch, changing more than one bit of address could impose a transient-wrong address. Therefore, this should only be done while in the memory mode. The mode select table summarizes the operations of the “259”. The 74HC/HCT259 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT259 are high-speed 8-bit addressable latches designed for general purpose storage applications in digital systems. The “259” are multifunctional devices QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH PARAMETER HCT D to Qn 18 20 ns An, LE to Qn 17 20 ns MR to Qn 15 20 ns 3.5 3.5 pF 19 19 pF CI input capacitance CPD power dissipation capacitance per latch CL = 15 pF; VCC = 5 V notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V December 1990 UNIT HC propagation delay tPHL CONDITIONS 2 Philips Semiconductors Product specification 8-bit addressable latch 74HC/HCT259 ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1, 2, 3 A0 to A2 address inputs 4, 5, 6, 7, 9 10, 11, 12 Q0 to Q7 latch outputs 8 GND ground (0 V) 13 D data input 14 LE latch enable input (active LOW) 15 MR conditional reset input (active LOW) 16 VCC positive supply voltage Fig.1 Pin configuration. December 1990 Fig.2 Logic symbol. 3 Fig.3 IEC logic symbol. Philips Semiconductors Product specification 8-bit addressable latch 74HC/HCT259 Fig.4 Functional diagram. MODE SELECT TABLE LE MR MODE L H L H H H L L addressable latch memory active HIGH 8-channel demultiplexer reset December 1990 4 Philips Semiconductors Product specification 8-bit addressable latch 74HC/HCT259 FUNCTION TABLE INPUTS OUTPUTS OPERATING MODES MR master reset L H X X X X L L L L L L L L L L L L L L L L d d d d L H L H L L H H L L L L Q=d L L L L Q=d L L L L Q=d L L L L Q=d L L L L L L L L L L L L L L L L L L L L L L L L d d d d L H L H L L H H H H H H L L L L L L L L L L L L L L L L Q=d L L L L Q=d L L L L Q=d L L L L Q=d H H X X X X q0 q1 q2 q3 q4 q5 q6 q7 H H H H L L L L d d d d L H L H L L H H L L L L Q=d q0 q0 q0 q1 Q=d q1 q1 q2 q2 Q=d q2 q3 q3 q3 Q=d q4 q4 q4 q4 q5 q5 q5 q5 q6 q6 q6 q6 q7 q7 q7 q7 H H H H L L L L d d d d L H L H L L H H H H H H q0 q0 q0 q0 q1 q1 q1 q1 q2 q2 q2 q2 q3 q3 q3 q3 Q=d q4 q4 q4 q5 Q=d q5 q5 q6 q6 Q=d q6 q7 q7 q7 Q=d demultiplex (active HIGH) decoder (when D = H) store (do nothing) LE D A0 A1 A2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 addressable latch Notes 1. H = HIGH voltage level L = LOW voltage level X = don’t care d = HIGH or LOW data one set-up time prior to the LOW-to-HIGH LE transition q = lower case letters indicate the state of the referenced output established during the last cycle in which it was addressed or cleared December 1990 5 Philips Semiconductors Product specification 8-bit addressable latch 74HC/HCT259 Fig.5 Logic diagram. December 1990 6 Philips Semiconductors Product specification 8-bit addressable latch 74HC/HCT259 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 min. −40 to +85 typ. max. min. max. −40 to +125 min. UNIT V WAVEFORMS CC (V) max. tPHL/ tPLH propagation delay D to Qn 58 21 17 185 37 31 230 46 39 280 56 48 ns 2.0 4.5 6.0 Fig.7 tPHL/ tPLH propagation delay An to Qn 58 21 17 185 37 31 230 46 39 280 56 48 ns 2.0 4.5 6.0 Fig.8 tPHL/ tPLH propagation delay LE to Qn 55 20 16 170 34 29 215 43 37 255 51 43 ns 2.0 4.5 6.0 Fig.6 tPHL propagation delay MR to Qn 50 18 14 155 31 26 195 39 33 235 47 40 ns 2.0 4.5 6.0 Fig.9 tTHL/ tTLH output transition time 19 7 6 75 15 13 95 19 16 119 22 19 ns 2.0 4.5 6.0 Figs 6 and 7 tW LE pulse width HIGH or LOW 70 14 12 17 6 5 90 18 15 105 21 18 ns 2.0 4.5 6.0 Fig.6 tW MR pulse width LOW 70 14 12 17 6 5 90 18 15 105 21 18 ns 2.0 4.5 6.0 Fig.9 tsu set-up time D, An to LE 80 16 14 19 7 6 100 20 17 120 24 20 ns 2.0 4.5 6.0 Figs 10 and 11 th hold time D to LE 0 0 0 −19 −6 −5 0 0 0 0 0 0 ns 2.0 4.5 6.0 Fig.10 th hold time An to LE 2 2 2 −11 −4 −3 2 2 2 2 2 2 ns 2.0 4.5 6.0 Fig.11 December 1990 7 Philips Semiconductors Product specification 8-bit addressable latch 74HC/HCT259 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT An LE D MR 1.50 1.50 1.20 0.75 December 1990 8 Philips Semiconductors Product specification 8-bit addressable latch 74HC/HCT259 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 min. −40 TO +85 −40 TO +125 typ. max. min. max. min. WAVEFORMS UNIT V CC (V) max. tPHL/ tPLH propagation delay D to Qn 23 39 49 59 ns 4.5 Fig.7 tPHL/ tPLH propagation delay An to Qn 25 41 51 62 ns 4.5 Fig.8 tPHL/ tPLH propagation delay LE to Qn 22 38 48 57 ns 4.5 Fig.6 tPHL propagation delay MR to Qn 23 39 49 59 ns 4.5 Fig.9 tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Figs 6 and 7 tW LE pulse width LOW 19 11 24 29 ns 4.5 Fig.6 tW MR pulse width LOW 18 10 23 27 ns 4.5 Fig.9 tsu set-up time D to LE 17 10 21 26 ns 4.5 Fig.10 tsu set-up time An to LE 17 10 21 26 ns 4.5 Fig.11 th hold time D to LE 0 −8 0 0 ns 4.5 Fig.10 th hold time An to LE 0 −4 0 0 ns 4.5 Fig.11 December 1990 9 Philips Semiconductors Product specification 8-bit addressable latch 74HC/HCT259 AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the enable input (LE) to output (Qn) propagation delays, the enable input pulse width and the output transition times. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the data input (D) to output (Qn) propagation delays and the output transition times. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.8 Waveforms showing the address inputs (An) to outputs (Qn) propagation delays and the output transition times. December 1990 10 Philips Semiconductors Product specification 8-bit addressable latch 74HC/HCT259 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.9 Waveforms showing the conditional reset input (MR) to output (Qn) propagation delays. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.10 Waveforms showing the data set-up and hold times for the D input to LE input. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.11 Waveforms showing the address set-up and hold times for An inputs to LE input. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. December 1990 11