CA-IS3740, CA-IS3741, CA-IS3742, CA-IS3745
www.chipanalog.com
Preview Version
CA-IS374x High-Speed Quad-Channel Digital Isolators
1
Key Features
•
•
•
•
•
•
•
•
Signal Rate: DC to 150Mbps
Wide Operating Supply Voltage: 2.5V to 5.5V
Wide Operating Temperature Range: -40°C to 125°C
No Start-Up Initialization Required
Default Output High and Low Options
High Electromagnetic Immunity
High CMTI: ±100kV/µs (Typical)
Low Power Consumption (Typical):
▪
1.5mA per Channel at 1Mbps with 3.3V Supply
▪
5.5mA per Channel at 100Mbps with 3.3V Supply
Precise Timing (Typical)
▪
8ns Propagation Delay
▪
1ns Pulse Width Distortion
▪
2ns Propagation Delay Skew
▪
5ns Minimum Pulse Width
Isolation Rating up to 5kVrms
Isolation Barrier Life: >40 Years
Tri-state Outputs with ENABLE
Schmitt Trigger Inputs
RoHS-Compliant Packages
▪
SOIC-16 Narrow Body
▪
SOIC-16 Wide Body
•
•
•
•
•
•
2
Applications
•
•
•
•
•
•
Industrial Automation Systems
Motor Control
Medical Electronics
Isolated Switch Mode Supplies
Solar Inverters
Isolated ADC, DAC
3
Description
The CA-IS374x devices are high-performance quad-channel
digital isolators with precise timing characteristics and low
power consumption. The CA-IS374x devices provide high
electromagnetic immunity and low emissions, while
isolating CMOS digital I/Os. All device versions have Schmitt
trigger input for high noise immunity. Each isolation channel
consists of a transmitter and a receiver separated by silicon
dioxide (SiO2) insulation barrier. The CA-IS3740 device has
all four channels in the same direction with output enable
Copyright © 2018, ChipAnalog Incorporated
on the output side (B side), the CA-IS3741 device has three
forward and one reverse-direction channels with output
enable on both sides, the CA-IS3742 device has two forward
and two reverse-direction channels with output enable on
both sides, and the CA-IS3745 device has the same channel
configuration as CA-IS3740 without output enable. All
devices have fail-safe mode option. If the input power or
signal is lost, default output is low for devices with suffix L
and high for devices with suffix H.
CA-IS374x devices has high insulation capability to handle
noise and surge on a data bus or other circuits from entering
the local ground and interfering with or damaging sensitive
circuitry. High CMTI ability promises the correct
transmission of digital signal. The CA-IS374x devices are
available in 16-pin narrow body SOIC and 16-pin wide body
SOIC packages. All products have > 2.5kVrms isolation rating,
and products in wide-body packages support insulation
withstanding up to 5kVrms.
Device Information
PART
NUMBER
CA-IS3740,
CA-IS3741,
CA-IS3742,
CA-IS3745
PACKAGE
BODY SIZE(NOM)
SOIC16-NB (N)
9.90 mm × 3.90 mm
SOIC16-WB(W)
10.30 mm × 7.50 mm
Simplified Channel Structure
Channel A side
Schmitt Trigger
Isolation
Barrrier
Channel B side
Mixer
VIN
Driver
VOUT
Driver
RX
GNDA
GNDB
Channel A side and B side are separated by isolation
capacitors. GNDA and GNDB are the isolated ground for
signals and supplies of A side and B side respectively.
CA-IS3740, CA-IS3741, CA-IS3742, CA-IS3745
Preview Version
4
www.chipanalog.com
Ordering Guide
Table 4-1 Ordering Guide for Valid Ordering Part Number
Ordering Part Number
Number of Inputs
A Side
Number of Inputs
B Side
Default
Output
Isolation
Rating (kV)
Output
Enable
Package
CA-IS3740LN
4
0
Low
2.5
Yes
NB SOIC-16
CA-IS3740LW
4
0
Low
5
Yes
WB SOIC-16
CA-IS3740HN
4
0
High
2.5
Yes
NB SOIC-16
CA-IS3740HW
4
0
High
5
Yes
WB SOIC-16
CA-IS3741LN
3
1
Low
2.5
Yes
NB SOIC-16
CA-IS3741LW
3
1
Low
5
Yes
WB SOIC-16
CA-IS3741HN
3
1
High
2.5
Yes
NB SOIC-16
CA-IS3741HW
3
1
High
5
Yes
WB SOIC-16
CA-IS3742LN
2
2
Low
2.5
Yes
NB SOIC-16
CA-IS3742LW
2
2
Low
5
Yes
WB SOIC-16
CA-IS3742HN
2
2
High
2.5
Yes
NB SOIC-16
CA-IS3742HW
2
2
High
5
Yes
WB SOIC-16
CA-IS3745LN
4
0
Low
2.5
No
NB SOIC-16
CA-IS3745LW
4
0
Low
5
No
WB SOIC-16
CA-IS3745HN
4
0
High
2.5
No
NB SOIC-16
CA-IS3745HW
4
0
High
5
No
WB SOIC-16
Copyright © 2018, ChipAnalog Incorporated
CA-IS3740, CA-IS3741, CA-IS3742
www.chipanalog.com
Preview Version
Table of Contents
1
2
3
4
5
6
7
Key Features ........................................................1
Applications .........................................................1
Description ..........................................................1
Ordering Guide ....................................................2
Revision History ...................................................3
PIN Descriptions and Functions ............................4
Specifications .......................................................5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
5
Absolute Maximum Ratings ............................... 5
ESD Ratings.......................................................... 5
Recommended Operating Conditions ................. 5
Thermal Information ........................................... 6
Power Rating ....................................................... 6
Electrical Characteristics ..................................... 7
1
7.6.1
7.6.2
7.6.3
VDDA = VDDB = 5 V ± 10%, TA = -40 to 125°C.......... 7
VDDA = VDDB = 3.3 V ± 10%, TA = -40 to 125°C....... 7
VDDA = VDDB = 2.5 V ± 5%, TA = -40 to 125°C......... 7
Supply Current Characteristics ............................ 8
7.8
8
9
7.7.1
7.7.2
7.7.3
VDDA = VDDB = 5 V ± 10%, TA = -40 to 125°C ......... 8
VDDA = VDDB = 3.3 V ± 10%, TA = -40 to 125°C ...... 9
VDDA = VDDB = 2.5 V ± 5%, TA = -40 to 125°C ...... 10
7.8.1
7.8.2
7.8.3
VDDA = VDDB = 5 V ± 10%, TA = -40 to 125°C ....... 11
VDDA = VDDB = 3.3 V ± 10%, TA = -40 to 125°C .... 11
VDDA = VDDB = 2.5 V ± 5%, TA = -40 to 125°C ...... 12
Timing Characteristics ....................................... 11
Parameter Measurement Information ................ 13
Detailed Description ..........................................15
9.1
9.2
9.3
Theory of Operation ......................................... 15
Functional Block Diagram ................................. 15
Device Operation Modes .................................. 16
10 Application and Implementation ........................17
11 Package Information ..........................................18
11.1
16-Pin Wide Body SOIC Package Outline and
Recommended Land Pattern .......................................... 18
11.2
16-Pin Narrow Body SOIC Package Outline....... 19
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
This is a preview version, initialized on July 23rd 2018.
Copyright © 2018, ChipAnalog Incorporated
CA-IS3740, CA-IS3741, CA-IS3742, CA-IS3745
Preview Version
6 PIN Descriptions and Functions
www.chipanalog.com
CA-IS3740 16-Pin SOIC NB/WB Top View
VDDA
TX
A2
TX
A3
TX
A4
TX
NC
VDDA
GNDB
GNDA
RX
B1
A1
TX
RX
B2
A2
TX
RX
B3
A3
TX
RX
B4
A4
RX
ENB
ENA
GNDB
GNDA
GNDA
CA-IS3742 16-Pin SOIC NB/WB Top View
VDDA
TX
A2
TX
A3
RX
A4
RX
ENA
GNDA
GNDB
RX
B1
RX
B2
RX
B3
TX
B4
ENB
GNDB
CA-IS3745 16-Pin SOIC NB/WB Top View
VDDB
VDDA
GNDB
GNDA
RX
B1
A1
TX
RX
B2
A2
TX
TX
B3
A3
TX
TX
B4
A4
TX
ENB
NC
GNDB
GNDA
VDDB
ISOLATION BARRIER
A1
ISOLATION BARRIER
GNDA
VDDB
ISOLATION BARRIER
A1
ISOLATION BARRIER
GNDA
CA-IS3741 16-Pin SOIC NB/WB Top View
VDDB
GNDB
RX
B1
RX
B2
RX
B3
RX
B4
NC
GNDB
Figure 6-1 CA-IS374x Top View
Table 6-1 CA-IS374x Pin Description and Functions
Name
VDDA
GNDA
A1
A2
A3
A4
NC1/ENA
GNDA
GNDB
NC1/ENB
B4
B3
B2
B1
GNDB
VDDB
SOIC-16 Pin#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Type
Supply
Ground
Digital Input
Digital Input
Digital I/O
Digital I/O
Digital Input
Ground
Ground
Digital Input
Digital I/O
Digital I/O
Digital Output
Digital Output
Ground
Supply
Description
Side A Power Supply
Side A Ground
Side A Digital Input
Side A Digital Input
Side A Digital Input for CA-IS3740/41/45 or Output for CA-IS3742
Side A Digital Input for CA-IS3740/45 or Output for CA-IS3741/42
Side A Active High Enable. NC for CA-IS3740/45
Side A Ground
Side B Ground
Side B Active High Enable. NC for CA-IS3745
Side B Digital Input for CA-IS3741/42 or Output for CA-IS3740/45
Side B Digital Input for CA-IS3742 or Output for CA-IS3740/41/45
Side B Digital Output
Side B Digital Output
Side B Ground
Side B Power Supply
Note:
1. No Connect. These pins are not internally connected. They can be left floating, tied to VDD or tied to GND
Copyright © 2018, ChipAnalog Incorporated
CA-IS3740, CA-IS3741, CA-IS3742
www.chipanalog.com
7 Specifications
7.1
Preview Version
Absolute Maximum Ratings1
MIN
MAX
UNIT
VDDA, VDDB
Supply Voltage2
-0.5
6.0
V
Vin
Voltage at Ax, Bx, ENx
-0.5
VDDA+0.53
V
IO
Output Current
15
15
mA
TJ
Junction Temperature
150
°C
TSTG
Storage Temperature
-65
150
°C
NOTE:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GNDA or GNDB) and are peak voltage
values.
3. Maximum voltage must not exceed 6 V.
7.2
ESD Ratings
VESD Electrostatic discharge
pins1
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins2
VALUE
2000
200
UNIT
V
NOTE:
1. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
2. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3
Recommended Operating Conditions
VDDA, VDDB
VDD（UVLO+）
Supply Voltage
VDD Undervoltage Threshold When Supply Voltage is Rising
MIN
2.375
1.95
TYP
3.3
2.24
MAX
5.5
2.375
UNIT
V
V
VDD（UVLO-）
VDD Undervoltage Threshold When Supply Voltage is Falling
1.88
2.16
2.325
V
VHYS（UVLO）
VDD Undervoltage Threshold Hysteresis
50
70
95
IOH
High-level Output Current
IOL
Low-level Output Current
VIH
High-level Input Voltage
VIL
Low-level Input Voltage
DR
Data Rate
TA
Ambient Temperature
NOTE:
1. VDDO = Output-side VDD
Copyright © 2018, ChipAnalog Incorporated
VDDO1 = 5V
VDDO = 3.3V
VDDO = 2.5V
VDDO = 5V
VDDO = 3.3V
VDDO = 2.5V
-4
-2
-1
mA
4
2
2
2.0
0
-40
mV
27
0.8
150
125
mA
V
V
Mbps
°C
CA-IS3740, CA-IS3741, CA-IS3742, CA-IS3745
Preview Version
7.4 Thermal Information
www.chipanalog.com
THERMAL METRIC
N (SOIC)
16 Pins
CA-IS374x
W (SOIC)
16 Pins
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
ψJB
Junction-to-board characterization parameter
°C/W
RθJC(bottom)
Junction-to-case(bottom) thermal resistance
°C/W
7.5
°C/W
°C/W
°C/W
°C/W
Power Rating
PARAMETER
CA-IS3740/45
PD
Maximum Power Dissipation
PDA
Maximum Power Dissipation on Side-A
PDB
Maximum Power Dissipation on Side-B
CA-IS3741
PD
Maximum Power Dissipation
PDA
Maximum Power Dissipation on Side-A
PDB
Maximum Power Dissipation on Side-B
CA-IS3742
PD
Maximum Power Dissipation
PDA
Maximum Power Dissipation on Side-A
PDB
Maximum Power Dissipation on Side-B
TEST CONDITIONS
MIN
TYP
MAX
UNIT
200
40
160
mW
mW
mW
TJ = 150°C, Input a 75-MHz 50% duty
cycle square wave
200
50
150
mW
mW
mW
VDDA = VDDB = 5.5 V, CL = 15 pF,
TJ = 150°C, Input a 75-MHz 50% duty
cycle square wave
200
100
100
mW
mW
mW
VDDA = VDDB = 5.5 V, CL = 15 pF,
TJ = 150°C, Input a 75-MHz 50% duty
cycle square wave
VDDA = VDDB = 5.5 V, CL = 15 pF,
Copyright © 2018, ChipAnalog Incorporated
www.chipanalog.com
7.6 Electrical Characteristics
7.6.1 VDDA = VDDB = 5 V ± 10%, TA = -40 to 125°C
VOH
VOL
VIT+(IN)
VIT-(IN)
VI(HYS)
IIH
IIL
ZO
CMTI
CI
PARAMETER
High-level Output Voltage
Low-level Output Voltage
Positive-going Input Threshold
Negative-going Input Threshold
Input Threshold Hysteresis
High-Level Input Leakage Current
Low-Level Input Leakage Current
Output Impedance2
Common-mode Transient Immunity
Input Capacitance3
NOTE:
1.
2.
3.
TEST CONDITIONS
IOH = -4mA; See Figure 8-2
IOL = 4mA; See Figure 8-2
VIH = VDDA at Ax or Bx or ENx
VIL = 0 V at Ax or Bx
VI = VDDI1 or 0 V, VCM = 1200 V; See Figure 8-4
VI = VDD/ 2 + 0.4×sin(2πft), f = 1 MHz,
VDD = 5 V
CA-IS3740, CA-IS3741, CA-IS3742
Preview Version
MIN
TYP
VDDO1-0.4 4.8
0.2
1.4
1.67
1.0
1.23
0.38
0.44
MAX
0.4
1.9
1.4
0.5
10
-10
85
50
100
2
UNIT
V
V
V
V
V
µA
µA
Ω
kV/µS
pF
VDDI = Input-side VDD, VDDO = Output-side VDD
The nominal output impedance of an isolator driver channel is approximately 50 Ω ± 40%.
Measured from pin to Ground.
7.6.2 VDDA = VDDB = 3.3 V ± 10%, TA = -40 to 125°C
VOH
VOL
VIT+(IN)
VIT-(IN)
VI(HYS)
IIH
IIL
ZO
CMTI
CI
PARAMETER
High-level Output Voltage
Low-level Output Voltage
Positive-going Input Threshold
Negative-going Input Threshold
Input Threshold Hysteresis
High-Level Input Leakage Current
Low-Level Input Leakage Current
Output Impedance2
Common-mode Transient Immunity
Input Capacitance3
TEST CONDITIONS
IOH = -4mA; See Figure 8-2
IOL = 4mA; See Figure 8-2
VIH = VDDA at Ax or Bx or ENx
VIL = 0 V at Ax or Bx
VI = VDDI1 or 0 V, VCM = 1200 V; See Figure 8-4
VI = VDD/ 2 + 0.4×sin(2πft), f = 1 MHz,
VDD = 3.3 V
MIN
TYP
VDDO1-0.4 3.1
0.2
1.4
1.67
1.0
1.23
0.38
0.44
MAX
0.4
1.9
1.4
0.5
10
-10
85
50
100
2
UNIT
V
V
V
V
V
µA
µA
Ω
kV/µs
pF
NOTE:
1. VDDI = Input-side VDD, VDDO = Output-side VDD
2. The nominal output impedance of an isolator driver channel is approximately 50 Ω ± 40%.
3. Measured from pin to Ground.
7.6.3 VDDA = VDDB = 2.5 V ± 5%, TA = -40 to 125°C
VOH
VOL
VIT+(IN)
VIT-(IN)
VI(HYS)
IIH
IIL
ZO
CMTI
CI
PARAMETER
High-level Output Voltage
Low-level Output Voltage
Positive-going Input Threshold
Negative-going Input Threshold
Input Threshold Hysteresis
High-Level Input Leakage Current
Low-Level Input Leakage Current
Output Impedance2
Common-mode Transient Immunity
Input Capacitance3
TEST CONDITIONS
IOH = -4mA; See Figure 8-2
IOL = 4mA; See Figure 8-2
VIH = VDDA at Ax or Bx or ENx
VIL = 0 V at Ax or Bx
VI = VDDI1 or 0 V, VCM = 1200 V; See Figure 8-4
VI = VDD/ 2 + 0.4×sin(2πft), f = 1 MHz,
VDD = 2.5 V
NOTE:
1. VDDI = Input-side VDD, VDDO = Output-side VDD
2. The nominal output impedance of an isolator driver channel is approximately 50 Ω ± 40%.
3. Measured from pin to Ground.
Copyright © 2018, ChipAnalog Incorporated
MIN
TYP
VDDO1-0.4 2.3
0.2
1.4
1.67
1.0
1.23
0.38
0.44
-10
85
50
100
2
MAX
0.4
1.9
1.4
0.5
10
UNIT
V
V
V
V
V
µA
µA
Ω
kV/µS
pF
CA-IS3740, CA-IS3741, CA-IS3742, CA-IS3745
Preview Version
7.7 Supply Current Characteristics
7.7.1 VDDA = VDDB = 5 V ± 10%, TA = -40 to 125°C
PARAMETER
CA-IS3740/45
Supply Current – Disable1
Supply Current – DC Signal
Supply Current – AC Signal
CA-IS3741
Supply Current – Disable
Supply Current – DC Signal
Supply Current – AC Signal
CA-IS3742
Supply Current – Disable
Supply Current – DC Signal
Supply Current – AC Signal
www.chipanalog.com
SUPPLY
CURRENT
TEST CONDITION
ENB2 = 0 V; VIN = 0V (CA-IS3740L);
VIN = VDDA (CA-IS3740H)
ENB = 0 V; VIN = VDDA (CA-IS3740L);
VIN = 0V(CA-IS3740H)
ENB = VDDB; VIN = 0V (CA-IS3740/45L);
VIN = VDDA (CA-IS3740/45H)
ENB = VDDB; VIN = VDDA (CA-IS3740/45L);
VIN = 0V(CA-IS3740/45H)
ENB = VDDB; All Channels Switching
with 50% Duty Cycle Square Wave
Clock Input with 5V Amplitude; CL = 15
pF for Each Channel
MAX
UNIT
1.6
3.8
9.2
4.0
1.6
3.8
9.2
4.0
5.0
4.0
5.0
5.6
5.0
22.8
mA
1Mbps
(500kHz)
10Mbps
(5MHz)
100Mbps
(50MHz)
1.0
2.4
6.1
2.5
1.0
2.4
6.1
2.5
3.6
2.9
3.6
4.0
3.6
17.5
1.4
2.3
5.2
3.6
1.4
2.3
5.2
3.6
3.4
3.3
3.7
4.1
7.3
14.3
2.2
3.7
7.8
5.4
2.2
3.7
7.8
5.4
4.8
4.6
5.2
5.8
9.8
18.5
mA
1Mbps
(500kHz)
10Mbps
(5MHz)
100Mbps
(50MHz)
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
1.8
1.8
4.4
4.4
1.8
1.8
4.4
4.4
3.3
3.3
3.9
3.9
11
11
2.9
2.9
6.6
6.6
2.9
2.9
6.6
6.6
4.6
4.6
5.4
5.4
14.3
14.3
mA
1Mbps
(500kHz)
10Mbps
(5MHz)
100Mbps
(50MHz)
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
ENA = ENB = 0 V; VIN = 0V (CA-IS3742L);
VIN = VDDI3 (CA-IS3742H)
ENA = ENB = 0 V; VIN = VDDI (CA-IS3742L);
VIN = 0V(CA-IS3742H)
ENA = ENB = VDDI; VIN = 0V (CA-IS3742L);
VIN = VDDI (CA-IS3742H)
ENA = ENB = VDDI; VIN = VDDI (CA-IS3742L);
VIN = 0V(CA-IS3742H)
ENA = ENB = VDDI; All Channels
Switching with 50% Duty Cycle Square
Wave Clock Input with 5V Amplitude;
CL = 15 pF for Each Channel
TYP
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
ENA = ENB = 0 V; VIN = 0V (CA-IS3741L);
VIN = VDDI1 (CA-IS3741H)
ENA = ENB = 0 V; VIN = VDDI (CA-IS3741L);
VIN = 0V(CA-IS3741H)
ENA = ENB = VDDI; VIN = 0V (CA-IS3741L);
VIN = VDDI (CA-IS3741H)
ENA = ENB = VDDI; VIN = VDDI (CA-IS3741L);
VIN = 0V(CA-IS3741H)
ENA = ENB = VDDI; All Channels
Switching with 50% Duty Cycle Square
Wave Clock Input with 5V Amplitude;
CL = 15 pF for Each Channel
MIN
Note:
1. CA-IS3745 device has no disable state.
2. CA-IS3745 device doesn’t have ENB pin but NC pin instead.
3. VDDI = Input-side VDD
Copyright © 2018, ChipAnalog Incorporated
CA-IS3740, CA-IS3741, CA-IS3742
www.chipanalog.com
7.7.2 VDDA = VDDB = 3.3 V ± 10%, TA = -40 to 125°C
PARAMETER
CA-IS3740/45
Supply Current – Disable1
Supply Current – DC Signal
Supply Current – AC Signal
CA-IS3741
Supply Current – Disable
Supply Current – DC Signal
Supply Current – AC Signal
CA-IS3742
Supply Current – Disable
Supply Current – DC Signal
Supply Current – AC Signal
Preview Version
SUPPLY
CURRENT
TEST CONDITION
ENB2 = 0 V; VIN = 0V (CA-IS3740L);
VIN = VDDA (CA-IS3740H)
ENB = 0 V; VIN = VDDA (CA-IS3740L);
VIN = 0V(CA-IS3740H)
ENB = VDDB; VIN = 0V (CA-IS3740/45L);
VIN = VDDA (CA-IS3740/45H)
ENB = VDDB; VIN = VDDA (CA-IS3740/45L);
VIN = 0V(CA-IS3740/45H)
ENB = VDDB; All Channels Switching
with 50% Duty Cycle Square Wave
Clock Input with 5V Amplitude; CL = 15
pF for Each Channel
Note:
1. CA-IS3745 device has no disable state.
2. CA-IS3745 device doesn’t have ENB pin but NC pin instead.
3. VDDI = Input-side VDD
Copyright © 2018, ChipAnalog Incorporated
MAX
UNIT
1.6
3.8
9.2
4.0
1.6
3.8
9.2
4.0
5.0
4.0
5.0
4.7
5.0
15.9
mA
1Mbps
(500kHz)
10Mbps
(5MHz)
100Mbps
(50MHz)
1.0
2.4
6.1
2.5
1.0
2.4
6.1
2.5
3.6
2.9
3.6
3.4
3.6
12.3
1.4
2.3
5.2
3.6
1.4
2.3
5.2
3.6
3.4
3.3
3.5
3.6
5.9
10.3
2.2
3.7
7.8
5.4
2.2
3.7
7.8
5.4
4.8
4.6
4.9
5.1
7.9
13.4
mA
1Mbps
(500kHz)
10Mbps
(5MHz)
100Mbps
(50MHz)
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
1.8
1.8
4.4
4.4
1.8
1.8
4.4
4.4
3.3
3.3
3.6
3.6
8.2
8.2
2.9
2.9
6.6
6.6
2.9
2.9
6.6
6.6
4.6
4.6
5.0
5.0
10.7
10.7
mA
1Mbps
(500kHz)
10Mbps
(5MHz)
100Mbps
(50MHz)
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
ENA = ENB = 0 V; VIN = 0V (CA-IS3742L);
VIN = VDDI3 (CA-IS3742H)
ENA = ENB = 0 V; VIN = VDDI (CA-IS3742L);
VIN = 0V(CA-IS3742H)
ENA = ENB = VDDI; VIN = 0V (CA-IS3742L);
VIN = VDDI (CA-IS3742H)
ENA = ENB = VDDI; VIN = VDDI (CA-IS3742L);
VIN = 0V(CA-IS3742H)
ENA = ENB = VDDI; All Channels
Switching with 50% Duty Cycle Square
Wave Clock Input with 5V Amplitude;
CL = 15 pF for Each Channel
TYP
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
ENA = ENB = 0 V; VIN = 0V (CA-IS3741L);
VIN = VDDI1 (CA-IS3741H)
ENA = ENB = 0 V; VIN = VDDI (CA-IS3741L);
VIN = 0V(CA-IS3741H)
ENA = ENB = VDDI; VIN = 0V (CA-IS3741L);
VIN = VDDI (CA-IS3741H)
ENA = ENB = VDDI; VIN = VDDI (CA-IS3741L);
VIN = 0V(CA-IS3741H)
ENA = ENB = VDDI; All Channels
Switching with 50% Duty Cycle Square
Wave Clock Input with 5V Amplitude;
CL = 15 pF for Each Channel
MIN
CA-IS3740, CA-IS3741, CA-IS3742, CA-IS3745
Preview Version
7.7.3 VDDA = VDDB = 2.5 V ± 5%, TA = -40 to 125°C
PARAMETER
CA-IS3740/45
Supply Current – Disable1
Supply Current – DC Signal
Supply Current – AC Signal
CA-IS3741
Supply Current – Disable
Supply Current – DC Signal
Supply Current – AC Signal
CA-IS3742
Supply Current – Disable
Supply Current – DC Signal
Supply Current – AC Signal
www.chipanalog.com
SUPPLY
CURRENT
TEST CONDITION
ENB2 = 0 V; VIN = 0V (CA-IS3740L);
VIN = VDDA (CA-IS3740H)
ENB = 0 V; VIN = VDDA (CA-IS3740L);
VIN = 0V(CA-IS3740H)
ENB = VDDB; VIN = 0V (CA-IS3740/45L);
VIN = VDDA (CA-IS3740/45H)
ENB = VDDB; VIN = VDDA (CA-IS3740/45L);
VIN = 0V(CA-IS3740/45H)
ENB = VDDB; All Channels Switching
with 50% Duty Cycle Square Wave
Clock Input with 5V Amplitude; CL = 15
pF for Each Channel
MAX
UNIT
1.6
3.8
9.2
4.0
1.6
3.8
9.2
4.0
5.0
4.0
5.0
4.3
5.0
12.8
mA
1Mbps
(500kHz)
10Mbps
(5MHz)
100Mbps
(50MHz)
1.0
2.4
6.1
2.5
1.0
2.4
6.1
2.5
3.6
2.9
3.6
3.1
3.6
9.9
1.4
2.3
5.2
3.6
1.4
2.3
5.2
3.6
3.4
3.3
3.5
3.4
5.2
8.5
2.2
3.7
7.8
5.4
2.2
3.7
7.8
5.4
4.8
4.6
4.8
4.8
7.0
11.1
mA
1Mbps
(500kHz)
10Mbps
(5MHz)
100Mbps
(50MHz)
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
1.8
1.8
4.4
4.4
1.8
1.8
4.4
4.4
3.3
3.3
3.4
3.4
6.9
6.9
2.9
2.9
6.6
6.6
2.9
2.9
6.6
6.6
4.6
4.6
4.8
4.8
9.0
9.0
mA
1Mbps
(500kHz)
10Mbps
(5MHz)
100Mbps
(50MHz)
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
ENA = ENB = 0 V; VIN = 0V (CA-IS3742L);
VIN = VDDI3 (CA-IS3742H)
ENA = ENB = 0 V; VIN = VDDI (CA-IS3742L);
VIN = 0V(CA-IS3742H)
ENA = ENB = VDDI; VIN = 0V (CA-IS3742L);
VIN = VDDI (CA-IS3742H)
ENA = ENB = VDDI; VIN = VDDI (CA-IS3742L);
VIN = 0V(CA-IS3742H)
ENA = ENB = VDDI; All Channels
Switching with 50% Duty Cycle Square
Wave Clock Input with 5V Amplitude;
CL = 15 pF for Each Channel
TYP
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
ENA = ENB = 0 V; VIN = 0V (CA-IS3741L);
VIN = VDDI1 (CA-IS3741H)
ENA = ENB = 0 V; VIN = VDDI (CA-IS3741L);
VIN = 0V(CA-IS3741H)
ENA = ENB = VDDI; VIN = 0V (CA-IS3741L);
VIN = VDDI (CA-IS3741H)
ENA = ENB = VDDI; VIN = VDDI (CA-IS3741L);
VIN = 0V(CA-IS3741H)
ENA = ENB = VDDI; All Channels
Switching with 50% Duty Cycle Square
Wave Clock Input with 5V Amplitude;
CL = 15 pF for Each Channel
MIN
Note:
1. CA-IS3745 device has no disable state.
2. CA-IS3745 device doesn’t have ENB pin but NC pin instead.
3. VDDI = Input-side VDD
Copyright © 2018, ChipAnalog Incorporated
CA-IS3740, CA-IS3741, CA-IS3742
www.chipanalog.com
7.8 Timing Characteristics
7.8.1 VDDA = VDDB = 5 V ± 10%, TA = -40 to 125°C
DR
PWmin
tPLH, tPHL
PWD
tsk(o)
tsk(pp)
tr
tf
tJIT(PK)
tPHZ
tPLZ
PARAMETER
Data Rate
Minimum Pulse Width
Propagation Delay Time
Pulse Width Distortion |tPLH - tPHL|
Channel-to-channel Output Skew Time1
Part-to-part Skew Time2
Output Signal Rise Time
Output Signal Fall Time
Peak Eye Diagram Jitter
Disable Propagation Delay, High to High Impedance Output
Disable Propagation Delay, Low to High Impedance Output
tPZH
Enable Propagation Delay, High Impedance to High Output
tPZL
Enable Propagation Delay, High Impedance to Low Output
tDO
tie
Default Output Delay Time from Input Power Loss
Time interval error
Preview Version
TEST CONDITIONS
See Figure 8-1
Same-direction channels
See Figure 8-1
See Figure 8-1
CA-IS374xL
CA-IS374xH
CA-IS374xL
CA-IS374xH
See Figure 8-2
See Figure 8-3
216 – 1 PRBS 100Mbps
data
MIN TYP MAX
0
150
5.0
5.0 8.0 13.0
0.2 4.5
0.4 2.5
2.0 4.5
2.5 4.0
2.5 4.0
350
8
12
8
12
6
11
6
8
0.7
11
12
UNIT
Mbps
ns
ns
ns
ns
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
tSU
Start-up Time
15 40
µs
NOTE:
1. tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction
while driving identical loads.
2. tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction
while operating at identical supply voltages, temperature, input signals and loads.
7.8.2 VDDA = VDDB = 3.3 V ± 10%, TA = -40 to 125°C
DR
PWmin
tPLH, tPHL
PWD
tsk(o)
tsk(pp)
tr
tf
tJIT(PK)
tPHZ
tPLZ
PARAMETER
Data Rate
Minimum Pulse Width
Propagation Delay Time
Pulse Width Distortion |tPLH - tPHL|
Channel-to-channel Output Skew Time1
Part-to-part Skew Time2
Output Signal Rise Time
Output Signal Fall Time
Peak Eye Diagram Jitter
Disable Propagation Delay, High to High Impedance Output
Disable Propagation Delay, Low to High Impedance Output
tPZH
Enable Propagation Delay, High Impedance to High Output
tPZL
Enable Propagation Delay, High Impedance to Low Output
tDO
tie
Default Output Delay Time from Input Power Loss
Time interval error
TEST CONDITIONS
See Figure 8-1
Same-direction channels
See Figure 8-1
See Figure 8-1
CA-IS374xL
CA-IS374xH
CA-IS374xL
CA-IS374xH
See Figure 8-2
See Figure 8-3
216 – 1 PRBS 100Mbps
data
MIN TYP MAX
0
150
5.0
5.0 8.0 13.0
0.2 4.5
0.4 2.5
2.0 4.5
2.5 4.0
2.5 4.0
350
8
12
8
12
6
11
6
8
0.7
11
12
UNIT
Mbps
ns
ns
ns
ns
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
tSU
Start-up Time
15 40
µs
NOTE:
1. tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction
while driving identical loads.
2. tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction
while operating at identical supply voltages, temperature, input signals and loads.
Copyright © 2018, ChipAnalog Incorporated
CA-IS3740, CA-IS3741, CA-IS3742, CA-IS3745
Preview Version
7.8.3 VDDA = VDDB = 2.5 V ± 5%, TA = -40 to 125°C
DR
PWmin
tPLH, tPHL
PWD
tsk(o)
tsk(pp)
tr
tf
tJIT(PK)
tPHZ
tPLZ
PARAMETER
Data Rate
Minimum Pulse Width
Propagation Delay Time
Pulse Width Distortion |tPLH - tPHL|
Channel-to-channel Output Skew Time1
Part-to-part Skew Time2
Output Signal Rise Time
Output Signal Fall Time
Peak Eye Diagram Jitter
Disable Propagation Delay, High to High Impedance Output
Disable Propagation Delay, Low to High Impedance Output
tPZH
Enable Propagation Delay, High Impedance to High Output
tPZL
Enable Propagation Delay, High Impedance to Low Output
tDO
tie
Default Output Delay Time from Input Power Loss
Time interval error
www.chipanalog.com
TEST CONDITIONS
See Figure 8-1
Same-direction channels
See Figure 8-1
See Figure 8-1
CA-IS374xL
CA-IS374xH
CA-IS374xL
CA-IS374xH
See Figure 8-2
See Figure 8-3
216 – 1 PRBS 100Mbps
data
MIN TYP MAX
0
150
5.0
5.0 8.0 13.0
0.2 5.0
0.4 2.5
2.0 5.0
2.5 4.0
2.5 4.0
350
8
12
8
12
6
11
6
8
0.7
11
12
UNIT
Mbps
ns
ns
ns
ns
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
tSU
Start-up Time
15 40
µs
NOTE:
1. tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction
while driving identical loads.
2. tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction
while operating at identical supply voltages, temperature, input signals and loads.
Copyright © 2018, ChipAnalog Incorporated
CA-IS3740, CA-IS3741, CA-IS3742
Isolation Barrier
www.chipanalog.com
8 Parameter Measurement Information
IN
VIN1
Preview Version
OUT
VOUT
VIN
50%
tPHL
tPLH
CL2
50Ω
50%
90%
VOUT
50%
50%
10%
tf
tr
NOTE:
1. A square wave generator generate the VIN input signal with the following constraints: waveform frequency ≤ 100kHz, 50%
duty cycle, tr≤3ns, tf≤3ns. Since the waveform generator has an output impedance of Zout = 50Ω, the 50Ω resistor in the
figure is used for matching. There is no need in the actual application.
2. CL is the load capacitance about 15pF together with the instrumentation capacitance. Since the load capacitance influence
the output rising time, it’s a key factor in the timing characteristic measurement.
Figure 8-1 Timing Characteristics Test Circuit and Voltage Waveforms
GNDI
Isolation Barrier
VDDO
IN
VEN1
VEN
VOUT
2V
2V
tPZL
tPLZ
EN
50Ω
Isolation Barrier
IN
OUT
CL2
VEN1
VDDI
VDDO
1kΩ
VOUT
50%
VOL =0.4V
VDDO
OUT
VEN
VOUT
2V
2V
tPZH
tPHZ
EN
CL2
50Ω
1kΩ
VOUT
50%
VOH = VDDO - 0.4V
NOTE:
1. A square wave generator generate the VEN input signal with the following constraints: waveform frequency ≤ 100kHz, 50%
duty cycle, tr≤3ns, tf≤3ns. Since the waveform generator has an output impedance of Zout = 50Ω, the 50Ω resistor in the
figure is used for matching. There is no need in the actual application.
2. CL is the load capacitance about 15pF together with the instrumentation capacitance. Since the load capacitance influence
the output rising time, it’s a key factor in the timing characteristic measurement.
Figure 8-2 Enable/Disable Propagation Delay Time Test Circuit and Waveform
Copyright © 2018, ChipAnalog Incorporated
CA-IS3740, CA-IS3741, CA-IS3742, CA-IS3745
Preview Version
VDDI1
www.chipanalog.com
VDDO
VDDI
VDDO
IN = 0 V for CA-IS374xH
IN = VDDI for CA-IS374xL
IN
Isolation Barrier
2.15V
OUT
0V
VOUT
tDO
Default High for CA-IS374xH
CL2
VOH
VOUT
50%
Default Low for CA-IS374xL
VOL
NOTE:
1. Power Supply Ramp Rate = 10 mV/ns. VDDI should ramp over 2.15V but no higher than 5.5V.
2. CL is the load capacitance about 15pF together with the instrumentation capacitance. Since the load capacitance influence
the output rising time, it’s a key factor in the timing characteristic measurement.
Figure 8-3 Default Output Delay Time Test Circuit and Voltage Waveforms
IN
CBP4
VDDO
Isolation Barrier
VDDI
OUT
VOUT3
CBP4
CL2
GNDA
High
Voltage
Surge
Generator1
GNDB
NOTE:
1. The High Voltage Surge Generator generates repetitive high voltage surges with > 1kV amplitude and 100kV/μs slew rate.
2. CL is the load capacitance about 15pF together with the instrumentation capacitance.
3. Pass-fail criteria: The output must remain stable whenever the high voltage surges come.
4. CBP is the 0.1 ~ 1uF bypass capacitance.
Figure 8-4 Common-Mode Transient Immunity Test Circuit
Copyright © 2018, ChipAnalog Incorporated
CA-IS3740, CA-IS3741, CA-IS3742
www.chipanalog.com
9 Detailed Description
Preview Version
9.1 Theory of Operation
The CA-IS374x family of devices use a simple ON-OFF keying (OOK) modulation scheme to transmit signal across the SiO2
isolation capacitors that provide a robust insulation between two different voltage domain and act as a high frequency signal
path between the input and the output. The transmitter (TX) modulates the input signal onto the carrier frequency, that is, TX
delivers high frequency signal across the isolation barrier in one input state and delivers no signal across the barrier in the other
input state. Then the receiver rebuilds the input signal according to the detected in-band energy. If the ENx pin is low then the
output goes to high impedance state and will be pulled up to VDDO (CA-IS374xH) or pull down to the corresponding GND (CAIS374xL). This simple architecture offers a robust isolated data path and requires no special considerations or initialization at
start-up. The capacitor-based signal path is fully differential to maximize noise immunity, which is also known as common-mode
transient immunity. Advanced circuitry techniques are applied for better EMI introduced by the carrier signal and IO switching.
The capacitively-coupled architecture provides much higher electromagnetic immunity compared to the inductively-coupled
one. And OOK modulation scheme eliminates the missing-pulse error that occurs in the pulse modulation method. A simplified
functional block diagram and conceptual operation waveforms of a single channel is shown in Figure 9-1 and Figure 9-2.
9.2 Functional Block Diagram
Isolation
Barrier
Transmitter (TX)
Receiver (RX)
Schmitt Trigger
Driver
VIN
Modulator
Demodulator
RF Carrier
Generator
EN
Figure 9-1 Functional Block Diagram of a Single Channel
VIN
Signal through
isolation barrier
VOUT
Figure 9-2 Conceptual Operation Waveforms of a Single Channel
Copyright © 2018, ChipAnalog Incorporated
VOUT
CA-IS3740, CA-IS3741, CA-IS3742, CA-IS3745
Preview Version
9.3 Device Operation Modes
Table 9-1 provides the operation modes for the CA-IS374x devices.
www.chipanalog.com
Table 9-1 Operation Mode Table1
VDDI
VDDO
PU
PU
INPUT(Ax/Bx)2
H
L
OUTPUT ENABLE(ENx)3,4
H or Open
H or Open
OUTPUT (Ax/Bx)
H
L
Open
H or Open
Default
X
PU
X
L
Z
PD
PU
X
H or Open
Default
X
PD
X
X
Undetermined
OPERATION
Normal operation mode:
A channel’s output follows the input state
Default output fail-safe mode:
If a channel’s input is left open, its output goes to the
default value (Low for CA-IS374xL and High for CA-IS374xH).
High impedance mode:
If Enable pin is tied to low, the output will be in high-Z mode
Default output fail-safe mode:
If the input side VDD is unpowered, the outputs go in to the
default output fail-safe mode (Low for CA-IS374xL and High
for CA-IS374xH)
If the output side VDD is unpowered, the outputs’ states are
undetermined.5
NOTE:
1. VDDI = Input-side VDD; VDDO = Output-side VDD; PU = Powered up (VCC ≥ 2.375 V); PD = Powered down (VCC ≤ 2.25 V); X = Irrelevant; H = High
level; L = Low level; Z = High Impedance.
2. A strongly driven input signal can weakly power the floating VDD through an internal protection diode and cause undetermined output.
3. It is recommended that the enable inputs be connected to an external logic high or low level when the CA-IS374x is operating in noisy
environments.
4. No Connect (NC) replaces ENA on CA-IS3740/45. No Connect replaces EN2 on the CA-IS3745. No Connects are not internally connected and
can be left floating, tied to VDD, or tied to GND.
5. The outputs are in undetermined state when 2.25V < VDDI, VDDO < 2.375 V.
Table 9-2 provides the Enable input truth table for the CA-IS374x devices.
Table 9-2 Enable Input Truth Table
PART NUMBER
CA-IS3740
CA-IS3741
CA-IS3742
ENA1,2
—
ENB1,2
H
OPERATION
Outputs B1, B2, B3, B4 are enabled and follow the input state.
—
L
Outputs B1, B2, B3, B4 are disabled and in high impedance state.
H
L
X
X
H
L
X
X
—
X
X
H
L
X
X
H
L
—
Output A4 enabled and follows the input state.
Output A4 disabled and in high impedance state.
Outputs B1, B2, B3 are enabled and follow the input state.
Outputs B1, B2, B3 are disabled and in high impedance state.
Outputs A3 and A4 are enabled and follow the input state.
Outputs A3 and A4 are disabled and in high impedance state.
Outputs B1 and B2 are enabled and follow the input state.
Outputs B1 and B2 are disabled and in high impedance state.
Outputs B1, B2, B3, B4 are enabled and follow the input state.
CA-IS3745
NOTE:
1. Enable inputs ENA and ENB can be used for multiplexing, for clock sync, or other output control. ENA, ENB logic operation is summarized for
each isolator product in Table 9-2. These inputs are internally pulled-up to local VDD allowing them to be connected to an external logic level
(high or low) or left floating. To minimize noise coupling, do not connect circuit traces to ENA or ENB if they are left floating. If ENA, ENB are
unused, it is recommended they be connected to an external logic level, especially if the CA-IS374x is operating in a noisy environment.
2. X = Irrelevant; H = High level; L = Low level.
Copyright © 2018, ChipAnalog Incorporated
CA-IS3740, CA-IS3741, CA-IS3742
www.chipanalog.com
Preview Version
10 Application and Implementation
Unlike optocouplers, which need external components to improve performance, provide bias, or limit current, the CA-IS374x
family device CMOS digital isolator needs only two external VDD bypass capacitors (0.1μF to 1 μF) to operate. Its TTL level
compatible input terminals draw only micro amps of leakage current, allowing them to be driven without external buffering
circuits. The output terminals have a characteristic impedance of 50 Ω (rail-to-rail swing) and are available in both forward and
reverse channel configurations. Figure 10-1 shows the typical application of CA-IS3742 device. And the circuit of Figure 10-2 is
typical for most applications of CA-IS37xx series products and is as easy to use as a standard logic gate.
VDD1
0.1uF
VDD2
2mm maximum from VDDA
0.1uF
2mm maximum from VDDB
VDDA
VDDB
IN1
A1
TX
IN2
A2
TX
OUT3
A3
RX
OUT4
A4
RX
ENA
ISOLATION BARRIER
GNDA
GNDB
RX
B1
OUT1
RX
B2
OUT2
TX
B3
IN3
TX
B4
IN4
ENB
GNDA
GNDB
Figure 10-1 Typical Application Circuit of CA-IS3742
VDD1
CA-IS37xx Series Products
VDDA
VDD2
VDDB
0.1uF
0.1uF
IN1
A1
TX
INm-1
Am-1
TX
OUTm
Am
RX
OUTn
An
RX
ISOLATION BARRIER
GNDA
GNDB
B1
RX
Bm-1
TX
Bm
INm
TX
Bn
INn
Figure 10-2 CA-IS37xx Series Digital Isolator Application Schematic
Copyright © 2018, ChipAnalog Incorporated
OUT1
RX
OUTm-1
CA-IS3740, CA-IS3741, CA-IS3742, CA-IS3745
Preview Version
11 Package Information
www.chipanalog.com
11.1 16-Pin Wide Body SOIC Package Outline and Recommended Land Pattern
The figure below illustrates the package details and the recommended land pattern details for the CA-IS374x digital isolator in a
16-pin wide-body SOIC package. The values for the dimensions are shown in millimeters.
10.40
10.20
0.60
1.27
9
16
2.00
7.60
7.40
10.50
10.10
9.30
PIN I ID
1
8
TOP VIEW
RECOMMENDED LAND PATTERN
1.07
0.97
2.35
2.25
2.65
0.43
0.35
1.27BSC
FRONT VIEW
0.30
0.10
0.85
0.55
8°
0°
1.40REF
LEFT-SIDE VIEW
Copyright © 2018, ChipAnalog Incorporated
CA-IS3740, CA-IS3741, CA-IS3742
www.chipanalog.com
Preview Version
11.2 16-Pin Narrow Body SOIC Package Outline
The figure below illustrates the package details and the recommended land pattern details for the CA-IS374x digital isolator in a
16-pin narrow-body SOIC package. The values for the dimensions are shown in millimeters.
10.00
9.80
16
0.60
1.27
9
2.00
4.00
3.80
5.40
6.20
5.80
PIN I ID
1
8
TOP VIEW
RECOMMENDED LAND PATTERN
0.70
0.60
1.50
1.30
0.50
0.25
1.75
0.47
0.39
1.27BSC
0.225
0.10
0.80
0.50
8°
0°
1.05REF
FRONT VIEW
Copyright © 2018, ChipAnalog Incorporated
LEFT-SIDE VIEW
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