GigaDevice Semiconductor Inc.
GD32F130xx
ARM® Cortex®-M3 32-bit MCU
Datasheet
GD32F130xx Datasheet
Table of Contents
Table of Contents ........................................................................................................... 1
List of Figures ................................................................................................................ 3
List of Tables .................................................................................................................. 4
1. General description ................................................................................................. 5
2. Device overview ....................................................................................................... 6
2.1.
Device information ...................................................................................................... 6
2.2.
Block diagram .............................................................................................................. 7
2.3.
Pinouts and pin assignment ....................................................................................... 8
2.4.
Memory map .............................................................................................................. 11
2.5.
Clock tree ................................................................................................................... 13
2.6.
Pin definitions ............................................................................................................ 14
2.6.1.
GD32F130R8 LQFP64 pin definitions .................................................................................. 14
2.6.2.
GD32F130Cx LQFP48 pin definitions .................................................................................. 18
2.6.3.
GD32F130Kx QFN32 pin definitions .................................................................................... 21
2.6.4.
GD32F130Gx QFN28 pin definitions .................................................................................... 24
2.6.5.
GD32F130Fx TSSOP20 pin definitions ................................................................................ 26
2.6.6.
GD32F130xx pin alternate functions .................................................................................... 28
3. Functional description .......................................................................................... 31
3.1.
ARM® Cortex®-M3 core .............................................................................................. 31
3.2.
On-chip memory ........................................................................................................ 31
3.3.
Clock, reset and supply management ...................................................................... 31
3.4.
Boot modes ................................................................................................................ 32
3.5.
Power saving modes ................................................................................................. 32
3.6.
Analog to digital converter (ADC) ............................................................................ 33
3.7.
DMA ............................................................................................................................ 33
3.8.
General-purpose inputs/outputs (GPIOs) ................................................................ 34
3.9.
Timers and PWM generation ..................................................................................... 34
3.10.
Real time clock (RTC) ............................................................................................ 35
3.11.
Inter-integrated circuit (I2C) .................................................................................. 36
3.12.
Serial peripheral interface (SPI) ............................................................................ 36
3.13.
Universal synchronous asynchronous receiver transmitter (USART) ............... 36
1
GD32F130xx Datasheet
3.14.
Debug mode ........................................................................................................... 37
3.15.
Package and operation temperature ..................................................................... 37
4. Electrical characteristics ....................................................................................... 38
4.1.
Absolute maximum ratings ....................................................................................... 38
4.2.
Recommended DC characteristics ........................................................................... 38
4.3.
Power consumption .................................................................................................. 39
4.4.
EMC characteristics .................................................................................................. 40
4.5.
Power supply supervisor characteristics ................................................................ 40
4.6.
Electrical sensitivity .................................................................................................. 41
4.7.
External clock characteristics .................................................................................. 41
4.8.
Internal clock characteristics ................................................................................... 42
4.9.
PLL characteristics.................................................................................................... 43
4.10.
Memory characteristics ......................................................................................... 43
4.11.
GPIO characteristics .............................................................................................. 43
4.12.
ADC characteristics ............................................................................................... 44
4.13.
SPI characteristics ................................................................................................. 44
4.14.
I2C characteristics ................................................................................................. 45
5. Package information.............................................................................................. 46
5.1.
TSSOP package outline dimensions ........................................................................ 46
5.2.
QFN package outline dimensions ............................................................................ 47
5.3.
LQFP package outline dimensions .......................................................................... 49
6. Ordering information ............................................................................................. 51
7. Revision history ..................................................................................................... 52
2
GD32F130xx Datasheet
List of Figures
Figure 2-1. GD32F130xx block diagram ............................................................................................................... 7
Figure 2-2. GD32F130Rx LQFP64 pinouts ........................................................................................................... 8
Figure 2-3. GD32F130Cx LQFP48 pinouts ........................................................................................................... 8
Figure 2-4. GD32F130Kx QFN32 pinouts ............................................................................................................. 9
Figure 2-5. GD32F130Gx QFN28 pinouts............................................................................................................. 9
Figure 2-6. GD32F130Fx TSSOP20 pinouts ...................................................................................................... 10
Figure 2-7. GD32F130xx clock tree ..................................................................................................................... 13
Figure 5-1. TSSOP package outline .................................................................................................................... 46
Figure 5-2. QFN package outline ......................................................................................................................... 47
Figure 5-3. LQFP package outline ....................................................................................................................... 49
3
GD32F130xx Datasheet
List of Tables
Table 2-1. GD32F130xx devices features and peripheral list ......................................................................... 6
Table 2-2. GD32F130xx memory map ................................................................................................................. 11
Table 2-3. GD32F130R8 LQFP64 pin definitions .............................................................................................. 14
Table 2-4. GD32F130Cx LQFP48 pin definitions .............................................................................................. 18
Table 2-5. GD32F130Kx QFN32 pin definitions ................................................................................................ 21
Table 2-6. GD32F130Gx QFN28 pin definitions ................................................................................................ 24
Table 2-7. GD32F130Fx TSSOP20 pin definitions ........................................................................................... 26
Table 2-8. Port A alternate functions summary ................................................................................................ 28
Table 2-9. Port B alternate functions summary ............................................................................................... 29
Table 2-10. Port C & D & F alternate functions summary .............................................................................. 30
Table 4-1. Absolute maximum ratings ................................................................................................................ 38
Table 4-2. DC operating conditions..................................................................................................................... 38
Table 4-3. Power consumption characteristics ................................................................................................ 39
Table 4-4. EMS characteristics ............................................................................................................................. 40
Table 4-5. EMI characteristics .............................................................................................................................. 40
Table 4-6. Power supply supervisor characteristics ...................................................................................... 40
Table 4-7. ESD characteristics ............................................................................................................................. 41
Table 4-8. Static latch-up characteristics .......................................................................................................... 41
Table 4-9. High speed crystal oscillator (HXTAL) generated from a crystal/ceramic characteristics 41
Table 4-10. Low speed crystal oscillator (LXTAL) generated from a crystal/ceramic characteristics
...................................................................................................................................................................................... 42
Table 4-11. Internal 8 MHz RC oscillator (IRC8M) characteristics ............................................................... 42
Table 4-12. Internal 40KHz RC oscillator (IRC40K) characteristics ............................................................ 42
Table 4-13. PLL characteristics ............................................................................................................................ 43
Table 4-14. Flash memory characteristics ........................................................................................................ 43
Table 4-15. I/O port characteristics ..................................................................................................................... 43
Table 4-16. ADC characteristics ........................................................................................................................... 44
Table 4-17. Standard SPI characteristics ........................................................................................................... 44
Table 4-18. I2C characteristics ............................................................................................................................. 45
Table 5-1. TSSOP20 package dimensions ......................................................................................................... 46
Table 5-2. QFN package dimensions .................................................................................................................. 48
Table 5-3. LQFP package dimensions ................................................................................................................ 50
Table 6-1. Part ordering code for GD32F130xx devices ................................................................................ 51
Table 7-1. Revision history .................................................................................................................................... 52
4
GD32F130xx Datasheet
1.
General description
The GD32F130xx device belongs to the value line of GD32 MCU family. It is a 32-bit generalpurpose microcontroller based on the high performance ARM® Cortex®-M3 RISC core with
best ratio in terms of processing power, reduced power consumption and peripheral set. The
Cortex®-M3 is a next generation processor core which is tightly coupled with a Nested
Vectored Interrupt Controller (NVIC), SysTick timer and advanced debug support.
The GD32F130xx device incorporates the ARM® Cortex®-M3 32-bit processor core operating
at 72 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It
provides up to 64 KB on-chip Flash memory and up to 8 KB SRAM memory. An extensive
range of enhanced I/Os and peripherals connected to two APB buses. The devices offer one
12-bit ADC, up to five general 16-bit timers, a general 32-bit timer, a PWM advanced timer,
as well as standard and advanced communication interfaces: up to two SPIs, two I2Cs and
two USARTs.
The device operates from a 2.6 to 3.6 V power supply and available in –40 to +85 °C
temperature range. Several power saving modes provide the flexibility for maximum
optimization between wakeup latency and power consumption, an especially important
consideration in low power applications.
The above features make the GD32F130xx devices suitable for a wide range of applications,
especially in areas such as industrial control, motor drives, user interface, power monitor and
alarm systems, consumer and handheld equipment, gaming and GPS, E-bike and so on.
5
GD32F130xx Datasheet
2.
Device overview
2.1.
Device information
Table 2-1. GD32F130xx devices features and peripheral list
GD32F130xx
Part Number
F4
F6
F8
G4
G6
G8
K4
K6
K8
C4
C6
C8
R8
Flash (KB)
16
32
64
16
32
64
16
32
64
16
32
64
64
SRAM (KB)
4
4
8
4
4
8
4
4
8
4
4
8
8
1
1
1
1
1
1
1
1
1
1
1
1
1
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
4
4
4
4
4
5
4
4
5
4
4
5
5
(2,13-16)
(2,13-16)
General
timer(32bit)
General
timer(16-
Timers
(2,13,15-16) (2,13,15-16) (2,13,15-16) (2,13,15-16) (2,13,15-16)
(2,13-16)
(2,13,15-16) (2,13,15-16)
(2,13-16)
(2,13,15-16) (2,13,15-16)
bit)
Advanced
1
1
1
1
1
1
1
1
1
1
1
1
1
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
SysTick
1
1
1
1
1
1
1
1
1
1
1
1
1
Watchdog
2
2
2
2
2
2
2
2
2
2
2
2
2
RTC
1
1
1
1
1
1
1
1
1
1
1
1
1
timer(16-
Connectivity
bit)
1
2
2
1
2
2
1
2
2
1
2
2
2
(0)
(0-1)
(0-1)
(0)
(0-1)
(0-1)
(0)
(0-1)
(0-1)
(0)
(0-1)
(0-1)
(0-1)
1
1
2
1
1
2
1
1
2
1
1
2
2
(0)
(0)
(0-1)
(0)
(0)
(0-1)
(0)
(0)
(0-1)
(0)
(0)
(0-1)
(0-1)
1
1
2
1
1
2
1
1
2
1
1
2
2
(0)
(0)
(0-1)
(0)
(0)
(0-1)
(0)
(0)
(0-1)
(0)
(0)
(0-1)
(0-1)
GPIO
15
15
15
23
23
23
27
27
27
39
39
39
55
EXTI
16
16
16
16
16
16
16
16
16
16
16
16
16
1
1
1
1
1
1
1
1
1
1
1
1
1
9
9
9
10
10
10
10
10
10
10
10
10
16
3
3
3
3
3
3
3
3
3
3
3
3
3
USART
I2C
SPI
ADC
Units
Channels
(External)
Channels
(Internal)
Package
TSSOP20
QFN28
QFN32
LQFP48
LQFP
64
6
GD32F130xx Datasheet
2.2.
Block diagram
Figure 2-1. GD32F130xx block diagram
LDO
1.2V
TPIU
SW
AHB Matrix
NVIC
ICode DCode System
ARM Cortex-M3
Processor
Fmax: 72MHz
AHB2: Fma x = 72MHz
IBus
GPIO Ports
A, B, C, D, F
SRAM
Controller
SRAM
Flash
Memory
Controller
Flash
Memory
POR/PDR
LVD
PLL
Fmax: 72MHz
HXTAL
4-32MHz
DBus
GP DMA
7chs
AHB1: Fma x = 72MHz
AHB to APB
Bridge 2
CRC
AHB to APB
Bridge 1
IRC8M
8MHz
RST/CLK
Controller
IRC14M
14MHz
IRC40K
40KHz
Powered by LDO (1.2V)
Powered by V DD/VDDA
PMU
EXTI
FWDGT
12-bit
SAR ADC
ADC
WWDGT
RTC
USART0
I2C0
SPI0
TIMER14
TIMER15
TIMER16
APB1: Fmax = 72MHz
TIMER0
APB2: Fmax = 72MHz
SYSCFG
I2C1
USART1
SPI1
TIMER1
TIMER2
TIMER13
7
GD32F130xx Datasheet
2.3.
Pinouts and pin assignment
Figure 2-2. GD32F130Rx LQFP64 pinouts
PA14
PA15
PC10
PC11
PD2
PC12
PB3
PB4
PB5
PB6
PB7
BOOT0
PB8
PB9
VSS
VDD
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VBAT
1
48
PC13
2
47
PF6
PC14-OSC32IN
3
46
PA13
PC15-OSC32OUT
PF0-OSCIN
4
45
PA12
5
44
PA11
PF1-OSCOUT
6
43
PA10
NRST
7
42
PA9
PC0
8
PC1
9
PC2
PC3
VSSA
GigaDevice GD32F130Rx
LQFP64
PF7
41
PA8
40
PC9
10
39
PC8
11
38
PC7
12
37
PC6
VDDA
13
36
PB15
PA0
14
35
PB14
PA1
15
34
PB13
PA2
16
33
PB12
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VDD
PB3
VSS
PB10
PB11
PB2
PB4
PB1
PC5
PB0
PC4
PA7
PA6
PA5
PA4
PF5
PF4
PA3
Figure 2-3. GD32F130Cx LQFP48 pinouts
PA14
PA15
PB5
PB6
PB7
BOOT0
PB8
VSS
PB9
VDD
48 47 46 45 44 43 42 41 40 39 38 37
VBAT
1
36
PF7
PC13
2
35
PF6
PC14-OSC32IN
3
34
PA13
PC15-OSC32OUT
PF0-OSCIN
4
33
PA12
5
32
PA11
PF1-OSCOUT
NRST
VSSA
6
31
PA10
30
PA9
8
29
VDDA
9
28
PA8
PB15
PA0
10
27
PB14
PA1
PA2
11
26
PB13
12
25
PB12
GigaDevice GD32F130Cx
LQFP48
7
13 14 15 16 17 18 19 20 21 22 23 24
VDD
VSS
PB11
PB10
PB2
PB1
PA7
PB0
PA6
PA5
PA4
PA3
8
GD32F130xx Datasheet
Figure 2-4. GD32F130Kx QFN32 pinouts
PA15
PB3
PB4
PB5
PB6
PB7
BOOT0
PB8
VDD
1
32 31 30 29 28 27 26 25
24
PA14
OSCIN/PF0
2
23
PA13
OSCOUT/PF1
NRST
3
22
PA12
21
PA11
VDDA
PA0
5
20
PA10
19
PA9
18
PA8
17
VDD
GigaDevice
GD32F130Kx
QFN32
4
6
PA1
7
PA2
8
VSS, VSSA
9 10 11 12 13 14 15 16
PB2
PB1
PB0
PA7
PA6
PA5
PA4
PA3
Figure 2-5. GD32F130Gx QFN28 pinouts
PA14
PA15
PB3
PB4
PB5
PB6
PB7
28 27 26 25 24 23 22
1
21
2
20
PA13
OSCOUT/PF1
NRST
3
19
PA9
18
PA8
VDDA
PA0
5
17
VDD
16
PA1
7
VSS
PB1
BOOT0
OSCIN/PF0
GigaDevice
GD32F130Gx
QFN28
4
6
8 9 10 11 12 13 14
15
PA10
PB0
PA7
PA6
PA5
PA4
PA3
PA2
9
GD32F130xx Datasheet
Figure 2-6. GD32F130Fx TSSOP20 pinouts
1
20
PA14
OSCIN/PF0
2
19
PA13
OSCOUT/PF1
3
18
PA10
4
17
PA9
BOOT0
NRST
VDDA
5
PA0
6
GigaDevice
16
GD32F130Fx
TSSOP20 15
PA1
7
14
PB1
PA2
8
13
PA7
PA3
9
12
PA6
PA4
10
11
PA5
VDD
Vss
10
GD32F130xx Datasheet
2.4.
Memory map
Table 2-2. GD32F130xx memory map
Pre-defined
Address
Peripherals
0xE000 0000 - 0xE00F FFFF
Cortex-M3 internal peripherals
External Device
0xA000 0000 - 0xDFFF FFFF
Reserved
External RAM
0x6000 0000 - 0x9FFF FFFF
Reserved
0x5000 0000 - 0x5FFF FFFF
Reserved
0x4800 1800 - 0x4FFF FFFF
Reserved
0x4800 1400 - 0x4800 17FF
GPIOF
0x4800 1000 - 0x4800 13FF
Reserved
0x4800 0C00 - 0x4800 0FFF
GPIOD
0x4800 0800 - 0x4800 0BFF
GPIOC
0x4800 0400 - 0x4800 07FF
GPIOB
0x4800 0000 - 0x4800 03FF
GPIOA
0x4002 4400 - 0x47FF FFFF
Reserved
0x4002 4000 - 0x4002 43FF
Reserved
0x4002 3400 - 0x4002 3FFF
Reserved
0x4002 3000 - 0x4002 33FF
CRC
0x4002 2400 - 0x4002 2FFF
Reserved
0x4002 2000 - 0x4002 23FF
FMC
0x4002 1400 - 0x4002 1FFF
Reserved
0x4002 1000 - 0x4002 13FF
RCU
0x4002 0400 - 0x4002 0FFF
Reserved
0x4002 0000 - 0x4002 03FF
DMA
0x4001 4C00 - 0x4001 FFFF
Reserved
0x4001 4800 - 0x4001 4BFF
TIMER16
0x4001 4400 - 0x4001 47FF
TIMER15
0x4001 4000 - 0x4001 43FF
TIMER14
0x4001 3C00 - 0x4001 3FFF
Reserved
0x4001 3800 - 0x4001 3BFF
USART0
0x4001 3400 - 0x4001 37FF
Reserved
0x4001 3000 - 0x4001 33FF
SPI0
0x4001 2C00 - 0x4001 2FFF
TIMER0
0x4001 2800 - 0x4001 2BFF
Reserved
0x4001 2400 - 0x4001 27FF
ADC
0x4001 0800 - 0x4001 23FF
Reserved
0x4001 0400 - 0x4001 07FF
EXTI
0x4001 0000 - 0x4001 03FF
SYSCFG
0x4000 C400 - 0x4000 FFFF
Reserved
0x4000 C000 - 0x4000 C3FF
Reserved
Regions
Bus
AHB1
AHB2
AHB1
Peripherals
APB2
APB1
11
GD32F130xx Datasheet
Pre-defined
Regions
SRAM
Code
Bus
Address
Peripherals
0x4000 7C00 - 0x4000 BFFF
Reserved
0x4000 7800 - 0x4000 7BFF
Reserved
0x4000 7400 - 0x4000 77FF
Reserved
0x4000 7000 - 0x4000 73FF
PMU
0x4000 6400 - 0x4000 6FFF
Reserved
0x4000 6000 - 0x4000 63FF
Reserved
0x4000 5C00 - 0x4000 5FFF
Reserved
0x4000 5800 - 0x4000 5BFF
I2C1
0x4000 5400 - 0x4000 57FF
I2C0
0x4000 4800 - 0x4000 53FF
Reserved
0x4000 4400 - 0x4000 47FF
USART1
0x4000 4000 - 0x4000 43FF
Reserved
0x4000 3C00 - 0x4000 3FFF
Reserved
0x4000 3800 - 0x4000 3BFF
SPI1
0x4000 3400 - 0x4000 37FF
Reserved
0x4000 3000 - 0x4000 33FF
FWDGT
0x4000 2C00 - 0x4000 2FFF
WWDGT
0x4000 2800 - 0x4000 2BFF
RTC
0x4000 2400 - 0x4000 27FF
Reserved
0x4000 2000 - 0x4000 23FF
TIMER13
0x4000 1400 - 0x4000 1FFF
Reserved
0x4000 1000 - 0x4000 13FF
Reserved
0x4000 0800 - 0x4000 0FFF
Reserved
0x4000 0400 - 0x4000 07FF
TIMER2
0x4000 0000 - 0x4000 03FF
TIMER1
0x2000 2000 - 0x3FFF FFFF
Reserved
0x2000 0000 - 0x2000 1FFF
SRAM
0x1FFF F810 - 0x1FFF FFFF
Reserved
0x1FFF F800 - 0x1FFF F80F
Option bytes
0x1FFF EC00 - 0x1FFF F7FF
System memory
0x0801 0000 - 0x1FFF EBFF
Reserved
0x0800 0000 - 0x0800 FFFF
Main Flash memory
0x0000 0000 - 0x07FF FFFF
Aliased to Flash or system memory
12
GD32F130xx Datasheet
2.5.
Clock tree
Figure 2-7. GD32F130xx clock tree
CK_FMC
SCS[1:0]
FMC enable
(by hardware)
(to FMC)
HCLK
CK_IRC8M
00
8 MHz
IRC8M
/2
0
PLL
AHB enable
CK_PLL
CK_SYS
10
1
72 MHz max
AHB
Prescaler
÷(1,2...512)
(to AHB bus,Cortex-M3,SRAM,DMA)
CK_CST
CK_AHB
÷8
72 MHz max
(to Cortex-M3 SysTick)
FCLK
HXTALPR
EDV
4-32 MHz
HXTAL
PLLSEL
01
PLLEN
(free running clock)
Clock
Monitor
÷1,2.
..16
TIMER1,2,13
if(APB1
prescale
=1)x1
else x 2
TIMERx
enable
APB1
Prescaler
÷(1,2,4,8,16)
72 MHz max
CK_TIMERx
to TIMER1,2,13
CK_HXTAL
/32
CK_APB1
PCLK1
to APB1 peripherals
11
Peripheral enable
CK_RTC
32.768 KHz
LXTAL
01
(to RTC)
10
RTCSRC[1:0]
CK_FWDGT
40 KHz
IRC40K
(to FWDGT)
TIMER0,14,1
5,16
if(APB2
prescale
=1)x1
else x 2
TIMERx
enable
APB2
Prescaler
÷(1,2,4,8,16)
72 MHz max
CK_TIMERx
to TIMER0,14,15,16
CK_APB2
PCLK2
to APB2 peripherals
Peripheral enable
0
CK_IRC14M
CK_IRC40K
CK_OUT
÷1,2,4...128
ADC
Prescaler
÷(2,4,6,8)
CK_ LXTAL
1
CK_ADC to ADC
0
14 MHz max
CK_SYS
ADCSEL
CK_IRC8M
CK_HXTAL
CKOUTDIV
*1,2
CK_PLL
14 MHz
IRC14M
CK_IRC8M
11
CK_LXTAL
10
CK_SYS
01
CK_USART0
to USART0
00
Legend:
HXTAL: High speed crystal oscillator
LXTAL: Low speed crystal oscillator
IRC8M: Internal 8M RC oscillators
IRC40K: Internal 40K RC oscillator
IRC14M: Internal 14M RC oscillators
13
GD32F130xx Datasheet
2.6.
Pin definitions
2.6.1.
GD32F130R8 LQFP64 pin definitions
Table 2-3. GD32F130R8 LQFP64 pin definitions
Pin
I/O
Pin Name
Pins
VBAT
1
P
2
I/O
3
I/O
4
I/O
5
I/O
5VT
6
I/O
5VT
7
I/O
Default: VBAT
PC13TAMPER-
Default: PC13
Additional: RTC_TAMP0, RTC_TS, RTC_OUT, WKUP1
RTC
PC14OSC32IN
Default: PC14
Additional: OSC32IN
PC15OSC32OU
Default: PC15
Additional: OSC32OUT
T
PF0OSCIN
PF1OSCOUT
NRST
Functions description
Type(1) Level(2)
Default: PF0
Additional: OSCIN
Default: PF1
Additional: OSCOUT
Default: NRST
Default: PC0
PC0
8
I/O
Alternate: EVENTOUT
Additional: ADC_IN10
Default: PC1
PC1
9
I/O
Alternate: EVENTOUT
Additional: ADC_IN11
Default: PC2
PC2
10
I/O
Alternate: EVENTOUT
Additional: ADC_IN12
Default: PC3
PC3
11
I/O
Alternate: EVENTOUT
Additional: ADC_IN13
VSSA
12
P
Default: VSSA
VDDA
13
P
Default: VDDA
Default: PA0
PA0-WKUP
14
I/O
Alternate: USART1_CTS, TIMER1_CH0, TIMER1_ETI,
I2C1_SCL
Additional: ADC_IN0, RTC_TAMP1, WKUP0
PA1
15
I/O
Default: PA1
Alternate: USART1_RTS, TIMER1_CH1, I2C1_SDA,
14
GD32F130xx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
EVENTOUT
Additional: ADC_IN1
Default: PA2
PA2
16
Alternate: USART1_TX, TIMER1_CH2, TIMER14_CH0 ,
I/O
Additional: ADC_IN2
Default: PA3
PA3
17
Alternate: USART1_RX, TIMER1_CH3, TIMER14_CH1
I/O
Additional: ADC_IN3
PF4
18
I/O
5VT
PF5
19
I/O
5VT
Default: PF4
Alternate: SPI1_NSS, EVENTOUT
Default: PF5
Alternate: EVENTOUT
Default: PA4
PA4
20
Alternate: SPI0_NSS, USART1_CK, TIMER13_CH0,
I/O
SPI1_NSS
Additional: ADC_IN4
Default: PA5
PA5
21
Alternate: SPI0_SCK, TIMER1_CH0, TIMER1_ETI
I/O
Additional: ADC_IN5
Default: PA6
PA6
22
Alternate: SPI0_MISO, TIMER2_CH0, TIMER0_BRKIN,
I/O
TIMER15_CH0, EVENTOUT
Additional: ADC_IN6
Default: PA7
PA7
23
Alternate: SPI0_MOSI, TIMER2_CH1, TIMER13_CH0,
I/O
TIMER0_CH0_ON, TIMER16_CH0, EVENTOUT
Additional: ADC_IN7
Default: PC4
PC4
24
Alternate: EVENTOUT
I/O
Additional: ADC_IN14
PC5
25
Default: PC5
I/O
Additional: ADC_IN15
Default: PB0
PB0
26
Alternate: TIMER2_CH2, TIMER0_CH1_ON, USART1_RX,
I/O
EVENTOUT
Additional: ADC_IN8
Default: PB1
PB1
27
Alternate: TIMER2_CH3, TIMER13_CH0, TIMER0_CH2_ON,
I/O
SPI1_SCK
Additional: ADC_IN9
PB2
28
I/O
5VT
PB10
29
I/O
5VT
Default: PB2
Default: PB10
Alternate: I2C1_SCL, TIMER1_CH2
15
GD32F130xx Datasheet
Pin
I/O
Type(1)
Level(2)
30
I/O
5VT
VSS
31
P
Default: VSS
VDD
32
P
Default: VDD
Pin Name
Pins
PB11
Functions description
Default: PB11
Alternate: I2C1_SDA, TIMER1_CH3, EVENTOUT
Default: PB12
PB12
33
I/O
5VT
Alternate: SPI1_NSS, TIMER0_BRKIN, I2C1_SMBA,
EVENTOUT
PB13
34
I/O
5VT
PB14
35
I/O
5VT
Default: PB13
Alternate: SPI1_SCK, TIMER0_CH0_ON
Default: PB14
Alternate: SPI1_MISO, TIMER0_CH1_ON, TIMER14_CH0
Default: PB15
Alternate: SPI1_MOSI, TIMER0_CH2_ON,
PB15
36
I/O
5VT
TIMER14_CH0_ON, TIMER14_CH1
Additional: RTC_REFIN
PC6
37
I/O
5VT
PC7
38
I/O
5VT
PC8
39
I/O
5VT
PC9
40
I/O
5VT
PA8
41
I/O
5VT
Default: PC6
Alternate: TIMER2_CH0
Default: PC7
Alternate: TIMER2_CH1
Default: PC8
Alternate: TIMER2_CH2
Default: PC9
Alternate: TIMER2_CH3
Default: PA8
Alternate: USART0_CK, TIMER0_CH0, CK_OUT,
USART1_TX, EVENTOUT
Default: PA9
PA9
42
I/O
5VT
Alternate: USART0_TX, TIMER0_CH1, TIMER14_BRKIN,
I2C0_SCL
Default: PA10
PA10
43
I/O
5VT
Alternate: USART0_RX, TIMER0_CH2, TIMER16_BRKIN,
I2C0_SDA
Default: PA11
PA11
44
I/O
5VT
PA12
45
I/O
5VT
PA13
46
I/O
5VT
PF6
47
I/O
5VT
Default: I2C0_SCL
PF7
48
I/O
5VT
Default: I2C0_SDA
PA14
49
I/O
5VT
Alternate: USART0_CTS, TIMER0_CH3, EVENTOUT
Default: PA12
Alternate: USART0_RTS, TIMER0_ETI, EVENTOUT
Default: PA13
Alternate: IFRP_OUT, SWDIO, SPI1_MISO
Default: PA14
Alternate: USART1_TX, SWCLK, SPI1_MOSI
16
GD32F130xx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
Default: PA15
PA15
50
I/O
5VT
Alternate: SPI0_NSS, USART1_RX, TIMER1_CH0,
TIMER1_ETI, SPI1_NSS, EVENTOUT
PC10
51
I/O
5VT
Default: PC10
PC11
52
I/O
5VT
Default: PC11
PC12
53
I/O
5VT
Default: PC12
PD2
54
I/O
5VT
PB3
55
I/O
5VT
PB4
56
I/O
5VT
PB5
57
I/O
5VT
Default: PD2
Alternate: TIMER2_ETI
Default: PB3
Alternate: SPI0_SCK, TIMER1_CH1, EVENTOUT
Default: PB4
Alternate: SPI0_MISO, TIMER2_CH0, EVENTOUT
Default: PB5
Alternate: SPI0_MOSI, I2C0_SMBA, TIMER15_BRKIN,
TIMER2_CH1
PB6
58
I/O
5VT
PB7
59
I/O
5VT
BOOT0
60
I
PB8
61
I/O
5VT
PB9
62
I/O
5VT
Default: PB6
Alternate: I2C0_SCL, USART0_TX, TIMER15_CH0_ON
Default: PB7
Alternate: I2C0_SDA, USART0_RX, TIMER16_CH0_ON
Default: BOOT0
Default: PB8
Alternate: I2C0_SCL, TIMER15_CH0
Default: PB9
Alternate: I2C0_SDA, IFRP_OUT, TIMER16_CH0,
EVENTOUT
VSS
63
P
Default: VSS
VDD
64
P
Default: VDD
Notes:
(1) Type: I = input, O = output, P = power.
(2) I/O Level: 5VT = 5 V tolerant.
17
GD32F130xx Datasheet
2.6.2.
GD32F130Cx LQFP48 pin definitions
Table 2-4. GD32F130Cx LQFP48 pin definitions
Pin
I/O
Pin Name
Pins
VBAT
1
P
2
I/O
3
I/O
4
I/O
5
I/O
5VT
6
I/O
5VT
NRST
7
I/O
VSSA
8
P
Default: VSSA
VDDA
9
P
Default: VDDA
Default: VBAT
PC13TAMPER-
Functions description
Type(1) Level(2)
Default: PC13
Additional: RTC_TAMP0, RTC_TS, RTC_OUT, WKUP1
RTC
PC14OSC32IN
PC15OSC32OUT
PF0-OSCIN
PF1OSCOUT
Default: PC14
Additional: OSC32IN
Default: PC15
Additional: OSC32OUT
Default: PF0
Additional: OSCIN
Default: PF1
Additional: OSCOUT
Default: NRST
Default: PA0
PA0-WKUP
10
I/O
Alternate: USART0_CTS(3), USART1_CTS(4), TIMER1_CH0,
TIMER1_ETI, I2C1_SCL(5)
Additional: ADC_IN0, RTC_TAMP1, WKUP0
Default: PA1
PA1
11
I/O
Alternate: USART0_RTS(3), USART1_RTS(4), TIMER1_CH1,
I2C1_SDA(5), EVENTOUT
Additional: ADC_IN1
Default: PA2
PA2
12
I/O
Alternate: USART0_TX(3), USART1_TX(4), TIMER1_CH2,
TIMER14_CH0
Additional: ADC_IN2
Default: PA3
PA3
13
I/O
Alternate: USART0_RX(3), USART1_RX(4), TIMER1_CH3,
TIMER14_CH1
Additional: ADC_IN3
Default: PA4
PA4
14
I/O
Alternate: SPI0_NSS, USART0_CK(3), USART1_CK(4),
TIMER13_CH0, SPI1_NSS(5)
Additional: ADC_IN4
Default: PA5
PA5
15
I/O
Alternate: SPI0_SCK, TIMER1_CH0, TIMER1_ETI
Additional: ADC_IN5
18
GD32F130xx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
Default: PA6
PA6
16
Alternate: SPI0_MISO, TIMER2_CH0, TIMER0_BRKIN,
I/O
TIMER15_CH0, EVENTOUT
Additional: ADC_IN6
Default: PA7
PA7
17
Alternate: SPI0_MOSI, TIMER2_CH1, TIMER13_CH0,
I/O
TIMER0_CH0_ON, TIMER16_CH0, EVENTOUT
Additional: ADC_IN7
Default: PB0
PB0
18
Alternate: TIMER2_CH2, TIMER0_CH1_ON, USART1_RX(4),
I/O
EVENTOUT
Additional: ADC_IN8
Default: PB1
PB1
19
Alternate: TIMER2_CH3, TIMER13_CH0, TIMER0_CH2_ON,
I/O
SPI1_SCK(5)
Additional: ADC_IN9
Default: PB2
PB2
20
I/O
5VT
PB10
21
I/O
5VT
PB11
22
I/O
5VT
VSS
23
P
Default: VSS
VDD
24
P
Default: VDD
Default: PB10
Alternate: I2C1_SCL(5), TIMER1_CH2
Default: PB11
Alternate: I2C1_SDA(5), TIMER1_CH3, EVENTOUT
Default: PB12
PB12
25
I/O
5VT
Alternate: SPI0_NSS(3), SPI1_NSS(5), TIMER0_BRKIN,
I2C1_SMBA(5), EVENTOUT
PB13
26
I/O
5VT
Default: PB13
Alternate: SPI0_SCK(3), SPI1_SCK(5), TIMER0_CH0_ON
Default: PB14
PB14
27
I/O
5VT
Alternate: SPI0_MISO(3), SPI1_MISO(5), TIMER0_CH1_ON,
TIMER14_CH0
Default: PB15
Alternate: SPI0_MOSI(3), SPI1_MOSI(5), TIMER0_CH2_ON,
PB15
28
I/O
5VT
TIMER14_CH0_ON, TIMER14_CH1
Additional: RTC_REFIN
Default: PA8
PA8
29
I/O
5VT
Alternate: USART0_CK, TIMER0_CH0, CK_OUT,
USART1_TX(4), EVENTOUT
Default: PA9
PA9
30
I/O
5VT
Alternate: USART0_TX, TIMER0_CH1, TIMER14_BRKIN,
I2C0_SCL
PA10
31
I/O
5VT
Default: PA10
19
GD32F130xx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
Alternate: USART0_RX, TIMER0_CH2, TIMER16_BRKIN,
I2C0_SDA
Default: PA11
PA11
32
I/O
5VT
PA12
33
I/O
5VT
PA13
34
I/O
5VT
PF6
35
I/O
5VT
Default: I2C0_SCL
PF7
36
I/O
5VT
Default: I2C0_SDA
Alternate: USART0_CTS, TIMER0_CH3, EVENTOUT
Default: PA12
Alternate: USART0_RTS, TIMER0_ETI, EVENTOUT
Default: PA13
Alternate: IFRP_OUT, SWDIO, SPI1_MISO(5)
Default: PA14
PA14
37
I/O
5VT
Alternate: USART0_TX(3), USART1_TX(4), SWCLK,
SPI1_MOSI(5)
Default: PA15
PA15
38
I/O
5VT
Alternate: SPI0_NSS, USART0_RX(3), USART1_RX(4),
TIMER1_CH0, TIMER1_ETI, SPI1_NSS(5), EVENTOUT
PB3
39
I/O
5VT
PB4
40
I/O
5VT
PB5
41
I/O
5VT
Default: PB3
Alternate: SPI0_SCK, TIMER1_CH1, EVENTOUT
Default: PB4
Alternate: SPI0_MISO, TIMER2_CH0, EVENTOUT
Default: PB5
Alternate: SPI0_MOSI, I2C0_SMBA, TIMER15_BRKIN,
TIMER2_CH1
PB6
42
I/O
5VT
PB7
43
I/O
5VT
BOOT0
44
I
PB8
45
I/O
Default: PB6
Alternate: I2C0_SCL, USART0_TX, TIMER15_CH0_ON
Default: PB7
Alternate: I2C0_SDA, USART0_RX, TIMER16_CH0_ON
Default: BOOT0
5VT
Default: PB8
Alternate: I2C0_SCL, TIMER15_CH0,
Default: PB9
PB9
46
I/O
5VT
Alternate: I2C0_SDA, IFRP_OUT, TIMER16_CH0,
EVENTOUT
VSS
47
P
Default: VSS
VDD
48
P
Default: VDD
Notes:
(1) Type: I = input, O = output, P = power.
(2) I/O Level: 5VT = 5 V tolerant.
(3) Functions are available on GD32F330C4 devices only.
(4) Functions are available on GD32F330C8/6 devices.
(5) Functions are available on GD32F330C8 devices.
20
GD32F130xx Datasheet
2.6.3.
GD32F130Kx QFN32 pin definitions
Table 2-5. GD32F130Kx QFN32 pin definitions
Pin
I/O
Pin Name
Pins
VDD
1
P
2
I/O
5VT
3
I/O
5VT
NRST
4
I/O
VDDA
5
P
PF0OSCIN
PF1OSCOUT
Functions description
Type(1) Level(2)
Default: VDD
Default: PF0
Additional: OSCIN
Default: PF1
Additional: OSCOUT
Default: NRST
Default: VDDA
Default: PA0
PA0-WKUP
6
I/O
Alternate: USART0_CTS(3), USART1_CTS(4), TIMER1_CH0,
TIMER1_ETI, I2C1_SCL(5)
Additional: ADC_IN0, RTC_TAMP1, WKUP0
Default: PA1
PA1
7
I/O
Alternate: USART0_RTS(3), USART1_RTS(4), TIMER1_CH1,
I2C1_SDA(5), EVENTOUT
Additional: ADC_IN1
Default: PA2
PA2
8
I/O
Alternate: USART0_TX(3), USART1_TX(4), TIMER1_CH2,
TIMER14_CH0
Additional: ADC_IN2
Default: PA3
PA3
9
I/O
Alternate: USART0_RX(3), USART1_RX(4), TIMER1_CH3,
TIMER14_CH1
Additional: ADC_IN3
Default: PA4
PA4
10
I/O
Alternate: SPI0_NSS, USART0_CK(3), USART1_CK(4),
TIMER13_CH0, SPI1_NSS(5)
Additional: ADC_IN4
Default: PA5
PA5
11
I/O
Alternate: SPI0_SCK, TIMER1_CH0, TIMER1_ETI
Additional: ADC_IN5
Default: PA6
PA6
12
I/O
Alternate: SPI0_MISO, TIMER2_CH0, TIMER0_BRKIN,
TIMER15_CH0, EVENTOUT
Additional: ADC_IN6
Default: PA7
PA7
13
I/O
Alternate: SPI0_MOSI, TIMER2_CH1, TIMER13_CH0,
TIMER0_CH0_ON, TIMER16_CH0, EVENTOUT
Additional: ADC_IN7
PB0
14
I/O
Default: PB0
21
GD32F130xx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
Alternate: TIMER2_CH2, TIMER0_CH1_ON, USART1_RX(4),
EVENTOUT
Additional: ADC_IN8
Default: PB1
PB1
15
Alternate: TIMER2_CH3, TIMER13_CH0, TIMER0_CH2_ON,
I/O
SPI1_SCK(5)
Additional: ADC_IN9
PB2
16
I/O
VDD
17
P
5VT
Default: PB2
Default: VDD
Default: PA8
PA8
18
I/O
5VT
Alternate: USART0_CK, TIMER0_CH0, CK_OUT,
USART1_TX(4), EVENTOUT
Default: PA9
PA9
19
I/O
5VT
Alternate: USART0_TX, TIMER0_CH1, TIMER14_BRKIN,
I2C0_SCL
Default: PA10
PA10
20
I/O
5VT
Alternate: USART0_RX, TIMER0_CH2, TIMER16_BRKIN,
I2C0_SDA
PA11
21
I/O
5VT
PA12
22
I/O
5VT
PA13
23
I/O
5VT
PA14
24
I/O
5VT
Default: PA11
Alternate: USART0_CTS, TIMER0_CH3, EVENTOUT
Default: PA12
Alternate: USART0_RTS, TIMER0_ETI, EVENTOUT
Default: PA13
Alternate: IFRP_OUT, SWDIO, SPI1_MISO(5)
Default: PA14
Alternate: USART0_TX(3), USART1_TX(4), SWCLK,
SPI1_MOSI(5)
Default: PA15
PA15
25
I/O
5VT
Alternate: SPI0_NSS, USART0_RX(3), USART1_RX(4),
TIMER1_CH0, TIMER1_ETI, SPI1_NSS(5), EVENTOUT
PB3
26
I/O
5VT
PB4
27
I/O
5VT
Default: PB3
Alternate: SPI0_SCK, TIMER1_CH1, EVENTOUT
Default: PB4
Alternate: SPI0_MISO, TIMER2_CH0, EVENTOUT
Default: PB5
PB5
28
I/O
5VT
Alternate: SPI0_MOSI, I2C0_SMBA, TIMER15_BRKIN,
TIMER2_CH1
PB6
29
I/O
5VT
PB7
30
I/O
5VT
BOOT0
31
I
Default: PB6
Alternate: I2C0_SCL, USART0_TX, TIMER15_CH0_ON
Default: PB7
Alternate: I2C0_SDA, USART0_RX, TIMER16_CH0_ON
Default: BOOT0
22
GD32F130xx Datasheet
Pin Name
Pins
PB8
32
Pin
I/O
Type(1)
Level(2)
I/O
5VT
Functions description
Default: PB8
Alternate: I2C0_SCL, TIMER15_CH0
Notes:
(1) Type: I = input, O = output, P = power.
(2) I/O Level: 5VT = 5 V tolerant.
(3) Functions are available on GD32F330K4 devices only.
(4) Functions are available on GD32F330K8/6 devices.
(5) Functions are available on GD32F330K8 devices.
23
GD32F130xx Datasheet
2.6.4.
GD32F130Gx QFN28 pin definitions
Table 2-6. GD32F130Gx QFN28 pin definitions
Pin
I/O
Pin Name
Pins
BOOT0
1
I
2
I/O
5VT
3
I/O
5VT
NRST
4
I/O
VDDA
5
P
PF0OSCIN
PF1OSCOUT
Functions description
Type(1) Level(2)
Default: BOOT0
Default: PF0
Additional: OSCIN
Default: PF1
Additional: OSCOUT
Default: NRST
Default: VDDA
Default: PA0
PA0-WKUP
6
I/O
Alternate: USART0_CTS(3), USART1_CTS(4), TIMER1_CH0,
TIMER1_ETI, I2C1_SCL(5)
Additional: ADC_IN0, RTC_TAMP1, WKUP0
Default: PA1
PA1
7
I/O
Alternate: USART0_RTS(3), USART1_RTS(4), TIMER1_CH1,
I2C1_SDA(5), EVENTOUT
Additional: ADC_IN1
Default: PA2
PA2
8
I/O
Alternate: USART0_TX(3), USART1_TX(4), TIMER1_CH2,
TIMER14_CH0
Additional: ADC_IN2
Default: PA3
PA3
9
I/O
Alternate: USART0_RX(3), USART1_RX(4), TIMER1_CH3,
TIMER14_CH1
Additional: ADC_IN3
Default: PA4
PA4
10
I/O
Alternate: SPI0_NSS, USART0_CK(3), USART1_CK(4),
TIMER13_CH0, SPI1_NSS(5)
Additional: ADC_IN4
Default: PA5
PA5
11
I/O
Alternate: SPI0_SCK, TIMER1_CH0, TIMER1_ETI
Additional: ADC_IN5
Default: PA6
PA6
12
I/O
Alternate: SPI0_MISO, TIMER2_CH0, TIMER0_BRKIN,
TIMER15_CH0, EVENTOUT
Additional: ADC_IN6
Default: PA7
PA7
13
I/O
Alternate: SPI0_MOSI, TIMER2_CH1, TIMER13_CH0,
TIMER0_CH0_ON, TIMER16_CH0, EVENTOUT
Additional: ADC_IN7
PB0
14
I/O
Default: PB0
24
GD32F130xx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
Alternate: TIMER2_CH2, TIMER0_CH1_ON, USART1_RX(4),
EVENTOUT
Additional: ADC_IN8
Default: PB1
PB1
15
Alternate: TIMER2_CH3, TIMER13_CH0, TIMER0_CH2_ON,
I/O
SPI1_SCK(5)
Additional: ADC_IN9
VSS
16
P
Default: VSS
VDD
17
P
Default: VDD
Default: PA8
PA8
18
I/O
5VT
Alternate: USART0_CK, TIMER0_CH0, CK_OUT,
USART1_TX(4), EVENTOUT
Default: PA9
PA9
19
I/O
5VT
Alternate: USART0_TX, TIMER0_CH1, TIMER14_BRKIN ,
I2C0_SCL
Default: PA10
PA10
20
I/O
5VT
Alternate: USART0_RX, TIMER0_CH2, TIMER16_BRKIN,
I2C0_SDA
PA13
21
I/O
5VT
Default: PA13
Alternate: IFRP_OUT, SWDIO, SPI1_MISO(5)
Default: PA14
PA14
22
I/O
5VT
Alternate: USART0_TX(3), USART1_TX(4), SWCLK,
SPI1_MOSI(5)
Default: PA15
PA15
23
I/O
5VT
Alternate: SPI0_NSS, USART0_RX(3), USART1_RX(4),
TIMER1_CH0, TIMER1_ETI, SPI1_NSS(5), EVENTOUT
PB3
24
I/O
5VT
PB4
25
I/O
5VT
PB5
26
I/O
5VT
Default: PB3
Alternate: SPI0_SCK, TIMER1_CH1, EVENTOUT
Default: PB4
Alternate: SPI0_MISO, TIMER2_CH0, EVENTOUT
Default: PB5
Alternate: SPI0_MOSI, I2C0_SMBA, TIMER15_BRKIN,
TIMER2_CH1
PB6
27
I/O
5VT
PB7
28
I/O
5VT
Default: PB6
Alternate: I2C0_SCL, USART0_TX, TIMER15_CH0_ON
Default: PB7
Alternate: I2C0_SDA, USART0_RX, TIMER16_CH0_ON
Notes:
(1) Type: I = input, O = output, P = power.
(2) I/O Level: 5VT = 5 V tolerant.
(3) Functions are available on GD32F330G4 devices only.
(4) Functions are available on GD32F330G8/6 devices.
25
GD32F130xx Datasheet
(5) Functions are available on GD32F330G8 devices.
2.6.5.
GD32F130Fx TSSOP20 pin definitions
Table 2-7. GD32F130Fx TSSOP20 pin definitions
Pin
I/O
Type(1)
Level(2)
Pin Name
Pins
BOOT0
1
I
2
I/O
5VT
3
I/O
5VT
NRST
4
I/O
VDDA
5
P
PF0OSCIN
PF1OSCOUT
Functions description
Default: BOOT0
Default: PF0
Additional: OSCIN
Default: PF1
Additional: OSCOUT
Default: NRST
Default: VDDA
Default: PA0
PA0-WKUP
6
I/O
Alternate: USART0_CTS(3), USART1_CTS(4), TIMER1_CH0,
TIMER1_ETI, I2C1_SCL(5)
Additional: ADC_IN0, RTC_TAMP1, WKUP0
Default: PA1
PA1
7
I/O
Alternate: USART0_RTS(3), USART1_RTS(4), TIMER1_CH1,
I2C1_SDA(5), EVENTOUT
Additional: ADC_IN1
Default: PA2
PA2
8
I/O
Alternate: USART0_TX(3), USART1_TX(4), TIMER1_CH2,
TIMER14_CH0
Additional: ADC_IN2
Default: PA3
PA3
9
I/O
Alternate: USART0_RX(3), USART1_RX(4), TIMER1_CH3,
TIMER14_CH1
Additional: ADC_IN3
Default: PA4
PA4
10
I/O
Alternate: SPI0_NSS, USART0_CK(3), USART1_CK(4),
TIMER13_CH0, SPI1_NSS(5)
Additional: ADC_IN4
Default: PA5
PA5
11
I/O
Alternate: SPI0_SCK, TIMER1_CH0, TIMER1_ETI
Additional: ADC_IN5
Default: PA6
PA6
12
I/O
Alternate: SPI0_MISO, TIMER2_CH0, TIMER0_BRKIN,
TIMER15_CH0, EVENTOUT
Additional: ADC_IN6
PA7
13
I/O
Default: PA7
Alternate: SPI0_MOSI, TIMER2_CH1, TIMER13_CH0,
26
GD32F130xx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
TIMER0_CH0_ON, TIMER16_CH0, EVENTOUT
Additional: ADC_IN7
Default: PB1
Alternate: TIMER2_CH3, TIMER13_CH0, TIMER0_CH2_ON,
PB1
14
I/O
VSS
15
P
Default: VSS
VDD
16
P
Default: VDD
SPI1_SCK(5)
Additional: ADC_IN9
Default: PA9
PA9
17
I/O
5VT
Alternate: USART0_TX, TIMER0_CH1, TIMER14_BRKIN,
I2C0_SCL
Default: PA10
PA10
18
I/O
5VT
Alternate: USART0_RX, TIMER0_CH2, TIMER16_BRKIN,
I2C0_SDA
PA13
19
I/O
5VT
Default: PA13
Alternate: IFRP_OUT, SWDIO, SPI1_MISO(5)
Default: PA14
PA14
20
I/O
5VT
Alternate: USART0_TX(3), USART1_TX(4), SWCLK,
SPI1_MOSI(5)
Notes:
(1) Type: I = input, O = output, P = power.
(2) I/O Level: 5VT = 5 V tolerant.
(3) Functions are available on GD32F330F4 devices only.
(4) Functions are available on GD32F330F8/6 devices.
(5) Functions are available on GD32F330F8 devices.
27
GD32F130xx Datasheet
2.6.6.
GD32F130xx pin alternate functions
Table 2-8. Port A alternate functions summary
Pin
Name
AF0
AF1
AF2
AF3
AF4
AF5
AF6
USART0_CTS(
PA0
1)
TIMER1_CH0
USART1_CTS(
TIMER1_ETI
I2C1_SCL(3)
2)
USART0_RTS(
1)
PA1
EVENTOUT
USART1_RTS(
TIMER1_CH1
I2C1_SDA(3)
2)
PA2
PA3
TIMER14_C USART0_TX(1)
H0
USART1_TX(2)
TIMER14_C USART0_RX(1)
H1
USART1_RX(2)
TIMER13_C
SPI1_NSS(
USART1_CK(2)
H0
3)
SPI0_NSS
PA5
SPI0_SCK
PA6
SPI0_MISO
TIMER2_CH0
PA7
SPI0_MOSI
TIMER2_CH1
PA8
CK_OUT
PA10
TIMER14_B
RKIN
TIMER16_B
RKIN
TIMER1_CH3
USART0_CK(1)
PA4
PA9
TIMER1_CH2
TIMER1_CH0
TIMER1_ETI
TIMER0_BRK
IN
H0
TIMER0_CH0
T
TIMER13_C TIMER16_C EVENTOU
_ON
USART0_CK TIMER0_CH0
USART0_TX
TIMER15_C EVENTOU
H0
H0
T
EVENT USART1_T
X(2)
OUT
TIMER0_CH1
I2C0_SCL
USART0_RX TIMER0_CH2
I2C0_SDA
PA11 EVENTOUT USART0_CTS TIMER0_CH3
PA12 EVENTOUT USART0_RTS TIMER0_ETI
PA13
SWDIO
PA14
SWCLK
PA15
SPI0_NSS
SPI1_MIS
IFRP_OUT
O(3)
USART0_TX(1)
SPI1_MOS
USART1_TX(2)
I(3)
USART0_RX(1) TIMER1_CH0 EVENT
USART1_RX(2) TIMER1_ETI
OUT
SPI1_NSS(
3)
Notes:
(1) Functions are available on GD32F130x4 devices only.
(2) Functions are available on GD32F130x8/6 devices.
(3) Functions are available on GD32F130x8 devices.
28
GD32F130xx Datasheet
Table 2-9. Port B alternate functions summary
Pin
Name
PB0
PB1
AF0
AF1
AF2
AF3
EVENTOU TIMER2_CH TIMER0_CH1_
T
2
AF4
3
AF6
USART1_RX(2)
ON
TIMER13_ TIMER2_CH TIMER0_CH2_
CH0
AF5
SPI1_SCK
(3)
ON
PB2
PB3
PB4
PB5
PB6
PB7
SPI0_SCK EVETOUT
SPI0_MIS TIMER2_CH
O
0
TIMER1_CH1
EVENTOUT
SPI0_MO TIMER2_CH TIMER15_BRKI
SI
USART0_
TX
USART0_
RX
1
I2C0_SCL
I2C0_SDA
N
TIMER15_CH0_
ON
TIMER16_CH0_
ON
PB8
I2C0_SCL
TIMER15_CH0
PB9
IFRP_OUT I2C0_SDA
TIMER16_CH0
PB10
PB11
EVENTOU
T
I2C0_SMBA
I2C1_SCL(3)
TIMER1_CH2
I2C1_SDA(3)
TIMER1_CH3
EVENTOUT
SPI0_NSS
(1)
PB12
SPI1_NSS
I2C1_SMBA(3)
EVENTOUT TIMER0_BRKIN
(3)
SPI0_SCK
PB13
(1)
TIMER0_CH0_
SPI1_SCK
ON
(3)
SPI0_MIS
PB14
O(1)
SPI1_MIS
TIMER14_C TIMER0_CH1_
H0
ON
O(3)
SPI0_MO
PB15
SI(1)
SPI1_MO
TIMER14_C TIMER0_CH2_
H1
ON
TIMER14_C
H0_ON
SI(3)
Notes:
(1) Functions are available on GD32F130x4 devices only.
(2) Functions are available on GD32F130x8/6 devices.
(3) Functions are available on GD32F130x8 devices.
29
GD32F130xx Datasheet
Table 2-10. Port C & D & F alternate functions summary
Pin
Name
AF0
PC0
EVENTOUT
PC1
EVENTOUT
PC2
EVENTOUT
PC3
EVENTOUT
PC4
EVENTOUT
PC6
TIMER2_CH0
PC7
TIMER2_CH1
PC8
TIMER2_CH2
PC9
TIMER2_CH3
PD2
TIMER2_ETI
PF4
PF5
AF1
AF2
AF3
AF4
AF5
AF6
SPI1_NSS,EV
ENTOUT
EVENTOUT
30
GD32F130xx Datasheet
3.
Functional description
3.1.
ARM® Cortex®-M3 core
The Cortex®-M3 processor is the latest generation of ARM® processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
32-bit ARM® Cortex®-M3 processor core
Up to 72 MHz operation frequency
Single-cycle multiplication and hardware divider
Integrated Nested Vectored Interrupt Controller (NVIC)
24-bit SysTick timer
The Cortex®-M3 processor is based on the ARMv7 architecture and supports both Thumb
and Thumb-2 instruction sets. Some system peripherals listed below are also provided by
Cortex®-M3:
Internal Bus Matrix connected with ICode bus, DCode bus, system bus, Private
Peripheral Bus (PPB) and debug accesses (AHB-AP)
3.2.
Nested Vectored Interrupt Controller (NVIC)
Flash Patch and Breakpoint (FPB)
Data Watchpoint and Trace (DWT)
Instrument Trace Macrocell (ITM)
Serial Wire JTAG Debug Port (SWJ-DP)
Trace Port Interface Unit (TPIU)
On-chip memory
Up to 64 Kbytes of Flash memory
Up to 8 Kbytes of SRAM with hardware parity checking
The ARM® Cortex®-M3 processor is structured in Harvard architecture which can use
separate buses to fetch instructions and load/store data. 64 Kbytes of inner Flash and 8
Kbytes of inner SRAM at most is available for storing programs and data, both accessed (R/W)
at CPU clock speed with zero wait states. The Table 2-2. GD32F130xx memory map
shows the memory map of the GD32F130xx series of devices, including code, SRAM,
peripheral, and other pre-defined regions.
3.3.
Clock, reset and supply management
Internal 8 MHz factory-trimmed RC and external 4 to 32 MHz crystal oscillator
Internal 40 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator
31
GD32F130xx Datasheet
Integrated system clock PLL
2.6 to 3.6 V application supply and I/Os
Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage
detector (LVD)
The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These
include speed internal RC oscillator and external crystal oscillator, high speed and low speed
two types. Several prescalers allow the frequency configuration of the AHB and two APB
domains. The maximum frequency of the AHB and two APB domains is 72 MHz. See Figure
2-7. GD32F130xx clock tree for details on the clock tree.
GD32F1x0 Reset Control includes the control of three kinds of reset: power reset, system
reset and backup domain reset. A system reset resets the processor core and peripheral IP
components with the exception of the SW-DP controller and the Backup domain. Power-on
reset (POR) and power-down reset (PDR) are always active, and ensures proper operation
starting from 2.6 V and down to 1.8V. The device remains in reset mode when VDD is below
a specified threshold. The embedded low voltage detector (LVD) monitors the power supply,
compares it to the voltage threshold and generates an interrupt as a wake up message for
leading the MCU into security.
Power supply schemes:
VDD range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator.
Provided externally through VDD pins.
VSSA, VDDA range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks,
RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
VBAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32 KHz oscillator and
backup registers (through power switch) when VDD is not present.
3.4.
Boot modes
At startup, boot pins are used to select one of three boot options:
Boot from main Flash memory (default)
Boot from system memory
Boot from on-chip SRAM
In default condition, boot from main Flash memory is selected. The boot loader is located in
the internal boot ROM memory (system memory). It is used to reprogram the Flash memory
by using USART0 (PA9 and PA10) or USART1 (PA2 and PA3, PA14 and PA15).
3.5.
Power saving modes
The MCU supports three kinds of power saving modes to achieve even lower power
consumption. They are sleep mode, deep-sleep mode, and standby mode. These operating
modes reduce the power consumption and allow the application to achieve the best balance
32
GD32F130xx Datasheet
between the CPU operating time, speed and power consumption.
Sleep mode
In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and
any interrupt/event can wake up the system.
Deep-sleep mode
In deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed
crystal oscillator (IRC8M, HXTAL) and PLL are disabled. Only the contents of SRAM and
registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the
system from the deep-sleep mode including the 16 external lines, the RTC alarm, the
LVD output, the RTC tamper and Timestamp, the USART0 wakeup and the CEC wakeup.
When exiting the deep-sleep mode, the IRC8M is selected as the system clock.
Standby mode
In standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of
IRC8M, HXTAL and PLL are disabled. The contents of SRAM and registers (except
Backup registers) are lost. There are four wakeup sources for the standby mode,
including the external reset from NRST pin, the RTC alarm, the FWDGT reset, and the
rising edge on WKUP pin.
3.6.
Analog to digital converter (ADC)
12-bit SAR ADC engine with up to 1 MSPS conversion rate
Input voltage range: VSSA to VDDA (2.6 to 3.6 V)
Temperature sensor
One 12-bit 1 μs multi-channel ADCs are integrated in the device. It is a total of up to 16
multiplexed external channels and 3 internal channels for temperature sensor, voltage
reference, VBAT voltage measurement. The conversion range is between 2.6 V < VDDA < 3.6
V. An analog watchdog block can be used to detect the channels, which are required to remain
within a specific threshold window. A configurable channel management block of analog
inputs also can be used to perform conversions in single, continuous, scan or discontinuous
mode to support more advanced usages. The ADC can be triggered from the events
generated by the general timers (TIMERx=1,2,14) and the advanced timers (TIMER0) with
internal connection.
The temperature sensor can be used to generate a voltage that varies linearly with
temperature. It is internally connected to the ADC_IN16 input channel which is used to convert
the sensor output voltage into a digital value. Each device is factory-calibrated to improve the
accuracy and the calibration data are stored in the system memory area.
3.7.
DMA
7 channel DMA controller
Peripherals supported: Timers, ADC, SPIs, I2Cs, USARTs
33
GD32F130xx Datasheet
The flexible general-purpose DMA controllers provide a hardware method of transferring data
between peripherals and/or memory without intervention from the CPU, thereby freeing up
bandwidth for other system functions. Three types of access method are supported:
peripheral to memory, memory to peripheral, memory to memory.
Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel
requests are determined by software configuration and hardware channel number. Transfer
size of source and destination are independent and configurable.
3.8.
General-purpose inputs/outputs (GPIOs)
Up to 55 fast GPIOs, all mappable on 16 external interrupt lines
Analog input/output configurable
Alternate function input/output configurable
There are up to 55 general purpose I/O pins (GPIO) in GD32F130xx, named PA0 ~ PA15 and
PB0 ~ PB15, PC0 ~ PC15, PD2, PF0, PF1, PF4-PF7 to implement logic input/output functions.
Each of the GPIO ports has related control and configuration registers to satisfy the
requirements of specific applications. The external interrupts on the GPIO pins of the device
have related control and configuration registers in the Interrupt/event controller (EXTI). The
GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility
on the package pins. Each of the GPIO pins can be configured by software as output (pushpull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate
function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs
are high-current capable except for analog inputs.
3.9.
Timers and PWM generation
One 16-bit advanced timer (TIMER0), one 32-bit general timer (TIMER1), five 16-bit
general timers (TIMER2, TIMER13 ~ TIMER16)
Up to 4 independent channels of PWM, output compare or input capture for each general
timer and external trigger input
16-bit, motor control PWM advanced timer with programmable dead-time generation for
output match
Encoder interface controller with two inputs using quadrature decoder
24-bit SysTick timer down counter
2 watchdog timers (free watchdog timer and window watchdog timer)
The advanced timer (TIMER0) can be used as a three-phase PWM multiplexed on 6 channels.
It has complementary PWM outputs with programmable dead-time generation. It can also be
used as a complete general timer. The 4 independent channels can be used for input capture,
compare match output, generation of PWM waveform (edge-aligned and center-aligned Mode)
and single pulse mode output. If configured as a general 16-bit timer, it has the same functions
as the TIMERx timer. It can be synchronized with external signals or to interconnect with other
34
GD32F130xx Datasheet
general timers together which have the same architecture and features.
The general timer can be used for a variety of purposes including general time, input signal
pulse width measurement or output waveform generation such as a single pulse generation
or PWM output, up to 4 independent channels for input capture/output compare. TIMER1 is
based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TIMER2 is based on a
16-bit auto-reload up/downcounter and a 16-bit prescaler. TIMER13 ~ TIMER16 is based on
a 16-bit auto-reload upcounter and a 16-bit prescaler. The general timer also supports an
encoder interface with two inputs using quadrature decoder.
The GD32F130xx have two watchdog peripherals, free watchdog timer and window watchdog
timer. They offer a combination of high safety level, flexibility of use and timing accuracy.
The free watchdog timer includes a 12-bit down-counting counter and an 8-bit prescaler, It is
clocked from an independent 40 KHz internal RC and as it operates independently of the
main clock, it can operate in stop and standby modes. It can be used either as a watchdog to
reset the device when a problem occurs, or as a free-running timer for application timeout
management.
The window watchdog timer is based on a 7-bit down counter that can be set as free-running.
It can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early wake up interrupt capability and the counter can be frozen in
debug mode.
The SysTick timer is dedicated for OS, but could also be used as a standard down counter.
The features are shown below:
3.10.
A 24-bit down counter
Auto reload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source
Real time clock (RTC)
Independent binary-coded decimal (BCD) format timer/counter with five 32-bit backup
registers
Calendar with subsecond, seconds, minutes, hours, week day, date, year and month
automatically correction
Alarm function with wake up from deep-sleep and standby mode capability
On-the-fly correction for synchronization with master clock. Digital calibration with 1 ppm
resolution for compensation of quartz crystal inaccuracy
The real time clock is an independent timer which provides a set of continuously running
counters in backup registers to provide a real calendar function, and provides an alarm
interrupt or an expected interrupt. It is not reset by a system or power reset, or when the
device wakes up from standby mode. A 20-bit prescaler is used for the time base clock and
is by default configured to generate a time base of 1 second from a clock at 32.768 KHz from
35
GD32F130xx Datasheet
external crystal oscillator.
3.11.
Inter-integrated circuit (I2C)
Up to two I2Cs bus interfaces can support both master and slave mode with a frequency
up to 400 KHz
Provide arbitration function, optional PEC (packet error checking) generation and
checking
Supports 7-bit and 10-bit addressing mode and general call addressing mode
The I2C interface is an internal circuit allowing communication with an external I2C interface
which is an industry standard two line serial interface used for connection to external
hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line
(SCL). The I2C module provides transfer rate of up to 100 KHz in standard mode and up to
400 KHz in fast mode. The I2C module also has an arbitration detect function to prevent the
situation where more than one master attempts to transmit data to the I2C bus at the same
time. A CRC-8 calculator is also provided in I2C interface to perform packet error checking
for I2C data.
3.12.
Serial peripheral interface (SPI)
Up to two SPIs interfaces with a frequency of up to 18 MHz
Support both master and slave mode
Hardware CRC calculation and transmit automatic CRC error checking
The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO
& MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by
the DMA controller. The SPI interface may be used for a variety of purposes, including simplex
synchronous transfers on two lines with a possible bidirectional data line or reliable
communication using CRC checking.
3.13.
Universal synchronous asynchronous receiver transmitter
(USART)
Up to two USARTs with operating frequency up to 9 MHz
Supports both asynchronous and clocked synchronous serial communication modes
IrDA SIR encoder and decoder support
LIN break generation and detection
ISO 7816-3 compliant smart card interface
The USART (USART0, USART1) are used to translate data between parallel and serial
interfaces, provides a flexible full duplex data exchange using synchronous or asynchronous
36
GD32F130xx Datasheet
transfer. It is also commonly used for RS-232 standard communication. The USART includes
a programmable baud rate generator which is capable of dividing the system clock to produce
a dedicated clock for the USART transmitter and receiver. The USART also supports DMA
function for high speed data communication.
3.14.
Debug mode
Serial wire JTAG debug port (SWJ-DP)
The ARM® SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
3.15.
Package and operation temperature
LQFP64 (GD32F130Rx), LQFP48 (GD32F130Cx), QFN32 (GD32F130Kx), QFN28
(GD32F130Gx) and TSSOP20 (GD32F130Fx)
Operation temperature range: -40°C to +85°C (industrial level)
Operation temperature range: -20°C to +85°C (commercial level)
37
GD32F130xx Datasheet
4.
Electrical characteristics
4.1.
Absolute maximum ratings
The maximum ratings are the limits to which the device can be subjected without permanently
damaging the device. Note that the device is not guaranteed to operate properly at the
maximum ratings. Exposure to the absolute maximum rating conditions for extended periods
may affect device reliability.
Table 4-1. Absolute maximum ratings
Symbol
Parameter
Min
Max
Unit
VDD
External voltage range
VSS - 0.3
VSS + 3.6
V
VDDA
External analog supply voltage
VSSA - 0.3
VSSA + 3.6
V
VBAT
External battery supply voltage
VSS - 0.3
VSS + 3.6
V
Input voltage on 5V tolerant pin
VSS - 0.3
VDD + 4.0
V
Input voltage on other I/O
VSS - 0.3
4.0
V
IIO
Maximum current for GPIO pins
—
25
mA
TA
Operating temperature range
-40
+85
°C
TSTG
Storage temperature range
-55
+150
°C
TJ
Maximum junction temperature
—
125
°C
VIN
4.2.
Recommended DC characteristics
Table 4-2. DC operating conditions
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD
Supply voltage
—
2.6
3.3
3.6
V
VDDA
Analog supply voltage
Same as VDD
2.6
3.3
3.6
V
VBAT
Battery supply voltage
—
1.8
—
3.6
V
38
GD32F130xx Datasheet
4.3.
Power consumption
The power measurements specified in the tables represent that code with data executing from
on-chip Flash with the following specifications.
Table 4-3. Power consumption characteristics
Symbol
Parameter
Conditions
Min
Typ
Max Unit
VDD=VBAT=3.3V, HXTAL=8MHz, System
—
17.26
—
mA
—
12.23
—
mA
-—
9.26
—
mA
—
6.75
—
mA
—
9.76
—
mA
—
3.89
—
mA
—
155.14
—
μA
—
143.17
—
μA
—
7.38
—
μA
—
6.94
—
μA
—
5.74
—
μA
—
3.08
—
μA
—
2.78
—
μA
—
2.12
—
μA
—
1.37
—
μA
—
1.25
—
μA
—
1.05
—
μA
clock=48 MHz, All peripherals enabled
VDD=VBAT=3.3V, HXTAL=8MHz, System clock
Supply current
=48 MHz, All peripherals disabled
(Run mode)
VDD=VBAT=3.3V, HXTAL=8MHz, System clock
=24 MHz, All peripherals enabled
VDD=VBAT=3.3V, HXTAL=8MHz, System Clock
=24 MHz, All peripherals disabled
VDD=VBAT=3.3V, HXTAL=8MHz, CPU clock off,
System clock =48 MHz, All peripherals
Supply current
IDD
enabled
(Sleep mode) VDD=VBAT=3.3V, HXTAL=8MHz, CPU clock off,
System clock =48 MHz, All peripherals
disabled
Supply current
(Deep-Sleep
mode)
VDD=VBAT=3.3V, Regulator in run mode,
IRC40K on, RTC on, All GPIOs analog mode
VDD=VBAT=3.3V, Regulator in low power mode,
IRC40K on, RTC on, All GPIOs analog mode
VDD=VBAT=3.3V, LXTAL off, IRC40K on, RTC
Supply current
(Standby
mode)
on
VDD=VBAT=3.3V, LXTAL off, IRC40K on, RTC
off
VDD=VBAT=3.3V, LXTAL off, IRC40K off, RTC
off
VDD not available, VBAT=3.6 V, LXTAL on with
external crystal, RTC on, Higher driving
VDD not available, VBAT=3.3 V, LXTAL on with
external crystal, RTC on, Higher driving
VDD not available, VBAT=2.6 V, LXTAL on with
IBAT
Battery supply
external crystal, RTC on, Higher driving
current
VDD not available, VBAT=3.6 V, LXTAL on with
external crystal, RTC on, Lower driving
VDD not available, VBAT=3.3 V, LXTAL on with
external crystal, RTC on, Lower driving
VDD not available, VBAT=2.6 V, LXTAL on with
external crystal, RTC on, Lower driving
39
GD32F130xx Datasheet
4.4.
EMC characteristics
EMS (electromagnetic susceptibility) includes ESD (Electrostatic discharge, positive and
negative) and FTB (Burst of Fast Transient voltage, positive and negative) testing result is
given in the Table 4-4. EMS characteristics, based on the EMS levels and classes
compliant with IEC 61000 series standard.
Table 4-4. EMS characteristics
Symbol
VESD
Parameter
Conditions
Voltage applied to all device pins to
VDD = 3.3 V, TA = +25 °C
induce a functional disturbance
conforms to IEC 61000-4-2
Fast transient voltage burst applied to
VFTB
induce a functional disturbance through
100 pF on VDD and VSS pins
Level/Class
3B
VDD = 3.3 V, TA = +25 °C
4A
conforms to IEC 61000-4-4
EMI (Electromagnetic Interference) emission testing result is given in the Table 4-5. EMI
characteristics, compliant with IEC 61967-2 standard which specifies the test board and
the pin loading.
Table 4-5. EMI characteristics
Symbol
Parameter
Conditions
4.5.
Peak level
frequency band
Conditions
Unit
24M
48M
0.1 to 2 MHz
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