ES7210

ES7210 High Performance Four Channels Audio ADC FEATURES APPLICATIONS            High performance multi-bit delta-sigma audio ADC 102 dB signal to noise ratio -85 dB THD+N 24-bit, 8 to 100 kHz sampling frequency I2S/PCM master or slave serial data port Support TDM 256/384Fs, USB 12/24 MHz and other non standard audio system clocks Low power standby mode Mic array Smart speaker Far field voice capture ORDERING INFORMATION ES7210 -40°C ~ +85°C QFN-32 BLOCK DIAGRAM SDOUT2/TDMIN MIC1P/MIC1N MIC2P/MIC2N MIC3P/MIC3N MIC4P/MIC4N Multi-bit Delta-sigma Modulator DSP Audio Data Interface 2 Clock Manager Sample Rate Detector IC Interface MCLK CCLK CDATA AD0 AD1 1 SDOUT1/TDMOUT SCLK LRCK Everest Semiconductor Confidential ES7210 1. PIN OUT AND DESCRIPTION REFQM MICBIAS34 MIC4N MIC4P REFP34 REFQ34 MIC3P MIC3N 25 26 27 28 29 30 31 32 AD0 AD1 CDATA CCLK MCLK VDDP VDDD GNDD 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 ES7210 MICBIAS12 VDDM VDDA GNDA MIC2N MIC2P REFQ12 REFP12 16 15 14 13 12 11 10 9 MIC1P MIC1N DMIC_CLK INT SDOUT2/TDMIN SDOUT1/TDMOUT LRCK SCLK Pin Name Pin number Input or Output Pin Description CCLK, CDATA AD0, AD1 MCLK SCLK LRCK SDOUT1/TDMOUT SDOUT2/TDMIN INT DMIC_CLK MIC1P, MIC1N MIC2P, MIC2N MIC3P, MIC3N MIC4P, MIC4N MICBIAS12 MICBIAS34 VDDP VDDD, GNDD VDDA, GNDA VDDM REFP12, REFP34 REFQ12, REFQ34 REFQM 3, 4 1, 2 5 9 10 11 12 13 14 16, 15 19, 20 31, 32 28, 27 24 26 6 7, 8 22, 21 23 17, 29 18, 30 25 I/O I I I/O I/O O I/O O O I2C clock and data I2C address Master clock Serial data bit clock Serial data left and right channel frame clock Analog Mic input Analog Mic bias Analog Analog Analog Analog Analog Analog Analog Power supply for the digital input and output Digital power supply Analog power supply Analog power supply Filtering capacitor connection Filtering capacitor connection Filtering capacitor connection Revision 9.1 Serial data output or TDM data input and output Interrupt Digital mic clock 2 January 2019 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES7210 2. TYPICAL APPLICATION CIRCUIT VD DM AGND 1uF AGND AGND IIC 1 2 3 4 5 9 10 11 12 IIS GPIO 100nF 8 100K VD DP 13 14 M CLK SCLK LRCK SDOUT 1/TDM O UT SDOUT 2/TDM IN 23 V D DA 21 V D DM 17 ES7210 Everes t M IC4P M IC4N M IC3P M IC3N M IC2P M IC2N M IC1P M IC1N * 26 M icbias34 28 27 1uF 1uF 31 32 AGND 1uF M ICBIAS12 VD DA AGND 1uF INT DM IC_CLK * * 1uF AGND M ICBIAS34 GNDD AD0 AD1 CD ATA CCLK G N DA 25 18 RE FP1 2 30 RE FQ M VD DP VD DD * * * * * RE FQ 1 2 * * 6 7 PGND RE FP3 4 VD DP VD DC 33 RE FQ 3 4 AGND 100nF 29 AGND In the lay o ut, c h ip is treated as an an alo g d ev ice 22 1uF 1uF 1uF 1uF 1uF 0R GND (SY S) 1uF 1uF M ic4P M ic4N M ic3P M ic3N * 24 19 20 16 15 M icbias12 1uF 1uF 1uF 1uF M ic2P M ic2N M ic1P M ic1N Fo r th e b es t pe rfo rm an ce ,d ec o up lin g an d f ilterin g c ap ac ito r s s h o u ld b e loc ated as c lo s e to th e d evice p ac kag e as po s s ib le Ad d itio n al par allel ca pac ito rs (ty p ically 0 .1 μF ) c an b e us ed , larg er v alu e c ap ac ito r s (typ ic ally 1 0 μF ) w o u ld als o help * 3. CLOCK MODES AND SAMPLING FREQUENCIES The device supports standard audio clocks (256Fs, 384Fs, 512Fs, etc), USB clocks (12/24 MHz), and some common non standard audio clocks (25 MHz, 26 MHz, etc). According to the serial audio data sampling frequency (Fs), the device can work in two speed modes: single speed mode or double speed mode. In single speed mode, Fs normally ranges from 8 kHz to 48 kHz, and in double speed mode, Fs normally range from 64 kHz to 96 kHz. The device can work either in master clock mode or slave clock mode. In slave mode, LRCK and SCLK are supplied externally, and LRCK and SCLK must be synchronously derived from the system clock with specific rates. In master mode, LRCK and SCLK are derived internally from device master clock. 4. MICRO-CONTROLLER CONFIGURATION INTERFACE The device supports standard I2C micro-controller configuration interface. External microcontroller can completely configure the device through writing to internal configuration registers. I2C interface is a bi-directional serial bus that uses a serial data line (CDATA) and a serial clock line (CCLK) for data transfer. The timing diagram for data transfer of this interface is given in Figure 1a and Figure 1b. Data are transmitted synchronously to CCLK clock on the CDATA line on a byte-by-byte basis. Each bit in a byte is sampled during CCLK high with MSB bit being transmitted firstly. Each transferred byte is followed by an acknowledge bit from receiver to pull the CDATA low. The transfer rate of this interface can be up to 400 kbps. Revision 9.1 3 January 2019 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES7210 A master controller initiates the transmission by sending a “start” signal, which is defined as a high-to-low transition at CDATA while CCLK is high. The first byte transferred is the slave address. It is a seven-bit chip address followed by a RW bit. The chip address must be 1000 0x, where x equals AD1 AD0. The RW bit indicates the slave data transfer direction. Once an acknowledge bit is received, the data transfer starts to proceed on a byte-by-byte basis in the direction specified by the RW bit. The master can terminate the communication by generating a “stop” signal, which is defined as a low-to-high transition at CDATA while CCLK is high. In I2C interface mode, the registers can be written and read. The formats of “write” and “read” instructions are shown in Table 1 and Table 2. Please note that, to read data from a register, you must set R/W bit to 0 to access the register address and then set R/W to 1 to read data from the register. Table 1 Write Data to Register in I2C Interface Mode start Chip Address 1000 0 AD1 AD0 R/W 0 ACK Chip Addr CDATA Register Address RAM Write ACK bit 1 to 7 Reg Addr ACK ACK bit 1 to 8 Data to be written DATA Write Data ACK ACK bit 1 to 8 CCLK START STOP Figure 1a I2C Write Timing Table 2 Read Data from Register in I2C Interface Mode Chip Address 1000 0 AD1 AD0 Chip Address 1000 0 AD1 AD0 Start Start Chip Addr CDATA bit 1 to 7 Write ACK R/W 0 R/W 1 Reg Addr ACK ACK ACK bit 1 to 8 Register Address RAM Data to be read Data Chip Addr bit 1 to 7 Read ACK ACK NACK Stop Read Data NO ACK bit 1 to 8 CCLK START START STOP Figure 1b I2C Read Timing Revision 9.1 4 January 2019 Latest datasheet: www.everest-semi.com or info@everest-semi.com Stop Everest Semiconductor Confidential ES7210 5. DIGITAL AUDIO INTERFACE The device provides many formats of serial audio data interface to the output from the ADC through LRCK, SCLK and SDOUT pins. These formats are I2S, left justified, DSP/PCM mode and TDM. ADC data is out at SDOUT on the falling edge of SCLK. The relationships of SDOUT, SCLK and LRCK with these formats are shown through Figure 2a to Figure 2h. ES7210 can be cascaded up to 16-ch through single I2S or TDM, please refer to the user guide for detail description. 1 SCLK 1 SCLK L Channel LRCK R Channel SCLK SDOUT MSB LSB LSB MSB Figure 2a I2S Serial Audio Data Format LRCK L Channel R Channel SCLK SDOUT LSB MSB MSB LSB Figure 2b Left Justified Serial Audio Data Format 1 SCLK LRCK R Channel L Channel SCLK SDOUT MSB LSB MSB LSB Figure 2c DSP/PCM Mode A Serial Audio Data Format LRCK R Channel L Channel SCLK SDOUT MSB LSB MSB LSB Figure 2d DSP/PCM Mode B Serial Audio Data Format Revision 9.1 5 January 2019 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential 1 SCLK ES7210 1 SCLK Channel 3 Channel 1 LRCK Channel 4 Channel 2 SCLK SDOUT MSB LSB LSB MSB MSB LSB LSB MSB Figure 2e TDM I2S Serial Audio Data Format LRCK Channel 3 Channel 1 Channel 4 Channel 2 SCLK SDOUT MSB LSB LSB MSB MSB LSB LSB MSB Figure 2f TDM Left Justified Serial Audio Data Format 1 SCLK LRCK Channel 4 Channel 3 Channel 2 Channel 1 SCLK SDOUT MSB LSB MSB LSB MSB LSB LSB MSB Figure 2g TDM DSP/PCM Mode A Serial Audio Data Format LRCK Channel 4 Channel 3 Channel 2 Channel 1 SCLK SDOUT MSB LSB MSB LSB MSB LSB MSB LSB Figure 2h TDM DSP/PCM Mode B Serial Audio Data Format Revision 9.1 6 January 2019 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES7210 6. ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Continuous operation at or beyond these conditions may permanently damage the device. PARAMETER Analog Supply Voltage Level Digital Supply Voltage Level Analog Input Voltage Range Digital Input Voltage Range Operating Temperature Range Storage Temperature MIN -0.3V -0.3V GNDA-0.3V GNDD-0.3V -40C -65C MAX +3.6V +3.6V VDDA+0.3V VDDP+0.3V +85C +150C RECOMMENDED OPERATING CONDITIONS PARAMETER MIN TYP VDDD 1.6 3.3 VDDP 1.6 3.3 VDDA 1.6 (Note) 3.3 VDDM 1.6 3.3 Note: For VDDA is less than 2V, PGA gain must set above 30 dB. MAX 3.6 3.6 3.6 3.6 UNIT V V V V ADC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS Test conditions are as the following unless otherwise specify: VDDA=3.3V, VDDD=3.3V, AGND=0V, DGND=0V, Ambient temperature=25C, Fs=48 KHz, 96 KHz or 192 KHz, MCLK/LRCK=256. PARAMETER ADC Performance Signal to Noise ratio (A-weigh) THD+N Channel Separation (1KHz) Interchannel Gain Mismatch Gain Error Filter Frequency Response – Single Speed Passband Stopband Passband Ripple Stopband Attenuation Filter Frequency Response – Double Speed Passband Stopband Passband Ripple Stopband Attenuation Filter Frequency Response – Quad Speed Passband Revision 9.1 MIN TYP MAX UNIT 95 -88 95 102 -85 100 0.1 104 -75 105 dB dB dB dB % ±5 0 0.5465 0.4535 ±0.05 70 0 0.5833 0.4167 ±0.005 70 0 0.2083 Fs Fs dB dB Fs Fs dB dB Fs 7 January 2019 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential Stopband Passband Ripple Stopband Attenuation Analog Input Full Scale Input Level Input Impedance ES7210 0.7917 Fs dB dB ±0.005 70 AVDD/3.3 6 Vrms KΩ DC CHARACTERISTICS PARAMETER Normal Operation Mode (Fs=16 KHz) VDDD=1.8V, VDDP=1.8V, VDDA=3.3V VDDD=1.8V, VDDP=1.8V, VDDA=1.8V Power Down Mode VDDD=1.8V, VDDP=1.8V, VDDA=3.3V Digital Voltage Level Input High-level Voltage Input Low-level Voltage Output High-level Voltage Output Low-level Voltage MIN TYP MAX UNIT 63 24 mW 10 uA 0.7*VDDP V V V V 0.5 VDDP 0 SERIAL AUDIO PORT SWITCHING SPECIFICATIONS PARAMETER MCLK frequency MCLK duty cycle LRCK frequency LRCK duty cycle SCLK frequency SCLK pulse width low SCLK Pulse width high SCLK falling to LRCK edge SCLK falling to SDOUT valid Symbol MIN 40 40 TSCLKL TSCLKH TSLR TSDO 15 15 –10 11 MAX 51.2 60 200 60 26 10 UNIT MHz % KHz % MHz ns ns ns ns Figure 3 Serial Audio Port Timing Revision 9.1 8 January 2019 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES7210 I2C SWITCHING SPECIFICATIONS PARAMETER CCLK Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time Clock Low time Clock High Time Setup Time for Repeated Start Condition CDATA Hold Time from CCLK Falling CDATA Setup time to CCLK Rising Rise Time of CCLK Fall Time CCLK Symbol FCCLK TTWID TTWSTH TTWCL TTWCH TTWSTS TTWDH TTWDS TTWR TTWF MIN MAX 400 1.3 0.6 1.3 0.4 0.6 900 100 300 300 UNIT KHz us us us us us ns ns ns ns Figure 4 I2C Timing Revision 9.1 9 January 2019 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES7210 7. PACKAGE Revision 9.1 10 January 2019 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES7210 8. CORPORATE INFORMATION Everest Semiconductor Co., Ltd. No. 1355 Jinjihu Drive, Suzhou Industrial Park, Jiangsu, P.R. China, Zip Code 215021 苏州工业园区金鸡湖大道 1355 号国际科技园, 邮编 215021 Email: info@everest-semi.com Revision 9.1 11 January 2019 Latest datasheet: www.everest-semi.com or info@everest-semi.com