ES7240S

ES7240S High Performance Stereo Audio ADC FEATURES APPLICATIONS • • • • • • • • • • • • • High performance multi-bit delta-sigma audio ADC 100 dB signal to noise ratio -85 dB THD+N 24-bit, 8 to 200 kHz sampling frequency I2S/LJ master or slave serial data port 256/384Fs and other non standard audio system clocks Low power standby mode Soundbar Audio Interface Digital TV A/V Receiver DVR NVR ORDERING INFORMATION ES7240S -40°C ~ +85°C TSSOP-16 BLOCK DIAGRAM AINL AINR Multi-bit Delta-sigma Modulator DSP Clock Manager Sample Rate Detector Audio Data Interface Control Interface MCLK M1 M0 1 SDOUT SCLK LRCK Everest Semiconductor 1. 2. 3. 4. 5. 6. Confidential ES7240S PIN OUT AND DESCRIPTION ................................................................................................ 3 TYPICAL APPLICATION CIRCUIT.......................................................................................... 4 CLOCK MODES AND SAMPLING FREQUENCIES ............................................................... 5 POWER UP AND POWER DOWN .......................................................................................... 5 DIGITAL AUDIO INTERFACE.................................................................................................. 5 ELECTRICAL CHARACTERISTICS ....................................................................................... 6 ABSOLUTE MAXIMUM RATINGS.................................................................................................. 6 RECOMMENDED OPERATING CONDITIONS ................................................................................ 6 ADC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS .......................................... 6 POWER CONSUMPTION CHARACTERISTICS ................................................................................ 7 SERIAL AUDIO PORT SWITCHING SPECIFICATIONS ..................................................................... 7 7. 8. PACKAGE ................................................................................................................................ 9 CORPORATE INFORMATION .............................................................................................. 10 Revision 8.0 2 September 2018 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES7240S 1. PIN OUT AND DESCRIPTION M0 MCLK VDDP SDOUT GNDD VDDD SCLK LRCK 1 2 3 4 5 6 7 8 ES7240S 16 15 14 13 12 11 10 9 M1 REFP GNDA VDDA AINR REFQ AINL RESETb Pin Name Pin number Input or Output Pin Description M0, M1 MCLK SCLK LRCK SDOUT RESETb AINL, AINR VDDP VDDD/GNDD VDDA/GNDA REFP REFQ 1, 16 2 7 8 4 9 10,12 3 6, 5 13, 14 15 11 I I I/O I/O O I I I I I O O Mode selection Master clock Serial data bit clock Serial data left and right channel frame clock Serial data output Active low chip reset (low power) Analog left and right inputs Power supply for the digital input and output Digital power supply Analog power supply Filtering capacitor connection Filtering capacitor connection Revision 8.0 3 September 2018 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES7240S 2. TYPICAL APPLICATION CIRCUIT For the best performance,decoupling and filtering capacitors should be located as close to the device package as possible Additional parallel capacitors(typically 0.1 μF) can be used, larger value capacitors(typically 10 μF) would also help * AGND AGND * * 100nF PVDD(+3V3) DVDD(+3V3) AGND CPU/DSP 100nF 3 6 ES7240S 5 GNDD VDDP VDDD 9 1 16 RESETb M0 M1 2 7 8 4 MCLK SCLK LRCK SDOUT VDDA 13 GNDA 14 REFP 15 REFQ 11 AINR AINL 1uF * AVDD(+3V3) *1uF* AGND 1uF 1uF 12 RIN 10 LIN 1uF 10K Everest GND(SYS) PVDD(+3V3) These formats are I2S (pull up resistor at SDOUT pin) and left justified (pull down resistor at SDOUT pin) Revision 8.0 0R AGND In the layout, chip is treated as an analog device 4 September 2018 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES7240S 3. CLOCK MODES AND SAMPLING FREQUENCIES The device can work either in master clock mode or slave clock mode by setting mode control pins M1 and M0 according to Table 1. Table 1 Mode Control Pin M1:M0 Pin Description 00 – master clock mode, single speed mode 01 – master clock mode, double speed mode 10 – master clock mode, quad speed mode 11 – slave clock mode, all speed modes In master mode, LRCK and SCLK are derived internally from MCLK. The available MCLK/LRCK ratios are listed in Table 2. SCLK/LRCK ratio is always 64 in master mode. Table 2 Master Mode Sampling Frequencies and MCLK/LRCK Ratio Speed Mode Single Speed Double Speed Quad Speed Sampling Frequency 8kHz – 50kHz 50kHz – 100kHz 100kHz – 200kHz MCLK/LRCK Ratio 256 128 64 In slave mode, LRCK and SCLK are supplied externally. LRCK and SCLK must be synchronously derived from the system clock with some specific rates. The device can auto detect MCLK/LRCK ratio according to Table 3. The device only supports the MCLK/LRCK ratios listed in Table 3. The SCLK/LRCK ratio is normally 64. Table 3 Slave Mode Sampling Frequencies and MCLK/LRCK Ratio Speed Mode Single Speed Double Speed Quad Speed Sampling Frequency 8kHz – 50kHz 50kHz – 100kHz 100kHz – 200kHz MCLK/LRCK Ratio 256, 384, 512, 768, 1024 128, 192 64 4. POWER UP AND POWER DOWN RESETb pin active low will put the device in power down mode. During power-up, RESETb pin should be hold at low level to keep the device in reset until the power supplies, clocks and mode selection pins are stable. 5. DIGITAL AUDIO INTERFACE The device provides many formats of serial audio data interface to the output from the ADC through LRCK, SCLK and SDOUT pins. These formats are I2S (pull up resistor at SDOUT pin) and left justified (pull down resistor at SDOUT pin). ADC data is out at SDOUT on the falling edge of Revision 8.0 5 September 2018 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES7240S SCLK. The relationships of SDOUT (SDATA), SCLK and LRCK with these formats are shown through Figure 1 to Figure 2. 1 SCLK SDATA 1 2 1 SCLK n-2 n-1 3 MSB n 1 LSB MSB 2 3 n-2 n-1 n LSB SCLK LEFT CHANNEL LRCK RIGHT CHANNEL Figure 1 I2S Serial Audio Data Format Up To 24-bit SDATA 1 2 3 n-2 n-1 MSB n 1 LSB MSB 2 3 n-2 n-1 n LSB SCLK LRCK RIGHT CHANNEL LEFT CHANNEL Figure 2 Left Justified Serial Audio Data Format Up To 24-bit 6. ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Continuous operation at or beyond these conditions may permanently damage the device. PARAMETER Analog Supply Voltage Level Digital Supply Voltage Level Input Voltage Range Operating Temperature Range Storage Temperature MIN -0.3V -0.3V DGND-0.3V -40°C -65°C MAX +5.0V +5.0V DVDD+0.3V +85°C +150°C RECOMMENDED OPERATING CONDITIONS PARAMETER VDDA VDDD VDDP MIN 3.0 3.0 1.6 TYP 3.3 3.3 3.3 MAX 3.6 3.6 3.6 UNIT V V V ADC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS Test conditions are as the following unless otherwise specify: VDDA=3.3V, VDDD=3.3V, AGND=0V, DGND=0V, Ambient temperature=25°C, Fs=48 KHz, 96 KHz or 192 KHz, MCLK/LRCK=256. PARAMETER ADC Performance Signal to Noise ratio (A-weigh) Revision 8.0 MIN TYP MAX UNIT 95 100 104 dB 6 September 2018 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential THD+N Channel Separation (1KHz) Interchannel Gain Mismatch Gain Error Filter Frequency Response – Single Speed Passband Stopband Passband Ripple Stopband Attenuation Filter Frequency Response – Double Speed Passband Stopband Passband Ripple Stopband Attenuation Filter Frequency Response – Quad Speed Passband Stopband Passband Ripple Stopband Attenuation Analog Input Full Scale Input Level Input Impedance -88 95 ES7240S -85 100 0.1 -75 105 ±5 0 0.5465 0.4535 ±0.05 70 0 0.5833 0.4167 ±0.005 70 0 0.7917 0.2083 ±0.005 70 AVDD/3.3 20 dB dB dB % Fs Fs dB dB Fs Fs dB dB Fs Fs dB dB Vrms KΩ POWER CONSUMPTION CHARACTERISTICS PARAMETER Normal Operation Mode VDDD=3.3V, VDDP=3.3V, VDDA=3.3V Power Down Mode VDDD=3.3V, VDDP=3.3V, VDDA=3.3V MIN TYP MAX UNIT 30 mA 28 uA SERIAL AUDIO PORT SWITCHING SPECIFICATIONS PARAMETER MCLK frequency MCLK duty cycle LRCK frequency LRCK duty cycle SCLK frequency SCLK pulse width low SCLK Pulse width high SCLK falling to LRCK edge SCLK falling to SDOUT valid Revision 8.0 Symbol MIN 40 40 TSCLKL TSCLKH TSLR TSDO 15 15 –10 11 MAX 51.2 60 200 60 26 10 UNIT MHz % KHz % MHz ns ns ns ns 7 September 2018 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES7240S Figure 4 Serial Audio Port Timing Revision 8.0 8 September 2018 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES7240S 7. PACKAGE Revision 8.0 9 September 2018 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES7240S 8. CORPORATE INFORMATION Everest Semiconductor Co., Ltd. No. 1355 Jinjihu Drive, Suzhou Industrial Park, Jiangsu, P.R. China, Zip Code 215021 苏州工业园区金鸡湖大道 1355 号国际科技园, 邮编 215021 Email: info@everest-semi.com Revision 8.0 10 September 2018 Latest datasheet: www.everest-semi.com or info@everest-semi.com