RTL8367RB-CG
LAYER 2 MANAGED 5+2-PORT 10/100/1000M SWITCH CONTROLLER
DATASHEET
(CONFIDENTIAL: Development Partners Only)
Rev. 1.0
09 June 2011
Track ID: JATR-2265-11
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211 Fax: +886-3-577-6047
www.realtek.com
RTL8367RB
Datasheet
COPYRIGHT
©2011 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the hardware and software engineer’s general information on the Realtek
RTL8367RB IC.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.
REVISION HISTORY
Revision
1.0
Release Date
2011/06/09
Summary
First release.
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
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RTL8367RB
Datasheet
Table of Contents
1.
GENERAL DESCRIPTION ..............................................................................................................................................1
2.
FEATURES .........................................................................................................................................................................3
3.
SYSTEM APPLICATIONS...............................................................................................................................................5
4.
APPLICATION EXAMPLES ...........................................................................................................................................6
4.1.
4.2.
5-PORT 1000BASE-T SWITCH ......................................................................................................................................6
5-PORT 1000BASE-T ROUTER WITH DUAL MII/RGMII...............................................................................................7
5.
BLOCK DIAGRAM ...........................................................................................................................................................8
6.
PIN ASSIGNMENTS .........................................................................................................................................................9
6.1.
6.2.
7.
PACKAGE IDENTIFICATION ...........................................................................................................................................9
PIN ASSIGNMENT TABLE ............................................................................................................................................10
PIN DESCRIPTIONS.......................................................................................................................................................13
7.1.
MEDIA DEPENDENT INTERFACE PINS .........................................................................................................................13
7.2.
GENERAL PURPOSE INTERFACES ................................................................................................................................14
7.2.1. RGMII Pins...........................................................................................................................................................14
7.2.2. MII Pins................................................................................................................................................................16
7.3.
LED PINS ...................................................................................................................................................................19
7.4.
CONFIGURATION STRAPPING PINS .............................................................................................................................20
7.5.
CONFIGURATION STRAPPING PINS (DISAUTOLOAD AND DIS_8051).....................................................................22
7.6.
MANAGEMENT INTERFACE PINS ................................................................................................................................22
7.7.
MISCELLANEOUS PINS ...............................................................................................................................................23
7.8.
TEST PINS ..................................................................................................................................................................23
7.9.
POWER AND GND PINS ..............................................................................................................................................23
8.
PHYSICAL LAYER FUNCTIONAL OVERVIEW......................................................................................................24
8.1.
8.2.
8.3.
8.4.
8.5.
8.6.
8.7.
8.8.
8.9.
8.10.
9.
MDI INTERFACE ........................................................................................................................................................24
1000BASE-T TRANSMIT FUNCTION ...........................................................................................................................24
1000BASE-T RECEIVE FUNCTION ..............................................................................................................................24
100BASE-TX TRANSMIT FUNCTION...........................................................................................................................24
100BASE-TX RECEIVE FUNCTION .............................................................................................................................25
10BASE-T TRANSMIT FUNCTION ...............................................................................................................................25
10BASE-T RECEIVE FUNCTION ..................................................................................................................................25
AUTO-NEGOTIATION FOR UTP ..................................................................................................................................25
CROSSOVER DETECTION AND AUTO CORRECTION .....................................................................................................26
POLARITY CORRECTION .............................................................................................................................................26
GENERAL FUNCTION DESCRIPTION......................................................................................................................27
9.1.
RESET ........................................................................................................................................................................27
9.1.1. Hardware Reset ....................................................................................................................................................27
9.1.2. Software Reset ......................................................................................................................................................27
9.2.
IEEE 802.3X FULL DUPLEX FLOW CONTROL ............................................................................................................27
9.3.
HALF DUPLEX FLOW CONTROL .................................................................................................................................28
9.3.1. Back-Pressure Mode ............................................................................................................................................28
9.4.
SEARCH AND LEARNING ............................................................................................................................................29
9.5.
SVL AND IVL/SVL ...................................................................................................................................................29
9.6.
ILLEGAL FRAME FILTERING .......................................................................................................................................29
9.7.
IEEE 802.3 RESERVED GROUP ADDRESSES FILTERING CONTROL .............................................................................30
9.8.
BROADCAST/MULTICAST/UNKNOWN DA STORM CONTROL .....................................................................................31
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PORT SECURITY FUNCTION ........................................................................................................................................31
9.9.
9.10.
MIB COUNTERS .........................................................................................................................................................31
9.11.
PORT MIRRORING ......................................................................................................................................................31
9.12.
VLAN FUNCTION ......................................................................................................................................................32
9.12.1.
Port-Based VLAN ............................................................................................................................................32
9.12.2.
IEEE 802.1Q Tag-Based VLAN.......................................................................................................................32
9.12.3.
Protocol-Based VLAN .....................................................................................................................................33
9.12.4.
Port VID ..........................................................................................................................................................33
9.13.
QOS FUNCTION ..........................................................................................................................................................34
9.13.1.
Input Bandwidth Control .................................................................................................................................34
9.13.2.
Priority Assignment .........................................................................................................................................34
9.13.3.
Priority Queue Scheduling...............................................................................................................................35
9.13.4.
IEEE 802.1p/Q and DSCP Remarking ............................................................................................................35
9.13.5.
ACL-Based Priority .........................................................................................................................................36
9.14.
IGMP & MLD SNOOPING FUNCTION.........................................................................................................................36
9.15.
IEEE 802.1X FUNCTION .............................................................................................................................................36
9.15.1.
Port-Based Access Control..............................................................................................................................36
9.15.2.
Authorized Port-Based Access Control ...........................................................................................................37
9.15.3.
Port-Based Access Control Direction..............................................................................................................37
9.15.4.
MAC-Based Access Control.............................................................................................................................37
9.15.5.
MAC-Based Access Control Direction ............................................................................................................37
9.15.6.
Optional Unauthorized Behavior.....................................................................................................................37
9.15.7.
Guest VLAN .....................................................................................................................................................37
9.16.
IEEE 802.1D FUNCTION ............................................................................................................................................38
9.17.
EMBEDDED 8051........................................................................................................................................................38
9.18.
REALTEK CABLE TEST (RTCT) .................................................................................................................................38
9.19.
LED INDICATORS.......................................................................................................................................................39
9.20.
GREEN ETHERNET ......................................................................................................................................................40
9.20.1.
Link-On and Cable Length Power Saving .......................................................................................................40
9.20.2.
Link-Down Power Saving ................................................................................................................................40
9.21.
IEEE 802.3AZ ENERGY EFFICIENT ETHERNET (EEE) FUNCTION ...............................................................................41
9.22.
INTERRUPT PIN FOR EXTERNAL CPU .........................................................................................................................41
10.
INTERFACE DESCRIPTIONS .................................................................................................................................42
10.1.
EEPROM SMI HOST TO EEPROM ...........................................................................................................................42
10.2.
EEPROM SMI SLAVE FOR EXTERNAL CPU..............................................................................................................43
10.3.
GENERAL PURPOSE INTERFACE..................................................................................................................................44
10.3.1.
Extension Ports RGMII Mode (1Gbps)............................................................................................................45
10.3.2.
Extension Ports MII MAC/PHY Mode Interface (10/100Mbps) ......................................................................46
11.
REGISTER DESCRIPTIONS ....................................................................................................................................48
11.1.
11.2.
11.3.
11.4.
11.5.
11.6.
11.7.
11.8.
11.9.
11.10.
11.11.
11.12.
11.13.
PCS REGISTER (PHY 0~4).........................................................................................................................................48
REGISTER 0: CONTROL ...............................................................................................................................................49
REGISTER 1: STATUS ..................................................................................................................................................50
REGISTER 2: PHY IDENTIFIER 1 .................................................................................................................................51
REGISTER 3: PHY IDENTIFIER 2 .................................................................................................................................51
REGISTER 4: AUTO-NEGOTIATION ADVERTISEMENT .................................................................................................51
REGISTER 5: AUTO-NEGOTIATION LINK PARTNER ABILITY.......................................................................................52
REGISTER 6: AUTO-NEGOTIATION EXPANSION ..........................................................................................................53
REGISTER 7: AUTO-NEGOTIATION PAGE TRANSMIT REGISTER ..................................................................................53
REGISTER 8: AUTO-NEGOTIATION LINK PARTNER NEXT PAGE REGISTER ............................................................54
REGISTER 9: 1000BASE-T CONTROL REGISTER ....................................................................................................54
REGISTER 10: 1000BASE-T STATUS REGISTER .....................................................................................................55
REGISTER 15: EXTENDED STATUS .........................................................................................................................55
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12.
ELECTRICAL CHARACTERISTICS......................................................................................................................56
12.1.
ABSOLUTE MAXIMUM RATINGS ................................................................................................................................56
12.2.
RECOMMENDED OPERATING RANGE..........................................................................................................................56
12.3.
THERMAL CHARACTERISTICS.....................................................................................................................................57
12.3.1.
Assembly Description ......................................................................................................................................57
12.3.2.
Material Properties .........................................................................................................................................57
12.3.3.
Simulation Conditions .....................................................................................................................................57
12.3.4.
Thermal Performance of E-Pad LQFP-128 on PCB Under Still Air Convection ...........................................58
12.3.5.
Thermal Performance of E-Pad LQFP-128 on PCB Under Forced Convection ............................................58
12.4.
DC CHARACTERISTICS ...............................................................................................................................................59
12.5.
AC CHARACTERISTICS ...............................................................................................................................................60
12.5.1.
EEPROM SMI Host Mode Timing Characteristics .........................................................................................60
12.5.2.
EEPROM SMI Slave Mode Timing Characteristics ........................................................................................61
12.5.3.
MDIO Slave Mode Timing Characteristics .....................................................................................................62
12.5.4.
MII MAC Mode Timing ...................................................................................................................................63
12.5.5.
MII PHY Mode Timing ....................................................................................................................................64
12.5.6.
RGMII Timing Characteristics ........................................................................................................................65
12.6.
POWER AND RESET CHARACTERISTICS ......................................................................................................................67
13.
MECHANICAL DIMENSIONS.................................................................................................................................68
14.
ORDERING INFORMATION ...................................................................................................................................69
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List of Tables
TABLE 1. PIN ASSIGNMENT TABLE ..............................................................................................................................................10
TABLE 2. MEDIA DEPENDENT INTERFACE PINS ...........................................................................................................................13
TABLE 3. EXTENSION GMAC1 RGMII PINS ...............................................................................................................................14
TABLE 4. EXTENSION GMAC2 RGMII PINS ...............................................................................................................................15
TABLE 5. EXTENSION GMAC1 MII PINS (MII MAC MODE OR MII PHY MODE).......................................................................16
TABLE 6. EXTENSION GMAC2 MII PINS (MII MAC MODE OR MII PHY MODE).......................................................................17
TABLE 7. LED PINS .....................................................................................................................................................................19
TABLE 8. CONFIGURATION STRAPPING PINS................................................................................................................................20
TABLE 9. CONFIGURATION STRAPPING PINS (DISAUTOLOAD AND DIS_8051).......................................................................22
TABLE 10. MANAGEMENT INTERFACE PINS ..................................................................................................................................22
TABLE 11. MISCELLANEOUS PINS .................................................................................................................................................23
TABLE 12. TEST PINS ....................................................................................................................................................................23
TABLE 13. POWER AND GND PINS ................................................................................................................................................23
TABLE 14. MEDIA DEPENDENT INTERFACE PIN MAPPING.............................................................................................................26
TABLE 15. RESERVED MULTICAST ADDRESS CONFIGURATION TABLE .........................................................................................30
TABLE 16. LED DEFINITIONS........................................................................................................................................................39
TABLE 17. RTL8367RB EXTENSION PORT 1 PIN DEFINITIONS .....................................................................................................44
TABLE 18. RTL8367RB EXTENSION PORT 2 PIN DEFINITIONS .....................................................................................................44
TABLE 19. EXTENSION GMAC1 RGMII PINS ...............................................................................................................................45
TABLE 20. EXTENSION GMAC2 RGMII PINS ...............................................................................................................................45
TABLE 21. EXTENSION GMAC1 MII PINS ....................................................................................................................................46
TABLE 22. EXTENSION GMAC2 MII PINS ....................................................................................................................................46
TABLE 23. PCS REGISTER (PHY 0~4)...........................................................................................................................................48
TABLE 24. REGISTER 0: CONTROL ................................................................................................................................................49
TABLE 25. REGISTER 1: STATUS....................................................................................................................................................50
TABLE 26. REGISTER 2: PHY IDENTIFIER 1...................................................................................................................................51
TABLE 27. REGISTER 3: PHY IDENTIFIER 2...................................................................................................................................51
TABLE 28. REGISTER 4: AUTO-NEGOTIATION ADVERTISEMENT ...................................................................................................51
TABLE 29. REGISTER 5: AUTO-NEGOTIATION LINK PARTNER ABILITY ........................................................................................52
TABLE 30. REGISTER 6: AUTO-NEGOTIATION EXPANSION ............................................................................................................53
TABLE 31. REGISTER 7: AUTO-NEGOTIATION PAGE TRANSMIT REGISTER....................................................................................53
TABLE 32. REGISTER 8: AUTO-NEGOTIATION LINK PARTNER NEXT PAGE REGISTER ...................................................................54
TABLE 33. REGISTER 9: 1000BASE-T CONTROL REGISTER ...........................................................................................................54
TABLE 34. REGISTER 10: 1000BASE-T STATUS REGISTER ............................................................................................................55
TABLE 35. REGISTER 15: EXTENDED STATUS ...............................................................................................................................55
TABLE 36. ABSOLUTE MAXIMUM RATINGS ..................................................................................................................................56
TABLE 37. RECOMMENDED OPERATING RANGE ...........................................................................................................................56
TABLE 38. ASSEMBLY DESCRIPTION .............................................................................................................................................57
TABLE 39. MATERIAL PROPERTIES ...............................................................................................................................................57
TABLE 40. SIMULATION CONDITIONS ...........................................................................................................................................57
TABLE 41. THERMAL PERFORMANCE OF E-PAD LQFP-128 ON PCB UNDER STILL AIR CONVECTION .........................................58
TABLE 42. THERMAL PERFORMANCE OF E-PAD LQFP-128 ON PCB UNDER FORCED CONVECTION ............................................58
TABLE 43. DC CHARACTERISTICS .................................................................................................................................................59
TABLE 44. EEPROM SMI HOST MODE TIMING CHARACTERISTICS .............................................................................................61
TABLE 45. EEPROM SMI SLAVE MODE TIMING CHARACTERISTICS ...........................................................................................61
TABLE 46. MDIO TIMING CHARACTERISTICS AND REQUIREMENT ...............................................................................................62
TABLE 47. MII MAC MODE TIMING .............................................................................................................................................63
TABLE 48. MII PHY MODE TIMING CHARACTERISTICS ................................................................................................................64
TABLE 49. RGMII TIMING CHARACTERISTICS ..............................................................................................................................66
TABLE 50. POWER AND RESET CHARACTERISTICS ........................................................................................................................67
TABLE 51. ORDERING INFORMATION ............................................................................................................................................69
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List of Figures
FIGURE 1. 5-PORT 1000BASE-T SWITCH .......................................................................................................................................6
FIGURE 2. 5-PORT 1000BASE-T ROUTER WITH DUAL MII/RGMII................................................................................................7
FIGURE 3. BLOCK DIAGRAM ..........................................................................................................................................................8
FIGURE 4. PIN ASSIGNMENTS (LQFP-128 EPAD).........................................................................................................................9
FIGURE 5. CONCEPTUAL EXAMPLE OF POLARITY CORRECTION ..................................................................................................26
FIGURE 6. PROTOCOL-BASED VLAN FRAME FORMAT AND FLOW CHART ..................................................................................33
FIGURE 7. RTL8367RB MAX-MIN SCHEDULING DIAGRAM ......................................................................................................35
FIGURE 8. PULL-UP AND PULL-DOWN OF LED PINS FOR SINGLE-COLOR LED...........................................................................40
FIGURE 9. PULL-UP AND PULL-DOWN OF LED PINS FOR BI-COLOR LED...................................................................................40
FIGURE 10. SMI START AND STOP COMMAND ..............................................................................................................................42
FIGURE 11. EEPROM SMI HOST TO EEPROM............................................................................................................................42
FIGURE 12. EEPROM SMI HOST MODE FRAME...........................................................................................................................42
FIGURE 13. EEPROM SMI WRITE COMMAND FOR SLAVE MODE ................................................................................................43
FIGURE 14. EEPROM SMI READ COMMAND FOR SLAVE MODE ..................................................................................................43
FIGURE 15. RGMII MODE INTERFACE SIGNAL DIAGRAM .............................................................................................................45
FIGURE 16. SIGNAL DIAGRAM OF MII PHY MODE INTERFACE (100MBPS) ..................................................................................47
FIGURE 17. SIGNAL DIAGRAM OF MII MAC MODE INTERFACE (100MBPS) .................................................................................47
FIGURE 18. EEPROM SMI HOST MODE TIMING CHARACTERISTICS ............................................................................................60
FIGURE 19. SCK/SDA POWER ON TIMING ....................................................................................................................................60
FIGURE 20. EEPROM AUTO-LOAD TIMING..................................................................................................................................60
FIGURE 21. EEPROM SMI SLAVE MODE TIMING CHARACTERISTICS ..........................................................................................61
FIGURE 22. MDIO SOURCED BY MASTER .....................................................................................................................................62
FIGURE 23. MDIO SOURCED BY RTL8367RB (SLAVE)................................................................................................................62
FIGURE 24. MII MAC MODE CLOCK TO DATA OUTPUT DELAY TIMING ......................................................................................63
FIGURE 25. MII MAC MODE INPUT TIMING .................................................................................................................................63
FIGURE 26. MII PHY MODE OUTPUT TIMING ...............................................................................................................................64
FIGURE 27. MII PHY MODE CLOCK OUTPUT TO DATA INPUT DELAY TIMING .............................................................................64
FIGURE 28. RGMII OUTPUT TIMING CHARACTERISTICS (RGX_TXCLK_DELAY=0) ................................................................65
FIGURE 29. RGMII OUTPUT TIMING CHARACTERISTICS (RGX_TXCLK_DELAY=2NS) ............................................................65
FIGURE 30. RGMII INPUT TIMING CHARACTERISTICS (RGX_RXCLK_DELAY=0)....................................................................65
FIGURE 31. RGMII INPUT TIMING CHARACTERISTICS (RGX_RXCLK_DELAY=2NS)................................................................66
FIGURE 32. POWER AND RESET CHARACTERISTICS .......................................................................................................................67
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1. General Description
The RTL8367RB-CG is a LQFP128 EPAD, high-performance 5+2-port Gigabit Ethernet switch. The
RTL8367RB features a low-power integrated 5-port Giga-PHY that supports 1000Base-T, 100Base-TX,
and 10Base-T.
For specific applications, the RTL8367RB supports two extra interfaces that could be configured as
RGMII/MII interfaces. The RTL8367RB integrates all the functions of a high-speed switch system;
including SRAM for packet buffering, non-blocking switch fabric, and internal register management into
a single CMOS device. Only a 25MHz crystal is required; an optional EEPROM is offered for internal
register configuration.
The embedded packet storage SRAM in the RTL8367RB features superior memory management
technology to efficiently utilize memory space. The RTL8367RB integrates a 2K-entry look-up table with
a 4-way XOR Hashing algorithm for address searching and learning. The table provides read/write access
from the EEPROM Serial Management Interface (SMI), Media Independent Interface Management
(MIIM), or SPI Interface. Each of the table entries can be configured as a static entry. The entry aging
time is between 200 and 400 seconds. Eight Filtering Databases are used to provide Independent VLAN
Learning and Shared VLAN Learning (IVL/SVL) functions.
The Extension GMAC1 and Extension GMAC2 of the RTL8367RB implement dual RGMII/MII
interfaces. These interfaces could be connected to an external PHY, MAC, CPU, or RISC for specific
applications. In router applications, the RTL8367RB supports Port VID (PVID) for each port to insert a
PVID in the VLAN tag on egress. When using this function, VID information carried in the VLAN tag
will be changed to PVID.
Note: The RTL8367RB Extra Interface (Extension GMAC1 and Extension GMAC2) supports:
Dual-Port Reduced Gigabit Media Independent Interface (RGMII)
Dual-Port Media Independent Interface (MII)
The RTL8367RB supports standard 802.3x flow control frames for full duplex, and optional backpressure
for half duplex. It determines when to invoke the flow control mechanism by checking the availability of
system resources, including the packet buffers and transmitting queues. The RTL8367RB supports
broadcast/multicast output dropping, and will forward broadcast/multicast packets to non-blocked ports
only. For IP multicast applications, the RTL8367RB supports IPv4 IGMPv1/v2/v3 and IPv6 MLDv1/v2
snooping.
In order to support flexible traffic classification, the RTL8367RB supports 64-entry ACL rule check and
multiple actions options. Each port can optionally enable or disable the ACL rule check function. The
ACL rule key can be based on packet physical port, Layer2, Layer3, and Layer4 information. When an
ACL rule matches, the action taken is configurable to Drop/Permit/Redirect/Mirror, change priority value
in 802.1q/Q tag, and rate policing. The rate policing mechanism supports from 8Kbps to 1Gbps (in 8Kbps
steps).
In Bridge operation the RTL8367RB supports 16 sets of port configurations: disable, block, learning, and
forwarding for Spanning Tree Protocol and Multiple Spanning Tree Protocol. To meet security and
management application requirements, the RTL8367RB supports IEEE 802.1x Port-based/MAC-based
Access Control. For those ports that do not pass IEEE 802.1x authentication, the RTL8367RB provides a
Port-based/MAC-based Guest VLAN function for them to access limited network resources. A 1-set Port
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Mirroring function is configured to mirror traffic (RX, TX, or both) appearing on one of the switch’s
ports. Support is provided on each port for multiple RFC MIB Counters, for easy debug and diagnostics.
To improve real-time or multimedia networking applications, the RTL8367RB supports eight priority
assignments for each received packet. These are based on (1) Port-based priority; (2) 802.1p/Q VLAN tag
priority; (3) DSCP field in IPv4/IPv6 header; and (4) ACL-assigned priority. Each output port supports a
weighted ratio of eight priority queues to fit bandwidth requirements in different applications. The input
bandwidth control function helps limit per-port traffic utilization. There is one leaky bucket for average
packet rate control for each queue of all ports. Queue scheduling algorithm can use Strict Priority (SP) or
Weighted Fair Queue (WFQ) or mixed.
The RTL8367RB provides a 4K-entry VLAN table for 802.1Q port-based, tag-based, and protocol-based
VLAN operation to separate logical connectivity from physical connectivity. The RTL8367RB supports
four Protocol-based VLAN configurations that can optionally select EtherType, LLC, and RFC1042 as
the search key. Each port may be set to any topology via EEPROM upon reset, or EEPROM SMI Slave
after reset.
In router applications, the router may want to know the input port of the incoming packet. The
RTL8367RB supports an option to insert a VLAN tag with VID=Port VID (PVID) on each egress port.
The RTL8367RB also provides an option to admit VLAN tagged packet with a specific PVID only. If this
function is enabled, the RTL8367RB will drop all non-tagged packets and packets with an incorrect
PVID.
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2. Features
Embedded 5-port 10/100/1000Base-T PHY
Each port supports full duplex
10/100/1000M connectivity (half duplex
only supported in 10/100M mode)
Single-chip 5+2-port gigabit non-blocking
switch architecture
Supports 4K VLANs and 32 Extra
Enhanced VLANs
Supports Un-tag definition in each VLAN
Supports VLAN policing and VLAN
forwarding decision
Port-based, Tag-based, and Protocol-based
Extra Interface (Extension GMAC1 and
Extension GMAC2) supports
VLAN
Up to 4 Protocol-based VLAN entries
Dual-port Media Independent Interface
Per-port and per-VLAN egress VLAN
(MII)
tagging and un-tagging
Dual-port Reduced Gigabit Media
Independent Interface (RGMII)
Full-duplex and half-duplex operation with
IEEE 802.3x flow control and backpressure
Supports 9216-byte jumbo packet length
forwarding at wire speed
Realtek Cable Test (RTCT) function
Supports 64-entry ACL Rules
Supports IEEE 802.1Q VLAN
Supports IVL, SVL, and IVL/SVL
2K-entry MAC address table with 4-way
hash algorithm
Up to 2K L2/L3 Filtering Database
Per-port MAC learning limitation
Supports Spanning Tree Port Behavior
configuration
IEEE 802.1w Rapid Spanning Tree
Search keys support physical port, Layer2,
IEEE 802.1s Multiple Spanning Tree with
Layer3, and Layer4 information
up to 16 Spanning Tree instances
Actions include mirror, redirect, dropping,
priority adjustment, traffic policing,
CVLAN decision, and SVLAN
assignment GPIO control, interrupt and
logging counter
Supports IEEE 802.1x Access Control
Protocol
Port-Based Access Control
MAC-Based Access Control
Supports 5 types of user defined ACL rule
Guest VLAN
format for 64 ACL rules
Optional per-port enable/disable of ACL
Supports Auto protection from Denial-ofService attacks
Supports H/W IGMP/MLD Snooping
function
Optional setting of per-port action to take
when ACL mismatch
IGMPv1/v2/3 and MLD v1/v2
Supports Fast Leave
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Static router port configuration
Supports 2 IEEE 802.3ad Link aggregation
port groups
Supports Port Mirror function for one source
port to multiple destination ports
Supports OAM and EEE LLDP (Energy
Efficient Ethernet Link Layer Discovery
Protocol
Supports Loop Detection
Security Filtering
Dynamic router port learning and aging
Supports Quality of Service (QoS)
Supports per port Input Bandwidth Control
Traffic classification based on IEEE
802.1p/Q priority definition, physical Port,
IP DSCP field, ACL definition, VLAN
based priority, MAC based priority and
SVLAN based priority
Eight Priority Queues per port
Per queue flow control
Disable learning for each port
Min-Max Scheduling
Disable learning-table aging for each port
Strict Priority and Weighted Fair Queue
Drop unknown DA for each port
(WFQ) to provide minimum bandwidth
One leaky bucket to constrain the average
Broadcast/Multicast/Unknown DA storm
control protects system from attack by
hackers
Supports Realtek Green Ethernet features
packet rate of each queue
Supports rate limiting (64 shared meters,
with 8kpbs granulation)
Link-On Cable Length Power Saving
Supports RFC MIB Counter
Link-Down Power Saving
MIB-II (RFC 1213)
Ethernet-Like MIB (RFC 3635)
Interface Group MIB (RFC 2863)
RMON (RFC 2819)
Bridge MIB (RFC 1493)
Supports 1 interrupt output to external CPU
for notification
Each port supports 3 LED outputs
Management Interface Supports
EEPROM SMI Slave interface
Bridge MIB Extension (RFC 2674)
Media Independent Interface Management
Supports Stacking VLAN and Port Isolation
with 8 Enhanced Filtering Databases
(MIIM)
SPI Slave Interface
Supports IEEE 802.1ad Stacking VLAN
Supports 64 SVLANs
Supports 32 L2/IPv4 Multicast mappings
to SVLAN
Supports MAC-based 1:N VLAN
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
4
Supports 32K-byte EEPROM space for
configuration
Integrated 8051 microprocessor.
25MHz crystal or 3.3V OSC input
14x14 LQFP 128-pin E-PAD package
Track ID: JATR-2265-11 Rev. 1.0
RTL8367RB
Datasheet
3. System Applications
5-Port 1000Base-T Switch
5-Port 1000Base-T Router with Dual MII/RGMII
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
5
Track ID: JATR-2265-11 Rev. 1.0
RTL8367RB
Datasheet
4. Application Examples
4.1.
5-Port 1000Base-T Switch
Figure 1. 5-Port 1000Base-T Switch
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
6
Track ID: JATR-2265-11 Rev. 1.0
RTL8367RB
Datasheet
4.2.
5-Port 1000Base-T Router with Dual MII/RGMII
Figure 2. 5-Port 1000Base-T Router with Dual MII/RGMII
Note: Extra Interface (Extension GMAC1 and Extension GMAC2) in MII/RGMII Mode.
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
7
Track ID: JATR-2265-11 Rev. 1.0
RTL8367RB
Datasheet
5. Block Diagram
UTP
UTP
UTP
UTP
UTP
MII/RGMII
MII/RGMII
Giga-PHY
PCS
P0
GMAC
Giga-PHY
PCS
P1
GMAC
Giga-PHY
PCS
P2
GMAC
Giga-PHY
PCS
P3
GMAC
Giga-PHY
PCS
P4
GMAC
SRAM
Controller
Queue
Management
GMAC
1
Extension
Extension
Interface 2
GMAC
2
Linking Lists
2K MAC
Address Table
Extension
Extension
Interface 1
Packet Buffer
SRAM
Lookup
Engine
4096 VLAN
Table
GNIC
MAC
GNIC
8051
I2C
Host
PLL
Management
Interface
Control
Registers
+
MIB Counter
SPIS
SCK/SDA
MMD_MDC/MDIO
25MHz
Crystal
Figure 3. Block Diagram
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
8
Track ID: JATR-2265-11 Rev. 1.0
RTL8367RB
Datasheet
6. Pin Assignments
Figure 4. Pin Assignments (LQFP-128 EPAD)
6.1.
Package Identification
Green package is indicated by the ‘G’ in GXXXX (Figure 4).
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
9
Track ID: JATR-2265-11 Rev. 1.0
RTL8367RB
Datasheet
6.2.
Pin Assignment Table
Upon Reset: Defined as a short time after the end of a hardware reset.
After Reset: Defined as the time after the specified ‘Upon Reset’ time.
I: Input Pin
AI: Analog Input Pin
O: Output Pin
AO: Analog Output Pin
I/O: Bi-Directional Input/Output Pin
AI/O: Analog Bi-Directional Input/Output Pin
P: Digital Power Pin
AP: Analog Power Pin
G: Digital Ground Pin
AG: Analog Ground Pin
IPU: Input Pin With Pull-Up Resistor;
OPU: Output Pin With Pull-Up Resistor;
(Typical Value = 75K Ohm)
(Typical Value = 75K Ohm)
IS: Input Pin With Schmitt Trigger
Name
AVDDH
P3MDIAP
P3MDIAN
P3MDIBP
P3MDIBN
AVDDL
P3MDICP
P3MDICN
P3MDIDP
P3MDIDN
AVDDH
AGND
MDIREF
AVDDL
RTT1
RTT2
AVDDH
DVDDIO
INTERRUPT
DIS_LPD / BUZZER
DVDDL
RESERVED
AVDDH
P4MDIAP
Table 1. Pin Assignment Table
Pin No. Type
Name
Pin No.
1
AP
P4MDIAN
25
2
AI/O
P4MDIBP
26
3
AI/O
P4MDIBN
27
4
AI/O
AVDDL
28
5
AI/O
P4MDICP
29
6
AP
P4MDICN
30
7
AI/O
P4MDIDP
31
8
AI/O
P4MDIDN
32
9
AI/O
AVDDH
33
10
AI/O
PLLVDDL1
34
11
AP
RESERVED
35
12
AG
AVDDH
36
13
AO
RESERVED
37
14
AP
RESERVED
38
15
AO
DVDDIO_2
39
16
AO
E2_CRS/M2M_CRS/RESERVED
40
41
17
AP
E2_DO3/RG2_TXD3/M2M_TXD3/
M2P_RXD3
18
P
42
E2_DO2/RG2_TXD2/M2M_TXD2/
19
OPU
M2P_RXD2
20
I/OPU
43
E2_DO1/RG2_TXD1/M2M_TXD1/
21
P
M2P_RXD1
22
IPU
44
E2_DO0/RG2_TXD0/M2M_TXD0/
23
AP
M2P_RXD0
24
AI/O
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
10
Type
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AP
AO
AP
AO
AO
P
I
I/O
I/O
O
O
Track ID: JATR-2265-11 Rev. 1.0
RTL8367RB
Datasheet
Name
Pin No.
E2_DOEN/RG2_TXCTL/
45
M2M_TXEN/M2P_RXDV
E2_GOCLK/RG2_TXCLK/
46
M2M_TXCLK/M2P_RXCLK
E2_DICLK/RG2_RXCLK/
47
M2M_RXCLK/M2P_TXCLK
E2_DIDV/RG2_RXCTL/
48
M2M_RXDV/M2P_TXEN
49
E2_DI0/RG2_RXD0/M2M_RXD0/
M2P_TXD0
50
E2_DI1/RG2_RXD1/M2M_RXD1/
M2P_TXD1
51
E2_DI2/RG2_RXD2/M2M_RXD2/
M2P_TXD2
52
E2_DI3/RG2_RXD3/M2M_RXD3/
M2P_TXD3
DVDDL
53
DVDDIO_2
54
DVDDIO_1
55
E1_CRS/M1M_CRS
56
E1_DO3/RG1_TXD3/M1M_TXD3/
57
M1P_RXD3
58
E1_DO2/RG1_TXD2/M1M_TXD2/
M1P_RXD2
59
E1_DO1/RG1_TXD1/M1M_TXD1/
M1P_RXD1
60
E1_DO0/RG1_TXD0/M1M_TXD0/
M1P_RXD0
E1_DOEN/RG1_TXCTL/
61
M1M_TXEN/M1P_RXDV
E1_GOCLK/RG1_TXCLK/
62
M1M_TXCLK/M1P_RXCLK
E1_DICLK/RG1_RXCLK/
63
M1M_RXCLK/M1P_TXCLK
E1_DIDV/RG1_RXCTL/
64
M1M_RXDV/M1P_TXEN
65
E1_DI0/RG1_RXD0/M1M_RXD0/
M1P_TXD0
66
E1_DI1/RG1_RXD1/M1M_RXD1/
M1P_TXD1
67
E1_DI2/RG1_RXD2/M1M_RXD2/
M1P_TXD2
68
E1_DI3/RG1_RXD3/
M1M_RXD3/M1P_TXD3
DVDDIO_1
69
DVDDIO_0
70
DVDDL
71
Type
I/O
Name
P4LED2/DIS_SPIS
P4LED0/EEPROM_MOD
P4LED1
P3LED1
P3LED2/RESERVED
P3LED0/RESERVED
P2LED2/DIS_8051
P2LED0/DISAUTOLOAD
P2LED1
P1LED2/RESERVED
P1LED0/RESERVED
P1LED1
P0LED2/EN_PHY
P0LED1/LED_DA
P0LED0/LED_CK/SMI_SEL
DVDDL
AVDDH
XTALO
XTALI
nRESET
SPIS_CSI
SPIS_CK/SCK/MMD_MDC
SPIS_DI /SDA/MMD_MDIO
SPIS_DO
AVDDH
P0MDIAP
P0MDIAN
P0MDIBP
P0MDIBN
AVDDL
P0MDICP
P0MDICN
P0MDIDP
P0MDIDN
AVDDH
P1MDIAP
P1MDIAN
P1MDIBP
P1MDIBN
AVDDL
P1MDICP
P1MDICN
P1MDIDP
P1MDIDN
I/O
I/O
I
I/O
I/O
I/O
I/O
P
P
P
I
O
O
O
O
O
I/O
I/O
I
I
I
I
I
P
P
P
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
11
Pin No.
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
Type
I/OPU
I/OPU
I/OPU
I/OPU
I/OPU
I/OPU
I/OPU
I/OPU
I/OPU
I/OPU
I/OPU
I/OPU
I/OPU
I/OPU
I/OPU
P
AP
AO
AI
IS
I
I/OPU
I/OPU
O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
Track ID: JATR-2265-11 Rev. 1.0
RTL8367RB
Datasheet
Name
PLLVDDL0
ATESTCK0
PLLGND0
AVDDH
P2MDIAP
P2MDIAN
P2MDIBP
Pin No.
116
117
118
119
120
121
122
Type
AP
AO
AG
AP
AI/O
AI/O
AI/O
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
Name
P2MDIBN
AVDDL
P2MDICP
P2MDICN
P2MDIDP
P2MDIDN
GND
12
Pin No.
123
124
125
126
127
128
EPAD
Type
AI/O
AP
AI/O
AI/O
AI/O
AI/O
G
Track ID: JATR-2265-11 Rev. 1.0
RTL8367RB
Datasheet
7. Pin Descriptions
7.1.
Media Dependent Interface Pins
Pin Name
P0MDIAP/N
P0MDIBP/N
P0MDICP/N
P0MDIDP/N
P1MDIAP/N
P1MDIBP/N
P1MDICP/N
P1MDIDP/N
P2MDIAP/N
P2MDIBP/N
P2MDICP/N
P2MDIDP/N
P3MDIAP/N
P3MDIBP/N
P3MDICP/N
P3MDIDP/N
P4MDIAP/N
P4MDIBP/N
P4MDICP/N
P4MDIDP/N
Table 2. Media Dependent Interface Pins
Drive
Pin No. Type
Description
(mA)
AI/O
10
Port 0 Media Dependent Interface A~D.
97
For 1000Base-T operation, differential data from the media is transmitted
98
and received on all four pairs. For 100Base-TX and 10Base-T operation,
99
only MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
100
MDIAP/N and MDIBP/N.
102
103
104
105
107
108
109
110
112
113
114
115
120
121
122
123
125
126
127
128
2
3
4
5
7
8
9
10
24
25
26
27
29
30
31
32
Each of the differential pairs has an internal 100-ohm termination resistor.
AI/O
10
Port 1 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is transmitted
and received on all four pairs. For 100Base-TX and 10Base-T operation,
only MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
MDIAP/N and MDIBP/N.
Each of the differential pairs has an internal 100-ohm termination resistor.
AI/O
10
Port 2 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is transmitted
and received on all four pairs. For 100Base-TX and 10Base-T operation,
only MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
MDIAP/N and MDIBP/N.
Each of the differential pairs has an internal 100-ohm termination resistor.
AI/O
10
Port 3 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is transmitted
and received on all four pairs. For 100Base-TX and 10Base-T operation,
only MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
MDIAP/N and MDIBP/N.
Each of the differential pairs has an internal 100-ohm termination resistor.
AI/O
10
Port 4 Media Dependent Interface A~D.
For 1000Base-T operation, differential data from the media is transmitted
and received on all four pairs. For 100Base-TX and 10Base-T operation,
only MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
MDIAP/N and MDIBP/N.
Each of the differential pairs has an internal 100-ohm termination resistor.
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
13
Track ID: JATR-2265-11 Rev. 1.0
RTL8367RB
Datasheet
7.2.
General Purpose Interfaces
The RTL8367RB supports multi-function General Purpose Interfaces that can be configured as
MII/RGMII mode for extension GMAC interfaces. The RTL8367RB supports two extension interfaces
(Extension GMAC0 and Extension GMAC1) for connecting with an external PHY, MAC, or CPU in
specific applications. These extension interfaces support RGMII, MII MAC mode, or MII PHY mode via
register configuration.
7.2.1.
RGMII Pins
The Extension GMAC1 and Extension GMAC2 of the RTL8367RB support dual RGMII interfaces to
connect with an external MAC or PHY device when register configuration is set to RGMII mode
interface.
Pin Name
RG1_TXD3
RG1_TXD2
RG1_TXD1
RG1_TXD0
RG1_TXCTL
RG1_TXCLK
RG1_RXCLK
RG1_RXCTL
RG1_RXD0
RG1_RXD1
RG1_RXD2
RG1_RXD3
Table 3. Extension GMAC1 RGMII Pins
Drive
Pin No. Type
Description
(mA)
O
RG1_TXD[3:0] Extension GMAC1 RGMII Transmit Data Output.
57
Transmitted data is sent synchronously to RG1_TXCLK.
58
59
60
61
O
RG1_TXCTL Extension GMAC1 RGMII Transmit Control signal
Output.
The RG1_TXCTL indicates TX_EN at the rising edge of RG1_TXCLK,
and TX_ER at the falling edge of RG1_TXCLK.
At the RG1_TXCLK falling edge, RG1_TXCTL= TX_EN (XOR)
TX_ER.
62
O
RG1_TXCLK Extension GMAC1 RGMII Transmit Clock Output.
RG1_TXCLK is 125MHz @ 1Gbps, 25MHz @ 100Mbps, and 2.5MHz
@ 10Mbps.
Used for RG1_TXD[3:0] and RG1_TXCTL synchronization at
RG1_TXCLK on both rising and falling edges.
63
I
RG1_RXCLK Extension GMAC1 RGMII Receive Clock Input.
RG1_RXCLK is 125MHz @ 1Gbps, 25MHz @ 100Mbps, and 2.5MHz
@ 10Mbps.
Used for RG1_RXD[3:0] and RG1_RXCTL synchronization at both
RG1_RXCLK rising and falling edges.
This pin must be pulled low with a 1K ohm resistor when not used.
64
I
RG1_RXCTL Extension GMAC1 RGMII Receive Control signal input.
The RG1_RXCTL indicates RX_DV at the rising of RG1_RXCLK and
RX_ER at the falling edge of RG1_RXCLK.
At RG1_RXCLK falling edge, RG1_RXCTL= RX_DV (XOR) RX_ER.
This pin must be pulled low with a 1K ohm resistor when not used.
I
RG1_RXD[3:0] Extension GMAC1 RGMII Receive Data Input.
65
Received data is received synchronously by RG1_RXCLK.
66
These pins must be pulled low with a 1K ohm resistor when not used.
67
68
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
14
Track ID: JATR-2265-11 Rev. 1.0
RTL8367RB
Datasheet
Pin Name
RG2_TXD3
RG2_TXD2
RG2_TXD1
RG2_TXD0
RG2_TXCTL
RG2_TXCLK
RG2_RXCLK
RG2_RXCTL
RG2_RXD0
RG2_RXD1
RG2_RXD2
RG2_RXD3
Table 4. Extension GMAC2 RGMII Pins
Drive
Pin No. Type
Description
(mA)
O
RG2_TXD[3:0] Extension GMAC2 RGMII Transmit Data Output.
41
Transmitted data is sent synchronously to RG2_TXCLK.
42
43
44
45
O
RG2_TXCTL Extension GMAC2 RGMII Transmit Control signal
Output.
The RG2_TXCTL indicates TX_EN at the rising edge of RG2_TXCLK,
and TX_ER at the falling edge of RG2_TXCLK.
At the RG2_TXCLK falling edge, RG2_TXCTL= TX_EN (XOR)
TX_ER.
46
O
RG2_TXCLK Extension GMAC2 RGMII Transmit Clock Output.
RG2_TXCLK is 125MHz @ 1Gbps, 25MHz @ 100Mbps, and 2.5MHz
@ 10Mbps.
Used for RG2_TXD[3:0] and RG2_TXCTL synchronization at
RG2_TXCLK on both rising and falling edges.
47
I
RG2_RXCLK Extension GMAC2 RGMII Receive Clock Input.
RG2_RXCLK is 125MHz @ 1Gbps, 25MHz @ 100Mbps, and 2.5MHz
@ 10Mbps.
Used for RG2_RXD[3:0] and RG2_RXCTL synchronization at both
RG2_RXCLK rising and falling edges.
This pin must be pulled low with a 1K ohm resistor when not used.
48
I
RG2_RXCTL Extension GMAC2 RGMII Receive Control signal input.
The RG2_RXCTL indicates RX_DV at the rising of RG2_RXCLK and
RX_ER at the falling edge of RG2_RXCLK.
At RG2_RXCLK falling edge, RG2_RXCTL= RX_DV (XOR) RX_ER.
This pin must be pulled low with a 1K ohm resistor when not used.
I
RG2_RXD[3:0] Extension GMAC2 RGMII Receive Data Input.
49
Received data is received synchronously by RG2_RXCLK.
50
These pins must be pulled low with a 1K ohm resistor when not used.
51
52
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
15
Track ID: JATR-2265-11 Rev. 1.0
RTL8367RB
Datasheet
7.2.2.
MII Pins
The Extension GMAC1 and Extension GMAC2 of the RTL8367RB support dual MII interfaces to
connect with an external MAC or PHY device when register configuration is set to MII mode interface.
These two MII interfaces can be configured as MII MAC mode or MII PHY mode by register.
Pin Name
M1M_CRS
Table 5. Extension GMAC1 MII Pins (MII MAC Mode or MII PHY Mode)
Drive
Pin No. Type
Description
(mA)
56
I
M1M_CRS Extension GMAC1 MII MAC Mode Carrier Sense Input
when operating in 10/100 MII half duplex mode.
This pin must be pulled low with a 1K ohm resistor when not used.
O
-
M1M_TXD[3:0] Extension GMAC1 MII MAC Mode Transmit Data
Output.
Transmitted data is sent synchronously at the rising edge of
M1M_TXCLK.
M1P_RXD[3:0] Extension GMAC1 MII PHY Mode Receive Data
Output.
Received data is received synchronously at the rising edge of
M1P_RXCLK.
61
O
-
M1M_TXCLK/
M1P_RXCLK
62
I/O
-
M1M_RXCLK/
M1P_TXCLK
63
I/O
-
M1M_TXEN Extension GMAC1 MII MAC Mode Transmit Data Enable
Output.
Transmit enable that is sent synchronously at the rising edge of
M1M_TXCLK.
M1P_RXDV Extension GMAC1 MII PHY Mode Receive Data Valid
Output.
Receive Data Valid signal that is sent synchronously at the rising edge of
M1P_RXCLK.
M1M_TXCLK Extension GMAC1 MII MAC Mode Transmit Clock
Input.
In MII 100Mbps, M1M_TXCLK is 25MHz Clock Input.
In MII 10Mbps, M1M_TXCLK is 2.5MHz Clock Input.
Used to synchronize M1M_TXD[3:0] and M1M_TXEN.
M1P_RXCLK Extension GMAC1 MII PHY Mode Receive Clock
Output.
In MII 100Mbps, M1P_RXCLK is 25MHz Clock Output.
In MII 10Mbps, M1P_RXCLK is 2.5MHz Clock Output.
Used to synchronize M1P_RXD[3:0] and M1P_RXDV.
This pin must be pulled low with a 1K ohm resistor when not used.
M1M_RXCLK Extension GMAC1 MII MAC Mode Receive Clock
Input.
In MII 100Mbps, M1M_RXCLK is 25MHz Clock Input.
In MII 10Mbps, M1M_RXCLK is 2.5MHz Clock Input.
Used to synchronize M1M_RXD[3:0], M1M_RXDV, and M1P_CRS.
M1P_TXCLK Extension GMAC1 MII PHY Mode Transmit Clock
Output.
In MII 100Mbps, M1P_TXCLK is 25MHz Clock Output.
In MII 10Mbps, M1P_TXCLK is 2.5MHz Clock Output.
Used to synchronize M1P_TXD[3:0] and M1P_TXEN.
This pin must be pulled low with a 1K ohm resistor when not used.
M1M_TXD3/
M1P_RXD3
M1M_TXD2/
M1P_RXD2
M1M_TXD1/
M1P_RXD1
M1M_TXD0/
M1P_RXD0
M1M_TXEN/
M1P_RXDV
57
58
59
60
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
16
Track ID: JATR-2265-11 Rev. 1.0
RTL8367RB
Datasheet
Pin Name
Pin No. Type
M1M_RXDV/
M1P_TXEN
64
I
M1M_RXD0/
M1P_TXD0
M1M_RXD1/
M1P_TXD1
M1M_RXD2/
M1P_TXD2
M1M_RXD3/
M1P_TXD3
65
I
Pin Name
M2M_CRS/
RESERVED
M2M_TXD3/
M2P_RXD3
M2M_TXD2/
M2P_RXD2
M2M_TXD1/
M2P_RXD1
M2M_TXD0/
M2P_RXD0
M2M_TXEN/
M2P_RXDV
66
67
68
Drive
Description
(mA)
M1M_RXDV Extension GMAC1 MII MAC Mode Receive Data Valid
Input.
Receive Data Valid sent synchronously at the rising edge of
M1M_RXCLK.
M1P_TXEN Extension GMAC1 MII PHY Mode Transmit Data Enable
Input.
Transmit Data Enable is received synchronously at the rising edge of
M1P_TXCLK.
This pin must be pulled low with a 1K ohm resistor when not used.
M1M_RXD[3:0] Extension GMAC1 MII MAC Mode Receive Data
Input.
Received data that is received synchronously at the rising edge of
M1M_RXCLK.
M1P_TXD[3:0] Extension GMAC1 MII PHY Mode Transmit Data Input.
Transmitted data is received synchronously at the rising edge of
M1P_TXCLK.
These pins must be pulled low with a 1K ohm resistor when not used.
Table 6. Extension GMAC2 MII Pins (MII MAC Mode or MII PHY Mode)
Drive
Pin No. Type
Description
(mA)
40
I
M2M_CRS Extension GMAC2 MII MAC Mode Carrier Sense Input
when operating in 10/100 MII half duplex mode.
This pin must be pulled low with a 1K ohm resistor.
O
41
M2M_TXD[3:0] Extension GMAC2 MII MAC Mode Transmit Data
Output.
Transmitted data is sent synchronously at the rising edge of
42
M2M_TXCLK.
M2P_RXD[3:0] Extension GMAC2 MII PHY Mode Receive Data
43
Output.
Received data is received synchronously at the rising edge of
44
M2P_RXCLK.
45
O
-
M2M_TXEN Extension GMAC2 MII MAC Mode Transmit Data Enable
Output.
Transmit enable that is sent synchronously at the rising edge of
M2M_TXCLK.
M2P_RXDV Extension GMAC2 MII PHY Mode Receive Data Valid
Output.
Receive Data Valid signal that is sent synchronously at the rising edge of
M2P_RXCLK.
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Datasheet
Pin Name
Pin No. Type
M2M_TXCLK/
M2P_RXCLK
46
I/O
M2M_RXCLK/
M2P_TXCLK
47
I/O
M2M_RXDV/
M2P_TXEN
48
I
M2M_RXD0/
M2P_TXD0
M2M_RXD1/
M2P_TXD1
M2M_RXD2/
M2P_TXD2
M2M_RXD3/
M2P_TXD3
49
I
50
51
52
Drive
Description
(mA)
M2M_TXCLK Extension GMAC2 MII MAC Mode Transmit Clock
Input.
In MII 100Mbps, M2M_TXCLK is 25MHz Clock Input.
In MII 10Mbps, M2M_TXCLK is 2.5MHz Clock Input.
Used to synchronize M2M_TXD[3:0] and M2M_TXEN.
M2P_RXCLK Extension GMAC2 MII PHY Mode Receive Clock
Output.
In MII 100Mbps, M2P_RXCLK is 25MHz Clock Output.
In MII 10Mbps, M2P_RXCLK is 2.5MHz Clock Output.
Used to synchronize M2P_RXD[3:0] and M2P_RXDV.
This pin must be pulled low with a 1K ohm resistor when not used.
M2M_RXCLK Extension GMAC2 MII MAC Mode Receive Clock
Input.
In MII 100Mbps, M2M_RXCLK is 25MHz Clock Input.
In MII 10Mbps, M2M_RXCLK is 2.5MHz Clock Input.
Used to synchronize M2M_RXD[3:0], M2M_RXDV, and M2M_CRS.
M2P_TXCLK Extension GMAC2 MII PHY Mode Transmit Clock
Output.
In MII 100Mbps, M2P_TXCLK is 25MHz Clock Output.
In MII 10Mbps, M2P_TXCLK is 2.5MHz Clock Output.
Used to synchronize M2P_TXD[3:0] and M2P_TXEN.
This pin must be pulled low with a 1K ohm resistor when not used.
M2M_RXDV Extension GMAC2 MII MAC Mode Receive Data Valid
Input.
Receive Data Valid sent synchronously at the rising edge of
M2M_RXCLK.
M2P_TXEN Extension GMAC2 MII PHY Mode Transmit Data Enable
Input.
Transmit Data Enable is received synchronously at the rising edge of
M2P_TXCLK.
This pin must be pulled low with a 1K ohm resistor when not used.
M2M_RXD[3:0] Extension GMAC2 MII MAC Mode Receive Data
Input.
Received data that is received synchronously at the rising edge of
M2M_RXCLK.
M2P_TXD[3:0] Extension GMAC2 MII PHY Mode Transmit Data Input.
Transmitted data is received synchronously at the rising edge of
M2P_TXCLK.
These pins must be pulled low with a 1K ohm resistor when not used.
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Datasheet
7.3.
LED Pins
The RTL8367RB LED Pins can be configured to parallel mode LED or serial mode LED interface via
Register configuration. LED0, LED1, and LED2 of Port n indicate information that can be defined via
register or EEPROM.
In parallel mode LED interface, when the LED pin is pulled low, the LED output polarity will be high
active. When the LED pin is pulled high, the LED output polarity will change from high active to low
active. See section 9.19 LED Indicators, page 39 for more details.
Pin Name
Pin No. Type
P4LED2/
DIS_SPIS
72
I/OPU
P4LED1
74
I/OPU
P4LED0/
EEPROM_MOD
73
I/OPU
P3LED2/
RESERVED
76
I/OPU
P3LED1
75
I/OPU
P3LED0/
RESERVED
77
I/OPU
P2LED2/
DIS_8051
78
I/OPU
P2LED1
80
I/OPU
P2LED0/
DISAUTOLOAD
79
I/OPU
P1LED2/
RESERVED
81
I/OPU
P1LED1
83
I/OPU
P1LED0/
RESERVED
82
I/OPU
Table 7. LED Pins
Drive
Description
(mA)
Port 4 LED2 Output Signal.
P4LED2 indicates information is defined by register or EEPROM.
See section 9.19 LED Indicators, page 39 for more details.
Port 4 LED1 Output Signal.
P4LED1 indicates information is defined by register or EEPROM.
See section 9.19 LED Indicators, page 39 for more details.
Port 4 LED0 Output Signal.
P4LED0 indicates information is defined by register or EEPROM.
See section 9.19 LED Indicators, page 39 for more details.
Port 3 LED2 Output Signal.
P3LED2 indicates information is defined by register or EEPROM.
See section 9.19 LED Indicators, page 39 for more details.
Port 3 LED1 Output Signal.
P3LED1 indicates information is defined by register or EEPROM.
See section 9.19 LED Indicators, page 39 for more details.
Port 3 LED0 Output Signal.
P3LED0 indicates information is defined by register or EEPROM.
See section 9.19 LED Indicators, page 39 for more details.
Port 2 LED2 Output Signal.
P2LED2 indicates information is defined by register or EEPROM.
See section 9.19 LED Indicators, page 39 for more details.
Port 2 LED1 Output Signal.
P2LED1 indicates information is defined by register or EEPROM.
See section 9.19 LED Indicators, page 39 for more details.
Port 2 LED0 Output Signal.
P2LED0 indicates information is defined by register or EEPROM.
See section 9.19 LED Indicators, page 39 for more details.
Port 1 LED2 Output Signal.
P1LED2 indicates information is defined by register or EEPROM.
See section 9.19 LED Indicators, page 39 for more details.
Port 1 LED1 Output Signal.
P1LED1 indicates information is defined by register or EEPROM.
See section 9.19 LED Indicators, page 39 for more details.
Port 1 LED0 Output Signal.
P1LED0 indicates information is defined by register or EEPROM.
See section 9.19 LED Indicators, page 39 for more details.
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Datasheet
Pin Name
Pin No. Type
P0LED2/
EN_PHY
84
I/OPU
P0LED1/
LED_DA
85
I/OPU
P0LED0/
LED_CK/
SMI_SEL
86
I/OPU
7.4.
Drive
Description
(mA)
Port 0 LED2 Output Signal.
P0LED2 indicates information is defined by register or EEPROM.
See section 9.19 LED Indicators, page 39 for more details.
Port 0 LED1 Output Signal.
P0LED1 indicates information is defined by register or EEPROM.
See section 9.19 LED Indicators, page 39 for more details.
Port 0 LED0 Output Signal.
P0LED0 indicates information is defined by register or EEPROM.
See section 9.19 LED Indicators, page 39 for more details.
Configuration Strapping Pins
Pin Name
EEPROM_MOD/
P4LED0
DIS_SPIS/
P4LED2
RESERVED/
P3LED2
RESERVED/
P3LED0
Table 8. Configuration Strapping Pins
Pin No. Type Description
73
I/OPU EEPROM Mode Selection.
Pull Up: EEPROM 24Cxx Size greater than 16Kbits (24C32~24C256)
Pull Down: EEPROM 24Cxx Size less than or equal to 16Kbit (24C02~24C16).
Note: This pin must be kept floating, or pulled high or low via an external 4.7k
ohm resistor upon power on or reset.
When this pin is pulled low, the LED output polarity will be high active. When this
pin is pulled high, the LED output polarity will change from high active to low
active. See section 9.19 LED Indicators, page 39 for more details.
72
I/OPU SPI Slave Management Interface Selection
Pull Up: Disable SPI Slave Management Interface
Pull Down: Enable SPI Slave Management Interface
Note: This pin must be kept floating, or pulled high or low via an external 4.7k
ohm resistor upon power on or reset.
When this pin is pulled low, the LED output polarity will be high active. When this
pin is pulled high, the LED output polarity will change from high active to low
active. See section 9.19 LED Indicators, page 39 for more details.
76
I/OPU Internal Use/Reserved.
Note: This pin must be kept floating, or pulled high via an external 4.7k ohm
resistor upon power on or reset.
When pulled high, the LED output polarity will be low active. See section 9.19
LED Indicators, page 39 for more details.
77
I/OPU Internal Use/Reserved.
Note: For normal operation, this pin must be pulled low via an external 4.7k ohm
resistor upon power on or reset.
When pulled low, the LED output polarity will be high active. See section 9.19
LED Indicators, page 39 for more details.
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Datasheet
Pin Name
DIS_8051/
P2LED2
DISAUTOLOAD/
P2LED0
RESERVED/
P1LED2
RESERVED/
P1LED0
EN_PHY/
P0LED2
SMI_SEL/
LED_CK/
P0LED0
Pin No. Type Description
78
I/OPU Disable Embedded 8051.
Pull Up: Disable embedded 8051
Pull Down: Enable embedded 8051
Note1: The strapping pin DISAUTOLOAD and DIS_8051 are for power on or reset
initial stage configuration. Refer to Table 9 Configuration Strapping Pins
(DISAUTOLOAD and DIS_8051), page 22 for details.
Note2: This pin must be kept floating, or pulled high or low via an external 4.7k
ohm resistor upon power on or reset.
When this pin is pulled low, the LED output polarity will be high active. When this
pin is pulled high, the LED output polarity will change from high active to low
active. See section 9.19 LED Indicator, page 39 for more details.
79
I/OPU Disable EEPROM Autoload.
Pull Up: Disable EEPROM autoload
Pull Down: Enable EEPROM autoload
Note1: The strapping pin DISAUTOLOAD and DIS_8051 are for power on or reset
initial stage configuration. Refer to Table 9 Configuration Strapping Pins
(DISAUTOLOAD and DIS_8051), page 22 for details.
Note2: This pin must be kept floating, or pulled high or low via an external 4.7k
ohm resistor upon power on or reset.
When this pin is pulled low, the LED output polarity will be high active. When this
pin is pulled high, the LED output polarity will change from high active to low
active. See section 9.19 LED Indicators, page 39 for more details.
81
I/OPU Internal Use/Reserved.
Note: This pin must be kept floating, or pulled high via an external 4.7k ohm
resistor upon power on or reset.
When pulled high, the LED output polarity will be low active. See section 9.19
LED Indicators, page 39 for more details.
82
I/OPU Internal Use/Reserved.
Note: For normal operation, this pin must be pulled low via an external 4.7k ohm
resistor upon power on or reset.
When pulled low, the LED output polarity will be high active. See section 9.19
LED Indicators, page 39 for more details.
84
I/OPU Enable Embedded PHY.
Pull Up: Enable embedded PHY
Pull Down: Disable embedded PHY
Note: This pin must be kept floating, or pulled high or low via an external 4.7k
ohm resistor upon power on or reset.
When this pin is pulled low, the LED output polarity will be high active. When this
pin is pulled high, the LED output polarity will change from high active to low
active. See section 9.19 LED Indicators, page 39 for more details.
86
I/OPU EEPROM SMI/MII Management Interface Selection.
Pull Up: EEPROM SMI interface when DIS_SPIS = 1
Pull Down: MII Management interface when DIS_SPIS = 1
Note: This pin must be kept floating, or pulled high or low via an external 4.7k
ohm resistor upon power on or reset.
When this pin is pulled low, the LED output polarity will be high active. When this
pin is pulled high, the LED output polarity will change from high active to low
active. See section 9.19 LED Indicators, page 39 for more details.
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Datasheet
Pin Name
DIS_LPD/
BUZZER
Pin No. Type Description
20
I/OPU Realtek Loop Detection Configuration.
Pull Up: Disable Loop detection function
Pull Down: Enable Loop detection function
Note: This pin must be kept floating, or pulled high or low via an external 4.7k
ohm resistor upon power on or reset. 2KHz signal out when looping is detected.
22
I/OPU Internal Use/Reserved.
Note: This pin must be kept floating, or pulled high via an external 4.7k ohm
resistor upon power on or reset.
RESERVED
7.5.
Configuration Strapping Pins (DISAUTOLOAD and
DIS_8051)
Table 9. Configuration Strapping Pins (DISAUTOLOAD and DIS_8051)
DISAUTOLOAD
0
1
7.6.
DIS_8051
0
1
Irrelevant
Initial Stage (Power On or Reset) Loading Data
From
To
EEPROM
EEPROM
Do Nothing
Register
Embedded 8051 Instruction Memory
Do Nothing
Management Interface Pins
Pin Name
SPIS_CSI
SPIS_CK/
SCK/
MMD_MDC
SPIS_DI/
SDA/
MMD_MDIO
SPIS_DO
INTERRUPT
Table 10. Management Interface Pins
Pin No. Type Description
92
I
When DIS_SPIS is Pulled Low, SPI Slave Management Interface is Enabled. This
pin acts as SPI slave mode Chip Selection Input pin.
When DIS_SPIS is Pulled Up, SPI Slave Management Interface is Disabled. This
pin is unused.
93
I/OPU When DIS_SPIS is Pulled Low, SPI Slave Management Interface is Enabled. This
pin acts as SPI slave mode Serial Clock Input pin.
When DIS_SPIS is Pulled Up, SPI Slave Management Interface is Disabled. This
pin acts as EEPROM SMI Interface Clock/MII Management Interface Clock
(selected via the hardware strapping pin, SMI_SEL).
94
I/OPU When DIS_SPIS is Pulled Low, SPI Slave Management Interface is Enabled. This
pin acts as SPI slave mode Serial Data Input pin.
When DIS_SPIS is Pulled Up, SPI Slave Management Interface is Disabled. This
pin acts as EEPROM SMI Interface Data/MII Management Interface Data
(selected via the hardware strapping pin, SMI_SEL).
95
O
When DIS_SPIS is Pulled Low, SPI Slave Management Interface is Enabled. This
pin acts as SPI slave mode Serial Data Output pin.
When DIS_SPIS is Pulled Up, SPI Slave Management Interface is Disabled. This
pin is unused.
19
OPU Interrupt Output for External CPU.
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Datasheet
7.7.
Miscellaneous Pins
Pin Name
XTALO
Pin No.
89
Type
AO
XTALI
90
AI
MDIREF
13
AO
RESERVED
RESERVED
RESERVED
RESERVED
nRESET
35
37
38
40
91
AO
AO
AO
I
IS
7.8.
Test Pins
Pin Name
RTT1
RTT2
ATESTCK0
7.9.
Table 11. Miscellaneous Pins
Description
25MHz Crystal Clock Output Pin.
25MHz +/-50ppm tolerance crystal output.
25MHz Crystal Clock Input and Feedback Pin.
25MHz +/-50ppm tolerance crystal reference or oscillator input.
Reference Resistor.
A 2.49K ohm (1%) resistor must be connected between MDIREF and GND.
Reserved. Must be left floating in normal operation.
Reserved. Must be left floating in normal operation.
Reserved. Must be left floating in normal operation.
Reserved. Must be pulled low with a 1K ohm resistor in normal operation.
System Reset Input Pin.
When low active will reset the RTL8367RB.
Pin No.
15
16
117
Type
AO
AO
AO
Table 12. Test Pins
Description
Reserved for Internal Use. Must be left floating.
Reserved for Internal Use. Must be left floating.
Reserved for Internal Use. Must be left floating.
Power and GND Pins
Pin Name
DVDDIO
DVDDIO_1
DVDDIO_2
DVDDL
AVDDH
AVDDL
PLLVDDL0
PLLVDDL1
GND
AGND
PLLGND0
Table 13. Power and GND Pins
Pin No.
Type Description
18, 70
P
Digital I/O High Voltage Power for LED, Management Interface,
nRESET, INTERRUPT, and DIS_LPD/BUZZER.
55, 69
P
Digital I/O High Voltage Power for Extension Port 1 General
Purpose Interface.
39, 54
P
Digital I/O High Voltage Power for Extension Port 2 General
Purpose Interface.
21, 53, 71, 87
P
Digital Low Voltage Power.
AP
Analog High Voltage Power.
1, 11, 17, 23, 33, 36,
88, 96, 106, 119
AP
Analog Low Voltage Power.
6, 14, 28, 101, 111,
124
118
AP
PLL0 Low Voltage Power.
34
AP
PLL1 Low Voltage Power.
EPAD
G
GND.
12
AG
Analog GND.
118
AG
PLL0 GND.
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Datasheet
8. Physical Layer Functional Overview
8.1.
MDI Interface
The RTL8367RB embeds five Gigabit Ethernet PHYs in one chip. Each port uses a single common MDI
interface to support 1000Base-T, 100Base-TX, and 10Base-T. This interface consists of four signal pairsA, B, C, and D. Each signal pair consists of two bi-directional pins that can transmit and receive at the
same time. The MDI interface has internal termination resistors, and therefore reduces BOM cost and
PCB complexity. For 1000Base-T, all four pairs are used in both directions at the same time. For 10/100
links and during auto-negotiation, only pairs A and B are used.
8.2.
1000Base-T Transmit Function
The 1000Base-TX transmit function performs 8B/10B coding, scrambling, and 4D-PAM5 encoding.
These code groups are passed through a waveform-shaping filter to minimize EMI effects, and are
transmitted onto 4-pair CAT5 cable at 125MBaud/s through a D/A converter.
8.3.
1000Base-T Receive Function
Input signals from the media pass through the sophisticated on-chip hybrid circuit to subtract the
transmitted signal from the input signal for effective reduction of near-end echo. The received signal is
then processed with state-of-the-art technology, e.g., adaptive equalization, BLW (Baseline Wander)
correction, cross-talk cancellation, echo cancellation, timing recovery, error correction, and 4D-PAM5
decoding. The 8-bit-wide data is recovered and is sent to the GMII interface at a clock speed of 125MHz.
The RX MAC retrieves the packet data from the internal receive MII/GMII interface and sends it to the
packet buffer manager.
8.4.
100Base-TX Transmit Function
The 100Base-TX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling,
NRZ/NRZI conversion, and MLT-3 encoding. The 5-bit serial data stream after 4B/5B coding is then
scrambled as defined by the TP-PMD Stream Cipher function to flatten the power spectrum energy such
that EMI effects can be reduced significantly.
The scrambled seed is based on PHY addresses and is unique for each port. After scrambling, the bit
stream is driven onto the network media in the form of MLT-3 signaling. The MLT-3 multi-level
signaling technology moves the power spectrum energy from high frequency to low frequency, which
also reduces EMI emissions.
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Datasheet
8.5.
100Base-TX Receive Function
The receive path includes a receiver composed of an adaptive equalizer and DC restoration circuits (to
compensate for an incoming distorted MLT-3 signal), an MLT-3 to NRZI and NRZI to NRZ converter to
convert analog signals to digital bit-stream, and a PLL circuit to clock data bits with minimum bit error
rate. A de-scrambler, 5B/4B decoder, and serial-to-parallel conversion circuits are followed by the PLL
circuit. Finally, the converted parallel data is fed into the MAC.
8.6.
10Base-T Transmit Function
The output 10Base-T waveform is Manchester-encoded before it is driven onto the network media. The
internal filter shapes the driven signals to reduce EMI emissions, eliminating the need for an external
filter.
8.7.
10Base-T Receive Function
The Manchester decoder converts the incoming serial stream to NRZ data when the squelch circuit
detects the signal level is above squelch level.
8.8.
Auto-Negotiation for UTP
The RTL8367RB obtains the states of duplex, speed, and flow control ability for each port in UTP mode
through the auto-negotiation mechanism defined in the IEEE 802.3 specifications. During autonegotiation, each port advertises its ability to its link partner and compares its ability with advertisements
received from its link partner. By default, the RTL8367RB advertises full capabilities (1000Full, 100Full,
100Half, 10Full, 10Half) together with flow control ability.
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Datasheet
8.9.
Crossover Detection and Auto Correction
The RTL8367RB automatically determines whether or not it needs to crossover between pairs (see Table
14) so that an external crossover cable is not required. When connecting to another device that does not
perform MDI crossover, when necessary, the RTL8367RB automatically switches its pin pairs to
communicate with the remote device. When connecting to another device that does have MDI crossover
capability, an algorithm determines which end performs the crossover function.
The crossover detection and auto correction function can be disabled via register configuration. The pin
mapping in MDI and MDI Crossover mode is given below.
Pairs
A
B
C
D
Table 14. Media Dependent Interface Pin Mapping
MDI
MDI Crossover
1000Base-T
100Base-TX
10Base-T
1000Base-T
100Base-TX
A
TX
TX
B
RX
B
RX
RX
A
TX
C
Unused
Unused
D
Unused
D
Unused
Unused
C
Unused
10Base-T
RX
TX
Unused
Unused
8.10. Polarity Correction
The RTL8367RB automatically corrects polarity errors on the receiver pairs in 1000Base-T and 10Base-T
modes. In 100Base-TX mode, the polarity is irrelevant.
In 1000Base-T mode, receive polarity errors are automatically corrected based on the sequence of idle
symbols. Once the de-scrambler is locked, the polarity is also locked on all pairs. The polarity becomes
unlocked only when the receiver loses lock.
In 10Base-T mode, polarity errors are corrected based on the detection of valid spaced link pulses. The
detection begins during the MDI crossover detection phase and locks when the 10Base-T link is up. The
polarity becomes unlocked when the link is down.
RTL8367RB
Link Partner
+
RX _
+
_ TX
+
TX _
_
+
+
_ RX
Figure 5. Conceptual Example of Polarity Correction
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Datasheet
9. General Function Description
9.1.
9.1.1.
Reset
Hardware Reset
In a power-on reset, an internal power-on reset pulse is generated and the RTL8367RB will start the reset
initialization procedures. These are:
•
•
•
•
•
Determine various default settings via the hardware strap pins at the end of the nRESET signal
Autoload the configuration from EEPROM if EEPROM is detected
Complete the embedded SRAM BIST process
Initialize the packet buffer descriptor allocation
Initialize the internal registers and prepare them to be accessed by the external CPU
9.1.2.
Software Reset
The RTL8367RB supports two software resets; a chip reset and a soft reset.
9.1.2.1
CHIP_RESET
When CHIP_RESET is set to 0b1 (write and self-clear), the chip will take the following steps:
1. Download configuration from strap pin and EEPROM
2. Start embedded SRAM BIST (Built-In Self Test)
3. Clear all the Lookup and VLAN tables
4. Reset all registers to default values
5. Restart the auto-negotiation process
9.1.2.2
SOFT_RESET
When SOFT_RESET is set to 0b1 (write and self-clear), the chip will take the following steps:
1. Clear the FIFO and re-start the packet buffer link list
2. Restart the auto-negotiation process
9.2.
IEEE 802.3x Full Duplex Flow Control
The RTL8367RB supports IEEE 802.3x flow control in 10/100/1000M modes. Flow control can be
decided in two ways:
•
•
When Auto-Negotiation is enabled, flow control depends on the result of NWay
When Auto-Negotiation is disabled, flow control depends on register definition
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Datasheet
9.3.
Half Duplex Flow Control
In half duplex mode, the CSMA/CD media access method is the means by which two or more stations
share a common transmission medium. To transmit, a station waits (defers) for a quiet period on the
medium (that is, no other station is transmitting) and then sends the intended message in bit-serial form. If
the message collides with that of another station, then each transmitting station intentionally transmits for
an additional predefined period to ensure propagation of the collision throughout the system. The station
remains silent for a random amount of time (backoff) before attempting to transmit again.
When a transmission attempt has terminated due to a collision, it is retried until it is successful. The
scheduling of the retransmissions is determined by a controlled randomization process called “Truncated
Binary Exponential Backoff”. At the end of enforcing a collision (jamming), the switch delays before
attempting to retransmit the frame. The delay is an integer multiple of slot time (512 bit times). The
number of slot times to delay before the nth retransmission attempt is chosen as a uniformly distributed
random integer ‘r’ in the range:
0 ≤ r < 2k
where:
k = min (n, backoffLimit). The backoffLimit for the RTL8367RB is 9.
The half duplex back-off algorithm in the RTL8367RB does not have the maximum retry count limitation
of 16 (as defined in IEEE 802.3). This means packets in the switch will not be dropped if the back-off
retry count is over 16.
9.3.1.
Back-Pressure Mode
In Back-Pressure mode, the RTL8367RB sends a 4-byte jam pattern (data=0xAA) to collide with
incoming packets when congestion control is activated. The Jam pattern collides at the fourth byte
counted from the preamble. The RTL8367RB supports 48PASS1, which receives one packet after 48
consecutive jam collisions (data collisions are not included in the 48). Enable this function to prevent port
partition after 63 consecutive collisions (data collisions + consecutive jam collisions).
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Datasheet
9.4.
Search and Learning
Search
When a packet is received, the RTL8367RB uses the destination MAC address, Filtering Identifier (FID)
and Enhanced Filtering Identifier (EFID) to search the 2K-entry look-up table. The 48-bit MAC address,
4-bit FID and 3-bit EFID use a hash algorithm, to calculate an 11-bit index value. The RTL8367RB uses
the index to compare the packet MAC address with the entries (MAC addresses) in the look-up table.
This is the ‘Address Search’. If the destination MAC address is not found, the switch will broadcast the
packet according to VLAN configuration.
Learning
The RTL8367RB uses the source MAC address, FID, and EFID of the incoming packet to hash into a
9-bit index. It then compares the source MAC address with the data (MAC addresses) in this index. If
there is a match with one of the entries, the RTL8367RB will update the entry with new information. If
there is no match and the 2K entries are not all occupied by other MAC addresses, the RTL8367RB will
record the source MAC address and ingress port number into an empty entry. This process is called
‘Learning’.
The RTL8367RB supports a 64-entry Content Addressable Memory (CAM) to avoid look-up table hash
collisions. When all 2K entries in the look-up table index are occupied, the source MAC address can be
learned into the 64-entry CAM. If both the look-up table and the CAM are full, the source MAC address
will not be learned in the RTL8367RB.
Address aging is used to keep the contents of the address table correct in a dynamic network topology.
The look-up engine will update the time stamp information of an entry whenever the corresponding
source MAC address appears. An entry will be invalid (aged out) if its time stamp information is not
refreshed by the address learning process during the aging time period. The aging time of the
RTL8367RB is between 200 and 400 seconds (typical is 300 seconds).
9.5.
SVL and IVL/SVL
The RTL8367RB supports a 16-group Filtering Identifier (FID) for L2 search and learning. In default
operation, all VLAN entries belong to the same FID. This is called Shared VLAN Learning (SVL). If
VLAN entries are configured to different FIDs, then the same source MAC address with multiple FIDs
can be learned into different look-up table entries. This is called Independent VLAN Learning and Shared
VLAN Learning (IVL/SVL).
9.6.
Illegal Frame Filtering
Illegal frames such as CRC error packets, runt packets (length maximum length) will be discarded by the RTL8367RB. The maximum packet length may be
set to 1522, 1536, 1552, or 16K bytes.
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9.7.
IEEE 802.3 Reserved Group Addresses Filtering Control
The RTL8367RB supports the ability to drop/forward IEEE 802.3 specified reserved group MAC
addresses: 01-80-C2-00-00-00 to 01-80-C2-00-00-2F. The default setting enables forwarding of these
reserved group MAC address control frames. Frames with group MAC address 01-80-C2-00-00-01
(802.3x Pause) and 01-80-C2-00-00-02 (802.3ad LACP) will always be filtered. Table 15 shows the
Reserved Multicast Address (RMA) configuration mode from 01-80-C2-00-00-00 to 01-80-C2-00-00-2F.
Table 15. Reserved Multicast Address Configuration Table
Assignment
Value
Bridge Group Address
01-80-C2-00-00-00
IEEE Std 802.3, 1988 Edition, Full Duplex PAUSE Operation
01-80-C2-00-00-01
IEEE Std 802.3ad Slow Protocols-Multicast Address
01-80-C2-00-00-02
IEEE Std 802.1X PAE Address
01-80-C2-00-00-03
Provider Bridge Group Address
1-80-C2-00-00-08
Undefined 802.1 Address
01-80-C2-00-00-04 ~
01-80-C2-00-00-07
&
01-80-C2-00-00-09 ~
01-80-C2-00-00-0C
&
01-80-C2-00-00-0F
Provider Bridge MVRP Address
01-80-C2-00-00-0D
IEEE Std 802.1AB Link Layer Discovery Protocol Address
01-80-C2-00-00-0E
All LANs Bridge Management Group Address
01-80-C2-00-00-10
Load Server Generic Address
Loadable Device Generic Address
Undefined 802.1 Address
01-80-C2-00-00-11
01-80-C2-00-00-12
01-80-C2-00-00-13 ~
01-80-C2-00-00-17
&
01-80-C2-00-00-19
&
01-80-C2-00-00-1B ~
01-80-C2-00-00-1F
01-80-C2-00-00-18
01-80-C2-00-00-1a
01-80-C2-00-00-20
01-80-C2-00-00-21
01-80-C2-00-00-22
|
01-80-C2-00-00-2F
Generic Address for All Manager Stations
Generic Address for All Agent Stations
GMRP Address
GVRP Address
Undefined GARP Address
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9.8.
Broadcast/Multicast/Unknown DA Storm Control
The RTL8367RB enables or disables per-port broadcast/multicast/unknown DA storm control by setting
registers (default is disabled). After the receiving rate of broadcast/multicast/unknown DA packets
exceeds a reference rate, all other broadcast/multicast/unknown DA packets will be dropped. The
reference rate is set via register configuration.
9.9.
Port Security Function
The RTL8367RB supports three types of security function to prevent malicious attacks:
•
•
•
Per-port enable/disable SA auto-learning for an ingress packet
Per-port enable/disable look-up table aging update function for an ingress packet
Per-port enable/disable drop all unknown DA packets
9.10. MIB Counters
The RTL8367RB supports a set of counters to support management functions.
•
•
•
•
•
•
MIB-II (RFC 1213)
Ethernet-Like MIB (RFC 3635)
Interface Group MIB (RFC 2863)
RMON (RFC 2819)
Bridge MIB (RFC 1493)
Bridge MIB Extension (RFC 2674)
9.11. Port Mirroring
The RTL8367RB supports one set of port mirroring functions for all ports. The TX, or RX, or both
TX/RX packets of the source port can be monitored to multiple mirror ports.
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9.12. VLAN Function
The RTL8367RB supports 4K VLAN groups. These can be configured as port-based VLANs,
IEEE 802.1Q tag-based VLANs, and Protocol-based VLANs. Two ingress-filtering and egress-filtering
options provide flexible VLAN configuration:
Ingress Filtering
• The acceptable frame type of the ingress process can be set to ‘Admit All’ or ‘Admit All Tagged’
• ‘Admit’ or ‘Discard’ frames associated with a VLAN for which that port is not in the member set
Egress Filtering
• ‘Forward’ or ‘Discard’ Leaky VLAN frames between different VLAN domains
• ‘Forward’ or ‘Discard’ Multicast VLAN frames between different VLAN domains
The VLAN tag can be inserted or removed at the output port. The RTL8367RB will insert a Port VID
(PVID) for untagged frames, or remove the tag from tagged frames. The RTL8367RB also supports a
special insert VLAN tag function to separate traffic from the WAN and LAN sides in Router and
Gateway applications.
In router applications, the router may want to know which input port this packet came from. The
RTL8367RB supports Port VID (PVID) for each port and can insert a PVID in the VLAN tag on egress.
Using this function, VID information carried in the VLAN tag will be changed to PVID. The
RTL8367RB also provides an option to admit VLAN tagged packets with a specific PVID only. If this
function is enabled, it will drop non-tagged packets and packets with an incorrect PVID.
9.12.1. Port-Based VLAN
This default configuration of the VLAN function can be modified via an attached serial EEPROM or
EEPROM SMI Slave interface. The 4K-entry VLAN Table designed into the RTL8367RB provides full
flexibility for users to configure the input ports to associate with different VLAN groups. Each input port
can join with more than one VLAN group.
Port-based VLAN mapping is the simplest implicit mapping rule. Each ingress packet is assigned to a
VLAN group based on the input port. It is not necessary to parse and inspect frames in real-time to
determine their VLAN association. All the packets received on a given input port will be forwarded to
this port’s VLAN members.
9.12.2. IEEE 802.1Q Tag-Based VLAN
The RTL8367RB supports 4K VLAN entries to perform 802.1Q tag-based VLAN mapping. In 802.1Q
VLAN mapping, the RTL8367RB uses a 12-bit explicit identifier in the VLAN tag to associate received
packets with a VLAN. The RTL8367RB compares the explicit identifier in the VLAN tag with the 4K
VLAN Table to determine the VLAN association of this packet, and then forwards this packet to the
member set of that VLAN. Two VIDs are reserved for special purposes. One of them is all 1’s, which is
reserved and currently unused. The other is all 0’s, which indicates a priority tag. A priority-tagged frame
should be treated as an untagged frame.
When ‘802.1Q tag aware VLAN’ is enabled, the RTL8367RB performs 802.1Q tag-based VLAN
mapping for tagged frames, but still performs port-based VLAN mapping for untagged frames. If ‘802.1Q
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tag aware VLAN’ is disabled, the RTL8367RB performs only port-based VLAN mapping both on nontagged and tagged frames. The processing flow when ‘802.1Q tag aware VLAN’ is enabled is illustrated
below.
Two VLAN ingress filtering functions are supported in registers by the RTL8367RB. One is the ‘VLAN
tag admit control, which provides the ability to receive VLAN-tagged frames only. Untagged or priority
tagged (VID=0) frames will be dropped. The other is ‘VLAN member set ingress filtering’, which will
drop frames if the ingress port is not in the member set.
9.12.3. Protocol-Based VLAN
The RTL8367RB supports a 4-group Protocol-based VLAN configuration. The packet format can be RFC
1042, LLC, or Ethernet, as shown in Figure 6. There are 4 configuration tables to assign the frame type
and corresponding field value. Taking IP packet configuration as an example, the user can configure the
frame type to be ‘Ethernet’, and value to be ‘0x0800’. Each table will index to one of the entries in the
4K-entry VLAN table. The packet stream will match the protocol type and the value will follow the
VLAN member configuration of the indexed entry to forward the packets.
Figure 6. Protocol-Based VLAN Frame Format and Flow Chart
9.12.4. Port VID
In a router application, the router may want to know which input port this packet came from. The
RTL8367RB supports Port VID (PVID) for each port to insert a PVID in the VLAN tag for untagged or
priority tagged packets on egress. When 802.1Q tag-aware VLAN is enabled, VLAN tag admit control is
enabled, and non-PVID Discard is enabled at the same time. When these functions are enabled, the
RTL8367RB will drop non-tagged packets and packets with an incorrect PVID.
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9.13. QoS Function
The RTL8367RB supports 8 priority queues and input bandwidth control. Packet priority selection can
depend on Port-based priority, 802.1p/Q Tag-based priority, IPv4/IPv6 DSCP-based priority, and ACLbased priority. When multiple priorities are enabled in the RTL8367RB, the packet’s priority will be
assigned based on the priority selection table.
Each queue has one leaky bucket for Average Packet Rate. Per-queue in each output port can be set as
Strict Priority (SP) or Weighted Fair Queue (WFQ) for packet scheduling algorithm.
9.13.1. Input Bandwidth Control
Input bandwidth control limits the input bandwidth. When input traffic is more than the RX Bandwidth
parameter, this port will either send out a ‘pause ON’ frame, or drop the input packet depending on
register setup. Per-port input bandwidth control rates can be set from 8Kbps to 1Gbps (in 8Kbps steps).
9.13.2. Priority Assignment
Priority assignment specifies the priority of a received packet according to various rules. The
RTL8367RB can recognize the QoS priority information of incoming packets to give a different egress
service priority.
The RTL8367RB identifies the priority of packets based on several types of QoS priority information:
•
•
•
•
•
•
•
Port-based priority
802.1p/Q-based priority
IPv4/IPv6 DSCP-based priority
ACL-based priority
VLAN-based priority
MAC-based priority
SVLAN-based priority
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9.13.3. Priority Queue Scheduling
The RTL8367RB supports MAX-MIN packet scheduling.
Packet scheduling offers two modes:
•
•
Average Packet Rate (APR) leaky bucket, which specifies the average rate of one queue
Weighted Fair Queue (WFQ), which decides which queue is selected in one slot time to guarantee the
minimal packet rate of one queue
In addition, each queue of each port can select Strict Priority or WFQ packet scheduling according to
packet scheduling mode. Figure 7 shows the RTL8367RB packet-scheduling diagram.
Guaranteed Max.
Guaranteed Min.
APR Leaky
Bucket
WFQ Leaky Bucket
Queue 0
Queue 1
Scheduler
Queue 7
Figure 7. RTL8367RB MAX-MIN Scheduling Diagram
9.13.4. IEEE 802.1p/Q and DSCP Remarking
The RTL8367RB supports the IEEE 802.1p/Q and IP DSCP (Differentiated Services Code Point)
remarking function. When packets egress from one of the 8 queues, the packet’s 802.1p/Q priority and IP
DSCP can optionally be remarked to a configured value. Each output queue has a 3-bit 802.1p/Q, and a
6-bit IP DSCP value configuration register.
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9.13.5. ACL-Based Priority
The RTL8367RB supports 64-entry ACL (Access Control List) rules. When a packet is received, its
physical port, Layer2, Layer3, and Layer4 information are recorded and compared to ACL entries.
If a received packet matches multiple entries, the entry with the lowest address is valid. If the entry is
valid, the action bit and priority bit will be applied.
•
•
•
•
If the action bit is ‘Drop’, the packet will be dropped. If the action bit is ‘CPU’, the packet will be
trapped to the CPU instead of forwarded to non-CPU ports (except where it will be dropped by rules
other than the ACL rule)
If the action bit is ‘Permit’, ACL rules will override other rules
If the action bit is ‘Mirror’, the packet will be forwarded to the mirror port and the L2 lookup result
destination port. The mirror port indicates the port configured in the port mirror mechanism
The priority bit will take effect only if the action bit is ‘CPU’, ‘Permit’, and ‘Mirror’. The Priority bit
is used to determine the packet queue ID according to the priority assignment mechanism
9.14. IGMP & MLD Snooping Function
The RTL8367RB supports H/W IGMP v1/v2/v3 and MLD v1/v2. The RTL8367RB can learn multicast
group membership information automatically without software effort. Multicast data packets can be
forwarded to member ports only. The IGMP & MLD Snooping function in the RTL8367RB also supports
‘Fast Leave’ for applications that want to remove membership after receiving a Leave packet.
9.15. IEEE 802.1x Function
The RTL8367RB supports IEEE 802.1x Port-based/MAC-based Access Control.
•
•
•
•
•
•
•
Port-Based Access Control for each port
Authorized Port-Based Access Control for each port
Port-Based Access Control Direction for each port
MAC-Based Access Control for each port
MAC-Based Access Control Direction
Optional Unauthorized Behavior
Guest VLAN
9.15.1. Port-Based Access Control
Each port of the RTL8367RB can be set to 802.1x port-based authenticated checking function usage and
authorized status. Ports with 802.1X unauthorized status will drop received/transmitted frames.
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9.15.2. Authorized Port-Based Access Control
If a dedicated port is set to 802.1x port-based access control, and passes the 802.1x authorization, then its
port authorization status can be set to authorized.
9.15.3. Port-Based Access Control Direction
Ports with 802.1X unauthorized status will drop received/transmitted frames only when port authorization
direction is ‘BOTH’. If the authorization direction of an 802.1X unauthorized port is IN, incoming frames
to that port will be dropped, but outgoing frames will be transmitted.
9.15.4. MAC-Based Access Control
MAC-Based Access Control provides authentication for multiple logical ports. Each logical port
represents a source MAC address. There are multiple logical ports for a physical port. When a logical port
or a MAC address is authenticated, the relevant source MAC address has the authorization to access the
network. A frame with a source MAC address that is not authenticated by the 802.1x function will be
dropped or trapped to the CPU.
9.15.5. MAC-Based Access Control Direction
Unidirectional and Bi-directional control are two methods used to process frames in 802.1x. As the
system cannot predict which port the DA is on, a system-wide MAC-based access control direction setup
is provided for determining whether receiving or bi-direction should be authorized.
If MAC-based access control direction is BOTH, then received frames with unauthenticated SA or
unauthenticated DA will be dropped. When MAC-based access control direction is IN, only received
frames with unauthenticated SA will be dropped.
9.15.6. Optional Unauthorized Behavior
Both in Port-Based Network Access Control and MAC-Based Access Control, a whole system control
setup is provided to determine unauthorized frame dropping, trapping to CPU, or tagging as belonging to
a Guest VLAN (see the following ‘Guest VLAN’ section).
9.15.7. Guest VLAN
When the RTL8367RB enables the Port-based or MAC-based 802.1x function, and the connected PC
does not support the 802.1x function or does not pass the authentication procedure, the RTL8367RB will
drop all packets from this port.
The RTL8367RB also supports one Guest VLAN to allow unauthorized ports or packets to be forwarded
to a limited VLAN domain. The user can configure one VLAN ID and member set for these unauthorized
packets.
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9.16. IEEE 802.1D Function
When using IEEE 802.1D, the RTL8367RB supports 16 sets and four status’ for each port for CPU
implementation 802.1D (STP) and 802.1s (MSTP) function:
•
•
•
•
Disabled: The port will not transmit/receive packets, and will not perform learning
Blocking: The port will only receive BPDU spanning tree protocol packets, but will not transmit any
packets, and will not perform learning
Learning: The port will receive any packet, including BPDU spanning tree protocol packets, and will
perform learning, but will only transmit BPDU spanning tree protocol packets
Forwarding: The port will transmit/receive all packets, and will perform learning
The RTL8367RB also supports a per-port transmission/reception enable/disable function. Users can
control the port state via register.
9.17. Embedded 8051
An 8051 MCU is embedded in the RTL8367RB to support management functions. The 8051 MCU can
access all of the registers in the RTL8367RB through the internal bus. With the Network Interface Circuit
(NIC) acting as the data path, the 8051 MCU connects to the switch core and can transmit frames to or
receive frames from the Ethernet network. The features of the 8051 MCU are listed below:
•
•
•
•
•
•
256 Bytes fast internal RAM
On-chip 32K data memory
On-chip 16K code memory
Supports code-banking
12KBytes NIC buffer
EEPROM read/write ability
9.18. Realtek Cable Test (RTCT)
The RTL8367RB physical layer transceivers use DSP technology to implement the Realtek Cable Test
(RTCT) feature. The RTCT function can be used to detect short, open, or impedance mismatch in each
differential pair. The RTL8367RB also provides LED support to indicate test status and results.
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9.19. LED Indicators
The RTL8367RB supports parallel LEDs for each port. Each port has three LED indicator pins, LED0,
LED1, and LED2. Each pin may have different indicator information (defined in Table 16). Refer to
section 7.3 LED Pins, page 19 for pin details. Upon reset, the RTL8367RB supports chip diagnostics and
LED operation test by blinking all LEDs once.
Table 16. LED Definitions
LED Statuses
LED_Off
Dup/Col
Link/Act
Spd1000
Spd100
Spd10
Spd1000/Act
Spd100/Act
Spd10/Act
Spd100 (10)/Act
Act
Description
LED Pin Output Disable.
Duplex/Collision Indicator. Blinking when collision occurs. Low for full duplex, and
high for half duplex mode.
Link, Activity Indicator. Low for link established. Link/Act Blinking when the
corresponding port is transmitting or receiving.
1000Mbps Speed Indicator. Low for 1000Mbps.
100Mbps Speed Indicator. Low for 100Mbps.
10Mbps Speed Indicator. Low for 10Mbps.
1000Mbps Speed/Activity Indicator. Low for 1000Mbps. Blinking when the
corresponding port is transmitting or receiving.
100Mbps Speed/Activity Indicator. Low for 100Mbps. Blinking when the
corresponding port is transmitting or receiving.
10Mbps Speed/Activity Indicator. Low for 10Mbps. Blinking when the corresponding
port is transmitting or receiving.
10/100Mbps Speed/Activity Indicator. Low for 10/100Mbps. Blinking when the
corresponding port is transmitting or receiving.
Activity Indicator. Act blinking when the corresponding port is transmitting or
receiving.
The LED pin also supports pin strapping configuration functions. The PnLED0, PnLED1, and PnLED2
pins are dual-function pins: input operation for configuration upon reset, and output operation for LED
after reset. If the pin input is pulled high upon reset, the pin output is active low after reset. If the pin
input is pulled down upon reset, the pin output is active high after reset. For details refer to Figure 8, page
40, and Figure 9, page 40. Typical values for pull-up/pull-down resistors are 4.7KΩ.
The PnLED1 can be combined with PnLED1 or PnLED2 as a Bi-color LED.
LED_ PnLED1 should operate with the same polarity as other Bi-color LED pins. For example:
•
•
P0LED1 should be pulled up upon reset if P0LED1 is combined with P0LED2 as a Bi-color LED, and
P0LED2 input is pulled high upon reset. In this configuration, the output of these pins is active low
after reset
P0LED1 should be pulled down upon reset if P0LED1 is combined with P0LED2 as a Bi-color LED,
and P0LED2 input is pulled down upon reset. In this configuration, the output of these pins is active
high after reset
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Pull-Down
Pull-Up
DVDDIO
4.7K
ohm
LED Pin
470 ohm
470 ohm
4.7K
ohm
LED Pin
LED Pins Output Active High
LED Pins Output Active Low
Figure 8. Pull-Up and Pull-Down of LED Pins for Single-Color LED
Pull-Down
Pull-Up
SPD 1000
4.7K
ohm
DVDDIO
SPD 100
470ohm
470ohm
Yellow
SPD100
4.7K ohm
Green
Yellow
SPD1000
4.7K
ohm
Green
4.7K ohm
LED Pins Output Active High
LED Pins Output Active Low
Figure 9. Pull-Up and Pull-Down of LED Pins for Bi-Color LED
9.20. Green Ethernet
9.20.1. Link-On and Cable Length Power Saving
The RTL8367RB provides link-on and dynamic detection of cable length and dynamic adjustment of
power required for the detected cable length. This feature provides high performance with minimum
power consumption.
9.20.2. Link-Down Power Saving
The RTL8367RB implements link-down power saving on a per-port basis, greatly cutting power
consumption when the network cable is disconnected. After it detects an incoming signal, it wakes up
from link-down power saving and operates in normal mode.
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9.21. IEEE 802.3az Energy Efficient Ethernet (EEE) Function
The RTL8367RB supports IEEE 802.3az Energy Efficient Ethernet ability for 1000Base-T, 100Base-TX
in full duplex operation, and 10Base-T in full/half duplex mode.
The Energy Efficient Ethernet (EEE) optional operational mode combines the IEEE 802.3 Media Access
Control (MAC) sub-layer with 100Base-TX and 1000Base-T Physical Layers defined to support
operation in Low Power Idle mode. When Low Power Idle mode is enabled, systems on both sides of the
link can disable portions of the functionality and save power during periods of low link utilization.
•
•
•
1000Base-T PHY: Supports Energy Efficient Ethernet with the optional function of Low Power Idle
100Base-TX PHY: Supports Energy Efficient Ethernet with the optional function of Low Power Idle
For 10Base-T, EEE defines a 10Mbps PHY (10Base-Te) with reduced transmit amplitude
requirements. 10Base-Te is fully interoperable with 10Base-T PHYs over 100m of Class-D (Cat-5)
cable
The RTL8367RB MAC uses Low Power Idle signaling to indicate to the PHY, and to the link partner,
that a break in the data stream is expected, and components may use this information to enter power
saving modes that require additional time to resume normal operation. Similarly, it informs the LPI Client
that the link partner has sent such an indication.
9.22. Interrupt Pin for External CPU
The RTL8367RB provides one Interrupt output pin to interrupt an external CPU. The polarity of the
Interrupt output pin can be configured via register access. In configuration registers, each port has link-up
and link-down interrupt flags with mask.
When port link-up or link-down interrupt mask is enabled, the RTL8367RB will raise the interrupt signal
to alarm the external CPU. The CPU can read the interrupt flag to determine which port has changed to
which status.
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10. Interface Descriptions
10.1. EEPROM SMI Host to EEPROM
The EEPROM interface of the RTL8367RB uses the serial bus EEPROM Serial Management Interface
(SMI) to read the EEPROM space up to 256K-bits. When the RTL8367RB is powered up, it drives SCK
and SDA to read the registers from the EEPROM.
SCK
SDA
START
STOP
Figure 10. SMI Start and Stop Command
SCK
8
1
9
DATA IN
DATA OUT
ACKNOWLEDGE
START
Figure 11. EEPROM SMI Host to EEPROM
Figure 12. EEPROM SMI Host Mode Frame
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10.2. EEPROM SMI Slave for External CPU
When EEPROM auto-load is complete, the RTL8367RB registers can be accessed via SCK and SDA by
an external CPU. The device address of the RTL8367RB is 0x4. For the start and end of a write/read
command, SCK needs one extra clock before/after the start/stop signals.
Figure 13. EEPROM SMI Write Command for Slave Mode
Figure 14. EEPROM SMI Read Command for Slave Mode
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10.3. General Purpose Interface
The RTL8367RB supports two extension interfaces. The interface function mux is summarized in Table
17 and Table 18. The Extension GMAC1 and Extension GMAC2 of the RTL8367RB support RGMII,
MII MAC mode, or MII PHY mode via register configuration.
Table 17. RTL8367RB Extension Port 1 Pin Definitions
Pin No.
56
57
58
59
60
61
62
63
64
65
66
67
68
Extension
Interface
E1_CRS
E1_DO3
E1_DO2
E1_DO1
E1_DO0
E1_DOEN
E1_GCLK
E1_DICLK
E1_DIDV
E1_DI0
E1_DI1
E1_DI2
E1_DI3
Type
RGMII
MII MAC Mode
MII PHY Mode
I
O
O
O
O
O
O
I
I
I
I
I
I
RG1_TXD3
RG1_TXD2
RG1_TXD1
RG1_TXD0
RG1_TXCTL
RG1_TXCLK
RG1_RXCLK
RG1_RXCTL
RG1_RXD0
RG1_RXD1
RG1_RXD2
RG1_RXD3
M1M_CRS
M1M_TXD3
M1M_TXD2
M1M_TXD1
M1M_TXD0
M1M_TXEN
M1M_TXCLK
M1M_RXCLK
M1M_RXDV
M1M_RXD0
M1M_RXD1
M1M_RXD2
M1M_RXD3
M1P_RXD3
M1P_RXD2
M1P_RXD1
M1P_RXD0
M1P_RXDV
M1P_RXCLK
M1P_TXCLK
M1P_TXEN
M1P_TXD0
M1P_TXD1
M1P_TXD2
M1P_TXD3
Table 18. RTL8367RB Extension Port 2 Pin Definitions
Pin No.
40
41
42
43
44
45
46
47
48
49
50
51
52
Extension
Interface
E2_CRS
E2_DO3
E2_DO2
E2_DO1
E2_DO0
E2_DOEN
E2_GCLK
E2_DICLK
E2_DIDV
E2_DI0
E2_DI1
E2_DI2
E2_DI3
Type
RGMII
MII MAC Mode
MII PHY Mode
I
O
O
O
O
O
O
I
I
I
I
I
I
RG2_TXD3
RG2_TXD2
RG2_TXD1
RG2_TXD0
RG2_TXCTL
RG2_TXCLK
RG2_RXCLK
RG2_RXCTL
RG2_RXD0
RG2_RXD1
RG2_RXD2
RG2_RXD3
M2M_CRS
M2M_TXD3
M2M_TXD2
M2M_TXD1
M2M_TXD0
M2M_TXEN
M2M_TXCLK
M2M_RXCLK
M2M_RXDV
M2M_RXD0
M2M_RXD1
M2M_RXD2
M2M_RXD3
M2P_RXD3
M2P_RXD2
M2P_RXD1
M2P_RXD0
M2P_RXDV
M2P_RXCLK
M2P_TXCLK
M2P_TXEN
M2P_TXD0
M2P_TXD1
M2P_TXD2
M2P_TXD3
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
44
Track ID: JATR-2265-11 Rev. 1.0
RTL8367RB
Datasheet
10.3.1. Extension Ports RGMII Mode (1Gbps)
The Extension GMAC1 and Extension GMAC2 of the RTL8367RB support dual-port RGMII interfaces
to an external CPU. The pin numbers and names are shown in Table 19 and Table 20. Figure 15 shows
the signal diagram for Extension Port 1 and Extension Port 2 in RGMII interfaces.
RTL8367RB Pin No.
57, 58, 59, 60
61
62
63
64
65, 66, 67, 68
Table 19. Extension GMAC1 RGMII Pins
Type
Extension Port 1 RGMII
O
RG1_TXD[3:0]
O
RG1_TXCTL
O
RG1_TXCLK
I
RG1_RXCLK
I
RG1_RXCTL
I
RG1_RXD[0:3]
RTL8367RB Pin No.
41, 42, 43, 44
45
46
47
48
49, 50, 51, 52
Table 20. Extension GMAC2 RGMII Pins
Type
Extension Port 2 RGMII
O
RG2_TXD[3:0]
O
RG2_TXCTL
O
RG2_TXCLK
I
RG2_RXCLK
I
RG2_RXCTL
I
RG2_RXD[0:3]
Figure 15. RGMII Mode Interface Signal Diagram
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
45
Track ID: JATR-2265-11 Rev. 1.0
RTL8367RB
Datasheet
10.3.2. Extension Ports MII MAC/PHY Mode Interface (10/100Mbps)
Both the Extension GMAC1, and Extension GMAC2 of the RTL8367RB support MII MAC/PHY mode
interfaces to an external CPU. The pin numbers and names are shown in Table 21, and Table 22. Figure
16, page 47, shows the signal diagram for the MII PHY mode interface, and Figure 17, page 47, for the
MAC mode interface.
RTL8367RB
Pin No.
56
57, 58, 59, 60
61
62
63
64
65, 66, 67, 68
Table 21. Extension GMAC1 MII Pins
Extension Port 1
Type
Type
MII MAC Mode
I
M1M_CRS
O
M1M_TXD[3:0]
O
O
M1M_TXEN
O
I
M1M_TXCLK
O
I
M1M_RXCLK
O
I
M1M_RXDV
I
I
M1M_RXD[0:3]
I
Extension Port 1
MII PHY Mode
M1P_RXD[3:0]
M1P_RXDV
M1P_RXCLK
M1P_TXCLK
M1P_TXEN
M1P_TXD[0:3]
RTL8367RB
Pin No.
41, 42, 43, 44
45
46
47
48
49, 50, 51, 52
Table 22. Extension GMAC2 MII Pins
Extension Port 2
Type
Type
MII MAC Mode
O
M2M_TXD[3:0]
O
O
M2M_TXEN
O
I
M2M_TXCLK
O
I
M2M_RXCLK
O
I
M2M_RXDV
I
I
M2M_RXD[0:3]
I
Extension Port 2
MII PHY Mode
M2P_RXD[3:0]
M2P_RXDV
M2P_RXCLK
M2P_TXCLK
M2P_TXEN
M2P_TXD[0:3]
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
46
Track ID: JATR-2265-11 Rev. 1.0
RTL8367RB
Datasheet
Figure 16. Signal Diagram of MII PHY Mode Interface (100Mbps)
Figure 17. Signal Diagram of MII MAC Mode Interface (100Mbps)
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
47
Track ID: JATR-2265-11 Rev. 1.0
RTL8367RB
Datasheet
11. Register Descriptions
In this section the following abbreviations are used:
RO: Read Only
LH: Latch High until clear
RW: Read/Write
SC: Self Clearing
LL: Latch Low until clear
11.1. PCS Register (PHY 0~4)
Register
0
1
2
3
4
5
6
7
8
9
10
11~14
15
16~31
Table 23. PCS Register (PHY 0~4)
Register Description
Control Register
Status Register
PHY Identifier 1
PHY Identifier 2
Auto-Negotiation Advertisement Register
Auto-Negotiation Link Partner Ability Register
Auto-Negotiation Expansion Register
Auto-Negotiation Page Transmit Register
Auto-Negotiation Link Partner Next Page Register
1000Base-T Control Register
1000Base-T Status Register
Reserved
Extended Status
ASIC Control Register
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
48
Default
0x1140
0x7949
0x001C
0xC980
0x0DE1
0x0000
0x0004
0x2001
0x0000
0x0E00
0x0000
0x0000
0x2000
-
Track ID: JATR-2265-11 Rev. 1.0
RTL8367RB
Datasheet
11.2. Register 0: Control
Reg.bit
0.15
0.14
0.13
0.12
0.11
0.10
0.9
0.8
0.7
0.6
0.[5:0]
Table 24. Register 0: Control
Mode Description
RW/SC 1: PHY reset
0: Normal operation
This bit is self-clearing.
Loopback
RW
1: Enable loopback. This will loopback TXD to RXD and ignore
all activity on the cable media
(Digital loopback)
0: Normal operation
This function is usable only when this PHY is operated in
10Base-T full duplex, 100Base-TX full duplex, or 1000Base-T full
duplex.
Speed Selection[0]
RW
[0.6, 0.13] Speed Selection[1:0]
11: Reserved
10: 1000Mbps
01: 100Mbps
00: 10Mbps
This bit can be set through SMI (Read/Write).
RW
1: Enable auto-negotiation process
Auto Negotiation
Enable
0: Disable auto-negotiation process
This bit can be set through SMI (Read/Write).
Power Down
RW
1: Power down. All functions will be disabled except SMI function
0: Normal operation
Isolate
RW
1: Electrically isolates the PHY from GMII. The PHY is still able
to respond to MDC/MDIO
0: Normal operation
RW/SC 1: Restart Auto-Negotiation process
Restart Auto
Negotiation
0: Normal operation
Duplex Mode
RW
1: Full duplex operation
0: Half duplex operation
This bit can be set through SMI (Read/Write).
Collision Test
RO
1: Collision test enabled
0: Normal operation
When set, this bit will cause the COL signal to be asserted in
response to the assertion of TXEN within 512-bit times. The COL
signal will be de-asserted within 4-bit times in response to the deassertion of TXEN.
Speed Selection[1]
RW
See bit 13
Reserved
RO
Reserved
Name
Reset
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
49
Default
0
0
0
1
0
0
0
1
0
1
000000
Track ID: JATR-2265-11 Rev. 1.0
RTL8367RB
Datasheet
11.3. Register 1: Status
Reg.bit
1.15
Name
100Base-T4
Mode
RO
1.14
100Base-TX-FD
RO
1.13
100Base-TX-HD
RO
1.12
10Base-T-FD
RO
1.11
10Base-T-HD
RO
1.10
100Base-T2-FD
RO
1.9
100Base-T2-HD
RO
1.8
Extended Status
RO
1.7
1.6
Reserved
MF Preamble
Suppression
Auto-negotiate
Complete
Remote Fault
RO
RO
1.5
1.4
1.3
RO
RO/LH
RO
1.2
Auto-Negotiation
Ability
Link Status
RO/LL
1.1
Jabber Detect
RO/LH
1.0
Extended
Capability
RO
Table 25. Register 1: Status
Description
0: No 100Base-T4 capability
The RTL8367RB does not support 100Base-T4 mode and this bit
should always be 0.
1: 100Base-TX full duplex capable
0: Not 100Base-TX full duplex capable
1: 100Base-TX half duplex capable
0: Not 100Base-TX half duplex capable
1: 10Base-T full duplex capable
0: Not 10Base-TX full duplex capable
1: 10Base-T half duplex capable
0: Not 10Base-TX half duplex capable
0: Not 100Base-T2 full duplex capable
The RTL8367RB does not support 100Base-T2 mode and this bit
should always be 0.
0: Not 100Base-T2 half duplex capable
The RTL8367RB does not support 100Base-T2 mode and this bit
should always be 0.
1: Extended status information in Register 15
The RTL8367RB always supports Extended Status Register.
Reserved
The RTL8367RB will accept management frames with preamble
suppressed.
1: Auto-negotiation process completed
0: Auto-negotiation process not completed
1: Remote fault condition detected
0: No remote fault detected
This bit will remain set until it is cleared by reading register 1 via
the management interface.
1: Auto-negotiation capable (permanently =1)
1: Link is established. If the link fails, this bit will be 0 until after
reading this bit again
0: Link has failed since previous read
If the link fails, this bit will be set to 0 until bit is read.
1: Jabber detected
0: No Jabber detected
Jabber is supported only in 10Base-T mode.
1: Extended register capable (permanently =1)
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
50
Default
0
1
1
1
1
0
0
1
0
1
0
0
1
0
0
1
Track ID: JATR-2265-11 Rev. 1.0
RTL8367RB
Datasheet
11.4. Register 2: PHY Identifier 1
The PHY Identifier Registers #1 and #2 together form a unique identifier for the PHY section of this
device. The Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), the
vendor’s model number, and the model revision number. A PHY may return a value of zero in each of the
32 bits of the PHY Identifier if desired. The PHY Identifier is intended to support network management.
Reg.bit
2.[15:0]
Name
OUI
Table 26. Register 2: PHY Identifier 1
Mode Description
RO
Composed of the 3rd to 18th bits of the Organizationally Unique
Identifier (OUI), respectively.
Default
0x001C
11.5. Register 3: PHY Identifier 2
Reg.bit
3.[15:10]
3.[9:4]
3.[3:0]
Name
OUI
Model Number
Revision Number
Table 27. Register 3: PHY Identifier 2
Mode Description
RO
Assigned to the 19th through 24th bits of the OUI
RO
Manufacturer’s model number
RO
Manufacturer’s revision number
Default
110010
011000
0000
11.6. Register 4: Auto-Negotiation Advertisement
This register contains the advertisement abilities of this device as they will be transmitted to its Link
Partner during Auto-negotiation.
Note: Each time the link ability of the RTL8367RB is reconfigured, the auto-negotiation process should be
executed to allow the configuration to take effect.
Reg.bit
4.15
4.14
4.13
4.12
4.11
4.10
4.9
4.8
4.7
Table 28. Register 4: Auto-Negotiation Advertisement
Name
Mode Description
Next Page
RO
1: Additional next pages exchange desired
0: No additional next pages exchange desired
Acknowledge
RO
Permanently=0
Remote Fault
RW
1: Advertises that the RTL8367RB has detected a remote fault
0: No remote fault detected
Reserved
RO
Reserved
Reserved
RW
Reserved
Pause
RW
1: Advertises that the RTL8367RB has flow control capability
0: No flow control capability
100Base-T4
RO
1: 100Base-T4 capable
0: Not 100Base-T4 capable (Permanently =0)
100Base-TX-FD
RW
1: 100Base-TX full duplex capable
0: Not 100Base-TX full duplex capable
100Base-TX
RW
1: 100Base-TX half duplex capable
0: Not 100Base-TX half duplex capable
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
51
Default
0
0
0
0
0
1
0
1
1
Track ID: JATR-2265-11 Rev. 1.0
RTL8367RB
Datasheet
Reg.bit
4.6
Name
10Base-T-FD
Mode
RW
Description
1: 10Base-TX full duplex capable
0: Not 10Base-TX full duplex capable
4.5
10Base-T
RW
1: 10Base-TX half duplex capable
0: Not 10Base-TX half duplex capable
4.[4:0] Selector Field
RO
[00001]=IEEE 802.3
Note 1: The setting of Register 4 has no effect unless auto-negotiation is restarted or the link goes down.
Note 2: If 1000Base-T is advertised, then the required next pages are automatically transmitted.
Default
1
1
00001
11.7. Register 5: Auto-Negotiation Link Partner Ability
This register contains the advertised abilities of the Link Partner as received during Auto-negotiation. The
content changes after a successful Auto-negotiation.
Reg.bit
5.15
5.14
5.13
5.12
5.11
5.10
5.9
5.8
5.7
5.6
5.5
5.[4:0]
Table 29. Register 5: Auto-Negotiation Link Partner Ability
Mode Description
RO
1: Link partner desires Next Page transfer
0: Link partner does not desire Next Page transfer
Acknowledge
RO
1: Link Partner acknowledges reception of Fast Link Pulse (FLP)
words
0: Not acknowledged by Link Partner
Remote Fault
RO
1: Remote Fault indicated by Link Partner
0: No remote fault indicated by Link Partner
Reserved
RO
Reserved
Asymmetric Pause
RO
1: Asymmetric Flow control supported by Link Partner
0: No Asymmetric flow control supported by Link Partner
When auto-negotiation is enabled, this bit reflects Link Partner
ability
Pause
RO
1: Flow control supported by Link Partner.
0: No flow control supported by Link Partner
When auto-negotiation is enabled, this bit reflects Link Partner
ability
100Base-T4
RO
1: 100Base-T4 supported by Link Partner
0: 100Base-T4 not supported by Link Partner
100Base-TX-FD
RO
1: 100Base-TX full duplex supported by Link Partner
0: 100Base-TX full duplex not supported by Link Partner
100Base-TX
RO
1: 100Base-TX half duplex supported by Link Partner
0: 100Base-TX half duplex not supported by Link Partner
10Base-T-FD
RO
1: 10Base-TX full duplex supported by Link Partner
0: 10Base-TX full duplex not supported by Link Partner
10Base-T
RO
1: 10Base-TX half duplex supported by Link Partner
0: 10Base-TX half duplex not supported by Link Partner
Selector Field
RO
[00001]=IEEE 802.3
Name
Next Page
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
52
Default
0
0
0
0
0
0
0
0
0
0
0
00000
Track ID: JATR-2265-11 Rev. 1.0
RTL8367RB
Datasheet
11.8. Register 6: Auto-Negotiation Expansion
Reg.bit
6.[15:5]
6.4
6.3
6.2
6.1
6.0
Table 30. Register 6: Auto-Negotiation Expansion
Name
Mode Description
Reserved
RO
Ignore on read
RO/
1: A fault has been detected via the Parallel Detection function
Parallel Detection
Fault
LH
0: No fault has been detected via the Parallel Detection function
RO
1: Link Partner is Next Page able
Link Partner Next
Page Ability
0: Link Partner is not Next Page able
RO
Not supported. Permanently =0
Local Next Page
Ability
Page Received
RO/
1: A New Page has been received
LH
0: A New Page has not been received
RO
If Auto-Negotiation is enabled, this bit means:
Link Partner AutoNegotiation
1: Link Partner is Auto-Negotiation able
Ability
0: Link Partner is not Auto-Negotiation able
Default
0
0
0
1
0
0
11.9. Register 7: Auto-Negotiation Page Transmit Register
Reg.bit
7.15
7.14
7.13
7.12
7.11
7.[10:0]
Table 31. Register 7: Auto-Negotiation Page Transmit Register
Name
Mode Description
Next Page
RW
1: Link partner desires Next Page transfer
0: Link partner does not desire Next Page transfer
Reserved
RO
1: A fault has been detected via the Parallel Detection function
0: No fault has been detected via the Parallel Detection function
Message Page
RW
1: Message page
0: No Message page ability
Acknowledge 2
RW
1: Local device has the ability to comply with the message
received
0: Local device has no ability to comply with the message received
Toggle
RO
Toggle bit
RW
Content of message/unformatted page
Message/
Unformatted Field
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
53
Default
0
0
1
0
0
1
Track ID: JATR-2265-11 Rev. 1.0
RTL8367RB
Datasheet
11.10. Register 8: Auto-Negotiation Link Partner Next Page
Register
Reg.bit
8.15
8.14
8.13
8.12
8.11
8.[10:0]
Table 32. Register 8: Auto-Negotiation Link Partner Next Page Register
Name
Mode Description
Next Page
RO
Received Link Code Word Bit 15
Acknowledge
RO
Received Link Code Word Bit 14
Message Page
RO
Received Link Code Word Bit 13
Acknowledge 2
RO
Received Link Code Word Bit 12
Toggle
RO
Received Link Code Word Bit 11
RO
Received Link Code Word Bit 10:0
Message/
Unformatted Field
Default
0
0
0
0
0
0
11.11. Register 9: 1000Base-T Control Register
Table 33. Register 9: 1000Base-T Control Register
Reg.bit Name
Mode Description
9.[15:13] Test Mode
RW
Test Mode Select.
000: Normal mode
001: Test mode 1 – Transmit waveform test
010: Test mode 2 – Transmit jitter test in MASTER mode
011: Test mode 3 – Transmit jitter test in SLAVE mode
100: Test mode 4 – Transmitter distortion test
101, 110, 111: Reserved
9.12
RW
1: Enable MASTER/SLAVE manual configuration
MASTER/SLAVE
Manual Configuration
0: Disable MASTER/SLAVE manual configuration
Enable
9.11
RW
MASTER/SLAVE
1: Configure PHY as MASTER during MASTER/SLAVE
Configuration Value
negotiation, only when bit 9.12 is set to logical one
0: Configure PHY as SLAVE during MASTER/SLAVE
negotiation, only when bit 9.12 is set to logical one
9.10
Port Type
RW
1: Multi-port device
0: Single-port device
9.9
1000Base-T Full Duplex
RW
1: Advertise PHY is 1000Base-T full duplex capable
0: Advertise PHY is not 1000Base-T full duplex capable
9.8
1000Base-T Half Duplex
RW
1: Advertise PHY is 1000Base-T half duplex capable
0: Advertise PHY is not 1000Base-T half duplex capable
9.[7:0] Reserved
RW
Reserved
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
54
Default
000
0
1
1
1
0
0
Track ID: JATR-2265-11 Rev. 1.0
RTL8367RB
Datasheet
11.12. Register 10: 1000Base-T Status Register
Reg.bit
10.15
10.14
10.13
10.12
10.11
10.10
10.[9:8]
10.[7:0]
Table 34. Register 10: 1000Base-T Status Register
Name
Mode Description
MASTER/SLAVE
RO/LH/ 1: MASTER/SLAVE configuration fault detected
Configuration Fault
SC
0: No MASTER/SLAVE configuration fault detected
RO
1: Local PHY configuration resolved to MASTER
MASTER/SLAVE
Configuration Resolution
0: Local PHY configuration resolved to SLAVE
Local Receiver Status
RO
1: Local receiver OK
0: Local receiver not OK
Remote Receiver Status
RO
1: Remote receiver OK
0: Remote receiver not OK
RO
1: Link partner is capable of 1000Base-T full duplex
Link Partner 1000Base-T
Full Duplex
0: Link partner is not capable of 1000Base-T full duplex
1000Base-T Half Duplex
RO
1: Link partner is capable of 1000Base-T half duplex
0: Link partner is not capable of 1000Base-T half duplex
Reserved
RO
Reserved
Idle Error Count
RO/SC Idle Error Counter.
The counter stops automatically when it reaches 0xFF
Default
0
0
0
0
0
0
0
0
11.13. Register 15: Extended Status
Table 35. Register 15: Extended Status
Reg.bit Name
Mode Description
15.15
1000Base-X Full Duplex
RO
1: 1000Base-X full duplex capable
0: Not 1000Base-X full duplex capable
15.14
1000Base-X Half Duplex
RO
1: 1000Base-X half duplex capable
0: Not 1000Base-X half duplex capable
15.13
1000Base-T Full Duplex
RO
1: 1000Base-T full duplex capable
0: Not 1000Base-T full duplex capable
15.12
1000Base-T Half Duplex
RO
1: 1000Base-T half duplex capable
0: Not 1000Base-T half duplex capable
15.[11:0] Reserved
RO
Reserved
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
55
Default
0
0
1
0
0
Track ID: JATR-2265-11 Rev. 1.0
RTL8367RB
Datasheet
12. Electrical Characteristics
12.1. Absolute Maximum Ratings
WARNING: Absolute maximum ratings are limits beyond which permanent damage may be caused to
the device, or device reliability will be affected. All voltages are specified reference to GND unless
otherwise specified.
Table 36. Absolute Maximum Ratings
Parameter
Min
Junction Temperature (Tj)
Storage Temperature
-45
DVDDIO, DVDDIO_1, DVDDIO_2, AVDDH, Supply
GND-0.3
Referenced to GND and AGND
DVDDL, AVDDL, PLLVDDL0, PLLVDDL1 Supply Referenced
GND-0.3
to GND, AGND, and PLLGND0.
Digital Input Voltage
GND-0.3
Max
+125
+125
Units
°C
°C
+3.63
V
+1.1
V
VDDIO+0.3
V
12.2. Recommended Operating Range
Table 37. Recommended Operating Range
Parameter
Min
Typical
Ambient Operating Temperature (Ta)
0
DVDDIO, AVDDH Supply Voltage Range
3.135
3.3
3.135
3.3
DVDDIO_1, DVDDIO_2 Supply 3.3V
Voltage Range
2.5V
2.375
2.5
DVDDL, AVDDL, PLLVDDL0, PLLVDDL1 Supply Voltage
0.95
1.0
Range
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
56
Max
70
3.465
3.465
2.626
Units
°C
V
V
V
1.05
V
Track ID: JATR-2265-11 Rev. 1.0
RTL8367RB
Datasheet
12.3. Thermal Characteristics
12.3.1. Assembly Description
Package
PCB
Table 38. Assembly Description
Type
E-Pad LQFP-128
Dimension (L×W)
14×14mm
Thickness
1.4mm
PCB Dimension (L×W)
100×80mm
PCB Thickness
1.6mm
2-Layer:
- Top layer (1oz): 20% coverage of Cu
- Bottom layer (1oz): 75% coverage of Cu
4-Layer:
Number of Cu Layer-PCB
- 1st layer (1oz): 20% coverage of Cu
- 2nd layer (1oz): 80% coverage of Cu
- 3rd layer (1oz): 80% coverage of Cu
- 4th layer (1oz): 75% coverage of Cu
12.3.2. Material Properties
Item
Package
Die
Silver Paste
Lead Frame
Mold Compound
PCB
Table 39. Material Properties
Material
Thermal Conductivity K (W/m-k)
Si
147
1033BF
2.5
CDA7025
168
7372
0.9
Cu
400
FR4
0.2
12.3.3. Simulation Conditions
Table 40. Simulation Conditions
1.7W
2L (2S)/4L (2S2P)
Air Flow = 0, 1, 2 m/s
Input Power
Test Board (PCB)
Control Condition
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
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Track ID: JATR-2265-11 Rev. 1.0
RTL8367RB
Datasheet
12.3.4. Thermal Performance of E-Pad LQFP-128 on PCB Under Still
Air Convection
Table 41. Thermal Performance of E-Pad LQFP-128 on PCB Under Still Air Convection
θJA
θJB
θJC
ΨJB
4L PCB
TBD
TBD
TBD
TBD
2L PCB
TBD
TBD
TBD
TBD
Note:
θJA: Junction to ambient thermal resistance
θJB: Junction to board thermal resistance
θJC: Junction to case thermal resistance
ΨJB: Junction to bottom surface center of PCB thermal characterization
12.3.5. Thermal Performance of E-Pad LQFP-128 on PCB Under Forced
Convection
Table 42. Thermal Performance of E-Pad LQFP-128 on PCB Under Forced Convection
Air Flow (m/s)
0
1
2
θJA
TBD
TBD
TBD
4L PCB
ΨJB
TBD
TBD
TBD
θJA
TBD
TBD
TBD
2L PCB
TBD
TBD
TBD
ΨJB
Note:
θJA: Junction to ambient thermal resistance
θJB: Junction to board thermal resistance
θJC: Junction to case thermal resistance
ΨJB: Junction to bottom surface center of PCB thermal characterization
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
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Track ID: JATR-2265-11 Rev. 1.0
RTL8367RB
Datasheet
12.4. DC Characteristics
Table 43. DC Characteristics
Parameter
SYM
Min
Typical
Max
Units
IDVDDIO_1
40
mA
Power Supply Current for RGMII1 DVDDIO_1 (2.5V)
(For General Purpose Interface)
IDVDDIO_2
40
mA
Power Supply Current for RGMII1 DVDDIO_2 (2.5V)
(For General Purpose Interface)
System Idle (All UTP Port Link Down, without Extension ports and LEDs)
Power Supply Current for VDDH
IDVDDIO, IAVDDH
54
mA
Power Supply Current for VDDL
IDVDDL, IAVDDL, IPLLVDDL
146
mA
1000M Active (All UTP Ports Link/Active, without Extension ports and LEDs)
Power Supply Current for VDDH
IDVDDIO, IAVDDH
265
mA
Power Supply Current for VDDL
IDVDDL, IAVDDL, IPLLVDDL
830
mA
VDDIO=3.3V
TTL Input High Voltage
Vih
1.9
V
TTL Input Low Voltage
Vil
0.7
V
Output High Voltage
Voh
2.7
V
Output Low Voltage
Vol
0.6
V
VDDIO=2.5V
TTL Input High Voltage
Vih
1.7
V
TTL Input Low Voltage
Vil
0.7
V
Output High Voltage
Voh
2.25
V
Output Low Voltage
Vol
0.4
V
Note: Both IDVDDIO_1 & IDVDDIO_2 should be added to the total current consumption when the dual extension ports of the
RTL8367RB are used.
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
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Track ID: JATR-2265-11 Rev. 1.0
RTL8367RB
Datasheet
12.5. AC Characteristics
12.5.1. EEPROM SMI Host Mode Timing Characteristics
Figure 18. EEPROM SMI Host Mode Timing Characteristics
t9
nRESET
SCK
SDA
Figure 19. SCK/SDA Power on Timing
Figure 20. EEPROM Auto-Load Timing
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
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Track ID: JATR-2265-11 Rev. 1.0
RTL8367RB
Datasheet
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
-
Table 44. EEPROM SMI Host Mode Timing Characteristics
Description
Type
Min
Typical
SCK Clock Period
O
TBD
10
SCK High Time
O
TBD
5
SCK Low Time
O
TBD
5
START Condition Setup Time
O
TBD
5.04
START Condition Hold Time
O
TBD
4.96
Data Hold Time
O
TBD
2.52
Data Setup Time
O
TBD
2.48
STOP Condition Setup Time
O
TBD
5.04
SCK/SDA Active from Reset Ready
O
TBD
78.4
8K-bits EEPROM Auto-Load Time
O
TBD
26.4
SCK Rise Time (10% to 90%)
O
10.25
SCK Fall Time (90% to 10%)
O
10.7
Duty Cycle
O
TBD
50
Max
TBD
TBD
TBD
Units
µs
µs
µs
µs
µs
µs
µs
µs
ms
ms
ns
ns
%
Max
-
Units
µs
µs
µs
µs
µs
ns
ns
µs
12.5.2. EEPROM SMI Slave Mode Timing Characteristics
Figure 21. EEPROM SMI Slave Mode Timing Characteristics
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
Table 45. EEPROM SMI Slave Mode Timing Characteristics
Description
Type
Min
Typical
SCK High Time
I
4.0
SCK Low Time
I
4.0
START Condition Setup Time
I
4.0
START Condition Hold Time
I
4.0
Data Hold Time
I
5.0
Data Setup Time
I
250
Clock to Data Output Delay
O
40
STOP Condition Setup Time
I
4.0
-
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
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Track ID: JATR-2265-11 Rev. 1.0
RTL8367RB
Datasheet
12.5.3.
MDIO Slave Mode Timing Characteristics
The RTL8367RB supports MDIO slave mode. The Master (CPU) can access the Slave (RTL8367RB)
registers via the MDIO interface. The MDIO is a bi-directional signal that can be sourced by the Master
or the Slave. In a write command, the master sources the MDIO signal. In a read command, the slave
sources the MDIO signal.
•
•
The timing characteristics t1, t2, and t3 (Table 46) of the Master (the RTL8367RB link partner CPU)
are provided by the Master when the Master sources the MDIO signal (Write command)
The timing characteristics t4 (Table 46) of the Slave (RTL8367RB) are provided by the RTL8367RB
when the RTL8367RB sources the MDIO signal (Read command)
Figure 22. MDIO Sourced by Master
Figure 23. MDIO Sourced by RTL8367RB (Slave)
Table 46. MDIO Timing Characteristics and Requirement
Parameter
SYM
Description/Condition
Type Min
MDC Clock Period
t1
Clock Period
I
125
t2
Input Setup Time
MDIO to MDC Rising Setup
I
25
Time (Write Data)
t3
Input Hold Time
MDIO to MDC Rising Hold
I
25
Time (Write Data)
t4
MDC to MDIO Delay Time
Clock (Falling Edge) to Data
O
0
(Read Data)
Delay Time
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
62
Typical
-
Max
-
Units
ns
-
-
ns
-
-
ns
-
40
ns
Track ID: JATR-2265-11 Rev. 1.0
RTL8367RB
Datasheet
12.5.4. MII MAC Mode Timing
Figure 24. MII MAC Mode Clock to Data Output Delay Timing
Figure 25. MII MAC Mode Input Timing
Parameter
100Base-TX MxM_TXCLK and
MxM_RXCLK Input Cycle Time
10Base-T MxM_TXCLK and
MxM_RXCLK Input Cycle Time
MxM_TXCLK to MxM_TXD[3:0]
and MxM_TXEN Output Delay Time
MxM_RXD[3:0], MxM_RXDV, and
MxM_CRS Input Setup Time
MxM_RXD[3:0], MxM_RXDV, and
MxM_CRS Input Hold Time
Table 47. MII MAC Mode Timing
SYM
Description/Condition
TMM_TX_CYC 25MHz Clock Input.
TMM_RX_CYC
TMM_TX_CYC 2.5MHz Clock Input.
TMM_RX_CYC
TMM_COD
-
Type
I
Min
-
Typical
40
Max
-
Units
ns
I
-
400
-
ns
O
3
4.8
7
ns
TMM_RX_SU
-
I
10
-
-
ns
TMM_RX_HO
-
I
10
-
-
ns
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Datasheet
12.5.5. MII PHY Mode Timing
Figure 26. MII PHY Mode Output Timing
Figure 27. MII PHY Mode Clock Output to Data Input Delay Timing
Table 48. MII PHY Mode Timing Characteristics
Parameter
SYM
Description/Condition Type Min
TMP_RX_CYC 25MHz Clock Output.
O
100M MxP_RXCLK and
MxP_TXCLK Output Cycle Time
TMP_TX_CYC
TMP_RX_CYC 2.5MHz Clock Output.
O
10M MxP_RXCLK and
MxP_TXCLK Output Cycle Time
TMP_TX_CYC
O
14
TMP_RX_SU 100M MxP_RXD[3:0] and
MxP_RXDV to MxP_RXCLK
Output Setup Time
O
16
TMP_RX_HO 100M MxP_RXD[3:0] and
MxP_RXDV to MxP_RXCLK
Output Hold Time
I
0
TMP_COD
100M MxP_TXCLK Clock Output to
MxP_TXD[3:0] and MxP_TXEN
Input Delay Time
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
64
Typical
40
Max
-
Units
ns
400
-
ns
17.2
-
ns
20.4
-
ns
-
25
ns
Track ID: JATR-2265-11 Rev. 1.0
RTL8367RB
Datasheet
12.5.6. RGMII Timing Characteristics
Figure 28. RGMII Output Timing Characteristics (RGx_TXCLK_DELAY=0)
Figure 29. RGMII Output Timing Characteristics (RGx_TXCLK_DELAY=2ns)
Figure 30. RGMII Input Timing Characteristics (RGx_RXCLK_DELAY=0)
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
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Track ID: JATR-2265-11 Rev. 1.0
RTL8367RB
Datasheet
Figure 31. RGMII Input Timing Characteristics (RGx_RXCLK_DELAY=2ns)
Table 49. RGMII Timing Characteristics
SYM Description/Condition
Type
TTX_CYC 125MHz Clock Output.
O
Refer to Figure 28, page 65.
TTX_CYC 25MHz Clock Output.
O
Refer to Figure 28, page 65.
TTX_CYC 2.5MHz Clock Output.
O
Refer to Figure 28, page 65.
O
TskewT Disable Output Clock Delay.
RGx_TXD[3:0] and RGx_TXCTL to
RGx_TXCLK Output Skew
(RGx_TXCLK_DELAY=0).
Refer to Figure 28, page 65.
O
RGx_TXD[3:0] and RGx_TXCTL to TTX_SU Enable Output Clock Delay.
RGx_TXCLK Output Setup Time
(RGx_TXCLK_DELAY=1).
Refer to Figure 29, page 65.
O
RGx_TXD[3:0] and RGx_TXCTL to TTX_HO Enable Output Clock Delay.
RGx_TXCLK Output Hold Time
(RGx_TXCLK_DELAY=1).
Refer to Figure 29, page 65.
I
TRX_SU Disable Input Clock Delay.
RGx_RXD[3:0] and RGx_RXCTL
to RGx_RXCLK Input Setup Time
(RGx_RXCLK_DELAY=0).
Refer to Figure 30, page 65.
I
TRX_HO Disable Input Clock Delay.
RGx_RXD[3:0] and RGx_RXCTL
to RGx_RXCLK Input Hold Time
(RGx_RXCLK_DELAY=0).
Refer to Figure 30, page 65.
I
TskewR Enable Input Clock Delay.
RGx_RXD[3:0] and RGx_RXCTL
to RGx_RXCLK Input Skew
(RGx_RXCLK_DELAY=1).
Refer to Figure 31, page 66.
Parameter
1000M RGx_TXCLKc Output Cycle
Time
100M RGx_TXCLK Output Cycle
Time
10M RGx_TXCLK Output Cycle
Time
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
66
Min
7.6
Typical Max
8
8.6
Units
ns
38
40
42
ns
380
400
420
ns
-500
500
ps
1.2
-
ns
1.2
-
ns
1.0
-
-
ns
1.0
-
-
ns
-600
-
600
ps
Track ID: JATR-2265-11 Rev. 1.0
RTL8367RB
Datasheet
12.6. Power and Reset Characteristics
t3
t1
DVDDL
AVDDL
DVDDIO
DVDDIO _x
AVDDH
t2
t4
nRESET
Figure 32. Power and Reset Characteristics
Parameter
Reset Delay Time
Reset Low Time
VDDL Power Rise Settling
Time
VDDH Power Rise Settling
Time
Table 50. Power and Reset Characteristics
SYM Description/Condition
Type
t1
I
The duration from ‘all power steady’ to
the reset signal released to high
t2
I
The duration of reset signal remaining
low time before issuing a reset to the
RTL8367RB
t3
I
DVDDL and AVDDL power rise
settling time
t4
I
DVDDIO, DVDDIO_x, and AVDDH
power rise settling time
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
67
Min
10
Typical
-
Max
-
Units
ms
10
-
-
ms
1
-
-
ms
1
-
-
ms
Track ID: JATR-2265-11 Rev. 1.0
RTL8367RB
Datasheet
13. Mechanical Dimensions
Thermally Enhanced Low Profile Plastic Quad Flat Package 128 Leads 14×14mm Outline.
Symbol
Dimension in mm
Min
Nom
Max
A
—
—
1.60
A1
0.05
—
0.15
A2
1.35
1.40
1.45
b
0.13
0.18
0.23
D/E
16.00BSC
D1/E1
14.00BSC
D2/E2
5.00
5.50
6.00
e
0.40BSC
L
0.45
0.60
0.75
L1
1.00 REF
Note 1: CONTROLLING DIMENSION: MILLIMETER (mm).
Note 2: REFERENCE DOCUMENT: JEDEC MS-026.
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
Min
—
0.002
0.053
0.005
0.197
0.018
68
Dimension in inch
Nom
—
—
0.055
0.007
0.630BSC
0.551BSC
0.217
0.016BSC
0.024
0.039 REF
Max
0.063
0.006
0.057
0.09
0.237
0.030
Track ID: JATR-2265-11 Rev. 1.0
RTL8367RB
Datasheet
14. Ordering Information
Table 51. Ordering Information
Part Number
Package
RTL8367RB-CG
LQFP 128-Pin E-PAD ‘Green’ Package
Note: See page 9 for package identification.
Status
-
Realtek Semiconductor Corp.
Headquarters
No. 2, Innovation Road II, Hsinchu Science Park,
Hsinchu 300, Taiwan, R.O.C.
Tel: 886-3-5780211 Fax: 886-3-5776047
www.realtek.com
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
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Track ID: JATR-2265-11 Rev. 1.0
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