PMS132
12-bit ADC Enhanced Controller
Datasheet
Version 0.02 – Nov. 23, 2017
Copyright 2017 by PADAUK Technology Co., Ltd., all rights reserved
10F-2, No. 1, Sec. 2, Dong-Da Road, Hsin-Chu 300, Taiwan, R.O.C.
TEL: 886-3-532-7598
www.padauk.com.tw
PMS132
12-bit ADC Enhanced Controller
IMPORTANT NOTICE
PADAUK Technology reserves the right to make changes to its products or to terminate
production of its products at any time without notice. Customers are strongly
recommended to contact PADAUK Technology for the latest information and verify
whether the information is correct and complete before placing orders.
PADAUK Technology products are not warranted to be suitable for use in life-support
applications or other critical applications. PADAUK Technology assumes no liability for
such applications. Critical applications include, but are not limited to, those which may
involve potential risks of death, personal injury, fire or severe property damage.
PADAUK Technology assumes no responsibility for any issue caused by a customer’s
product design. Customers should design and verify their products within the ranges
guaranteed by PADAUK Technology. In order to minimize the risks in customers’ products,
customers should design a product with adequate operating safeguards.
PMS132 is NOT designed for AC RC step-down powered, high power ripple or high EFT
requirement application. Please do NOT apply PMS132 to those application products.
© Copyright 2017, PADAUK Technology Co. Ltd
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PDK-DS-PMS132-EN_V002 – Nov. 23, 2017
PMS132
12-bit ADC Enhanced Controller
Table of content
1. Features ................................................................................................................................. 9
1.1.
Special Features ..................................................................................................................... 9
1.2.
System Features ..................................................................................................................... 9
1.3.
CPU Features ......................................................................................................................... 9
1.4.
Package Information ............................................................................................................... 9
2. General Description and Block Diagram .......................................................................... 10
3. Pin Assignment and Description ...................................................................................... 11
4. Device Characteristics ....................................................................................................... 18
4.1.
AC/DC Device Characteristics .............................................................................................. 18
4.2.
Absolute Maximum Ratings................................................................................................... 20
4.3.
Typical ILRC frequency vs. VDD and temperature ................................................................ 21
4.4.
Typical IHRC frequency deviation vs. VDD ........................................................................... 21
4.5.
Typical ILRC Frequency vs. Temperature ............................................................................. 22
4.6.
Typical IHRC Frequency vs. Temperature (calibrated to 16MHz) .......................................... 22
4.7.
Typical operating current vs. VDD @ system clock = ILRC/n ................................................ 23
4.8.
Typical operating current vs. VDD @ system clock = IHRC/n ............................................... 23
4.9.
Typical operating current vs. VDD @ system clock = 4MHz EOSC / n .................................. 24
4.10.
Typical operating current vs. VDD @ system clock = 32KHz EOSC / n (reserved) ................ 24
4.11.
Typical operating current vs. VDD @ system clock = 1MHz EOSC / n .................................. 25
4.12.
Typical IO driving current (IOH) and sink current (IOL) ............................................................. 25
4.13.
Typical IO input high/low threshold voltage (VIH/VIL) .............................................................. 27
4.14.
Typical resistance of IO pull high device ............................................................................... 28
4.15.
Typical power down current (IPD) and power save current (IPS) .............................................. 28
4.16.
Timing charts for boot up conditions ...................................................................................... 29
5. Functional Description ....................................................................................................... 30
5.1.
Program Memory - OTP ........................................................................................................ 30
5.2.
Boot Procedure ..................................................................................................................... 30
5.3.
Data Memory - SRAM ........................................................................................................... 31
5.4.
Oscillator and clock ............................................................................................................... 31
5.4.1. Internal High RC oscillator and Internal Low RC oscillator ......................................... 31
5.4.2. Chip calibration .......................................................................................................... 31
5.4.3. IHRC Frequency Calibration and System Clock ........................................................ 32
5.4.4. External Crystal Oscillator ......................................................................................... 33
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12-bit ADC Enhanced Controller
5.4.5. System Clock and LVR level ..................................................................................... 35
5.4.6. System Clock Switching ............................................................................................ 36
5.5.
Comparator ........................................................................................................................... 37
5.5.1
Internal reference voltage (Vinternal R) ........................................................................... 38
5.5.2
Using the comparator ................................................................................................ 40
5.5.3
Using the comparator and band-gap 1.20V ............................................................... 40
5.6
16-bit Timer (Timer16) .......................................................................................................... 41
5.7
8-bit Timer (Timer2/Timer3) with PWM generation ................................................................ 43
5.8
5.7.1
Using the Timer2 to generate periodical waveform .................................................... 44
5.7.2
Using the Timer2 to generate 8-bit PWM waveform................................................... 45
5.7.3
Using the Timer2 to generate 6-bit PWM waveform................................................... 47
11-bit PWM Generator .......................................................................................................... 48
5.8.1
PWM Waveform ........................................................................................................ 48
5.8.2
Hardware and Timing Diagram .................................................................................. 49
5.8.3
Equations for 11-bit PWM Generator ......................................................................... 50
5.9
WatchDog Timer ................................................................................................................... 50
5.10
Interrupt ................................................................................................................................ 51
5.11
Power-Save and Power-Down .............................................................................................. 53
5.11.1 Power-Save mode (“stopexe”) ................................................................................... 53
5.11.2 Power-Down mode (“stopsys”) .................................................................................. 54
5.11.3 Wake-up .................................................................................................................... 54
5.12
IO Pins .................................................................................................................................. 55
5.13
Reset and LVR...................................................................................................................... 56
5.13.1 Reset ......................................................................................................................... 56
5.13.2 LVR reset .................................................................................................................. 56
5.14
Analog-to-Digital Conversion (ADC) module ......................................................................... 57
5.14.1 The input requirement for AD conversion .................................................................. 58
5.14.2 Select the reference high voltage .............................................................................. 59
5.14.3 ADC clock selection................................................................................................... 59
5.14.4 Configure the analog pins .......................................................................................... 59
5.14.5 Using the ADC........................................................................................................... 59
5.15
Multiplier ............................................................................................................................... 60
6. IO Registers ........................................................................................................................ 61
6.1.
ACC Status Flag Register (flag), IO address = 0x00 ............................................................. 61
6.2.
Stack Pointer Register (sp), IO address = 0x02 .................................................................... 61
6.3.
Clock Mode Register (clkmd), IO address = 0x03 ................................................................. 61
6.4.
Interrupt Enable Register (inten), IO address = 0x04 ............................................................ 62
6.5.
Interrupt Request Register (intrq), IO address = 0x05 ........................................................... 62
6.6.
Multiplier Operand Register (mulop), IO address = 0x08 ....................................................... 62
© Copyright 2017, PADAUK Technology Co. Ltd
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PMS132
12-bit ADC Enhanced Controller
6.7.
Multiplier Result High Byte Register (mulrh), IO address = 0x09 ........................................... 62
6.8.
Timer16 mode Register (t16m), IO address = 0x06............................................................... 63
6.9.
External Oscillator setting Register (eoscr), IO address = 0x0a............................................. 63
6.10.
Interrupt Edge Select Register (integs), IO address = 0x0c ................................................... 64
6.11.
Port A Digital Input Enable Register (padier), IO address = 0x0d .......................................... 64
6.12.
Port B Digital Input Enable Register (pbdier), IO address = 0x0e .......................................... 64
6.13.
Port A Data Register (pa), IO address = 0x10 ....................................................................... 65
6.14.
Port A Control Register (pac), IO address = 0x11 ................................................................. 65
6.15.
Port A Pull-High Register (paph), IO address = 0x12 ............................................................ 65
6.16.
Port B Data Register (pb), IO address = 0x14 ....................................................................... 65
6.17.
Port B Control Register (pbc), IO address = 0x15 ................................................................. 65
6.18.
Port B Pull-High Register (pbph), IO address = 0x16 ............................................................ 65
6.19.
Miscellaneous Register (misc), IO address = 0x17................................................................ 66
6.20.
Comparator Control Register (gpcc), IO address = 0x18 ....................................................... 66
6.21.
Comparator Selection Register (gpcs), IO address = 0x19 .................................................... 67
6.22.
Reset Status Register (rstst), IO address = 0x1b .................................................................. 67
6.23.
Timer2 Control Register (tm2c), IO address = 0x1c .............................................................. 68
6.24.
Timer2 Counter Register (tm2ct), IO address = 0x1d ............................................................ 68
6.25.
Timer2 Scalar Register (tm2s), IO address = 0x1e................................................................ 68
6.26.
Timer2 Bound Register (tm2b), IO address = 0x09 ............................................................... 69
6.27.
PWMG0 control Register (pwmg0c), IO address = 0x20 ....................................................... 69
6.28.
PWMG0 Scalar Register (pwmg0s), IO address = 0x21 ........................................................ 69
6.29.
PWMG0 Counter Upper Bound High Register (pwmg0cubh), IO address = 0x24 ................. 69
6.30.
PWMG0 Counter Upper Bound Low Register (pwmg0cubl), IO address = 0x25 ................... 70
6.31.
PWMG0 Duty Value High Register (pwmg0dth), IO address = 0x22 ..................................... 70
6.32.
PWMG0 Duty Value Low Register (pwmg0dtl), IO address = 0x23 ....................................... 70
6.33.
Timer3 Control Register (tm3c), IO address = 0x32 .............................................................. 70
6.34.
Timer3 Counter Register (tm3ct), IO address = 0x33 ............................................................ 71
6.35.
Timer3 Scalar Register (tm3s), IO address = 0x34................................................................ 71
6.36.
Timer3 Bound Register (tm3b), IO address = 0x3f ................................................................ 71
6.37.
ADC Control Register (adcc), IO address = 0x3b .................................................................. 71
6.38.
ADC Mode Register (adcm), IO address = 0x3c.................................................................... 72
6.39.
ADC Regulator Control Register (adcrgc), IO address = 0x3d............................................... 72
6.40.
ADC Result High Register (adcrh), IO address = 0x3e .......................................................... 72
6.41.
ADC Result Low Register (adcrl), IO address = 0x3f ............................................................. 72
6.42.
PWMG1 control Register (pwmg1c), IO address = 0x26 ....................................................... 73
6.43.
PWMG1 Scalar Register (pwmg1s), IO address = 0x27 ........................................................ 73
6.44.
PWMG1 Counter Upper Bound High Register (pwmg1cubh), IO address = 0x2A ................. 73
6.45.
PWMG1 Counter Upper Bound Low Register (pwmg1cubl), IO address = 0x2B ................... 73
6.46.
PWMG1 Duty Value High Register (pwmg1dth), IO address = 0x28 ..................................... 74
© Copyright 2017, PADAUK Technology Co. Ltd
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PMS132
12-bit ADC Enhanced Controller
6.47.
PWMG1 Duty Value Low Register (pwmg1dtl), IO address = 0x29 ....................................... 74
6.48.
PWMG2 control Register (pwmg2c), IO address = 0x2C....................................................... 74
6.49.
PWMG2 Scalar Register (pwmg2s), IO address = 0x2D ....................................................... 74
6.50.
PWMG2 Counter Upper Bound High Register (pwmg2cubh), IO address = 0x30 ................. 75
6.51.
PWMG2 Counter Upper Bound Low Register (pwmg2cubl), IO address = 0x31 ................... 75
6.52.
PWMG2 Duty Value High Register (pwmg2dth), IO address = 0x2E ..................................... 75
6.53.
PWMG2 Duty Value Low Register (pwmg2dtl), IO address = 0x2F ....................................... 75
7. Instructions ......................................................................................................................... 76
7.1.
Data Transfer Instructions ..................................................................................................... 77
7.2.
Arithmetic Operation Instructions .......................................................................................... 79
7.3.
Shift Operation Instructions ................................................................................................... 81
7.4.
Logic Operation Instructions.................................................................................................. 82
7.5.
Bit Operation Instructions ...................................................................................................... 84
7.6.
Conditional Operation Instructions ........................................................................................ 86
7.7.
System control Instructions ................................................................................................... 87
7.8.
Summary of Instructions Execution Cycle ............................................................................. 88
7.9.
Summary of affected flags by Instructions ............................................................................. 89
8. Code Options ...................................................................................................................... 90
9. Special Notes ...................................................................................................................... 91
9.1.
Warning ................................................................................................................................ 91
9.2.
Using IC ................................................................................................................................ 91
9.2.1 IO pin usage and setting ............................................................................................... 91
9.2.2
Interrupt ..................................................................................................................... 92
9.2.3
System clock switching .............................................................................................. 92
9.2.4
Power down mode, wakeup and watchdog ................................................................ 93
9.2.5
TIMER time out ......................................................................................................... 93
9.2.6
IHRC ......................................................................................................................... 93
9.2.7
LVR ........................................................................................................................... 94
9.2.8
The result of Comparator controls the PWM output pins ............................................ 94
9.2.9
Instructions ................................................................................................................ 94
9.2.10 BIT definition ............................................................................................................. 94
9.2.11 Programming the PMS132 ........................................................................................ 95
9.3
Using ICE.............................................................................................................................. 95
© Copyright 2017, PADAUK Technology Co. Ltd
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PDK-DS-PMS132-EN_V002 – Nov. 23, 2017
PMS132
12-bit ADC Enhanced Controller
Revision History:
Revision
Date
0.00
2016/08/08
0.01
2016/12/01
0.02
2017/11/23
Description
Preliminary version
1. Revise Chapter 3: Pin Assignment and Description
2. Revise Section 5.8.2: Hardware and Timing Diagram
3. Revise Section 5.8.3: Frequency of PWM Output
4. Add Section 5.8: 11-bit PWM Generator Functional Description
5. Add Section 6.43~6.51: IO Registers
1. Revise Section 1.2 System Features
2. Add Section 1.4 Package Information
3. Revise Chapter 2 General Description and Block Diagram
4. Add Chapter 3 Pin Assignment and Description:PMS132-S08,PMS132-U06
5. Revise Section 4.1 AC/DC Device Characteristics: “VIL” and “VIH”
6. Revise Section 4.3 Typical ILRC frequency vs. VDD and temperature
7. Revise Section 4.4 Typical IHRC frequency deviation vs. VDD
8. Revise Section 4.5 Typical ILRC Frequency vs. Temperature
9. Revise Section 4.6 Typical IHRC Frequency vs. Temperature
10. Revise Section 4.7 Typical operating current vs. VDD @ system clock = ILRC/n
11. Revise Section 4.8 Typical operating current vs. VDD @ system clock = IHRC/n
12. Revise Section 4.9 Typical operating current vs.VDD@system clock=4MHz EOSC / n
13. Revise Section 4.10 Typical operating current vs.VDD@system clock=32KHz EOSC / n
14. Revise Section 4.11 Typical operating current vs.VDD@system clock=1MHz EOSC / n
15. Revise Section 4.12 Typical IO driving current (IOH) and sink current (IOL)
16. Revise Section 4.13 Typical IO input high/low threshold voltage (VIH/VIL)
17. Revise Section 4.14 Typical resistance of IO pull high device
18. Add Section 4.15 Typical power down current (IPD) and power save current (IPS)
19. Revise Section 5.1 Program Memory - OTP
20. Revise Table 2: Three oscillation circuits
21. Revise Section 5.4.3 IHRC Frequency Calibration and System Clock
22. Revise Section 5.4.4 External Crystal Oscillator
23. Revise Fig. 3: Options of System Clock
24. Revise Section 5.5.2 Using the comparator
25. Revise Section 5.6 16-bit Timer
26. Revise Section 5.8 11-bit PWM Generator
27. Revise Section 5.11.1 Power-Save mode
28. Revise Fig. 20: ADC Block Diagram
29. Revise Section 5.14.4 Configure the analog pin
30. Revise Section 5.14.5 Using the ADC
31. Revise Section 6.3 Clock Mode Register
32. Revise Section 6.4 Interrupt Enable Register
33. Revise Section 6.5 Interrupt Request Register
34. Revise Section 6.11 Port A Digital Input Enable Register
35. Revise Section 6.12 Port B Digital Input Enable Register
36. Delete Section 6.13 MISC2 Register
37. Revise Section 6.21 Comparator Control Register
38. Revise Section 6.28 PWMG0 control Register
39. Revise Section 6.29 PWMG0 Counter Upper Bound High Register
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PMS132
12-bit ADC Enhanced Controller
40.
41.
42.
43.
44.
45.
46.
47.
48.
49.
50.
51.
52.
53.
54.
55.
56.
57.
58.
Revise Section 6.30 PWMG0 Counter Upper Bound Low Register
Revise Section 6.31 PWMG0 Duty Value High Register
Revise Section 6.32 PWMG0 Duty Value Low Register
Revise Section 6.38 ADC Control Register
Revise Section 6.40 ADC Regulator Control Register
Revise Section 6.43 PWMG1 control Register
Revise Section 6.49 PWMG2 control Register
Delete Chapter 7: Instructions symbol “word” and “pc0”
Revise Section 7.5 “swapc IO.n” Bit Operation Instruction
Add Chapter 8 Code Options
Revise Section 9.2.1 IO pin usage and setting
Revise Section 9.2.3 System clock switching
Add Section 9.2.6 IHRC
Revise Section 9.2.7 LVR
Revise Section 9.2.8 The result of Comparator controls the PWM output pins
Revise Section 9.2.10 BIT definition
Revise Section 9.2.11 Programming the PMS132
Revise Section 9.3 Using ICE
Revise all PWMG registers from ” R/W” to “WO”
© Copyright 2017, PADAUK Technology Co. Ltd
Page 8 of 95
PDK-DS-PMS132-EN_V002 – Nov. 23, 2017
PMS132
12-bit ADC Enhanced Controller
1. Features
1.1. Special Features
General purpose series
Please don’t apply to AC RC step-down powered, high power ripple or high EFT requirement application
Operating temperature range: -20°C ~ 70°C
1.2. System Features
2KW OTP program memory
128 Bytes data RAM
One hardware 16-bit timer
Two hardware 8-bit timers with PWM generation
Three hardware 11-bit PWM generators (PWMG0, PWMG1 & PWMG2)
Provide 1T 8x8 hardware multiplier
14 IO pins with optional pull-high resistor
Every IO pin can be configured to enable wake-up function
Band-gap circuit to provide 1.20V reference voltage
Up to 12-channel 12-bit resolution ADC
Provide ADC reference high voltage: external input, internal VDD, Band-gap(1.20V), 4V, 3V, 2V
Clock sources: internal high RC oscillator, internal low RC oscillator and external crystal oscillator
For every wake-up enabled IO, two optional wake-up speed are supported: normal and fast
Eight levels of LVR reset: 4.0V, 3.5V, 3.0V, 2.75V, 2.5V, 2.2V, 2.0V, 1.8V
Four selectable external interrupt pins
1.3. CPU Features
One processing unit operating mode
87 powerful instructions
Most instructions are 1T execution cycle
Programmable stack pointer to provide adjustable stack level
Direct and indirect addressing modes for data and instructions
All data memories are available for use as an index pointer
Separated IO and memory space
1.4. Package Information
PMS132-U06: SOT23-6 (60mil);
PMS132-S08: SOP8 (150mil);
PMS132-M10: MSOP10 (118mil);
PMS132-4N10: DFN3*3-10P (0.5pitch);
PMS132-S14: SOP14 (150mil);
PMS132-S16A: SOP16A (150mil);
PMS132-S16B: SOP16B (150mil);
PMS132-2J16A: QFN4*4-16P (0.65pitch);
PMS132-1J16A: QFN3*3-16P (0.5pitch)
© Copyright 2017, PADAUK Technology Co. Ltd
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PMS132
12-bit ADC Enhanced Controller
2. General Description and Block Diagram
The PMS132 family is an ADC-Type, fully static, OTP-based CMOS 8-bit microcontroller. It employs RISC
architecture and all the instructions are executed in one cycle except that some instructions are two cycles that
handle indirect memory access.
2KW bits OTP program memory and 128 bytes data SRAM are inside, one up to 12 channels 12-bit ADC is built
inside the chip with one channel for internal band-gap reference voltage or 0.25*VDD. PMS132 also provides six
hardware timers: one is 16-bit timer, two are 8-bit timers with PWM generation, and three hardware 11-bit timers
with PWM generation are also included.
© Copyright 2017, PADAUK Technology Co. Ltd
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PMS132
12-bit ADC Enhanced Controller
3. Pin Assignment and Description
VDD
1
16
GND
PA7/X1
2
15
PA0/AD10/CO/INT0/PG0PWM
PA6/X2
3
14
PA4/AD9/CIN+/CIN-/INT1A/PG1PWM
PA5/PRSTB/PG2PWM
4
13
PA3/AD8/CIN0-/TW2PWM/PG2PWM
PB7/AD7/CIN5-/TM3PWM/PG1PWM
5
12
PB3/AD3/PG2PWM
PB4/AD4/TW2PWM/PG0PWM
6
11
PB1/AD1/Vref
PB5/AD5/INT0A/TM3PWM/PG0PWM
7
10
PB0/AD0/INT1
PB6/AD6/CIN4-/TW3PWM/PG1PWM
8
9
PB2/AD2/TM2PWM/PG2PWM
PMS132-S16A (SOP16A-150mil)
GND
1
16
VDD
PA7/X1
2
15
PA0/AD10/CO/INT0/PG0PWM
PA6/X2
3
14
PA4/AD9/CIN+/CIN-/INT1A/PG1PWM
PA5/PRSTB/PG2PWM
4
13
PA3/AD8/CIN0-/TW2PWM/PG2PWM
PB7/AD7/CIN5-/TM3PWM/PG1PWM
5
12
PB3/AD3/PG2PWM
PB4/AD4/TW2PWM/PG0PWM
6
11
PB1/AD1/Vref
PB5/AD5/INT0A/TM3PWM/PG0PWM
7
10
PB0/AD0/INT1
PB6/AD6/CIN4-/TW3PWM/PG1PWM
8
9
PB2/AD2/TM2PWM/PG2PWM
PMS132-S16B (SOP16B-150mil)
VDD
1
14
GND
PA7/X1
2
13
PA0/AD10/CO/INT0/PG0PWM
PA6/X2
3
12
PA4/AD9/CIN+/CIN-/INT1A/PG1PWM
PA5/PRSTB/PG2PWM
4
11
PA3/AD8/CIN0-/TW2PWM/PG2PWM
PB7/AD7/CIN5-/TM3PWM/PG1PWM
5
10
PB3/AD3/PG2PWM
PB4/AD4/TW2PWM/PG0PWM
6
9
PB1/AD1/Vref
PB5/AD5/INT0A/TM3PWM/PG0PWM
7
8
PB0/AD0/INT1
PMS132-S14 (SOP14-150mil)
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PDK-DS-PMS132-EN_V002 – Nov. 23, 2017
PMS132
PA0/AD10/CO/INT0/PG0PWM
PA4/AD9/CIN+/CIN-/INT1A/PG1PWM
PA3/AD8/CIN0-/TW2PWM/PG2PWM
16
15
14
13
VDD 1
PG1PWMP
GND
12-bit ADC Enhanced Controller
12 PB3/AD3/PG2PWM
PA7/X1 2
11 PB1/AD1/Vref
PA6/X2 3
10 PB0/AD0/INT1
PA5/PRSTB/PG2PWM 4
5
6
7
8
PB7/AD7/CIN5-/TM3PWM/PG1PWM
PB4/AD4/TW2PWM/PG0PWM
PB5/AD5/INT0A/TM3PWM/PG0PWM
PB6/AD6/CIN4-/TW3PWM/PG1PWM
9 PB2/AD2/TM2PWM/PG2PWM
PMS132-2J16A(QFN4*4-16P-0.65pitch)
PMS132-1J16A(QFN3*3-16P-0.5pitch)
VDD
1
10
GND
PA6/X2
2
9
PA0/AD10/CO/INT0/PG0PWM
PA5/RSTB/PG2PWM
3
8
PA4/AD9/CIN+/CIN-/INT1A/PG1PWM
PB7/AD7/CIN5-/TM3PWM/PG1PWM
4
7
PA3/AD8/CIN0-/TW2PWM/PG2PWM
5
6
PB1/AD1/Vref
PB4/AD4/TW2PWM/PG0PWM
PMS132-M10 (MSOP10-118mil)
VDD
1
10
GND
PA6/X2
2
9
PA0/AD10/CO/INT0/PG0PWM
PA5/PRSTB/PG2PWM
3
8
PA4/AD9/CIN+/CIN-/INT1A/PG1PWM
PB7/AD7/CIN5-/TM3PWM/PG1PWM
4
7
PA3/AD8/CIN0-/TW2PWM/PG2PWM
PB4/AD4/TW2PWM/PG0PWM
5
6
PB1/AD1/Vref
PMS132-4N10 (DFN3*3-10P-0.5pitch)
© Copyright 2017, PADAUK Technology Co. Ltd
Page 12 of 95
PDK-DS-PMS132-EN_V002 – Nov. 23, 2017
PMS132
12-bit ADC Enhanced Controller
VDD
1
8
GND
PA6/X2
2
7
PA4/AD9/CIN+/CIN-/INT1A/PG1PWM
PA5/PRSTB/PG2PWM
3
6
PA3/AD8/CIN0-/TW2PWM/PG2PWM
PB7/AD7/CIN5-/TM3PWM/PG1PWM
4
5
PB1/AD1/Vref
PMS132-S08 (SOP8-150mil)
PA4/AD9/CIN+/CIN-/INT1A/PG1PWM
PA4
1
6
PA3/AD8/CIN0-/TW2PWM/PG2PWM
GND
GND
2
5
VDD
PA6/X2
PA6
3
4
PA5/PRSTB/PG2PWM
PA5/PRSTB
PMS132-U06 (SOT23-6 60mil)
Pin Description
Pin Name
Pin Type &
Description
Buffer Type
The functions of this pin can be:
PA7 /
X1
IO
ST /
CMOS
(1) Bit 7 of port A. It can be configured as input or output with pull-up resistor.
(2) X1 when crystal oscillator is used.
If this pin is used for crystal oscillator, bit 7 of padier register must be programmed “0”
to avoid leakage current. This pin can be used to wake-up system during sleep mode;
however, wake-up function is also disabled if bit 7 of padier register is “0”.
The functions of this pin can be:
PA6 /
X2
IO
ST /
CMOS
(1) Bit 6 of port A. It can be configured as input or output with pull-up resistor.
(2) X2 when crystal oscillator is used.
If this pin is used for crystal oscillator, bit 6 of padier register must be programmed “0”
to avoid leakage current. This pin can be used to wake-up system during sleep mode;
however, wake-up function is also disabled if bit 6 of padier register is “0”.
The functions of this pin can be:
PA5 /
PRSTB /
PG2PWM
(1) Bit 5 of port A. It can be configured as input or open-drain output pin
IO (OD)
ST /
CMOS
(2) Hardware reset
(3) Output of 11-bit PWM generator PWMG2
This pin can be used to wake-up system during sleep mode; however, wake-up
function is also disabled if bit 5 of padier register is “0”. Please put 33Ω resistor in
series to have high noise immunity when this pin is in input mode.
© Copyright 2017, PADAUK Technology Co. Ltd
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PDK-DS-PMS132-EN_V002 – Nov. 23, 2017
PMS132
12-bit ADC Enhanced Controller
Pin Name
Pin Type &
Description
Buffer Type
The functions of this pin can be:
(1) Bit 4 of port A. It can be configured as digital input, two-state output with pull-up
resistor by software independently
PA4 /
(2) Channel 9 of ADC analog input
AD9 /
(3) Plus input source of comparator
CIN+ /
IO
CIN1- /
ST /
(4) Minus input source 1 of comparator
(5) External interrupt line 1A. It can be used as an external interrupt line 1. Both rising
INT1A /
CMOS /
edge and falling edge are accepted to request interrupt service and configurable
PG1PWM
Analog
by register setting
(6) Output of 11-bit PWM generator PWMG1
When this pin is configured as analog input, please use bit 4 of register padier to
disable the digital input to prevent current leakage. The bit 4 of padier register can be
set to “0” to disable digital input; wake-up from power-down by toggling this pin is also
disabled.
The functions of this pin can be:
(1) Bit 3 of port A. It can be configured as digital input, two-state output with pull-up
resistor independently by software
PA3 /
AD8 /
CIN0- /
TM2PWM /
PG2PWM
IO
ST /
CMOS /
Analog
(2) Channel 8 of ADC analog input
(3) Minus input source 0 of comparator
(4) PWM output from Timer2
(5) Output of 11-bit PWM generator PWMG2
When this pin is configured as analog input, please use bit 3 of register padier to
disable the digital input to prevent current leakage. The bit 3 of padier register can be
set to “0” to disable digital input; wake-up from power-down by toggling this pin is also
disabled.
The functions of this pin can be:
(1) Bit 0 of port A. It can be configured as digital input, two-state output with pull-up
resistor independently by software
PA0 /
AD10 /
CO /
PG0PWM /
INT0
IO
ST /
CMOS /
Analog
(2) Channel 10 of ADC analog input
(3) Output of comparator
(4) Output of 11-bit PWM generator PWMG0
(5) External interrupt line 0. It can be used as an external interrupt line 0. Both rising
edge and falling edge are accepted to request interrupt service and configurable
by register setting
The bit 0 of padier register can be set to “0” to disable wake-up from power-down by
toggling this pin.
© Copyright 2017, PADAUK Technology Co. Ltd
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PDK-DS-PMS132-EN_V002 – Nov. 23, 2017
PMS132
12-bit ADC Enhanced Controller
Pin Name
Pin Type &
Description
Buffer Type
The functions of this pin can be:
(1) Bit 7 of port B. It can be configured as digital input, two-state output with pull-up
resistor independently by software
PB7 /
AD7 /
CIN5- /
TM3PWM/
PG1PWM
IO
ST /
CMOS /
Analog
(2) Channel 7 of ADC analog input
(3) Minus input source 5 of comparator
(4) PWM output from Timer3
(5) Output of 11-bit PWM generator PWMG1
When this pin is configured as analog input, please use bit 7 of register pbdier to
disable the digital input to prevent current leakage. The bit 7 of pbdier register can be
set to “0” to disable digital input; wake-up from power-down by toggling this pin is also
disabled.
The functions of this pin can be:
(1) Bit 6 of port B. It can be configured as digital input, two-state output with pull-up
resistor independently by software
PB6 /
AD6 /
IO
CIN4- /
ST /
TM3PWM/
CMOS /
PG1PWM
Analog
(2) Channel 6 of ADC analog input
(3) Minus input source 4 of comparator.
(4) PWM output from Timer3
(5) Output of 11-bit PWM generator PWMG1
When this pin is configured as analog input, please use bit 6 of register pbdier to
disable the digital input to prevent current leakage. The bit 6 of pbdier register can be
set to “0” to disable digital input; wake-up from power-down by toggling this pin is also
disabled.
The functions of this pin can be:
(1) Bit 5 of port B. It can be configured as digital input, two-state output with pull-up
resistor independently by software
(2) Channel 5 of ADC analog input
PB5 /
AD5 /
TM3PWM /
PG0PWM /
INT0A
IO
ST /
CMOS /
Analog
(3) PWM output from Timer3
(4) Output of 11-bit PWM generator PWMG0.
(5) External interrupt line 0A. It can be used as an external interrupt line 0. Both rising
edge and falling edge are accepted to request interrupt service and configurable
by register setting.
When this pin is configured as analog input, please use bit 5 of register pbdier to
disable the digital input to prevent current leakage. The bit 5 of pbdier register can be
set to “0” to disable digital input; wake-up from power-down by toggling this pin is also
disabled.
© Copyright 2017, PADAUK Technology Co. Ltd
Page 15 of 95
PDK-DS-PMS132-EN_V002 – Nov. 23, 2017
PMS132
12-bit ADC Enhanced Controller
Pin Name
Pin Type &
Description
Buffer Type
The functions of this pin can be:
(1) Bit 4 of port B. It can be configured as digital input, two-state output with pull-up
resistor independently by software
PB4 /
IO
AD4 /
ST /
(2) Channel 4 of ADC analog input
TM2PWM /
CMOS /
(4) Output of 11-bit PWM generator PWMG0.
PG0PWM
Analog
When this pin is configured as analog input, please use bit 4 of register pbdier to
(3) PWM output from Timer2
disable the digital input to prevent current leakage. The bit 4 of pbdier register can
be set to “0” to disable digital input; wake-up from power-down by toggling this pin is
also disabled.
The functions of this pin can be:
(1) Bit 3 of port B. It can be configured as digital input, two-state output with pull-up
PB3 /
IO
AD3 /
ST /
PG2PWM
CMOS /
Analog
resistor independently by software
(2) Channel 3 of ADC analog input
(3) Output of 11-bit PWM generator PWMG2
When this pin is configured as analog input, please use bit 3 of register pbdier to
disable the digital input to prevent current leakage. The bit 3 of pbdier register can
be set to “0” to disable digital input; wake-up from power-down by toggling this pin is
also disabled.
The functions of this pin can be:
(1) Bit 2 of port B. It can be configured as digital input, two-state output with pull-up
resistor independently by software
PB2 /
IO
(2) Channel 2 of ADC analog input
AD2 /
ST /
TM2PWM /
CMOS /
(4) Output of 11-bit PWM generator PWMG2
PG2PWM
Analog
When this pin is configured as analog input, please use bit 2 of register pbdier to
(3) PWM output from Timer2
disable the digital input to prevent current leakage. The bit 2 of pbdier register can
be set to “0” to disable digital input; wake-up from power-down by toggling this pin is
also disabled.
The functions of this pin can be:
(1) Bit 1 of port B. It can be configured as digital input, two-state output with pull-up
PB1 /
AD1 /
Vref
IO
ST /
CMOS /
Analog
resistor independently by software
(2) Channel 1 of ADC analog input
(3) External reference high voltage for ADC.
When this pin is configured as analog input, please use bit 1 of register pbdier to
disable the digital input to prevent current leakage. The bit 1 of pbdier register can
be set to “0” to disable digital input; wake-up from power-down by toggling this pin is
also disabled.
© Copyright 2017, PADAUK Technology Co. Ltd
Page 16 of 95
PDK-DS-PMS132-EN_V002 – Nov. 23, 2017
PMS132
12-bit ADC Enhanced Controller
Pin Name
Pin Type &
Description
Buffer Type
The functions of this pin can be:
(1) Bit 0 of port B. It can be configured as analog input, digital input, and two-state
output mode with pull-up resistor independently by software.
PB0 /
AD0 /
INT1
IO
ST /
(2) Channel 0 of ADC analog input.
(3) External interrupt line 1. It can be used as an external interrupt line 1. Both rising
CMOS /
edge and falling edge are accepted to request interrupt service and configurable
Analog
by register setting.
When this pin acts as analog input, please use bit 0 of register pbdier to disable the
digital input to prevent current leakage. If bit 0 of pbdier register is set to “0” to
disable digital input, wake-up from power-down by toggling this pin is also disabled.
VDD
VDD
Positive power
GND
GND
Ground
Notes: IO: Input/Output; ST: Schmitt Trigger input; OD: Open Drain; Analog: Analog input pin
CMOS: CMOS voltage level
© Copyright 2017, PADAUK Technology Co. Ltd
Page 17 of 95
PDK-DS-PMS132-EN_V002 – Nov. 23, 2017
PMS132
12-bit ADC Enhanced Controller
4. Device Characteristics
4.1. AC/DC Device Characteristics
All data are acquired under the conditions of VDD=5.0V, fSYS =2MHz unless noted.
Symbol
VDD
LVR%
fSYS
IOP
IPD
IPS
Description
Operating Voltage
Low Voltage Reset Tolerance
System clock (CLK)* =
IHRC/2
IHRC/4
IHRC/8
ILRC
VIH
Input high voltage for IO lines
VIN
IINJ (PIN)
Max
Unit
2.2
-5
5.0
5.5
5
V
%
8M
4M
2M
Hz
0
0
0
Power Down Current
(by stopsys command)
Power Save Current
(by stopexe command)
Input low voltage for IO lines
IOH
Typ
Operating Current
VIL
IOL
Min
mA
uA
uA
uA
5
uA
0
0.1 VDD
0
0.2 VDD
0.8 VDD
VDD
0.7 VDD
VDD
IO lines sink current
PA5
PA0, PA3, PA4
PA6, PA7, PB0, PB1, PB3 PB2,
PB5, PB6
PB4, PB7 (Normal)
PB4, PB7 (Low)
IO lines drive current
PA5
PB4, PB7 (Normal)
PB4, PB7 (Low)
Others IO
Input voltage
55K
1
15
1
0.6
23
20
13
13
40
20
0
-20
-10
-10
-0.3
Injected current on pin
V
V
Pull-high Resistance
fIHRC
tINT
Band-gap Reference Voltage
Frequency of IHRC after
calibration *
Interrupt pulse width
© Copyright 2017, PADAUK Technology Co. Ltd
PA5
Others IO
VDD=5.0V, VOH=4.5V
V
1
mA
VDD +0.3≧VIN≧ -0.3
VDD =5.0V
KΩ
VDD =3.3V
VDD =2.2V
1.145*
1.20*
1.255*
15.76*
16*
16.24*
15.20*
16*
16.80*
Page 18 of 95
Others IO
mA
VDD +0.3
200
30
PA5
VDD=5.0V, VOL=0.5V
450
VBG
VDD ≧ 3.5V
VDD ≧ 2.5V
VDD ≧ 2.2V
VDD =5.0V
fSYS=IHRC/16=1MIPS@5.0V
fSYS=ILRC=55KHz@3.3V
fSYS= 0Hz, VDD =5.0V
fSYS= 0Hz, VDD =3.3V
VDD =5.0V; fSYS= ILRC
Only ILRC module is enabled.
mA
100
RPH
o
Conditions (Ta=25 C)
V
VDD =2.2V ~ 5.5V
o
o
-20 C “IC Introduction” ->
“Register Introduction” -> CLKMD”.
Case 1: Switching system clock from ILRC to IHRC/2
…
CLKMD
CLKMD.2
…
=
=
//
//
//
0x34；
0；
system clock is ILRC
switch to IHRC/2, ILRC CAN NOT be disabled here
ILRC CAN be disabled at this time
Case 2: Switching system clock from ILRC to EOSC
…
CLKMD
CLKMD.2
…
=
=
//
//
//
0xA6；
0；
system clock is ILRC
switch to IHRC, ILRC CAN NOT be disabled here
ILRC CAN be disabled at this time
Case 3: Switching system clock from IHRC/2 to ILRC
…
//
system clock is IHRC/2
CLKMD
=
0xF4；
//
switch to ILRC, IHRC CAN NOT be disabled here
CLKMD.4
=
0；
//
IHRC CAN be disabled at this time
…
Case 4: Switching system clock from IHRC/2 to EOSC
…
//
system clock is IHRC/2
CLKMD
=
0XB0；
//
switch to EOSC, IHRC CAN NOT be disabled here
CLKMD.4
=
0；
//
IHRC CAN be disabled at this time
…
Case 5: Switching system clock from IHRC/2 to IHRC/4
…
CLKMD
=
0X14；
//
system clock is IHRC/2, ILRC is enabled here
//
switch to IHRC/4
…
Case 6: System may hang if it is to switch clock and turn off original oscillator at the same time
…
CLKMD
=
0x30；
//
system clock is ILRC
//
CAN NOT switch clock from ILRC to IHRC/2 and
turn off ILRC oscillator at the same time
© Copyright 2017, PADAUK Technology Co. Ltd
Page 36 of 95
PDK-DS-PMS132-EN_V002 – Nov. 23, 2017
PMS132
12-bit ADC Enhanced Controller
5.5. Comparator
One hardware comparator is built inside the PMS132; Fig.4 shows its hardware diagram. It can compare signals
between two pins or with either internal reference voltage Vinternal R or internal band-gap reference voltage. The
two signals to be compared, one is the plus input and the other one is the minus input. For the minus input of
comparator can be PA3, PA4, Internal band-gap 1.20 volt, PB6, PB7 or Vinternal R selected by bit [3:1] of gpcc
register, and the plus input of comparator can be PA4 or Vinternal R selected by bit 0 of gpcc register. The output
result can be enabled to output to PA0 directly, or sampled by Time2 clock (TM2_CLK) which comes from
Timer2 module. The output can be also inversed the polarity by bit 4 of gpcc register, the comparator output can
be used to request interrupt service.
16 stages
VDD
8R
8R
8R
R
gpcs.5=1
R
R
R
gpcs.4=0
gpcs.4=1
gpcs.5=0
gpcs[3:0]
MUX
Vinternal R
gpcc[3:1]
PA3/CIN1PA4/CIN+
Band-gap
PB6/CIN2PB7/CIN3-
000
001 M
010 U
011 X
100
101
0 MUX
PA4/CIN+
1
gpcc.4
+
Timer 2
clock
TM2_CLK
D
F
F
M
U
X
gpcc.5
gpcc.0
X
O
R
To request interrupt
(rising edge)
gpcc.6
To
PA0
gpcs.7
Fig.4: Hardware diagram of comparator
© Copyright 2017, PADAUK Technology Co. Ltd
Page 37 of 95
PDK-DS-PMS132-EN_V002 – Nov. 23, 2017
PMS132
12-bit ADC Enhanced Controller
5.5.1
Internal reference voltage (Vinternal R)
The internal reference voltage Vinternal R is built by series resistance to provide different level of reference
voltage, bit 4 and bit 5 of gpcs register are used to select the maximum and minimum values of Vinternal R
and bit [3:0] of gpcs register are used to select one of the voltage level which is deivided-by-16 from the
defined maximum level to minimum level. Fig.5 to Fig.8 shows four conditions to have different reference
voltage Vinternal R. By setting the gpcs register, the internal reference voltage Vinternal R can be ranged from
(1/32)*VDD to (3/4)*VDD.
Case 1 : gpcs.5=0 & gpcs.4=0
16 stages
VDD
8R
8R
8R
gpcs.5=1
R
R
R
R
gpcs.5=0
gpcs.4=0
gpcs.4=1
MUX
gpcs[3:0]
V internal R = (3/4) VDD ~ (1/4) VDD + (1/32) VDD
@ gpcs[3:0] = 1111 ~ gpcs[3:0] = 0000
1
V internal R =
4
(n+1)
* VDD +
32
* VDD, n = gpcs[3:0] in decimal
Fig.5: Vinternal R hardware connection if gpcs.5=0 and gpcs.4=0
Case 2 : gpcs.5=0 & gpcs.4= 1
16 stages
VDD
8R
8R
gpcs.5=1
8R
R
R
R
R
gpcs.5=0
gpcs.4=0
gpcs.4=1
MUX
gpcs[3:0]
V internal R = (2/3) VDD ~ (1/24) VDD
@ gpcs[3:0] = 1111 ~ gpcs[3:0] = 0000
V internal R =
(n+1)
24
* VDD, n = gpcs[3:0] in decimal
Fig.6: Vinternal R hardware connection if gpcs.5=0 and gpcs.4=1
© Copyright 2017, PADAUK Technology Co. Ltd
Page 38 of 95
PDK-DS-PMS132-EN_V002 – Nov. 23, 2017
PMS132
12-bit ADC Enhanced Controller
Case 3 : gpcs.5= 1 & gpcs.4= 0
16 stages
VDD
8R
8R
8R
gpcs.5=1
R
R
R
R
gpcs.5=0
gpcs.4=0
gpcs.4=1
MUX
gpcs[3:0]
V internal R = (3/5) VDD ~ (1/5) VDD + (1/40) VDD
@ gpcs[3:0] = 1111 ~ gpcs[3:0] = 0000
1
V internal R =
5
(n+1)
* VDD +
40
* VDD, n = gpcs[3:0] in decimal
Fig.7: Vinternal R hardware connection if gpcs.5=1 and gpcs.4=0
Case 4 : gpcs.5=1 & gpcs.4=1
VDD
8R
16 stages
8R
gpcs.5=1
8R
R
R
R
R
gpcs.5=0
gpcs.4=0
gpcs.4=1
MUX
gpcs[3:0]
V internal R = (1/2) VDD ~ (1/32) VDD
@ gpcs[3:0] = 1111 ~ gpcs[3:0] = 0000
V internal R =
(n+1)
* VDD, n = gpcs[3:0] in decimal
32
Fig.8: Vinternal R hardware connection if gpcs.5=1 and gpcs.4=1
© Copyright 2017, PADAUK Technology Co. Ltd
Page 39 of 95
PDK-DS-PMS132-EN_V002 – Nov. 23, 2017
PMS132
12-bit ADC Enhanced Controller
5.5.2
Using the comparator
Case I:
Choosing PA3 as minus input and Vinternal R with (18/32)*VDD voltage level as plus input, the comparator
result will be output to PA0, the comparator result will be output to PA0. Vinternal R is configured as Fig. 10
and gpcs [3:0] = 4b’1001 (n=9) to have Vinternal R = (1/4)*VDD + [(9+1)/32]*VDD = (18/32)*VDD.
gpcs
= 0b1_0_00_1001;
// output to PA0, Vinternal R = VDD*(18/32)
gpcc
= 0b1_0_0_0_000_0;
// enable comp, - input: PA3, + input: Vinternal R
padier = 0bxxxx_0_xxx;
// disable PA3 digital input to prevent leakage current
Case 2:
Choosing Vinternal R as minus input with (14/32)*VDD voltage level and PA4 as plus input, the comparator
result will be inversed and then output to PA0. Vinternal R is configured as Fig. 11 and gpcs [3:0] = 4b’1101
(n=13) to have Vinternal R = [(13+1)/32]*VDD = (14/32)*VDD.
gpcs
= 0b1_1_1_1_1101;
// Vinternal R = VDD*(14/32)
gpcc
= 0b1_0_0_1_011_1;
// Inverse output, - input: Vinternal R, + input: PA4
padier = 0bxxx_0_xxxx;
5.5.3
// disable PA4 digital input to prevent leakage current
Using the comparator and band-gap 1.20V
The internal band-gap module can provide 1.20 volt, it can measure the external supply voltage level. The
band-gap 1.20 volt is selected as minus input of comparator and Vinternal R is selected as plus input, the
supply voltage of Vinternal R is VDD, the VDD voltage level can be detected by adjusting the voltage level of
Vinternal R to compare with band-gap. If N (gpcs[3:0] in decimal) is the number to let Vinternal R closest to
band-gap 1.20 volt, the supply voltage VDD can be calculated by using the following equations:
For using Case 1: VDD = [ 32 / (N+9) ] * 1.20 volt ;
For using Case 2: VDD = [ 24 / (N+1) ] * 1.20 volt ;
For using Case 3: VDD = [ 40 / (N+9) ] * 1.20 volt ;
For using Case 4: VDD = [ 32 / (N+1) ] * 1.20 volt ;
More information and sample code, please refer to IDE utility.
© Copyright 2017, PADAUK Technology Co. Ltd
Page 40 of 95
PDK-DS-PMS132-EN_V002 – Nov. 23, 2017
PMS132
12-bit ADC Enhanced Controller
5.6 16-bit Timer (Timer16)
A 16-bit hardware timer (Timer16) is implemented in the PMS132, the clock sources of Timer16 may come
from system clock (CLK), clock of external crystal oscillator (EOSC), internal high RC oscillator (IHRC),
internal low RC oscillator (ILRC), PA4 and PA0, a multiplex is used to select clock output for the clock source.
Before sending clock to the counter16, a pre-scaling logic with divided-by-1, 4, 16, and 64 is used for wide
range counting. The 16-bit counter performs up-counting operation only, the counter initial values can be
stored from memory by stt16 instruction and the counting values can be loaded to memory by ldt16 instruction.
A selector is used to select the interrupt condition of Timer16, whenever overflow occurs, the Timer16 interrupt
can be triggered. The hardware diagram of Timer16 is shown as Fig.9. The interrupt source of Timer16 comes
from one of bit 8 to 15 of 16-bit counter, and the interrupt type can be rising edge trigger or falling edge trigger
which is specified in the bit 5 of integs register (IO address 0x0C).
stt16 command
t16m[7:5]
DATA Memory
t16m[4:3]
ldt16 command
CLK
IHRC
EOSC
ILRC
PA0↓
PA4
M
U
X
Prescalar
÷
1, 4,
16, 64
16-bit
up
counter
Bit[15:0]
Bit[15:8]
Data Bus
M
U
X
or
To set
interrupt
request flag
t16m[2:0]
integs.4
Fig.9: Hardware diagram of Timer16
When using the Timer16, the syntax for Timer16 has been defined in the .INC file. There are three parameters
st
to define the Timer16; 1 parameter is used to define the clock source of Timer16, 2
nd
parameter is used to
define the pre-scalar and the last one is to define the interrupt source. The detail description is shown as
below:
T16M
IO_RW
0x06
st
$ 7~5: STOP, SYSCLK, X, PA4_F, IHRC, EOSC, ILRC, PA0_F
// 1 par.
$ 4~3: /1, /4, /16, /64
// 2 par.
$ 2~0: BIT8, BIT9, BIT10, BIT11, BIT12, BIT13, BIT14, BIT15
// 3 par.
© Copyright 2017, PADAUK Technology Co. Ltd
nd
Page 41 of 95
rd
PDK-DS-PMS132-EN_V002 – Nov. 23, 2017
PMS132
12-bit ADC Enhanced Controller
User can define the parameters of T16M based on system requirement, some examples are shown below and
more examples please refer to “Help Application Note IC Introduction Register Introduction T16M” in
IDE utility.
$ T16M SYSCLK, /64, BIT15;
// choose (SYSCLK/64) as clock source, every 2^16 clock to set INTRQ.2=1
// if using System Clock = IHRC / 2 = 8 MHz
// SYSCLK/64 = 8 MHz/64 = 125KHz, about every 512 mS to generate INTRQ.2=1
$ T16M EOSC, /1, BIT13;
// choose (EOSC/1) as clock source, every 2^14 clocks to generate INTRQ.2=1
// if EOSC=32768 Hz, 32768 Hz/(2^14) = 2Hz, every 0.5S to generate INTRQ.2=1
$ T16M PA0_F, /1, BIT8;
// choose PA0 as clock source, every 2^9 to generate INTRQ.2=1
// receiving every 512 times PA0 to generate INTRQ.2=1
$ T16M STOP;
// stop Timer16 counting
If Timer16 is operated at free running, the frequency of interrupt can be described as below:
FINTRQ_T16M = Fclock source ÷ P ÷ 2n+1
Where, F is the frequency of selected clock source to Timer16;
P is the selection of t16m [4:3]; (1, 4, 16, 64)
th
N is the n bit selected to request interrupt service, for example: n=10 if bit 10 is selected.
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12-bit ADC Enhanced Controller
5.7 8-bit Timer (Timer2/Timer3) with PWM generation
Two 8-bit hardware timers (Timer2 and Timer3) with PWM generation are implemented in the PMS132. The
following descriptions thereinafter are for Timer2 only. It is because Timer3 have same structure with Timer2.
Please refer to Fig.10 shown the hardware diagram of Timer2, the clock sources of Timer2 may come from
system clock, internal high RC oscillator (IHRC), internal low RC oscillator (ILRC), external crystal oscillator
(EOSC), PA0, PB0,PA4 and comparator. Bit [7:4] of register tm2c are used to select the clock of Timer2. If
IHRC is selected for Timer2 clock source, the clock sent to Timer2 will keep running when using ICE in halt
state. The output of Timer2 can be sent to pin PB2, PA3 or PB4, depending on bit [3:2] of tm2c register. A clock
pre-scaling module is provided with divided-by- 1, 4, 16, and 64 options, controlled by bit [6:5] of tm2s register;
one scaling module with divided-by-1~31 is also provided and controlled by bit [4:0] of tm2s register. In
conjunction of pre-scaling function and scaling function, the frequency of Timer2 clock (TM2_CLK) can be wide
range and flexible.
The Timer2 counter performs 8-bit up-counting operation only; the counter values can be set or read back by
tm2ct register. The 8-bit counter will be clear to zero automatically when its values reach for upper bound
register, the upper bound register is used to define the period of timer or duty of PWM. There are two operating
modes for Timer2: period mode and PWM mode; period mode is used to generate periodical output waveform
or interrupt event; PWM mode is used to generate PWM output waveform with optional 6-bit or 8-bit PWM
resolution, Fig.11 shows the timing diagram of Timer2 for both period mode and PWM mode.
Fig.10: Timer2 hardware diagram
The output of Timer3 can be sent to pin PB5, PB6 or PB7.
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12-bit ADC Enhanced Controller
Time out and
Interrupt request
Time out and
Interrupt request
Time out and
Interrupt request
Counter
Counter
Counter
0xFF
0xFF
0x3F
bound
bound
Time
Event Trigger
Output-pin
bound
Event Trigger
Time
Output-pin
Time
Output-pin
Time
Time
Mode 0 – Period Mode
Event Trigger
Mode 1 – 8-bit PWM Mode
Time
Mode 1 – 6-bit PWM Mode
Fig.11: Timing diagram of Timer2 in period mode and PWM mode (tm2c.1=1)
5.7.1 Using the Timer2 to generate periodical waveform
If periodical mode is selected, the duty cycle of output is always 50%; its frequency can be summarized as
below:
Frequency of Output = Y ÷ [2 × (K+1) × S1 × (S2+1) ]
Where,
Y = tm2c[7:4] : frequency of selected clock source
K = tm2b[7:0] : bound register in decimal
S1 = tm2s[6:5] : pre-scalar (1, 4, 16, 64)
S2 = tm2s[4:0] : scalar register in decimal (1 ~ 31)
Example 1:
tm2c = 0b0001_1000, Y=8MHz
tm2b = 0b0111_1111, K=127
tm2s = 0b0000_00000, S1=1, S2=0
frequency of output = 8MHz ÷
[ 2 × (127＋1) × 1 × (0＋1) ] = 31.25KHz
Example 2:
tm2c = 0b0001_1000, Y=8MHz
tm2b = 0b0111_1111, K=127
tm2s[7:0] = 0b0111_11111, S1=64 , S2 = 31
frequency = 8MHz ÷ ( 2 × (127＋1) × 64 × (31＋1) ) =15.25Hz
Example 3:
tm2c = 0b0001_1000, Y=8MHz
tm2b = 0b0000_1111, K=15
tm2s = 0b0000_00000, S1=1, S2=0
frequency = 8MHz ÷ ( 2 × (15＋1) × 1 × (0＋1) ) = 250KHz
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Example 4:
tm2c = 0b0001_1000, Y=8MHz
tm2b = 0b0000_0001, K=1
tm2s = 0b0000_00000, S1=1, S2=0
frequency = 8MHz ÷ ( 2 × (1＋1) × 1 × (0＋1) ) =2MHz
The sample program for using the Timer2 to generate periodical waveform from PA3 is shown as below:
Void
FPPA0 (void)
{
. ADJUST_IC
SYSCLK=IHRC/2, IHRC=16MHz, VDD=5V
…
tm2ct = 0x0;
tm2b = 0x7f;
tm2s = 0b0_00_00001;
//
8-bit PWM, pre-scalar = 1, scalar = 2
tm2c = 0b0001_10_0_0;
//
system clock, output=PA3, period mode
while(1)
{
nop;
}
}
5.7.2
Using the Timer2 to generate 8-bit PWM waveform
If 8-bit PWM mode is selected, it should set tm2c[1]=1 and tm2s[7]=0, the frequency and duty cycle of
output waveform can be summarized as below:
Frequency of Output = Y ÷ [256 × S1 × (S2+1) ]
Duty of Output = ( K＋1 ) ÷ 256
Where,
Y = tm2c[7:4] : frequency of selected clock source
K = tm2b[7:0] : bound register in decimal
S1= tm2s[6:5] : pre-scalar (1, 4, 16, 64)
S2 = tm2s[4:0] : scalar register in decimal (1 ~ 31)
Example 1:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0111_1111, K=127
tm2s = 0b0000_00000, S1=1, S2=0
frequency of output = 8MHz ÷ ( 256 × 1 × (0+1) ) = 31.25KHz
duty of output = [(127+1) ÷ 256] × 100% = 50%
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Example 2:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0111_1111, K=127
tm2s = 0b0111_11111, S1=64, S2=31
frequency of output = 8MHz ÷ ( 256 × 64 × (31+1) ) = 15.25Hz
duty of output = [(127+1) ÷ 256] × 100% = 50%
Example 3:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b1111_1111, K=255
tm2s = 0b0000_00000, S1=1, S2=0
PWM output keep high
duty of output = [(255+1) ÷ 256] × 100% = 100%
Example 4:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0000_1001, K = 9
tm2s = 0b0000_00000, S1=1, S2=0
frequency of output = 8MHz ÷ ( 256 × 1 × (0+1) ) = 31.25KHz
duty of output = [(9+1) ÷ 256] × 100% = 3.9%
The sample program for using the Timer2 to generate PWM waveform from PA3 is shown as below:
void
FPPA0 (void)
{
.ADJUST_IC
SYSCLK=IHRC/2, IHRC=16MHz, VDD=5V
wdreset;
tm2ct = 0x0;
tm2b = 0x7f;
tm2s = 0b0_00_00001;
//
8-bit PWM, pre-scalar = 1, scalar = 2
tm2c = 0b0001_10_1_0;
//
system clock, output=PA3, PWM mode
while(1)
{
nop;
}
}
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12-bit ADC Enhanced Controller
5.7.3
Using the Timer2 to generate 6-bit PWM waveform
If 6-bit PWM mode is selected, it should set tm2c[1]=1 and tm2s[7]=1, the frequency and duty cycle of
output waveform can be summarized as below:
Frequency of Output = Y ÷ [64 × S1 × (S2+1) ]
Duty of Output = [( K＋1 ) ÷ 64] × 100%
Where, tm2c[7:4] = Y : frequency of selected clock source
tm2b[7:0] = K : bound register in decimal
tm2s[6:5] = S1 : pre-scalar (1, 4, 16, 64)
tm2s[4:0] = S2 : scalar register in decimal (1 ~ 31)
Example 1:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0001_1111, K=31
tm2s = 0b1000_00000, S1=1, S2=0
frequency of output = 8MHz ÷ ( 64 × 1 × (0+1) ) = 125KHz
duty = [(31+1) ÷ 64] × 100% = 50%
Example 2:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0001_1111, K=31
tm2s = 0b1111_11111, S1=64, S2=31
frequency of output = 8MHz ÷ ( 64 × 64 × (31+1) ) = 61.03 Hz
duty of output = [(31+1) ÷ 64] × 100% = 50%
Example 3:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0011_1111, K=63
tm2s = 0b1000_00000, S1=1, S2=0
PWM output keep high
duty of output = [(63+1) ÷ 64] × 100% = 100%
Example 4:
tm2c = 0b0001_1010, Y=8MHz
tm2b = 0b0000_0000, K=0
tm2s = 0b1000_00000, S1=1, S2=0
frequency = 8MHz ÷ ( 64 × 1 × (0+1) ) = 125KHz
duty = [(0+1) ÷ 64] × 100% =1.5%
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12-bit ADC Enhanced Controller
5.8 11-bit PWM Generator
Three 11-bit hardware PWM generators (PWMG0, PWMG1 & PWMG2) are implemented in the PMS132. The
following descriptions thereinafter are for PWMG0 only. It is because PWMG1 & PWMG2 have the same
structures and functions with PWMG0.
Their individual outputs are listed as below:
PWMG0 – PA0, PB4, PB5
PWMG1 – PA4, PB6, PB7
PWMG2 – PA3, PB2, PB3, PA5 (Only PA5 open drain output, and ICE does not support.)
5.8.1
PWM Waveform
A PWM output waveform (Fig.12) has a time-base (TPeriod = Time of Period) and a time with output high level
(Duty Cycle). The frequency of the PWM output is the inverse of the period (f PWM = 1/TPeriod), the resolution of the
N
PWM is the clock count numbers for one period (N bits resolution, 2 × Tclock = TPeriod).
Period
Duty Cycle
clock
‧‧‧‧‧‧‧
N bit resolution
Fig.12: PWM Output Waveform
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5.8.2
Hardware and Timing Diagram
Three 11-bit hardware PWM generators are built inside the PMS132; Fig.13 shows the hardware diagram
PWMG0 as an example. The clock source can be IHRC or system clock and output pin can be selected via
pwmc register selection. The period of PWM waveform is defined in the PWM upper bond high and low registers,
the duty cycle of PWM waveform is defined in the PWM duty high and low registers.
Fig.13: Hardware Diagram of 11-bit PWM Generator
0x7FF
Counter_Bound[10:0]
11 bit
Counter
Duty[10:0]
Time
Time
Output
Output Timing Diagram for 11- bit PWM generation
-
Fig.14: Output Timing Diagram of 11-bit PWM Generator
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12-bit ADC Enhanced Controller
5.8.3
Equations for 11-bit PWM Generator
If FIHRC is the frequency of IHRC oscillator and IHRC is the chosen clock source for 11-bit PWM generator,
the PWM frequency and duty cycle in time will be:
Frequency of PWM Output = FIHRC ÷ [P × K × CB ]
Duty Cycle of PWM Output (in time) = (1/FIHRC) * [ DB ÷ CB]
Where,
pwms[6:5] = P ; pre-scalar
pwms[4:0] =
K ; scalar
Duty_Bound[10:0] = {pwmdth[7:0],pwmdtl[7:5]} = DB; duty bound
Counter_Bount[10:0] = {pwmcubh[7:0], pwmcubl[7:5]} =
5.9
CB; counter bount
WatchDog Timer
The watchdog timer (WDT) is a counter with clock coming from ILRC. WDT can be cleared by power-on-reset
or by command wdreset at any time.
There are four different timeout periods of watchdog timer to be chosen
by setting the misc register, it is:
8k ILRC clocks period if register misc[1:0]=00 (default)
16k ILRC clocks period if register misc[1:0]=01
64k ILRC clocks period if register misc[1:0]=10
256k ILRC clocks period if register misc[1:0]=11
The frequency of ILRC may drift a lot due to the variation of manufacture, supply voltage and temperature; user
should reserve guard band for save operation. Besides, the watchdog period will also be shorter than expected
after Reset or Wakeup events. It is suggested to clear WDT by wdreset command after these events to ensure
enough clock periods before WDT timeout.
When WDT is timeout, PMS132 will be reset to restart the program execution. The relative timing diagram of
watchdog timer is shown as Fig.15.
VDD
tSBP
WD
Time Out
Program
Execution
Watch Dog Time Out Sequence
Fig.15: Sequence of Watch Dog Time Out
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5.10 Interrupt
There are eight interrupt lines for PMS132:
External interrupt PA0/PB5
External interrupt PB0/PA4
ADC interrupt
Timer16 interrupt
GPC interrupt
PWMG0 interrupt
Timer2 interrupt
Timer3 interrupt
Every interrupt request line has its own corresponding interrupt control bit to enable or disable it; the hardware
diagram of interrupt function is shown as Fig.16. All the interrupt request flags are set by hardware and cleared
by writing intrq register. When the request flags are set, it can be rising edge, falling edge or both, depending
on the setting of register integs. All the interrupt request lines are also controlled by engint instruction (enable
global interrupt) to enable interrupt operation and disgint instruction (disable global interrupt) to disable it.
The stack memory for interrupt is shared with data memory and its address is specified by stack register sp.
Since the program counter is 16 bits width, the bit 0 of stack register sp should be kept 0. Moreover, user can
use pushaf / popaf instructions to store or restore the values of ACC and flag register to / from stack memory.
Since the stack memory is shared with data memory, user should manipulate the memory using carefully. By
adjusting the memory location of stack point, the depth of stack pointer for every CPU could be fully specified
by user to achieve maximum flexibility of system.
Fig.16: Hardware diagram of interrupt controller
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Once the interrupt occurs, its operation will be:
The program counter will be stored automatically to the stack memory specified by register sp.
New sp will be updated to sp+2.
Global interrupt will be disabled automatically.
The next instruction will be fetched from address 0x010.
During the interrupt service routine, the interrupt source can be determined by reading the intrq register.
After finishing the interrupt service routine and issuing the reti instruction to return back, its operation will be:
The program counter will be restored automatically from the stack memory specified by register sp.
New sp will be updated to sp-2.
Global interrupt will be enabled automatically.
The next instruction will be the original one before interrupt.
User must reserve enough stack memory for interrupt, two bytes stack memory for one level interrupt and four
bytes for two levels interrupt. For interrupt operation, the following sample program shows how to handle the
interrupt, noticing that it needs four bytes stack memory to handle interrupt and pushaf.
void
FPPA0
(void)
{
...
$
INTEN
INTRQ
=
PA0;
// INTEN =1; interrupt request when PA0 level changed
0;
// clear INTRQ
ENGINT
// global interrupt enable
...
DISGINT
// global interrupt disable
...
}
void
Interrupt
(void)
//
interrupt service routine
{
PUSHAF
If
//
store ALU and FLAG register
//
Here for PA0 interrupt service routine
(INTRQ.0)
{
INTRQ.0
=
0;
...
}
...
POPAF
//
restore ALU and FLAG register
}
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12-bit ADC Enhanced Controller
5.11 Power-Save and Power-Down
There are three operational modes defined by hardware: ON mode, Power-Save mode and Power-Down
modes. ON mode is the state of normal operation with all functions ON, Power-Save mode (“stopexe”) is the
state to reduce operating current and CPU keeps ready to continue, Power-Down mode (“stopsys”) is used to
save power deeply. Therefore, Power-Save mode is used in the system which needs low operating power with
wake-up occasionally and Power-Down mode is used in the system which needs power down deeply with
seldom wake-up. Fig.17 shows the differences in oscillator modules between Power-Save mode (“stopexe”)
and Power-Down mode (“stopsys”).
Differences in oscillator modules between STOPSYS and STOPEXE
IHRC
ILRC
EOSC
STOPSYS
Stop
Stop
Stop
STOPEXE
No Change
No Change
No Change
Fig.17: Differences in oscillator modules between STOPSYS and STOPEXE
5.11.1
Power-Save mode (“stopexe”)
Using “stopexe” instruction to enter the Power-Save mode, only system clock is disabled, remaining all the
oscillator modules active. For CPU, it stops executing; however, for Timer16, counter keep counting if its clock
source is not the system clock. Wake-up from input pins can be considered as a continuation of normal
execution, the detail information for Power-Save mode shows below:
IHRC, ILRC and EOSC oscillator modules: No change, keep active if it was enabled
System clock: Disable, therefore, CPU stops execution
OTP memory is turned off
Timer16: Stop counting if system clock is selected or the corresponding oscillator module is disabled;
otherwise, it keeps counting.
Wake-up sources: IO toggle or Timer16.
An example shows how to use Timer16 to wake-up from “stopexe”:
$ T16M
…
WORD
STT16
stopexe;
ILRC, /1, BIT8
count =
count;
// Timer16 setting
0;
…
The initial counting value of Timer16 is zero and the system will be woken up after the Timer16 counts 256
ILRC clocks.
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5.11.2 Power-Down mode (“stopsys”)
Power-Down mode is the state of deeply power-saving with turning off all the oscillator modules. By using the
“stopsys” instruction, this chip will be put on Power-Down mode directly. The following shows the internal status
of PMS132 detail when “stopsys” command is issued:
All the oscillator modules are turned off
OTP memory is turned off
The contents of SRAM and registers remain unchanged
Wake-up sources: ANY IO toggle.
If PA or PB is input mode and set to analog input by padier or pbdier register, it can NOT be used to
wake-up the system.
Wake-up from input pins can be considered as a continuation of normal execution. To minimize power
consumption, all the I/O pins should be carefully manipulated before entering power-down mode. The
reference sample program for power down is shown as below:
CLKMD
=
0xF4;
//
Change clock from IHRC to ILRC
CLKMD.4
=
0;
//
disable IHRC
STOPSYS;
//
enter power-down
if
//
if wakeup happen and check OK, then return to high speed
//
else stay in power-down mode again
//
Change clock from ILRC to IHRC/2
…
while (1)
{
(…)
break;
}
CLKMD =
5.11.3
0x34;
Wake-up
After entering the Power-Down or Power-Save modes, the PMS132 can be resumed to normal operation by
toggling IO pins, Timer16 interrupt is available for Power-Save mode ONLY. Fig.18 shows the differences in
wake-up sources between STOPSYS and STOPEXE.
Differences in wake-up sources between STOPSYS and STOPEXE
IO Toggle
T16 Interrupt
STOPSYS
Yes
No
STOPEXE
Yes
Yes
Fig.18: Differences in wake-up sources between Power-Save mode and Power-Down mode
When using the IO pins to wake-up the PMS132, registers padier should be properly set to enable the wake-up
function for every corresponding pin. The time for normal wake-up is about 3000 ILRC clocks counting from
wake-up event; fast wake-up can be selected to reduce the wake-up time by misc register, and the time for fast
wake-up is about 45 ILRC clocks from IO toggling.
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Suspend mode
Wake-up mode
STOPEXE suspend
or
Fast wake-up
STOPSYS suspend
STOPEXE suspend
or
Normal wake-up
Wake-up time (tWUP) from IO toggle
45 * TILRC,
Where TILRC is the time period of ILRC
3000 * TILRC,
Where TILRC is the clock period of ILRC
STOPSYS suspend
Please notice that when Fast boot-up is selected, no matter which wake-up mode is selected in misc.5, the
wake-up mode will be forced to be FAST. If Normal boot-up is selected, the wake-up mode is determined by
misc.5.
5.12 IO Pins
All the pins can be independently set into two states output or input by configuring the data registers (pa, pb),
control registers (pac, pbc) and pull-high registers (paph, pbph). All these pins have Schmitt-trigger input
buffer and output driver with CMOS level. When it is set to output low, the pull-up resistor is turned off
automatically. If user wants to read the pin state, please notice that it should be set to input mode before
reading the data port; if user reads the data port when it is set to output mode, the reading data comes from
data register, NOT from IO pad. As an example, Table 5 shows the configuration table of bit 0 of port A. The
hardware diagram of IO buffer is also shown as Fig.19.
pa.0
pac.0 paph.0
X
X
0
1
1
0
0
1
1
1
0
1
X
0
1
Description
Input without pull-up resistor
Input with pull-up resistor
Output low without pull-up resistor
Output high without pull-up resistor
Output high with pull-up resistor
Table 5: PA0 Configuration Table
RD pull-high latch
D
WR pull-high latch
Q
(weak P --MOS)
pull-high
latch
D
Q
Q1
Data
latch
WR data latch
PAD
RD control latch
D
WR control latch
Q
Control
M
latch
U
X
RD Port
Data Bus
padier.x or pbdier.x
Wakeup module
Interrupt module
(PA0,PB5,PB0,PA4)
Analog Module
Fig.19: Hardware diagram of IO buffer
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Other than PA5, all the IO pins have the same structure; PA5 can be open-drain ONLY when setting to output
mode (without Q1). The corresponding bits in registers padier / pbdier should be set to low to prevent leakage
current for those pins are selected to be analog function. When PMS132 is put in power-down or power-save
mode, every pin can be used to wake-up system by toggling its state. Therefore, those pins needed to
wake-up system must be set to input mode and set the corresponding bits of registers padier and pbdier to
high. The same reason, padier.0 should be set high when PA0 is used as external interrupt pin, pbdier.0 for
PB0, padier.4 for PA4 and pbdier.5 for PB5.
5.13 Reset and LVR
5.13.1 Reset
There are many causes to reset the PMS132, once reset is asserted, most of all the registers in PMS132
will be set to default values, system should be restarted once abnormal cases happen, or by jumping
program counter to address 0x0. The data memory is in uncertain state when reset comes from power-up
and LVR; however, the content will be kept when reset comes from PRSTB pin or WDT timeout.
5.13.2 LVR reset
By code option, there are 8 different levels of LVR for reset: 4.0V, 3.5V, 3.0V, 2.75V, 2.5V, 2.2V, 2.0V and
1.8V; usually, user selects LVR reset level to be in conjunction with operating frequency and supply voltage.
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5.14 Analog-to-Digital Conversion (ADC) module
Fig.20: ADC Block Diagram
There are seven registers when using the ADC module, which are:
ADC Control Register (adcc)
ADC Regulator Control Register (adcrgc)
ADC Mode Register (adcm)
ADC Result High/Low Register (adcrh, adcrl)
Port A/B Digital Input Enable Register (padier, pbdier)
The following steps are required to do the AD conversion procedure:
(1) Configure the voltage reference high by adcrgc register
(2) Configure the AD conversion clock by adcm register
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(3) Configure the pin as analog input by padier, pbdier register
(4) Select the ADC input channel by adcc register
(5) Enable the ADC module by adcc register
(6) Delay a certain amount of time after enabling the ADC module
Condition 1: using the internal voltage reference high which are 2V, 3V, 4V or the input channel is bandgap
It must delay more than 1 ms when the time of 200 AD clocks is less than 1ms. Or it must delay
200 AD clocks when the time of 200 AD clocks is larger than 1ms
Condition 2: without using any internal 2V, 3V, 4V, bandgap voltage
It needs to delay 200 AD clocks only.
(7) Execute the AD conversion and check if ADC data is ready
set ‘1’ to addc.6 to start the conversion and check whether addc.6 is ‘1’
(8) Read the ADC result registers:
First read the adcrh register and then read the adcrl register.
If user power down the ADC and enable the ADC again, be sure to go to step 6 to confirm the ADC becomes
ready before the conversion.
5.14.1 The input requirement for AD conversion
For the AD conversion to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed
to fully charge to the voltage reference high level and discharge to the voltage reference low level. The
analog input model is shown as Fig.21, the signal driving source impedance (Rs) and the internal sampling
switch impedance (Rss) will affect the required time to charge the capacitor C HOLD directly. The internal
sampling switch impedance may vary with ADC supply voltage; the signal driving source impedance will
affect accuracy of analog input signal.
User must ensure the measured signal is stable before sampling;
therefore, the maximum signal driving source impedance is highly dependent on the frequency of signal to
be measured. The recommended maximum impedance for analog driving source is about 10KΩ under
500KHz input frequency.
VDD
Rs
Sampling
Switch
VT = 0.6V
ANx
RIC _
< 1k
SS
Rss
CHOLD
VA
CPIN
5 pF
VT = 0.6V
= DAC capacitance
= 5.1 pF
I leakage
± 50 nA
VSS
Legend CPIN
VT
I leakage
RIC
SS
CHOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to various junctions
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
Fig.21: Analog Input Model
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Before starting the AD conversion, the minimum signal acquisition time should be met for the selected
analog input signal, the selection of ADCLK must be met the minimum signal acquisition time.
5.14.2 Select the reference high voltage
The ADC reference high voltage can be selected via bit[7:5] of register adcrgc and its option can be VDD,
4V, 3V, 2V, band-gap (1.20V) reference voltage or PB1 from external pin.
5.14.3 ADC clock selection
The clock of ADC module (ADCLK) can be selected by adcm register; there are 8 possible options for
ADCLK from CLK÷1 to CLK÷128 (CLK is the system clock). Due to the signal acquisition time TACQ is one
clock period of ADCLK, the ADCLK must meet that requirement. The recommended ADC clock is to
operate at 2us.
5.14.4 Configure the analog pins
There are 12 analog signals can be selected for AD conversion, 11 analog input signals come from
external pins and one is from internal band-gap reference voltage or 0.25*VDD. There are 4 voltage levels
selectable for the internal band-gap reference, they are 1.2V, 2V, 3V and 4V. For external pins, the analog
signals are shared with Port A[0], Port A[3], Port A[4], and Port B[7:0]. To avoid leakage current at the
digital circuit, those pins defined for analog input should disable the digital input function (set the
corresponding bit of padier or pbdier register to be 0).
The measurement signals of ADC belong to small signal; it should avoid the measured signal to be
interfered during the measurement period, the selected pin should (1) be set to input mode (2) turn off
weak pull-high resistor (3) set the corresponding pin to analog input by port A/B digital input disable register
(padier / pbdier).
5.14.5 Using the ADC
The following example shows how to use ADC with PB0~PB3.
First, defining the selected pins:
PBC
PBPH
PBDIER
=
=
=
0B_XXXX_0000;
0B_XXXX_0000;
0B_XXXX_0000;
//
//
//
PB0 ~ PB3 as Input
PB0 ~ PB3 without pull-high
PB0 ~ PB3 digital input is disabled
//
//
//
set PB3 as ADC input
set PB2 as ADC input
set PB0 as ADC input
//
//
recommend /16 @System Clock=8MHz
recommend /8 @System Clock=4MHz
Next, setting ADCC register, example as below:
$
$
$
ADCC Enable, PB3;
ADCC Enable, PB2;
ADCC Enable, PB0;
Next, setting ADCM register, example as below:
$
$
ADCM 12BIT, /16;
ADCM 12BIT, /8;
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Next, delay 400us, example as below:
.Delay 8*2*200;
.Delay 4*2*200;
//
//
System Clock=8MHz
System Clock=4MHz
Then, start the ADC conversion:
AD_START =
1;
while (! AD_DONE) NULL;
//
//
start ADC conversion
wait ADC conversion result
Finally, it can read ADC result when AD_DONE is high:
WORD
Data$1
Data$0
Data
Data;
ADCRH
ADCRL;
Data >> 4;
=
=
=
//
two bytes result: ADCRH and ADCRL
The ADC can be disabled by using the following method:
$
ADCC Disable;
or
ADCC
=
0;
5.15 Multiplier
There is an 8x8 multiplier on-chip to enhance hardware capability in arithmetic function, its multiplication is an
8 x8 unsigned operation and can be finished in one clock cycle. Before issuing the mul command, both
multiplicand and multiplicator must be put on ACC and register mulop (0x08); After mul command, the high
byte result will be put on register mulrh (0x09) and low byte result on ACC. The hardware diagram of this
multiplier is shown as Fig.22.
8-bit
8-bit
ACC
mulop (0x08)
mulrh
Bit[15~8]
ACC
Bit[7~0]
Fig.22: Block diagram of hardware multiplier
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6. IO Registers
6.1. ACC Status Flag Register (flag), IO address = 0x00
Bit
Reset
R/W
7-4
-
-
3
0
R/W
Description
Reserved. Please do not use.
OV (Overflow Flag). This bit is set to be 1 whenever the sign operation is overflow.
AC (Auxiliary Carry Flag). There are two conditions to set this bit, the first one is carry out
2
0
R/W
of low nibble in addition operation and the other one is borrow from the high nibble into low
nibble in subtraction operation.
C (Carry Flag). There are two conditions to set this bit, the first one is carry out in addition
1
0
R/W
operation, and the other one is borrow in subtraction operation. Carry is also affected by
shift with carry instruction.
0
0
R/W
Z (Zero Flag). This bit will be set when the result of arithmetic or logic operation is zero;
Otherwise, it is cleared.
6.2. Stack Pointer Register (sp), IO address = 0x02
Bit
Reset
R/W
7-0
-
R/W
Description
Stack Pointer Register. Read out the current stack pointer, or write to change the stack
pointer.
6.3. Clock Mode Register (clkmd), IO address = 0x03
Bit
Reset
R/W
Description
System clock (CLK) selection:
Type 0, clkmd[3]=0
7-5
111
R/W
Type 1, clkmd[3]=1
000: IHRC÷4
000: IHRC÷16
001: IHRC÷2
001: IHRC÷8
010: IHRC
010: ILRC÷16 (ICE does NOT Support.)
011: EOSC÷4
011: IHRC÷32
100: EOSC÷2
100: IHRC÷64
101: EOSC
101: EOSC÷8
110: ILRC÷4
111: ILRC (default)
11x: reserved.
4
1
R/W
Internal High RC Enable. 0 / 1: disable / enable
3
0
R/W
2
1
R/W
1
1
R/W
Watch Dog Enable. 0 / 1: disable / enable
0
0
R/W
Pin PA5/PRSTB function. 0 / 1: PA5 / PRSTB
Clock Type Select. This bit is used to select the clock type in bit [7:5].
0 / 1: Type 0 / Type 1
Internal Low RC Enable. 0 / 1: disable / enable
If ILRC is disabled, watchdog timer is also disabled.
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6.4. Interrupt Enable Register (inten), IO address = 0x04
Bit
Reset
R/W
Description
7
0
R/W
Enable interrupt from Timer3. 0 / 1: disable / enable.
6
0
R/W
Enable interrupt from Timer2. 0 / 1: disable / enable.
5
0
R/W
Enable interrupt from PWMG0. 0 / 1: disable / enable.
4
0
R/W
Enable interrupt from comparator. 0 / 1: disable / enable.
3
0
R/W
Enable interrupt from ADC. 0 / 1: disable / enable.
2
0
R/W
Enable interrupt from Timer16 overflow. 0 / 1: disable / enable.
1
0
R/W
Enable interrupt from PB0/PA4. 0 / 1: disable / enable.
0
0
R/W
Enable interrupt from PA0/PB5. 0 / 1: disable / enable.
6.5. Interrupt Request Register (intrq), IO address = 0x05
Bit
Reset
R/W
7
-
R/W
6
-
R/W
5
-
R/W
4
-
R/W
3
-
R/W
2
-
R/W
1
-
R/W
0
-
R/W
Description
Interrupt Request from Timer3, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
Interrupt Request from Timer2, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
Interrupt Request from PWMG0, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
Interrupt Request from comparator, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
Interrupt Request from ADC, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
Interrupt Request from Timer16, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
Interrupt Request from pin PB0/PA4, this bit is set by hardware and cleared by software.
0 / 1: No request / Request
Interrupt Request from pin PA0/PB5, this bit is set by hardware and cleared by software.
0 / 1: No Request / request
6.6. Multiplier Operand Register (mulop), IO address = 0x08
Bit
Reset
R/W
7-0
-
R/W
Description
Operand for hardware multiplication operation.
6.7. Multiplier Result High Byte Register (mulrh), IO address = 0x09
Bit
Reset
R/W
7-0
-
RO
Description
High byte result of multiplication operation (read only).
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6.8. Timer16 mode Register (t16m), IO address = 0x06
Bit
Reset
R/W
Description
Timer16 Clock source selection.
000: disable
001: CLK (system clock)
010: reserved
7-5
000
R/W
011: PA4 falling edge (from external pin)
100: IHRC
101: EOSC
110: ILRC
111: PA0 falling edge (from external pin)
Timer16 clock pre-divider.
00: ÷1
4-3
00
R/W
01: ÷4
10: ÷16
11: ÷64
Interrupt source selection. Interrupt event happens when the selected bit status is changed.
0 : bit 8 of Timer16
1 : bit 9 of Timer16
2 : bit 10 of Timer16
2-0
000
R/W
3 : bit 11 of Timer16
4 : bit 12 of Timer16
5 : bit 13 of Timer16
6 : bit 14 of Timer16
7 : bit 15 of Timer16
6.9. External Oscillator setting Register (eoscr), IO address = 0x0a
Bit
Reset
R/W
7
0
WO
Description
Enable external crystal oscillator.
0 / 1 : Disable / Enable
External crystal oscillator selection.
00 : reserved
6-5
00
WO
01 : Low driving capability, for lower frequency, ex: 32KHz crystal oscillator (reserved)
10 : Middle driving capability, for middle frequency, ex: 1MHz crystal oscillator
11 : High driving capability, for higher frequency, ex: 4MHz crystal oscillator
4-1
-
-
0
0
WO
Reserved. Please keep 0 for future compatibility.
Power-down the Band-gap and LVR hardware modules. 0 / 1: normal / power-down.
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6.10.Interrupt Edge Select Register (integs), IO address = 0x0c
Bit
Reset
R/W
7-5
-
-
Description
Reserved.
Timer16 edge selection.
4
0
WO
0 : rising edge of the selected bit to trigger interrupt
1 : falling edge of the selected bit to trigger interrupt
PB0/PA4 edge selection.
00 : both rising edge and falling edge of the selected bit to trigger interrupt
3-2
00
WO
01 : rising edge of the selected bit to trigger interrupt
10 : falling edge of the selected bit to trigger interrupt
11
reserved.
PA0/PB5 edge selection.
00 : both rising edge and falling edge of the selected bit to trigger interrupt
1-0
00
WO
01 : rising edge of the selected bit to trigger interrupt
10 : falling edge of the selected bit to trigger interrupt
11 : reserved.
6.11.Port A Digital Input Enable Register (padier), IO address = 0x0d
Bit
Reset
R/W
Description
Enable PA7 digital input and wake-up event. 1 / 0 : enable / disable.
This bit should be set to low to prevent leakage current when external crystal oscillator is
used. If this bit is set to low, PA7 can NOT be used to wake-up the system.
Enable PA6 digital input and wake-up event. 1 / 0 : enable / disable.
This bit should be set to low to prevent leakage current when external crystal oscillator is
used. If this bit is set to low, PA6 can NOT be used to wake-up the system.
Enable PA5 digital input and wake-up event. 1 / 0 : enable / disable.
This bit can be set to low to disable wake-up from PA5 toggling.
Enable PA4 digital input and wake-up event. 1 / 0 : enable / disable.
This bit should be set to low when PA4 is assigned as AD input to prevent leakage current.
If this bit is set to low, PA4 can NOT be used to wake-up the system.
Enable PA3 digital input and wake-up event. 1 / 0 : enable / disable.
This bit should be set to low when PA3 is assigned as AD input to prevent leakage current.
If this bit is set to low, PA3 can NOT be used to wake-up the system.
7
1
WO
6
1
WO
5
1
WO
4
1
WO
3
1
WO
2-1
1
WO
Reserved
0
1
WO
Enable PA0 digital input and wake-up event and interrupt request. 1 /0: enable / disable.
This bit can be set to low to prevent leakage current when PA0 is assigned as AD input,
and to disable wake-up from PA0 toggling and interrupt request from this pin.
6.12.Port B Digital Input Enable Register (pbdier), IO address = 0x0e
Bit
Reset
R/W
Description
Enable PB7~PB0 digital input to prevent leakage when the pin is assigned for AD input.
7-0
0xFF
WO
When disable is selected, the wakeup function from this pin is also disabled.
0 / 1 : disable / enable
.
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6.13. Port A Data Register (pa), IO address = 0x10
Bit
Reset
R/W
7-0
0x00
R/W
Description
Data register for Port A.
6.14. Port A Control Register (pac), IO address = 0x11
Bit
Reset
R/W
Description
Port A control registers. This register is used to define input mode or output mode for
7-0
0x00
R/W
each corresponding pin of port A.
0 / 1: input / output
Please note that PA5 can be INPUT or OUTPUT LOW ONLY, the output state will be
tri-state when PA5 is programmed into output mode with data 1.
6.15. Port A Pull-High Register (paph), IO address = 0x12
Bit
Reset
R/W
Description
Port A pull-high register. This register is used to enable the internal pull-high device on
7-0
0x00
R/W
each corresponding pin of port A and this pull high function is active only for input mode.
0 / 1 : disable / enable
6.16. Port B Data Register (pb), IO address = 0x14
Bit
Reset
R/W
7-0
0x00
R/W
Description
Data register for Port B.
6.17. Port B Control Register (pbc), IO address = 0x15
Bit
Reset
R/W
7-0
0x00
R/W
Description
Port B control register. This register is used to define input mode or output mode for each
corresponding pin of port B.
0 / 1: input / output
6.18. Port B Pull-High Register (pbph), IO address = 0x16
Bit
Reset
R/W
Description
Port B pull-high register. This register is used to enable the internal pull-high device on
7-0
0x00
R/W
each corresponding pin of port B and this pull high function is active only for input mode.
0 / 1 : disable / enable
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6.19. Miscellaneous Register (misc), IO address = 0x17
Bit
Reset
R/W
7-6
-
-
Description
Reserved. (keep 0 for future compatibility)
Enable fast Wake-up. Fast wake-up is NOT supported when EOSC is enabled.
0: Normal wake-up.
The wake-up time is 3000 ILRC clocks (Not for fast boot-up)
5
0
WO
1: Fast wake-up.
The wake-up time is 45 ILRC clocks + oscillator stable time.
If wake-up from STOPEXE suspend, there is no oscillator stable time;
If wake-up from STOPSYS suspend, it will be IHRC or ILRC stable time from power-on.
4-3
-
-
2
0
WO
1-0
00
WO
Reserved. (keep 0 for future compatibility)
Disable LVR function.
0 / 1 : Enable / Disable
Watch dog time out period.
00: 8k ILRC clock period
01: 16k ILRC clock period
10: 64k ILRC clock period
11: 256k ILRC clock period
6.20. Comparator Control Register (gpcc), IO address = 0x18
Bit
Reset
R/W
Description
Enable comparator.
7
0
R/W
0 / 1 : disable / enable
When this bit is set to enable, please also set the corresponding analog input pins to be
digital disable to prevent IO leakage.
Comparator result of comparator.
6
-
RO
0: plus input < minus input
1: plus input > minus input
Select whether the comparator result output will be sampled by TM2_CLK?
5
0
R/W
0: result output NOT sampled by TM2_CLK
1: result output sampled by TM2_CLK
Inverse the polarity of result output of comparator.
4
3-1
0
000
R/W
R/W
0: polarity is NOT inversed.
1: polarity is inversed.
Selection the minus input (-) of comparator.
000 : PA3
001 : PA4
010 : Internal 1.20 volt band-gap reference voltage
011 : Vinternal R
100 : PB6
101 : PB7
11X: reserved
Selection the plus input (+) of comparator.
0
0
R/W
0 : Vinternal R
1 : PA4
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6.21. Comparator Selection Register (gpcs), IO address = 0x19
Bit
Reset
R/W
Description
7
0
WO
6
0
-
5
0
WO
Selection of high range of comparator.
4
0
WO
Selection of low range of comparator.
3-0
0000
WO
Comparator output enable (to PA0).
0 / 1 : disable / enable
Reserved
Selection the voltage level of comparator.
0000 (lowest) ~ 1111 (highest)
6.22. Reset Status Register (rstst), IO address = 0x1b
Bit
Reset
R/W
Description
(POR only)
MCU had been reset by Watch-Dog time-out? This bit is set to high whenever reset
7
0
R/W
occurs from watch-dog time-out, and reset only when writing “0” to clear this bit or POR
(power-on-reset) happens. 0 / 1 : No / Yes..
MCU had been reset by invalid code? This bit is set to high whenever reset occurs from
6
0
R/W
invalid instruction code, and reset only when writing “0” to clear this bit or POR
(power-on-reset) happens. 0 / 1 : No / Yes..
5
0
-
Reserved. Please keep 0.
4
-
-
Reserved. Please keep 1.
MCU reset from external reset pin (PA5)? This bit is set to high whenever reset occurs
3
-
R/W
from PA5 pin, and reset only when writing “0” to clear this bit or POR (power-on-reset)
happens. 0 / 1 : No / Yes.
VDD had been lower than 4V? This bit is set to high whenever VDD under 4V and reset
2
-
R/W
only when writing “0” to clear this bit or POR (power-on-reset) happens.
0 / 1 : No / Yes.
VDD had been lower than 3V? This bit is set to high whenever VDD under 3V and reset
1
-
R/W
only when writing “0” to clear this bit or POR (power-on-reset) happens.
0 / 1 : No / Yes.
VDD had been lower than 2V? This bit is set to high whenever VDD under 2V and reset
0
-
R/W
only when writing “0” to clear this bit or POR (power-on-reset) happens.
0 / 1 : No / Yes.
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6.23. Timer2 Control Register (tm2c), IO address = 0x1c
Bit
Reset
R/W
Description
Timer2 clock selection.
0000 : disable
0001 : CLK (system clock)
0010 : IHRC
0011 : EOSC
0100 : ILRC
0101 : comparator output
7-4
0000
R/W
011x : reserved
1000 : PA0 (rising edge)
1001 : ~PA0 (falling edge)
1010 : PB0 (rising edge)
1011 : ~PB0 (falling edge)
1100 : PA4 (rising edge)
1101 : ~PA4 (falling edge)
Notice: In ICE mode and IHRC is selected for Timer2 clock, the clock sent to Timer2 does
NOT be stopped, Timer2 will keep counting when ICE is in halt state.
Timer2 output selection.
00 : disable
3-2
00
R/W
01 : PB2
10 : PA3
11 : PB4
1
0
R/W
0
0
R/W
Timer2 mode selection.
0 / 1 : period mode / PWM mode
Enable to inverse the polarity of Timer2 output.
0 / 1: disable / enable.
6.24. Timer2 Counter Register (tm2ct), IO address = 0x1d
Bit
Reset
R/W
7–0
0x00
R/W
Description
Bit [7:0] of Timer2 counter register.
6.25. Timer2 Scalar Register (tm2s), IO address = 0x1e
Bit
Reset
R/W
Description
PWM resolution selection.
7
0
WO
0 : 8-bit
1 : 6-bit
Timer2 clock pre-scalar.
00 : ÷ 1
6-5
00
WO
01 : ÷ 4
10 : ÷ 16
11 : ÷ 64
4-0
00000
WO
Timer2 clock scalar.
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6.26. Timer2 Bound Register (tm2b), IO address = 0x09
Bit
Reset
R/W
7-0
0x00
WO
Description
Timer2 bound register.
6.27. PWMG0 control Register (pwmg0c), IO address = 0x20
Bit
Reset
R/W
Description
7
0
WO
Enable PWMG0 generator. 0 / 1 : disable / enable.
6
-
RO
Output status of PWMG0 generator.
5
0
WO
Enable to inverse the polarity of PWMG0 generator output. 0 / 1 : disable / enable.
4
0
WO
PWMG0 counter reset.
Writing “1” to clear PWMG0 counter and this bit will be self clear to 0 after counter reset.
3-1
0
WO
Select PWM output pin for PWMG0.
000: none
001: PB5
011: PA0
100: PB4
Others: reserved
0
0
WO
Clock source of PWMG0 generator.
0 : SYSCLK
1 : IHRC or IHRC * 2 (by Code Option: PWM_Source)
6.28. PWMG0 Scalar Register (pwmg0s), IO address = 0x21
Bit
7
Reset
0
R/W
Description
WO
PWMG0 interrupt mode.
0: Generate interrupt when counter is 0.
1: Generate interrupt when counter matches the duty value
6-5
0
WO
PWMG0 clock pre-scalar.
00 : ÷1
01 : ÷4
10 : ÷16
11 : ÷64
4-0
0
WO
PWMG0 clock divider.
6.29. PWMG0 Counter Upper Bound High Register (pwmg0cubh), IO address = 0x24
Bit
Reset
R/W
7-0
-
WO
Description
Bit[10:3] of PWMG0 counter upper bound.
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6.30. PWMG0 Counter Upper Bound Low Register (pwmg0cubl), IO address = 0x25
Bit
Reset
R/W
7-5
-
WO
4-0
-
-
Description
Bit[2:0] of PWMG0 counter upper bound.
Reserved
6.31. PWMG0 Duty Value High Register (pwmg0dth), IO address = 0x22
Bit
Reset
R/W
7-0
-
WO
Description
Duty values bit[10:3] of PWMG0.
6.32. PWMG0 Duty Value Low Register (pwmg0dtl), IO address = 0x23
Bit
Reset
R/W
7-5
-
WO
4-0
-
-
Description
Duty values bit [2:0] of PWMG0.
Reserved
Note: It’s necessary to write PWMG0 Duty_Value Low Register before writing PWMG0 Duty_Value High Register.
6.33. Timer3 Control Register (tm3c), IO address = 0x32
Bit
Reset
R/W
7-4
0000
R/W
Description
Timer3 clock selection.
0000 : disable
0001 : CLK (system clock)
0010 : IHRC
0011 : EOSC
0100 : ILRC
0101 : comparator output
011x : reserved
1000 : PA0 (rising edge)
1001 : ~PA0 (falling edge)
1010 : PB0 (rising edge)
1011 : ~PB0 (falling edge)
1100 : PA4 (rising edge)
1101 : ~PA4 (falling edge)
Notice: In ICE mode and IHRC is selected for Timer3 clock, the clock sent to Timer3
does NOT be stopped, Timer3 will keep counting when ICE is in halt state.
Timer3 output selection.
00 : disable
3-2
00
R/W
01 : PB5
10 : PB6
11 : PB7
1
0
R/W
0
0
R/W
Timer3 mode selection.
0 / 1 : period mode / PWM mode
Enable to inverse the polarity of Timer3 output.
0 / 1: disable / enable
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12-bit ADC Enhanced Controller
6.34. Timer3 Counter Register (tm3ct), IO address = 0x33
Bit
Reset
R/W
7-0
0x00
R/W
Description
Bit [7:0] of Timer3 counter register.
6.35. Timer3 Scalar Register (tm3s), IO address = 0x34
Bit
Reset
R/W
Description
PWM resolution selection.
7
0
WO
0 : 8-bit
1 : 6-bit
Timer3 clock pre-scalar.
00 : ÷ 1
6-5
00
WO
01 : ÷ 4
10 : ÷ 16
11 : ÷ 64
4-0
00000
WO
Timer3 clock scalar.
6.36. Timer3 Bound Register (tm3b), IO address = 0x3f
Bit
Reset
R/W
7-0
0x00
WO
Description
Timer3 bound register.
6.37. ADC Control Register (adcc), IO address = 0x3b
Bit
Reset
R/W
7
0
R/W
6
0
R/W
Description
Enable ADC function. 0/1: Disable/Enable.
ADC process control bit.
Read “1” to indicate the ADC is ready.
Channel selector. These four bits are used to select input signal for AD conversion.
0000: PB0/AD0,
0001: PB1/AD1,
0010: PB2/AD2,
0011: PB3/AD3,
0100: PB4/AD4,
5-2
0000
R/W
0101: PB5/AD5,
0110: PB6/AD6,
0111: PB7/AD7,
1000: PA3/AD8,
1001: PA4/AD9,
1010: PA0/AD10,
1111: (Channel F) Band-gap reference voltage or 0.25*VDD
Others: reserved
0-1
-
-
Reserved. (keep 0 for future compatibility)
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12-bit ADC Enhanced Controller
6.38. ADC Mode Register (adcm), IO address = 0x3c
Bit
Reset
R/W
7-4
-
-
Description
Reserved (keep 0 for future compatibility)
ADC clock source selection.
000: CLK (system clock) ÷ 1,
001: CLK (system clock) ÷ 2,
010: CLK (system clock) ÷ 4,
3-1
000
WO
011: CLK (system clock) ÷ 8,
100: CLK (system clock) ÷ 16,
101: CLK (system clock) ÷ 32,
110: CLK (system clock) ÷ 64,
111: CLK (system clock) ÷ 128,
0
-
-
Reserved
6.39. ADC Regulator Control Register (adcrgc), IO address = 0x3d
Bit
Reset
R/W
Description
These three bits are used to select input signal for ADC reference high voltage.
000: VDD,
001: 2V,
7-5
000
WO
010: 3V,
011: 4V,
100: PB1,
101: Band-gap 1.20 volt reference voltage
Others: reserved
ADC channel F selector:
4
0
WO
0: Band-gap reference voltage
1: 0.25*VDD. The deviation is within ±0.01*VDD mostly.
Band-gap reference voltage selector for ADC channel F:
00: 1.2V
3-2
00
WO
01: 2V
10: 3V
11: 4V
1-0
-
-
Reserved. Please keep 0.
6.40. ADC Result High Register (adcrh), IO address = 0x3e
Bit
Reset
R/W
7-0
-
RO
Description
These eight read-only bits will be the bit [11:4] of AD conversion result. The bit 7 of this
register is the MSB of ADC result for any resolution.
6.41. ADC Result Low Register (adcrl), IO address = 0x3f
Bit
Reset
R/W
7-4
-
RO
3-0
-
-
Description
These four bits will be the bit [3:0] of AD conversion result.
Reserved
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12-bit ADC Enhanced Controller
6.42. PWMG1 control Register (pwmg1c), IO address = 0x26
Bit
Reset
R/W
Description
7
0
WO
Enable PWMG1. 0 / 1 : disable / enable.
6
-
RO
Output of PWMG1.
5
0
WO
Enable to inverse the polarity of PWMG1 output. 0 / 1 : disable / enable.
4
0
WO
PWMG1 counter reset.
Writing “1” to clear PWMG1 counter.
Select PWMG1 output pin.
000: none
3-1
0
WO
001: PB6
011: PA4
100: PB7
Others: reserved
0
0
WO
Clock source of PWMG1.
0 : SYSCLK
1 : IHRC or IHRC * 2 (by Code Option : PWM_Source)
6.43. PWMG1 Scalar Register (pwmg1s), IO address = 0x27
Bit
Reset
R/W
7
0
WO
Description
PWMG1 interrupt mode.
0: Generate interrupt when counter matches the duty value.
1: Generate interrupt when counter is 0.
PWMG1 clock pre-scalar.
00 : ÷1
6-5
0
WO
01 : ÷4
10 : ÷16
11 : ÷64
4-0
0
WO
PWMG1 clock divider.
6.44. PWMG1 Counter Upper Bound High Register (pwmg1cubh), IO address = 0x2A
Bit
Reset
R/W
7-0
8’h00
WO
Description
Bit[10:3] of PWMG1 counter upper bound.
6.45. PWMG1 Counter Upper Bound Low Register (pwmg1cubl), IO address = 0x2B
Bit
Reset
R/W
7-5
000
WO
4-0
-
-
Description
Bit[2:0] of PWMG1 counter upper bound.
Reserved
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12-bit ADC Enhanced Controller
6.46. PWMG1 Duty Value High Register (pwmg1dth), IO address = 0x28
Bit
Reset
R/W
7-0
8’h00
WO
Description
Duty values bit[10:3] of PWMG1.
6.47. PWMG1 Duty Value Low Register (pwmg1dtl), IO address = 0x29
Bit
Reset
R/W
7-5
000
WO
4-0
-
-
Description
Duty values bit[2:0] of PWMG1.
Reserved
Note: It’s necessary to write PWMG1 Duty_Value Low Register before writing PWMG1 Duty_Value High Register.
6.48. PWMG2 control Register (pwmg2c), IO address = 0x2C
Bit
Reset
R/W
Description
7
0
WO
Enable PWMG2. 0 / 1 : disable / enable.
6
-
RO
Output of PWMG2.
5
0
WO
Enable to inverse the polarity of PWMG2 output. 0 / 1 : disable / enable.
4
0
WO
PWMG2 counter reset.
Writing “1” to clear PWMG2 counter.
3-1
0
WO
Select PWMG2 output pin.
000: disable
001: PB3
011: PA3
100: PB2
101: PA5
Others: reserved
0
0
WO
Clock source of PWMG2.
0 : SYSCLK
1 : IHRC or IHRC * 2 (by Code Option : PWM_Source)
6.49. PWMG2 Scalar Register (pwmg2s), IO address = 0x2D
Bit
Reset
R/W
7
0
WO
6-5
0
WO
4-0
0
WO
Description
PWMG2 interrupt mode.
0: Generate interrupt when counter matches the duty value.
1: Generate interrupt when counter is 0.
PWMG2 clock pre-scalar.
00 : ÷1
01 : ÷4
10 : ÷16
11 : ÷64
PWMG2 clock divider.
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12-bit ADC Enhanced Controller
6.50. PWMG2 Counter Upper Bound High Register (pwmg2cubh), IO address = 0x30
Bit
Reset
R/W
7-0
8’h00
WO
Description
Bit[10:3] of PWMG2 counter upper bound.
6.51. PWMG2 Counter Upper Bound Low Register (pwmg2cubl), IO address = 0x31
Bit
Reset
R/W
7-5
000
WO
4-0
-
-
Description
Bit[2:0] of PWMG2 counter upper bound.
Reserved
6.52. PWMG2 Duty Value High Register (pwmg2dth), IO address = 0x2E
Bit
Reset
R/W
7-0
8’h00
WO
Description
Duty values bit[10:3] of PWMG2.
6.53. PWMG2 Duty Value Low Register (pwmg2dtl), IO address = 0x2F
Bit
Reset
R/W
7-5
000
WO
4-0
-
-
Description
Duty values bit[2:0] of PWMG2.
Reserved
Note: It’s necessary to write PWMG2 Duty_Value Low Register before writing PWMG2 Duty_Value High Register.
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PMS132
12-bit ADC Enhanced Controller
7. Instructions
Symbol
ACC
a
sp
flag
Description
Accumulator (Abbreviation of accumulator)
Accumulator (symbol of accumulator in program)
Stack pointer
ACC status flag register
I
Immediate data
&
Logical AND
|
Logical OR
←
Movement
^
Exclusive logic OR
+
Add
－
Subtraction
〜
NOT (logical complement, 1’s complement)
〒
NEG (2’s complement)
OV
Overflow (The operational result is out of range in signed 2’s complement number system)
Z
C
AC
Zero (If the result of ALU operation is zero, this bit is set to 1)
Carry (The operational result is to have carry out for addition or to borrow carry for subtraction in
unsigned number system)
Auxiliary Carry
(If there is a carry out from low nibble after the result of ALU operation, this bit is set to 1)
IO.n
The bit of register
M.n
Only addressed in 0~0x3F (0~63) is allowed
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12-bit ADC Enhanced Controller
7.1. Data Transfer Instructions
mov
a, I
mov
M, a
mov
a, M
mov
a, IO
mov
IO, a
ldt16
word
Move immediate data into ACC.
Example: mov
a, 0x0f;
Result:
a ← 0fh;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Move data from ACC into memory
Example: mov
MEM, a;
Result:
MEM ← a
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Move data from memory into ACC
Example: mov
a, MEM ;
Result:
a ← MEM; Flag Z is set when MEM is zero.
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Move data from IO into ACC
Example: mov
a, pa ;
Result:
a ← pa; Flag Z is set when pa is zero.
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Move data from ACC into IO
Example: mov
pb, a;
Result:
pb ← a
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Move 16-bit counting values in Timer16 to memory in word.
Example: ldt16 word;
Result:
word ← 16-bit timer
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
-----------------------------------------------------------------------------------------------------------------------word
T16val ;
// declare a RAM word
…
clear
lb@ T16val ;
// clear T16val (LSB)
clear
hb@ T16val ;
// clear T16val (MSB)
stt16
T16val ;
// initial T16 with 0
…
set1
t16m.5 ;
// enable Timer16
…
set0
t16m.5 ;
// disable Timer 16
ldt16
T16val ;
// save the T16 counting value to T16val
….
------------------------------------------------------------------------------------------------------------------------
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12-bit ADC Enhanced Controller
stt16
word
idxm
a, index
Idxm
index, a
Store 16-bit data from memory in word to Timer16.
Example: stt16 word;
Result:
16-bit timer ←word
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
-----------------------------------------------------------------------------------------------------------------------word
T16val ;
// declare a RAM word
…
mov
a, 0x34 ;
mov
lb@ T16val , a ; // move 0x34 to T16val (LSB)
mov
a, 0x12 ;
mov
hb@ T16val , a ; // move 0x12 to T16val (MSB)
stt16
T16val ;
// initial T16 with 0x1234
…
---------------------------------------------------------------------------------------------------------------------Move data from specified memory to ACC by indirect method. It needs 2T to execute this
instruction.
Example: idxm a, index;
Result:
a ← [index], where index is declared by word.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
----------------------------------------------------------------------------------------------------------------------word
RAMIndex ;
// declare a RAM pointer
…
mov
a, 0x5B ;
// assign pointer to an address (LSB)
mov
lb@RAMIndex, a ;
// save pointer to RAM (LSB)
mov
a, 0x00 ;
// assign 0x00 to an address (MSB), should be 0
mov
hb@RAMIndex, a ; // save pointer to RAM (MSB)
…
idxm
a, RAMIndex ;
// mov memory data in address 0x5B to ACC
----------------------------------------------------------------------------------------------------- ------------------Move data from ACC to specified memory by indirect method. It needs 2T to execute this
instruction.
Example: idxm index, a;
Result:
[index] ← a; where index is declared by word.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
-----------------------------------------------------------------------------------------------------------------------word
RAMIndex ;
// declare a RAM pointer
…
mov
a, 0x5B ;
// assign pointer to an address (LSB)
mov
lb@RAMIndex, a ;
// save pointer to RAM (LSB)
mov
a, 0x00 ;
// assign 0x00 to an address (MSB), should be 0
mov
hb@RAMIndex, a ; // save pointer to RAM (MSB)
…
mov
a, 0xA5 ;
idxm
RAMIndex, a ;
// mov 0xA5 to memory in address 0x5B
------------------------------------------------------------------------------------------------------------------------
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12-bit ADC Enhanced Controller
xch
M
pushaf
Exchange data between ACC and memory
Example: xch MEM ;
Result:
MEM ← a , a ← MEM
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Move the ACC and flag register to memory that address specified in the stack pointer.
Example: pushaf;
Result:
[sp] ← {flag, ACC};
sp ← sp + 2 ;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
-----------------------------------------------------------------------------------------------------------------------.romadr 0x10 ;
// ISR entry address
pushaf ;
// put ACC and flag into stack memory
…
// ISR program
…
// ISR program
popaf ;
// restore ACC and flag from stack memory
reti ;
-----------------------------------------------------------------------------------------------------------------------Restore ACC and flag from the memory which address is specified in the stack pointer.
Example: popaf;
Result:
sp ← sp - 2 ;
{Flag, ACC} ← [sp] ;
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
popaf
7.2. Arithmetic Operation Instructions
add
a, I
add
a, M
add
M, a
addc
a, M
addc
M, a
Add immediate data with ACC, then put result into ACC
Example: add
a, 0x0f ;
Result:
a ← a + 0fh
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Add data in memory with ACC, then put result into ACC
Example: add
a, MEM ;
Result:
a ← a + MEM
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Add data in memory with ACC, then put result into memory
Example: add
MEM, a;
Result:
MEM ← a + MEM
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Add data in memory with ACC and carry bit, then put result into ACC
Example: addc
a, MEM ;
Result:
a ← a + MEM + C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Add data in memory with ACC and carry bit, then put result into memory
Example: addc
MEM, a ;
Result:
MEM ← a + MEM + C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
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12-bit ADC Enhanced Controller
addc
a
addc
M
nadd
a, M
nadd
M, a
sub
a, I
sub
a, M
sub
M, a
subc
a, M
subc
M, a
subc
a
subc
M
Add carry with ACC, then put result into ACC
Example: addc
a;
Result:
a←a+C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Add carry with memory, then put result into memory
Example: addc
MEM ;
Result:
MEM ← MEM + C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Add negative logic (2’s complement) of ACC with memory
Example: nadd
a, MEM ;
Result:
a ← 〒a + MEM
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Add negative logic (2’s complement) of memory with ACC
Example: nadd
MEM, a ;
Result:
MEM ← 〒MEM + a
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Subtraction immediate data from ACC, then put result into ACC.
Example: sub
a, 0x0f;
Result:
a ← a - 0fh ( a + [2’s complement of 0fh] )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Subtraction data in memory from ACC, then put result into ACC
Example: sub
a, MEM ;
Result:
a ← a - MEM ( a + [2’s complement of M] )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Subtraction data in ACC from memory, then put result into memory
Example: sub
MEM, a;
Result:
MEM ← MEM - a ( MEM + [2’s complement of a] )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Subtraction data in memory and carry from ACC, then put result into ACC
Example: subc
a, MEM;
Result:
a ← a – MEM - C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Subtraction ACC and carry bit from memory, then put result into memory
Example: subc
MEM, a ;
Result:
MEM ← MEM – a - C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Subtraction carry from ACC, then put result into ACC
Example: subc
a;
Result:
a←a-C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Subtraction carry from the content of memory, then put result into memory
Example: subc
MEM;
Result:
MEM ← MEM - C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
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12-bit ADC Enhanced Controller
inc
M
dec
M
clear
M
mul
Increment the content of memory
Example: inc
MEM ;
Result:
MEM ← MEM + 1
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Decrement the content of memory
Example: dec
MEM;
Result:
MEM ← MEM - 1
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Clear the content of memory
Example: clear
MEM ;
Result:
MEM ← 0
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Multiplication operation, 8x8 unsigned multiplications will be executed.
Example: mul ;
Result:
{MulRH,ACC} ← ACC * MulOp
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example :
--------------------------------------------------------------------------------------------------------------------…
mov
a, 0x5a ;
mov
mulop, a ;
mov
a, 0xa5 ;
mul
// 0x5A * 0xA5 = 3A02 (mulrh + ACC)
mov
ram0, a ;
// LSB, ram0=0x02
mov
a, mulrh ;
// MSB, ACC=0X3A
…
---------------------------------------------------------------------------------------------------------------------
7.3. Shift Operation Instructions
sr
src
sr
src
a
a
M
M
Shift right of ACC, shift 0 to bit 7
Example: sr
a;
Result: a (0,b7,b6,b5,b4,b3,b2,b1) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a(b0)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift right of ACC with carry bit 7 to flag
Example: src a ;
Result: a (c,b7,b6,b5,b4,b3,b2,b1) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a(b0)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift right the content of memory, shift 0 to bit 7
Example: sr MEM ;
Result: MEM(0,b7,b6,b5,b4,b3,b2,b1) ← MEM(b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM(b0)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift right of memory with carry bit 7 to flag
Example: src MEM ;
Result: MEM(c,b7,b6,b5,b4,b3,b2,b1) ← MEM (b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM(b0)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
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12-bit ADC Enhanced Controller
sl
slc
sl
slc
a
a
M
M
swap
a
Shift left of ACC shift 0 to bit 0
Example: sl a ;
Result: a (b6,b5,b4,b3,b2,b1,b0,0) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a (b7)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift left of ACC with carry bit 0 to flag
Example: slc a ;
Result: a (b6,b5,b4,b3,b2,b1,b0,c) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a(b7)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift left of memory, shift 0 to bit 0
Example: sl MEM ;
Result: MEM (b6,b5,b4,b3,b2,b1,b0,0) ← MEM (b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM(b7)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift left of memory with carry bit 0 to flag
Example: slc MEM ;
Result: MEM (b6,b5,b4,b3,b2,b1,b0,C) ← MEM (b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM (b7)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Swap the high nibble and low nibble of ACC
Example: swap
a;
Result:
a (b3,b2,b1,b0,b7,b6,b5,b4) ← a (b7,b6,b5,b4,b3,b2,b1,b0)
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
7.4. Logic Operation Instructions
and
a, I
and
a, M
and
M, a
or
a, I
or
a, M
or
M, a
Perform logic AND on ACC and immediate data, then put result into ACC
Example: and
a, 0x0f ;
Result:
a ← a & 0fh
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic AND on ACC and memory, then put result into ACC
Example: and
a, RAM10 ;
Result:
a ← a & RAM10
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic AND on ACC and memory, then put result into memory
Example: and
MEM, a ;
Result:
MEM ← a & MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic OR on ACC and immediate data, then put result into ACC
Example: or
a, 0x0f ;
Result:
a ← a | 0fh
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic OR on ACC and memory, then put result into ACC
Example: or
a, MEM ;
Result:
a ← a | MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic OR on ACC and memory, then put result into memory
Example: or
MEM, a ;
Result:
MEM ← a | MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
© Copyright 2017, PADAUK Technology Co. Ltd
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12-bit ADC Enhanced Controller
xor
a, I
xor
IO, a
xor
a, M
xor
M, a
not
a
not
M
neg
a
Perform logic XOR on ACC and immediate data, then put result into ACC
Example: xor
a, 0x0f ;
Result:
a ← a ^ 0fh
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic XOR on ACC and IO register, then put result into IO register
Example: xor
pa, a ;
Result:
pa ← a ^ pa ; // pa is the data register of port A
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Perform logic XOR on ACC and memory, then put result into ACC
Example: xor
a, MEM ;
Result:
a ← a ^ RAM10
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic XOR on ACC and memory, then put result into memory
Example:
xor
MEM, a ;
Result:
MEM ← a ^ MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform 1’s complement (logical complement) of ACC
Example: not
a;
Result:
a ← 〜a
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Application Example:
-----------------------------------------------------------------------------------------------------------------------mov
a, 0x38 ;
// ACC=0X38
not
a;
// ACC=0XC7
-----------------------------------------------------------------------------------------------------------------------Perform 1’s complement (logical complement) of memory
Example: not
MEM ;
Result:
MEM ← 〜MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Application Example:
-----------------------------------------------------------------------------------------------------------------------mov
a, 0x38 ;
mov
mem, a ;
// mem = 0x38
not
mem ;
// mem = 0xC7
-----------------------------------------------------------------------------------------------------------------------Perform 2’s complement of ACC
Example: neg
a;
Result:
a ← 〒a
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Application Example:
-----------------------------------------------------------------------------------------------------------------------mov
a, 0x38 ;
// ACC=0X38
neg
a;
// ACC=0XC8
------------------------------------------------------------------------------------------------------------------------
© Copyright 2017, PADAUK Technology Co. Ltd
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12-bit ADC Enhanced Controller
neg
M
comp
a, M
comp
M, a
Perform 2’s complement of memory
Example: neg
MEM;
Result:
MEM ← 〒MEM
Affected flags: 『Y』Z 『N』C 『N』AC
『N』OV
Application Example:
-----------------------------------------------------------------------------------------------------------------------mov
a, 0x38 ;
mov
mem, a ;
// mem = 0x38
not
mem ;
// mem = 0xC8
-----------------------------------------------------------------------------------------------------------------------Compare ACC with the content of memory
Example: comp
a, MEM;
Result: Flag will be changed by regarding as ( a - MEM )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Application Example:
-----------------------------------------------------------------------------------------------------------------------mov
a, 0x38 ;
mov
mem, a ;
comp
a, mem ; // Z flag is set as 1
mov
a, 0x42 ;
mov
mem, a ;
mov
a, 0x38 ;
comp
a, mem ; // C flag is set as 1
-----------------------------------------------------------------------------------------------------------------------Compare ACC with the content of memory
Example: comp
MEM, a;
Result: Flag will be changed by regarding as ( MEM - a )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
7.5. Bit Operation Instructions
set0
set1
IO.n
IO.n
Set bit n of IO port to low
Example: set0 pa.5 ;
Result: set bit 5 of port A to low
Affected flags: 『N』Z 『N』C
Set bit n of IO port to high
Example: set1 pb.5 ;
Result: set bit 5 of port B to high
Affected flags: 『N』Z 『N』C
© Copyright 2017, PADAUK Technology Co. Ltd
『N』AC
『N』OV
『N』AC
『N』OV
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PMS132
12-bit ADC Enhanced Controller
swapc
IO.n
Swap the nth bit of IO port with carry bit
Example:
Result:
swapc
IO.0;
C ← IO.0 , IO.0 ← C
When IO.0 is a port to output pin, carry C will be sent to IO.0;
When IO.0 is a port from input pin, IO.0 will be sent to carry C;
Affected flags: 『N』Z
『Y』C
『N』AC
『N』OV
Application Example1 (serial output) :
-----------------------------------------------------------------------------------------------------------------------...
set1
pac.0 ;
// set PA.0 as output
flag.1 ;
// C=0
...
set0
swapc
set1
swapc
pa.0 ;
flag.1 ;
pa.0 ;
// move C to PA.0 (bit operation), PA.0=0
// C=1
// move C to PA.0 (bit operation), PA.0=1
...
-----------------------------------------------------------------------------------------------------------------------Application Example2 (serial input) :
-----------------------------------------------------------------------------------------------------------------------...
set0
pac.0 ;
// set PA.0 as input
swapc
pa.0 ;
// read PA.0 to C (bit operation)
src
a;
// shift C to bit 7 of ACC
swapc
pa.0 ;
// read PA.0 to C (bit operation)
src
a;
// shift new C to bit 7, old C
...
...
set0
M.n
set1
M.n
------------------------------------------------------------------------------------------------------------------- ----Set bit n of memory to low
Example: set0 MEM.5 ;
Result: set bit 5 of MEM to low
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Set bit n of memory to high
Example: set1 MEM.5 ;
Result: set bit 5 of MEM to high
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
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12-bit ADC Enhanced Controller
7.6. Conditional Operation Instructions
ceqsn
a, I
ceqsn
a, M
cneqsn
a, M
Compare ACC with immediate data and skip next instruction if both are equal.
Flag will be changed like as (a ← a – I)
Example: ceqsn
a, 0x55 ;
inc
MEM ;
goto
error ;
Result: If a=0x55, then “goto error”; otherwise, “inc MEM”.
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Compare ACC with memory and skip next instruction if both are equal.
Flag will be changed like as (a ← a - M)
Example: ceqsn
a, MEM;
Result: If a=MEM, skip next instruction
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Compare ACC with memory and skip next instruction if both are not equal.
Flag will be changed like as (a ← a - M)
Example:
cneqsn
a, MEM;
Result: If a≠MEM, skip next instruction
Affected flags: 『Y』Z 『Y』C 『Y』AC
cneqsn
a, I
『Y』OV
Compare ACC with immediate data and skip next instruction if both are no equal.
Flag will be changed like as (a ← a - I)
Example:
cneqsn
inc
goto
a,0x55 ;
MEM ;
error ;
Result: If a≠0x55, then “goto error”; Otherwise, “inc MEM”.
t0sn
IO.n
t1sn
IO.n
t0sn
M.n
t1sn
M.n
izsn
a
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Check IO bit and skip next instruction if it’s low
Example: t0sn
pa.5;
Result: If bit 5 of port A is low, skip next instruction
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Check IO bit and skip next instruction if it’s high
Example: t1sn
pa.5 ;
Result: If bit 5 of port A is high, skip next instruction
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Check memory bit and skip next instruction if it’s low
Example: t0sn MEM.5 ;
Result: If bit 5 of MEM is low, then skip next instruction
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Check memory bit and skip next instruction if it’s high
EX: t1sn MEM.5 ;
Result: If bit 5 of MEM is high, then skip next instruction
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Increment ACC and skip next instruction if ACC is zero
Example: izsn
a;
Result:
a ← a + 1,skip next instruction if a = 0
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
© Copyright 2017, PADAUK Technology Co. Ltd
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PMS132
12-bit ADC Enhanced Controller
dzsn
a
izsn
M
dzsn
M
Decrement ACC and skip next instruction if ACC is zero
Example: dzsn
a;
Result:
A ← A - 1,skip next instruction if a = 0
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Increment memory and skip next instruction if memory is zero
Example: izsn
MEM;
Result:
MEM ← MEM + 1, skip next instruction if MEM= 0
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Decrement memory and skip next instruction if memory is zero
Example: dzsn
MEM;
Result:
MEM ← MEM - 1, skip next instruction if MEM = 0
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
7.7. System control Instructions
call
label
goto
label
ret
ret
reti
nop
I
Function call, address can be full range address space
Example: call
function1;
Result:
[sp] ← pc + 1
pc ← function1
sp ← sp + 2
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Go to specific address which can be full range address space
Example: goto
error;
Result:
Go to error and execute program.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Place immediate data to ACC, then return
Example: ret 0x55;
Result:
A ← 55h
ret ;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Return to program which had function call
Example: ret;
Result:
sp ← sp - 2
pc ← [sp]
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Return to program that is interrupt service routine. After this command is executed, global
interrupt is enabled automatically.
Example: reti;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
No operation
Example: nop;
Result: nothing changed
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
© Copyright 2017, PADAUK Technology Co. Ltd
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PMS132
12-bit ADC Enhanced Controller
pcadd
engint
disgint
stopsys
stopexe
reset
wdreset
a
Next program counter is current program counter plus ACC.
Example: pcadd a;
Result: pc ← pc + a
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
-----------------------------------------------------------------------------------------------------------------------…
mov
a, 0x02 ;
pcadd
a;
// PC 33Ω resistor in between PA5 and the long wire
Avoid using PA5 as input in such application.
(6) PA7 and PA6 as external crystal oscillator
Configure PA7 and PA6 as input
Disable PA7 and PA6 internal pull-up resistor
Configure PADIER register to set PA6 and PA7 as analog input
EOSCR register bit [6:5] selects corresponding crystal oscillator frequency :
01 : for lower frequency, ex : 32KHz (reserved)
10 : for middle frequency, ex : 455KHz, 1MHz
11 : for higher frequency, ex : 4MHz
Program EOSCR.7 =1 to enable crystal oscillator
Ensure EOSC working well before switching from IHRC or ILRC to EOSC, refer to 9.2.3.(2)
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12-bit ADC Enhanced Controller
9.2.2 Interrupt
(1) When using the interrupt function, the procedure should be:
Step1: Set INTEN register, enable the interrupt control bit
Step2: Clear INTRQ register
Step3: In the main program, using ENGINT to enable CPU interrupt function
Step4: Wait for interrupt. When interrupt occurs, enter to Interrupt Service Routine
Step5: After the Interrupt Service Routine being executed, return to the main program
*Use DISGINT in the main program to disable all interrupts
*When interrupt service routine starts, use PUSHAF instruction to save ALU and FLAG register.
POPAF instruction is to restore ALU and FLAG register before RETI as below:
void Interrupt (void)
// Once the interrupt occurs, jump to interrupt service routine
{
// enter DISGINT status automatically, no more interrupt is accepted
PUSHAF;
…
POPAF;
}
// RETI will be added automatically. After RETI being executed, ENGINT status will be
restored
(2) INTEN and INTRQ have no initial values. Please set required value before enabling interrupt function
(3) PA4 and PB5 can be used as external interrupt pins. When using the PA4 as external interrupt pin, the
setting method of inten/intrq/integs registers are same as that of PB0, the only difference is to choose PB0
or PA4 as source of interrupt_Src1 in PADAUK_CODE_OPTION. Similarly, when using the PB5 as external
interrupt pin, the setting method of inten/intrq/integs registers are same as that of PA0, the only difference
is to choose PA0 or PB5 as source of interrupt_Src0 in PADAUK_CODE_OPTION.
9.2.3 System clock switching
(1) System clock can be switched by CLKMD register. Please notice that, NEVER switch the system clock
and turn off the original clock source at the same time. For example: When switching from clock A to clock B,
please switch to clock B first; and after that turn off the clock A oscillator through CLKMD.
Case 1 : Switch system clock from ILRC to IHRC/2
CLKMD
=
CLKMD.2 =
0;
// switch to IHRC, ILRC can not be disabled here
// ILRC can be disabled at this time
Case 2 : Switch system clock from ILRC to EOSC
CLKMD
=
CLKMD.2 =
0x36;
0xA6;
// switch to EOSC, ILRC can not be disabled here
0;
// ILRC can be disabled at this time
ERROR. Switch ILRC to IHRC and turn off ILRC simultaneously
CLKMD
=
0x50;
© Copyright 2017, PADAUK Technology Co. Ltd
// MCU will hang
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12-bit ADC Enhanced Controller
(2) Please ensure the EOSC oscillation has established before switching from ILRC or IHRC to EOSC. MCU
will not check its status. Please wait for a while after enabling EOSC. System clock can be switched to
EOSC afterwards. Otherwise, MCU will hang. The example for switching system clock from ILRC to 4MHz
EOSC after boot up is as below:
.ADJUST_IC
SYSCLK=ILRC;
$
Enable, 4MHz;
EOSCR
// 4MHz EOSC start to oscillate.
// delay time to wait crystal oscillator stable
$ T16M EOSC, /1, BIT10
Word Count = 0;
Stt16 Count;
Intrq.T16 = 0;
do
{ nop; }while(!Intrq.T16);
CLKMD
= 0xA4;
// ILRC -> EOSC;
CLKMD.2 = 0;
// turn off ILRC only if necessary
The delay duration should be adjusted in accordance with the characteristic of the crystal and PCB. To
measure the oscillator signal by the oscilloscope, please select (x10) on the probe and measure through
PA6(X2) pin to avoid the interference on the oscillator.
9.2.4 Power down mode, wakeup and watchdog
Watchdog will be inactive once ILRC is disabled.
9.2.5 TIMER time out
When select T16M counter BIT8 as 1 to generate interrupt, the first interrupt will occur when the counter
reaches to 0x100 ( BIT8 from 0 to 1) and the second interrupt will occur when the counter reaches 0x300（BIT8
from 0 to 1）. Therefore, selecting BIT8 as 1 to generate interrupt means that the interrupt occurs every 512
counts. Please notice that if T16M counter is restarted, the next interrupt will occur once Bit8 turns from 0 to 1.
9.2.6 IHRC
(1) The IHRC frequency calibration is performed when IC is programmed by the writer.
(2) Because the characteristic of the Epoxy Molding Compound (EMC) would some degrees affects the
IHRC frequency (either for package or COB), if the calibration is done before molding process, the actual
IHRC frequency after molding may be deviated or becomes out of spec. Normally , the frequency is getting
slower a bit.
(3) It usually happens in COB package or Quick Turnover Programming (QTP). And PADAUK would not
take any responsibility for this situation.
(4) Users can make some compensatory adjustments according to their own experiences. For example, users
can set IHRC frequency to be 0.5% ~ 1% higher and aim to get better re-targeting after molding.
© Copyright 2017, PADAUK Technology Co. Ltd
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12-bit ADC Enhanced Controller
9.2.7 LVR
(1) VDD must reach or above 2.0V for successful power-on process; otherwise IC will be inactive.
(2) The setting of LVR (1.8V, 2.0V, 2.2V etc.) will be valid just after successful power-on process.
(3) User can set MISC.2 as “1” to disable LVR. However, VDD must be kept as exceeding the lowest working
voltage of chip; Otherwise IC may work abnormally.
9.2.8 The result of Comparator controls the PWM output pins
The special function of GPC_PWM in PADAUK_CODE_OPTION is used to control the output pins of PWM
modules including TM2, TM3 and PWMG0 / PWMG1 / PWMG2 according to the status of gpcc.6. Any output
pins of those PWM modules will go to 0 when gpcc.6 is 1 and go back to normal PWM function when gpcc.6 is
0.
9.2.9 Instructions
(1) PMS132 supports 87 instructions.
(2) The instruction execution cycle of PMS132 is shown as below:
Instruction
Condition
goto, call, pcadd, ret, reti
CPU
2T
Condition is fulfilled
2T
Condition is not fulfilled
1T
ceqsn, cneqsn, t0sn, t1sn, dzsn, izsn
idxm
2T
Others
1T
9.2.10 BIT definition
Bit access of RAM is only available for address from 0x00 to 0x3F.
© Copyright 2017, PADAUK Technology Co. Ltd
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12-bit ADC Enhanced Controller
9.2.11 Programming the PMS132
There are 6 pins for using the writer to program: PA3, PA4, PA5, PA6, VDD, and GND.
Please use PDK3S-P-002 to program and put the PMS132-S16A/ S16B /S14 to move down three spaces over
the CN38. Other packages could be programmed by user’s way. All the left signs behind the jumper are the
same (there are VDD, PA0(not required), PA3, PA4, PA5, PA6, PA7(not required), and GND).The following
picture is shown:
If user use PDK5S-P-002 or above to program, please follow the instruction.
9.3 Using ICE
(1) It is recommended to use PDK5S-I-S01 for emulation of PMS132. PDK5S-I-S01 supports PMS132 1-FPPA
MCU emulation work, the following items should be noted when using PDK5S-I-S01 to emulate PMS132:
PDK5S-I-S01 doesn’t support the instruction NADD/COMP of PMS132.
PDK5S-I-S01 doesn’t support SYSCLK=ILRC/16 of PMS132.
PDK5S-I-S01 doesn’t support the function TM2.GPCRS/TM3.GPCRS of PMS132.
PDK5S-I-S01 doesn’t support the function PWMG2C.PA5.
PDK5S-I-S01 doesn’t support the function ADCRGC.BG_2V/BG_3V_BG_4V, and fix BG_1V2 only.
PDK5S-I-S01 doesn’t support the code options: GPC_PWM, PWM_Source, and TMx_bit.
Fast Wakeup time is different from PDK5S-I-S01: 128 SysClk, PMS132: 45 ILRC
Watch dog time out period is different from PDK5S-I-S01:
WDT period
PMS132
PDK5S-I-S01
misc[1:0]=00
8K* TILRC
2048* TILRC
misc[1:0]=01
16K* TILRC
4096* TILRC
misc[1:0]=10
64K* TILRC
16384* TILRC
misc[1:0]=11
256K* TILRC
256* TILRC
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