THGBMJG7C1LBAIL
TOSHIBA Memory e-MMC Module
16GB THGBMJG7C1LBAIL
y
INTRODUCTION
FEATURES
THGBMJG7C1LBAIL Interface
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THGBMJG7C1LBAIL is 16GB density of e-MMC Module product housed in 153 ball BGA package. This unit is utilized
advanced TOSHIBA NAND flash device(s) and controller chip assembled as Multi Chip Module. THGBMJG7C1LBAIL
has an industry standard MMC protocol for easy use.
THGBMJG7C1LBAIL has the JEDEC/MMCA Version 5.1 interface with 1-I/O, 4-I/O and 8-I/O mode.
Pin Connection
P-WFBGA153-1113-0.50 (11.5mm x 13mm, H0.8mm max. package)
14
NC
NC
NC
NC
NC
13
NC
NC
NC
NC
NC
12
NC
NC
NC
NC
NC
11
NC
NC
NC
10
NC
NC
NC
VSF VSF RFU VSS
9
NC
NC
NC
VSF
8
NC
NC
NC
RFU
6
5
4
3
2
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VCC RFU
NC
NC
RFU
VCC
NC
NC
NC
VSS
NC
NC
NC
Top View
RFU NC
NC
VSS
RFU
NC
NC
RFU
VSS
DAT7
VCCQ
VCC
RFU
CLK
NC
VSSQ
DAT2
DAT6
NC
DAT1
DAT5
VSSQ NC index
DAT0
DAT4
NC
NC
NC
NC
RFU NC
NC
NC
NC
NC
NC
DAT3
VDDi NC
NC
NC
NC
NC
NC
NC
NC
NC VSSQ NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
A
B
C
D
E
F
G
H
J
K
L
M
N
P
RFU VCC
VSS
DS
VSS
CMD VSSQ VCCQ
RST_n
VCCQ VCCQ VSSQ
NC VCCQ
Pin Number
Name
Pin Number
Name
Pin Number
Name
Pin Number
Name
A3
DAT0
C2
VDDi
J5
VSS
N4
VCCQ
Pre
1
NC
lim
7
NC
A4
DAT1
C4
VSSQ
J10
VCC
N5
VSSQ
A5
DAT2
C6
VCCQ
K5
RST_n
P3
VCCQ
A6
VSS
E6
VCC
K8
VSS
P4
VSSQ
B2
DAT3
E7
VSS
K9
VCC
P5
VCCQ
B3
DAT4
F5
VCC
M4
VCCQ
P6
VSSQ
B4
DAT5
G5
VSS
M5
CMD
B5
DAT6
H5
DS
M6
CLK
B6
DAT7
H10
VSS
N2
VSSQ
NC: No Connect, shall be connected to ground or left floating.
RFU: Reserved for Future Use, shall be left floating for future use.
VSF: Vendor Specific Function, shall be left floating.
© 2019 Toshiba Memory Corporation
1
January 31st, 2019
THGBMJG7C1LBAIL
Part Number
Part Number
Density
Package Size
THGBMJG7C1LBAIL
16GB
11.5mm x 13mm x 0.8mm(max)
NAND Flash Type
Weight
1 x 128Gbit 15nm
0.17g typ.
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Temperature
y
Available e-MMC Module Product – Part Number
Characteristics
Operating temperature
Storage temperature
Min
Max
Unit
-25
85
°C
-40
85
°C
Note: Avoid locations where e-MMC devices may be exposed to water (wet, rain, dew condensation, etc).
Performance
X8 mode/ Sequential access(4MByte access size)
Part Number
Density
NAND Flash Type
Interleave
Operation
Frequency
/Mode
52MHz/SDR
16GB
1 x 128Gbit 15nm
52MHz/DDR
lim
THGBMJG7C1LBAIL
Non
Interleave
Typ. Performance
[MB/s]
VCCQ
Read
Write
1.8V
45
45
3.3V
45
45
1.8V
90
45
3.3V
90
45
HS200
1.8V
180
45
HS400
1.8V
220
45
Power Supply
VCC = 2.7V to 3.6V
VCCQ = 1.7V to 1.95V / 2.7V to 3.6V
Operating Current (RMS)
The measurement for max RMS current is done as average RMS current consumption over a period of 100ms.
Density
NAND Flash Type
Pre
Part Number
THGBMJG7C1LBAIL
16GB
© 2019 Toshiba Memory Corporation
1 x 128Gbit 15nm
2
Interleave
Operation
Frequency
/Mode
ICCQ
ICC
1.8V
95
40
3.3V
110
40
1.8V
115
45
3.3V
140
45
HS200
1.8V
170
55
HS400
1.8V
215
55
52MHz/SDR
Non
Interleave
VCCQ
Max Operating
Current [mA]
52MHz/DDR
January 31st, 2019
THGBMJG7C1LBAIL
Part Number
Density
THGBMJG7C1LBAIL
16GB
NAND Flash Type
1 x 128Gbit 15nm
Interleave
Operation
Non Interleave
y
Sleep Mode Current
ICCQS [μA]
ICCQS+ICCS [μA]
Typ. Note 1
Max. Note 2
Typ. Note 1
Max. Note 2
100
510
120
585
Product Architecture
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Note 1: The conditions of typical values are 25°C and VCCQ = 3.3V or 1.8V.
Note 2: The conditions of maximum values are 85°C and VCCQ = 3.6V or 1.95V.
The diagram in Figure 1 illustrates the main functional blocks of the THGBMJG7C1LBAIL.
Specification of the CREG and recommended values of the CVCC, and CVCCQ in the Figure 1 are as follows.
Parameter
Symbol
VDDi capacitor value
CREG
VCC capacitor value
CVCC
VCCQ capacitor value
CVCCQ
Unit
Min.
Typ.
Max.
μF
0.10
-
2.2 Note 1
Except HS400
μF
1.00
-
2.2 Note 1
HS400
μF
-
2.2 + 0.1
-
μF
-
2.2 + 0.1
-
Remark
lim
Note 1: Toshiba Memory recommends that the value should be usually applied as the value of CREG.
Package
VCC (3.3V)
CVCC
VCCQ (1.8V / 3.3V)
x11
Pre
MMC I/F (1.8V / 3.3V)
CORE LOGIC
Figure 1
© 2019 Toshiba Memory Corporation
NAND
Control signal
NAND I/O
I/O BLOCK
CREG
REGULATOR
NAND I/O BLOCK
VDDi
MMC I/O BLOCK
CVCCQ
NAND
THGBMJG7C1LBAIL Block Diagram
3
January 31st, 2019
THGBMJG7C1LBAIL
PRODUCT SPECIFICATIONS
Package Dimensions
y
P-WFBGA153-1113-0.50 (11.5mm x 13mm, H0.8mm max. package)
Pre
lim
ina
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Unit: mm
© 2019 Toshiba Memory Corporation
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January 31st, 2019
THGBMJG7C1LBAIL
Density Specifications
Part Number
Interleave
Operation
User Area Density
[Bytes]
SEC_COUNT in
Extended CSD
16GB
THGBMJG7C1LBAIL
Non Interleave
15,758,000,128
0x01D5A000
y
Density
Register Informations
OCR Register
OCR bit
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Note: User area density shall be reduced if enhanced user data area is defined.
VDD Voltage window
Value
[6:0]
Reserved
000 0000b
1.70-1.95 V
1b
[14:8]
2.0-2.6 V
000 0000b
[23:15]
2.7-3.6 V
1 1111 1111b
[28:24]
Reserved
0 0000b
[30:29]
Access Mode
10b
[7]
( card power up status bit (busy) ) Note
[31]
Note: This bit is set to LOW if the Device has not finished the power up routine.
CID Register
[127:120]
[119:114]
[113:112]
[111:104]
[103:56]
[55:48]
[47:16]
[15:8]
[7:1]
Width
Value
MID
8
0001 0001b
Reserved
-
6
0b
Device/BGA
CBX
2
01b
OEM/Application ID
OID
8
0b
Product name
PNM
48
0x30 31 36 47 42 30 (016GB0)
Product revision
PRV
8
0x00
Product serial
PSN
32
Serial number
Manufacturing date
MDT
8
see-JEDEC Specification
CRC7 checksum
CRC
7
CRC7
Not used, always ‘1’
-
1
1b
Manufacturer ID
Pre
[0]
Field
Name
lim
CID-slice
© 2019 Toshiba Memory Corporation
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January 31st, 2019
THGBMJG7C1LBAIL
CSD Register
Name
Field
Width
Cell Type
Value
y
CSD-slice
CSD structure
CSD_STRUCTURE
2
R
0x3
[125:122]
System specification version
SPEC_VERS
4
R
0x4
[121:120]
Reserved
-
2
R
0x0
[119:112]
Data read access-time 1
TAAC
[111:104]
Data read access-time 2 in CLK cycles
(NSAC * 100)
8
R
0x27
NSAC
8
R
0x00
[103:96]
Max. bus clock frequency
TRAN_SPEED
8
R
0x32
[95:84]
Device command classes
CCC
12
R
0x8F5
[83:80]
Max. read data block length
READ_BL_LEN
4
R
0x9
[79:79]
Partial blocks for read allowed
READ_BL_PARTIAL
1
R
0x0
[78:78]
Write block misalignment
WRITE_BLK_MISALIGN
1
R
0x0
[77:77]
Read block misalignment
READ_BLK_MISALIGN
1
R
0x0
[76:76]
DSR implemented
DSR_IMP
1
R
0x0
[75:74]
Reserved
-
2
R
0x0
[73:62]
Device size
C_SIZE
12
R
0xFFF
[61:59]
Max. read current @ VDD min.
VDD_R_CURR_MIN
3
R
0x7
[58:56]
Max. read current @ VDD max.
VDD_R_CURR_MAX
3
R
0x7
[55:53]
Max. write current @ VDD min.
VDD_W_CURR_MIN
3
R
0x7
[52:50]
Max. write current @ VDD max.
VDD_W_CURR_MAX
3
R
0x7
[49:47]
Device size multiplier
C_SIZE_MULT
3
R
0x7
[46:42]
Erase group size
ERASE_GRP_SIZE
5
R
0x1F
[41:37]
Erase group size multiplier
ERASE_GRP_MULT
5
R
0x1F
[36:32]
Write protect group size
WP_GRP_SIZE
5
R
0x07
[31:31]
Write protect group enable
WP_GRP_ENABLE
1
R
0x1
[30:29]
Manufacturer default ECC
DEFAULT_ECC
2
R
0x0
[28:26]
Write speed factor
R2W_FACTOR
3
R
0x1
[25:22]
Max. write data block length
WRITE_BL_LEN
4
R
0x9
[21:21]
Partial blocks for write allowed
WRITE_BL_PARTIAL
1
R
0x0
[20:17]
Reserved
-
4
R
0x0
[16:16]
Content protection application
CONTENT_PROT_APP
1
R
0x0
[15:15]
File format group
FILE_FORMAT_GRP
1
R/W
0x0
[14:14]
Copy flag (OTP)
COPY
1
R/W
0x0
[13:13]
Permanent write protection
PERM_WRITE_PROTECT
1
R/W
0x0
[12:12]
Temporary write protection
TMP_WRITE_PROTECT
1
R/W/E
0x0
[11:10]
File format
FILE_FORMAT
2
R/W
0x0
[9:8]
ECC code
ECC
2
R/W/E
0x0
Pre
lim
ina
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[127:126]
[7:1]
CRC
CRC
7
R/W/E
CRC
[0]
Not used, always ‘1’
-
1
-
0x1
© 2019 Toshiba Memory Corporation
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January 31st, 2019
THGBMJG7C1LBAIL
Extended CSD Register
Cell
Size
(Bytes)
Type
6
-
All ‘0’
1
R
0x00
1
R
0x01
1
R
0x01
BKOPS_SUPPORT
1
R
0x01
MAX_PACKED_READS
1
R
0x3F
MAX_PACKED_WRITES
1
R
0x3F
DATA_TAG_SUPPORT
1
R
0x01
TAG_UNIT_SIZE
1
R
0x03
TAG_RES_SIZE
1
R
0x00
CONTEXT_CAPABILITIES
1
R
0x7F
LARGE_UNIT_SIZE_M1
1
R
0x00
EXT_SUPPORT
1
R
0x03
SUPPORTED_MODES
1
R
0x01
FFU_FEATURES
1
R
0x00
OPERATION_CODES_TIMEOUT
1
R
0x00
FFU_ARG
4
R
0xFFFFFFFF
BARRIER_SUPPORT
1
R
0x01
177
-
All ‘0’
Name
Field
Value
y
CSD-slice
Reserved
-
[505]
Extended Security Commands Error
EXT_SECURITY_ERR
[504]
Supported Command Sets
S_CMD_SET
[503]
HPI features
HPI_FEATURES
[502]
Background operations support
[501]
Max_packed read commands
[500]
Max_packed write commands
[499]
Data Tag Support
[498]
Tag Unit Size
[497]
Tag Resource Size
[496]
Context management capabilities
[495]
Large Unit size
[494]
Extended partitions attribute support
[493]
Supported modes
[492]
FFU features
[491]
Operation codes timeout
[490:487]
FFU Argument
[486]
Barrier support
[485:309]
Reserved
[308]
CMD Queuing Support
CMDQ_SUPPORT
1
R
0x01
[307]
CMD Queuing Depth
CMDQ_DEPTH
1
R
0x1F
[306]
Reserved
-
1
-
0x00
4
R
All ’0’
ina
r
[511:506]
lim
-
Number of FW sectors correctly programmed
[301:270]
Vendor proprietary health report
VENDOR_PROPRIETARY
_HEALTH_REPORT
32
R
All ‘0’
[269]
Device life time estimation type B
DEVICE_LIFE_TIME_EST_TYP_B
1
R
0x00
[268]
Device life time estimation type A
DEVICE_LIFE_TIME_EST_TYP_A
1
R
0x01
[267]
Pre EOL information
PRE_EOL_INFO
1
R
0x01
[266]
Optimal read size
OPTIMAL_READ_SIZE
1
R
0x08
[265]
Optimal write size
OPTIMAL_WRITE_SIZE
1
R
0x08
[264]
Optimal trim unit size
OPTIMAL_TRIM_UNIT_SIZE
1
R
0x01
[263:262]
Device version
DEVICE_VERSION
2
R
0x01
[261:254]
Firmware version
FIRMWARE_VERSION
8
R
0x03
[253]
Power class for 200MHz, DDR at VCC=3.6V
PWR_CL_DDR_200_360
1
R
0xCC
[252:249]
Cache size
CACHE_SIZE
4
R
0x00001000
[248]
Generic CMD6 timeout
GENERIC_CMD6_TIME
1
R
0x0A
[247]
Power off notification(long) timeout
POWER_OFF_LONG_TIME
1
R
0x32
[246]
Background operations status
BKOPS_STATUS
1
R
0x00
[245:242]
Number of correctly programmed sectors
CORRECTLY
_PRG_SECTORS_NUM
4
R
0x00000000
[241]
1st
INI_TIMEOUT_AP
1
R
0x1E
Pre
[305:302]
NUMBER_OF_FW_SECTORS_C
ORRECTLY_PROGRAMMED
initialization time after partitioning
© 2019 Toshiba Memory Corporation
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January 31st, 2019
THGBMJG7C1LBAIL
Name
Field
Cache Flushing Policy
CACHE_FLUSH_POLICY
[239]
Power class for 52MHz, DDR at 3.6V
PWR_CL_DDR_52_360
[238]
Power class for 52MHz, DDR at 1.95V
PWR_CL_DDR_52_195
[237]
Power class for 200MHz,
at VCCQ =1.95V, VCC = 3.6V
PWR_CL_200_195
[236]
Power class for 200MHz,
at VCCQ=1.3V, VCC = 3.6V
[235]
Minimum Write Performance for 8bit
at 52MHz in DDR mode
Minimum Read Performance for 8bit
[234]
at 52MHz in DDR mode
Reserved
[232]
TRIM Multiplier
[231]
Secure Feature support
[230]
Secure Erase Multiplier
[229]
Secure TRIM Multiplier
[228]
Boot information
[227]
Reserved
[226]
Boot partition size
[225]
Access size
[224]
High-capacity erase unit size
[223]
High-capacity erase timeout
[222]
Value
1
R
0x01
1
R
0x66
1
R
0xBB
1
R
0xBB
PWR_CL_200_130
1
R
0xBB
MIN_PERF_DDR_W_8_52
1
R
0x00
MIN_PERF_DDR_R_8_52
1
R
0x64
-
1
-
0x00
TRIM_MULT
1
R
0x01
SEC_FEATURE_SUPPORT
1
R
0x55
SEC_ERASE_MULT
1
R
0xF3
SEC_TRIM_MULT
1
R
0xF7
BOOT_INFO
1
R
0x07
-
1
R
0x00
1
R
0x20
ACC_SIZE
1
R
0x08
HC_ERASE_GRP_SIZE
1
R
0x08
ERASE_TIMEOUT_MULT
1
R
0x11
Reliable write sector count
REL_WR_SEC_C
1
R
0x01
[221]
High-capacity write protect group size
HC_WP_GRP_SIZE
1
R
0x01
[220]
Sleep current (VCC)
S_C_VCC
1
R
0x07
[219]
Sleep current (VCCQ)
S_C_VCCQ
1
R
0x09
[218]
Production state awareness timeout
PRODUCTION_STATE
_AWARENESS_TIMEOUT
1
R
0x0A
[217]
Sleep/awake timeout
S_A_TIMEOUT
1
R
0x14
[216]
Sleep Notification Timeout
SLEEP_NOTIFICATION_TIME
1
R
0x10
[215:212]
Sector Count
SEC_COUNT
4
R
0x01D5A000
[211]
Sector Write Protection Information
SECURE_WP_INFO
1
R
0x01
[210]
Minimum Write Performance for 8bit
at 52MHz
MIN_PERF_W_8_52
1
R
0x00
[209]
Minimum Read Performance 8bit
at 52MHz
MIN_PERF_R_8_52
1
R
0x78
[208]
Minimum Write Performance for 8bit
at 26MHz, for 4bit at 52MHz
MIN_PERF_W_8_26_4_52
1
R
0x00
[207]
Minimum Read Performance for 8 bit
at 26MHz, for 4bit at 52MHz
MIN_PERF_R_8_26_4_52
1
R
0x46
[206]
Minimum Write Performance for 4bit
at 26MHz
MIN_PERF_W_4_26
1
R
0x00
[205]
Minimum Read Performance for 4bit
at 26MHz
MIN_PERF_R_4_26
1
R
0x1E
Pre
BOOT_SIZE_MULTI
lim
[233]
Cell Type
ina
r
[240]
Size
(Bytes)
y
CSD-slice
© 2019 Toshiba Memory Corporation
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January 31st, 2019
THGBMJG7C1LBAIL
Name
Field
[204]
Reserved
-
[203]
Power class for 26MHz at 3.6V
PWR_CL_26_360
[202]
Power class for 52MHz at 3.6V
PWR_CL_52_360
[201]
Power class for 26MHz at 1.95V
PWR_CL_26_195
[200]
Power class for 52MHz at 1.95V
PWR_CL_52_195
[199]
Partition switching timing
[198]
Out-of-interrupt busy timing
[197]
I/O Driver Strength
[196]
Device Type
[195]
Reserved
[194]
CSD structure version
[193]
Reserved
[192]
Extended CSD revision
[191]
Command Set
[190]
Reserved
[189]
Command set revision
[188]
Reserved
Cell Type
Value
1
-
0x00
1
R
0x55
1
R
0x55
1
R
0xBB
1
R
0xBB
PARTITION_SWITCH_TIME
1
R
0x0A
OUT_OF_INTERRUPT_TIME
1
R
0x0A
DRIVER_STRENGTH
1
R
0x1F
DEVICE_TYPE
1
R
0x57
-
1
-
0x00
CSD_STRUCTURE
1
R
0x02
-
1
-
0x00
ina
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Note 1
Size
(Bytes)
y
CSD-slice
EXT_CSD_REV
1
R
0x08
CMD_SET
1
R/W/E_P
0x00
-
1
-
0x00
CMD_SET_REV
1
R
0x00
-
1
-
0x00
POWER_CLASS
1
R/W/E_P
0x00
-
1
-
0x00
HS_TIMING
1
R/W/E_P
0x00
Power class
[186]
Reserved
[185]
High-speed interface timing
[184]
Strobe Support
STROBE_SUPPORT
1
R
0x01
[183]
Bus width mode
BUS_WIDTH
1
W/E_P
0x00
[182]
Reserved
-
1
-
0x00
[181]
Erased memory content
ERASED_MEM_CONT
1
R
0x00
[180]
Reserved
-
1
-
0x00
[179]
Partition configuration
PARTITION_CONFIG
1
R/W/E &
R/W/E_P
0x00
[178]
Boot config protection
BOOT_CONFIG_PROT
1
R/W &
R/W/C_P
0x00
[177]
Boot bus Conditions
BOOT_BUS_CONDITIONS
1
R/W/E
0x00
[176]
Reserved
-
1
-
0x00
[175]
High-density erase group definition
ERASE_GROUP_DEF
1
R/W/E_P
0x00
[174]
Boot write protection status registers
BOOT_WP_STATUS
1
R
0x00
R/W &
R/W/C_P
0x00
Pre
lim
[187]
[173]
Boot area write protection register
BOOT_WP
1
[172]
Reserved
-
1
-
0x00
0x00
[171]
User area write protection register
USER_WP
1
R/W,
R/W/C_P &
R/W/E_P
[170]
Reserved
-
1
-
0x00
[169]
FW configuration
FW_CONFIG
1
R/W
0x00
© 2019 Toshiba Memory Corporation
9
January 31st, 2019
THGBMJG7C1LBAIL
Name
Field
RPMB Size
RPMB_SIZE_MULT
[167]
Write reliability setting register
WR_REL_SET
[166]
Write reliability parameter register
WR_REL_PARAM
[165]
Start Sanitize operation
SANITIZE_START
[164]
Manually start
BKOPS_START
background operations
Cell Type
Value
1
R
0x20
1
R/W
0x1F
1
R
0x15
1
W/E_P
0x00
1
W/E_P
0x00
0x00
ina
r
[168]
Size
(Bytes)
y
CSD-slice
[163]
Enable background operations handshake
BKOPS_EN
1
R/W
&
R/W/E
[162]
H/W reset function
RST_n_FUNCTION
1
R/W
0x00
[161]
HPI management
HPI_MGMT
1
R/W/E_P
0x00
[160]
Partitioning Support
PARTITIONING_SUPPORT
1
R
0x07
[159:157]
Max Enhanced Area Size Note 2
MAX_ENH_SIZE_MULT
3
R
0x000757
[156]
Partitions attribute
PARTITIONS_ATTRIBUTE
1
R/W
0x00
[155]
Partitioning Setting
PARTITION_SETTING_COMPLET
ED
1
R/W
0x00
[154:143]
General Purpose Partition Size Note 3
GP_SIZE_MULT
12
R/W
0x00
[142:140]
Enhanced User Data Area Size Note 4
ENH_SIZE_MULT
3
R/W
0x00
[139:136]
Enhanced User Data Start Address
ENH_START_ADDR
4
R/W
0x00
[135]
Reserved
-
1
-
0x00
[134]
Bad Block Management mode
1
R/W
0x00
1
R/W/E
0x00
lim
SEC_BAD_BLK_MGMNT
Production state awareness Note 6
[132]
Package Case Temperature is controlled Note 1
TCASE_SUPPORT
1
W/E_P
0x00
[131]
Periodic Wake-up Note 1
PERIODIC_WAKEUP
1
R/W/E
0x00
[130]
Program CID/CSD in DDR mode support
PROGRAM_CID_CSD_DDR_SUP
PORT
1
R
0x01
[129:128]
Reserved
-
2
-
All ‘0’
[127:64]
Vendor Specific Fields
VENDOR_SPECIFIC_FIELD
64
-
-
[63]
Native sector size
NATIVE_SECTOR_SIZE
1
R
0x01
[62]
Sector size emulation
USE_NATIVE_SECTOR
1
R/W
0x00
[61]
Sector size
DATA_SECTOR_SIZE
1
R
0x00
[60]
1st initialization
after disabling sector size emulation
INI_TIMEOUT_EMU
1
R
0x0A
[59]
Class 6 commands control
CLASS_6_CTRL
1
R/W/E_P
0x00
[58]
Number of addressed group to be Released
DYNCAP_NEEDED
1
R
0x00
[57:56]
Exception events control
EXCEPTION_EVENTS_CTRL
2
R/W/E_P
0x00
[55:54]
Exception events status
EXCEPTION_EVENTS_STATUS
2
R
All ‘0’
[53:52]
Extended partitions attribute Note 1
EXT_PARTITIONS_ATTRIBUTE
2
R/W
0x00
[51:37]
Context configuration
CONTEXT_CONF
15
R/W/E_P
0x00
[36]
Packed command status
PACKED_COMMAND_STATUS
1
R
0x00
[35]
Packed command failure index
PACKED_FAILURE_INDEX
1
R
0x00
POWER_OFF_NOTIFICATION
1
R/W/E_P
0x00
CACHE_CTRL
1
R/W/E_P
0x00
Pre
[133]
PRODUCTION_STATE
_AWARENESS
Note 5
[34]
Power Off Notification
[33]
Control to turn the Cache ON/OFF
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THGBMJG7C1LBAIL
Size
(Bytes)
Cell Type
Value
1
W/E_P
0x00
1
R/W
0x00
1
R/W/E_P
0x00
1
W/E_P
0x00(not support.
Return switch error)
2
-
All ‘0’
FFU_STATUS
1
R
0x00
PRE_LOADING_DATA_SIZE
4
R/W/E_P
0x00757000
MAX_PRE_LOADING_DATA
_SIZE
4
R
0x00757000
Name
Field
Flushing of the cache
FLUSH_CACHE
[31]
Control to turn the Barrier ON/OFF
BARRIER_CTRL
[30]
Mode config
MODE_CONFIG
[29]
Mode operation codes
MODE_OPERATION_CODES
[28:27]
Reserved
-
[26]
FFU status
Note 6
ina
r
[32]
y
CSD-slice
[25:22]
Pre loading data size
[21:18]
Max pre loading data size
[17]
Product state awareness enablement Note 6
PRODUCT_STATE
_AWARENESS_ENABLEMENT
1
R/W/E
&R
0x03
[16]
Secure Removal Type
SECURE_REMOVAL_TYPE
1
R/W & R
0x39
[15]
Command Queue Mode Enable
CMDQ_MODE_EN
1
R/W/E_P
0x00
[14:0]
Reserved
-
15
-
All ‘0’
Note 1: Although these fields can be re-written by host, TOSHIBA Memory e-MMC does not support.
Note 2: Max Enhanced Area Size (MAX_ENH_SIZE_MULT [159:157]) has to be calculated by following formula.
Max Enhanced Area = MAX_ENH_SIZE_MULT x HC_WP_GRP_SIZE x HC_ERASE_GRP_SIZE x 512kBytes
4
∑ Enhanced general partition size(i) + Enhanced user data area ≤ Max enhanced area
lim
i=1
Note 3: General Purpose Partition Size (GP_SIZE_MULT_GP0 - GP_SIZE_MULT_GP3 [154:143]) has to be calculated
by following formula.
General_Purpose_Partition_X Size = (GP_SIZE_MULT_X_2 x 216 + GP_SIZE_MULT_X_1 x 28
+ GP_SIZE_MULT_X_0 x 20 ) x HC_WP_GRP_SIZE
x HC_ERASE_GRP_SIZE x 512kBytes
Note 4: Enhanced User Data Area Size (ENH_SIZE_MULT [142:140]) has to be calculated by following formula.
Enhanced User Data Area x Size = (ENH_SIZE_MULT_2 x 216 + ENH_SIZE_MULT_1 x 28
+ ENH_SIZE_MULT_0 x 20 ) x HC_WP_GRP_SIZE
x HC_ERASE_GRP_SIZE x 512kBytes
Pre
Note 5: Toshiba Memory recommends to issue the Power Off Notification before turning off the device, especially when
cache is on or AUTO_EN(BKOPS_EN[163]:bit1) is set to ‘1b’.
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THGBMJG7C1LBAIL
y
Note 6: - Pre loading data size = PRE_LOADING_DATA_SIZE x Sector Size
Pre-loading data size should be multiple of 4KB and the pre-loading data should be written by multiple of 4KB
chunk size, aligned with 4KB address. This is because the valid data size will be treated as 4KB when host
writes data less than 4KB.
- If the host continues to write data in Normal state (after it wrote PRE_LOADING_DATA_SIZE amount
of data) and before soldering, the pre-loading data might be corrupted after soldering.
Pre
lim
ina
r
- If a power cycle is occurred during the data transfer, the amount of data written to device is not clear.
Therefore in this case, host should erase the entire pre-loaded data and set again
PRE_LOADING_DATA_SIZE[25:22], PRODUCTION_STATE_AWARENESS[133], and
PRODUCT_STATE_AWARENESS_ENABLEMENT[17].
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ELECTRICAL CHARACTERISTICS
y
DC Characteristics
Absolute Maximum Ratings
Parameter
Supply voltage 1
Supply voltage 2
Voltage Input
General
Parameter
ina
r
The absolute maximum ratings of a semiconductor device are a set of specified parameter values, which must
not be exceeded during operation, even for an instant.
If any of these rating would be exceeded during operation, the device electrical characteristics may be irreparably
altered and the reliability and lifetime of the device can no longer be guaranteed. Moreover, these operations with
exceeded ratings may cause break down, damage, and/or degradation to any other equipment. Applications using
the device should be designed such that each maximum rating will never be exceeded in any operating conditions.
Before using, creating, and/or producing designs, refer to and comply with the precautions and conditions set forth
in this document.
Symbol
Test Conditions
Min
Max
Unit
VCC
-
-0.5
4.1
V
VCCQ
-
-0.5
4.1
V
VIO
-
-0.5
VCCQ+0.5(≤4.1)
V
Symbol
Test Conditions
Min
Max
Unit
-
-
-0.5
VCCQ+0.5
V
Input Leakage Current (before initialization sequence Note 1
and/or the internal pull up resistors connected)
-
-
-100
100
μA
Input Leakage Current (after initialization sequence and the
internal pull up resistors disconnected)
-
-
-2
2
μA
Output Leakage Current (before initialization sequence)
-
-
-100
100
μA
Output Leakage Current (after initialization sequence)
-
-
-2
2
μA
Peak voltage on all lines
All Outputs
lim
All Inputs
Note 1: Initialization sequence is defined in Power-Up chapter of JEDEC/MMCA Standard
Power Supply Voltage
Parameter
Pre
Supply voltage 1
Supply voltage 2
Symbol
Test Conditions
Min
Max
Unit
VCC
-
2.7
3.6
V
1.7
1.95
V
VCCQ
2.7
3.6
V
Note 1: Once the power supply VCC or VCCQ falls below the minimum guaranteed voltage (for example, upon sudden power fail),
the voltage level of VCC or VCCQ shall be kept less than 0.5 V for at least 1ms before it goes beyond 0.5 V again.
Note 2: The host and device I/O power (VCCQ) shall be provided from same power supply.
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THGBMJG7C1LBAIL
Supply Current
Symbol
Min
Interleave
Operation
Mode
VCCQ
Icc
Iccq
Icc
1.8V
95
15
3.3V
110
15
Operation
(RMS)
Non Interleave
1.8V
115
20
3.3V
140
20
DDR
HS200
1.8V
170
35
mA
HS400
1.8V
215
40
mA
1.8V
60
40
3.3V
65
40
1.8V
65
45
3.3V
70
45
HS200
1.8V
75
55
mA
HS400
1.8V
80
55
mA
SDR
IWOP
Non Interleave
DDR
mA
mA
Pre
lim
Write
mA
mA
ina
r
IROP
Unit
Iccq
SDR
Read
Max
y
Parameter
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THGBMJG7C1LBAIL
Internal resistance and Device capacitance
Single device capacitance
Internal pull up resistance DAT1 – DAT7
Symbol
Test Conditions
CDEVICE
－
RINT
－
V
VCCQ
Input
high level
VOH
VIH
Max
Unit
－
6
pF
10
150
kΩ
ina
r
Bus Signal Levels
Min
y
Parameter
Output
high level
undefined
VIL
Input
low level
VOL
VSS
Output
low level
t
Open-Drain Mode Bus Signal Level
Parameter
Min
Max
Unit
VOH
VCCQ - 0.2
V
Note 1
VOL
0.3
V
IOL = 2 mA
lim
Output HIGH voltage
Symbol
Output LOW voltage
Conditions
Note 1: Because VOH depends on external resistance value (including outside the package), this value does not apply as device
specification. Host is responsible to choose the external pull-up and open drain resistance value to meet VOH Min value.
Push-Pull Mode Bus Signal Level (High-Voltage)
Symbol
Min
Max
Unit
Output HIGH voltage
VOH
0.75 * VCCQ
V
IOH = -100 μA @ VCCQ min
Output LOW voltage
VOL
0.125 * VCCQ
V
IOL = 100 μA @ VCCQ min
Input HIGH voltage
VIH
0.625 * VCCQ
VCCQ + 0.3
V
Input LOW voltage
VIL
VSS - 0.3
0.25 * VCCQ
V
Pre
Parameter
Conditions
Push-Pull Mode Bus Signal Level (Dual-Voltage)
Parameter
Symbol
Min
Max
Unit
Output HIGH voltage
VOH
VCCQ - 0.45
V
IOH = -2mA
Output LOW voltage
VOL
0.45
V
IOL = 2mA
Input HIGH voltage
VIH
0.65 * VCCQ
VCCQ + 0.3
V
Input LOW voltage
VIL
VSS - 0.3
0.35 * VCCQ
V
© 2019 Toshiba Memory Corporation
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Conditions
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THGBMJG7C1LBAIL
Driver Types Definition
y
In JEDEC, Driver Type-0 is defined as mandatory for e-MMC HS200&HS400 Device. While four additional Driver
Types (1, 2, 3 and 4) are defined as optional, to allow the support of wider Host loads. The Host may select the most
appropriate Driver Type of the Device (if supported) to achieve optimal signal integrity performance.
ina
r
Driver Type-0 is targeted for transmission line, based distributed system with 50Ω nominal line impedance.
Therefore, it is defined as 50Ω nominal driver. The nominal line impedance should be kept as 50Ω even if Driver Type
would be changed.
For HS200, when tested with CL = 15pF Driver Type-0 shall meet all AC characteristics and HS200 Device output
timing requirements. The test circuit defined in section 10.5.4.3 of JEDEC/MMCA Standard 5.1 is used for testing of
Driver Type-0.
For HS400, when tested with the reference load defined in page 27 HS400 reference load figure, Driver Type-0 or
Driver Type-1 or Driver Type-4 shall meet all AC characteristics and HS400 Device output timing requirements.
Driver
Type
TOSHIBA
e-MMC
Nominal Impedance
(Driver strength)
Approximated driving capability
compared to Type-0
0
Supported
50 Ω (18mA)
x1
1
Supported
33 Ω (27mA)
x1.5
2
Supported
66 Ω (14mA)
x0.75
3
Supported
100 Ω (9mA)
x0.5
4
Supported
40 Ω (23mA)
x1.2
Remark
Default Driver Type
Recommendation at HS400 under the
condition of JEDEC standard
reference load.
Recommendation at HS400 under the
condition of JEDEC standard
reference load.
lim
Note: Nominal impedance is defined by I-V characteristics of output driver at 0.9V when VCCQ = 1.8V.
Pre
*The most suitable setting for user’s operating environment should be selected.
At HS400, Toshiba Memory recommends Driver Type-1 and Type-4. This is because they meet all AC
characteristics and Device output timing requirements under the condition of JEDEC standard reference load.
© 2019 Toshiba Memory Corporation
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THGBMJG7C1LBAIL
Bus Timing
tWH
tISU
Data
50% VCCQ
tTLH
max(VIL)
ina
r
tIH
Input
min(VIH)
tWL
50% VCCQ
CLK
y
tPP
tTHL
Invalid
min(VIH)
Data
max(VIL)
tOSU
tODLY
tOH
min(VOH)
Invalid
Data
Output
Data
max(VOL)
Data must always be sampled on the rising edge of the clock
Device Interface Timings (High-speed interface timing)
Parameter
Clock CLK Note 1
Symbol
Min
Max
Unit
Remark
fpp
0
52 Note 3
MHz
CL ≤ 30pF
Tolerance: +100kHz
Clock frequency Identification Mode (OD)
fOD
0
400
kHz
Tolerance: +20kHz
Clock high time
tWH
6.5
ns
CL ≤ 30pF
tWL
6.5
ns
CL ≤ 30pF
Clock rise time Note 4
tTLH
3
ns
CL ≤ 30pF
Clock fall time
tTHL
3
ns
CL ≤ 30pF
Input set-up time
tISU
3
ns
CL ≤ 30pF
Input hold time
tIH
3
ns
CL ≤ 30pF
tODLY
13.7
ns
CL ≤ 30pF
tOH
2.5
ns
CL ≤ 30pF
trise
3
ns
CL ≤ 30pF
tfall
3
ns
CL ≤ 30pF
Clock low time
lim
Clock frequency Data Transfer Mode (PP) Note 2
Inputs CMD, DAT (referenced to CLK)
Outputs CMD, DAT (referenced to CLK)
Pre
Output Delay time during Data Transfer
Output hold time
Signal rise time
Note 5
Signal fall time
Note 1: CLK timing is measured at 50% of VCCQ.
Note 2: This product shall support the full frequency range from 0 MHz - 26 MHz, or 0 MHz - 52 MHz.
Note 3: Device can operate as high-speed interface timing at 26MHz clock frequency.
Note 4: CLK rise and fall times are measured by min (VIH) and max (VIL).
Note 5: Inputs CMD, DAT rise and fall times area measured by min (VIH) and max (VIL), and outputs CMD, DAT rise and fall times
are measured by min (VOH) and max (VOL).
© 2019 Toshiba Memory Corporation
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Device Interface Timings (Backward-compatible interface timing)
Symbol
Min
Max
Clock frequency Data Transfer Mode (PP) Note 3
fpp
0
26
MHz
Clock frequency Identification Mode (OD)
fOD
0
400
kHz
Clock high time
tWH
10
ns
Clock rise time Note 4
Clock fall time
Inputs CMD,DAT (referenced to CLK)
Input set-up time
Input hold time
Outputs CMD,DAT (referenced to CLK)
Output set-up time Note 5
Output hold time Note 5
Remark Note 1
CL ≤ 30pF
CL ≤ 30pF
ina
r
Clock CLK Note 2
Clock low time
Unit
y
Parameter
tWL
10
ns
CL ≤ 30pF
tTLH
10
ns
CL ≤ 30pF
tTHL
10
ns
CL ≤ 30pF
tISU
3
ns
CL ≤ 30pF
tIH
3
ns
CL ≤ 30pF
tOSU
11.7
ns
CL ≤ 30pF
tOH
8.3
ns
CL ≤ 30pF
lim
Note 1: The e-MMC must always start with the backward-compatible interface timing. The timing mode can be switched to
high-speed interface timing by the host sending the SWITCH command (CMD6) with the argument for high-speed
interface select.
Note 2: CLK timing is measured at 50% of VCCQ.
Note 3: For compatibility with e-MMCs that support the v4.2 standard or earlier, host should not use >26MHz before switching to
high-speed interface timing.
Note 4: CLK rise and fall times are measured by min (VIH) and max (VIL).
Note 5: tOSU and tOH are defined as values from clock rising edge. However, the e-MMC device will utilize clock falling edge to
output data in backward compatibility mode. Therefore, it is recommended for hosts either to set tWL value as long as
possible within the range which will not go over tCK - tOH(min) in the system or to use slow clock frequency, so that host
could have data set up margin for the device.
Toshiba e-MMC device utilize clock falling edge to output data in backward compatibility mode.
Host should optimize the timing in order to have data set up margin as follows.
tWL
Pre
CLK
tODLY
Output
tOS
tOH
Invalid
Data
tOSU (min) = tWL(min) Figure 2
© 2019 Toshiba Memory Corporation
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tODLY(max 8ns)
Output timing
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THGBMJG7C1LBAIL
Bus Timing for DAT signals for during 2x data rate operation
y
These timings applies to the DAT[7:0] signals only when the device is configured for dual data mode operation. In
this dual data mode, the DAT signals operates synchronously of both the rising and the falling edges of CLK. The
CMD signal still operates synchronously of the rising edge of CLK and therefore complies with the bus timing
specified in High-speed interface timing or Backward-compatible interface timing.
CLK
ina
r
tPP
50% VCCQ
50% VCCQ
tIHddr
tISUddr
min(VIH)
max(VIL)
tIHddr
tISUddr
min(VIH)
Input
DATA
DATA
DATA
Invalid
max(VIL)
tODLYddr(max)
tODLYddr(max)
tODLYddr(min)
tODLYddr(min)
DATA
DATA
min(VOH)
DATA
lim
Output
Invalid
max(VOL)
In DDR mode data on DAT[7:0] lines are sampled on both edges of the clock
(not applicable for CMD line).
High-speed dual data rate interface timings
Parameter
Min
Max
Unit
Remark
45
55
%
Includes jitter, phase noise
tTLH
3
ns
CL ≤ 30pF
tTHL
3
ns
CL ≤ 30pF
Input set-up time
tISUddr
3
ns
CL ≤ 20pF
Input hold time
tIHddr
3
ns
CL ≤ 20pF
tODLY
13.7
ns
CL ≤ 20pF
Output hold time
tOH
2.5
ns
CL ≤ 20pF
Signal rise time
tRISE
3
ns
CL ≤ 20pF
Signal fall time
tFALL
3
ns
CL ≤ 20pF
Input CLK Note 1
Clock duty cycle
Clock rise time
Pre
Clock fall time
Symbol
Input CMD (referenced to CLK-SDR mode)
Output CMD (referenced to CLK-SDR mode)
Output delay time during data transfer
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Symbol
Min
Max
Input set-up time
tISUddr
2.5
ns
CL ≤ 20pF
Input hold time
tIHddr
2.5
ns
CL ≤ 20pF
Input DAT (referenced to CLK-DDR mode)
Output DAT (referenced to CLK-DDR mode)
Signal rise time (all signals) Note 2
Signal fall time (all signals)
Remark
tODLYddr
1.5
7
ns
CL ≤ 20pF
tRISE
2
ns
CL ≤ 20pF
tFALL
2
ns
CL ≤ 20pF
ina
r
Output delay time during data transfer
Unit
y
Parameter
Pre
lim
Note 1: CLK timing is measured at 50% of VCCQ.
Note 2: Inputs DAT rise and fall times are measured by min (VIH) and max (VIL), and outputs DAT rise and fall times are measured by min
(VOH) and max (VOL).
© 2019 Toshiba Memory Corporation
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THGBMJG7C1LBAIL
Bus Timing Specification in HS200 mode
y
HS200 Clock Timing
Host CLK Timing in HS200 mode shall conform to the timing specified in following figure and Table. CLK input shall
satisfy the clock timing over all possible operation and environment conditions. CLK input parameters should be
measured while CMD and DAT lines are stable high or low, as close as possible to the Device. The maximum
frequency of HS200 is 200MHz. Hosts can use any frequency up to the maximum that HS200 mode allows.
VIH
CLOCK
INPUT
VT
VIL
VSS
tTLH
ina
r
tPERIOD
VCCQ
tTHL
Note 1: VIH denote VIH(min.) and VIL denotes VIL(max.).
Note 2: VT = 50% of VCCQ, indicates clock reference point for timing measurements.
Min
Max
tPERIOD
5
tTLH, tTHL
0.2 * tPERIOD
Duty Cycle
30
70
Unit
Remark
ns
200MHz (max.), between rising edges
ns
tTLH, tTHL < 1ns (max.) at 200MHz, CDEVICE=6pF,
The absolute maximum value of tTLH, tTHL is 10ns regardless of
clock frequency.
%
lim
Symbol
HS200 Device Input Timing
VCCQ
CLOCK
INPUT
tPERIOD
VT
VSS
tIH
tISU
VCCQ
VIH
VIH
VALID
WINDOW
VIL
Pre
CMD.DAT[7-0]
INPUT
VIL
VSS
Note 1: tISU and tIH are measured at VIL(max) and VIH(min).
Note 2: VIH denote VIH(min) and VIL denotes VIL(max).
Symbol
Min
Max
Unit
tISU
1.40
ns
CDEVICE ≤ 6pF
tIH
0.8
ns
CDEVICE ≤ 6pF
© 2019 Toshiba Memory Corporation
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Remark
January 31st, 2019
THGBMJG7C1LBAIL
HS200 Device Output Timing
y
tPH parameter is defined to allow device output delay to be longer than tPERIOD. After initialization, the tPH may have
random phase relation to the clock. The Host is responsible to find the optimal sampling point for the Device outputs,
while switching to the HS200 mode.
While setting the sampling point of data, a long term drift, which mainly depends on temperature drift, should be
considered. The temperature drift is expressed by ΔTPH. Output valid data window (tVW) is available regardless of the
drift (ΔTPH) but position of data window varies by the drift.
CLOCK
INPUT
VT
VSS
ina
r
tPERIOD
VCCQ
tPH
tVW
VCCQ
VOH
VOH
CMD.DAT[7-0]
OUTPUT
VOL
VALID
WINDOW
VOL
VSS
Note: VOH denotes VOH(min) and VOL denotes VOL(max).
tPH
ΔTPH
tVW
Min
Max
Remark Note 1
Unit
UI
Device output momentary phase from CLK input to CMD
or DAT lines output.
Does not include a long term temperature drift.
ps
Delay variation due to temperature change after tuning.
Total allowable shift of output valid window (tVW ) from last
system Tuning procedure.
ΔTPH is 2600ps for ΔT from -25 °C to 125 °C during
operation.
UI
tVW =2.88ns at 200MHz
Using test circuit in following figure including skew
among CMD and DAT lines created by the Device.
Host path may add Signal Integrity induced noise, skews,
etc. Expected tVW at Host input is larger than 0.475UI.
lim
Symbol
0
2
-350
(ΔT = -20 °C)
+1550
(ΔT = 90 °C )
0.575
Note 1: Unit Interval (UI) is one bit nominal time. For example, UI=5ns at 200 MHz.
Pre
Meas. Location
Driver
CL=15pF
Note 1: CL is total equivalent lumped capacitance for each Driver.
Note 2: CL incorporates device die load, device package load and equivalent lumped load external to the device.
Note 3: In distributed transmission lines only part of the line capacitance considered as load for the Driver.
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ΔTPH = -350ps
ΔTPH = 1550ps
Sampling point
VALID
WINDOW
VALID
WINDOW
VALID
WINDOW
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Sampling point after tuning
y
ΔTPH consideration
Sampling point after junction heated to +90 ℃
Sampling point after junction cooled to -20 ℃
Pre
lim
Implementation Guide:
Host should design to avoid sampling errors that may be caused by the ΔTPH drift.
It is recommended to perform tuning procedure while Device wakes up, after sleep.
One simple way to overcome the ΔTPH drift is by reduction of operating frequency.
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Bus Timing Specification in HS400 mode
y
HS400 Input Timing
The CMD input timing for HS400 mode is the same as CMD input timing for HS200 mode.
tPERIOD
VCCQ
VSS
VCCQ
tCKDCD
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CLOCK
INPUT
VT
tCKMPW
tISU
VIH
DAT[7-0]
INPUT
tCKMPW
tCKDCD
tISU
tIH
tIH
VIH
VALID
WINDOW
VIL
VSS
VIL
VALID
WINDOW
Note: VT = 50% of VCCQ, indicates clock reference point for timing measurements.
Input CLK
Symbol
Min
Max
Unit
Remark
lim
Parameter
tPERIOD
5
ns
SR
1.125
V/ns
Duty cycle distortion
tCKDCD
0.0
0.3
ns
Allowable deviation from an ideal 50% duty cycle.
With respect to VT
Includes jitter, phase noise
Minimum pulse width
tCKMPW
2.2
ns
With respect to VT
tISUddr
0.4
ns
CDEVICE ≤ 6 pF
With respect to VIH /VIL
tIhddr
0.4
ns
CDEVICE ≤ 6 pF
With respect to VIH /VIL
SR
1.125
V/ns
With respect to VIH /VIL
Cycle time data transfer
mode
Slew rate
200 MHz(max), between rising edges
With respect to VT
With respect to VIH /VIL
Input DAT (referenced to CLK)
Input set-up time
Input hold time
Pre
Slew rate
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HS400 Device Output Timing
y
The Data Strobe is used to read data in HS400 mode. The Data Strobe is toggled only during data read or CRC status response.
tPERIOD
VCCQ
tDSDCD
tDSMPW
tDSMPW
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Data Strobe
VT
tDSDCD
VSS
tRQH
tRQ
VCCQ
VOH
DAT[7-0]
OUTPUT
VOH
VALID
WINDOW
VOL
VSS
VOL
VALID
WINDOW
Note: VT = 50% of VCCQ, indicates clock reference point for timing measurements.
Data Strobe
Symbol
Min
Max
Unit
Remark
lim
Parameter
tPERIOD
5
ns
SR
1.125
V/ns
Duty cycle distortion
tDSDCD
0.0
0.2
ns
Allowable deviation from the input CLK duty cycle
distortion(tCKDCD)
With respect to VT
Includes jitter, phase noise
Minimum pulse width
tDSMPW
2.0
ns
With respect to VT
tRQ
0.4
ns
With respect to VOH /VOL and HS400 reference load
tRQH
0.4
ns
With respect to VOH /VOL and HS400 reference load
SR
1.125
V/ns
With respect to VOH /VOL and HS400 reference load
Cycle time data transfer
mode
Slew rate
200 MHz(max), between rising edges
With respect to VT
With respect to VOH/VOL and HS400 reference load
Output DAT (referenced to Data Strobe)
Output skew
Output hold skew
Pre
Slew rate
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HS400 Device Command Output Timing
tPERIOD
VCCQ
y
The Data Strobe is used to response of any command in HS400 mode.
tDSDCD
VT
tDSMPW
tDSMPW
ina
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Data Strobe
tDSDCD
VSS
tRQ_CMD
VCCQ
VOH
CMD
OUTPUT
VOL
VSS
tRQH_CMD
VALID
WINDOW
Note: VT = 50% of VCCQ, indicates clock reference point for timing measurements.
Parameter
Symbol
Min
Max
Unit
tPERIOD
5
ns
Data Strobe
Cycle time data transfer
mode
Remark
200 MHz(max), between rising edges
With respect to VT
1.125
V/ns
Duty cycle distortion
tDSDCD
0.0
0.2
ns
Allowable deviation from the input CLK duty cycle
distortion(tCKDCD)
With respect to VT
Includes jitter, phase noise
Minimum pulse width
tDSMPW
2.0
ns
With respect to VT
tRQ_CMD
0.4
ns
With respect to VOH /VOL and HS400 reference load
Output hold skew (CMD)
tRQH_CMD
0.4
ns
With respect to VOH /VOL and HS400 reference load
Slew rate
SR
1.125
V/ns
With respect to VOH /VOL and HS400 reference load
lim
SR
Slew rate
With respect to VOH/VOL and HS400 reference load
CMD Response (referenced to Data Strobe)
Pre
Output skew (CMD)
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Driver
Measurement Point
Z0 = 50 Ohm
Td = 350 ps
CREFERENCE = 4pF
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Device I/O
Reference Load
Figure 3
HS400 Capacitance
HS400 reference load
The Data Strobe is used to read data in HS400 mode. The Data Strobe is toggled only during data read or CRC status response.
Parameter
Pull-up resistance for CMD
Pull-up resistance for DAT0-7
Pull-down resistance for Data Strobe
Internal pull up resistance DAT1-DAT7
Single Device capacitance
Symbol
Min
RCMD
Typ.
4.7
RDAT
10
RDS
10
Rint
10
CDEVICE
Max
Unit
100
Note 1
kΩ
100
Note 1
kΩ
100
Note 1
kΩ
150
kΩ
6
pF
Remark
Pre
lim
Note 1: Recommended maximum value is 50 kΩ for 1.8 V interface supply voltages.
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Overshoot/Undershoot Specification
VCCQ
Unit
y
1.70V - 1.95V
Maximum peak amplitude allowed for overshoot area.
(See Figure Overshoot/Undershoot definition)
Maximum area above VCCQ
(See Figure Overshoot/Undershoot definition)
Maximum area below VSSQ
(See Figure Overshoot/Undershoot definition)
Maximum Amplitude
V
CCQ
Volts
(V) VSSQ
0.9
V
Max
0.9
V
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Maximum peak amplitude allowed for undershoot area.
(See Figure Overshoot/Undershoot definition)
Max
Maximum Amplitude
Max
1.5
V-ns
Max
1.5
V-ns
Overshoot Area
Undershoot Area
Time (ns)
Figure 4
lim
H/W Reset Operation
Overshoot/Undershoot definition
CLK
*1
RST_n
tRSTW
tRSCA
tRSTH
Host can issue boot
initiation or CMD1
Pre
Device starts a reset sequence
at the RST_n rising edge
Do not care
*1: Device will detect the rising edge of RST_n signal to trigger internal reset sequence.
H/W Reset Timings
Symbol
tRSTW
Parameter
RST_n pulse width
tRSCA
RST_n to Command time
tRSTH
RST_n high period (interval time)
Min
Max
Unit
1
μs
200
Note 1
1
μs
μs
Note 1: 74 cycles of clock signal required before issuing CMD1 or CMD0 with argument 0xFFFFFFFA.
Note 2: During the device internal initialization sequence right after power on, device may not be able to detect RST_n signal,
because the device may not complete loading RST_n_ENABLE bits of the extended CSD register into the controller yet.
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Power-up sequence
y
Supply voltage
VCC min
VCCQ max
VCCQ min
0.5V
ina
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VCC max
time
VCCQ Power up time
tPRUL
VCC Power up time
VCCQ Power up time
tPRUH
tPRUL
Figure 5
Power-up parameter
Parameter
Symbol
Min
Max
Remark
tPRUH
5 μs
35 ms
-
tPRUL
5 μs
25 ms
-
lim
Supply power-up for 3.3V
Power up sequence
Pre
Supply power-up for 1.8V
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Functional restrictions
y
- Pre loading data size is limited to MAX_PRE_LOADING_DATA_SIZE[21-18] regardless of using Production
State Awareness function.
- MAX_PRE_LOADING_DATA_SIZE[21-18] value will change when host sets Enhanced User area Partition.
Reliability Guidance
-Write/Erase Endurance
ina
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This reliability guidance is intended to notify some guidance related to using raw NAND flash. Although random bit errors
may occur during use, it does not necessarily mean that a block is bad. Generally, a block should be marked as bad
when a program status failure or erase status failure is detected. The other failure modes may be recovered by a block
erase. ECC treatment for read data is mandatory due to the following Data Retention and Read Disturb failures.
Write/Erase endurance failures may occur in a cell, page, or block, and are detected by doing a status read after either
an auto program or auto block erase operation. The cumulative bad block count will increase along with the number of
write/erase cycles.
lim
-Data Retention
The data in memory may change after a certain amount of storage time. This is due to charge loss or charge gain. After
block erasure and reprogramming, the block may become usable again. Also write/erase endurance deteriorates data
retention capability. The figure below shows a generic trend of relationship between write/erase endurance and data
retention.
-Read Disturb
A read operation may disturb the data in memory. The data may change due to charge gain. Usually, bit errors occur on
other pages in the block, not the page being read. After a large number of read cycles (between block erases), a tiny
charge may build up and can cause a cell to be soft programmed to another state. After block erasure and
reprogramming, the block may become usable again.
Pre
Considering the above failure modes, Toshiba Memory recommends following usage:
- Please avoid any excessive iteration of resets and initialization sequences (Device identification mode) as far as
possible after power-on, which may result in read disturb failure. The resets include hardware resets and software
resets.
e.g.1) Iteration of the following command sequence, CMD0 - CMD1 --The assertion of CMD1 implies a count of internal read operation in Raw NAND.
CMD0: Reset command, CMD1: Send operation command
e.g.2) Iteration of the following commands, CMD30 and/or CMD31
CMD30: Send status of write protection bits, CMD31: Send type of write protection
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January 31st, 2019
- Released as preliminary revision
Pre
lim
ina
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Rev.0.1
y
Document Revision History
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RESTRICTIONS ON PRODUCT USE
y
Toshiba Memory Corporation and its subsidiaries and affiliates are collectively referred to as “TOSHIBA”.
Hardware, software and systems described in this document are collectively referred to as “Product”.
• TOSHIBA reserves the right to make changes to the information in this document and related Product without notice.
• This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with
TOSHIBA's written permission, reproduction is permissible only if reproduction is without alteration/omission.
ina
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• Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. Customers are
responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware,
software and systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of
human life, bodily injury or damage to property, including data loss or corruption. Before customers use the Product, create
designs including the Product, or incorporate the Product into their own applications, customers must also refer to and comply
with (a) the latest versions of all relevant TOSHIBA information, including without limitation, this document, the specifications,
the data sheets and application notes for Product and the precautions and conditions set forth in the " Reliability Information”
in Toshiba Memory Corporation’s website and (b) the instructions for the application with which the Product will be used with
or for. Customers are solely responsible for all aspects of their own product design or applications, including but not limited to
(a) determining the appropriateness of the use of this Product in such design or applications; (b) evaluating and determining
the applicability of any information contained in this document, or in charts, diagrams, programs, algorithms, sample
application circuits, or any other referenced documents; and (c) validating all operating parameters for such designs and
applications. TOSHIBA ASSUMES NO LIABILITY FOR CUSTOMERS' PRODUCT DESIGN OR APPLICATIONS.
• PRODUCT IS NEITHER INTENDED NOR WARRANTED FOR USE IN EQUIPMENTS OR SYSTEMS THAT REQUIRE
EXTRAORDINARILY HIGH LEVELS OF QUALITY AND/OR RELIABILITY, AND/OR A MALFUNCTION OR FAILURE OF
WHICH MAY CAUSE LOSS OF HUMAN LIFE, BODILY INJURY, SERIOUS PROPERTY DAMAGE AND/OR SERIOUS
PUBLIC IMPACT ("UNINTENDED USE"). Except for specific applications as expressly stated in this document, Unintended
Use includes, without limitation, equipment used in nuclear facilities, equipment used in the aerospace industry, lifesaving
and/or life supporting medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic
signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, and
devices related to power plant. IF YOU USE PRODUCT FOR UNINTENDED USE, TOSHIBA ASSUMES NO LIABILITY FOR
PRODUCT. For details, please contact your TOSHIBA sales representative or contact us via our website.
• Do not disassemble, analyze, reverse-engineer, alter, modify, translate or copy Product, whether in whole or in part.
• Product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited
under any applicable laws or regulations.
lim
• The information contained herein is presented only as guidance for Product use. No responsibility is assumed by TOSHIBA
for any infringement of patents or any other intellectual property rights of third parties that may result from the use of Product.
No license to any intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise.
• ABSENT A WRITTEN SIGNED AGREEMENT, EXCEPT AS PROVIDED IN THE RELEVANT TERMS AND CONDITIONS
OF SALE FOR PRODUCT, AND TO THE MAXIMUM EXTENT ALLOWABLE BY LAW, TOSHIBA (1) ASSUMES NO
LIABILITY WHATSOEVER, INCLUDING WITHOUT LIMITATION, INDIRECT, CONSEQUENTIAL, SPECIAL, OR
INCIDENTAL DAMAGES OR LOSS, INCLUDING WITHOUT LIMITATION, LOSS OF PROFITS, LOSS OF
OPPORTUNITIES, BUSINESS INTERRUPTION AND LOSS OF DATA, AND (2) DISCLAIMS ANY AND ALL EXPRESS OR
IMPLIED WARRANTIES AND CONDITIONS RELATED TO SALE, USE OF PRODUCT, OR INFORMATION, INCLUDING
WARRANTIES OR CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, ACCURACY OF
INFORMATION, OR NONINFRINGEMENT.
• Do not use or otherwise make available Product or related software or technology for any military purposes, including without
limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or
missile technology products (mass destruction weapons). Product and related software and technology may be controlled
under the applicable export laws and regulations including, without limitation, the Japanese Foreign Exchange and Foreign
Trade Law and the U.S. Export Administration Regulations. Export and re-export of Product or related software or technology
are strictly prohibited except in compliance with all applicable export laws and regulations.
Pre
• Please contact your TOSHIBA sales representative for details as to environmental matters such as the RoHS compatibility of
Product. Please use Product in compliance with all applicable laws and regulations that regulate the inclusion or use of
controlled substances, including without limitation, the EU RoHS Directive. TOSHIBA ASSUMES NO LIABILITY FOR
DAMAGES OR LOSSES OCCURRING AS A RESULT OF NONCOMPLIANCE WITH APPLICABLE LAWS AND
REGULATIONS.
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