ES7243

ES7243 High Performance Stereo Audio ADC FEATURES APPLICATIONS                High performance multi-bit delta-sigma audio ADC 102 dB signal to noise ratio -95 dB THD+N 24-bit, 8 to 200 kHz sampling frequency I2S/PCM master or slave serial data port Support TDM 256/384Fs, USB 12/24 MHz and other non standard audio system clocks Low power standby mode Mic Array Soundbar Audio Interface Digital TV A/V Receiver DVR NVR ORDERING INFORMATION ES7243 -40°C ~ +85°C QFN-20 BLOCK DIAGRAM TDMIN AINLP/AINLN AINRP/AINRN Multi-bit Delta-sigma Modulator DSP Clock Manager Sample Rate Detector MCLK Audio Data Interface 2 IC Interface CCLK CDATA AD0 AD1 1 SDOUT SCLK LRCK Everest Semiconductor Confidential ES7243 1. PIN OUT AND DESCRIPTION AINRP AD0 CDATA CCLK MCLK 16 17 18 19 20 VDDP TDMIN SDOUT GNDD VDDD 1 2 3 4 5 15 14 13 12 11 ES7243 AINRN REFP GNDA VDDA REFQ 10 9 8 7 6 AINLN AINLP AD1 LRCK SCLK Pin Name Pin number Input or Output Pin Description CCLK, CDATA AD0, AD1 MCLK SCLK LRCK TDMIN SDOUT AINLP, AINLN AINRP, AINRN VDDP VDDD/GNDD VDDA/GNDA REFP REFQ 19, 18 17,8 20 6 7 2 3 9, 10 16, 15 1 5, 4 12, 13 14 11 I/O I I I/O I/O I O I2C clock and data I2C addresses Master clock Serial data bit clock Serial data left and right channel frame clock TDM data in Serial data output I Analog left and right inputs I I I O O Power supply for the digital input and output Digital power supply Analog power supply Filtering capacitor connection Filtering capacitor connection Revision 8.1 2 January 2019 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES7243 2. TYPICAL APPLICATION CIRCUIT 0R AGND In the lay o ut, c h ip is treated as an an alo g d ev ice AGND AGND CPU/DSP IIS TD M IN 20 6 7 3 2 21 1uF VA * 12 * * GNDD AD0 AD1 CCLK CD ATA AINRP ES7243 M CLK SCLK LRCK SDOUT TD M IN PGND V D DA AGND RE FQ AGND 17 8 19 18 1uF 14 100nF 4 IIC 5 * V D DP * 100nF V D DD VD DD 1 VD DP 11 1uF RE FP GND (SY S) AINRN GNDA AINLP AINLN 16 AINRP 1uF 15 13 AINRN 1uF AGND 9 1uF 10 AINLP AINLN 1uF 100K AGND AGND Fo r th e b es t pe rfo rm an ce ,d ec o up lin g an d f ilterin g c ap ac ito r s s h o u ld b e loc ated as c lo s e to th e d evice p ac kag e as po s s ib le Ad d itio n al par allel ca pac ito rs (ty p ically 0 .1 μF ) c an b e us ed , larg er v alu e c ap ac ito r s (typ ic ally 1 0 μF ) w o u ld als o help * Revision 8.1 3 January 2019 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES7243 3. CLOCK MODES AND SAMPLING FREQUENCIES The device supports standard audio clocks (256Fs, 384Fs, 512Fs, etc), USB clocks (12/24 MHz), and some common non standard audio clocks (25 MHz, 26 MHz, etc). According to the serial audio data sampling frequency (Fs), the device can work in two speed modes: single speed mode or double speed mode. In single speed mode, Fs normally ranges from 8 kHz to 48 kHz, and in double speed mode, Fs normally range from 64 kHz to 96 kHz. The device can work either in master clock mode or slave clock mode. In slave mode, LRCK and SCLK are supplied externally, and LRCK and SCLK must be synchronously derived from the system clock with specific rates. In master mode, LRCK and SCLK are derived internally from device master clock. 4. MICRO-CONTROLLER CONFIGURATION INTERFACE The device supports standard I2C micro-controller configuration interface. External microcontroller can completely configure the device through writing to internal configuration registers. I2C interface is a bi-directional serial bus that uses a serial data line (CDATA) and a serial clock line (CCLK) for data transfer. The timing diagram for data transfer of this interface is given in Figure 1a and Figure 1b. Data are transmitted synchronously to CCLK clock on the CDATA line on a byte-by-byte basis. Each bit in a byte is sampled during CCLK high with MSB bit being transmitted firstly. Each transferred byte is followed by an acknowledge bit from receiver to pull the CDATA low. The transfer rate of this interface can be up to 400 kbps. A master controller initiates the transmission by sending a “start” signal, which is defined as a high-to-low transition at CDATA while CCLK is high. The first byte transferred is the slave address. It is a seven-bit chip address followed by a RW bit. The chip address must be 0010 0x, where x equals A AD0. The RW bit indicates the slave data transfer direction. Once an acknowledge bit is received, the data transfer starts to proceed on a byte-by-byte basis in the direction specified by the RW bit. The master can terminate the communication by generating a “stop” signal, which is defined as a low-to-high transition at CDATA while CCLK is high. In I2C interface mode, the registers can be written and read. The formats of “write” and “read” instructions are shown in Table 1 and Table 2. Please note that, to read data from a register, you must set R/W bit to 0 to access the register address and then set R/W to 1 to read data from the register. Table 1 Write Data to Register in I2C Interface Mode start Chip Address A AD0 Revision 8.1 R/W 0 ACK Register Address RAM ACK Data to be written DATA ACK 4 January 2019 Latest datasheet: www.everest-semi.com or info@everest-semi.com Stop Everest Semiconductor Confidential Chip Addr CDATA Write ACK bit 1 to 7 ES7243 Reg Addr ACK Write Data bit 1 to 8 ACK bit 1 to 8 CCLK START STOP Figure 1a I2C Write Timing Table 2 Read Data from Register in I2C Interface Mode Chip Address A AD0 Chip Address A AD0 Start Start Chip Addr CDATA R/W 0 R/W 1 Write ACK Reg Addr bit 1 to 7 Register Address RAM Data to be read Data ACK ACK ACK Chip Addr bit 1 to 8 ACK NACK Stop Read Data NO ACK Read ACK bit 1 to 8 bit 1 to 7 CCLK START STOP START Figure 1b I2C Read Timing 5. DIGITAL AUDIO INTERFACE The device provides many formats of serial audio data interface to the output from the ADC through LRCK, SCLK and SDOUT pins. These formats are I2S, left justified and DSP/PCM mode. ADC data is out at SDOUT on the falling edge of SCLK. The relationships of SDOUT (SDATA), SCLK and LRCK with these formats are shown through Figure 2 to Figure 5. The device supports up to 8-ch of TDM, please refer to user guide for detail description. 1 SCLK SDATA 1 2 1 SCLK 3 n-2 n-1 MSB n 1 LSB MSB 2 3 n-2 n-1 n LSB SCLK LRCK LEFT CHANNEL RIGHT CHANNEL Figure 2 I2S Serial Audio Data Format Up To 24-bit Revision 8.1 5 January 2019 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor SDATA 1 2 3 Confidential n-2 n-1 MSB n 1 LSB MSB 2 ES7243 3 n-2 n-1 n LSB SCLK LRCK RIGHT CHANNEL LEFT CHANNEL Figure 3 Left Justified Serial Audio Data Format Up To 24-bit Figure 4 DSP/PCM Mode A Figure 5 DSP/PCM Mode B 6. ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Continuous operation at or beyond these conditions may permanently damage the device. PARAMETER Analog Supply Voltage Level Digital Supply Voltage Level Analog Input Voltage Range Digital Input Voltage Range Operating Temperature Range Storage Temperature Revision 8.1 MIN -0.3V -0.3V GNDA-0.3V GNDD-0.3V -40C -65C MAX +3.6V +3.6V VDDA+0.3V VDDP+0.3V +85C +150C 6 January 2019 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES7243 RECOMMENDED OPERATING CONDITIONS PARAMETER VDDA VDDD VDDP MIN 3.0 3.0 1.6 TYP 3.3 3.3 3.3 MAX 3.6 3.6 3.6 UNIT V V V ADC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS Test conditions are as the following unless otherwise specify: VDDA=3.3V, VDDD=3.3V, AGND=0V, DGND=0V, Ambient temperature=25C, Fs=48 KHz, 96 KHz or 192 KHz, MCLK/LRCK=256. PARAMETER ADC Performance Signal to Noise ratio (A-weigh) THD+N Channel Separation (1KHz) Interchannel Gain Mismatch Gain Error Filter Frequency Response – Single Speed Passband Stopband Passband Ripple Stopband Attenuation Filter Frequency Response – Double Speed Passband Stopband Passband Ripple Stopband Attenuation Filter Frequency Response – Quad Speed Passband Stopband Passband Ripple Stopband Attenuation Analog Input Full Scale Input Level Input Impedance MIN TYP MAX UNIT 95 -98 95 102 -95 100 0.1 104 -90 105 dB dB dB dB % ±5 0 0.5465 0.4535 Fs Fs dB dB ±0.05 70 0 0.5833 0.4167 Fs Fs dB dB ±0.005 70 0 0.7917 0.2083 Fs Fs dB dB ±0.005 70 AVDD/3.3 8 (0 dB PGA) 6 (27 dB PGA) Vrms KΩ DC CHARACTERISTICS PARAMETER Normal Operation Mode VDDD=3.3V, VDDP=3.3V, VDDA=3.3V Power Down Mode VDDD=3.3V, VDDP=3.3V, VDDA=3.3V Digital Voltage Level Input High-level Voltage Revision 8.1 MIN 0.7*VDDP TYP MAX UNIT 14 mA 19 uA V 7 January 2019 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential Input Low-level Voltage Output High-level Voltage Output Low-level Voltage ES7243 0.5 V V V VDDP 0 SERIAL AUDIO PORT SWITCHING SPECIFICATIONS PARAMETER MCLK frequency MCLK duty cycle LRCK frequency LRCK duty cycle SCLK frequency SCLK pulse width low SCLK Pulse width high SCLK falling to LRCK edge SCLK falling to SDOUT valid Symbol MIN 40 40 TSCLKL TSCLKH TSLR TSDO 15 15 –10 11 MAX 51.2 60 200 60 26 10 UNIT MHz % KHz % MHz ns ns ns ns Figure 6 Serial Audio Port Timing I2C SWITCHING SPECIFICATIONS PARAMETER SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of SCL Fall Time SCL Revision 8.1 Symbol FSCL TTWID TTWSTH TTWCL TTWCH TTWSTS TTWDH TTWDS TTWR TTWF MIN MAX 400 1.3 0.6 1.3 0.4 0.6 900 100 300 300 UNIT KHz us us us us us ns ns ns ns 8 January 2019 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES7243 SDA TTWSTS TTWSTH TTWCL SCL TTWDH TTWID TTWDS TTWCH S TTWF TTWR P S Figure 7 I2C Timing Revision 8.1 9 January 2019 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES7243 7. PACKAGE Revision 8.1 10 January 2019 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES7243 8. CORPORATE INFORMATION Everest Semiconductor Co., Ltd. No. 1355 Jinjihu Drive, Suzhou Industrial Park, Jiangsu, P.R. China, Zip Code 215021 苏州工业园区金鸡湖大道 1355 号国际科技园, 邮编 215021 Email: info@everest-semi.com Revision 8.1 11 January 2019 Latest datasheet: www.everest-semi.com or info@everest-semi.com