AW5017DNR
2016 年 1 月
V1.2
AW5017:内置可调谐电容的 FM 低噪声放大器
特性
描述
无需耳机及拉杆天线,
通过复用 GSM 天线实现 FM
AW5017 是一款低噪声放大器,
无需耳机和拉杆天线,
信号接收
通过复用 GSM 天线实现 FM 信号接收。
内置一线可编程逻辑单元的可调谐电容阵列,有效
AW5017 内置 EN 管脚控制的一线可编程逻辑单元,
提升短天线在不同工作频段的天线效率
可控制 16 个台阶的可调谐电容阵列,有效提升短天
极低的噪声系数:1.2dB
线增益
标准 CMOS 工艺
AW5017 具有低噪声,高增益,高线性度的特性,典
1.8V 工作电压下高达 20dB 的增益
型值噪声系数 1.2dB,增益 21dB。
高线性度
AW5017 的电源电压和使能 EN 电压范围在 1.5V 到
EN 管脚支持一线可编程逻辑的 4bit 可调谐电容
工作电压:1.5V~3.6V
关机电流1
Kf
IIP3
Input 3rd-order intercept
point
IB P-1dB
In-Band
1dB-compression point
OOB P-1dB
Output-Of-Band
1dB- compression point
(NOTE 3)
Input/Output 50ohm
(NOTE 4)
Copyright © 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD
Page5 of 18
-9
dBm
-21
dBm
-2
dBm
AW5017DNR
Jan 2016
V1.2
Table 6 ELECTRICAL CHARACTERISTICS OF TUNABLE CAPACITOR
Test condition: TA=25 ℃, VCC=1.5~3.6V, EN=VCC, Rs=Ro=50 ohm,frequency=90 MHz for typical values
(unless otherwise noted).
PARAMETER
MIN
TYP
MAX
UNIT
Vcc
Supply Voltage
1.5
2.8
3.6
V
TH
EN High Level Duration Time
0.4
50
μs
TL
EN Low Level Duration Time
0.4
50
μs
150
500
μs
150
500
μs
(NOTE 5)
TLATCH
EN State Latch Time
TOFF
EN Off Delay Time
(NOTE 6)
n
Tunable Stage Number
16
Cmin
Minimum Tunable Capacitor
15
pF
Cmax
Maximum Tunable Capacitor
45
pF
Cstep
Minimum Stage
2
pF
NOTE1: Conditions out of those ranges listed in "absolute maximum ratings" may cause permanent damages
to the device. In spite of the limits above, functional operation conditions of the device should within the
ranges listed in "recommended operating conditions". Exposure to absolute-maximum-rated conditions for
prolonged periods may affect device reliability.
NOTE2: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. Test
method: MIL-STD-883G Method 3015.7
NOTE3: Measure IIP3 parameter through two tones of -40dBm/tone with the frequency of 97M and 98MHz
NOTE4: Input/Output are both 50-ohm; Input signal is composed of in-band 90-MHz signal and out-of-band
900MHz signal. Signal of 90-MHz is fixed to -40-dBm; signal of 900MHz varies and power level is measured
when power gain of 90MHz signal drops 1dB.
NOTE5: Latch mechanism is already designed inside. When pulse width of high-level is wider than state latch
time, chip will keep latch state inside unchanged and won’t accept any new pulses, until off state.
NOTE6: Latch mechanism is already designed inside. When EN is changed from high-level to low-level, state
inside will be changed to off after off delay time.
Pulse Number n
Tunable Capacitor State n
TOFF
TH TL
Figure 3 One-Line-Logic Timing Diagram
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V1.2
TYPICAL CHARACTERISTICS
Test condition: TA=25 ℃, VCC=1.8 V, EN=1.8 V, Rs=Ro=50 ohm,frequency=90 MHz for typical values
(unless otherwise noted).
Table 7 TABLE OF FIGURES
INDEX
FIGURE No.
S parameter
S11/S21/S12/S22
FIGURE 4/5/6/7
Noise Figure
NF
FIGURE 8
Stability Factor
Kf
FIGURE 9
P1dB Compression Point
P1dB(In-band/Out-of-Band)
FIGURE 10
Noise Figure
Cin
FIGURE 11
25
0
-1
20
S11(dB)
S21(dB)
-2
15
-3
-4
10
-5
5
-7
0
10
22
34
46
58
70
82
94
106
118
130
142
154
166
178
190
202
10
23
36
49
62
75
88
101
114
127
140
153
166
179
192
205
-6
Frequency(MHz)
Frequency(MHz)
Figure 5 Power Gain(S21)
Figure 4 Input Return Loss(S11)
0
-2
-4
-6
-8
-10
-12
-14
-16
-18
-20
0
-10
-30
-40
-50
10
23
36
49
62
75
88
101
114
127
140
153
166
179
192
205
-60
10
23
36
49
62
75
88
101
114
127
140
153
166
179
192
205
S12(dB)
S22(dB)
-20
Frequency(MHz)
Frequency(MHz)
Figure 6 Reverse Isolation(S12)
Figure 7 Output Return Loss(S22)
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V1.2
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
40
49
58
67
76
85
94
103
112
121
130
139
148
157
10
210
410
610
810
1,010
1,210
1,410
1,610
1,810
2,010
2,210
2,409
2,609
2,809
Stability Factor (Kf)
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
Frequency(MHz)
Frequency(MHz)
Figure 8 Noise Figure(NF)
Figure 9 Stability Factor(Kf)
Input Equivalent Capacitor(pF)
25
20
Power Gain(dB)
Noise Figure(dB)
Jan 2016
15
10
Out-Of-Band P1dB
In-Band P1dB
5
0
-50 -35 -24 -21 -18 -15 -8 -5
Input Power(dBm)
-2
Figure 10 P1dB(In-Band/Out-Of-Band)
50
45
40
35
30
25
20
15
10
5
0
0 1 2 3 4 5 6 7 8 9 101112131415
Pulse Number
Figure 11 Tunable Capacitor(Cin)
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Test condition: TA=25 ℃, VCC=2.8 V, EN=2.8 V, Rs=Ro=50 ohm,frequency=90 MHz for typical values
(unless otherwise noted).
Table 8 TABLE OF FIGURES
INDEX
FIGURE No.
S parameter
S11/S21/S12/S22
FIGURE 12/13/14/15
Noise Figure
NF
FIGURE 16
Stability Factor
Kf
FIGURE 17
P1dB Compression Point
P1dB(In-band/Out-of-Band)
FIGURE 18
Noise Figure
Cin
FIGURE 19
25
0
-1
20
-2
S11(dB)
S21(dB)
15
-3
-4
10
-5
5
-6
10
23
36
49
62
75
88
101
114
127
140
153
166
179
192
205
10
22
34
46
58
70
82
94
106
118
130
142
154
166
178
190
202
0
-7
Frequency(MHz)
Frequency(MHz)
Figure 13 Power Gain(S21)
Figure 12 Input Return Loss(S11)
0
0
-10
-5
-20
S12(dB)
-10
2
-30
-40
-15
-50
-20
-60
10
23
36
49
62
75
88
101
114
127
140
153
166
179
192
205
Frequency(MHz)
Figure 14 Reverse Isolation(S12)
10
23
36
49
62
75
88
101
114
127
140
153
166
179
192
205
-25
-70
Frequency(MHz)
Figure 15 Output Return Loss(S22)
Copyright © 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD
Page9 of 18
AW5017DNR
Jan 2016
13
12
11
10
9
8
7
6
5
4
3
2
1
0
10
210
410
610
810
1,010
1,210
1,410
1,610
1,810
2,010
2,210
2,409
2,609
2,809
40
49
58
67
76
85
94
103
112
121
130
139
148
157
Noise Figure(dB)
Stability Factor(Kf)
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
Frequency(MHz)
Frequency(MHz)
25
Power Gain(dB)
20
15
Out-Of-Band P1dB
In-Band P1dB
5
0
-50 -40 -30 -24 -22 -20 -18 -16 -10 -8 -6 -4 -2 0
Input Power(dBm)
Figure 18 P1dB(In-Band/Out-Of-Band)
Figure 17 Stability Factor(Kf)
Input Equivalent Capacitor(pF)
Figure 16 Noise Figure(NF)
10
V1.2
50
45
40
35
30
25
20
15
10
5
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Pulse Number
Figure 19 Tunable Capacitor(Cin)
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AW5017DNR
Jan 2016
FUNCTIONAL BLOCK DIAGRAM
VCC
1
EN
5
LDO
Reference
4bit
DCAP
RFIN
3 RF OUT
LNA
6
Figure 20
2
4
NC
GND
AW5017 FUNCTION BLOCK DIAGRAM
MEASUREMENT DIAGRAM
Test DC Characteristics (Current&Power)
A
1
2.8V
VCC
RFIN
6
Pin
C1
C2
V
2
AW5017
NC
EN
5
EZ-FM
3
Pout
RFOUT
GND
4
C3
Figure 21
AW5017 DC Test diagram
Copyright © 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD
Page11 of 18
GPIO
1.8V/2.8V
V1.2
AW5017DNR
Jan 2016
Test S-parameter
1
2.8V
VCC
RFIN
6
Pin
C1
C2
2
AW5017
EN
NC
5
GPIO
1.8V/2.8V
EZ-FM
3
Pout
RFOUT
GND
4
C3
NetWork Analyzer
Figure 22
AW5017 S-parameter measurement Diagram
Test Noise-Figure
1
2.8V
VCC
RFIN
6
Pin
C1
C2
2
AW5017
NC
EN
5
GPIO
1.8V/2.8V
EZ-FM
3
Pout
RFOUT
GND
4
C3
NF Analyzer
Figure 23
Noise
Source
AW5017 Noise Figure Measurement Diagram
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V1.2
AW5017DNR
Jan 2016
Test IIP3
Signal
Generator
1
2.8V
VCC
RFIN
6
Pin
C1
C2
2
AW5017
NC
EN
5
Signal Analyzer
RFOUT
GND
Signal
Generator
GPIO
1.8V/2.8V
EZ-FM
3
Pout
Power
Combiner
4
C3
Figure 24
AW5017 IIP3 Measurement Diagram
Test Tunable Capacitor
2.8V
1
VCC
RFIN
6
C1
C2
2
AW5017
EN
NC
5
EZ-FM
3
Figure 25
NetWork Analyzer
RFOUT
GND
Arbitrary Waveform
Generator
4
AW5017 Tunable Capacitor Measurement Diagram
Copyright © 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD
Page13 of 18
V1.2
AW5017DNR
Jan 2016
V1.2
APPLICATION INFORMATION
Choice of components
Take Figure 2 for example:
Filter block near PIFA antenna is composed of L6 and C3. These two components can be removed for
Dipole antenna. Typical value of L6 is 68 nH and of C3 is 39 pF.
Filter block of FM signal is composed of C1 and L1. GSM signal could go through and FM signal will be
blocked. GSM antenna π-type matching circuit is composed of C2, L3 and L4, adjustable based on GSM
antenna characteristics. Typically C1 is 39 pF and L1 is 68 nH.
Matching circuit of FM signal path is composed of C4, L4, L5 and L7. FM signal could go through and
GSM signal will be blocked. Typically L4 is 100 nH, L5 is 68 nH and L7 is 33 nH.
C5 is supply filtering capacitor. C6 is DC-blocking capacitor. Both are 47 nF typically.
Only when supporting earphone antenna application, C7 is added with the value of 47 nF.
Table 9 shows recommended inductor type and values. Table 10 shows recommended capacitor type
and values.
Table 9 CHOICE OF INDUCTOR
PART No.
TYP.
Q(min)
Frequency
LQG15HS33NJ02
33nH
8
100MHz
LQG15HS68NJ02
68nH
8
100MHz
LQG15HSR12J02
120nH
8
100MHz
LQG15HSR10J02
100nH
8
100MHz
SDCL1005C33NJTDF
33nH
8
100MHz
MFR
SIZE
0402
Murata
0402
0402
0402
0402
Sunlord
SDCL1005C68NJTDF
68nH
8
100MHz
0402
SDCL1005CR12JTDF
120nH
8
100MHz
0402
SDCL1005CR10JTDF
100nH
8
100MHz
0402
Table 10 CHOICE OF INDUCTOR
PART No.
TYP.
Voltage
GRM1555C1H220JA01
22pF
25V
GRM1555C1H390JA01
39pF
25V
GRM155R71C473KA01
47nF
16V
MFR
SIZE
0402
Murata
0402
0402
EN Control
AW5017 supports earphone. When baseband detects earphone inserting, GPIO will pull down, cutting off
AW5017 to avoid unnecessary power consumption.
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V1.2
When One-Line-Logic is enabled to change the capacitance of tunable capacitor to improve the voltage
gain at the input port, based equivalent diagram is shown as figure 26.
In operation frequency band of FM, short antenna can be approximated to series of open induced voltage
and equivalent inductor. Therefore, through tuning capacitance value in input port, the voltage gain can be
achieved in specified frequency. Meanwhile the receiver performance will be improved.
Gain=Vin/Vi
Short Antenna Model
L5
+
68nH
Lant
Open Induced Voltage
Vi
-
C3
39pF
Figure 26
L4
100nH
Tunable Input Capacitor
L7
C4
33nH
47nF
L6
68 nH
Vin
Cin
AW5017 Frequency Tuning Equivalent Schematic
In schematic, the value of tunable capacitor will be derived as following. fboost is FM operation frequency,
Leqq is equivalent inductance of input port towards antenna side, which depends on the type and size of short
antenna, Cin is tunable capacitance of input port.
f boost
1
(Hz)
2 π L eqq Cin
Figure 27 shows an example of voltage gain influenced by tunable capacitor. Blue and red curves are
voltage gain (equal to input voltage / open induced voltage) with maximum and minimum tunable capacitor,
respectively. The equivalent inductance of short antenna is 150nH.
60
63.3
66.6
69.9
73.2
76.5
79.8
83.1
86.4
89.7
93
96.3
99.6
102.9
106.2
109.5
112.8
116.1
119.4
122.7
126
129.3
132.6
135.9
139.2
Voltage Gain(dB)
35
30
25
20
15
10
5
0
-5
-10
-15
-20
frequency(MHz)
Figure 27
Voltage Gain with Different Tunable Capacitor
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PACKAGE DESCRIPTION
Figure 28
Package outline
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V1.2
AW5017DNR
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TAPE&REEL DESCRIPTION
2.0±0.05
Φ1.55±0.05
B'
4.0±0.1
4.0±0.1
1.72±0.05
A'
A
REF 5°
1.12±0.05
8.0±0.3
3.5±0.05
1.75±0.1
0.25±0.05
B
Φ0.55±0.05
0.7±0.05
Section A-A'
Figure 29.
Tape and Reel
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Page17 of 18
Section B-B'
V1.2
AW5017DNR
Jan 2016
V1.2
REVISION HISTORY
Table 11 .
Revision history
Document ID
Release date
Change notice
Supersedes
AW5017_V1.2
2016-01
Added Tape & Reel Description and corrected the
marking location of Pin1
AW5017_V1.1
AW5017_V1.1
2015-12
Modified Marking A into B
AW5017_V1.0
AW5017_V1.0
2015-11
Added matching capacitor C10
AW5017_V0.9
AW5017_V0.9
2014-12
Preliminary data sheet
-
DISCLAIMER
Information in this document is believed to be accurate and reliable. However, Shanghai AWINIC Technology
Co., Ltd (AWINIC Technology) does not give any representations or warranties, expressed or implied, as to the
accuracy or completeness of such information and shall have no liability for the consequences of use of such
information.
AWINIC Technology reserves the right to make changes to information published in this document, including
without limitation specifications and product descriptions, at any time and without notice. Customers shall
obtain the latest relevant information before placing orders and shall verify that such information is current and
complete. This document supersedes and replaces all information supplied prior to the publication hereof.
AWINIC Technology products are not designed, authorized or warranted to be suitable for use in medical,
military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an AWINIC
Technology product can reasonably be expected to result in personal injury, death or severe property or
environmental damage. AWINIC Technology accepts no liability for inclusion and/or use of AWINIC
Technology products in such equipment or applications and therefore such inclusion and/or use is at the
customer’s own risk.
Applications that are described herein for any of these products are for illustrative purposes only. AWINIC
Technology makes no representation or warranty that such applications will be suitable for the specified use
without further testing or modification.
All products are sold subject to the general terms and conditions of commercial sale supplied at the time of
order acknowledgement.
Nothing in this document may be interpreted or construed as an offer to sell products that is open for
acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other
industrial or intellectual property rights.
Reproduction of AWINIC information in AWINIC data books or data sheets is permissible only if reproduction is
without alteration and is accompanied by all associated warranties, conditions, limitations, and notices.
AWINIC is not responsible or liable for such altered documentation. Information of third parties may be subject
to additional restrictions.
Resale of AWINIC components or services with statements different from or beyond the parameters stated by
AWINIC for that component or service voids all express and any implied warranties for the associated AWINIC
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AW5017DNR
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V1.2
component or service and is an unfair and deceptive business practice. AWINIC is not responsible or liable for
any such statements.
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