NT5CB128M16IP-EK

Nanya Technology Corp. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP NT5CB(C)256M8IN / NT5CB(C)128M16IP Commercial, Industrial and Automotive DDR3(L) 2Gb SDRAM Features  Signal Integrity  JEDEC DDR3 Compliant - Configurable DS for system compatibility - 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/) - Configurable On-Die Termination - Double-data rate on DQs, DQS and DM - ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240 ohm ± 1%)  Data Integrity  Signal Synchronization - Auto Self Refresh (ASR) by DRAM built-in TS - Write Leveling via MR settings 6 - Auto Refresh and Self Refresh Modes - Read Leveling via MPR  Power Saving Mode  Interface and Power Supply - Partial Array Self Refresh (PASR) 1 - SSTL_15 for DDR3:VDD/VDDQ=1.5V(±0.075V) 3 - Power Down Mode - SSTL_135 for DDR3L:VDD/VDDQ=1.35V(-0.067/+0.1V) Options  Speed Grade (CL-TRCD-TRP) 2  Temperature Range (Tc) 4 - Commercial Grade = 0℃~95℃ - Quasi Industrial Grade (-T) = -40℃~95℃ - Industrial Grade (-I) = -40℃~95℃ - Automotive Grade 2 (-H) = -40℃~105℃ - Automotive Grade 3 (-A) = -40℃~95℃ - 2133 Mbps / 14-14-14 - 1866 Mbps / 13-13-13 - 1600 Mbps / 11-11-11 Programmable Functions  CAS Latency (6/7/8/9/10/11/13/14)  Self RefreshTemperature Range(Normal/Extended)  CAS Write Latency (5/6/7/8/9/10)  Output Driver Impedance (34/40)  Additive Latency (0/CL-1/CL-2)  On-Die Termination of Rtt_Nom(20/30/40/60/120)  Write Recovery Time (5/6/7/8/10/12/14/16)  On-Die Termination of Rtt_WR(60/120)  Burst Type (Sequential/Interleaved)  Precharge Power Down (slow/fast)  Burst Length (BL8/BC4/BC4 or 8 on the fly) Packages / Density Information Density and Addressing Lead-free RoHS compliance and Halogen-free 2Gb Length x Width Ball pitch (Org. / Package) (mm) (mm) Organization 256Mb x 8 Bank Address BA0 – BA2 Auto precharge 256Mbx8 128Mbx16 78-ball VFBGA 96-ball VFBGA 8.00 x 10.50 8.00 x 13.00 0.80 0.80 128Mb x 16 BA0 – BA2 A10 / AP A10 / AP BL switch on the fly A12 /  A12 /  Row Address A0 – A14 A0 – A13 Column Address A0 – A9 A0 – A9 Page Size 1KB 2KB tREFI(us) tRFC(ns) 4 Tc85℃:3.9 5 160ns NOTE 1 Default state of PASR is disabed. This is enabled by using an electrical fuse. Please contact with NTC for the demand. NOTE 2 Please refer to ordering information for the detail. NOTE 3 1.35V DDR3L are backward compatible to 1.5V DDR3 parts. Please refer to page 5 operating frequency table.1.35V DDR3L-RS parts are exceptional and unallowable to be compatible to 1.35V DDR3L and 1.5V DDR3 parts. NOTE 4 If TC exceeds 85°C, the DRAM must be refreshed externally at 2x refresh, which is a 3.9us interval refresh rate. Extended SRT or ASR must be enabled. NOTE 5 Violating tRFC specification will induce malfunction. NOTE 6 Only Support prime DQ’s feedback for each byte lane. Version 1.9 02/2017 1 NTC has the rights to change any specifications or product without notification. Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Fundamental AC Specifications – Core Timing DDR3-2133, DDR3(L)-1866, DDR3(L)-1600 and DDR3(L)-1333 DDR3-2133 DDR3(L)-1866 DDR3(L)-1600 14-14-14 13-13-13 11-11-11 DDR3(L)-1333 Speed Bins 9-9-9 10-10-10 Unit Parameter Min Max Min Max Min Max Min Max Min Max tAA 13.09 20 13.91 20 13.75 20 13.5 20 15 20 ns tRCD 13.09 - 13.91 - 13.75 - 13.5 - 15 - ns tRP 13.09 - 13.91 - 13.75 - 13.5 - 15 - ns tRC 46.09 - 47.91 - 48.75 - 49.5 - 51 - ns tRAS 33 9*tREFI 34 9*tREFI 35 9*tREFI 36 9*tREFI 36 9*tREFI ns DDR3(L)-1066 and DDR3-800 DDR3(L)-1066 DDR3-800 Speed Bins 7-7-7 Version 1.9 02/2017 8-8-8 6-6-6 Unit Parameter Min Max Min Max Min Max tAA 13.125 20 15 20 15 20 ns tRCD 13.125 - 15 - 15 - ns tRP 13.125 - 15 - 15 - ns tRC 50.625 - 52.5 - 52.5 - ns tRAS 37.5 9*tREFI 37.5 9*tREFI 37.5 9*tREFI ns 2 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Descriptions The 2Gb Double-Data-Rate-3 (DDR3(L)) is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAMs. The 2Gb chip is organized as 32Mbit x 8 I/Os x 8 banks or 16Mbit x 16 I/Os x 8 bank devices. These synchronous devices achieve high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin for general applications. The chip is designed to comply with all key DDR3(L) DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and  falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fashion. These devices operate with a single 1.5V ± 0.075V or 1.35V -0.067V/+0.1V power supply and are available in BGA packages. Version 1.9 02/2017 3 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Ordering Information Speed Organization Part Number Package Clock (MHz) Data Rate (Mb/s) CL-TRCD-TRP DDR3(L) Commercial Grade 256M x 8 128M x 16 NT5CB256M8IN-DI NT5CB256M8IN-EK1 NT5CB256M8IN-FL NT5CC256M8IN-DI NT5CC256M8IN-EK NT5CC256M8IN-DIB NT5CB128M16IP-DI NT5CB128M16IP-EK1 NT5CB128M16IP-FL NT5CC128M16IP-DI NT5CC128M16IP-EK NT5CC128M16IP-DIB 78-Ball 96-Ball 800 DDR3-1600 11-11-11 933 DDR3-1866 13-13-13 1066 DDR3-2133 14-14-14 800 DDR3L-16003 11-11-11 933 DDR3L-18663 13-13-13 800 DDR3L-16003 11-11-11 800 DDR3-1600 11-11-11 933 DDR3-1866 13-13-13 1066 DDR3-2133 14-14-14 800 DDR3L-16003 11-11-11 933 DDR3L-18663 13-13-13 800 DDR3L-16003 11-11-11 DDR3(L) Industrial Grade 256M x 8 128M x 16 NT5CB256M8IN-DII NT5CB256M8IN-EKI NT5CC256M8IN-DII NT5CC256M8IN-EKI NT5CB128M16IP-DII NT5CB128M16IP-EKI NT5CC128M16IP-DII NT5CC128M16IP-EKI 78-Ball 96-Ball 800 DDR3-1600 11-11-11 933 DDR3-1866 13-13-13 800 DDR3L-16003 11-11-11 933 3 DDR3L-1866 13-13-13 800 DDR3-1600 11-11-11 933 DDR3-1866 13-13-13 800 DDR3L-16003 11-11-11 933 DDR3L-18663 13-13-13 DDR3(L) Quasi Industrial Grade 256M x 8 128M x 16 NT5CB256M8IN-DIT NT5CB256M8IN-EKT NT5CC256M8IN-DIT NT5CC256M8IN-EKT NT5CB128M16IP-DIT NT5CB128M16IP-EKT NT5CC128M16IP-DIT NT5CC128M16IP-EKT 78-Ball 96-Ball 800 DDR3-1600 11-11-11 933 DDR3-1866 13-13-13 800 DDR3L-16003 11-11-11 933 DDR3L-18663 13-13-13 800 DDR3-1600 11-11-11 933 DDR3-1866 13-13-13 800 DDR3L-16003 11-11-11 933 DDR3L-18663 13-13-13 DDR3-1600 11-11-11 DDR3(L) Automotive Grade 2 256M x 8 128M x 16 NT5CB256M8IN-DIH NT5CC256M8IN-DIH NT5CB128M16IP-DIH NT5CC128M16IP-DIH 78-Ball 96-Ball 800 128M x 16 NT5CB256M8IN-DIA NT5CC256M8IN-DIA NT5CB128M16IP-DIA NT5CC128M16IP-DIA 78-Ball 96-Ball 3 800 DDR3L-1600 11-11-11 800 DDR3-1600 11-11-11 800 DDR3L-16003 11-11-11 800 DDR3-1600 11-11-11 800 DDR3L-16003 11-11-11 800 DDR3-1600 11-11-11 800 DDR3L-16003 11-11-11 DDR3(L) Automotive Grade 3 256M x 8 2 2 NOTE 1 Mainstream Product. NOTE 2 Please confirm with NTC for the available schedule. NOTE 3 1.35V DDR3L are backward compatible to 1.5V DDR3 parts. Please refer to page 5 operating frequency table.1.35V DDR3L-RS parts are exceptional and unallowable to be compatible to 1.35V DDR3L and 1.5V DDR3 parts. Version 1.9 02/2017 4 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP NANYA Component Part Numbering Guide NT 5C B 256M8 I N DI Special Type Option NA = Commercial Grade T = Quasi industrial Grade I = Industrial Grade H = Automotive Grade2 A = Automotive Grade3 B = Reduced Standby NANYA Technology Product Family 5C = DDR3 SDRAM Speed DDR3 SDRAM DI = DDR3 - 1600 11-11-11 EK = DDR3 - 1866 13-13-13 FL = DDR3- 2133 14-14-14 Interface & Power ( VDD & VDDQ) B = SSTL_ 15 (1.5V , 1.5V) C = SSTL_135 (1.35V , 1.35V) Organization (Depth , Width) 128M 16 = 256M 8 = 2Gb Note: M= Mono Package Code RoHS + Halogen Free N=78 -Ball VFBGA P=96 -Ball VFBGA Device Version I = 9 th Version Operating frequency The backward compatibility of each speed grade is listed in a table below. If an application operates at specific frequency which is not defined herein but within the highest and the lowest supporting grade, then the comparative loose specifications to DRAM must be adopted from the neighboring defined speed bins. Pls confirm notices with NTC for operating frequency slower than defined speed bins. For instance, DRAMs of -FL grade can support not only DDR3-2133 but also low speed bin like DDR3-1866 or DDR3-1600. In case AP cooperates with DRAM of -FL grade and operates at undefined DDR3-1800 condition, then CL must be set to 13 which is a comparative looser spec than 11. Do the same way for the rest parameters. Frequency [Mbps] CL[nCK] 14 VDD[V] 1.5 13 1.35 11 1.5 DDR3-FL 2133 DDR3-EK N/A DDR3-DI N/A N/A DDR3L-EK N/A 1866 DDR3L-DI N/A N/A Version 1.9 02/2017 1866 N/A 1866 1.35 1.5 1.35 1.5 7 or 8 1.35 1.5 6 1.5 1600 1333 1066 800 1600 1333 1066 800 1333 1066 800 1600 1333 1066 800 1600 1333 1066 800 N/A 5 9 or 10 1600 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Ball Configuration – 78 Ball VFBGA Package (X8) See the balls through the package A B C D E F G H J K L M N 1 VSS VSS VDDQ VSSQ VREFDQ NC ODT NC VSS VDD VSS VDD VSS 1 2 VDD VSSQ DQ2 DQ6 VDDQ VSS VDD 3 NC DQ0 DQS 4 5 6  DQ4 RA A WE  BA0 A3 A5 A7 BA2 A0 A2 A9 A13 3 REET 2 7 NU,T DM,TDQS DQ1 VDD DQ7 CK  4 5 6 A10/AP NC A12,  A1 A11 A14 7 8 VSS VSSQ DQ3 VSS DQ5 VSS VDD ZQ VREFCA BA1 A4 A6 A8 8 9 VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD VSS VDD VSS 9 A B C D E F G H J K L M N Unit: mm * BSC (Basic Spacing between Center) Version 1.9 02/2017 6 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Ball Configuration – 96 Ball VFBGA Package (X16) See the balls through the package A B C D E F G H J K L M N P R T 1 VDDQ VSSQ VDDQ VSSQ VSS VDDQ VSSQ VREFDQ NC ODT NC VSS VDD VSS VDD VSS 1 2 DQU5 VDD DQU3 VDDQ VSSQ DQL2 DQL6 VDDQ VSS VDD 3 DQU7 VSS DQU1 DMU DQL0 DQSL 4 5 6 U DQSU DQU0 DML DQL1 VDD DQL7 CK L DQL4 RA A WE  BA0 A3 A5 A7 BA2 A0 A2 A9 A13 3 REET 2 7 DQU4  4 5 6 A10/AP NC A12,  A1 A11 NC 7 8 VDDQ DQU6 DQU2 VSSQ VSSQ DQL3 VSS DQL5 VSS VDD ZQ VREFCA BA1 A4 A6 A8 8 9 VSS VSSQ VDDQ VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD VSS VDD VSS 9 A B C D E F G H J K L M N P R T Unit: mm * BSC (Basic Spacing between Center) Version 1.9 02/2017 7 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Ball Descriptions Symbol Type  Input Function Clock: CK and  are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of . Clock Enable: CKE high activates, and CKE low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE low provides Precharge Power-Down and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is CKE Input asynchronous for Self-Refresh exit. After VREF has become stable during the power on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF must maintain to this input. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, , ODT and CKE are disabled during Power Down. Input buffers, excluding CKE, are disabled during Self-Refresh. Chip Select: All commands are masked when  is registered high.  provides for external  Input rank selection on systems with multiple memory ranks.  is considered part of the command code. RA, A, WE Input For x8, Command Inputs: RA, A and WE (along with ) define the command being entered. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is DM Input For x16, sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS. For x8 device, the function of DM or TDQS/T is enabled by Mode Register A11 setting in MR1. DMU, DML Bank Address Inputs: BA0, BA1, and BA2 define to which bank an Active, Read, Write or BA0 - BA2 Input Precharge command is being applied. Bank address also determines which mode register is to be accessed during a MRS cycle. Auto-Precharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be performed to the accessed bank after the Read/Write operation. (HIGH: A10 / AP Input Autoprecharge; LOW: no Autoprecharge). A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank addresses. For x8, Address Inputs: Provide the row address for Activate commands and the column address for A0 – A14 Input Read/Write commands to select one location out of the memory array in the respective bank. For x16, (A10/AP and A12/ have additional function as below.) The address inputs also provide the A0 – A13 op-code during Mode Register Set commands. A12/ Input Burst Chop: A12/is sampled during Read and Write commands to determine if burst chop (on the fly) will be performed. (HIGH - no burst chop; LOW - burst chopped). On Die Termination: ODT (registered HIGH) enables termination resistance internal to the ODT Input DDR3 SDRAM. When enabled, ODT is applied to each DQ, DQS, and DM/TDQS, NU/T (when TDQS is enabled via Mode Register A11=1 in MR1) signal for x8 configurations. The ODT pin will be ignored if Mode-registers, MR1and MR2, are programmed to disable RTT. Version 1.9 02/2017 8 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Symbol Type REET Input Function Active Low Asynchronous Reset: Reset is active when REET is LOW, and inactive when REET is HIGH. REET must be HIGH during normal operation. REET is a CMOS rail to rail signal with DC high and low at 80% and 20% of VDD, i.e. 1.20V for DC high and 0.30V. Data Inputs/Output: Bi-directional data bus. DQ0 is the prime DQ in a low byte lane of DQ Input/output x4/x8/x16 configuration and DQ8 is the prime DQ in a high byte lane of x16 configuration for write leveling. Data Strobe: output with read data, input with write data. Edge aligned with read data, centered For x8, with write data. The data strobes DQS, DQSL, DQSU are paired with differential signals , DQS, () For x16, Input/output L, U, respectively, to provide differential pair signaling to the system during both reads and writes. DDR3 SDRAM supports differential data strobe only and does not support DQSL,(L), single-ended. DQSU,(U) Termination Data Strobe: TDQS/T is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in MR1, DRAM will enable the same termination resistance function on For x8, Output TDQS, (T) TDQS/T that is applied to DQS/. When disabled via mode register A11=0 in MR1, DM/T will provide the data mask function and T is not used. x16 DRAMs must disable the TDQS function via mode register A11=0 in MR1. NC - VDDQ Supply DQ Power Supply: 1.35V -0.067V/+0.1V or 1.5V ± 0.075V VDD Supply Power Supply: 1.35V -0.067V/+0.1V or 1.5V ± 0.075V VSSQ Supply DQ Ground VSS Supply Ground VREFCA Supply Reference voltage for CA VREFDQ Supply Reference voltage for DQ ZQ Supply Reference pin for ZQ calibration. No Connect: No internal electrical connection is present. Notes: 1. Input only pins (BA0-BA2, A0-A14, RA, A, WE, , CKE, ODT, and REET) do not supply termination. 2. The signal may show up in a different symbol but it indicates the same thing. e.g., /CK = CK# =  = CKb, /DQS = DQS# =  = DQSb, /CS = CS# =  = CSb. Version 1.9 02/2017 9 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Simplified State Diagram Power Applied Power ON Reset Procedure MRS, MPR, Write Levelizing Initialization Self Refresh SRE From any State ZQCL RESET MRS SRX ZQCL ZQCS ZQ Calibration Idle Refreshing REF PDX ACT PDE Precharge Power Down Activating Active Power Down PDE PDX Bank Active Write Read Read Write Read Writing Reading Write Write A Automatic Sequence Read A Write A Read A Read A Write A Command Sequence PRE, PREA Writing PRE, PREA Reading PRE, PREA Precharging State Diagram Command Definitions Version 1.9 02/2017 Abbr. Function Abbr. Function Abbr. Function ACT Active Read RD, RDS4, RDS8 PDE Enter Power-down PRE Precharge Read A RDA, RDAS4, RDAS8 PDX Exit Power-down PREA Precharge All Write WR, WRS4, WRS8 SRE Self-Refresh entry MRS Mode Register Set Write A WRA, WRAS4, WRAS8 SRX Self-Refresh exit REF Refresh RESET Start RESET Procedure MPR Multi-Purpose Register ZQCL ZQ Calibration Long ZQCS ZQ Calibration Short 10 - - Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Basic Functionality The DDR3(L) SDRAM is a high-speed dynamic random access memory internally configured as an eight-bank DRAM. The DDR3(L) SDRAM uses an 8n prefetch architecture to achieve high speed operation. The 8n prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3(L) SDRAM consists of a single 8n-bit wide, four clock data transfer at the internal DRAM core and eight corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins. Read and write operation to the DDR3(L) SDRAM are burst oriented, start at a selected location, and continue for a burst length of eight or a ‘chopped’ burst of four in a programmed sequence. Operation begins with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be activated (BA0-BA2 select the bank; A0-A14 select the row). The address bit registered coincident with the Read or Write command are used to select the starting column location for the burst operation, determine if the auto precharge command is to be issued (via A10), and select BC4 or BL8 mode ‘on the fly’ (via A12) if enabled in the mode register. Prior to normal operation, the DDR3(L) SDRAM must be powered up and initialized in a predefined manner. The following sections provide detailed information covering device reset and initialization, register definition, command descriptions and device operation. RESET and Initialization Procedure Power-up Initialization sequence The Following sequence is required for POWER UP and Initialization 1. Apply power (REET is recommended to be maintained below 0.2 x VDD, all other inputs may be undefined). REET needs to be maintained for minimum 200μs with stable power. CKE is pulled “Low” anytime before REETbeing de-asserted (min. time 10ns). The power voltage ramp time between 300mV to VDD min must be no greater than 200ms; and during the ramp, VDD>VDDQ and (VDD-VDDQ) =2.5ns) 6 (2.5ns>=tCK(avg)>=1.875ns) 7 (1.875ns>=tCK(avg)>=1.5ns) 8 (1.5ns>=tCK(avg)>=1.25ns) 9 (1.25ns>=tCK(avg)>=1.07ns) 10 (1.07ns>=tCK(avg)>=0.935ns) RFU RFU * 1 : Default state of PASR is disabed. This is enabled by using an electrical fuse. Please contact with NTC for the demand. * 2 : BA2, A5, A8, A11 ~ A15 are RFU and must be programmed to 0 during MRS. * 3 : The Rtt_WR value can be applied during writes even when Rtt_Nom is disabled. During write leveling, Dynamic ODT is not available. Version 1.9 02/2017 24 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP CAS Write Latency (CWL) The CAS Write Latency is defined by MR2 (bits A3-A5) shown in MR2. CAS Write Latency is the delay, in clock cycles, between the internal Write command and the availability of the first bit of input data. DDR3(L) DRAM does not support any half clock latencies. The overall Write Latency (WL) is defined as Additive Latency (AL) + CAS Write Latency (CWL); WL=AL+CWL. Auto Self-Refresh (ASR) and Self-Refresh Temperature (SRT) DDR3(L) SDRAM must support Self-Refresh operation at all supported temperatures. Applications requiring Self-Refresh operation in the Extended Temperature Range must use the ASR function or program the SRT bit appropriately. Optional in DDR3(L) SDRAM: Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3(L) SDRAM devices support the following options or requirements referred to in this material. For more details refer to “Extended Temperature Usage”. DDR3(L) SDRAMs must support Self-Refresh operation at all supported temperatures. Applications requiring Self-Refresh operation in the Extended Temperature Range must use the optional ASR function or program the SRT bit appropriately. Dynamic ODT (Rtt_WR) DDR3(L) SDRAM introduces a new feature “Dynamic ODT”. In certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the DDR3(L) SDRAM can be changed without issuing an MRS command. MR2 Register locations A9 and A10 configure the Dynamic ODT settings. In Write leveling mode, only RTT_Nom is available. For details on Dynamic ODT operation, refer to “Dynamic ODT”. Version 1.9 02/2017 25 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Mode Register MR3 The Mode Register MR3 controls Multi-purpose registers. The Mode Register 3 is written by asserting low on , RA, A, WE high on BA1 and BA0, and low on BA2 while controlling the states of address pins according to the table below. MR3 Definition BA2 BA1 BA0 A15-A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ 0 MR select 0 A2 0 1 BA1 0 0 1 1 BA0 0 1 0 1 MPR Normal operation Dataflow from MPR MR select MR0 MR1 MR2 MR3 MPR A1 0 0 1 1 A0 0 1 0 1 MPR Loc MPR Loc Predefined pattern Reserved Reserved Reserved * 1 : BA2, A3 - A15 are RFU and must be programmed to 0 during MRS. * 2 : The predefined pattern will be used for read synchronization. * 3 : When MPR control is set for normal operation (MR3 A[2] = 0) then MR3 A[1:0] will be ignored. Version 1.9 02/2017 26 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Multi-Purpose Register (MPR) The Multi Purpose Register (MPR) function is used to Read out a predefined system timing calibration bit sequence. Fig. 1: MPR Block Diagram To enable the MPR, a MODE Register Set (MRS) command must be issued to MR3 Register with bit A2 = 1, prior to issuing the MRS command, all banks must be in the idle state (all banks precharged and tRP met). Once the MPR is enabled, any subsequent RD or RDA commands will be redirected to the Multi Purpose Register. The resulting operation, when a RD or RDA command is issued, is defined by MR3 bits A[1:0] when the MPR is enabled as shown. When the MPR is enabled, only RD or RDA commands are allowed until a subsequent MRS command is issued with the MPR disabled (MR3 bit A2 = 0). Note that in MPR mode RDA has the same functionality as a READ command which means the auto precharge part of RDA is ignored. Power-Down mode, Self-Refresh and any other non-RD/RDA command is not allowed during MPR enable mode. The RESET function is supported during MPR enable mode. Version 1.9 02/2017 27 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP MPR MR3 Register Definition MR3 A[2] MR3 A[1:0] MPR MPR-Loc Function Normal operation, no MPR transaction. 0b don't care (0b or 1b) All subsequent Reads will come from DRAM array. All subsequent Write will go to DRAM array. 1b See MR3 Table Enable MPR mode, subsequent RD/RDA commands defined by MR3 A[1:0]. MPR Functional Description • One bit wide logical interface via all DQ pins during READ operation. • Register Read on x8: • DQ[0] drives information from MPR. • DQ[7:1] either drive the same information as DQ [0], or they drive 0b. • Register Read on x16: • DQL[0] and DQU[0] drive information from MPR. • DQL[7:1] and DQU[7:1] either drive the same information as DQL [0], or they drive 0b. • Addressing during for Multi Purpose Register reads for all MPR agents: • BA [2:0]: don’t care • A[1:0]: A[1:0] must be equal to ‘00’b. Data read burst order in nibble is fixed • A[2]: For BL=8, A[2] must be equal to 0b, burst order is fixed to [0,1,2,3,4,5,6,7], *) For Burst Chop 4 cases, the burst order is switched on nibble base A [2]=0b, Burst order: 0,1,2,3 *) A[2]=1b, Burst order: 4,5,6,7 *) • A[9:3]: don’t care • A10/AP: don’t care • A12/BC: Selects burst chop mode on-the-fly, if enabled within MR0. • A11, A13... (if available): don’t care • Regular interface functionality during register reads: • Support two Burst Ordering which are switched with A2 and A[1:0]=00b. • Support of read burst chop (MRS and on-the-fly via A12/BC) • All other address bits (remaining column address bits including A10, all bank address bits) will be ignored by the DDR3(L) SDRAM. • Regular read latencies and AC timings apply. • DLL must be locked prior to MPR Reads. NOTE: *Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent. Version 1.9 02/2017 28 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP MPR MR3 Register Definition MR3 A[2] MR3 A[1:0] Function Burst Length Read Address Burst Order A[2:0] and Data Pattern 000b BL8 Read Predefined 1b 00b Pattern for System Burst order 0,1,2,3,4,5,6,7 Pre-defined Data Pattern [0,1,0,1,0,1,0,1] 000b BC4 Burst order 0,1,2,3 Pre-defined Data Pattern [0,1,0,1] Calibration Burst order 4,5,6,7 BC4 100b BL8 000b Burst order 0,1,2,3,4,5,6,7 BC4 000b Burst order 0,1,2,3 BC4 100b Burst order 4,5,6,7 BL8 000b Burst order 0,1,2,3,4,5,6,7 BC4 000b Burst order 0,1,2,3 BC4 100b Burst order 4,5,6,7 BL8 000b Burst order 0,1,2,3,4,5,6,7 BC4 000b Burst order 0,1,2,3 BC4 100b Burst order 4,5,6,7 Pre-defined Data Pattern [0,1,0,1] 1b 1b 1b 01b 10b 11b RFU RFU RFU NOTE: Burst order bit 0 is assigned to LSB and the burst order bit 7 is assigned to MSB of the selected MPR agent. Version 1.9 02/2017 29 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP DDR3(L) SDRAM Command Description and Operation Command Truth Table CKE A0BA0- A13- A12- A10A9, NOTES Previous Current  RA A WE BA2 A14  AP A11 Cycle Cycle Function Abbr. Mode Register Set MRS H H L L L L BA Refresh REF H H L L L H V V V V V Self Refresh Entry SRE H L L L L H V V V V V H X X X X X X X X Self Refresh Exit SRX L H L H H H V V V V V Single Bank Precharge OP Code 7,9,12 7,8,9,12 PRE H H L L H L BA V V L V PREA H H L L H L V V V H V Bank Activate ACT H H L L H H BA Write (Fixed BL8 or BC4) WR H H L H L L BA RFU V L CA Write (BC4, on the Fly) WRS4 H H L H L L BA RFU L L CA Write (BL8, on the Fly) WRS8 H H L H L L BA RFU H L CA Write with Auto Precharge (Fixed BL8 or BC4) WRA H H L H L L BA RFU V H CA Write with Auto Precharge (BC4, on the Fly) WRAS4 H H L H L L BA RFU L H CA Write with Auto Precharge (BL8, on the Fly) WRAS8 H H L H L L BA RFU H H CA RD H H L H L H BA RFU V L CA Read (BC4, on the Fly RDS4 H H L H L H BA RFU L L CA Read (BL8, on the Fly) RDS8 H H L H L H BA RFU H L CA Read with Auto Precharge (Fixed BL8 or BC4) RDA H H L H L H BA RFU V H CA Read with Auto Precharge (BC4, on the Fly) RDAS4 H H L H L H BA RFU L H CA Read with Auto Precharge (BL8, on the Fly) RDAS8 H H L H L H BA RFU H H CA No Operation NOP H H L H H H V V V V V 10 Device Deselected DES H H H X X X X X X X X 11 L H H H V V V V V Power Down Entry PDE H L H X X X X X X X X L H H H V V V V V H X X X X X X X X Precharge all Banks Read (Fixed BL8 or BC4) Power Down Exit PDX L Row Address (RA) 6,12 H 6,12 ZQ Calibration Long ZQCL H H L H H L X X X H X ZQ Calibration Short ZQCS H H L H H L X X X L X Version 1.9 02/2017 30 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP DDR3(L) SDRAM Command Description and Operation Command Truth Table (Conti.) NOTE1. All DDR3(L) SDRAM commands are defined by states of , RA, A, WEand CKE at the rising edge of the clock. The MSB of BA, RA and CA are device density and configuration dependant. NOTE2. REET is Low enable command which will be used only for asynchronous reset so must be maintained HIGH during any function. NOTE3. Bank addresses (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register. NOTE4. “V” means “H or L (but a defined logic level)” and “X” means either “defined or undefined (like floating) logic level”. NOTE5. Burst reads or writes cannot be terminated or interrupted and Fixed/on-the-Fly BL will be defined by MRS. NOTE6. The Power-Down Mode does not perform any refresh operation. NOTE7. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. NOTE8. Self Refresh Exit is asynchronous. NOTE9. VREF (Both VrefDQ and VrefCA) must be maintained during Self Refresh operation. NOTE10. The No Operation command should be used in cases when the DDR3(L) SDRAM is in an idle or wait state. The purpose of the No Operation command (NOP) is to prevent the DDR3(L) SDRAM from registering any unwanted commands between operations. A No Operation command will not terminate a pervious operation that is still executing, such as a burst read or write cycle. NOTE11. The Deselect command performs the same function as No Operation command. NOTE12. Refer to the CKE Truth Table for more detail with CKE transition. Version 1.9 02/2017 31 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP CKE Truth Table CKE Command (N) RA, A,WE,  Action (N) Notes L X Maintain Power-Down 14,15 L H DESELECT or NOP Power-Down Exit 11,14 L L X Maintain Self-Refresh 15,16 L H DESELECT or NOP Self-Refresh Exit 8,12,16 Bank(s) Active H L DESELECT or NOP Active Power-Down Entry 11,13,14 Reading H L DESELECT or NOP Power-Down Entry 11,13,14,17 Writing H L DESELECT or NOP Power-Down Entry 11,13,14,17 Precharging H L DESELECT or NOP Power-Down Entry 11,13,14,17 Refreshing H L DESELECT or NOP Precharge Power-Down Entry 11 H L DESELECT or NOP Precharge Power-Down Entry 11,13,14,18 H L REFRESH Self-Refresh 9,13,18 Current State Previous Cycle (N-1) Current Cycle (N) L Power-Down Self-Refresh All Banks Idle NOTE 1 CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge. NOTE 2 Current state is defined as the state of the DDR3(L) SDRAM immediately prior to clock edge N. NOTE 3 COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N), ODT is not included here. NOTE 4 All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. NOTE 5 The state of ODT does not affect the states described in this table. The ODT function is not available during Self-Refresh. NOTE 6 CKE must be registered with the same value on tCKEmin consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the tCKEmin clocks of registrations. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + tCKEmin + tIH. NOTE 7 DESELECT and NOP are defined in the Command Truth Table. NOTE 8 On Self-Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXS period. Read or ODT commands may be issued only after tXSDLL is satisfied. NOTE 9 Self-Refresh modes can only be entered from the All Banks Idle state. NOTE 10 Must be a legal command as defined in the Command Truth Table. NOTE 11 Valid commands for Power-Down Entry and Exit are NOP and DESELECT only. NOTE 12 Valid commands for Self-Refresh Exit are NOP and DESELECT only. NOTE 13 Self-Refresh cannot be entered during Read or Write operations. NOTE 14 The Power-Down does not perform any refresh operations. NOTE 15 “X” means “don’t care“(including floating around VREF) in Self-Refresh and Power-Down. It also applies to Address pins. NOTE 16 VREF (Both Vref_DQ and Vref_CA) must be maintained during Self-Refresh operation. NOTE 17 If all banks are closed at the conclusion of the read, write or precharge command, then Precharge Power-Down is entered, otherwise Active Power-Down is entered. NOTE 18 ‘Idle state’ is defined as all banks are closed (tRP, tDAL, etc. satisfied), no data bursts are in progress, CKE is high, and all timings from previous operations are satisfied (tMRD, tMOD, tRFC, tZQinit, tZQoper, tZQCS, etc.) as well as all Self-Refresh exit and Power-Down Exit parameters are satisfied (tXS, tXP, tXPDLL, etc). Version 1.9 02/2017 32 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP No Operation (NOP) Command The No operation (NOP) command is used to instruct the selected DDR3(L) SDRAM to perform a NOP (low and RA, A, and WE high). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. Deselect Command The DESELECT function (HIGH) prevents new commands from being executed by the DDR3(L) SDRAM. The DDR3(L) SDRAM is effectively deselected. Operations already in progress are not affected. DLL- Off Mode DDR3(L) DLL-off mode is entered by setting MR1 bit A0 to “1”; this will disable the DLL for subsequent operations until A0 bit set back to “0”. The MR1 A0 bit for DLL control can be switched either during initialization or later. The DLL-off Mode operations listed below are an optional feature for DDR3(L). The maximum clock frequency for DLL-off Mode is specified by the parameter tCKDLL_OFF. There is no minimum frequency limit besides the need to satisfy the refresh interval, tREFI. Due to latency counter and timing restrictions, only one value of CAS Latency (CL) in MR0 and CAS Write Latency (CWL) in MR2 are supported. The DLL-off mode is only required to support setting of both CL=6 and CWL=6. DLL-off mode will affect the Read data Clock to Data Strobe relationship (tDQSCK) but not the data Strobe to Data relationship (tDQSQ, tQH). Special attention is needed to line up Read data to controller time domain. Comparing with DLL-on mode, where tDQSCK starts from the rising clock edge (AL+CL) cycles after the Read command, the DLL-off mode tDQSCK starts (AL+CL-1) cycles after the read command. Another difference is that tDQSCK may not be small compared to tCK (it might even be larger than tCK) and the difference between tDQSCKmin and tDQSCKmax is significantly larger than in DLL-on mode. The timing relations on DLL-off mode READ operation have shown at the following Timing Diagram (CL=6, BL=8) Version 1.9 02/2017 33 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP DLL-off mode READ Timing Operation T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 CK CK CMD Address READ Bank, Col b RL = AL+CL = 6 (CL=6, AL=0) DQSdiff_DLL_on Din b DQ_DLL_on RL(DLL_off) = AL+(CL-1) = 5 Din b+1 Din b+2 Din b+3 Din b+4 Din b+5 Din b+6 Din b+7 tDQSCKDLL_diff_min DQSdiff_DLL_off Din b DQ_DLL_off Din b+1 Din b+2 Din b+3 Din b+4 Din b+5 Din b+6 Din b+7 Din b+3 Din b+4 Din b+5 Din b+6 DQSdiff_DLL_off tDQSCKDLL_diff_max Din b DQ_DLL_off Din b+1 Din b+2 Din b+7 Note: The tDQSCK is used here for DQS, , and DQ to have a simplified diagram; the DLL_off shift will affect both timings in the same way and the skew between all DQ, DQS, and signals will still be tDQSQ. Version 1.9 02/2017 34 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP DLL on/off switching procedure DDR3(L) DLL-off mode is entered by setting MR1 bit A0 to “1”; this will disable the DLL for subsequent operation until A0 bit set back to “0”. DLL “on” to DLL “off” Procedure To switch from DLL “on” to DLL “off” requires the frequency to be changed during Self-Refresh outlined in the following procedure: 1. Starting from Idle state (all banks pre-charged, all timing fulfilled, and DRAMs On-die Termination resistors, RTT, must be in high impedance state before MRS to MR1 to disable the DLL). 2. Set MR1 Bit A0 to “1” to disable the DLL. 3. Wait tMOD. 4. Enter Self Refresh Mode; wait until (tCKSRE) is satisfied. 5. Change frequency, in guidance with “Input Clock Frequency Change” section. 6. Wait until a stable clock is available for at least (tCKSRX) at DRAM inputs. 7. Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until all tMOD timings from any MRS command are satisfied. In addition, if any ODT features were enabled in the mode registers when Self Refresh mode was entered, the ODT signal must continuously be registered LOW until all tMOD timings from any MRS command are satisfied. If both ODT features were disabled in the mode registers when Self Refresh mode was entered, ODT signal can be registered LOW or HIGH. 8. Wait tXS, and then set Mode Registers with appropriate values (especially an update of CL, CWL, and WR may be necessary. A ZQCL command may also be issued after tXS). 9. Wait for tMOD, and then DRAM is ready for next command. Version 1.9 02/2017 35 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP DLL Switch Sequence from DLL-on to DLL-off T0 T1 T 0 a T 1 a T 0 b T 0 c T 0 d T 1 d T 0 e T 1 e T 0 f CK CK tMOD CMD 1) MRS 2) NOP tCKSRE SRE 3) 4) tCKSRX 5) tXS SRX 6) NOP NOP tMOD MRS 7) NOP Vali 8) d tCKESR CKE Vali 8) d Vali 8) d ODT Tim e break Do not Car e Note: ODT: Static LOW in case RTT_Nom and RTT_WR is enabled, otherwise static Low or High 1) Starting with Idle State, RTT in Hi-Z State. 2) Disable DLL by setting MR1 Bit A0 to 1. 3) Enter SR. 4) Change Frequency. 5) Clock must be stable at least tCKSRX. 6) Exit SR. 7) Update Mode registers with DLL off parameters setting. 8) Any valid command. Version 1.9 02/2017 36 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP DLL “off” to DLL “on” Procedure To switch from DLL “off” to DLL “on” (with requires frequency change) during Self-Refresh: 1. Starting from Idle state (all banks pre-charged, all timings fulfilled and DRAMs On-die Termination resistors (RTT) must be in high impedance state before Self-Refresh mode is entered). 2. Enter Self Refresh Mode, wait until tCKSRE is satisfied. 3. Change frequency, in guidance with “Input clock frequency change” section. 4. Wait until a stable is available for at least (tCKSRX) at DRAM inputs. 5. Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until tDLLK timing from subsequent DLL Reset command is satisfied. In addition, if any ODT features were enabled in the mode registers when Self Refresh mode was entered. The ODT signal must continuously be registered LOW until tDLLK timings from subsequent DLL Reset command is satisfied. If both ODT features are disabled in the mode registers when Self Refresh mode was entered, ODT signal can be registered LOW or HIGH. 6. Wait tXS, then set MR1 Bit A0 to “0” to enable the DLL. 7. Wait tMRD, then set MR0 Bit A8 to “1” to start DLL Reset. 8. Wait tMRD, then set Mode registers with appropriate values (especially an update of CL, CWL, and WR may be necessary. After tMOD satisfied from any proceeding MRS command, a ZQCL command may also be issued during or after tDLLK). 9. Wait for tMOD, then DRAM is ready for next command (remember to wait tDLLK after DLL Reset before applying command requiring a locked DLL!). In addition, wait also for tZQoper in case a ZQCL command was issued. Version 1.9 02/2017 37 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP DLL Switch Sequence from DLL-off to DLL-on T0 Ta0 NOP SRE 2) Ta1 Tb0 Tc0 Tc1 Td0 Te0 Tf1 Tg0 Th0 SRX 5) MRS 6) MRS 7) MRS 8) Valid CK CK CMD 1) ODTLoff + 1tck NOP tCKSRE 3) tCKSRX 4) tXS tMRD tMRD tDLLK CKE Valid tCKESR ODT Note: ODT: Static LOW in case RTT_Nom and RTT_WR is enabled, otherwise static Low or High 1) Starting from Idle State. 2) Enter SR. 3) Change Frequency. 4) Clock must be stable at least tCKSRX. 5) Exit SR. 6) Set DLL-on by MR1 A0="0" 7) Start DLL Reset 8) Any valid command Version 1.9 02/2017 38 Time break Do not Care Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Input Clock frequency change Once the DDR3(L) SDRAM is initialized, the DDR3(L) SDRAM requires the clock to be “stable” during almost all states of normal operation. This means once the clock frequency has been set and is to be in the “stable state”, the clock period is not allowed to deviate except for what is allowed for by the clock jitter and SSC (spread spectrum clocking) specification. The input clock frequency can be changed from one stable clock rate to another stable clock rate under two conditions: (1) Self-Refresh mode and (2) Precharge Power-Down mode. Outside of these two modes, it is illegal to change the clock frequency. For the first condition, once the DDR3(L) SDRAM has been successfully placed in to Self-Refresh mode and tCKSRE has been satisfied, the state of the clock becomes a don’t care. Once a don’t care, changing the clock frequency is permissible, provided the new clock frequency is stable prior to tCKSRX. When entering and exiting Self-Refresh mode of the sole purpose of changing the clock frequency. The DDR3(L) SDRAM input clock frequency is allowed to change only within the minimum and maximum operating frequency specified for the particular speed grade. The second condition is when the DDR3(L) SDRAM is in Precharge Power-Down mode (either fast exit mode or slow exit mode). If the RTT_Nom feature was enabled in the mode register prior to entering Precharge power down mode, the ODT signal must continuously be registered LOW ensuring RTT is in an off state. If the RTT_Nom feature was disabled in the mode register prior to entering Precharge power down mode, RTT will remain in the off state. The ODT signal can be registered either LOW or HIGH in this case. A minimum of tCKSRE must occur after CKE goes LOW before the clock frequency may change. The DDR3(L) SDRAM input clock frequency is allowed to change only within the minimum and maximum operating frequency specified for the particular speed grade. During the input clock frequency change, ODT and CKE must be held at stable LOW levels. Once the input clock frequency is changed, stable new clocks must be provided to the DRAM tCKSRX before precharge Power Down may be exited; after Precharge Power Down is exited and tXP has expired, the DLL must be RESET via MRS. Depending on the new clock frequency additional MRS commands may need to be issued to appropriately set the WR, CL, and CWL with CKE continuously registered high. During DLL re-lock period, ODT must remain LOW and CKE must remain HIGH. After the DLL lock time, the DRAM is ready to operate with new clock frequency. Version 1.9 02/2017 39 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Change Frequency during Precharge Power-down Previous Clock Frequency T0 T1 T2 New Clock Frequency Ta0 Tb0 Tc0 Tc1 Td0 Td1 Te0 Te1 NOP MRS NOP Valid tCKb tCHb tCLb tCK CK CK tCH tCL tCKSRE tCKSRX CKE tIH tIS tIH tCPDED tIS tCKE Command NOP NOP NOP NOP DLL Reset Address tAOFPD/tAOF Valid tXP ODT tIH DQS, DQS High-Z DQ High-Z tIS tDLLK DM Enter Precharge Power-Down mode Exit Precharge Power-Down mode Frequency Change NOTES: 1. Applicable for both SLOW EXIT and FAST EXIT Precharge Power-down 2. tAOFPD and tAOF must be statisfied and outputs High-Z prior to T1; refer to ODT timing section for exact requirements 3. If the RTT_NOM feature was enabled in the mode register prior to entering Precharge power down mode, the ODT signal must continuously be registered LOW ensuring RTT is in an off state. If the RTT_NOM feature was disabled in the mode register prior to entering Precharge power down mode, RTT will remain in the off state. The ODT signal can be registered either LOW or HIGH in this case. Version 1.9 02/2017 40 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Write Leveling For better signal integrity, DDR3(L) memory adopted fly by topology for the commands, addresses, control signals, and clocks. The fly by topology has benefits from reducing number of stubs and their length but in other aspect, causes flight time skew between clock and strobe at every DRAM on DIMM. It makes it difficult for the Controller to maintain tDQSS, tDSS, and tDSH specification. Therefore, the controller should support “write leveling” in DDR3(L) SDRAM to compensate the skew. The memory controller can use the “write leveling” feature and feedback from the DDR3(L) SDRAM to adjust the DQS  to CK -  relationship. The memory controller involved in the leveling must have adjustable delay setting on DQS  to align the rising edge of DQS -  with that of the clock at the DRAM pin. DRAM asynchronously feeds back CK , sampled with the rising edge of DQS - , through the DQ bus. The controller repeatedly delays DQS - until a transition from 0 to 1 is detected. The DQS -  delay established though this exercise would ensure tDQSS specification. Besides tDQSS, tDSS, and tDSH specification also needs to be fulfilled. One way to achieve this is to combine the actual tDQSS in the application with an appropriate duty cycle and jitter on the DQS- signals. Depending on the actual tDQSS in the application, the actual values for tDQSL and tDQSH may have to be better than the absolute limits provided in “AC Timing Parameters” section in order to satisfy tDSS and tDSH specification. A conceptual timing of this scheme is show as below figure. Write Leveling Concept Diff_CK Source Diff _ DQS Diff _ CK Destination Diff_DQS DQ 0 or 1 0 0 0 Push DQS to capture 0 -1 transition DQ 0 or 1 1 1 1 DQS/ driven by the controller during leveling mode must be determined by the DRAM based on ranks populated. Similarly, the DQ bus driven by the DRAM must also be terminated at the controller. A separated feedback mechanism should be able for each byte lane. The low byte lane’s prime DQ, DQ0, carries the leveling feedback to the controller across the DRAM configurations x4/x8 whereas DQ0 indicates the lower diff_DQS (diff_LDQS) to clock relationship. The high byte lane’s prime DQ, DQ8, provides the feedback of the upper diff_DQS (diff_UDQS) to clock relationship Version 1.9 02/2017 41 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP DRAM setting for write leveling and DRAM termination unction in that mode DRAM enters into Write leveling mode if A7 in MR1 set “High” and after finishing leveling, DRAM exits from write leveling mode if A7 in MR1 set “Low”. Note that in write leveling mode, only DQS/ terminations are activated and deactivated via ODT pin not like normal operation. MR setting involved in the leveling procedure Function MR1 Enable Disable Write leveling enable A7 1 0 Output buffer mode (Qoff) A12 0 1 DRAM termination function in the leveling mode ODT pin at DRAM DQS/ termination DQs termination De-asserted off off Asserted on off Note: In write leveling mode with its output buffer disabled (MR1[bit7]=1 with MR1[bit12]=1) all RTT_Nom settings are allowed; in Write Leveling Mode with its output buffer enabled (MR1[bit7]=1 with MR1[bit12]=0) only RTT_Nom settings of RZQ/2, RZQ/4, and RZQ/6 are allowed. Procedure Description Memory controller initiates Leveling mode of all DRAMs by setting bit 7 of MR1 to 1. With entering write leveling mode, the DQ pins are in undefined driving mode. During write leveling mode, only NOP or Deselect commands are allowed. As well as an MRS command to exit write leveling mode. Since the controller levels one rank at a time, the output of other rank must be disabled by setting MR1 bit A12 to 1. Controller may assert ODT after tMOD, time at which DRAM is ready to accept the ODT signal. Controller may drive DQS low and  high after a delay of tWLDQSEN, at which time DRAM has applied on-die termination on these signals. After tDQSL and tWLMRD controller provides a single DQS, edge which is used by the DRAM to sample CK –  driven from controller. tWLMRD (max) timing is controller dependent. DRAM samples CK -  status with rising edge of DQS and provides feedback on all the DQ bits asynchronously after tWLO timing. There is a DQ output uncertainty of tWLOE defined to allow mismatch on DQ bits; there are no read strobes (DQS/DQS) needed for these DQs. Controller samples incoming DQ and decides to increment or decrement DQS –  delay setting and launches the next DQS/ pulse after some time, which is controller dependent. Once a 0 to 1 transition is detected, the controller locks DQS – delay setting and write leveling is achieved for the device. The following figure describes the timing diagram and parameters for the overall Write leveling procedure. Version 1.9 02/2017 42 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Timing details of Write leveling sequence (For Information. Only Support prime DQ) DQS -  is capturing CK -  low at T1 and CK -  high at T2 T1 tWLS T2 t WLH tWLS t WLH CK CK CMD M RS NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP tMOD ODT t DQSL tWLDQSEN tDQSH tDQSL tDQSH Di ff_ DQS tWLMR D On e Pri me DQ: tWLO t WLO Prime DQ t WLO Late Re ma ini ng DQs Earl y Re ma ini ng DQs tWLO All DQs are Prime : tWLMRD tWLOE t WLO tWLO Late Re ma ini ng DQs t WLOE Earl y Re ma ini ng DQs tWLO tWLOE t WLO Undefined Driving Mode Time break Do not Care Note: 1. DRAM has the option to drive leveling feedback on a prime DQ or all DQs. If feedback is driven only on one DQ, the remaining DQs must be driven low as shown in above Figure, and maintained at this state through out the leveling procedure. 2. MRS: Load MR1 to enter write leveling mode 3. NOP: NOP or deselect 4. diff_DQS is the differential data strobe (DQS, ). Timing reference points are the zero crossings. DQS is shown with solid line,  is shown with dotted line. 6. DQS/ needs to fulfill minimum pulse width requirements tDQSH(min) and tDQSL(min) as defined for regular Writes; the max pulse width is system dependent. Write Leveling Mode Exit The following sequence describes how Write Leveling Mode should be exited: 1. After the last rising strobe edge (see ~T0), stop driving the strobe signals (see ~Tc0). Note: From now on, DQ pins are in undefined driving mode, and will remain undefined, until tMOD after the respective MR command (Te1). 2. Drive ODT pin low (tIS must be satisfied) and keep it low (see Tb0). 3. After the RTT is switched off, disable Write Level Mode via MRS command (see Tc2). 4. After tMOD is satisfied (Te1), any valid command may be registered. (MR commands may be issued after tMRD (Td1). Version 1.9 02/2017 43 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Timing detail of Write Leveling exit T0 T1 NOP NOP T2 Ta0 Tb0 Tc0 Tc1 NOP NOP Tc2 Td0 Td1 Te0 Te1 NOP Valid NOP Valid CK CK CMD NOP NOP NOP MRS tMOD MR1 BA Valid Valid tMRD ODT tIS tWLO RTT_DQS_DQS tAOFmin tODTLoff RTT_Nom tAOFmax DQS_DQS DQ Result = 1 Time Break Transitioning Do not Care Undefined Driving Mode Extended Temperature Usage Nanya’s DDR3(L) SDRAM supports the optional extended temperature range of 0°C to +95°C, TC. Thus, the SRT and ASR options must be used at a minimum. The extended temperature range DRAM must be refreshed externally at 2X (double refresh) anytime the case temperature is above +85°C (in supporting temperature range). The external refreshing requirement is accomplished by reducing the refresh period from 64ms to 32ms. However, self refresh mode requires either ASR or SRT to support the extended temperature. Thus either ASR or SRT must be enabled when TC is above +85°C or self refresh cannot be used until the case temperature is at or below +85°C. Mode Register Description Field Bits Description Auto Self-Refresh (ASR) When enabled, DDR3(L) SDRAM automatically provides Self-Refresh power management functions for all supported operating temperature values. If not enabled, the SRT bit must be programmed to indicate TOPER ASR MR2(A6) during subsequent Self-Refresh operation. 0 = Manual SR Reference (SRT) 1 = ASR enable Self-Refresh Temperature (SRT) Range If ASR = 0, the SRT bit must be programmed to indicate TOPER during subsequent Self-Refresh operation. If SRT MR2(A7) ASR = 1, SRT bit must be set to 0. 0 = Normal operating temperature range 1 = Extended operating temperature range Version 1.9 02/2017 44 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Auto Self-Refresh mode - ASR mode DDR3(L) SDRAM provides an Auto-Refresh mode (ASR) for application ease. ASR mode is enabled by setting MR2 bit A6=1 and MR2 bit A7=0. The DRAM will manage Self-Refresh entry in either the Normal or Extended Temperature Ranges. In this mode, the DRAM will also manage Self-Refresh power consumption when the DRAM operating temperature changes, lower at low temperatures and higher at high temperatures. If the ASR option is not supported by DRAM, MR2 bit A6 must set to 0. If the ASR option is not enabled (MR2 bit A6=0), the SRT bit (MR2 bit A7) must be manually programmed with the operating temperature range required during Self-Refresh operation. Support of the ASR option does not automatically imply support of the Extended Temperature Range. Self-Refresh Temperature Range - SRT SRT applies to devices supporting Extended Temperature Range only. If ASR=0, the Self-Refresh Temperature (SRT) Range bit must be programmed to guarantee proper self-refresh operation. If SRT=0, then the DRAM will set an appropriate refresh rate for Self-Refresh operation in the Normal Temperature Range. If SRT=1, then the DRAM will set an appropriate, potentially different, refresh rate to allow Self-Refresh operation in either the Normal or Extended Temperature Ranges. The value of the SRT bit can effect self-refresh power consumption, please refer to IDD table for details. Self-Refresh mode summary MR2 A[6] MR2 A[7] 0 0 0 1 Allowed Operating Temperature Range for Self-Refresh mode Self-Refresh operation Normal 1 Self-Refresh rate appropriate for the Normal Temperature Range Self-Refresh appropriate for either the Normal or Extended Temperature Ranges. The DRAM must support Extended Temperature Range. The value of the SRT bit can Normal and Extended 2 effect self-refresh power consumption, please refer to the IDD table for details. 1 0 1 0 1 1 ASR enabled (for devices supporting ASR and Normal Temperature Range). Normal 1 Self-Refresh power consumption is temperature dependent. ASR enabled (for devices supporting ASR and Extended Temperature Range). Normal and Extended 2 Self-Refresh power consumption is temperature dependent. Illegal NOTES: 1. The Normal range depends on product’s grade. - Commercial Grade = 0℃~85℃ - Quasi Industrial Grade (-T) = -40℃~85℃ - Industrial Grade (-I) = -40℃~85℃ - Automotive Grade 2 (-H) = -40℃~85℃ - Automotive Grade 3 (-A) = -40℃~85℃ 2. The Normal and Extended range depends on product’s grade. - Commercial Grade = 0℃~95℃ - Quasi Industrial Grade (-T) = -40℃~95℃ - Industrial Grade (-I) = -40℃~95℃ - Automotive Grade 2 (-H) = -40℃~105℃ - Automotive Grade 3 (-A) = -40℃~95℃ Version 1.9 02/2017 45 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP MPR MR3 Register Definition MR3 A[2] MR3 A[1:0] 0 don't care (0 or 1) 1 See the following table Function Normal operation, no MPR transaction. All subsequent Reads will come from DRAM array. All subsequent Writes will go to DRAM array. Enable MPR mode, subsequent RD/RDA commands defined by MR3 A[1:0]. MPR Functional Description • One bit wide logical interface via all DQ pins during READ operation. • Register Read on x8: • DQ[0] drives information from MPR. • DQ[7:1] either drive the same information as DQ [0], or they drive 0b. • Register Read on x16: • DQL[0] and DQU[0] drive information from MPR. • DQL[7:1] and DQU[7:1] either drive the same information as DQL [0], or they drive 0b. • Addressing during for Multi Purpose Register reads for all MPR agents: • BA [2:0]: don’t care • A[1:0]: A[1:0] must be equal to ‘00’b. Data read burst order in nibble is fixed • A[2]: For BL=8, A[2] must be equal to 0b, burst order is fixed to [0,1,2,3,4,5,6,7], *) For Burst Chop 4 cases, the burst order is switched on nibble base A [2]=0b, Burst order: 0,1,2,3 *) A[2]=1b, Burst order: 4,5,6,7 *) • A[9:3]: don’t care • A10/AP: don’t care • A12/BC: Selects burst chop mode on-the-fly, if enabled within MR0. • A11, A13... (if available): don’t care • Regular interface functionality during register reads: • Support two Burst Ordering which are switched with A2 and A[1:0]=00b. • Support of read burst chop (MRS and on-the-fly via A12/BC) • All other address bits (remaining column address bits including A10, all bank address bits) will be ignored by the DDR3(L) SDRAM. • Regular read latencies and AC timings apply. • DLL must be locked prior to MPR Reads. NOTE: *Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent. Version 1.9 02/2017 46 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP MPR Register Address Definition The following table provide an overview of the available data location, how they are addressed by MR3 A[1:0] during a MRS to MR3, and how their individual bits are mapped into the burst order bits during a Multi Purpose Register Read. MPR MR3 Register Definition MR3 A[2] MR3 A[1:0] Function Burst Length Read Address A[2:0] Read BL8 000 Burst Order and Data Pattern Burst order 0,1,2,3,4,5,6,7 Pre-defined Data Pattern [0,1,0,1,0,1,0,1] Predefined 1 00 Pattern for 000 BC4 Burst order 0,1,2,3 Pre-defined Data Pattern [0,1,0,1] System Calibration 100 BC4 Burst order 4,5,6,7 Pre-defined Data Pattern [0,1,0,1] 1 1 1 01 10 11 RFU RFU RFU BL8 000 Burst order 0,1,2,3,4,5,6,7 BC4 000 Burst order 0,1,2,3 BC4 100 Burst order 4,5,6,7 BL8 000 Burst order 0,1,2,3,4,5,6,7 BC4 000 Burst order 0,1,2,3 BC4 100 Burst order 4,5,6,7 BL8 000 Burst order 0,1,2,3,4,5,6,7 BC4 000 Burst order 0,1,2,3 BC4 100 Burst order 4,5,6,7 Note: Burst order bit 0 is assigned to LSB and the burst order bit 7 is assigned to MSB of the selected MPR agent. ACTIVE Command The ACTIVE command is used to open (or activate) a row in a particular bank for subsequent access. The value on the BA0-BA2 inputs selects the bank, and the addresses provided on inputs A0-A15 selects the row. These rows remain active (or open) for accesses until a precharge command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. Version 1.9 02/2017 47 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP PRECHARGE Command The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row activation a specified time (tRP) after the PRECHARGE command is issued, except in the case of concurrent auto precharge, where a READ or WRITE command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command is allowed if there is no open row in that bank (idle bank) or if the previously open row is already in the process of precharging. However, the precharge period will be determined by the last PRECHARGE command issued to the bank. Version 1.9 02/2017 48 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP READ Operation Read Burst Operation During a READ or WRITE command DDR3(L) will support BC4 and BL8 on the fly using address A12 during the READ or WRITE (AUTO PRECHARGE can be enabled or disabled). A12=0, BC4 (BC4 = burst chop, tCCD=4) A12=1, BL8 A12 is used only for burst length control, not as a column address. Read Burst Operation RL=5 (AL=0, CL=5, BL=8) T0 T1 T2 T3 NOP NOP NOP T4 T5 T6 NOP NOP T7 T8 T9 T10 NOP NOP NOP CK CK CMD READ Address Bank Col n NOP NOP tRPST tRPRE DQS, DQS Dout n DQ CL=5 RL = AL + CL Dout n +1 Dout n +2 Dout n +3 Dout n +4 Dout n +5 Dout n +6 Dout n +7 Notes:. 1. BL8, RL = 5, AL = 0, CL = 5. 2. DOUT n = data-out from column n. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during READ command at T0. READ Burst Operation RL = 9 (AL=4, CL=5, BL=8) T0 T1 T2 T3 NOP NOP NOP T4 T5 T6 NOP NOP T7 T8 T9 T10 NOP NOP NOP CK CK CMD READ Address Bank Col n NOP NOP AL = 4 tRPRE DQS, DQS CL=5 Dout n DQ RL = AL + CL Dout n +1 Dout n +2 Notes:. 1. BL8, RL = 9, AL = (CL - 1), CL = 5. 2. DOUT n = data-out from column n. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during READ command at T0. Version 1.9 02/2017 49 Nanya Technology Cooperation © All Rights Reserved. Dout n +3 DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP READ Timing Definitions Read timing is shown in the following figure and is applied when the DLL is enabled and locked. Rising data strobe edge parameters: • tDQSCK min/max describes the allowed range for a rising data strobe edge relative to CK, . • tDQSCK is the actual position of a rising strobe edge relative to CK, . • tQSH describes the DQS,  differential output high time. • tDQSQ describes the latest valid transition of the associated DQ pins. • tQH describes the earliest invalid transition of the associated DQ pins. Falling data strobe edge parameters: • tQSL describes the DQS,  differential output low time. • tDQSQ describes the latest valid transition of the associated DQ pins. • tQH describes the earliest invalid transition of the associated DQ pins. tDQSQ; both rising/falling edges of DQS, no tAC defined. READ Timing Definition Version 1.9 02/2017 50 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Read Timing; Clock to Data Strobe relationship Clock to Data Strobe relationship is shown in the following figure and is applied when the DLL is enabled and locked. Rising data strobe edge parameters: • tDQSCK min/max describes the allowed range for a rising data strobe edge relative to CK and . • tDQSCK is the actual position of a rising strobe edge relative to CK and . • tQSH describes the data strobe high pulse width. Falling data strobe edge parameters: • tQSL describes the data strobe low pulse width. Clock to Data Strobe Relationship RL Measured to this point CK CK tLZ(DQS)min tDQSCKmin tQSH tRPRE tQSL tRPST tHZ(DQS)min DQS, DQS Early Strobe tHZ(DQS)max tDQSCKmax tLZ(DQS)max tRPST DQS, DQS Late Strobe tRPRE NOTES: 1. Within a burst, rising strobe edge is not necessarily fixed to be always at tDQSCK(min) or tDQSCK(max). Instead, rising strobe edge can vary between tDQSCK(min) and tDQSCK(max). 2. The DQS,  differential output high time is defined by tQSH and the DQS,  differential output low time is defined by tQSL. 3. Likewise, tLZ(DQS)min and tHZ(DQS)min are not tied to tDQSCKmin (early strobe case) and tLZ(DQS)max and tHZ(DQS)max are not tied to tDQSCKmax (late strobe case). 4. The minimum pulse width of read preamble is defined by tRPRE(min). 5. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZDSQ(max) on the right side. 6. The minimum pulse width of read postamble is defined by tRPST(min). 7. The maximum read preamble is bound by tLZDQS(min) on the left side and tDQSCK(max) on the right side. Version 1.9 02/2017 51 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Read Timing; Data Strobe to Data Relationship The Data Strobe to Data relationship is shown in the following figure and is applied when the DLL is enabled and locked. Rising data strobe edge parameters: • tDQSQ describes the latest valid transition of the associated DQ pins. • tQH describes the earliest invalid transition of the associated DQ pins. Falling data strobe edge parameters: • tDQSQ describes the latest valid transition of the associated DQ pins. • tQH describes the earliest invalid transition of the associated DQ pins. • tDQSQ; both rising/falling edges of DQS, no tAC defined Data Strobe to Data Relationship T0 T1 T2 T3 NOP NOP NOP T4 T5 T6 NOP NOP T7 T8 T9 NOP NOP CK CK CMD READ Address Bank Col n NOP tRPRE NOP tDQSQmax tQH tRPST DQS, DQS tLZ(DQ)min RL = AL + CL tDQSQmin Dout n DQ (Last data valid) DQ (First data no longer valid) Dout n Dout n +1 Dout n +1 tHZ(DQ)min tQH Dout n +2 Dout n +2 Dout n +3 Dout n +3 Dout n +4 Dout n +4 Dout n +5 Dout n +5 Dout n +6 Dout n +6 Dout n +7 Dout n +7 All DQ collectively Valid data Valid data Notes: 1. BL = 8, RL = 5 (AL = 0, CL = 5) 2. DOUT n = data-out from column n. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during READ command at T0. 5. Output timings are referenced to VDDQ/2, and DLL on for locking. 6. tDQSQ defines the skew between DQS, to Data and does not define DQS,  to Clock. 7. Early Data transitions may not always happen at the same DQ. Data transitions of a DQ can vary (either early or late) within a burst. Version 1.9 02/2017 52 Nanya Technology Cooperation © All Rights Reserved. Version 1.9 02/2017 Bank Col n Address 53 Bank Col n Address DQ DQS, DQS READ CMD DQ DQS, DQS READ CMD CK CK T0 NOP NOP T1 tCCD NOP tCCD NOP T2 RL = 5 RL = 5 NOP NOP T3 READ READ Bank Col b READ Bank Col b READ T4 tRPRE tRPRE NOP NOP T5 Dout n Dout n Dout n +1 Dout n +1 NOP NOP T6 Dout n +2 NOP tRPST Dout n +3 Dout n +3 RL = 5 Dout n +2 RL = 5 NOP T7 Dout n +5 Dout n +6 Dout n +7 NOP T9 tRPRE NOP READ (BL4) to READ (BL4) NOP READ (BL8) to READ (BL8) Dout n +4 NOP T8 Dout b Dout b Dout b +1 Dout b +1 NOP NOP T10 Dout b +2 Dout b +2 NOP Dout b +3 tRPST Dout b +3 NOP T11 Dout b +4 Dout b +5 NOP NOP T12 Dout b +6 Dout b +7 NOP tRPST NOP T13 DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Read to Read (CL=5, AL=0) Nanya Technology Cooperation © All Rights Reserved. Version 1.9 02/2017 Bank Col n Address 54 Bank Col n Address DQ DQS, DQS READ CMD DQ DQS, DQS READ CMD CK CK T0 NOP T3 NOP T4 tRPRE NOP NOP READ RL = 5 Bank Col b WRITE tRPRE READ to Write Command delay = RL +tCCD + 2tCK -WL RL = 5 NOP T2 READ to WRITE Command Delay = RL + tCCD/2 + 2tCK - WL NOP NOP T1 NOP NOP T5 Dout n Dout n Dout n +1 Dout n +1 NOP Bank Col b Dout n +2 Dout n +3 Dout n +5 Dout n +6 Dout n +7 WL = 5 tRPST NOP T9 NOP tWPRE Dout b NOP READ (BL8) to WRITE (BL8) Dout n +4 NOP T8 READ (BL4) to WRITE (BL4) NOP NOP T7 tRPST Dout n +3 WL = 5 Dout n +2 WRITE T6 Dout b +1 Dout b +2 NOP NOP T10 NOP Dout b Dout b +3 tBL = 4 clocks tWPST tWRPRE NOP T11 Dout b +1 NOP Dout b +2 NOP T12 Dout b +3 NOP Dout b +4 NOP T13 Dout b +5 NOP Dout b +6 NOP T14 tWR tWTR Dout b +7 NOP tWPST NOP T15 DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP READ to WRITE (CL=5, AL=0; CWL=5, AL=0) Nanya Technology Cooperation © All Rights Reserved. Version 1.9 02/2017 Bank Col n Address 55 Bank Col n Address DQ DQS, DQS READ CMD DQ DQS, DQS READ CMD CK CK T0 NOP NOP T1 tCCD NOP tCCD NOP T2 RL = 5 RL = 5 NOP NOP T3 READ READ Bank Col b READ Bank Col b READ T4 tRPRE tRPRE NOP NOP T5 Dout n Dout n Dout n +1 Dout n +1 NOP NOP T6 Dout n +2 NOP tRPST Dout n +3 Dout n +3 RL = 5 Dout n +2 RL = 5 NOP T7 Dout n +5 Dout n +6 Dout n +7 NOP T9 tRPRE NOP READ (BC4) to READ (BL8) NOP READ (BL8) to READ (BC4) Dout n +4 NOP T8 Dout b Dout b Dout b +1 Dout b +1 NOP NOP T10 Dout b +2 Dout b +2 Dout b +3 Dout b +3 NOP tRPST NOP T11 Dout b +4 Dout b +5 NOP NOP T12 Dout b +6 Dout b +7 tRPST NOP NOP T13 DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP READ to READ (CL=5, AL=0) Nanya Technology Cooperation © All Rights Reserved. Version 1.9 02/2017 Bank Col n Address 56 Bank Col n Address DQ DQS, DQS READ CMD DQ DQS, DQS READ CMD CK CK T0 NOP T3 NOP T4 tRPRE NOP NOP READ RL = 5 Bank Col b WRITE tRPRE READ to Write Command delay = RL +tCCD + 2tCK -WL RL = 5 NOP T2 READ to WRITE Command Delay = RL + tCCD/2 + 2tCK - WL NOP NOP T1 NOP NOP T5 Dout n Dout n Dout n +1 Dout n +1 NOP Bank Col b Dout n +2 Dout n +3 Dout n +5 Dout n +6 Dout n +7 WL = 5 tRPST NOP T9 NOP tWPRE Dout b NOP READ (BL8) to WRITE (BL8) Dout n +4 NOP T8 READ (BL4) to WRITE (BL4) NOP NOP T7 tRPST Dout n +3 WL = 5 Dout n +2 WRITE T6 Dout b +1 Dout b +2 NOP NOP T10 NOP Dout b Dout b +3 tBL = 4 clocks tWPST tWRPRE NOP T11 Dout b +1 NOP Dout b +2 NOP T12 Dout b +3 NOP Dout b +4 NOP T13 Dout b +5 NOP Dout b +6 NOP T14 tWR tWTR Dout b +7 NOP tWPST NOP T15 DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP READ to WRITE (CL=5, AL=0; CWL=5, AL=0) Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Write Operation DDR3(L) Burst Operation During a READ or WRITE command, DDR3(L) will support BC4 and BL8 on the fly using address A12 during the READ or WRITE (Auto Precharge can be enabled or disabled). A12=0, BC4 (BC4 = Burst Chop, tCCD=4) A12=1, BL8 A12 is used only for burst length control, not as a column address. WRITE Timing Violations Motivation Generally, if timing parameters are violated, a complete reset/initialization procedure has to be initiated to make sure the DRAM works properly. However, it is desirable for certain minor violations that the DRAM is guaranteed not to “hang up” and errors be limited to that particular operation. For the following, it will be assumed that there are no timing violations with regard to the Write command itself (including ODT, etc.) and that it does satisfy all timing requirements not mentioned below. Data Setup and Hold Violations Should the data to strobe timing requirements (tDS, tDH) be violated, for any of the strobe edges associated with a write burst, then wrong data might be written to the memory location addressed with the offending WRITE command. Subsequent reads from that location might result in unpredictable read data, however, the DRAM will work properly otherwise. Strobe to Strobe and Strobe to Clock Violations Should the strobe timing requirements (tDQSH, tDQSL, tWPRE, tWPST) or the strobe to clock timing requirements (tDSS, tDSH, tDQSS) be violated, for any of the strobe edges associated with a Write burst, then wrong data might be written to the memory location addressed with the offending WRITE command. Subsequent reads from that location might result in unpredictable read data, however the DRAM will work properly otherwise. Write Timing Parameters This drawing is for example only to enumerate the strobe edges that “belong” to a write burst. No actual timing violations are shown here. For a valid burst all timing parameters for each edge of a burst need to be satisfied (not only for one edge as shown). Version 1.9 02/2017 57 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Write Timing Definition T0 T1 T2 T3 CMD Write NOP NOP NOP Address Bank Col n T4 T5 T6 NOP NOP T7 T8 T9 Tn NOP NOP NOP CK CK NOP NOP tDSH tDSH tDSH tDQSS tDSH tWPST(min) tDSS tWPRE(min) DQS, DQS (tDQSS min) tDQSH tDQSL tDQSH Din n DQ tDQSH tDSS tDSS Din n +1 tDQSL(min) tDSS Din n +2 Din n +3 Din n +4 Din n +5 Din n +6 Din n +7 tDSS WL = AL + CWL tWPST(min) tDSH tDSH tDSH tDSH tDSS tWPRE(min) DQS, DQS (tDQSS nominal) tDQSH tDQSL tDQSH Din n DQ Din n +1 tDQSH tDSS tDSS tDQSL(min) tDSS Din n +2 Din n +3 Din n +4 Din n +5 Din n +6 Din n +7 tDSS tDSH tDQSS tDSH tWPRE(min) tWPST(min) tDSH tDSH DQS, DQS (tDQSS max) tDSS tDQSH tDQSL Din n DQ tDSS tDSS tDQSH Din n +1 Din n +2 Din n +3 Din n +4 Din n +5 tDQSH Din n +6 tDSS tDQSL(min) Din n +7 tDSS Note: 1. BL=8, WL=5 (AL=0, CWL=5). 2. Din n = data in from column n. 3. NOP commands are shown for ease of illustration; other command may be valid at these times. 4. BL8 setting activated by either MR0 [A1:0=00] or MR0 [A1:0=01] and A12 = 1 during WRITE command at T0. 5. tDQSS must be met at each rising clock edge. Version 1.9 02/2017 58 Nanya Technology Cooperation © All Rights Reserved. Version 1.9 02/2017 Bank Col n Address 59 Bank Col n Address DQ DQS, DQS WRITE CMD DQ DQS, DQS WRITE CMD CK CK T0 NOP NOP T1 WL = 5 NOP T3 WL = 5 NOP READ WRITE (BC4) to WRITE (BC4) tCCD NOP WRITE (BL8) to WRITE (BL8) tCCD NOP T2 Bank Col b WRITE Bank Col b WRITE T4 tWPRE tWPRE Dout n NOP Dout n NOP T5 Dout n +1 Dout n +1 Dout n +2 NOP Dout n +2 NOP T6 NOP Dout n +4 Dout n +3 WL = 5 tWPST WL = 5 Dout n +3 NOP T7 Dout n +5 NOP Dout n +6 NOP T8 tWPRE Dout n +7 Dout b NOP Dout b NOP T9 Dout b +1 Dout b +1 Dout b +2 NOP Dout b +2 NOP T10 tBL=4 NOP Dout b +4 Dout b +3 tWPST Dout b +3 tBL=4 NOP T11 Dout b +5 NOP Dout b +6 NOP T12 Dout b +7 NOP tWPST NOP T13 tWTR tWR tWTR tWR DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP WRITE to WRITE (WL=5; CWL=5, AL=0) Nanya Technology Cooperation © All Rights Reserved. Version 1.9 02/2017 Bank Col n Address 60 Bank Col n Address DQ DQS, DQS WRITE CMD DQ DQS, DQS WRITE CMD CK CK T0 NOP NOP T1 WL = 5 NOP T3 WL = 5 NOP WRITE (BC4) to READ (BC4/BL8) NOP WRITE (BL8) to READ (BC4/BL8) NOP T2 NOP NOP T4 tWPRE tWPRE NOP Dout n NOP T5 Dout n Dout n +1 Dout n +1 NOP Dout n +2 NOP T6 Dout n +2 NOP Dout n +4 tBL=4 Dout n +3 tWPST Dout n +3 NOP T7 Dout n +5 NOP Dout n +6 NOP T8 Dout n +7 NOP tWPST NOP T9 NOP NOP T10 tWTR NOP tWTR NOP T11 NOP NOP T12 Bank Col b READ Bank Col b READ T13 RL=5 RL=5 DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP WRITE to READ (RL=5, CL=5, AL=0; WL=5, CWL=5, AL=0; BL=4) Nanya Technology Cooperation © All Rights Reserved. Version 1.9 02/2017 Bank Col n Address 61 Bank Col n Address DQ DQS, DQS WRITE CMD DQ DQS, DQS WRITE CMD CK CK T0 NOP NOP T1 WL = 5 NOP T3 WL = 5 NOP READ WRITE (BC4) to WRITE (BL8) tCCD NOP WRITE (BL8) to WRITE (BC4) tCCD NOP T2 Bank Col b WRITE Bank Col b WRITE T4 tWPRE tWPRE Dout n NOP Dout n NOP T5 Dout n +1 Dout n +1 Dout n +2 NOP Dout n +2 NOP T6 NOP Dout n +4 Dout n +3 WL = 5 tWPST WL = 5 Dout n +3 NOP T7 Dout n +5 NOP Dout n +6 NOP T8 tWPRE Dout n +7 Dout b NOP Dout b NOP T9 Dout b +1 Dout b +1 Dout b +2 NOP Dout b +2 NOP T10 Dout b +3 Dout b +3 Dout b +3 tBL=4 NOP tWPST tBL=4 NOP T11 Dout b +4 Dout b +5 NOP NOP T12 Dout b +6 Dout b +7 tWPST NOP NOP T13 tWTR tWR tWTR tWR DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP WRITE to WRITE (WL=5, CWL=5, AL=0) Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Refresh Command The Refresh command (REF) is used during normal operation of the DDR3(L) SDRAMs. This command is not persistent, so it must be issued each time a refresh is required. The DDR3(L) SDRAM requires Refresh cycles at an average periodic interval of tREFI. When , RA, and A are held Low and WE High at the rising edge of the clock, the chip enters a Refresh cycle. All banks of the SDRAM must be precharged and idle for a minimum of the precharge time tRP(min) before the Refresh Command can be applied. The refresh addressing is generated by the internal refresh controller. This makes the address bits “Don’t Care” during a Refresh command. An internal address counter suppliers the address during the refresh cycle. No control of the external address bus is required once this cycle has started. When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the Refresh Command and the next valid command, except NOP or DES, must be greater than or equal to the minimum Refresh cycle time tRFC(min) as shown in the following figure. In general, a Refresh command needs to be issued to the DDR3(L) SDRAM regularly every tREFI interval. To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of 8 Refresh commands can be postponed during operation of the DDR3(L) SDRAM, meaning that at no point in time more than a total of 8 Refresh commands are allowed to be postponed. In case that 8 Refresh commands are postponed in a row, the resulting maximum interval between the surrounding Refresh commands is limited to 9 x tREFI. A maximum of 8 additional Refresh commands can be issued in advance (“pulled in”), with each one reducing the number of regular Refresh commands required later by one. Note that pulling in more than 8 Refresh commands in advance does not further reduce the number of regular Refresh commands required later, so that the resulting maximum interval between two surrounding Refresh command is limited to 9 x tREFI. Before entering Self-Refresh Mode, all postponed Refresh commands must be executed. Self-Refresh Entry/Exit Timing T0 T1 REF NOP Ta0 Ta1 Tb0 Tb1 Tb2 Tb3 Valid Valid Tc0 Tc1 CK CK CMD NOP tRFC REF NOP NOP Valid Valid Valid REF Valid tRFC(min) DRAM must be idle tREFI (max, 9 x tREFI) DRAM must be idle Time Break Postponing Refresh Commands (Example) tREFI 9 x tREFI t tREFI 8 REF-Command postponed Version 1.9 02/2017 62 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Pulled-in Refresh Commands (Example) tREFI 9 x tREFI t tREFI 8 REF-Commands pulled-in Self-Refresh Operation The Self-Refresh command can be used to retain data in the DDR3(L) SDRAM, even if the rest of the system is powered down. When in the Self-Refresh mode, the DDR3(L) SDRAM retains data without external clocking. The DDR3(L) SDRAM device has a built-in timer to accommodate Self-Refresh operation. The Self-Refresh Entry (SRE) Command is defined by having , RA, A, and E held low with WE high at the rising edge of the clock. Before issuing the Self-Refreshing-Entry command, the DDR3(L) SDRAM must be idle with all bank precharge state with tRP satisfied. Also, on-die termination must be turned off before issuing Self-Refresh-Entry command, by either registering ODT pin low “ODTL + 0.5tCK” prior to the Self-Refresh Entry command or using MRS to MR1 command. Once the Self-Refresh Entry command is registered, CKE must be held low to keep the device in Self-Refresh mode. During normal operation (DLL on), MR1 (A0=0), the DLL is automatically disabled upon entering Self-Refresh and is automatically enabled (including a DLL-RESET) upon exiting Self-Refresh. When the DDR3(L) SDRAM has entered Self-Refresh mode, all of the external control signals, except CKE and REET, are “don’t care”. For proper Self-Refresh operation, all power supply and reference pins (VDD, VDDQ, VSS, VSSQ, VRefCA, and VRefDQ) must be at valid levels. The DRAM initiates a minimum of one Refresh command internally within tCKE period once it enters Self-Refresh mode. The clock is interna during Self-Refresh operation to save power. The minimum time that the DDR3(L) SDRAM must remain in Self-Refresh mode is tCKESR. The user may change the external clock frequency or halt the external clock tCKSRE after Self-Refresh entry is registered; however, the clock must be restarted and stable tCKSRX before the device can exit Self-Refresh mode. The procedure for exiting Self-Refresh requires a sequence of events. First, the clock must be stable prior to CKE going back HIGH. Once a Self-Refresh Exit Command (SRX, combination of CKE going high and either NOP or Deselect on command bus) is registered, a delay of at least tXS must be satisfied before a valid command not requiring a locked DLL can be issued to the device to allow for any internal refresh in progress. Before a command which requires a locked DLL can be applied, a delay of at least tXSDLL and applicable ZQCAL function requirements must be satisfied. Version 1.9 02/2017 63 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Before a command that requires a locked DLL can be applied, a delay of at least tXSDLL must be satisfied. Depending on the system environment and the amount of time spent in Self-Refresh, ZQ calibration commands may be required to compensate for the voltage and temperature drift as described in “ZQ Calibration Commands”. To issue ZQ calibration commands, applicable timing requirements must be satisfied. CKE must remain HIGH for the entire Self-Refresh exit period tXSDLL for proper operation except for Self-Refresh re-entry. Upon exit from Self-Refresh, the DDR3(L) SDRAM can be put back into Self-Refresh mode after waiting at least tXS period and issuing one refresh command (refresh period of tRFC). NOP or deselect commands must be registered on each positive clock edge during the Self-Refresh exit interval tXS. ODT must be turned off during tXSDLL. The use of Self-Refresh mode instructs the possibility that an internally times refresh event can be missed when CKE is raised for exit from Self-Refresh mode. Upon exit from Self-Refresh, the DDR3(L) SDRAM requires a minimum of one extra refresh command before it is put back into Self-Refresh mode. Self-Refresh Entry/Exit Timing T0 T1 T2 Ta0 Tb0 Tc0 Tc1 Td0 Te0 Tf Valid Valid CK, CK tCKSRE tCKSRX tCPDED CKE tCKESR Valid ODT ODTL CMD NOP SRE T NOP SRX Valid 2) Valid 3) Valid Valid tXS tXSDLL tRP Enter Self Refresh Exit Self Refresh Do Not Care Note: 1. Only NOP or DES commands 2. Valid commands not requiring a locked DLL 3. Valid commands requiring a locked DLL Version 1.9 02/2017 NOP 1) 64 Time Break Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Power-Down Modes Power-Down Entry and Exit Power-Down is synchronously entered when CKE is registered low (along with NOP or Deselect command). CKE is not allowed to go low while mode register set command, MPR operations, ZQCAL operations, DLL locking or read/write operation are in progress. CKE is allowed to go low while any of other operation such as row activation, precharge or auto precharge and refresh are in progress, but power-down IDD spec will not be applied until finishing those operation. The DLL should be in a locked state when power-down is entered for fastest power-down exit timing. If the DLL is not locked during power-down entry, the DLL must be reset after exiting power-down mode for proper read operation and synchronous ODT operation. DRAM design provides all AC and DC timing and voltage specification as well as proper DLL operation with any CKE intensive operations as long as DRAM controller complies with DRAM specifications. During Power-Down, if all banks are closed after any in progress commands are completed, the device will be in precharge Power-Down mode; if any bank is open after in progress commands are completed, the device will be in active Power-Down mode. Entering Power-down deactivates the input and output buffers, excluding CK, CK, ODT, E, and REET. To protect DRAM internal delay on CKE line to block the input signals, multiple NOP or Deselect commands are needed during the CKE switch off and cycle(s) after, this timing period are defined as tCPDED. CKE_low will result in deactivation of command and address receivers after tCPDED has expired. Power-Down Entry Definitions Status of DRAM MRS bit A12 DLL PD Exit Don't Care On Fast Relevant Parameters Active tXP to any valid command. (A Bank or more open) tXP to any valid command. Since it is in precharge state, Precharged commands here will be ACT, AR, MRS/EMRS, PR, or PRA. 0 Off Slow (All Banks Precharged) tXPDLL to commands who need DLL to operate, such as RD, RDA, or ODT control line. Precharged 1 On Fast tXP to any valid command. (All Banks Precharged) Also the DLL is disabled upon entering precharge power-down (Slow Exit Mode), but the DLL is kept enabled during precharge power-down (Fast Exit Mode) or active power-down. In power-down mode, CKE low, REET high, and a stable clock signal must be maintained at the inputs of the DDR3(L) SDRAM, and ODT should be in a valid state but all other input signals are “Don’t care” (If REET goes low during Power-Down, the DRAM will be out of PD mode and into reset state). CKE low must be maintain until tCKE has been satisfied. Power-down duration is limited by 9 times tREFI of the device. Version 1.9 02/2017 65 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP The power-down state is synchronously exited when CKE is registered high (along with a NOP or Deselect command). CKE high must be maintained until tCKE has been satisfied. A valid, executable command can be applied with power-down exit latency, tXP and/or tXPDLL after CKE goes high. Power-down exit latency is defined at AC spec table of this datasheet. Active Power-Down Entry and Exit timing diagram T0 T1 T2 Ta0 Valid NOP NOP Ta1 Tb0 Tb1 Tc0 NOP NOP NOP Valid Valid CK CK CMD NOP tIS tPD tIH CKE tIH tIS Address tCKE Valid Valid tCPDED tXP Enter Power-Down Exit Power-Down Do not care Time Break Timing Diagrams for CKE with PD Entry, PD Exit with Read, READ with Auto Precharge, Write and Write with Auto Precharge, Activate, Precharge, Refresh, MRS: Power-Down Entry after Read and Read with Auto Precharge T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 RD or RDA NOP NOP NOP NOP NOP NOP NOP NOP Ta7 Ta8 Tb0 Tb1 NOP NOP NOP Valid CK CK CMD tIS CKE tCPDED Valid tPD Address Valid Valid RL = AL + CL DQS, DQS BL8 Din b Din b+1 Din b+2 Din b+3 BC4 Din b Din b+1 Din b+2 Din b+3 Din b+4 Din b+5 Din b+6 Din b+7 tRDPDEN Power-Down Entry Version 1.9 02/2017 66 Do not care Time Break Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Power-Down Entry after Write with Auto Precharge T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Tb0 WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP Tb1 Tb2 Tb3 Tc0 NOP NOP NOP Valid CK CK CMD tIS CKE Address tCPDED Bank, Col n WL=AL+CWL WR (1) tPD DQS, DQS BL8 Din b Din b+1 Din b+2 Din b+3 BC4 Din b Din b+1 Din b+2 Din b+3 Din b+4 Din b+5 Din b+6 Din b+7 Start Internal Precharge tWRAPDEN Power-Down Entry Do not care Time Break Power-Down Entry after Write T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Tb0 WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP Tb1 Tb2 Tc0 NOP NOP NOP CK CK CMD tIS CKE Address tCPDED Bank, Col n WL=AL+CWL WR tPD DQS, DQS BL8 Din b Din b+1 Din b+2 Din b+3 BC4 Din b Din b+1 Din b+2 Din b+3 Din b+4 Din b+5 Din b+6 Din b+7 tWRPDEN Power-Down Entry Version 1.9 02/2017 67 Do not care Nanya Technology Cooperation © All Rights Reserved. Time Break DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Precharge Power-Down (Fast Exit Mode) Entry and Exit T0 T1 WRITE NOP T2 Ta0 Ta1 NOP NOP Tb0 Tb1 Tc0 NOP NOP NOP NOP Valid CK CK CMD NOP tCPDED tCKE tIS tIH CKE tIS tPD tXP Enter Power-Down Mode Exit Power-Down Mode Do not care Time Break Precharge Power-Down (Slow Exit Mode) Entry and Exit T0 T1 T2 Ta0 Ta1 WRITE NOP NOP NOP NOP Tb0 Tb1 Tc0 Td0 NOP NOP Valid Valid NOP Valid Valid CK CK CMD tCPDED tCKE tIS tIH CKE tIS tXP tPD Enter Power-Down Mode Version 1.9 02/2017 tXPDLL Exit Power-Down Mode 68 Do not care Time Break Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Refresh Command to Power-Down Entry T0 T1 T2 T3 Ta0 CMD REF NOP NOP NOP Address Valid Ta1 CK CK Valid Valid tIS tCPDED tPD CKE Valid tREFPDEN Do not care Version 1.9 02/2017 69 Time Break Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Active Command to Power-Down Entry T0 T1 T2 T3 Ta0 CMD Active NOP NOP NOP Address Valid Ta1 CK CK Valid Valid tCPDED tIS tPD CKE Valid tACTPDEN Do not care Time Break Precharge/Precharge all Command to Power-Down Entry T0 T1 T2 T3 Ta0 CMD PRE PREA NOP NOP NOP Address Valid Ta1 CK CK Valid Valid tIS tCPDED tPD CKE Valid tPREPDEN Do not care Time Break MRS Command to Power-Down Entry T0 T1 Ta0 Ta1 CMD MRS NOP NOP NOP Address Valid Tb0 Tb1 CK CK Valid Valid tIS tCPDED tPD CKE Valid tMRSPDEN Do not care Version 1.9 02/2017 70 Time Break Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP On-Die Termination (ODT) ODT (On-Die Termination) is a feature of the DDR3(L) SDRAM that allows the DRAM to turn on/off termination resistance for each DQ, DQS, , and DM for x8 configuration (and TDQS, T for x8 configuration, when enabled via A11=1 in MR1) via the ODT control pin. For x16 configuration, ODT is applied to each DQ, DQSU, U, DQSL, L, DMU and DMl signal via the ODT control pin. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to independently turn on/off termination resistance for any or all DRAM devices. The ODT feature is turned off and not supported in Self-Refresh mode. A simple functional representation of the DRAM ODT feature is shown as below. Functional Representation of ODT ODT To other circuitry like RCV, ... VDDQ / 2 RTT Switch DQ , DQS, DM, TDQS The switch is enabled by the internal ODT control logic, which uses the external ODT pin and other control information. The value of RTT is determined by the settings of Mode Register bits. The ODT pin will be ignored if the Mode Register MR1 and MR2 are programmed to disable ODT and in self-refresh mode. ODT Mode Register and ODT Truth Table The ODT Mode is enabled if either of MR1 {A2, A6, A9} or MR2 {A9, A10} are non-zero. In this case, the value of RTT is determined by the settings of those bits. Application: Controller sends WR command together with ODT asserted. One possible application: The rank that is being written to provides termination. DRAM turns ON termination if it sees ODT asserted (except ODT is disabled by MR) DRAM does not use any write or read command decode information. Termination Truth Table ODT pin DRAM Termination State 0 OFF 1 ON, (OFF, if disabled by MR1 {A2, A6, A9} and MR2{A9, A10} in general) Version 1.9 02/2017 71 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Synchronous ODT Mode Synchronous ODT mode is selected whenever the DLL is turned on and locked. Based on the power-down definition, these modes are:  Any bank active with CKE high  Refresh with CKE high  Idle mode with CKE high  Active power down mode (regardless of MR0 bit A12)  Precharge power down mode if DLL is enabled during precharge power down by MR0 bit A12 The direct ODT feature is not supported during DLL-off mode. The on-die termination resistors must be disabled by continuously registering the ODT pin low and/or by programming the RTT_Nom bits MR1{A9,A6,A2} to {0,0,0} via a mode register set command during DLL-off mode. In synchronous ODT mode, RTT will be turned on ODTLon clock cycles after ODT is sampled high by a rising clock edge and turned off ODTLoff clock cycles after ODT is registered low by a rising clock edge. The ODT latency is tied to the write latency (WL) by: ODTLonn = WL - 2; ODTLoff = WL-2. ODT Latency and Posted ODT In synchronous ODT Mode, the Additive Latency (AL) programmed into the Mode Register (MR1) also applies to the ODT signal. The DRAM internal ODT signal is delayed for a number of clock cycles defined by the Additive Latency (AL) relative to the external ODT signal. ODTLon = CWL + AL - 2; ODTLoff = CWL + AL - 2. For details, refer to DDR3(L) SDRAM latency definitions. ODT Latency Symbol Parameter DDR3-1600 Unit ODTLon ODT turn on Latency WL - 2 = CWL + AL - 2 tCK ODTLoff ODT turn off Latency WL - 2 = CWL + AL - 2 tCK Version 1.9 02/2017 72 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Timing Parameters In synchronous ODT mode, the following timing parameters apply: ODTLon, ODTLoff, tAON min/max, tAOF min/max. Minimum RTT turn-on time (tAON min) is the point in time when the device leaves high impedance and ODT resistance begins to turn on. Maximum RTT turn-on time (tAON max) is the point in time when the ODT resistance is fully on. Both are measured from ODTLon. Minimum RTT turn-off time (tAOF min) is the point in time when the device starts to turn off the ODT resistance. Maximum RTT turn off time (tAOF max) is the point in time when the on-die termination has reached high impedance. Both are measured from ODTLoff. When ODT is asserted, it must remain high until ODTH4 is satisfied. If a Write command is registered by the SDRAM with ODT high, then ODT must remain high until ODTH4 (BL=4) or ODTH8 (BL=8) after the write command. ODTH4 and ODTH8 are measured from ODT registered high to ODT registered low or from the registration of a write command until ODT is registered low. Synchronous ODT Timing Example for AL=3; CWL=5; ODTLon=AL+CWL-2=6; ODTLoff=AL+CWL-2=6 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 CK CK CKE ODT AL=3 AL=3 tAONmax CWL - 2 tAONmax ODTH4, min ODTLon = CWL + AL -2 tAONmin tAONmin ODTLoff = CWL + AL -2 RTT_NOM DRAM_RTT Transitioning Do not care Synchronous ODT example with BL=4, WL=7 T0 T1 T2 NOP NOP NOP T3 T4 T5 T6 NOP NOP T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CK CK NOP NOP WRS4 NOP ODTH4 ODTH4 ODT ODTH4min ODTLoff = CWL -2 tAONmin ODTLoff = WL - 2 tAOFmax tAONmax tAOFmax tAONmax tAONmin tAOFmin tAOFmin RTT_NOM DRAM_RTT ODTLon = CWL -2 ODTLon = CWL -2 Transitioning Do not care ODT must be held high for at least ODTH4 after assertion (T1); ODT must be kept high ODTH4 (BL=4) or ODTH8 (BL=8) after Write command (T7). ODTH is measured from ODT first registered high to ODT first registered low, or from registration of Write command with ODT high to ODT registered low. Note that although ODTH4 is satisfied from ODT registered at T6 ODT must not go low before T11 as ODTH4 must also be satisfied from the registration of the Write command at T7. Version 1.9 02/2017 73 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP ODT during Reads: As the DDR3(L) SDRAM cannot terminate and drive at the same time, RTT must be disabled at least half a clock cycle before the read preamble by driving the ODT pin low appropriately. RTT may not be enabled until the end of the post-amble as shown in the following figure. DRAM turns on the termination when it stops driving which is determined by tHZ. If DRAM stops driving early (i.e. tHZ is early), then tAONmin time may apply. If DRAM stops driving late (i.e. tHZ is late), then DRAM complies with tAONmax timing. Note that ODT may be disabled earlier before the Read and enabled later after the Read than shown in this example. ODT must be disabled externally during Reads by driving ODT low. (Example: CL=6; AL=CL-1=5; RL=AL+CL=11; CWL=5; ODTLon=CWL+AL-2=8; ODTLoff=CWL+AL-2=8) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 NOP NOP NOP NOP NOP NOP NOP NOP NOP CK CK CMD Read Address Valid NOP NOP NOP NOP NOP NOP NOP RL = AL + CL ODT ODTLon = CWL + AL - 2 ODTLoff = CWL + AL - 2 tAONmax tAOFmin DRAM ODT RTT_NOM RTT RTT_NOM tAOFmax DQSdiff Din b DQ Version 1.9 02/2017 74 Din b+1 Din b+2 Din b+3 Din b+4 Din b+5 Din b+6 Din b+7 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Dynamic ODT In certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the DDR3(L) SDRAM can be changed without issuing an MRS command. This requirement is supported by the “Dynamic ODT” feature as described as follows: Functional Description The Dynamic ODT Mode is enabled if bit (A9) or (A10) of MR2 is set to ‘1’. The function is described as follows: Two RTT values are available: RTT_Nom and RTT_WR.  The value for RTT_Nom is preselected via bits A[9,6,2] in MR1.  The value for RTT_WR is preselected via bits A[10,9] in MR2. During operation without write commands, the termination is controlled as follows:  Nominal termination strength RTT_Nom is selected.  Termination on/off timing is controlled via ODT pin and latencies ODTLon and ODTLoff. When a Write command (WR, WRA, WRS4, WRS8, WRAS4, WRAS8) is registered, and if Dynamic ODT is enabled, the termination is controlled as follows:  A latency ODTLcnw after the write command, termination strength RTT_WR is selected.  A latency ODTLcwn8 (for BL8, fixed by MRS or selected OTF) or ODTLcwn4 (for BC4, fixed by MRS or selected OTF) after the write command, termination strength RTT_Nom is selected.  Termination on/off timing is controlled via ODT pin and ODTLon, ODTLoff. The following table shows latencies and timing parameters which are relevant for the on-die termination control in Dynamic ODT mode. The dynamic ODT feature is not supported at DLL-off mode. User must use MRS command to set RTT_WR, MR2[A10,A9 = [0,0], to disable Dynamic ODT externally. When ODT is asserted, it must remain high until ODTH4 is satisfied. If a Write command is registered by the SDRAM with ODT high, then ODT must remain high until ODTH4 (BL=4) or ODTH8 (BL=8) after the Write command. ODTH4 and ODTH8 are measured from ODT registered high to ODT registered low or from the registration of Write command until ODT is register low. Version 1.9 02/2017 75 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Latencies and timing parameters relevant for Dynamic ODT Name and Description Abbr. Defined from Defined to Definition for all DDR3(L) speed pin Unit ODT turn-on Latency ODTLon registering external ODT signal high turning termination on ODTLon=WL-2 tCK ODT turn-off Latency ODTLoff registering external ODT signal low turning termination off ODTLoff=WL-2 tCK ODT Latency for changing from RTT_Nom to RTT_WR ODTLcnw registering external write command change RTT strength from RTT_Nom to RTT_WR ODTLcnw=WL-2 tCK ODT Latency for change from RTT_WR to RTT_Nom (BL=4) ODTLcwn4 registering external write command change RTT strength from RTT_WR to RTT_Nom ODTLcwn4=4+ODTLoff tCK ODT Latency for change from RTT_WR to RTT_Nom (BL=8) ODTLcwn8 registering external write command change RTT strength from RTT_WR to RTT_Nom ODTLcwn8=6+ODTLoff tCK(avg) Minimum ODT high time after ODT assertion ODTH4 registering ODT high ODT registered low ODTH4=4 tCK(avg) Minimum ODT high time after Write (BL=4) ODTH4 registering write with ODT high ODT registered low ODTH4=4 tCK(avg) Minimum ODT high time after Write (BL=8) ODTH8 registering write with ODT high ODT register low ODTH8=6 tCK(avg) RTT change skew tADC ODTLcnw ODTLcwn RTT valid tADC(min)=0.3tCK(avg) tADC(max)=0.7tCK(avg) tCK(avg) Note: tAOF,nom and tADC,nom are 0.5tCK (effectively adding half a clock cycle to ODTLoff, ODTcnw, and ODTLcwn) Version 1.9 02/2017 76 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP ODT Timing Diagrams Dynamic ODT: Behavior with ODT being asserted before and after the write T0 T1 T2 T3 NOP NOP NOP NOP T4 T5 T6 NOP NOP T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CK CK CMD WRS4 Address NOP Valid ODT ODTLoff ODTH4 ODTLcwn4 tADCmin tAONmin RTT_Nom RTT RTT_WR tAONmax RTT_Nom tADCmax ODTLon tAOFmin tADCmin tAOFmax tADCmax ODTLcnw ODTH4 DQS/DQS WL Din n DQ Din n+1 Din n+2 Din n+3 Do not care Note: Example for BC4 (via MRS or OTF), AL=0, CWL=5. ODTH4 applies to first registering ODT high and to the registration of the Write command. In this example ODTH4 would be satisfied if ODT went low at T8. (4 clocks after the Write command). Dynamic ODT: Behavior without write command, AL=0, CWL=5 T0 T1 T2 T3 T4 Valid Valid Valid Valid T5 T6 Valid Valid T7 T8 T9 T10 T11 Valid Valid Valid Valid CK CK CMD Valid Valid Address ODTLoff ODT ODTH4 ODTLoff tADCmin tAONmin RTT_Nom RTT tADCmax tAONmax ODTLon DQS/DQS DQ Do not care Transitioning Note: ODTH4 is defined from ODT registered high to ODT registered low, so in this example ODTH4 is satisfied; ODT registered low at T5 would also be legal. Version 1.9 02/2017 77 Nanya Technology Cooperation © All Rights Reserved. Transitioning DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Dynamic ODT: Behavior with ODT pin being asserted together with write command for the duration of 6 clock cycles. T0 T1 T2 T3 NOP WRS8 NOP T4 T5 T6 NOP NOP T7 T8 T9 T10 T11 NOP NOP NOP NOP CK CK CMD NOP NOP NOP ODTLcnw Valid Address ODT ODTH8 ODTLoff ODTLon tAOFmin tAONmin RTT_WR RTT tAOFmax tAONmax ODTLcwn8 DQS/DQS WL Din h DQ Din h+1 Din h+2 Din h+3 Din h+4 Din h+5 Din h+6 Din h+7 Do not care Transitioning Note: Example for BL8 (via MRS or OTF), AL=0, CWL=5. In this example ODTH8=6 is exactly satisfied. Dynamic ODT: Behavior with ODT pin being asserted together with write command for a duration of 6 clock cycles, example for BC4 (via MRS or OTF), AL=0, CWL=5. T0 T1 T2 NOP WRS4 NOP T3 T4 T5 T6 NOP NOP T7 T8 T9 T10 T11 NOP NOP NOP NOP CK CK CMD Address ODTLcnw NOP NOP NOP Valid ODT ODTH4 tAONmin ODTLoff tADCmin RTT_WR RTT tAOFmin RTT_Nom tAONmax tAOFmax tADCmax ODTLon ODTLcwn4 DQS/DQS WL Din n DQ Din n+1 Din n+2 Din n+3 Do not care Version 1.9 02/2017 78 Transitioning Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Dynamic ODT: Behavior with ODT pin being asserted together with write command for the duration of 4 clock cycles. T0 T1 T2 NOP WRS4 NOP T3 T4 T5 T6 NOP NOP T7 T8 T9 T10 T11 NOP NOP NOP NOP CK CK# CMD Address ODTLcnw NOP NOP NOP Valid ODT ODTH4 tAONmin ODTLoff tAOFmin RTT_WR RTT tAONmax tAOFmax ODTLon ODTLcwn4 DQS/DQS WL Din n DQ Din n+1 Din n+2 Din n+3 Do not care Version 1.9 02/2017 79 Transitioning Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Asynchronous ODT Mode Asynchronous ODT mode is selected when DRAM runs in DLLon mode, but DLL is temporarily disabled (i.e. frozen) in precharge power-down (by MR0 bit A12). Based on the power down mode definitions, this is currently Precharge power down mode if DLL is disabled during precharge power down by MR0 bit A12. In asynchronous ODT timing mode, internal ODT command is NOT delayed by Additive Latency (AL) relative to the external ODT command. In asynchronous ODT mode, the following timing parameters apply: t AONPD min/max, tAOFPD min/max. Minimum RTT turn-on time (tAONPD min) is the point in time when the device termination circuit leaves high impedance state and ODT resistance begins to turn on. Maximum RTT turn on time (t AONPD max) is the point in time when the ODT resistance is fully on. tAONPDmin and tAONPDmax are measured from ODT being sampled high. Minimum RTT turn-off time (tAOFPDmin) is the point in time when the devices termination circuit starts to turn off the ODT resistance. Maximum ODT turn off time (t AOFPDmax) is the point in time when the on-die termination has reached high impedance. tAOFPDmin and tAOFPDmax are measured from ODT being sample low. Asynchronous ODT Timings on DDR3(L) SDRAM with fast ODT transition: AL is ignored. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 CK CK# CKE tIS tIH ODT tIS tIH tAONPDmax tAOFPDmin RTT tAONPDmin tAOFPDmax Do not care Transitioning In Precharge Power Down, ODT receiver remains active; however no Read or Write command can be issued, as the respective ADD/CMD receivers may be disabled. Asynchronous ODT Timing Parameters for all Speed Bins Symbol Description Min. Max. Unit tAONPD Asynchronous RTT turn-on delay (Power-Down with DLL frozen) 2 8.5 ns tAOFPD Asynchronous RTT turn-off delay (Power-Down with DLL frozen) 2 8.5 ns Version 1.9 02/2017 80 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP ODT timing parameters for Power Down (with DLL frozen) entry and exit transition period Description Min. Max. min{ ODTLon * tCK + tAONmin; tAONPDmin } max{ ODTLon * tCK + tAONmax; tAONPDmax } min{ (WL - 2) * tCK + tAONmin; tAONPDmin } max{ (WL - 2) * tCK + tAONmax; tAONPFmax } min{ ODTLoff * tCK + tAOFmin; tAOFPDmin } max{ ODTLoff * tCK + tAOFmax; tAOFPDmax } min{ (WL - 2) * tCK + tAOFmin; tAOFPDmin } max{ (WL - 2) * tCK + tAOFmax; tAOFPDmax } ODT to RTT turn-on delay ODT to RTT turn-off delay tANPD WL-1 Synchronous to Asynchronous ODT Mode Transition during Power-Down Entry If DLL is selected to be frozen in Precharge Power Down Mode by the setting of bit A12 in MR0 to “0”, there is a transition period around power down entry, where the DDR3(L) SDRAM may show either synchronous or asynchronous ODT behavior. The transition period is defined by the parameters tANPD and tCPDED(min). tANPD is equal to (WL-1) and is counted backwards in time from the clock cycle where CKE is first registered low. tCPDED(min) starts with the clock cycle where CKE is first registered low. The transition period begins with the starting point of tANPD and terminates at the end point of tCPDED(min). If there is a Refresh command in progress while CKE goes low, then the transition period ends at the later one of tRFC(min) after the Refresh command and the end point of tCPDED(min). Please note that the actual starting point at tANPD is excluded from the transition period, and the actual end point at tCPDED(min) and tRFC(min, respectively, are included in the transition period. ODT assertion during the transition period may result in an RTT change as early as the smaller of tAONPDmin and (ODTLon*tCK + tAONmin) and as late as the larger of tAONPDmax and (ODTLon*tCK + tAONmax). ODT de-assertion during the transition period may result in an RTT change as early as the smaller of tAOFPDmin and (ODTLoff*tCK + tAOFmin) and as late as the larger of tAOFPDmax and (ODTLoff*tCK + tAOFmax). Note that, if AL has a large value, the range where RTT is uncertain becomes quite large. Figure 85 shows the three different cases: ODT_A, synchronous behavior before tANPD; ODT_B has a state change during the transition period; ODT_C shows a state change after the transition period. Version 1.9 02/2017 81 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Synchronous to asynchronous transition during Precharge Power Down (with DLL frozen) entry (AL=0; CWL=5; tANPD=WL-1=4) T1 T2 T3 T4 T5 NOP NOP NOP NOP NOP T6 T7 T8 T9 T10 T11 T12 CK CK CMD NOP NOP NOP NOP NOP NOP NOP NOP CKE tANPD tCPDEDmin tCPDED PD entry transition period Last sync. ODT tAOFmin RTT RTT ODTLoff tAOFmax Sync. Or async. ODT RTT RTT tAOFPDmin tAOFPDmax ODTLoff+tAOFPDmin ODTLoff+tAOFPDmax First async. ODT tAOFPDmax RTT RTT tAOFPDmin Transitioning Version 1.9 02/2017 82 Do not care Time Break Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Asynchronous to Synchronous ODT Mode transition during Power-Down Exit If DLL is selected to be frozen in Precharge Power Down Mode by the setting of bit A12 in MR0 to “0”, there is also a transition period around power down exit, where either synchronous or asynchronous response to a change in ODT must be expected from the DDR3(L) SDRAM. This transition period starts tANPD before CKE is first registered high, and ends tXPDLL after CKE is first registered high. tANPD is equal to (WL -1) and is counted (backwards) from the clock cycle where CKE is first registered high. ODT assertion during the transition period may result in an RTT change as early as the smaller of tAONPDmin and (ODTLon*tCK+tAONmin) and as late as the larger of tAONPDmax and (ODTLon*tCK+tAONmax). ODT de-assertion during the transition period may result in an RTT change as early as the smaller of t AOFPDmin and (ODTLoff*tCK+tAOFmin) and as late as the larger of tAOFPDmax and (ODToff*tCK+tAOFmax). Note that if AL has a large value, the range where RTT is uncertain becomes quite large. The following figure shows the three different cases: ODT_C, asynchronous response before t ANPD; ODT_B has a state change of ODT during the transition period; ODT_A shows a state change of ODT after the transition period with synchronous response. Asynchronous to synchronous transition during Precharge Power Down (with DLL frozen) exit (CL=6; AL=CL-1; CWL=5; tANPD=WL-1=9) T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 Tb1 Tb2 Tc0 Tc1 Tc2 Td0 Td1 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CK CK CKE CMD NOP NOP NOP NOP tANPD tXPDLL PD exit transition period ODT_C _sync tAOFPDmin DRAM _RTT_ C_sync RTT tAOFPDmax ODT_B _tran tAOFPDmin DRAM _RTT_ B_tran RTT tAOFPDmax ODTLoff + tAOFmin ODTLoff + tAOFmax ODTLoff ODT_A _async tAOFmax tAOFmin DRAM_ RTT_A_ async RTT Transitioning Version 1.9 02/2017 83 Do not care Time Break Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Asynchronous to Synchronous ODT Mode during short CKE high and short CKE low periods If the total time in Precharge Power Down state or Idle state is very short, the transition periods for PD entry and PD exit may overlap. In this case, the response of the DDR3(L) SDRAMs RTT to a change in ODT state at the input may be synchronous or asynchronous from the state of the PD entry transition period to the end of the PD exit transition period (even if the entry ends later than the exit period). If the total time in Idle state is very short, the transition periods for PD exit and PD entry may overlap. In this case, the response of the DDR3(L) SDRAMs RTT to a change in ODT state at the input may be synchronous or asynchronous from the start of the PD exit transition period to the end of the PD entry transition period. Note that in the following figure, it is assumed that there was no Refresh command in progress when Idle state was entered. Transition period for short CKE cycles with entry and exit period overlapping (AL=0; WL=5; tANPD=WL-1=4) T0 T1 T2 T3 REF NOP NOP NOP T4 T5 T6 NOP NOP T7 T8 T9 T10 T11 T12 T13 T14 NOP NOP NOP NOP NOP NOP NOP CK CK CMD NOP NOP CKE tANPD tANPD PD exit transition period PD entry transition period tRFC(min) tXPDLL CKE Short CKE high transition period tXPDLL Version 1.9 02/2017 84 Do not care Transitioning Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP ZQ Calibration Commands ZQ Calibration Description ZQ Calibration command is used to calibrate DRAM Ron and ODT values. DDR3(L) SDRAM needs longer time to calibrate output driver and on-die termination circuits at initialization and relatively smaller time to perform periodic calibrations. ZQCL command is used to perform the initial calibration during power-up initialization sequence. This command may be issued at any time by the controller depending on the system environment. ZQCL command triggers the calibration engine inside the DRAM and once calibration is achieved the calibrated values are transferred from calibration engine to DRAM IO which gets reflected as updated output driver and on-die termination values. The first ZQCL command issued after reset is allowed a timing period of tZQinit to perform the full calibration and the transfer of values. All other ZQCL commands except the first ZQCL command issued after RESET is allowed a timing period of tZQoper. ZQCS command is used to perform periodic calibrations to account for voltage and temperature variations. A shorter timing window is provided to perform the calibration and transfer of values as defined by timing parameter tZQCS. No other activities should be performed on the DRAM channel by the controller for the duration of tZQinit, tZQoper, or tZQCS. The quiet time on the DRAM channel allows calibration of output driver and on-die termination values. Once DRAM calibration is achieved, the DRAM should disable ZQ current consumption path to reduce power. All banks must be precharged and tRP met before ZQCL or ZQCS commands are issued by the controller. ZQ calibration commands can also be issued in parallel to DLL lock time when coming out of self refresh. Upon self-refresh exit, DDR3(L) SDRAM will not perform an IO calibration without an explicit ZQ calibration command. The earliest possible time for ZQ Calibration command (short or long) after self refresh exit is tXS. In systems that share the ZQ resistor between devices, the controller must not allow any overlap of tZQoper, tZQinit, or tZQCS between ranks. Version 1.9 02/2017 85 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP ZQ Calibration Timing T0 T1 Ta0 Ta1 ZQCL NOP NOP NOP Ta2 Ta3 Tb0 Tb1 Valid Valid ZQCS Address Valid Valid A10 Valid Valid Tc0 Tc1 Tc2 NOP NOP Valid CK CK CMD NOP Valid CKE (1) Valid Valid (1) Valid ODT (2) Valid Valid (2) Valid DQ Bus (3) Hi-Z Activities (3) tZQinit or tZQoper Hi-Z Activities tZQCS Do not care Time Break Note: 1. CKE must be continuously registered high during the calibration procedure. 2. On-die termination must be disabled via the ODT signal or MRS during the calibration procedure. 3. All devices connected to the DQ bus should be high impedance during the calibration procedure. ZQ External Resistor Value, Tolerance, and Capacitive loading In order to use the ZQ calibration function, a 240 ohm +/- 1% tolerance external resistor connected between the ZQ pin and ground. The single resistor can be used for each SDRAM or one resistor can be shared between two SDRAMs if the ZQ calibration timings for each SDRAM do not overlap. The total capacitive loading on the ZQ pin must be limited. Version 1.9 02/2017 86 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Absolute Maximum Ratings Absolute Maximum DC Ratings Symbol VDD VDDQ Vin, Vout Tstg Parameter Rating Unit Note Voltage on VDD pin relative to Vss -0.4 V ~ 1.80 V V 1,3 Voltage on VDDQ pin relative to Vss -0.4 V ~ 1.80 V V 1,3 Voltage on any pin relative to Vss -0.4 V ~ 1.80 V V 1 -55 ~ 150 C 1,2 Storage Temperature Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. 3. VDD and VDDQ must be within 300mV of each other at all times; and Vref must be not greater than 0.6VDDQ, when VDD and VDDQ are less than 500Mv; Vref may be equal to or less than 300mV. Refresh parameters by device density Parameter Symbol 2Gb Unit REF command to ACT or REF command time tRFC 160 ns Version 1.9 02/2017 87 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Temperature Range Condition Parameter Value Unit Notes Normal Operating Temperature Range 0 ≤Toper ≤ 85 C 1 Extended Temperature Range 85 < Toper ≤ 95 C 1,2 Normal Operating Temperature Range -40 ≤ Toper ≤ 85 C 1 Extended Temperature Range 85 < Toper ≤ 95 C 1,2 Normal Operating Temperature Range -40 ≤ Toper ≤ 85 C 1 Extended Temperature Range 85 < Toper ≤ 95 C 1,2 Normal Operating Temperature Range -40 ≤ Toper ≤ 85 C 1 Extended Temperature Range 85 < Toper ≤ 105 C 1,2 Normal Operating Temperature Range -40 ≤ Toper ≤ 85 C 1 Extended Temperature Range 85 < Toper ≤ 95 C 1,2 Commercial Quasi Industrial Industrial Automotive Grade 2 Automotive Grade 3 Note: 1. Operating Temperature Toper is the case surface temperature on the center/top side of the DRAM. 2. Some applications require operation of the DRAM in the Extended Temperature Range a) Refresh commands must be doubled in frequency, therefore, reducing the Refresh interval tREFI to 3.9us. b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6=0 and MR2 A7=1) or enable the optional Auto Self-Refresh mode (MR2 A6=1 and MR2 A7=0). Version 1.9 02/2017 88 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP AC & DC Operating Conditions Recommended DC Operating Conditions Symbol Rating Parameter DDR3 VDD VDDQ Unit Min. Typ. Max. 1.425 1.5 1.575 Supply Voltage Note 1,2 V DDR3L 1.283 1.35 1.45 DDR3 1.425 1.5 1.575 Supply Voltage for Output 3,4,5,6,7 1,2 V DDR3L 1.283 1.35 1.45 3,4,5,6,7 Note: 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. 3. Maximun DC value may not be great than 1.425V.The DC value is the linear average of VDD/ VDDQ(t) over a very long period of time (e.g., 1 sec). 4. If maximum limit is exceeded, input levels shall be governed by DDR3 specifications. 5. Under these supply voltages, the device operates to this DDR3L specification. 6. Once initialized for DDR3 operation, DDR3L operation may only be used if the device is in reset while VDD and VDDQ are changed for DDR3L operation. 7. 1.35V DDR3L are backward compatible to 1.5V DDR3 parts. Version 1.9 02/2017 89 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP AC & DC Input Measurement Levels DDR3 AC and DC Logic Input Levels for Command and Address DDR3 Symbol Parameter 800,1066,1333,1600 1866,2133 Min Max Min Max U ni t Notes VIH.CA(DC100) DC input logic high Vref + 0.1 VDD Vref + 0.1 VDD V 1, 5 VIL.CA(DC100) DC input logic low VSS Vref - 0.1 VSS Vref - 0.1 V 1, 6 VIH.CA(AC175) AC input logic high Vref + 0.175 Note 2 - - V 1, 2, 7 VIL.CA(AC175) AC input logic low Note 2 Vref - 0.175 - - V 1, 2, 8 VIH.CA(AC150) AC input logic high Vref + 0.150 Note 2 - - V 1, 2, 7 VIL.CA(AC150) AC input logic low Note 2 Vref - 0.150 - - V 1, 2, 8 VIH.CA(AC135) AC input logic high - - Vref + 0.135 Note 2 V 1, 2, 7 VIL.CA(AC135) AC input logic low - - Note 2 Vref - 0.135 V 1, 2, 8 VIH.CA(AC125) AC input logic high - - Vref + 0.125 Note 2 V 1, 2, 7 VIL.CA(AC125) AC input logic low - - Note 2 Vref - 0.125 V 1, 2, 8 VRefCA(DC) Reference Voltage for ADD, CMD inputs 0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD V 3, 4, 9 NOTE 1. For input only pins except REET. Vref = VrefCA(DC). NOTE 2. See “Overshoot and Undershoot Specifications” . NOTE 3. The ac peak noise on VRef may not allow VRef to deviate from VRefCA(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV). NOTE 4. For reference: approx. VDD/2 +/- 15 mV. NOTE 5. VIH(dc) is used as a simplified symbol for VIH.CA(DC100) NOTE 6. VIL(dc) is used as a simplified symbol for VIL.CA(DC100) NOTE 7. VIH(ac) is used as a simplified symbol for VIH.CA(AC175), VIH.CA(AC150), VIH.CA(AC135), and VIH.CA(AC125); VIH.CA(AC175) value is used when Vref + 0.175V is referenced, VIH.CA(AC150) value is used when Vref + 0.150V is referenced, VIH.CA(AC135) value is used when Vref + 0.135V is referenced, and VIH.CA(AC125) value is used when Vref + 0.125V is referenced. NOTE 8. VIL(ac) is used as a simplified symbol for VIL.CA(AC175), VIL.CA(AC150), VIL.CA(AC135) and VIL.CA(AC125); VIL.CA(AC175) value is used when Vref - 0.175V is referenced, VIL.CA(AC150) value is used when Vref - 0.150V is referenced, VIL.CA(AC135) value is used when Vref - 0.135V is referenced, and VIL.CA(AC125) value is used when Vref - 0.125V is referenced. NOTE 9. VrefCA(DC) is measured relative to VDD at the same point in time on the same device Version 1.9 02/2017 90 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP DDR3L AC and DC Logic Input Levels for Command and Address DDR3L Symbol Parameter 1066 1333,1600 1866 Min Max Min Max Min Max Unit Notes VIH.CA(DC90) DC input logic high Vref + 0.09 VDD Vref + 0.09 VDD Vref + 0.09 VDD V 1 VIL.CA(DC90) DC input logic low VSS Vref - 0.09 VSS Vref - 0.09 VSS Vref - 0.09 V 1 VIH.CA(AC160) AC input logic high Vref + 0.16 Note 2 Vref + 0.16 Note 2 - - V 1,2 VIL.CA(AC160) AC input logic low Note 2 Vref - 0.16 Note 2 Vref - 0.16 - - V 1,2 VIH.CA(AC135) AC input logic high Vref + 0.135 Note 2 Vref + 0.135 Note 2 Vref + 0.135 Note 2 V 1,2 VIL.CA(AC135) AC input logic low Note 2 Vref - 0.135 Note 2 Vref - 0.135 Note 2 Vref - 0.135 V 1,2 VIH.CA(AC125) AC input logic high - - - - Vref + 0.125 Note 2 V 1,2 VIL.CA(AC125) AC input logic low - - - - Note 2 Vref - 0.125 V 1,2 0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD V 3,4 VRefCA(DC) Reference Voltage for ADD, CMD inputs NOTE 1 For input only pins except REET. Vref = VrefCA(DC). NOTE 2 See “Overshoot and Undershoot Specifications” NOTE 3 The AC peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 13.5 mV). NOTE 4 For reference: approx. VDD/2 +/- 13.5 mV Version 1.9 02/2017 91 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP DDR3 AC and DC Logic Input Levels for DQ and DM DDR3 Symbol Parameter 800,1066 1333,1600 1866,2133 Unit Notes Min Max Min Max Min Max VIH.DQ(DC100) DC input logic high Vref + 0.1 VDD Vref + 0.1 VDD Vref + 0.1 VDD V 1, 5 VIL.DQ(DC100) DC input logic low VSS Vref - 0.1 VSS Vref - 0.1 VSS Vref - 0.1 V 1, 6 VIH.DQ(AC175) AC input logic high Vref + 0.175 Note 2 - - - - V 1, 2, 7 VIL.DQ(AC175) AC input logic low Note 2 Vref - 0.175 - - - - V 1, 2, 8 VIH.DQ(AC150) AC input logic high Vref + 0.150 Note 2 Vref + 0.150 Note 2 - - V 1, 2, 7 VIL.DQ(AC150) AC input logic low Note 2 Vref - 0.150 Note 2 Vref - 0.150 - - V 1, 2, 8 VIH.DQ(AC135) AC input logic high Vref + 0.135 Note 2 Vref + 0.135 Note 2 Vref + 0.135 Note 2 V 1, 2, 7 VIL.DQ(AC135) AC input logic low Note 2 Vref - 0.135 Note 2 Vref - 0.135 Note 2 Vref - 0.135 V 1, 2, 8 0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD V 3, 4, 9 VRefDQ(DC) Reference Voltage for DQ, DM inputs NOTE 1. Vref = VrefDQ(DC). NOTE 2. See “Overshoot and Undershoot Specifications” . NOTE 3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference:approx. +/- 15 mV). NOTE 4. For reference: approx. VDD/2 +/- 15 mV. NOTE 5. VIH(dc) is used as a simplified symbol for VIH.DQ(DC100) NOTE 6. VIL(dc) is used as a simplified symbol for VIL.DQ(DC100) NOTE 7. VIH(ac) is used as a simplified symbol for VIH.DQ(AC175), VIH.DQ(AC150), and VIH.DQ(AC135);VIH.DQ(AC175) value is used when Vref + 0.175V is referenced, VIH.DQ(AC150) value is used when Vref + 0.150V is referenced, and VIH.DQ(AC135) value is used when Vref + 0.135V is referenced. NOTE 8. VIL(ac) is used as a simplified symbol for VIL.DQ(AC175), VIL.DQ(AC150), and VIL.DQ(AC135);VIL.DQ(AC175) value is used when Vref - 0.175V is referenced, VIL.DQ(AC150) value is used when Vref -0.150V is referenced, and VIL.DQ(AC135) value is used when Vref - 0.135V is referenced. NOTE 9. VrefCA(DC) is measured relative to VDD at the same point in time on the same device Version 1.9 02/2017 92 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP DDR3L AC and DC Logic Input Levels for DQ and DM DDR3L Symbol Parameter 1066 1333,1600 1866 Unit Min Max Min Max Min Max VIH.DQ(DC90) DC input logic high Vref + 0.09 VDD Vref + 0.09 VDD Vref + 0.09 VDD V VIL.DQ(DC90) DC input logic low VSS Vref - 0.09 VSS Vref - 0.09 VSS Vref - 0.09 V Vref + 0.16 Note 2 Vref + 0.16 Note 2 - - V Note 2 Vref - 0.16 Note 2 Vref - 0.16 - - V Note 2 Vref + 0.135 Note 2 Vref + 0.135 Note 2 V VIH.DQ(AC160) AC input logic high VIL.DQ(AC160) AC input logic low VIH.DQ(AC135) AC input logic high Vref + 0.135 V Notes 1 1 1,2 1,2 1,2 1,2 VIL.DQ(AC135) AC input logic low Note 2 Vref - 0.135 Note 2 Vref - 0.135 Note 2 Vref - 0.135 VIH.DQ(AC130) AC input logic high - - - - Vref + 0.13 Note 2 VIL.DQ(AC130) AC input logic low - - - - Note 2 Vref - 0.13 V 1,2 0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD V 3,4 VRefDQ(DC) Reference Voltage for DQ, DM inputs V 1,2 NOTE 1 For input only pins except REET. Vref = VrefDQ(DC). NOTE 2 See “Overshoot and Undershoot Specifications”. NOTE 3 The AC peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 13.5 mV). NOTE 4 For reference: approx. VDD/2 +/- 13.5 mV. Version 1.9 02/2017 93 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Vref Tolerances The dc-tolerance limits and ac-noise limits for the reference voltages VrefCA and VrefDQ are illustrated in the following figure. It shows a valid reference voltage Vref(t) as a function of time. (Vref stands for VrefCA and VrefDQ likewise). Vref(DC) is the linear average of Vref(t) over a very long period of time (e.g.,1 sec). This average has to meet the min/max requirement in previous page. Furthermore Vref(t) may temporarily deviate from Vref(DC) by no more than ±1% VDD. The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC), and VIL(DC) are dependent on Vref. “Vref” shall be understood as Vref(DC). The clarifies that dc-variations of Vref affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for Vref(DC) deviations from the optimum position within the data-eye of the input signals. This also clarifies that the DRAM setup/hold specification and de-rating values need to include time and voltage associated with Vref ac-noise. Timing and voltage effects due to ac-noise on Vref up to the specified limit (±1% of VDD) are included in DRAM timing and their associated de-ratings. Illustration of Vref(DC) tolerance and Vrefac-noise limits Voltage VDD Vref ac-noise VRef(t) Vref(DC)max Vref(DC) VDD/2 Vref(DC)min VSS time Version 1.9 02/2017 94 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP DDR3 Differential AC and DC Input Levels for clock (CK - ) and strobe (DQS - ) DDR3-800, 1066, 1333, & 1600 Symbol Parameter Min Max Unit Notes VIHdiff Differential input high + 0.200 Note 3 V 1 VILdiff Differential input logic low Note 3 - 0.200 V 1 VIHdiff(ac) Differential input high ac 2 x (VIH(ac) - Vref) Note 3 V 2 VILdiff(ac) Differential input low ac Note 3 2 x (VIL(ac) - Vref) V 2 NOTE 1. Used to define a differential signal slew-rate. NOTE 2. For CK -  use VIH/VIL(ac) of ADD/CMD and VREFCA; for DQS - , DQSL, L, DQSU ,U use VIH/VIL(ac) of DQs and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group,then the reduced level applies also here. NOTE 3. These values are not defined; however, the single-ended signals CK, , DQS, , DQSL, L, DQSU, U need to be within the respective limits (VIH(dc) max, VIL(dc)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to “Overshoot and Undershoot Specifications” DDR3L Differential AC and DC Input Levels for clock (CK - ) and strobe (DQS - ) DDR3L-1066, 1333, 1600 & 1866 Symbol Parameter Min Max Unit Notes VIHdiff Differential input high + 0.180 Note 3 V 1 VILdiff Differential input logic low Note 3 - 0.180 V 1 VIHdiff(ac) Differential input high ac 2 x (VIH(ac) - Vref) Note 3 V 2 VILdiff(ac) Differential input low ac Note 3 2 x (VIL(ac) - Vref) V 2 NOTE 1 Used to define a differential signal slew-rate. NOTE 2 For CK -  use VIH/VIL(AC) of ADD/CMD and VREFCA; for DQS - , DQSL, L, DQSU , U use VIH/VIL(AC) of DQs and VREFDQ; if a reduced AC-high or AC-low level is used for a signal group, then the reduced level applies also here. NOTE 3 These values are not defined, however the single-ended signals CK, , DQS, , DQSL, L, DQSU, U need to be within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to “Overshoot and Undershoot Specifications”. Version 1.9 02/2017 95 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Differential Input Voltage (i.e. DQS – DQS, CK – CK) Definition of differential ac-swing and “time above ac-level” tDVAC VIH.Diff.AC.min VIH.Diff. DC min 0 Half cycle VIL. Diff. DC max VIL.Diff.AC.max tDVAC Time Version 1.9 02/2017 96 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP DDR3 Allowed time before ringback (tDVAC) for CK -  and DQS -  DDR3-800 / 1066 / 1333 / 1600 Slew Rate tDVAC [ps] [V/ns] @ |VIH/Ldiff(AC)| = 350mV DDR3-1866 / 2133 tDVAC [ ps ] tDVAC [ ps ] tDVAC [ ps ] tDVAC [ ps ] @ |VIH/Ldiff(AC)| = @ |VIH/Ldiff(AC)| = @ |VIH/Ldiff(AC)| = @ |VIH/Ldiff(AC)| = 300mV (DQS - ) only 300mV (CK - ) only Min Max Min Max Min Max Min Max Min Max > 4.0 75 - 175 - 214 - 134 - 139 - 4.0 57 - 170 - 214 - 134 - 139 - 3.0 50 - 167 - 191 - 112 - 118 - 2.0 38 - 119 - 146 - 67 - 77 - 1.8 34 - 102 - 131 - 52 - 63 - 1.6 29 - 81 - 113 - 33 - 45 - 1.4 22 - 54 - 88 - 9 - 23 - 1.2 note - 19 - 56 - note - note - 1.0 note - note - 11 - note - note - < 1.0 note - note - note - note - note - NOTE 1. Rising input differential signal shall become equal to or greater than VIHdiff(ac) level and Falling input differential signal shall become equal to or less than VILdiff(ac) level. Version 1.9 02/2017 97 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP DDR3L Allowed time before ringback (tDVAC) for CK -  and DQS -  DDR3L-1066/1333/1600 Slew Rate [V/ns] tDVAC [ps] @|VIH/Ldiff(AC)| = 320 mV DDR3L-1866 tDVAC [ps] @|VIH/Ldiff(AC)| = 270 mV tDVAC [ps] @|VIH/Ldiff(AC)| = 270 mV tDVAC [ps] @|VIH/Ldiff(AC)| = 250 mV tDVAC [ps] @|VIH/Ldiff(AC)| = 260 mV Min Max Min Max Min Max Min Max Min Max > 4.0 189 - 201 - 163 - 168 - 176 - 4.0 189 - 201 - 163 - 168 - 176 - 3.0 162 - 179 - 140 - 147 - 154 - 2.0 109 - 134 - 95 - 105 - 111 - 1.8 91 - 119 - 80 - 91 - 97 - 1.6 69 - 100 - 62 - 74 - 78 - 1.4 40 - 76 - 37 - 52 - 56 - 1.2 note - 44 - 5 - 22 - 24 - 1.0 note - note - note - note - note - < 1.0 note - note - note - note - note - NOTE 1. Rising input differential signal shall become equal to or greater than VIHdiff(ac) level and Falling input differential signal shall become equal to or less than VILdiff(ac) level. Version 1.9 02/2017 98 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Single-ended requirements for differential signals Each individual component of a differential signal (CK, DQS, DQSL, DQSU, , ,L, or U) has also to comply with certain requirements for single-ended signals. CK and  have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH (ac) / VIL (ac)) for ADD/CMD signals) in every half-cycle. DQS, DQSL, DQSU, , L have to reach VSEHmin / VSELmax (approximately the ac-levels (VIH (ac) / VIL (ac)) for DQ signals) in every half-cycle proceeding and following a valid transition. Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g., if VIH150 (ac)/VIL150(ac) is used for ADD/CMD signals, then these ac-levels apply also for the single ended signals CK and  Version 1.9 02/2017 99 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Single-ended levels for CK, DQS, DQSL, DQSU, , , L, or U DDR3-800, DDR3(L)-1066, 1333, & 1600 Symbol Parameter Unit Notes note3 V 1, 2 (VDDQ/2) + 0.175 note3 V 1, 2 Single-ended low-level for strobes note3 (VDDQ/2) - 0.175 V 1, 2 Single-ended Low-level for CK,  note3 (VDDQ/2) - 0.175 V 1, 2 Min. Max. Single-ended high-level for strobes (VDDQ/2) + 0.175 Single-ended high-level for CK,  VSEH VSEL Note: 1. For CK,  use VIH/VIL(ac) of ADD/CMD; for strobes (DQS, DQSL, DQSU, CK, , L, or U) use VIH/VIL(ac) of DQs. 2. VIH(ac)/VIL(ac) for DQs is based on VREFDQ; VIH(ac)/VIL(ac) for ADD/CMD is based on VREFCA; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also there. 3. These values are not defined, however the single-ended signals CK, , DQS, , DQSL, L, DQSU, U need to be within the respective limits (VIH(dc)max, VIL(dc)min) for single-ended signals as well as limitations for overshoot and undershoot. Version 1.9 02/2017 100 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK,  and DQS, ) must meet the requirements in the following table. The differential input cross point voltage Vix is measured from the actual cross point of true and complete signal to the midlevel between of VDD and VSS. Vix Definition VDD , VIX VSEH VDD/2 VIX VIX CK,DQS VSEL VSS Cross point voltage for differential input signals (CK, DQS) Symbol VIX(CK) VIX(DQS) Note 1 Parameter DDR3 DDR3L 800/1066/1333/1600/ 1866/2133 1066/1333/1600/ 1866 Differential Input Cross Point Voltage relative to VDD/2 for CK,  Differential Input Cross Point Voltage relative to VDD/2 for DQS,  Min Max - 150 + 150 - 175 + 175 - 150 + 150 Min Max - 150 + 150 - 150 + 150 Unit Notes mV 1 mV 2 mV 1 The relation between Vix Min/Max and VSEL/VSEH should satisfy following: (VDD/2) + VIX (min) - VSEL >= 25 mV ; VSEH - ((VDD/2) + VIX (max)) >= 25 mV; Note 2 Version 1.9 02/2017 Extended range for Vix is only allowed for clock and if single-ended clock input signals CK and  are monotonic with a single-ended swing VSEL / VSEH of at least VDD/2 +/-250 mV, and when the differential slew rate of CK -  is larger than 3 V/ns. 101 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Slew Rate Definition for Differential Input Signals Input slew rate for differential signals (CK,  and DQS, ) are defined and measured as shown below. Differential Input Slew Rate Definition Measured Description Defined by From To Differential input slew rate for rising edge (CK-& DQS-) VILdiffmax VIHdiffmin [VIHdiffmin-VILdiffmax] / DeltaTRdiff Differential input slew rate for falling edge (CK- & DQS-) VIHdiffmin VILdiffmax [VIHdiffmin-VILdiffmax] / DeltaTFdiff The differential signal (i.e., CK-& DQS-) must be linear between these thresholds. Version 1.9 02/2017 102 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Input Nominal Slew Rate Definition for single ended signals Delta TRdiff VIHdiffMin 0 VILdiffMax Delta TFdiff AC and DC Output Measurement Levels Single Ended AC and DC Output Levels Symbol Parameter DDR3(L) Unit Notes VOH(DC) DC output high measurement level (for IV curve linearity) 0.8xVDDQ V VOM(DC) DC output mid measurement level (for IV curve linearity) 0.5xVDDQ V VOL(DC) DC output low measurement level (fro IV curve linearity) 0.2xVDDQ V VOH(AC) AC output high measurement level (for output SR) VTT+0.1xVDDQ V 1 VOL(AC) AC output low measurement level (for output SR) VTT-0.1xVDDQ V 1 Note: 1. The swing of ±0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40 Ω and an effective test load of 25 Ω to VTT = VDDQ/2. Differential AC and DC Output Levels Symbol Parameter DDR3(L) Unit Notes VOHdiff(AC) AC differential output high measurement level (for output SR) +0.2 x VDDQ V 1 VOLdiff(AC) AC differential output low measurement level (for output SR) -0.2 x VDDQ V 1 Note: 1. The swing of ± 0.2 x VDDQ is based on approximately 50% of the static differential output high or low swing with a driver impedance of 40 Ω and an effective test load of 25 Ω to VTT=VDDQ/2 at each of the differential outputs. Version 1.9 02/2017 103 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Single Ended Output Slew Rate Measured Description Defined by From To Single ended output slew rate for rising edge VOL(AC) VOH(AC) [VOH(AC)-VOL(AC)] / DeltaTRse Single ended output slew rate for falling edge VOH(AC) VOL(AC) [VOH(AC)-VOL(AC)] / DeltaTFse Note: Output slew rate is verified by design and characterization, and may not be subject to production test. Single Ended Output Slew Rate Definition Delta TFse Single Ended Output Voltage (i.e. DQ) VOH (AC) VTT VOL (AC) Delta TFse Version 1.9 02/2017 104 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Output Slew Rate (Single-ended) 800 Parameter Single-ended Output Slew Rate Symbol 1066 1333 1600 1866 2133 Unit Min Max Min Max Min Max Min Max Min Max Min Max DDR3 2.5 5 2.5 5 2.5 5 2.5 5 2.5 5 2.5 5 V/ns DDR3L 1.75 5 1.75 5 1.75 5 1.75 5 1.75 5 1.75 5 V/ns SRQse Description: SR: Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) se: Single-ended Signals For Ron = RZQ/7 setting Note 1): In two cases, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane. Case 1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining DQ signals in the same byte lane are static (i.e. they stay at either high or low). Case 2 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining DQ signals in the same byte lane are switching into the opposite direction (i.e. from low to high or high to low respectively). For the remaining DQ signal switching into the opposite direction, the regular maximum limit of 5 V/ns applies. Version 1.9 02/2017 105 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Differential Output Slew Rate Measured Description Defined by From To Differential output slew rate for rising edge VOLdiff(AC) VOHdiff(AC) [VOHdiff(AC)-VOLdiff(AC)] / DeltaTRdiff Differential output slew rate for falling edge VOHdiff(AC) VOLdiff(AC) [VOHdiff(AC)-VOLdiff(AC)] / DeltaTFdiff Note: Output slew rate is verified by design and characterization, and may not be subject to production test. Differential Output Slew Rate Definition Differential Output Voltage (i.e. DQS-DQS) Delta TRdiff V Oh diff (AC) 0 VOL diff (AC) Delta TRdiff Output Slew Rate (Differential) 800 Parameter Differential Output Slew Rate Symbol 1066 1333 1600 1866 2133 DDR3 Unit Min Max Min Max Min Max Min Max Min Max Min Max 5 10 5 10 5 10 5 10 5 12 5 12 V/ns 3.5 12 3.5 12 3.5 12 3.5 12 3.5 12 3.5 12 V/ns SRQdiff DDR3L Description: SR: Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) diff: Differential Signals For Ron = RZQ/7 setting Version 1.9 02/2017 106 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Reference Load for AC Timing and Output Slew Rate The following figure represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate measurements. It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics. VDDQ CK ,  25 Ohm DUT Vtt = VDDQ/2 DQ DQS  Timing Reference Points Version 1.9 02/2017 107 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Overshoot and Undershoot Specifications AC Overshoot/Undershoot Specification for Address and Control Pins - 800 1066 1333 1600 1866 2133 Unit Maximum peak amplitude allowed for overshoot area 0.4 0.4 0.4 0.4 0.4 0.4 V Maximum peak amplitude allowed for undershoot area. 0.4 0.4 0.4 0.4 0.4 0.4 V Maximum overshoot area above VDD 0.67 0.5 0.4 0.33 0.28 0.25 V-ns Maximum undershoot area below VSS 0.67 0.5 0.4 0.33 0.28 0.25 V-ns NOTE 1. The sum of the applied voltage (VDD) and peak amplitude overshoot voltage is not to exceed absolute maximum DC ratings NOTE 2. The sum of applied voltage (VDD) and the peak amplitude undershoot voltage is not to exceed absolute maximum DC ratings Maximum Amplitude Volts (V) Overshoot Area VDD VSS Maximum Amplitude Undershoot Area Time (ns) Version 1.9 02/2017 108 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Overshoot and Undershoot Specifications AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask 800 1066 1333 1600 1866 2133 Unit Maximum peak amplitude allowed for overshoot area 0.4 0.4 0.4 0.4 0.4 0.4 V Maximum peak amplitude allowed for undershoot area. 0.4 0.4 0.4 0.4 0.4 0.4 V Maximum overshoot area above VDD 0.25 0.19 0.15 0.13 0.11 0.10 V-ns Maximum undershoot area below VSS 0.25 0.19 0.15 0.13 0.11 0.10 V-ns NOTE 1. The sum of the applied voltage (VDD) and peak amplitude overshoot voltage is not to exceed absolute maximum DC ratings NOTE 2. The sum of applied voltage (VDD) and the peak amplitude undershoot voltage is not to exceed absolute maximum DC ratings Maximum Amplitude Volts (V) Overshoot Area VDDQ VSSQ Maximum Amplitude Undershoot Area Time (ns) Version 1.9 02/2017 109 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP 34 Ohm Output Driver DC Electrical Characteristics A Functional representation of the output buffer is shown as below. Output driver impedance RON is defined by the value of the external reference resistor RZQ as follows: RON34 = RZQ / 7 (nominal 34.4ohms +/-10% with nominal RZQ=240ohms) The individual pull-up and pull-down resistors (RONPu and RONPd) are defined as follows: RONPu = RONPd = VDDQ – VOut under the condition that RONPd is turned off (1) under the condition that RONPu is turned off (2) | IOut | VOut | IOut | Output Driver: Definition of Voltages and Currents Version 1.9 02/2017 110 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Output Driver DC Electrical Characteristics, assuming RZQ = 240ohms; entire operating temperature range; after proper ZQ calibration RONNom Resistor Vout Min. Nom. Max. Unit Notes VOLdc = 0.2 x VDDQ 0.6 1.0 1.15 RZQ / 7 1,2,3 VOMdc = 0.5 x VDDQ 0.9 1.0 1.15 RZQ / 7 1,2,3 VOHdc = 0.8 x VDDQ 0.9 1.0 1.45 RZQ / 7 1,2,3 VOLdc = 0.2 x VDDQ 0.9 1.0 1.45 RZQ / 7 1,2,3 VOMdc = 0.5 x VDDQ 0.9 1.0 1.15 RZQ / 7 1,2,3 VOHdc = 0.8 x VDDQ 0.6 1.0 1.15 RZQ / 7 1,2,3 VOLdc = 0.2 × VDDQ 0.6 1.0 1.15 RZQ / 6 1,2,3 VOMdc = 0.5 × VDDQ 0.9 1.0 1.15 RZQ / 6 1,2,3 VOHdc = 0.8 × VDDQ 0.9 1.0 1.45 RZQ / 6 1,2,3 VOLdc = 0.2 × VDDQ 0.9 1.0 1.45 RZQ / 6 1,2,3 VOMdc = 0.5 × VDDQ 0.9 1.0 1.15 RZQ / 6 1,2,3 VOHdc = 0.8 × VDDQ 0.6 1.0 1.15 RZQ / 6 1,2,3 VOMdc = 0.5 x VDDQ -10 +10 % 1,2,4 DDR3L RON34Pd 34 ohms RON34Pu RON40Pd 40 ohms RON40Pu Mismatch between pull-up and pull-down, MMPuPd DDR3 RON34Pd VOLdc = 0.2 x VDDQ 0.6 1.0 1.1 RZQ / 7 1,2,3 VOMdc = 0.5 x VDDQ 0.9 1.0 1.1 RZQ / 7 1,2,3 VOHdc = 0.8 x VDDQ 0.9 1.0 1.4 RZQ / 7 1,2,3 VOLdc = 0.2 x VDDQ 0.9 1.0 1.4 RZQ / 7 1,2,3 VOMdc = 0.5 x VDDQ 0.9 1.0 1.1 RZQ / 7 1,2,3 VOHdc = 0.8 x VDDQ 0.6 1.0 1.1 RZQ / 7 1,2,3 VOLdc = 0.2 × VDDQ 0.6 1.0 1.1 RZQ / 6 1,2,3 VOMdc = 0.5 × VDDQ 0.9 1.0 1.1 RZQ / 6 1,2,3 VOHdc = 0.8 × VDDQ 0.9 1.0 1.4 RZQ / 6 1,2,3 VOLdc = 0.2 × VDDQ 0.9 1.0 1.4 RZQ / 6 1,2,3 VOMdc = 0.5 × VDDQ 0.9 1.0 1.1 RZQ / 6 1,2,3 VOHdc = 0.8 × VDDQ 0.6 1.0 1.1 RZQ / 6 1,2,3 VOMdc = 0.5 x VDDQ -10 +10 % 1,2,4 34 ohms RON34Pu RON40Pd 40 ohms RON40Pu Mismatch between pull-up and pull-down, MMPuPd Version 1.9 02/2017 111 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP NOTE 1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity. NOTE 2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS. NOTE 3. Pull-down and pull-up output driver impedances are recommended to be calibrated at 0.5 x VDDQ. Other calibration schemes may be used to achieve the linearity spec shown above, e.g. calibration at 0.2 x VDDQ and 0.8 x VDDQ. NOTE 4. Measurement definition for mismatch between pull-up and pull-down, MMPuPd: Measure RONPu and RONPd, both at 0.5 * VDDQ: MMPuPd = Version 1.9 02/2017 RonPu – RonPd RonNom X 100 112 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Output Driver Temperature and Voltage sensitivity If temperature and/or voltage after calibration, the tolerance limits widen according to the following table. Delta T = T - T(@calibration); Delta V = VDDQ - VDDQ(@calibration); VDD = VDDQ Note: dRONdT and dRONdV are not subject to production test but are verified by design and characterization. Output Driver Sensitivity Definition Items Min. Max. Unit RONPU@VOHdc 0.6 - dRONdTH*lDelta Tl - dRONdVH*lDelta Vl 1.1 + dRONdTH*lDelta Tl - dRONdVH*lDelta Vl RZQ/7 RON@VOMdc 0.9 - dRONdTM*lDelta Tl - dRONdVM*lDelta Vl 1.1 + dRONdTM*lDelta Tl - dRONdVM*lDelta Vl RZQ/7 RONPD@VOLdc 0.6 - dRONdTL*lDelta Tl - dRONdVL*lDelta Vl 1.1 + dRONdTL*lDelta Tl - dRONdVL*lDelta Vl RZQ/7 Output Driver Voltage and Temperature Sensitivity Speed Bin DDR3-800, DDR3(L)-1066/1333 DDR3(L)-1600 Unit Items Min. Max. Min. Max. dRONdTM 0 1.5 0 1.5 %/C dRONdVM 0 0.15 0 0.13 %/mV dRONdTL 0 1.5 0 1.5 %/C dRONdVL 0 0.15 0 0.13 %/mV dRONdTH 0 1.5 0 1.5 %/C dRONdVH 0 0.15 0 0.13 %/mV Note: These parameters may not be subject to production test. They are verified by design and characterization. Version 1.9 02/2017 113 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP On-Die Termination (ODT) Levels and I-V Characteristics On-Die Termination effective resistance RTT is defined by bits A9, A6, and A2 of the MR1 Register. ODT is applied to the DQ, DM, DQS/, and TDQS/T (x8 devices only) pins. A functional representation of the on-die termination is shown in the following figure. The individual pull-up and pull-down resistors (RTTPu and RTTPd) are defined as follows: RTTPu = RTTPd = VDDQ – VOut under the condition that RTTPd is turned off (3) under the condition that RTTPu is turned off (4) | IOut | VOut | IOut | On-Die Termination: Definition of Voltages and Currents Version 1.9 02/2017 114 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP ODT DC Electrical Characteristics The following table provides an overview of the ODT DC electrical characteristics. The values for RTT60Pd120, RTT60Pu120, RTT120Pd240, RTT120Pu240, RTT40Pd80, RTT40Pu80, RTT30Pd60, RTT30Pu60, RTT20Pd40, RTT20Pu40 are not specification requirements, but can be used as design guide lines: ODT DC Electrical Characteristics, assuming RZQ = 240ohms +/- 1% entire operating temperature range; after proper ZQ calibration(DDR3L) MR1 A9,A6,A2 RTT Resistor Vout Min. Nom. Max. Unit Notes VOLdc = 0.2 x VDDQ 0.6 1 1.15 RZQ 1,2,3,4 0.5 x VDDQ 0.9 1 1.15 RZQ 1,2,3,4 VOHdc = 0.8 x VDDQ 0.9 1 1.45 RZQ 1,2,3,4 VOLdc = 0.2 x VDDQ 0.9 1 1.45 RZQ 1,2,3,4 0.5 x VDDQ 0.9 1 1.15 RZQ 1,2,3,4 VOHdc = 0.8 x VDDQ 0.6 1 1.15 RZQ 1,2,3,4 VIL(ac) to VIH(ac) 0.9 1 1.65 RZQ /2 1,2,5 VOLdc = 0.2 x VDDQ 0.6 1 1.15 RZQ/2 1,2,3,4 0.5 x VDDQ 0.9 1 1.15 RZQ/2 1,2,3,4 VOHdc = 0.8 x VDDQ 0.9 1 1.45 RZQ/2 1,2,3,4 VOLdc = 0.2 x VDDQ 0.9 1 1.45 RZQ/2 1,2,3,4 0.5 x VDDQ 0.9 1 1.15 RZQ/2 1,2,3,4 VOHdc = 0.8 x VDDQ 0.6 1 1.15 RZQ/2 1,2,3,4 DDR3L RTT120Pd240 0,1,0 120Ω RTT120Pu240 RTT120 RTT60Pd120 0, 0, 1 60Ω RTT60Pu120 RTT60 RTT40Pd80 0, 1, 1 40Ω RTT40Pu80 RTT40 RTT30Pd60 1, 0, 1 30Ω RTT30Pu60 RTT30 RTT20Pd40 1, 0, 0 20Ω RTT20Pu40 RTT20 VIL(ac) to VIH(ac) 0.9 1 1.65 RZQ/4 1,2,5 VOLdc = 0.2 x VDDQ 0.6 1 1.15 RZQ/3 1,2,3,4 0.5 x VDDQ 0.9 1 1.15 RZQ/3 1,2,3,4 VOHdc = 0.8 x VDDQ 0.9 1 1.45 RZQ/3 1,2,3,4 VOLdc = 0.2 x VDDQ 0.9 1 1.45 RZQ/3 1,2,3,4 0.5 x VDDQ 0.9 1 1.15 RZQ/3 1,2,3,4 VOHdc = 0.8 x VDDQ 0.6 1 1.15 RZQ/3 1,2,3,4 VIL(ac) to VIH(ac) 0.9 1 1.65 RZQ/6 1,2,5 VOLdc = 0.2 x VDDQ 0.6 1 1.15 RZQ/4 1,2,3,4 0.5 x VDDQ 0.9 1 1.15 RZQ/4 1,2,3,4 VOHdc = 0.8 x VDDQ 0.9 1 1.45 RZQ/4 1,2,3,4 VOLdc = 0.2 x VDDQ 0.9 1 1.45 RZQ/4 1,2,3,4 0.5 x VDDQ 0.9 1 1.15 RZQ/4 1,2,3,4 VOHdc = 0.8 x VDDQ 0.6 1 1.15 RZQ/4 1,2,3,4 VIL(ac) to VIH(ac) 0.9 1 1.65 RZQ/8 1,2,5 VOLdc = 0.2 x VDDQ 0.6 1 1.15 RZQ/6 1,2,3,4 0.5 x VDDQ 0.9 1 1.15 RZQ/6 1,2,3,4 VOHdc = 0.8 x VDDQ 0.9 1 1.45 RZQ/6 1,2,3,4 VOLdc = 0.2 x VDDQ 0.9 1 1.45 RZQ/6 1,2,3,4 0.5 x VDDQ 0.9 1 1.15 RZQ/6 1,2,3,4 VOHdc = 0.8 x VDDQ 0.6 1 1.15 RZQ/6 1,2,3,4 VIL(ac) to VIH(ac) 0.9 1 1.65 RZQ/12 1,2,5 +5 % 1,2,5,6 Deviation of VM w.r.t. VDDQ/2, DVM Version 1.9 02/2017 -5 115 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP ODT DC Electrical Characteristics, assuming RZQ = 240ohms +/- 1% entire operating temperature range; after proper ZQ calibration (DDR3) MR1 A9,A6,A2 RTT Resistor Vout Min. Nom. Max. Unit Notes VOLdc = 0.2 x VDDQ 0.6 1 1.1 RZQ 1,2,3,4 DDR3 RTT120Pd240 0,1,0 120Ω RTT120Pu240 RTT120 RTT60Pd120 0, 0, 1 60Ω RTT60Pu120 RTT60 RTT40Pd80 0, 1, 1 40Ω RTT40Pu80 RTT40 RTT30Pd60 1, 0, 1 30Ω RTT30Pu60 RTT30 RTT20Pd40 1, 0, 0 20Ω RTT20Pu40 RTT20 0.5 x VDDQ 0.9 1 1.1 RZQ 1,2,3,4 VOHdc = 0.8 x VDDQ 0.9 1 1.4 RZQ 1,2,3,4 VOLdc = 0.2 x VDDQ 0.9 1 1.4 RZQ 1,2,3,4 0.5 x VDDQ 0.9 1 1,1 RZQ 1,2,3,4 VOHdc = 0.8 x VDDQ 0.6 1 1.1 RZQ 1,2,3,4 VIL(ac) to VIH(ac) 0.9 1 1.6 RZQ /2 1,2,5 VOLdc = 0.2 x VDDQ 0.6 1 1.1 RZQ/2 1,2,3,4 0.5 x VDDQ 0.9 1 1.1 RZQ/2 1,2,3,4 VOHdc = 0.8 x VDDQ 0.9 1 1.4 RZQ/2 1,2,3,4 VOLdc = 0.2 x VDDQ 0.9 1 1.4 RZQ/2 1,2,3,4 0.5 x VDDQ 0.9 1 1.1 RZQ/2 1,2,3,4 VOHdc = 0.8 x VDDQ 0.6 1 1.1 RZQ/2 1,2,3,4 VIL(ac) to VIH(ac) 0.9 1 1.6 RZQ/4 1,2,5 VOLdc = 0.2 x VDDQ 0.6 1 1.1 RZQ/3 1,2,3,4 0.5 x VDDQ 0.9 1 1.1 RZQ/3 1,2,3,4 VOHdc = 0.8 x VDDQ 0.9 1 1.4 RZQ/3 1,2,3,4 VOLdc = 0.2 x VDDQ 0.9 1 1.4 RZQ/3 1,2,3,4 0.5 x VDDQ 0.9 1 1.1 RZQ/3 1,2,3,4 VOHdc = 0.8 x VDDQ 0.6 1 1.1 RZQ/3 1,2,3,4 VIL(ac) to VIH(ac) 0.9 1 1.6 RZQ/6 1,2,5 VOLdc = 0.2 x VDDQ 0.6 1 1.1 RZQ/4 1,2,3,4 0.5 x VDDQ 0.9 1 1.1 RZQ/4 1,2,3,4 VOHdc = 0.8 x VDDQ 0.9 1 1.4 RZQ/4 1,2,3,4 VOLdc = 0.2 x VDDQ 0.9 1 1.4 RZQ/4 1,2,3,4 0.5 x VDDQ 0.9 1 1.1 RZQ/4 1,2,3,4 VOHdc = 0.8 x VDDQ 0.6 1 1.1 RZQ/4 1,2,3,4 VIL(ac) to VIH(ac) 0.9 1 1.6 RZQ/8 1,2,5 VOLdc = 0.2 x VDDQ 0.6 1 1.1 RZQ/6 1,2,3,4 0.5 x VDDQ 0.9 1 1.1 RZQ/6 1,2,3,4 VOHdc = 0.8 x VDDQ 0.9 1 1.4 RZQ/6 1,2,3,4 VOLdc = 0.2 x VDDQ 0.9 1 1.4 RZQ/6 1,2,3,4 0.5 x VDDQ 0.9 1 1.1 RZQ/6 1,2,3,4 VOHdc = 0.8 x VDDQ 0.6 1 1.1 RZQ/6 1,2,3,4 VIL(ac) to VIH(ac) 0.9 1 1.6 RZQ/12 1,2,5 +5 % 1,2,5,6 Deviation of VM w.r.t. VDDQ/2, DVM Version 1.9 02/2017 -5 116 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP NOTE 1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity. NOTE 2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS. NOTE 3. Pull-down and pull-up ODT resistors are recommended to be calibrated at 0.5 x VDDQ. Other calibration schemes may be used to achieve the linearity spec shown above, e.g. calibration at 0.2 x VDDQ and 0.8 x VDDQ. NOTE 4. Not a specification requirement, but a design guide line. NOTE 5. Measurement definition for RTT: Apply VIH(ac) to pin under test and measure current I(VIH(ac)), then apply VIL(ac) to pin under test and measure current I(VIL(ac)) respectively. RTT = VIH(ac) – VIL(ac) I(VIH(ac)) – I(VIL(ac)) NOTE 6. Measurement definition for VM and DVM: Measure voltage (VM) at test pin (midpoint) with no load: △VM = ( 2 x VM – 1) x 100 VDDQ Version 1.9 02/2017 117 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP ODT Temperature and Voltage sensitivity If temperature and/or voltage after calibration, the tolerance limits widen according to the following table. Delta T = T - T(@calibration); Delta V = VDDQ - VDDQ(@calibration); VDD = VDDQ ODT Sensitivity Definition Min. RTT Max. 0.9 – dRTTdT * l△Tl – dRTTdV * l△Vl Unit 1.6 + dRTTdT * l△Tl + dRTTdV * l△Vl RZQ/2,4,6,8,12 ODT Voltage and Temperature Sensitivity Min. Max. Unit dRTTdT 0 1.5 %/C dRTTdV 0 0.15 %/mV Note: These parameters may not be subject to production test. They are verified by design and characterization. Test Load for ODT Timings Different than for timing measurements, the reference load for ODT timings is defined in the following figure. VDDQ CK ,  DUT RTT= 25 Ohm Vtt = VSSQ DQ , DM DQS ,  TDQS , T Timing Reference Points VSSQ ODT Timing Reference Load Version 1.9 02/2017 118 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP ODT Timing Definitions Definitions for tAON, tAONPD, tAOF, tAOFPD, and tADC are provided in the following table and subsequent figures. Symbol Begin Point Definition End Point Definition tAON Rising edge of CK -  defined by the end point of ODTLon Extrapolated point at VSSQ tAONPD Rising edge of CK -  with ODT being first registered high Extrapolated point at VSSQ tAOF Rising edge of CK -  defined by the end point of ODTLoff End point: Extrapolated point at VRTT_Nom tAOFPD Rising edge of CK -  with ODT being first registered low End point: Extrapolated point at VRTT_Nom Rising edge of CK -  defined by the end point of ODTLcnw, End point: Extrapolated point at VRTT_Wr and ODTLcwn4, or ODTLcwn8 VRTT_Nom respectively tADC Reference Settings for ODT Timing Measurements DDR3 Parameter RTT_Nom DDR3L RTT_Wr VSW1[V] VSW2[V] VSW1[V] VSW2[V] RZQ/4 NA 0.05 0.10 0.05 0.10 RZQ/12 NA 0.10 0.20 0.10 0.20 RZQ/4 NA 0.05 0.10 0.05 0.10 RZQ/12 NA 0.10 0.20 0.10 0.20 RZQ/4 NA 0.05 0.10 0.05 0.10 RZQ/12 NA 0.10 0.20 0.10 0.20 RZQ/4 NA 0.05 0.10 0.05 0.10 RZQ/12 NA 0.10 0.20 0.10 0.20 RZQ/12 RZQ/2 0.20 0.30 0.20 0.25 tAON tAONPD tAOF tAOFPD tADC Definition of tAON Begin point: Rising edge of CK – CK# Defined by the end point of ODTLon CK VTT CK# tAON Tsw2 Tsw1 DQ, DM DQS, DQS# TDQS, TDQS# Vsw2 Vsw1 VSSQ End point: Extrapolated point at VSSQ Version 1.9 02/2017 119 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Definition of tAONPD Begin point: Rising edge of CK – CK# with ODT being first register high CK VTT CK# tAONPD Tsw2 Tsw1 DQ, DM DQS, DQS# TDQS, TDQS# Vsw2 Vsw1 VSSQ End point: Extrapolated point at VSSQ Definition of tAOF Begin point: Rising edge of CK – CK# defined by the end point of ODTLoff CK VTT CK# tAOF VRTT_Nom End point: Extrapolated point at VRTT_Nom Tsw2 DQ, DM DQS, DQS# TDQS, TDQS# Version 1.9 02/2017 Tsw1 Vsw2 Vsw1 VSSQ 120 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Definition of tAOFPD Begin point: Rising edge of CK – CK# with ODT being first registered low CK VTT CK# tAOFPD VRTT_Nom End point: Extrapolated point at VRTT_Nom Tsw2 DQ, DM DQS, DQS# TDQS, TDQS# Tsw1 Vsw2 Vsw1 VSSQ Definition of tADC Begin point: Rising edge of CK – CK# defined by the end of ODTLcnw CK Begin point: Rising edge of CK – CK# defined by the end of ODTLcwn4 or ODTLcwn8 CK VTT CK# CK# tADC VRTT_Nom tADC End point: Extrapolated point at VRTT_Nom Tsw22 Tsw21 DQ, DM DQS, DQS# TDQS, TDQS# Tsw12 Tsw11 Vsw2 Version 1.9 02/2017 VRTT_Nom VRTT_Wr Vsw1 121 End point: Extrapolated point at VRTT_Wr VSSQ Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Input/Output Capacitance 800 Parameter 1066 1333 1600 1866 2133 Symbol Unit Notes 2.1 pF 1,2,3 - - pF 1,2,3 Min Max Min Max Min Max Min Max Min Max Min Max 1.4 3.0 1.4 2.7 1.4 2.5 1.4 2.3 1.4 2.2 1.4 1.4 2.5 1.4 2.5 1.4 2.3 1.4 2.2 1.4 2.1 CIO Input/output capacitance (DDR3) (DQ, DM, DQS, , CIO TDQS,T) (DDR3L) Input capacitance, CK and  CCK 0.8 1.6 0.8 1.6 0.8 1.4 0.8 1.4 0.8 1.3 0.8 1.3 pF 2,3 Input capacitance delta, CK and  CDCK 0 0.15 0 0.15 0 0.15 0 0.15 0 0.15 0 0.15 pF 2,3,4 CDDQS 0 0.15 0 0.15 0 0.15 0 0.15 0 0.15 0 0.15 pF 2,3,5 0.75 1.4 0.75 1.35 0.75 1.3 0.75 1.3 0.75 1.2 0.75 1.2 pF 2,3,6 0.75 1.3 0.75 1.3 0.75 1.3 0.75 1.2 0.75 1.2 - - pF 2,3,6 -0.5 0.3 -0.5 0.3 -0.4 0.2 -0.4 0.2 -0.4 0.2 -0.4 0.2 pF 2,3,7,8 -0.5 0.5 -0.5 0.5 -0.4 0.4 -0.4 0.4 -0.4 0.4 -0.4 0.4 pF Input/output capacitance delta DQS and  CI Input capacitance, (DDR3) (CTRL, ADD,CMD input-only pins) CI (DDR3L) Input capacitance delta, CDI_CTRL (All CTRL input-only pins Input capacitance delta, (All ADD/CMD input-only pins) CDI_ADD_ 2,3,9, CMD 10 Input/output capacitance delta, DQ, CDIO -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 pF 2,3,11 CZQ - 3 - 3 - 3 - 3 - 3 - 3 pF 2,3,12 DM, DQS, , TDQS, T Input/output capacitance of ZQ pin NOTE 1. Although the DM, TDQS and T pins have different functions, the loading matches DQ and DQS NOTE 2. This parameter is not subject to production test. It is verified by design and characterization. The capacitance is measured according to JEP147(“PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER(VNA)”) with VDD, VDDQ, VSS, VSSQ applied and all other pins floating (except the pin under test, CKE, REET and ODT as necessary). VDD=VDDQ=1.5V, VBIAS=VDD/2 and ondie termination off. NOTE 3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here NOTE 4. Absolute value of CCK- NOTE 5. Absolute value of CIO(DQS)-CIO() NOTE 6. CI applies to ODT, , CKE, A0-A14, BA0-BA2, RA, A, WE. NOTE 7. CDI_CTRL applies to ODT,  and CKE NOTE 8. CDI_CTRL=CI(CTRL)-0.5*(CI(CLK)+CI(L)) NOTE 9. CDI_ADD_CMD applies to A0-A14, BA0-BA2, RA, A and WE NOTE 10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(L)) NOTE 11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO()) NOTE 12. Maximum external load capacitance on ZQ pin: 5 pF. Version 1.9 02/2017 122 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP DDR3L IDD Currents Symbol IDD0 IDD1 IDD2P0 IDD2P1 DDR3L-1600 (11-11-11) Parameter/Condition Operating Current 0 One Bank Activate-> Precharge Operating Current 1 One Bank Activate-> Read-> Precharge Precharge Power-Down Current Slow Exit - MR0 bit A12 = 0 Precharge Power-Down Current Fast Exit - MR0 bit A12 = 1 DDR3L-1866 (13-13-13) Unit X8 X16 X8 X16 62 67 67 72 mA 71 76 76 81 mA 11 12 11 12 mA 20 23 mA IDD2Q Precharge Quiet Standby Current 32 37 mA IDD2N Precharge Standby Current 32 37 mA IDD2NT Precharge Standby ODT Current 37 40 42 45 mA IDD3P Active Power-Down Current Always Fast Exit IDD3N Active Standby Current 42 45 47 50 mA IDD4R Operating Current Burst Read 140 150 150 160 mA IDD4W Operating Current Burst Write 145 155 155 165 mA IDD5B Burst Refresh Current IDD6TC 1 (RS -DIB) IDD6 2 IDD6ET 3 32 Self-Refresh Current: Room Temperature Range Self-Refresh Current Normal Self-Refresh Current: Extended IDD7 All Bank Interleave Read Current IDD8 Reset Low Current 37 mA 135 140 mA 3 3 mA 11 12 11 14 210 12 14 220 220 13 mA 230 13 mA mA mA NOTE 1 IDD6TC (RS-DIB):TC ≤ Room Temperature; SRT is disabled, ASR is enabled. Value is maximum. NOTE 2 IDD6: SRT is ‘Normal’, ASR is disabled. Value is maximum. - Commercial Grade = 0℃~85℃ - Quasi Industrial Grade (-T) = -40℃~85℃ - Industrial Grade (-I) = -40℃~85℃ - Automotive Grade 2 (-H) = -40℃~85℃ - Automotive Grade 3 (-A) = -40℃~85℃ NOTE 3 IDD6ET: SRT is ‘Extended’, ASR is disabled. Value is maximum. - Commercial Grade = 0℃~95℃ - Quasi Industrial Grade (-T) = -40℃~95℃ - Industrial Grade (-I) = -40℃~95℃ - Automotive Grade 2 (-H) = -40℃~105℃ - Automotive Grade 3 (-A) = -40℃~95℃ NOTE 4 IDD will be derated (increased) when above 95℃ Version 1.9 02/2017 123 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP DDR3 IDD Currents Symbol Parameter/Condition DDR3-1600 (11-11-11) DDR3-1866 (13-13-13) DDR3-2133 (14-14-14) X8 X16 X8 X16 X8 X16 Unit IDD0 Operating Current 0 One Bank Activate -> Precharge 65 70 70 75 75 80 mA IDD1 Operating Current 1 One Bank Activate-> Read-> Precharge 75 80 80 85 85 90 mA IDD2P0 Precharge Power-Down Current Slow Exit - MR0 bit A12 = 0 12 15 12 15 12 16 mA IDD2P1 Precharge Power-Down Current Fast Exit - MR0 bit A12 = 1 22 25 28 mA IDD2Q Precharge Quiet Standby Current 35 40 45 mA IDD2N Precharge Standby Current 35 40 45 mA IDD2NT Precharge Standby ODT Current 40 43 45 48 50 53 mA IDD3P Active Power-Down Current Always Fast Exit IDD3N Active Standby Current 45 55 50 53 55 58 mA IDD4R Operating Current Burst Read 145 155 150 160 165 175 mA IDD4W Operating Current Burst Write 150 160 160 170 170 180 mA IDD5B Burst Refresh Current 145 145 150 12 12 15 12 15 mA IDD6 1 IDD6ET 2 Self-Refresh Current Normal Self-Refresh Current Extended IDD7 All Bank Interleave Read Current IDD8 Reset Low Current 35 40 45 mA 155 mA 15 17 15 17 15 17 mA 230 240 240 250 250 260 mA 14 mA NOTE 1 IDD6: SRT is ‘Normal’, ASR is disabled. Value is maximum. - Commercial Grade = 0℃~85℃ - Quasi Industrial Grade (-T) = -40℃~85℃ - Industrial Grade (-I) = -40℃~85℃ - Automotive Grade 2 (-H) = -40℃~85℃ - Automotive Grade 3 (-A) = -40℃~85℃ NOTE 2 IDD6ET: SRT is ‘Extended’, ASR is disabled. Value is maximum. - Commercial Grade = 0℃~95℃ - Quasi Industrial Grade (-T) = -40℃~95℃ - Industrial Grade (-I) = -40℃~95℃ - Automotive Grade 2 (-H) = -40℃~105℃ - Automotive Grade 3 (-A) = -40℃~95℃ NOTE 3 IDD will be derated (increased) when above 95℃ Version 1.9 02/2017 124 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP IDD Measurement Conditions Symbol Parameter/Condition Operating One Bank Active-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, CL: see the table of Timings used for IDD and IDDQ; BL: 8(1); AL: 0; :High between ACT and PRE; IDD0 Command, Address, Bank Address Inputs: partially toggling; Data IO: MID-LEVEL; DM:stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,...; Output Buffer and RTT: Enabled in Mode Registers(2); ODT Signal: stable at 0; Operating One Bank Active-Read-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see see the table of Timings used for IDD and IDDQ; BL: 8(1,7); AL:0; IDD1 : High between ACT, RD and PRE; Command, Address, Bank Address Inputs, Data IO: partially toggling; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,...; Output Buffer and RTT: Enabled in Mode Registers(2); ODT Signal: stable at 0; Precharge Standby Current CKE: High; External clock: On; tCK, CL: see the table of Timings used for IDD and IDDQ; BL: 8(1); AL: 0; : stable at 1; Command, Address, Bank Address Inputs: partially toggling; IDD2N Data IO: MID-LEVEL; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers(2); ODT Signal: stable at 0; Precharge Power-Down Current Slow Exit CKE: Low; External clock: On; IDD2P(0) tCK, CL: see the table of Timings used for IDD and IDDQ; BL: 8(1); AL: 0; : stable at 1; Version 1.9 02/2017 125 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Command, Address, Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers(2); ODT Signal: stable at 0; Pecharge Power Down Mode: Slow Exit(3) Precharge Power-Down Current Fast Exit CKE: Low; External clock: On; tCK, CL: see the table of Timings used for IDD and IDDQ; BL: 8(1); AL: 0; : stable at 1; Command, Address, Bank Address Inputs: stable at 0; IDD2P(1) Data IO: MID-LEVEL; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers(2); ODT Signal: stable at 0; Pecharge Power Down Mode: Fast Exit(3) Precharge Quiet Standby Current CKE: High; External clock: On; tCK, CL: see the table of Timings used for IDD and IDDQ; BL: 8(1); AL: 0; : stable at 1; IDD2Q Command, Address, Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers(2); ODT Signal: stable at 0 Active Standby Current CKE: High; External clock: On; tCK, CL: see the table of Timings used for IDD and IDDQ; BL: 8(1); AL: 0; IDD3N : stable at 1; Command, Address, Bank Address Inputs: partially toggling; Data IO: MID-LEVEL; DM:stable at 0; Version 1.9 02/2017 126 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers(2); ODT Signal: stable at 0; Active Power-Down Current CKE: Low; External clock: On; tCK, CL: see the table of Timings used for IDD and IDDQ; BL: 8(1); AL: 0; : stable at 1; IDD3P Command, Address, Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM:stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers(2); ODT Signal: stable at 0 Operating Burst Read Current CKE: High; External clock: On; tCK, CL: see the table of Timings used for IDD and IDDQ; BL: 8(1,7); AL: 0; : High between RD; IDD4R Command, Address, Bank Address Inputs: partially toggling; Data IO: seamless read data burst with different data between one burst and the next one; DM:stable at 0; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...; Output Buffer and RTT: Enabled in Mode Registers(2); ODT Signal: stable at 0; Operating Burst Write Current CKE: High; External clock: On; tCK, CL: see the table of Timings used for IDD and IDDQ; BL: 8(1); AL: 0; : High between WR; IDD4W Command, Address, Bank Address Inputs: partially toggling; Data IO: seamless write data burst with different data between one burst and the next one ; DM: stable at 0; Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,...; Output Buffer and RTT: Enabled in Mode Registers(2); ODT Signal: stable at HIGH; Version 1.9 02/2017 127 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Burst Refresh Current CKE: High; External clock: On; tCK, CL, nRFC: see the table of Timings used for IDD and IDDQ; BL: 8(1); AL: 0; : High between REF; IDD5B Command, Address, Bank Address Inputs: partially toggling; Data IO: MID-LEVEL; DM:stable at 0; Bank Activity: REF command every nRFC; Output Buffer and RTT: Enabled in Mode Registers(2); ODT Signal: stable at 0; Self Refresh Current: Normal Temperature Range TCASE: Normal Temperature Range; Auto Self-Refresh (ASR): Disabled(4); Self-Refresh Temperature Range (SRT):Normal(5); CKE: Low; External clock: Off; CK and : LOW; CL: see the table of Timings used for IDD and IDDQ; IDD6 BL: 8(1);AL: 0; , Command, Address, Bank Address, Data IO: MID-LEVEL; DM:stable at 0; Bank Activity:Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers(2); ODT Signal: MID-LEVEL Self-Refresh Current: Extended Temperature Range (6) TCASE: Extended Temperature Range; Auto Self-Refresh (ASR): Disabled(4); Self-Refresh Temperature Range (SRT):Extended(5); CKE: Low; External clock: Off; CK and : LOW; CL: see the table of Timings used for IDD and IDDQ; IDD6ET BL: 8(1);AL: 0; , Command, Address, Bank Address, Data IO: MID-LEVEL; DM:stable at 0; Bank Activity:Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers(2); ODT Signal: MID-LEVEL Auto Self-Refresh Current (6) IDD6TC Auto Self-Refresh (ASR): Enabled(4); Self-Refresh Temperature Range (SRT):Normal(5); Version 1.9 02/2017 128 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP CKE: Low; External clock: Off; CK and : LOW; CL: see the table of Timings used for IDD and IDDQ; BL: 8(1);AL: 0; , Command, Address, Bank Address, Data IO: MID-LEVEL; DM:stable at 0; Bank Activity:Auto Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers(2); ODT Signal: MIDLEVEL Operating Bank Interleave Read Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see the table of Timings used for IDD and IDDQ; BL: 8(1,7); AL: CL-1; : High between ACT and RDA; Command, Address, Bank Address Inputs:partially toggling; IDD7 Data IO: read data bursts with different data between one burst and the next one; DM:stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing; Output Buffer and RTT: Enabled in Mode Registers(2); ODT Signal: stable at 0; RESET Low Current RESET: LOW; External clock: Off; CK and : LOW; CKE: FLOATING; IDD8 , Command, Address,Bank Address, Data IO: FLOATING; ODT Signal: FLOATING RESET Low current reading is valid once power is stable and RESET has been LOW for at least 1ms. NOTE 1. Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B NOTE 2. Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B NOTE 3. Pecharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit NOTE 4. Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature NOTE 5. Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range NOTE 6. Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM device NOTE 7. Read Burst Type: Nibble Sequential, set MR0 A[3] = 0B Version 1.9 02/2017 129 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP IDD0 Measurement-Loop Pattern Version 1.9 02/2017 130 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP IDD1 Measurement-Loop Pattern Version 1.9 02/2017 131 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP IDD2N and IDD3N Measurement-Loop Pattern Version 1.9 02/2017 132 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP IDD4R and IDDQ4R Measurement-Loop Pattern IDD4W Measurement-Loop Pattern Version 1.9 02/2017 133 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP IDD5B Measurement-Loop Pattern Version 1.9 02/2017 134 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP IDD7 Measurement-Loop Pattern Version 1.9 02/2017 135 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Fundamental AC Specifications – Operating Frequency DDR3-2133 DDR3-2133 14-14-14 Speed Bins Parameter CWL5 CL6 CL7 CL8 tCK Min Max 2.5 3.3 CL9 CWL6 Reserved ns Reserved ns CWL5 Reserved ns CWL6 1.875 < 2.5 ns CWL7 Reserved ns CWL8/9/10 Reserved ns CWL5 Reserved ns CWL6 1.875 < 2.5 ns CWL7 Reserved ns CWL8/9/10 Reserved ns CWL7 ns Reserved 1.5 < 1.875 ns CWL8 Reserved ns CWL9/10 Reserved ns CWL5/6 Reserved ns CWL7 CL10 ns CWL7/8/9/10 CWL5/6 (Avg) Unit 1.5 < 1.875 ns CWL8 Reserved ns CWL9 Reserved ns CWL10 Reserved ns CWL5/6/7 CWL8 ns Reserved 1.25 < 1.5 ns CL11 CL12 tCK (Avg) CL13 CWL9 Reserved ns CWL10 Reserved ns CWL5/6/7/8 Reserved ns CWL9 Reserved ns CWL10 Reserved ns CWL5/6/7/8 Reserved ns CWL9 1.07 < 1.25 ns CWL10 Reserved ns CWL5/6/7/8/9 Reserved ns CL14 CWL10 0.938 < 1.07 ns Supported CL 6,7,8,9,10,11,13,14 nCK Supported CWL 5,6,7,8,9,10 nCK Version 1.9 02/2017 136 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Fundamental AC Specifications – Operating Frequency DDR3-1866 and DDR3L-1866 DDR3(L)-1866 Speed Bins Parameter CWL5 CL6 CL7 13-13-13 Unit Min Max 2.5 3.3 ns CWL6 Reserved ns CWL7/8/9 Reserved ns CWL5 Reserved ns CWL6 1.875 ns < 2.5 CWL7/8/9 Reserved ns CWL5 Reserved ns CWL6 1.875 ns < 2.5 CL8 tCK CWL7 Reserved ns CWL8/9 Reserved ns CWL5/6 Reserved ns CWL7 1.5 ns < 1.875 CL9 (Avg) CL10 CL11 CWL8 Reserved ns CWL9 Reserved ns CWL5/6 Reserved ns CWL7 1.5 ns < 1.875 CWL8 Reserved ns CWL5/6/7 Reserved ns CWL8 1.25 ns < 1.5 CWL9 Reserved ns CWL5/6/7/8 Reserved ns CL12 CWL9 < 1.25 ns Reserved ns Reserved CWL5/6/7/8 CL13 CWL9 1.07 ns < 1.25 Supported CL 6,7,8,9,10,11,13 nCK Supported CWL 5, 6, 7, 8, 9 nCK Version 1.9 02/2017 137 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Fundamental AC Specifications – Operating Frequency DDR3-1600 and DDR3L-1600 DDR3(L)-1600 Speed Bins Parameter CWL5 CL6 Unit 11-11-11 Min Max 2.5 3.3 ns CWL6 Reserved ns CWL7/8 Reserved ns CWL5 Reserved ns CWL6 1.875 < 2.5 ns CL7 tCK CWL7 Reserved ns CWL8 Reserved ns CWL5 Reserved ns CWL6 1.875 < 2.5 ns CL8 (Avg) CL9 CL10 CWL7 Reserved ns CWL8 Reserved ns CWL5/6 Reserved ns CWL7 1.5 VIH(ac)=VREF(dc)+175mV, VIL(ac)=VREF(dc)-175mV CK,  Differential Slew Rate 4.0 V/ns CMD/ADD 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH 2 88 50 88 50 88 50 96 58 104 66 112 74 120 84 128 100 1.5 59 34 59 34 59 34 67 42 75 50 83 58 91 68 99 84 1 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 -2 -4 -2 -4 -2 -4 6 4 14 12 22 20 30 30 38 46 Slew rate 0.8 -6 -10 -6 -10 -6 -10 2 -2 10 6 18 14 26 24 34 40 V/ns 0.7 -11 -16 -11 -16 -11 -16 -3 -8 5 0 13 8 21 18 29 34 0.6 -17 -26 -17 -26 -17 -26 -9 -18 -1 -10 7 -2 15 8 23 24 0.5 -35 -40 -35 -40 -35 -40 -27 -32 -19 -24 -11 -16 -2 -6 5 10 0.4 -62 -60 -62 -60 -62 -60 -54 -52 -46 -44 -38 -36 -30 -26 -22 -10 Version 1.9 02/2017 151 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Derating values DDR3-800/1066/1333/1600 tIS/tIH - AC/DC based AC150 Threshold DDR3 Alternate AC150 Threshold -> VIH(ac)=VREF(dc)+150mV, VIL(ac)=VREF(dc)-150mV CK,  Differential Slew Rate 4.0 V/ns CMD/ADD 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH 2 75 50 75 50 75 50 83 58 91 66 99 74 107 84 115 100 1.5 50 34 50 34 50 34 58 42 66 50 74 58 82 68 90 84 1 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 0 -4 0 -4 0 -4 8 4 16 12 24 20 32 30 40 46 Slew rate 0.8 0 -10 0 -10 0 -10 8 -2 16 6 24 14 32 24 40 40 V/ns 0.7 0 -16 0 -16 0 -16 8 -8 16 0 24 8 32 18 40 34 0.6 -1 -26 -1 -26 -1 -26 7 -18 15 -10 23 -2 31 8 39 24 0.5 -10 -40 -10 -40 -10 -40 -2 -32 6 -24 14 -16 22 -6 30 10 0.4 -25 -60 -25 -60 -25 -60 -17 -52 -9 -44 -1 -36 7 -26 15 -10 Derating values DDR3-1866/2133 tIS/tIH - AC/DC based AC135 Threshold DDR3 Alternate AC135 Threshold -> VIH(ac)=VREF(dc)+135mV, VIL(ac)=VREF(dc)-135mV CK,  Differential Slew Rate 4.0 V/ns CMD/ADD 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH 2 68 50 68 50 68 50 76 58 84 66 92 74 100 84 108 100 1.5 45 34 45 34 45 34 53 42 61 50 69 58 77 68 85 84 1 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 10 4 18 12 26 20 34 30 42 46 0.9 2 -4 2 -4 2 -4 Slew rate 0.8 3 -10 3 -10 3 -10 11 -2 19 6 27 14 35 24 43 40 V/ns 0.7 6 -16 6 -16 6 -16 14 -8 22 0 30 8 38 18 46 34 0.6 9 -26 9 -26 9 -26 17 -18 25 -10 33 -2 41 8 49 24 0.5 5 -40 5 -40 5 -40 13 -32 21 -24 29 -16 37 -6 45 10 0.4 -3 -60 -3 -60 -3 -60 6 -52 14 -44 22 -36 30 -26 38 -10 Version 1.9 02/2017 152 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Derating values DDR3-1866/2133 tIS/tIH - AC/DC based AC125 Threshold DDR3 Alternate AC125 Threshold -> VIH(ac)=VREF(dc)+125mV, VIL(ac)=VREF(dc)-125mV CK,  Differential Slew Rate 4.0 V/ns CMD/ADD 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH 2 63 50 63 50 63 50 71 58 79 66 87 74 95 84 103 100 1.5 42 34 42 34 42 34 50 42 58 50 66 58 74 68 82 84 1 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 4 -4 4 -4 4 -4 12 4 20 12 28 20 36 30 44 46 Slew rate 0.8 6 -10 6 -10 6 -10 14 -2 22 6 30 14 38 24 46 40 V/ns 0.7 11 -16 11 -16 11 -16 19 -8 27 0 35 8 43 18 51 34 0.6 16 -26 16 -26 16 -26 24 -18 32 -10 40 -2 48 8 56 24 0.5 15 -40 15 -40 15 -40 23 -32 31 -24 39 -16 47 -6 55 10 0.4 13 -60 13 -60 13 -60 21 -52 29 -44 37 -36 45 -26 53 -10 Version 1.9 02/2017 153 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Required time tVAC above VIH(AC) {below VIL(AC)} for ADD/CMD transition DDR3 Slew Rate 800/1066/1333/1600 DDR3L 1866/2133 1066/1333/1600 1866 Unit [V/ns] 175mV [ps] 150mV[ps] 135mV [ps] 125mV [ps] 160 mV [ps] 135 mV [ps] 135 mV [ps] 125 mV [ps] > 2.0 75 175 168 173 200 213 200 205 ps 2.0 57 170 168 173 200 213 200 205 ps 1.5 50 167 145 152 173 190 178 184 ps 1.0 38 130 100 110 120 145 133 143 ps 0.9 34 113 85 96 102 130 118 129 ps 0.8 29 93 66 79 80 111 99 111 ps 0.7 22 66 42 56 51 87 75 89 ps 0.6 note 30 10 27 13 55 43 59 ps 0.5 note note note note Note 10 Note 18 ps VIH(AC)=VREF(DC)+160mV, VIL(AC)=VREF(DC)-160mV DQS,  Differential Slew Rate 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH DQ 2 80 45 80 45 80 45 - - - - - - - - - - 1.5 53 30 53 30 53 30 61 38 - - - - - - - - 1 0 0 0 0 0 0 8 8 16 16 - - - - - - 0.9 - - -1 -3 -1 -3 7 5 15 13 23 21 - - - - Slew rate 0.8 - - - - -3 -8 5 1 13 9 21 17 29 27 - - V/ns 0.7 - - - - - - 3 -5 11 3 19 11 27 21 35 37 0.6 - - - - - - - - 8 -4 16 4 24 14 32 30 0.5 - - - - - - - - - - 4 -6 12 4 20 20 0.4 - - - - - - - - - - - - -8 -11 0 5 NOTE1: Cell contents shaded in gray are defined as ‘not supported’. Version 1.9 02/2017 155 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Derating values DDR3L-1066/1333/1600 tDS/tDH - AC/DC based AC135/ Threshold DDR3L Alternate AC135 Threshold -> VIH(AC)=VREF(DC)+135mV, VIL(AC)=VREF(DC)-135mV DQS,  Differential Slew Rate 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH DQ 2 68 45 68 45 68 45 - - - - - - - - - 1.5 45 30 45 30 45 30 53 38 - - - - - - - - 1 0 0 0 0 0 0 8 8 16 16 - - - - - - 0.9 - - 2 -3 2 -3 10 5 18 13 26 21 - - - - Slew rate 0.8 - - - - 3 -8 11 1 19 9 27 17 35 27 - - V/ns 0.7 - - - - - - 14 -5 22 3 30 11 38 21 46 37 0.6 - - - - - - - - 25 -4 33 4 41 14 49 30 0.5 - - - - - - - - - - 29 -6 37 4 45 20 0.4 - - - - - - - - - - - - 30 -11 38 5 NOTE1: Cell contents shaded in gray are defined as ‘not supported’. Derating values DDR3L- 1866 tDS/tDH - AC/DC based AC130 Threshold DDR3L Alternate AC130 Threshold -> VIH(AC)=VREF(DC)+130mV, VIL(AC)=VREF(DC)-130mV DQS,  Differential Slew Rate 8.0 V/ns 7.0 V/ns 6.0 V/ns 5.0 V/ns △tDS △tDH △tDS △tDH △tDS △tDH △tDS DQ 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH 4 33 23 33 23 33 23 - - - - - - - - - - - - - - - - - - 3.5 28 19 28 19 28 19 28 19 - - - - - - - - - - - - - - - - 3 22 15 22 15 22 15 22 15 22 15 - - - - - - - - - - - - - - 2.5 - - 13 9 13 9 13 9 13 9 13 9 - - - - - - - - - - - - 2 - - - - 0 0 0 0 0 0 0 0 0 0 - - - - - - - - - - Slew 1.5 rate 4.0 V/ns - - - - - - -22 -15 -22 -15 -22 -15 -22 -15 -14 -7 - - - - - - - - 1 - - - - - - - - -65 -45 -65 -45 -65 -45 -57 -37 -49 -29 - - - - - - - - 0.9 - - - - - - - - - - -62 -48 -62 -48 -54 -40 -46 -32 -38 -24 - - V/ns 0.8 - - - - - - - - - - - - -61 -53 -53 -45 -45 -37 -37 -29 -29 -19 - - 0.7 - - - - - - - - - - - - - - -49 -50 -41 -42 -33 -34 -25 -24 -17 -8 0.6 - - - - - - - - - - - - - - - - -37 -49 -29 -41 -21 -31 -13 -15 0.5 - - - - - - - - - - - - - - - - - - -31 -51 -23 -41 -15 -25 0.4 - - - - - - - - - - - - - - - - - - - - -28 -56 -20 -40 NOTE1: Cell contents shaded in gray are defined as ‘not supported’. Version 1.9 02/2017 156 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Derating values DDR3- 800/1066 tDS/tDH - AC/DC based AC175 Threshold DDR3 AC175 Threshold DQS,  Differential Slew Rate 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH DQ 2 88 50 88 50 88 50 - - - - - - - - - 1.5 59 34 59 34 59 34 67 42 - - - - - - - - 1 0 0 0 0 0 0 8 8 16 16 - - - - - - 0.9 - - -2 -4 -2 -4 6 4 14 12 22 20 - - - - Slew rate 0.8 - - - - -6 -10 2 -2 10 6 18 14 26 24 - - V/ns 0.7 - - - - - - -3 -8 5 0 13 8 21 18 29 34 0.6 - - - - - - - - -1 -10 7 -2 15 8 23 24 0.5 - - - - - - - - - - -11 -16 -2 -6 5 10 0.4 - - - - - - - - - - - - -30 -26 -22 -10 NOTE1: Cell contents shaded in gray are defined as ‘not supported’. Derating values DDR3- 800/1066/1333/1600 tDS/tDH - AC/DC based AC150 Threshold DDR3 AC150 Threshold DQS,  Differential Slew Rate 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH DQ 2 75 50 75 50 75 50 - - - - - - - - - 1.5 50 34 50 34 50 34 58 42 - - - - - - - - 1 0 0 0 0 0 0 8 8 16 16 - - - - - - 0.9 - - 0 -4 0 -4 8 4 16 12 24 20 - - - - Slew rate 0.8 - - - - 0 -10 8 -2 16 6 24 14 32 24 - - V/ns 0.7 - - - - - - 8 -8 16 0 24 8 32 18 40 34 0.6 - - - - - - - - 15 -10 23 -2 31 8 39 24 0.5 - - - - - - - - - - 14 -16 22 -6 30 10 0.4 - - - - - - - - - - - - 7 -26 15 -10 NOTE1: Cell contents shaded in gray are defined as ‘not supported’. Version 1.9 02/2017 157 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Derating values DDR3- 1866/2133 tDS/tDH - AC/DC based AC135 Threshold DDR3 Alternate AC135 Threshold -> VIH(ac)=VREF(dc)+135mV, VIL(ac)=VREF(dc)-135mV Alternate DC100 Threshold -> VIH(dc)=VREF(dc)+100mV, VIL(dc)=VREF(dc)-100mV DQS,  Differential Slew Rate 8.0 V/ns 7.0 V/ns 6.0 V/ns 5.0 V/ns 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH 4 34 25 34 25 34 25 - - - - - - - - - - - - - - - - - - 3.5 29 21 29 21 29 21 29 21 - - - - - - - - - - - - - - - - 3 23 17 23 17 23 17 23 17 23 17 - - - - - - - - - - - - - - 2.5 - - 14 10 14 10 14 10 14 10 14 10 - - - - - - - - - - - - DQ 2 - - - - 0 0 0 0 0 0 0 0 0 0 - - - - - - - - - - Slew 1.5 - - - - - - -23 -17 -23 -17 -23 -17 -23 -17 -15 -9 - - - - - - - - 1 - - - - - - - - -68 -50 -68 -50 -68 -50 -60 -42 -52 -34 - - - - - - 0.9 - - - - - - - - - - -66 -54 -66 -54 -58 -46 -50 -38 -42 -30 - - - - 0.8 - - - - - - - - - - - - -64 -60 -56 -52 -48 -44 -40 -36 -32 -26 - - 0.7 - - - - - - - - - - - - - - -53 -59 -45 -51 -37 -43 -29 -33 -21 -17 0.6 - - - - - - - - - - - - - - - - -43 -61 -35 -53 -27 -43 -19 -27 0.5 - - - - - - - - - - - - - - - - - - -39 -66 -31 -56 -23 -40 0.4 - - - - - - - - - - - - - - - - - - - - -38 -76 -30 -60 rate V/ns NOTE1: Cell contents shaded in gray are defined as ‘not supported’. Derating values DDR3- 800/1066/1333/1600 tDS/tDH - AC/DC based AC135 Threshold DDR3 Alternate AC135 Threshold -> VIH(ac)=VREF(dc)+135mV, VIL(ac)=VREF(dc)-135mV Alternate DC100 Threshold -> VIH(dc)=VREF(dc)+100mV, VIL(dc)=VREF(dc)-100mV DQS,  Differential Slew Rate 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH 2 68 50 68 50 68 50 - - - - - - - - - - 1.5 45 34 45 34 45 34 53 42 - - - - - - - - 1 0 0 0 0 0 0 8 8 16 16 - - - - - - 0.9 - - 2 -4 2 -4 10 4 18 12 26 20 - - - - Slew rate 0.8 - - - - 3 -10 11 -2 19 6 27 14 35 24 - - V/ns 0.7 - - - - - - 14 -8 22 0 30 8 38 18 46 34 0.6 - - - - - - - - 25 -10 33 -2 41 8 49 24 0.5 - - - - - - - - - - 29 -16 37 -6 45 10 0.4 - - - - - - - - - - - - 30 -26 38 -10 DQ NOTE1: Cell contents shaded in gray are defined as ‘not supported’. Version 1.9 02/2017 158 Nanya Technology Cooperation © All Rights Reserved. DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP Required time tVAC above VIH(AC) {below VIL(AC)} for DQ transition DDR3 Slew 800/1066/ 800/1066/ 1333/1600 1333/1600 175mV [ps] 150mV[ps] > 2.0 75 2.0 Rate 800/1066 DDR3L 1066/1333 2133 1066 135mV [ps] 135mV [ps] 135 mV [ps] 160 mV [ps] 135 mV [ps] 130 mV [ps] 105 113 93 73 165 113 95 ps 57 105 113 93 73 165 113 95 ps 1.5 50 80 90 70 50 138 90 73 ps 1.0 38 30 45 25 5 85 45 30 ps 0.9 34 13 30 Note Note 67 30 16 ps 0.8 29 Note 11 Note Note 45 11 Note ps 0.7 Note Note Note - - 16 Note - ps 0.6 Note Note Note - - Note Note - ps 0.5 Note Note Note - - Note Note - ps