A000078

ATmega16U4/ATmega32U4 8-bit Microcontroller with 16/32K bytes of ISP Flash and USB Controller DATASHEET Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture • • • • – 135 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16MHz – On-Chip 2-cycle Multiplier Non-volatile Program and Data Memories – 16/32KB of In-System Self-Programmable Flash – 1.25/2.5KB Internal SRAM – 512Bytes/1KB Internal EEPROM – Write/Erase Cycles: 10,000 Flash/100,000 EEPROM – Data retention: 20 years at 85C/ 100 years at 25C(1) – Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation Parts using external XTAL clock are pre-programed with a default USB bootloader – Programming Lock for Software Security JTAG (IEEE® std. 1149.1 compliant) Interface – Boundary-scan Capabilities According to the JTAG Standard – Extensive On-chip Debug Support – Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface USB 2.0 Full-speed/Low Speed Device Module with Interrupt on Transfer Completion – Complies fully with Universal Serial Bus Specification Rev 2.0 – Supports data transfer rates up to 12Mbit/s and 1.5Mbit/s – Endpoint 0 for Control Transfers: up to 64-bytes – Six Programmable Endpoints with IN or Out Directions and with Bulk, Interrupt or Isochronous Transfers – Configurable Endpoints size up to 256 bytes in double bank mode – Fully independent 832 bytes USB DPRAM for endpoint memory allocation – Suspend/Resume Interrupts – CPU Reset possible on USB Bus Reset detection – 48MHz from PLL for Full-speed Bus Operation – USB Bus Connection/Disconnection on Microcontroller Request – Crystal-less operation for Low Speed mode Peripheral Features – On-chip PLL for USB and High Speed Timer: 32 up to 96MHz operation – One 8-bit Timer/Counter with Separate Prescaler and Compare Mode Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016 • • • • • – Two 16-bit Timer/Counter with Separate Prescaler, Compare- and Capture Mode – One 10-bit High-Speed Timer/Counter with PLL (64MHz) and Compare Mode – Four 8-bit PWM Channels – Four PWM Channels with Programmable Resolution from 2 to 16 Bits – Six PWM Channels for High Speed Operation, with Programmable Resolution from 2 to 11 Bits – Output Compare Modulator – 12-channels, 10-bit ADC (features Differential Channels with Programmable Gain) – Programmable Serial USART with Hardware Flow Control – Master/Slave SPI Serial Interface – Byte Oriented 2-wire Serial Interface – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wake-up on Pin Change – On-chip Temperature Sensor Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal 8MHz Calibrated Oscillator – Internal clock prescaler and On-the-fly Clock Switching (Int RC / Ext Osc) – External and Internal Interrupt Sources – Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby I/O and Packages – All I/O combine CMOS outputs and LVTTL inputs – 26 Programmable I/O Lines – 44-lead TQFP Package, 10x10mm – 44-lead QFN Package, 7x7mm Operating Voltages – 2.7 - 5.5V Operating temperature – Industrial (-40°C to +85°C) Maximum Frequency – 8MHz at 2.7V - Industrial range – 16MHz at 4.5V - Industrial range Note: 1. See “Data Retention” on page 8 for details. 2 ATmega16U4/32U4 [DATASHEET] Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016 Pin Configurations (INT.6/AIN0) PE6 UVcc GND AREF PF0 (ADC0) PF1 (ADC1) PF4 (ADC4/TCK) PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF7 (ADC7/TDI) GND VCC 43 42 41 40 39 38 37 36 35 34 Pinout AVCC Figure 1-1. 44 1. 33 PE2 (HWB) 1 ) 32 PC7 (ICP3/CLK0/OC4A 2 INDEX C ORNER D- 3 ( ) 31 PC6 OC3A/OC4A D+ 4 30 PB6 (PCINT6/OC1B/OC4B/ADC UGnd 5 29 UCap 6 VBus 7 20 21 (RXD1/INT2) PD2 (TXD1/INT3) PD3 (XCK1/CTS) PD5 22 19 (SDA/INT1) PD1 (OC0B/SCL/INT0) PD0 (PCINT7/OC0A/OC1C/RTS) PB7 2. 18 GND 17 23 XTAL1 11 16 AVCC XTAL2 24 15 10 GND 25 PD4 (ICP1/ADC8) 14 9 12 (PDO/PCINT3/MISO ) PB3 26 PD6 (T1/OC4D/ADC9) VCC (PDI/PCINT2/MOSI) PB2 27 PD7 (T0/OC4D/ADC10) 8 13 (PCINT1/SCLK ) PB1 28 PB4 (PCINT4/ADC11) ATmega32U4 ATmega16U4 44-pin QFN/T QFP RESET (SS/PCINT0) PB0 PB5 (PCINT5/OC1A/OC4B/ADC Overview The ATmega16U4/ATmega32U4 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the device achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. ATmega16U4/32U4 [DATASHEET ] Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016 3 Block Diagram PF7 - PF4 VCC PC7 PC6 PF1 PF0 PORTF DRIVERS RESET Block Diagram XTAL2 Figure 2-1. XTAL1 2.1 PORTC DRIVERS GND DATA REGISTER PORTF DATA DIR. REG. PORTF DATA REGISTER PORTC DATA DIR. REG. PORTC 8-BIT DA TA BUS POR - BOD RESET JTAG TAP PROGRAM COUNTER STACK POINTER ON-CHIP DEBUG PROGRAM FLASH SRAM BOUNDARYSCAN INSTRUCTION REGISTER INTERNAL OSCILLATOR INSTRUCTION DECODER TEMPERATURE SENSOR CONTROL LINES TIMING AND CONTROL MCU CONTROL REGISTER TIMERS/ COUNTERS GENERAL PURPOSE REGISTERS INTERRUPT UNIT UVcc Y Z ON-CHIP USB PAD 3V REGULATOR EEPROM ALU PLL HIGH SPEED ADC TIMER/PWM STATUS REGISTER AREF UCap 1uF AVCC AGND OSCILLATOR WATCHDOG TIMER X PROGRAMMING LOGIC CALIB. OSC VBUS DP USB 2.0 ANALOG COMPARATOR DATA REGISTER PORTE DATA DIR. REG. PORTE PORTE DRIVERS PE6 PE2 DATA REGISTER PORTB DATA DIR. REG. PORTB PORTB DRIVERS PB7 - PB0 DM TWO-WIRE SERIAL INTERFACE SPI USART1 DATA REGISTER PORTD DATA DIR. REG. PORTD PORTD DRIVERS PD7 - PD0 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The device provides the following features: 16/32K bytes of In-System Programmable Flash with Read-WhileWrite capabilities, 512Bytes/1K bytes EEPROM, 1.25/2.5K bytes SRAM, 26 general purpose I/O lines (CMOS outputs and LVTTL inputs), 32 general purpose working registers, four flexible Timer/Counters with compare modes and PWM, one more high-speed Timer/Counter with compare modes and PLL adjustable source, one USART (including CTS/RTS flow control signals), a byte oriented 2-wire Serial Interface, a 12-channels 10-bit ADC with optional differential input stage with programmable gain, an on-chip calibrated temperature sensor, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming and six software selectable 4 ATmega16U4/32U4 [DATASHEET] Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016 power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. The device is manufactured using the Atmel® high-density nonvolatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the device is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega16U4/ATmega32U4 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. 2.2 Pin Descriptions 2.2.1 VCC Digital supply voltage. 2.2.2 GND Ground. 2.2.3 Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tristated when a reset condition becomes active, even if the clock is not running. Port B has better driving capabilities than the other ports. Port B also serves the functions of various special features of the device as listed on page 74. 2.2.4 Port C (PC7,PC6) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tristated when a reset condition becomes active, even if the clock is not running. Only bits 6 and 7 are present on the product pinout. Port C also serves the functions of special features of the device as listed on page 77. 2.2.5 Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tristated when a reset condition becomes active, even if the clock is not running. ATmega16U4/32U4 [DATASHEET ] Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016 5 Port D also serves the functions of various special features of the ATmega16U4/ATmega32U4 as listed on page 78. 2.2.6 Port E (PE6,PE2) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tristated when a reset condition becomes active, even if the clock is not running. Only bits 2 and 6 are present on the product pinout. Port E also serves the functions of various special features of the ATmega16U4/ATmega32U4 as listed on page 81. 2.2.7 Port F (PF7..PF4, PF1,PF0) Port F serves as analog inputs to the A/D Converter. Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter channels are not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running. Bits 2 and 3 are not present on the product pinout. Port F also serves the functions of the JTAG interface. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs. 2.2.8 DUSB Full speed / Low Speed Negative Data Upstream Port. Should be connected to the USB D- connector pin with a serial 22 resistor. 2.2.9 D+ USB Full speed / Low Speed Positive Data Upstream Port. Should be connected to the USB D+ connector pin with a serial 22 resistor. 2.2.10 UGND USB Pads Ground. 2.2.11 UVCC USB Pads Internal Regulator Input supply voltage. 2.2.12 UCAP USB Pads Internal Regulator Output supply voltage. Should be connected to an external capacitor (1µF). 2.2.13 VBUS USB VBUS monitor input. 6 ATmega16U4/32U4 [DATASHEET] Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016 2.2.14 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 8-2 on page 53. Shorter pulses are not guaranteed to generate a reset. 2.2.15 XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. 2.2.16 XTAL2 Output from the inverting Oscillator amplifier. 2.2.17 AVCC AVCC is the supply voltage pin (input) for all the A/D Converter channels. If the ADC is not used, it should be externally connected to VCC. If the ADC is used, it should be connected to VCC through a low-pass filter. 2.2.18 AREF This is the analog reference pin (input) for the A/D Converter. ATmega16U4/32U4 [DATASHEET ] Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016 7 3. About 3.1 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min. and Max. values will be available after the device is characterized. 3.2 Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 3.3 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Confirm with the C compiler documentation for more details. These code examples assume that the part specific header file is included before compilation. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". 3.4 Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1PPM over 20 years at 85°C or 100 years at 25°C. 8 ATmega16U4/32U4 [DATASHEET] Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016 4. AVR CPU Core 4.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Architectural Overview Figure 4-1. Block Diagram of the AVR Architecture Data Bus 8-bit Flash Program Memory Program Counter Status and Control 32 x 8 General Purpose Registrers Instruction Decoder Control Lines Indirect Addressing Instruction Register Direct Addressing 4.2 Interrupt Unit SPI Unit Watchdog Timer ALU Analog Comparator I/O Module1 Data SRAM I/O Module 2 I/O Module n EEPROM I/O Lines In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two ATmega16U4/32U4 [DATASHEET] Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016 9 operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Zregister, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot Program section. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega16U4/ATmega32U4 has Extended I/O space from 0x60 0x0FF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. 4.3 ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See “Instruction Set Summary” on page 418 for a detailed description. 4.4 Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. ATmega16U4/32U4 [DATASHEET] Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016 10 The AVR Status Register – SREG – is defined as: Bit Read/Write Initial Value 7 I R/W 0 6 T R/W 0 5 H R/W 0 4 S R/W 0 3 V R/W 0 2 N R/W 0 1 Z R/W 0 0 C R/W 0 SREG • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference. • Bit 6 – T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. • Bit 5 – H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD arithmetic. See “Instruction Set Summary” on page 418 for detailed information. • Bit 4 – S: Sign Bit, S = N V The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See “Instruction Set Summary” on page 418 for detailed information. • Bit 3 – V: Two’s Complement Overflow Flag The Two’s Complement Overflow Flag V supports two’s arithmetic complements. See “Instruction Set Summary” on page 418 for detailed information. • Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See “Instruction Set Summary” on page 418 for detailed information. • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See “Instruction Set Summary” on page 418 for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See “Instruction Set Summary” on page 418 for detailed information. 4.5 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File:  One 8-bit output operand and one 8-bit result input  Two 8-bit output operands and one 8-bit result input ATmega16U4/32U4 [DATASHEET] Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016 11  Two 8-bit output operands and one 16-bit result input  One 16-bit output operand and one 16-bit result input Figure 4-2 shows the structure of the 32 general purpose working registers in the CPU. Figure 4-2. AVR CPU General Purpose Working Registers 7 General Purpose Working Registers R0 R1 R2 … R13 R14 R15 R16 R17 … R26 R27 R28 R29 R30 R31 0 Addr. 0x00 0x01 0x02 0x0D 0x0E 0x0F 0x10 0x11 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F X-register Low Byte X-register High Byte Y-register Low Byte Y-register High Byte Z-register Low Byte Z-register High Byte Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 4-2, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-pointer registers can be set to index any register in the file. 4.5.1 The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 4-3. ATmega16U4/32U4 [DATASHEET] Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016 12 Figure 4-3. The X-, Y-, and Z-registers 15 7 R27 (0x1B) XH X-register 15 7 R29 (0x1D) YH Y-register Z-register 15 7 R31 (0x1F) ZH 0 0 7 R26 (0x1A) 0 7 R28 (0x1C) XL 0 0 YL 0 0 ZL 7 R30 (0x1E) 0 0 In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (See “Instruction Set Summary” on page 418 for detailed information). 4.6 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x0100. The initial value of the stack pointer is the last address of the internal SRAM. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by three when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by three when data is popped from the Stack with return from subroutine RET or return from interrupt RETI. The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. Bit Read/Write Initial Value 15 SP15 SP7 7 R/W R/W 0 1 14 SP14 SP6 6 R/W R/W 0 1 13 SP13 SP5 5 R/W R/W 1 1 12 SP12 SP4 4 R/W R/W 0 1 11 SP11 SP3 3 R/W R/W 0 1 10 SP10 SP2 2 R/W R/W 0 1 9 SP9 SP1 1 R/W R/W 0 1 8 SP8 SP0 0 R/W R/W 0 1 SPH SPL ATmega16U4/32U4 [DATASHEET] Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016 13 4.6.1 Extended Z-pointer Register for ELPM/SPM - RAMPZ Bit Read/Write Initial Value 7 RAMPZ7 R/W 0 6 RAMPZ6 R/W 0 5 RAMPZ5 R/W 0 4 RAMPZ4 R/W 0 3 RAMPZ3 R/W 0 2 RAMPZ2 R/W 0 1 RAMPZ1 R/W 0 0 RAMPZ0 R/W 0 RAMPZ For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown in Figure 4-4. Note that LPM is not affected by the RAMPZ setting. Figure 4-4. Bit (Individually) Bit (Z-pointer) The Z-pointer used by ELPM and SPM 7 RAMPZ 23 0 16 7 ZH 15 0 7 ZL 7 8 0 0 The actual number of bits is implementation dependent. Unused bits in an implementation will always read as zero. For compatibility with future devices, be sure to write these bits to zero. 4.7 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 4-5 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 4-5. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 4-6 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. ATmega16U4/32U4 [DATASHEET] Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016 14 Figure 4-6. Single Cycle ALU Operation T1 T2 T3 T4 clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back 4.8 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section “Memory Programming” on page 353 for details. The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 63. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 63 for more information. The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see “Memory Programming” on page 353. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. ATmega16U4/32U4 [DATASHEET] Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016 15 When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. Assembly Code Example in r16, SREG ; store SREG value cli ; disable interrupts during timed sequence sbi EECR, EEMPE ; start EEPROM write sbi EECR, EEPE out SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG; store SREG value */ /* disable interrupts during timed sequence */ __disable_interrupt(); EECR |= (1