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5CSX-H6-42A-RC

5CSX-H6-42A-RC

  • 厂商:

    CRITICALLINK

  • 封装:

    -

  • 描述:

    5CSX-H6-42A-RC

  • 数据手册
  • 价格&库存
5CSX-H6-42A-RC 数据手册
Critical Link, LLC www.CriticalLink.com MitySOM MitySOM-5CSx System on Module 25 April 2019 FEATURES  Intel Cyclone V - U672 SoC - Up To Dual ARM Cortex- A9 MPU - 925MHz Max clock speed - Dual NEON SIMD Coprocessors - 32 KB L1 Program Cache (per core) - 32 KB L1 Data Cache (per core) - 512 KB L2 Cache (shared) - 64 KB on-chip RAM - ECC Support - Up To 133 User FPGA I/O Pins - 44 CPU I/O Pins - 6 High speed transceivers (SX only)  Cyclone V Processor Choices - Cyclone V SX (3.125 Gbps transceivers) - Cyclone V SE  Memory - Up To 2GB DDR3 CPU RAM x32 bits + ECC - Up To 512MB DDR3 FPGA RAM x8 bits (optional) - Up To 272MB QPSI NOR FLASH   Integrated Power Management JTAG connector on-module  FPGA Fabric - Up To 110K Logic Elements (LE) - 460Mhz Global Clock - Up To 5.1Mb M10K Memory - Up To 621Kb MLAB Memory - Up To 112 DSP Blocks - Up To 6 FPGA PLLs - Fractional PLL Outputs on each PLL  Low Power Serial Transceivers (SX only) - 3.125Gbps Transceivers - PCIe Hard IP Block (Gen1.1 x1 or x4)  Power, Reset and Clock Management  Mechanical - 314-Pin Card Edge Connector - Small 82mm (3.2”) x 39mm (1.5”) size  Hard Processor System (HPS) - Selection of boot sources - Up to 2 10/100/1000 Mbps Ethernet MACs - Up to 2 USB 2.0 OTG Ports - Up to 2 CAN Interfaces - Up to 2 UARTs - 1 MMC/SD/SDIO - Up to 4 I2C controllers - Up to 2 master/2 slave SPI - 3 HPS PLLs APPLICATIONS  Machine Vision  Test and Measurement  Embedded Instrumentation  Industrial Automation and Control  Industrial Instrumentation  Medical Instrumentation  Closed Loop Motor Control BENEFITS  Rapid Development / Deployment  Multiple Connectivity and I/O Options  Rich User Interfaces  High System Integration  High Level OS Support - Embedded Linux - Micrium uC/OS (via 3rd Party) - Android (via 3rd Party) - QNX (via 3rd Party) DESCRIPTION The MitySOM-5CSx series of highly configurable, small form-factor System-on-Modules (SoM) feature an Intel Cyclone V System-on-Chip (SoC). Additionally, the module includes on-board power supplies, NOR FLASH and DDR3 RAM memory subsystems. A MitySOM-5CSx provides a complete and flexible CPU infrastructure for highly integrated embedded systems. 1 Copyright © 2015, Critical Link LLC Specifications Subject to Change 60-000035-1A Critical Link, LLC www.CriticalLink.com MitySOM MitySOM-5CSx System on Module 25 April 2019 The MitySOM-5CSX is available with either a Cyclone V SX or Cyclone V SE which provide up-to Dual-core Cortex-A9 32-bit RISC processors with dual NEON SIMD coprocessors. This MPU is capable of running a rich set of real-time operating systems containing software applications programming interfaces (APIs) expected by modern system designers. The ARM architecture supports several operating systems, including Linux, Micrium uC/OS, Android and QNX. MitySOM 5CSx System On Module Block Diagram Up To 512 MB DDR3 RAM x8 Up To 512 MB DDR3 RAM x8 Up To 512 MB DDR3 RAM X8 (ECC) Up To 512 MB DDR3 RAM x8 Up To 512 MB DDR3 RAM x8 Temperature (LM73) RGB LED (LP5562) 16Kb EEPROM RTC (AB1803) I2C0 HPS DDR3 Interface (Maximum 32 bits wide + 8 bits ECC) QUAD SPI QUAD SPI Boot FLASH NOR FLASH 16 MB NOR Up-to 256 MB Intel Cyclone V SX w/ 6x 3.125Gbps Xcvrs or Cyclone V SE w/o Xcvrs JTAG Connector (HPS & FPGA) Up-to 133 User FPGA I/O or 107 User FPGA I/O with FPGA DDR 44 User HPS I/O Up-to DUAL ARM Cortex A9 925 MHz FPGA Fabric + High Speed Interconnect Bank3A/5A FPGA I/O (Expanded IO No FPGA DDR) 1 USB1 6 Bank5A FPGA I/O 32 Bank8A FPGA I/O 68 Bank3B FPGA I/O 8 Bank4A FPGA I/O 3 FPGA CONFIG 5 HPS CLK/RESET 14 MSEL 12 CAN/I2C/SPI 16 SDMMC/USB0 2 RGMII1 / NAND / GPIOs Cyclone V SX only 6 TX, 6 RX, 2 RefClk, 3.125Gbps HPS GPI ID +V_B3B +V_B8A +3VBAT +V_B4A +5VIN +1.8V +VIO_EN_2.5V 28 UART0 TX/RX 26 10 Up-to 512 MB DDR3 RAM X8 (optional) USB OTG PHY OTG USB 1 Power Supply Generation And Sequencing 5 314-pin Edge Connector Figure 1 MitySOM-5CSx Block Diagram Figure 1 provides a top-level block diagram of the MitySOM-5CSx processor card. As shown in the figure, the primary interface to the MitySOM-5CSx is through a 314-Pin card edge interface. Details of the edge connector interface are included in the Card Edge Interface Description section. 2 Copyright © 2015, Critical Link LLC Specifications Subject to Change 60-000035-1A Critical Link, LLC www.CriticalLink.com MitySOM MitySOM-5CSx System on Module 25 April 2019 MitySOM-5CSx Onboard Storage DDR3 Memory – HPS Memory The MitySOM-5CSx includes one dedicated 40-bit DDR3 memory interface. The memory interface can be up-to 40-bits wide including 8-bits for ECC. A maximum of 2GB of DDR3 RAM with ECC is supported by the MitySOM-5CSx module. The standard MitySOM-5CSx includes 1GB of DDR3 RAM with ECC (40-bits wide) integrated on the module. The lowest KLE variant of the MitySOM-5CSE includes 512MB of DDR3 RAM without ECC (16-bits wide) integrated on the. This HPS DDR3 memory is available for both the HPS (Cortex-A9 ARM core(s)) as well as the FPGA fabric through either the AXI or Avalon high speed interfaces internal to the Cyclone V. The MitySOM-5CSx family adheres to Intel’s Cyclone V maximum memory speeds. At this time the HPS memory clocked at 400Mhz as the maximum and a slower speed may be selected, if desired, down to 300MHz. This may change if Intel makes changes to their Silicon/recommendations. See Table 10: Standard Model Numbers for additional details. DDR3 Memory – FPGA Memory (Optional) The MitySOM-5CSx modules can also include up to 512MB of DDR3 connected directly to the Cyclone V FPGA fabric through a 8-bit bus. This memory is exclusively for the use of the FPGA fabric for buffering and local storage and is available through a high speed, low latency direct connect. A total of 26 additional FPGA I/O is available through the card edge connector in models that do not feature the FPGA DDR3 memory. See Table 10: Standard Model Numbers for additional details. HPS-FPGA AXI The high bandwidth HPS-FPGA AXI bridges provided by Intel in the Cyclone V SoC allow masters in the FPGA fabric to communicate with slaves in the HPS logic and vice versa. These bridges can be configured for 32, 64, or 128 bit widths. For example, designers can instantiate additional memories or peripherals in the FPGA fabric, and master interfaces belonging to components in the HPS logic can access them. Designers can also instantiate components such as a Nios® II processor in the FPGA fabric and their master interfaces can access memories or peripherals in the HPS logic, including DDR3 Memory – HPS Memory. 3 Copyright © 2015, Critical Link LLC Specifications Subject to Change 60-000035-1A Critical Link, LLC www.CriticalLink.com MitySOM MitySOM-5CSx System on Module 25 April 2019 NOR FLASH A maximum of 272MB (1 x 16MB and 1 x 256MB) of on-board NOR FLASH memory is connected to the Cyclone V using a Quad Serial Peripheral Interface (QSPI SS0 and SS1). This is a reliable flash memory that can be used as a boot media for the module as well as configuration information if needed for custom applications. Configuration EEPROM MitySOM-5CSx modules contain a 2048 x 8-bit EEPROM that is used to hold configuration data for the module. The EEPROM is connected to the Cyclone V using the I2C0 interface. This EEPROM contains information such as the module type, Serial Number, MAC addresses for the Ethernet interface(s) and additional information as required by Critical Link. Note that this memory shall not be used except for Critical Link factory configuration information and its contents may change as required by Critical Link. 4 Copyright © 2015, Critical Link LLC Specifications Subject to Change 60-000035-1A Critical Link, LLC www.CriticalLink.com MitySOM MitySOM-5CSx System on Module 25 April 2019 On-board Interfaces The following on-board interfaces were chosen to provide the most flexibility for end user applications. As many HPS MUX options as possible were left available for the user. These interfaces should not be muxed external to the module on other pins. Console Serial port The console serial port (UART0) is supported on pins 2 (RX) and 4 (TX) of the 314-Pin Card Edge Connector with a simple TX/RX interface. By default, the flow control signals are not enabled but can be added to the console serial interface if desired. Please reference the Card Edge Pin-Out for specific Cyclone V pin-connections. I2C0 Interface The I2C0 peripheral is consumed local to the module. It is used for the Real Time Clock, Temperature Sensor, Configuration EEPROM, and to control a PWM LED driver for status and debug. Table 1: I2C0 Peripherals Address 1000010 Device AS3668 1010XXX FT24C16A 1101001 1001100 AB1805-T3 LM73CIMK-1 Feature LED Driver for RGB Status LED (D1) and a Green LED (D5) 16Kbit EEPROM for Critical Link factory configuration parameters Real Time Clock Temperature sensor For application information about each of these I2C devices, including drivers and example code, please visit our support site at https://support.criticallink.com/. QuadSPI Interface The QUADSPI peripheral is wired to Bank 7B and is used for the NOR FLASH interface on the module. Both Slave select 0 and slave select 1 have been utilized for this NOR memory. Table 2: QSPI Slave Selects Slave Select 0 1 Feature Boot flash Additional flash Memory Sizing 128Mb –x4 width - 16MB max 128Mb –x4 width (not populated on 16MB NOR modules) – 256MB max 5 Copyright © 2015, Critical Link LLC Specifications Subject to Change 60-000035-1A Critical Link, LLC www.CriticalLink.com MitySOM MitySOM-5CSx System on Module 25 April 2019 USB-2.0 OTG Phy The USB1 interface of the Cyclone V processor is connected directly to a USB 2.0 OTG phy on the module itself. The necessary USB ID, power and data pins are available at the edge connector of the module. Please see Table 8 for the specific pin locations. Debug Interface The JTAG interface signals for the Cyclone V processor have been brought out to a 31 pin Hirose connector (DF9-31P-1V(32)), J2, which is intended for use with available Critical Link breakout adapters. For JTAG interfacing please utilize the Critical Link JTAG Debug Adapter, part number 80-000616. The interface on the module allows for both HPS (ARM processor(s)) and FPGA debug. Below is the pin-out of the J2 connector on the MitySOM-5CSx module. Debug Interface Connector Description (J2) Table 3 J2 Hirose Connector Pin I/O Signal Pin I/O Signal 1 GND 2 I/O HPS_RST_N 3 I MICTOR_TRACE_PRSNT* 4 I HPS_GPI10_SYSCON 5 GND 6 I JTAG_HPS_TCK 7 GND 8 NC 9 I/O MICTOR_TRACE_D0* 10 O JTAG_HPS_TDO 11 I/O MICTOR_TRACE_D1* 12 VCC (3.3V) 13 I/O MICTOR_TRACE_D2* 14 I JTAG_HPS_TDI 15 I/O MICTOR_TRACE_D3* 16 I JTAG_HPS_TRST 17 I/O MICTOR_TRACE_D4* 18 I JTAG_HPS_TMS 19 I/O MICTOR_TRACE_D5* 20 GND 21 I/O MICTOR_TRACE_D6* 22 +VPD_3A5A5B 23 I/O MICTOR_TRACE_D7* 24 I JTAG_FPGA_TMS 25 GND 26 I JTAG_FPGA_TCK 27 GND 28 O JTAG_FPGA_TDO 29 I/O MICTOR_TRACE_CLK* 30 I JTAG_FPGA_TDI 31 GND *For TRACE support please contact your Critical Link representative for further information A debug breakout adapter is not included with individual modules but the JTAG adapter is included with each Critical Link MitySOM-5CSx Development Kit that is ordered. If an adapter is needed please contact your Critical Link representative. The JTAG debug adapter from Critical Link is compatible with the Intel FPGA Download Cable and Download Cable II Intel Download Cables[3]. Note that this header, J2, can be removed for production units; please contact your Critical Link representative for details. 6 Copyright © 2015, Critical Link LLC Specifications Subject to Change 60-000035-1A Critical Link, LLC www.CriticalLink.com MitySOM MitySOM-5CSx System on Module 25 April 2019 External Interfaces The Cyclone V makes extensive use of functional pin multiplexing to provide a highly configurable device that can be tailored to a multitude of applications. HPS Interfaces A list of the interfaces/functions that are available to the user from the HPS is provided below.          Up to 2 Universal Serial Bus (USB) 2.0 High-Speed On-The-Go (OTG) port o USB1 features an on SoM TI TUSB1211 USB Phy o USB0 ULPI interface pins available at edge connector, no Phy on SoM 2 Controller-Area Network (CAN) ports Up to 2 Gigabit Ethernet MAC’s (10/100/1000 Mbps) o EMAC1 through HPS or FPGA fabric o EMAC0 through FPGA fabric 1 MMC/SD/SDIO ports 4 Serial Peripheral (SPI) ports o 2 Master o 2 Slave 2 Universal Asynchronous Receive/Transmit (UART) ports 4 Inter-Integrated Circuit (I2C) ports o I2C0 is connected to the on-board EEPROM, Temperature Sensor, RTC and LED Driver JTAG/Debugger port RTC Battery Input (+3VBAT) Additionally, most of the pin multiplexed signals can be configured as general purpose I/O signals with interrupt capability. FPGA Interfaces GPIO Up to 133 FPGA Input/Output pins are available externally to a module that does not contain FPGA memory and 107 FPGA Input/Output pins are available externally for modules that feature the FPGA memory. 3.125 Gbps Transceivers (Cyclone V SX based modules only) A total of six (6) 3.125Gbps transceivers are available on the module for supporting high speed serial interfaces. This feature is only available on Cyclone V SX based modules. 7 Copyright © 2015, Critical Link LLC Specifications Subject to Change 60-000035-1A Critical Link, LLC www.CriticalLink.com MitySOM MitySOM-5CSx System on Module 25 April 2019 Configuration and Boot Modes The Cyclone V has two groups of pins, documented below, that are read during reset to determine which media to boot from for the HPS and one group of pins that is used to configure the FPGA. Please see Table 8 for the specific pin locations. HPS Configuration pins The BSEL and CSEL pins determine which memory interface has the bootloader and how to clock the interface. For booting the HPS, the BSEL and CSEL pins details are covered in CV-5400A[1].. BSEL[0:2] (HPS Boot Select at Reset) The MitySOM-5CSx module can boot from a number of devices and identified in Table 4 below. Pull-ups and pull-downs must be included in the base-board design to select the correct boot option; please consult the MitySOM-5CSx Carrier Board Design Guide for details. Table 4 lists the BSEL values that could be used on a MitySOM-5CSx design. The necessary BSEL configuration pins are all exposed to the edge connector for their HPS peripheral functions, Table 8. Table 4: BSEL Values BSEL Value 0x0 0x1 0x2 0x5 0x6 Boot device Reserved FPGA (HPS-to-FPGA bridge) 1.8V NAND flash memory 3.0V SD/MMC flash memory with external transceiver 1.8V SPI or Quad SPI flash memory (16MB bootable QSPI NOR) CSEL[0:1] (HPS Clock Select at Reset) The HPS signals that include the two CLKSEL boot configuration options are exposed on the module's edge connector pins. The default setting recommended by Critical Link is b’00’. These need to be pulled to the desired clock select option for your design. The default is to use the MitySOM-5CSx module's included 25MHz clock source into the osc1_clk pin. Please consult the MitySOM-5CSx Carrier Board Design Guide for details. The CSEL settings allow some of the HPS peripherals to run from a different clock source than the main HPS reference. Refer to CV-5400A[1] for the CSEL setting details. 8 Copyright © 2015, Critical Link LLC Specifications Subject to Change 60-000035-1A Critical Link, LLC www.CriticalLink.com MitySOM MitySOM-5CSx System on Module 25 April 2019 FPGA Configuration Pins The FPGA MSEL configuration input pins are dedicated inputs that should be connected directly to either power or ground. These define where the FPGA configuration boot stream will come from and the master that will clock the interface. Please see Cyclone V Device Handbook CV-52007[2] for details on what value to use for the MSEL connections and the MitySOM-5CSx Carrier Board Design Guide for further recommendations. MSEL[0:4] (FPGA Configuration Mode Select at Power-On-Reset) The MSEL should be set to FPPx16 if the design is going to use the FPGA Manager. With MSEL set to FPP, the HPS will be able to load the FPGA using the FPGA manager. This works in both FPPx16 and FPPx32 modes, but partial reconfiguration only works if set to FPPx16. The MSEL may be internally adjusted in the future using the HPS when it is configured first, the initial devices are not able to exercise this functionality. The default MSEL values recommended are b’00000’. For modules that include the optional DDR memory connected to the FPGA fabric I/Os the FPP configuration modes are not supported because the Bank 3A pins are consumed by the DDR interface. If the FPGA needs to be loaded first, the serial configuration modes are available, but the HPS will not be able to use the FPGA Manager to reconfigure the logic. When configuring the FPGA through the HPS, MSEL can be:  FPPx16 or FPPx32 (required for FPGA Manager to function properly)  FPPx16 mode required to support partial reconfiguration  Set MSEL to boot peripheral image. Can be from a prom or from the HPS preloader.  Using the internal HPS FPGA Manager Supported MSEL Options  FPP – Fast Passive Parallel (Modules without FPGA DDR only) FPP configuration is expected to work on the future module without FPGA DDR and FPPx16 is the default mode to use for booting from HPS.  PS – Passive Serial 1bit @ 125MHz Max – 10000 and 10001  AS – Active Serial 1bit or 4bit @ 100MHz Max – 10010 and 10011  CVP – Config via Protocol (over the PCI Express bus) This mode is supported for production Cyclone V silicon, but not for the modules shipped with early silicon. These early silicon modules are identified with a -X indicator at the end of their Critical Link model number, Table 10. 9 Copyright © 2015, Critical Link LLC Specifications Subject to Change 60-000035-1A Critical Link, LLC www.CriticalLink.com MitySOM MitySOM-5CSx System on Module 25 April 2019 Because the MSEL connections are dedicated inputs that should be tied directly to a power supply or ground, they are arranged on the edge connector to help isolate clock signals from crosstalk. They are also used for return current paths to improve signal integrity. To get this benefit, there are 1000pF capacitors on each of these signals on the module. The baseboard design must also include these caps to get the additional return current path benefits if they are not directly connected to ground. Debug LEDs There are 5 debug LEDs on the MitySOM-5CSx module. Three of them are on/off status LEDs tied to a specific condition and the other two are controlled by software through the LED controller on the I2C0 interface, Table 1. The LEDs have been identified in Figure 2. General Status LED’s Trace Debug D3 indicates that the JTAG/TRACE adapter board has been inserted into J2 of the module and was detected. Power OK D4 indicates the MitySOM-5CSx on-module +3.3V supply is operating. Configuration Debug D2 indicates that FPGA configuration is not complete by lighting a yellow LED. This is only a warning rather than an error because the HPS can still boot and load the FPGA. I2C Controllable LED’s Status Feedback The first LED, D1, is an RGB LED which is controlled when using the UBoot image provided by Critical Link. The second LED, D5, is a green LED that is also controlled by the LED controller on the I2C0 interface. 10 Copyright © 2015, Critical Link LLC Specifications Subject to Change 60-000035-1A Critical Link, LLC www.CriticalLink.com MitySOM MitySOM-5CSx System on Module 25 April 2019 Software and Application Development Support Users of the MitySOM-5CSx are encouraged to develop applications using the MitySOM-5CSx software development kit provided by Critical Link LLC. The SDK is an expansion of the Intel platform support package for the Cyclone V and includes an implementation of a Yocto Project-compatible board support package providing an Angstrom based Linux root filesystem/distribution and compatible gcc compiler toolchain with debugger. Additional embedded Linux support is available from TimeSys, Inc. Please visit https://support.criticallink.com/ to utilize our support resources. Growth Options The MitySOM-5CSx has been designed to support several upgrade options. These options include a range of speed grades, FPGA DDR memory, I/O, main DDR memory configurations, and operating temperature specifications including commercial and industrial temperature ranges. The available options are listed in the section below containing ordering information. For additional ordering information and details regarding these options, or to inquire about a particular configuration not listed below, please contact a Critical Link sales representative. Absolute Maximum Ratings If Military/Aerospace specified cards are required, please contact the Critical Link Sales Office or unit Distributors for availability and specifications. Table 5: Absolute Maximum Ratings Maximum Supply Voltage (+5VIN) Storage Temperature Range 5.2V -55oC to 150oC Operating Conditions The following are the minimum temperature ratings for the components that are installed on a MitySOM-5CSx. For specifications not contained in this table please contact a Critical Link sales representative. Please see the Thermal Management section below concerning ambient/operating temperature recommendations. Table 6: Module Component Temperature Ratings (minimum) Temperature Range Commercial (-RC) Industrial (-RI) Component Ratings 0oC to 70oC -40oC to 85oC 11 Copyright © 2015, Critical Link LLC Specifications Subject to Change 60-000035-1A Critical Link, LLC www.CriticalLink.com MitySOM MitySOM-5CSx System on Module 25 April 2019 Thermal Management The MitySOM-5CSx module requires careful consideration of thermal management. Depending on processor load, thermal management may be required for operation at room temperatures and above. The primary thermal concern is with the Cyclone V SoC device. Even when idle, case temperature on this device rises significantly. Additional processing activity will require more power consumption and more heat dissipation. Critical Link has operated the MitySOM-5CSx module without a heat sink or air flow on bench tops at room temperatures for long periods of time without issue. Thermal management is a system level issue that must be addressed in conjunction with the overall system design. Some systems may have available airflow with limited space for a heat sink; others may have room for a heat sink with or without the possibility for additional airflow. As a result, the approach taken for thermal management is a design consideration that must be addressed by the overall system designers when integrating the MitySOM-5CSx into an end product. Critical Link has developed a sample heat-spreader that is compatible with the MitySOM-5CSx. Please contact your Critical Link representative for further details. Every end product is different and it is advisable to perform thorough testing to ensure that the product will meet desired performance and longevity specifications. We recommend that customers utilize Intel’s Early Power Estimator (EPE) for the Cyclone V. This utility will assist in estimating the potential power usage of the processor for a given application. Details can be found on the PowerPlay EPE[4] page at Intel.com. In order to achieve reliable operation at the maximum specified operating temperatures it has been determined that heat dissipation will likely be required. Example Thermal Dissipation Scenarios By utilizing the PowerPlay EPE for the Cyclone V SoC Critical Link has provided some example scenarios detailing the effects of different cooling fin and airflows. Please be advised these are only estimations based on the Intel modeling tool that are only being used to illustrate the effect of different heat dissipation techniques and are not tested conditions by Critical Link. Table 7: Example EPE Based Scenarios Cyclone V Power 2.90W 4.25W 4.25W 4.25W 4.25W 4.25W Fin Size 23 mm 15 mm 15 mm 15 mm 23 mm 28 mm Airflow 200 LFM None 100 LFM 400 LFM 200 LFM 400 LFM 12 Max Ambient 71oC 49oC 55oC 65oC 65oC 67oC Copyright © 2015, Critical Link LLC Specifications Subject to Change 60-000035-1A Critical Link, LLC www.CriticalLink.com MitySOM MitySOM-5CSx System on Module 25 April 2019 Card-Edge Interface Description The primary interface connector for the MitySOM-5CSx is the 314-pin card edge interface which contains 7 classes of signals:         Power (PWR) o Input – Input power to the module o Output – Voltage supply from the module o Enable – Voltage enable signal from the module for sequencing on carrier boards Bank IO Power to the module (PWR_VIO) FPGA Bank Power (PWR_FPGA) Dedicated signals mapped to the Cyclone V SoC HPS / FPGA pins (5CSx_D) Multi-function signals mapped to the Cyclone V SoC HPS pins (5CSx_HPS) General purpose I/O pins mapped to the Cyclone V SoC FPGA pins (5CSx_IO) General purpose I/O pins available on expanded IO modules; no FPGA DDR memory present on the module (5CSx_EIO) Dedicated 3.125Gbps Transceiver signals mapped to the Cyclone V SoC (5CSX_GXB). Only available on Cyclone V SX based modules. Table 8 contains a summary of the MitySOM-5CSx pin-mapping. Card-Edge Mating Connector The MitySOM-5CSx module mates with a single connector that contains all of the power and I/O for the module. The mating socket is a 314-pin MXM 3.0 type connector. An example connector is a JAE - MM70-314-310B1-1-R300 which is available from distributors such as DigiKey and Mouser. More information is available in the MitySOM-5CSx Carrier Board Design guide from Critical Link. 13 Copyright © 2015, Critical Link LLC Specifications Subject to Change 60-000035-1A Critical Link, LLC www.CriticalLink.com MitySOM MitySOM-5CSx System on Module 25 April 2019 Table 8: MitySOM-5CSx Edge Connector Pin-Out Module Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Class PWR - Input 5CSx_HPS PWR - Input 5CSx_HPS PWR - Input 5CSx_HPS PWR - Input 5CSx_HPS PWR - Input 5CSx_HPS PWR 5CSx_HPS PWR 5CSx_HPS PWR 5CSx_HPS PWR PWR - Input 5CSx_D 5CSx_HPS 5CSx_D 5CSx_HPS 5CSx_D 5CSx_HPS 5CSx_D 5CSx_HPS 5CSx_D 5CSx_HPS 5CSx_D 5CSx_HPS 5CSx_D 5CSx_HPS 5CSx_D 5CSx_HPS 5CSx_D 5CSx_D 5CSx_D 5CSx_HPS 5CSx_D PWR 5CSx_D 5CSx_EIO 5CSx_D 5CSx_EIO 5CSx_D PWR-Enable SCH NET Name +5VIN UART0_RX +5VIN UART0_TX,CLKSEL0 +5VIN UART0_RTS/SPIM0_MOSI/I2C1_SCL/HPS_GPIO58 +5VIN UART0_CTS/SPIM0_CLK/I2C1_SDA/HPS_GPIO57 +5VIN CAN0_TX,CLKSEL1/HPS_GPIO62 GND CAN0_RX/SPIM0_SS1/HPS_GPIO61 GND CAN1_TX,BOOTSEL0/SPIM0_SS0/HPS_GPIO60 GND CAN1_RX/SPIM0_MISO/HPS_GPIO59 GND +3VBAT B7A_HPS_CLK2 TRACE_D7/SPIS1_MISO/HPS_GPIO56 nPERSTL1/B5A_RX_R6n TRACE_D6/SPIS1_SS0/HPS_GPIO55 HPS_nRST TRACE_D5/SPIS1_MOSI/CAN1_TX/HPS_GPIO54 HPS_nPOR TRACE_D4/SPIS1_CLK/CAN1_RX/HPS_GPIO53 B3B_FPGA_DCLK TRACE_D3/SPIS0_SS0/I2C1_SCL/HPS_GPIO52 MSEL0 TRACE_D2/SPIS0_MISO/I2C1_SDA/HPS_GPIO51 B3B_FPGA_D3 TRACE_D1/SPIS0_MOSI/HPS_GPIO50 B3B_FPGA_D2 TRACE_D0/SPIS0_CLK/HPS_GPIO49 B3B_FPGA_D1 MSEL4 B3B_FPGA_D0 TRACE_CLK/HPS_GPIO48 nCONFIG GND nSTATUS B5A_TX_R5_P/NC with FPGA DDR Memory nCSO B5A_TX_R5_N/NC with FPGA DDR Memory MSEL1 VIO_ENABLE_2V5 Bank Number 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 5A 7A 7A 7A 7A 7A 3A 7A 9A 7A 3A 7A 3A 7A 3A 9A 3A 7A 9A 9A 5A/NC 3A 5A/NC 9A - Cyclone V 5CSXFC6 U672 B19 C16 C17 A18 H17 A17 J17 B18 D20 C18 W15 A19 A23 J18 H19 A20 AA8 K18 J10 A21 AB6 B21 AC5 A22 AC6 K9 AD7 C21 F7 H8 AC24 AA6 AB23 H9 - HPS Pin Mux Select 3 HPS Pin Mux Select 2 HPS Pin Mux Select 1 HPS Pin Mux Select 0 CAN0_RX UART0_RX SPIM1_MISO HPS_GPIO65 CAN0_TX,CLKSEL0 UART0_TX,CLKSEL0 SPIM1_SS0 HPS_GPIO66 SPIM0_MOSI I2C1_SCL UART0_RTS HPS_GPIO58 SPIM0_CLK I2C1_SDA UART0_CTS HPS_GPIO57 UART0_TX,CLKSEL1 CAN0_TX,CLKSEL1 SPIM1_SS1 HPS_GPIO62 UART0_RX CAN0_RX SPIM0_SS1 HPS_GPIO61 SPIM0_SS0 CAN1_TX,BOOTSEL0 UART1_RTS,BOOTSEL0 HPS_GPIO60 SPIM0_MISO CAN1_RX UART1_CTS HPS_GPIO59 TRACE_D7 SPIS1_MISO I2C0_SCL HPS_GPIO56 TRACE_D6 SPIS1_SS0 I2C0_SDA HPS_GPIO55 TRACE_D5 SPIS1_MOSI CAN1_TX HPS_GPIO54 TRACE_D4 SPIS1_CLK CAN1_RX HPS_GPIO53 TRACE_D3 SPIS0_SS0 I2C1_SCL HPS_GPIO52 TRACE_D2 SPIS0_MISO I2C1_SDA HPS_GPIO51 TRACE_D1 SPIS0_MOSI UART0_TX HPS_GPIO50 TRACE_D0 SPIS0_CLK UART0_RX HPS_GPIO49 TRACE_CLK HPS_GPIO48 14 Copyright © 2015, Critical Link LLC Specifications Subject to Change 60-000035-1A Critical Link, LLC www.CriticalLink.com Module Pin Number 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 Class 5CSx_EIO PWR_VIO 5CSx_EIO PWR 5CSx_D 5CSx_IO 5CSx_EIO 5CSx_IO 5CSx_EIO 5CSx_IO 5CSx_D 5CSx_IO PWR 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO PWR 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO PWR 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO PWR 5CSx_IO 5CSx_IO 5CSx_IO SCH NET Name B5A_TX_R1_P/NC with FPGA DDR Memory +VIO_4A B5A_TX_R1_N/NC with FPGA DDR Memory GND MSEL2 B4A_TX_B80p/DQ8B/B_DM_4 B5A_TX_R3_P/NC with FPGA DDR Memory B4A_TX_B80n/DQ8B/B_DQ_39 B5A_TX_R3_N/NC with FPGA DDR Memory B4A_TX_B77p/DQ8B/B_DQ_38 MSEL3 B4A_TX_B77n/DQ8B/GND GND B4A_TX_B76n/DQ8B/B_DQ_35 B4A_RX_B78p/DQ8B/B_DQ_37 B4A_TX_B73p/DQ8B/B_DQ_34 B4A_RX_B78n/DQ8B/B_DQ_36 B4A_TX_B72p/DQ7B/B_DM_3 B4A_RX_B75p/DQS8B/B_DQS_4 B4A_TX_B72n/DQ7B/B_DQ_31 B4A_RX_B75n/DQSn8B/B_DQS#_4 B4A_TX_B69p/DQ7B/B_DQ_30 B4A_RX_B74p/DQ8B/B_DQ_33 B4A_TX_B69n/DQ7B/GND B4A_RX_B74n/DQ8B/B_DQ_32 GND B4A_RX_B70p/DQ7B/B_DQ_29 B4A_TX_B68n/DQ7B/B_DQ_27 B4A_RX_B70n/DQ7B/B_DQ_28 B4A_TX_B65p/DQ7B/B_DQ_26 B4A_RX_B67p/DQS7B/B_DQS_3 B4A_TX_B64p/DQ6B/B_DM_2 B4A_RX_B67n/DQSn7B/B_DQS#_3 B4A_TX_B64n/DQ6B/B_DQ_23 GND B4A_TX_B61p/DQ6B/B_DQ_22 B4A_RX_B66p/DQ7B/B_DQ_25 B4A_TX_B61n/DQ6B/GND B4A_RX_B66n/DQ7B/B_DQ_24 B4A_TX_B60p/B_RESET# B4A_RX_B62p/DQ6B/B_DQ_21 B4A_TX_B60n/DQ6B/B_DQ_19 B4A_RX_B62n/DQ6B/B_DQ_20 B4A_TX_B57p/DQ6B/B_DQ_18 B4A_RX_B59p/DQS6B/B_DQS_2 GND B4A_RX_B59n/DQSn6B/B_DQS#_2 B4A_TX_B56p/DQ5B/B_DM_1 B4A_RX_B58p/DQ6B/B_DQ_17 MitySOM MitySOM-5CSx System on Module 25 April 2019 Bank Number 5A/NC 5A/NC 9A 4A 5A/NC 4A 5A/NC 4A 9A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A Cyclone V 5CSXFC6 U672 AF26 AE26 G6 AF27 AE25 AF28 AD26 AG28 K10 AH27 AH26 AF25 AG26 AG25 AG24 AC22 AH24 AC23 AH23 AE24 AH22 AE23 AG23 AH21 AF23 AG21 AD23 AF20 AE22 AG20 AG19 AF22 AH19 AF21 AG18 AE20 AH18 AD20 AF18 AA19 AA18 AH17 AE19 HPS Pin Mux Select 3 HPS Pin Mux Select 2 15 HPS Pin Mux Select 1 HPS Pin Mux Select 0 Copyright © 2015, Critical Link LLC Specifications Subject to Change 60-000035-1A Critical Link, LLC www.CriticalLink.com Module Pin Number 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Class 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO PWR 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO PWR 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO PWR 5CSx_IO PWR_VIO 5CSx_IO PWR 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO SCH NET Name B4A_TX_B56n/DQ5B/B_DQ_15 B4A_RX_B58n/DQ6B/B_DQ_16 B4A_TX_B53p/DQ5B/B_DQ_14 CLK3p/B4A_RX_B55p B4A_TX_B53n/DQ5B/B_CKE_0 CLK3n/B4A_RX_B55n B4A_TX_B52p/B_CKE_1 GND B4A_TX_B52n/DQ5B/B_DQ_11 B4A_RX_B54p/DQ5B/B_DQ_13 B4A_TX_B49p/DQ5B/B_DQ_10 B4A_RX_B54n/DQ5B/B_DQ_12 GND B4A_RX_B51p/DQS5B/B_DQS_1 B4A_TX_B48p/DQ4B/B_DM_0 B4A_RX_B51n/DQSn5B/B_DQS#_1 B4A_TX_B48n/DQ4B/B_DQ_7 B4A_RX_B50p/DQ5B/B_DQ_9 B4A_TX_B45p/DQ4B/B_DQ_6 B4A_RX_B50n/DQ5B/B_DQ_8 B4A_TX_B45n/DQ4B/B_ODT_1 CLK2p/B4A_RX_B47p B4A_TX_B44p/B_ODT_0 CLK2n/B4A_RX_B47n B4A_TX_B44n/DQ4B/B_DQ_3 B4A_RX_B46p/DQ4B/B_DQ_5 B4A_TX_B41p/DQ4B/B_DQ_2 B4A_RX_B46n/DQ4B/B_DQ_4 RZQ_0/B4A_TX_B41n GND Key3 Key3 Key3 Key3 Key3 Key3 Key3 B4A_RX_B43p/DQS4B/B_DQS_0 +VIO_3B B4A_RX_B43n/DQSn4B/B_DQS#_0 GND B4A_RX_B42p/DQ4B/B_DQ_1 B3B_TX_B29p/DQ2B/B_A_10 B4A_RX_B42n/DQ4B/B_DQ_0 B3B_TX_B29n/DQ2B/B_A_11 B3B_RX_B38p/DQ3B/B_A_4 B3B_TX_B28p/B_A_12 B3B_RX_B38n/DQ3B/B_A_5 B3B_TX_B28n/DQ2B/B_A_13 MitySOM MitySOM-5CSx System on Module 25 April 2019 Bank Number 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 3B 4A 3B 3B 3B 3B 3B Cyclone V 5CSXFC6 U672 AH16 AD19 AG15 Y15 AH14 AA15 AG14 AH13 AD17 AH12 AE17 W14 AG11 V13 AH11 AF17 AG10 AG16 AH9 Y13 AG9 AA13 AH8 AF15 AG8 AE15 AH7 U14 U13 AG13 AE8 AF13 AF9 AE12 AE7 AD12 AF8 HPS Pin Mux Select 3 HPS Pin Mux Select 2 16 HPS Pin Mux Select 1 HPS Pin Mux Select 0 Copyright © 2015, Critical Link LLC Specifications Subject to Change 60-000035-1A Critical Link, LLC www.CriticalLink.com Module Pin Number 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 Class 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO PWR 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO PWR 5CSx_IO 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO PWR PWR_VIO 5CSx_IO 5CSx_IO 5CSx_IO 5CSx_IO PWR_VIO PWR 5CSx_EIO 5CSx_EIO 5CSx_EIO 5CSx_EIO 5CSx_EIO 5CSx_EIO 5CSx_EIO 5CSx_EIO 5CSx_EIO 5CSx_EIO SCH NET Name B3B_RX_B30p/DQ2B/B_A_8 B3B_TX_B32p/DQ2B/B_CAS# B3B_RX_B30n/DQ2B/B_A_9 B3B_TX_B32n/DQ2B/B_RAS# B3B_RX_B34p/DQ3B/B_BA_1 B3B_TX_B33p/DQ3B/B_BA_0 B3B_RX_B34n/DQ3B/B_BA_2 B3B_TX_B33n/GND GND B3B_TX_B40p/DQ3B/B_A_0 B3B_RX_B35p/DQS3B/B_CK B3B_TX_B40n/DQ3B/B_A_1 B3B_RX_B35n/DQSn3B/B_CK# GND B3B_RX_B27p/DQS2B/B_CS#_0 CLKOUT0,CLKOUTp,FPLL_BL_FB/ B3B_TX_B37p/DQ3B/B_A_2 B3B_RX_B27n/DQSn2B/B_CS#_1 CLKOUT1,CLKOUTn/B3B_TX_B37n/DQ3B/B_A_3 CLK1p/B3B_RX_B39p B3B_TX_B25p/DQ2B/B_WE# CLK1n/B3B_RX_B39n B3B_TX_B25n/GND CLK0p,FPLL_BL_FBp/B3B_RX_B31p B3B_TX_B36p/B_A_6 CLK0n,FPLL_BL_FBn/B3B_RX_B31n B3B_TX_B36n/DQ3B/B_A_7 B3B_RX_B26p/DQ2B/B_A_14 CLK6p,FPLL_TL_FBp/B8A_RX_T9p B3B_RX_B26n/DQ2B/B_A_15 CLK6n,FPLL_TL_FBn/B8A_RX_T9n GND +VIO_8A CLK7p/B8A_RX_T1p CLKOUT0,CLKOUTp,FPLL_TL_FB/B8A_TX_T4p CLK7n/B8A_RX_T1n CLKOUT1,CLKOUTn/B8A_TX_T4n VIO_3A5A5B/NC with FPGA DDR Memory GND B5A_RX_R2_P/NC with FPGA DDR Memory B3A_TX_B8_P/NC with FPGA DDR Memory B5A_RX_R2_N/NC with FPGA DDR Memory B3A_TX_B8_N/NC with FPGA DDR Memory B5A_RX_R4_P/NC with FPGA DDR Memory B3A_TX_B6_P/NC with FPGA DDR Memory B5A_RX_R4_N/NC with FPGA DDR Memory B3A_TX_B6_N/NC with FPGA DDR Memory B3A_RX_B7_P/NC with FPGA DDR Memory B3A_TX_B4_P/NC with FPGA DDR Memory MitySOM MitySOM-5CSx System on Module 25 April 2019 Bank Number 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B Cyclone V 5CSXFC6 U672 AD11 AF5 AE11 AF6 AF11 AF7 AF10 AG6 AH6 T13 AH5 T12 T11 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 8A 3B 8A 8A 8A 8A 8A 5A/NC 3A/NC 5A/NC 3A/NC 5A/NC 3A/NC 5A/NC 3A/NC 3A/NC 3A/NC AG5 U11 AH4 V12 AE4 W12 AF4 V11 AH3 W11 AH2 AD10 E11 AE9 D11 D12 E8 C12 D8 AA20 AC4 Y19 AD4 Y17 AD5 Y18 AE6 Y11 AA4 HPS Pin Mux Select 3 HPS Pin Mux Select 2 17 HPS Pin Mux Select 1 HPS Pin Mux Select 0 Copyright © 2015, Critical Link LLC Specifications Subject to Change 60-000035-1A Critical Link, LLC www.CriticalLink.com Module Pin Number 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 Class 5CSx_EIO 5CSx_EIO 5CSx_EIO 5CSx_EIO 5CSx_EIO 5CSx_EIO 5CSx_EIO PWR 5CSx_EIO 5CSX_GXB 5CSx_EIO 5CSX_GXB 5CSx_EIO PWR PWR 5CSX_GXB 5CSX_GXB 5CSX_GXB 5CSX_GXB PWR PWR 5CSX_GXB 5CSX_GXB 5CSX_GXB 5CSX_GXB PWR PWR 5CSX_GXB 5CSX_GXB 5CSX_GXB 5CSX_GXB PWR PWR 5CSX_GXB 5CSX_GXB 5CSX_GXB 5CSX_GXB PWR PWR 5CSX_GXB 5CSX_GXB 5CSX_GXB 5CSX_GXB PWR PWR 5CSX_GXB 5CSX_GXB 5CSX_GXB 5CSX_GXB MitySOM MitySOM-5CSx System on Module 25 April 2019 SCH NET Name Bank Number B3A_RX_B7_N/NC with FPGA DDR Memory B3A_TX_B4_N/NC with FPGA DDR Memory B3A_RX_B5_P/NC with FPGA DDR Memory B3A_TX_B2_P/NC with FPGA DDR Memory B3A_RX_B5_N/NC with FPGA DDR Memory B3A_TX_B2_N/NC with FPGA DDR Memory B3A_RX_B3_P/NC with FPGA DDR Memory GND B3A_RX_B3_N/NC with FPGA DDR Memory GXB_RX_0_P B3A_RX_B1_P/NC with FPGA DDR Memory GXB_RX_0_N B3A_RX_B1_N/NC with FPGA DDR Memory GND GND GXB_RX_1_P GXB_TX_0_P GXB_RX_1_N GXB_TX_0_N GND GND GXB_RX_2_P GXB_TX_1_P GXB_RX_2_N GXB_TX_1_N GND GND GXB_REFCLK0_P GXB_TX_2_P GXB_REFCLK0_N GXB_TX_2_N GND GND GXB_RX_3_P GXB_REFCLK1_P GXB_RX_3_N GXB_REFCLK1_N GND GND GXB_RX_4_P GXB_TX_3_P GXB_RX_4_N GXB_TX_3_N GND GND GXB_RX_5_P GXB_TX_4_P GXB_RX_5_N GXB_TX_4_N 3A/NC 3A/NC 3A/NC 3A/NC 3A/NC 3A/NC 3A/NC 3A/NC GXB_L0 3A/NC GXB_L0 3A/NC GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L0 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 GXB_L1 Cyclone V 5CSXFC6 U672 AA11 AB4 U10 Y5 V10 Y4 U9 T8 AF2 W8 AF1 Y8 AB2 AD2 AB1 AD1 V2 Y1 Y2 V1 V5 T2 V4 T1 P2 P8 P1 N8 K2 M2 K1 M1 F2 H2 F1 H1 HPS Pin Mux Select 3 HPS Pin Mux Select 2 18 HPS Pin Mux Select 1 HPS Pin Mux Select 0 Copyright © 2015, Critical Link LLC Specifications Subject to Change 60-000035-1A Critical Link, LLC www.CriticalLink.com Module Pin Number 242 243 244 245 246 247 248 249 250 251 252 Class MitySOM MitySOM-5CSx System on Module 25 April 2019 SCH NET Name Bank Number Cyclone V 5CSXFC6 U672 B12 D2 D1 B6 A6 C13 J12 A5 HPS Pin Mux Select 3 HPS Pin Mux Select 2 5CSx_D PWR 5CSx_HPS 5CSX_GXB 5CSx_D 5CSX_GXB 5CSx_HPS 5CSx_D 5CSx_HPS 5CSx_HPS 5CSx_HPS USB1_FAULT_N GND SDMMC_CLK_IN/USB0_CLK/HPS_GPIO44 GXB_TX_5_P USB1_PS_ON GXB_TX_5_N SDMMC_D1/USB0_D3/HPS_GPIO39 QSPI_SS0,BOOTSEL1/HPS_GPIO33 SDMMC_D0/USB0_D2/HPS_GPIO38 RGMII1_RX_CLK/NAND_DQ5/HPS_GPIO24 SDMMC_PWREN/USB0_D1/HPS_GPIO37 7C GXB_L1 GXB_L1 7C 7B 7C 7B 7C SDMMC_CLK_IN USB0_CLK HPS_GPIO44 SDMMC_D1 QSPI_SS0,BOOTSEL1 SDMMC_D0 NAND_DQ5 SDMMC_PWREN USB0_D3 HPS_GPIO39 HPS_GPIO33 HPS_GPIO38 HPS_GPIO24 HPS_GPIO37 HPS_GPIO28,B OOTSEL2 HPS_GPIO45 HPS_GPIO22 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 E1 E2 E3 E4 5CSx_HPS 5CSx_HPS 5CSx_HPS 5CSx_D 5CSx_HPS 5CSx_HPS 5CSx_HPS 5CSx_HPS 5CSx_HPS 5CSx_HPS 5CSx_HPS 5CSx_HPS 5CSx_HPS 5CSx_HPS 5CSx_HPS 5CSx_HPS 5CSx_HPS 5CSx_HPS 5CSx_HPS 5CSx_D PWR-Output 5CSx_D 5CSx_HPS 5CSx_D 5CSx_HPS 5CSx_D 5CSx_HPS PWR 5CSx_HPS PWR PWR I2C I2C QSPI 5CSx_D 5CSx_D 5CSx_D HPS_GPIO28,BOOTSEL2/NAND_WE 7B D15 NAND_WE SDMMC_CLK/USB0_STP/HPS_GPIO45 7C B8 SDMMC_CLK RGMII1_RX_CTL/NAND_DQ3/HPS_GPIO22 7B J13 NAND_DQ3 RTC_PSW/IRQ2_N RGMII1_RXD0/NAND_DQ0/HPS_GPIO19 7B A14 NAND_DQ0 SDMMC_CMD/USB0_D0/HPS_GPIO36 7C D14 SDMMC_CMD RGMII1_RXD1/NAND_DQ6/HPS_GPIO25 7B A11 NAND_DQ6 SDMMC_D3/USB0_NXT/HPS_GPIO47 7C B9 SDMMC_D3 RGMII1_RXD2/NAND_DQ7/HPS_GPIO26 7B C15 NAND_DQ7 SDMMC_D2/USB0_DIR/HPS_GPIO46 7C B11 SDMMC_D2 RGMII1_RXD3/NAND_WP/HPS_GPIO27 7B A9 NAND_WP SDMMC_D4/USB0_D4/HPS_GPIO40 7C H13 SDMMC_D4 RGMII1_MDC/NAND_DQ2/I2C3_SCL/HPS_GPIO21 7B A13 NAND_DQ2 SDMMC_D5/USB0_D5/HPS_GPIO41 7C A4 SDMMC_D5 RGMII1_MDIO/NAND_DQ1/I2C3_SDA/HPS_GPIO20 7B E16 NAND_DQ1 SDMMC_D6/USB0_D6/HPS_GPIO42 7C H12 SDMMC_D6 RGMII1_TX_CTL/NAND_DQ4/HPS_GPIO23 7B A12 NAND_DQ4 SDMMC_D7/USB0_D7/HPS_GPIO43 7C B4 SDMMC_D7 RGMII1_TX_CLK/NAND_ALE/HPS_GPIO14 7B J15 NAND_ALE USB1_ID +1.8VOUT USB1_D_N RGMII1_TXD3/NAND_RB/HPS_GPIO18 7B D17 NAND_RB USB1_D_P RGMII1_TXD2/NAND_RE/HPS_GPIO17 7B A15 NAND_RE +USB1_VBUS RGMII1_TXD1/NAND_CLE/HPS_GPIO16 7B J14 NAND_CLE GND RGMII1_TXD0/NAND_CE/HPS_GPIO15 7B A16 NAND_CE Reserved (Future Use) - 10-Pin Equivalent Reserved (Future Use) - 10-Pin Equivalent GND - 10-Pin Equivalent GND - 10-Pin Equivalent On-Module HPS Interfaces Below (No External Access) I2C0_SDA 7A C19 I2C0_SDA I2C0_SCL 7A B16 I2C0_SCL QSPI_IO0/USB1_CLK/HPS_GPIO29 7B A8 QSPI_IO0 USB0_D2 RGMII1_RX_CLK USB0_D1 QSPI_SS1 USB0_STP RGMII1_RX_CTL RGMII1_RXD0 USB0_D0 RGMII1_RXD1 USB0_NXT RGMII1_RXD2 USB0_DIR RGMII1_RXD3 USB0_D4 RGMII1_MDC USB0_D5 RGMII1_MDIO USB0_D6 RGMII1_TX_CTL USB0_D7 RGMII1_TX_CLK HPS Pin Mux Select 1 USB1_D6 USB1_D4 HPS Pin Mux Select 0 QSPI_SS3 HPS_GPIO19 HPS_GPIO36 HPS_GPIO25 HPS_GPIO47 HPS_GPIO26 HPS_GPIO46 HPS_GPIO27 HPS_GPIO40 HPS_GPIO21 HPS_GPIO41 HPS_GPIO20 HPS_GPIO42 HPS_GPIO23 HPS_GPIO43 HPS_GPIO14 RGMII1_TXD3 USB1_D3 HPS_GPIO18 RGMII1_TXD2 USB1_D2 HPS_GPIO17 RGMII1_TXD1 USB1_D1 HPS_GPIO16 RGMII1_TXD0 USB1_D0 HPS_GPIO15 UART1_RX UART1_TX SPIM1_CLK SPIM1_MOSI USB1_CLK HPS_GPIO63 HPS_GPIO64 HPS_GPIO29 19 USB1_D7 QSPI_SS2 I2C3_SCL I2C3_SDA USB1_D5 Copyright © 2015, Critical Link LLC Specifications Subject to Change 60-000035-1A Critical Link, LLC www.CriticalLink.com Module Pin Number QSPI QSPI QSPI QSPI QSPI QSPI USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 Class 5CSx_D 5CSx_D 5CSx_D 5CSx_D 5CSx_D 5CSx_D 5CSx_D 5CSx_D 5CSx_D 5CSx_D 5CSx_D 5CSx_D 5CSx_D 5CSx_D 5CSx_D 5CSx_D 5CSx_D 5CSx_D 5CSx_D SCH NET Name QSPI_IO1/USB1_STP/HPS_GPIO30 QSPI_IO2/USB1_DIR/HPS_GPIO31 QSPI_IO3/USB1_NXT/HPS_GPIO32 QSPI_CLK/HPS_GPIO34 QSPI_SS1/HPS_GPIO35 HPS_GPIO0 HPS_GPIO9 USB1_D0 USB1_D1 USB1_D2 USB1_D3 USB1_D4 USB1_D5 USB1_D6 USB1_D7 USB1_CLK USB1_STP USB1_DIR USB1_NXT MitySOM MitySOM-5CSx System on Module 25 April 2019 Bank Number 7B 7B 7B 7B 7B 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D Cyclone V 5CSXFC6 U672 H16 A7 J16 C14 B14 E4 C6 C10 F5 C9 C4 C8 D4 C7 F4 G4 C5 E5 D5 HPS Pin Mux Select 3 QSPI_IO1 QSPI_IO2 QSPI_IO3 QSPI_CLK QSPI_SS1 RGMII0_TX_CLK RGMII0_TX_CTL RGMII0_TXD0 RGMII0_TXD1 RGMII0_TXD2 RGMII0_TXD3 RGMII0_RXD0 RGMII0_MDIO RGMII0_MDC RGMII0_RX_CTL RGMII0_RX_CLK RGMII0_RXD1 RGMII0_RXD2 RGMII0_RXD3 HPS Pin Mux Select 2 USB1_D0 USB1_D1 USB1_D2 USB1_D3 USB1_D4 USB1_D5 USB1_D6 USB1_D7 USB1_CLK USB1_STP USB1_DIR USB1_NXT HPS Pin Mux Select 1 HPS Pin Mux Select 0 USB1_STP USB1_DIR USB1_NXT HPS_GPIO30 HPS_GPIO31 HPS_GPIO32 HPS_GPIO34 HPS_GPIO35 HPS_GPIO0 HPS_GPIO9 HPS_GPIO1 HPS_GPIO2 HPS_GPIO3 HPS_GPIO4 HPS_GPIO5 HPS_GPIO6 HPS_GPIO7 HPS_GPIO8 HPS_GPIO10 HPS_GPIO11 HPS_GPIO12 HPS_GPIO13 I2C2_SDA I2C2_SCL Notes: 1) For more information about pin definitions and pin connection guidelines please refer to the Cyclone V Device Family Pin Connection Guidelines (PCG-01014) 2) The Keys are shown in the numbering but no actual pins exist. The connector is 314-pins counted as follows: 281 total "pins" minus 7 for the "keys" plus 40 for the E1, E2, E3 and E4 pin-groups. 20 Copyright © 2015, Critical Link LLC Specifications Subject to Change 60-000035-1A Critical Link, LLC www.CriticalLink.com MitySOM MitySOM-5CSx System on Module 25 April 2019 ELECTRICAL CHARACTERISTICS Symbol Parameter Table 9: Electrical Characteristics Conditions VIN I5.0 Voltage supply, volt input. Quiescent Current draw[1] I5.0 Quiescent Current draw[1] I5.0 Quiescent Current draw[1] I5.0 Quiescent Current draw[1] I1.8V-Out Output current capability 1.8V supply from MitySOM 1.8V supply from MitySOM Only recommended to support Bank 7B IO signals Only recommended to support Bank 7B IO signals RTC Battery Backup Current draw RTC Battery Backup Current draw VBAT = 3.0V, volatile key storage not enabled VBAT = 3.0V, Theoretical maximum V1.8V-Out I+3VBAT I+3VBAT 1. Min Typ Max Units 4.8 5.0 420 5.15 Volts mA 5CSX-H6-42A 5.0 volt input, 800 MHz Dual Core, 1GB DDR3, no FPGA fabric, Linux idle 5CSX-H6-42A 5.0 volt input, 800 MHz Dual Core, 1GB DDR3, FPGA fabric programmed with Dev Kit example, Linux idle 5CSE-L2-3Y8 5.0 volt input, 600 MHz Single Core, 512MB DDR3, no FPGA fabric, Linux idle 5CSE-L2-3Y8 5.0 volt input, 600 MHz Single Core, 512MB DDR3, FPGA fabric programmed with Dev Kit example, Linux idle 1.62 540 mA 354 mA 368 mA 500 mA 1.8 1.98 Volts 600 1100 nA 4700 nA Power utilization of the MitySOM-5CSX is heavily dependent on end-user application. Major factors include: ARM CPU PLL configuration, CPU Utilization, and external DDR3 RAM utilization. 21 Copyright © 2019, Critical Link LLC Specifications Subject to Change 60-000035-1A Critical Link, LLC www.CriticalLink.com MitySOM MitySOM-5CSx System on Module 25 April 2019 ORDERING INFORMATION The following table lists the standard module configurations. For shipping status, availability, and lead time of these configurations please contact your Critical Link representative or visit one of our authorized distributors. Cores Model 5CSE-L2-3Y8-RC 5CSE-H4-3YA-RC 5CSE-H4-3YA-RI 5CSE-H4-8YA-RI 5CSX-H5-4YA-RC 5CSX-H5-4YA-RI 5CSX-H6-42A-RC 5CSX-H6-42A-RI 5CSX-H6-4YA-RC 5CSX-H6-4YA-RI 5CSX-H6-53B-RC Single Dual Dual Dual Dual Dual Dual Dual Dual Dual Dual CPU MHz 600 800 800 800 800 800 800 800 800 800 800 Table 10: Standard Model Numbers Speed FPGA NOR FPGA FPGA Grade KLE I/O RAM 8 25 16MB 133 N/A 7 40 16MB 133 N/A 7 40 16MB 133 N/A 7 40 272MB 133 N/A 7 85 32MB 133 N/A 7 85 32MB 133 N/A 7 110 32MB 107 256MB 7 110 32MB 107 256MB 7 110 32MB 133 N/A 7 110 32MB 133 N/A 7 110 48MB 107 512MB HPS RAM 512MB 1GB 1GB 1GB 1GB 1GB 1GB 1GB 1GB 1GB 2GB Component Temperature Ratings 0oC to 70o C 0oC to 70o C -40oC to 85o C -40oC to 85o C 0oC to 70o C -40oC to 85o C 0oC to 70o C -40oC to 85o C 0oC to 70o C -40oC to 85o C 0oC to 70o C MitySOM-5CSx Module Family Model Number Guide If a module suitable for your specific application is not found in Table 10 please reference the following MitySOM-5CSx model number decoder for configuring a custom module. Please contact your Critical Link representative to determine pricing, lead-time and availability of a custom module. 5CSX- H6-42A-RC Component Temperature Range C – 0oC to 70oC (Commercial) I – -40oC to 85oC (Industrial) CPU 5CSX – 3.125Gbps Transceivers 5CSE – No Transceivers RoHS Compliance R – RoHS Compliant CPU Speed Grade H – 800MHz (Dual Core) – C7 & I7 Grade S – 800MHz (Single Core) – C7 & I7 Grade O – 600MHz (Dual) – C8 Grade L – 600MHz (Single Core) – C8 Grade M – 925MHz (Dual Core) – C6 Grade N – 925MHz (Single) – C6 Grade HPS RAM Size 8 – 512MB DDR3 (No ECC) A – 1GB DDR3 (ECC) B – 2GB DDR3 (ECC) FPGA Ram Size X – None with Standard IO 2 – 256MB with Standard IO 3 – 512MB with Standard IO Y – None with Expanded IO NOR Flash Size 3 – 16MB (1x 16MB) 1.8V 4 – 32MB (2x 16MB) 1.8V 5 – 48MB (1x 16MB & 1x 32MB) 1.8V 8 – 272MB (1x 16MB & 1 x 256MB) 1.8V FPGA Size 2 – 25 KLE’s 4 – 40 KLE’s 5 – 85 KLE’s 6 – 110 KLE’s 22 Copyright © 2019, Critical Link LLC Specifications Subject to Change 60-000035-1A Critical Link, LLC www.CriticalLink.com MitySOM MitySOM-5CSx System on Module 25 April 2019 MECHANICAL INTERFACE A mechanical outline of the MitySOM-5CSx is illustrated in Figure 2, below. Figure 2 MitySOM-5CSx Mechanical Outline REVISION HISTORY Revision Date ENGINEERING May 31, 2013 ENGINEERING September 12, 2013 ENGINEERING March 5, 2014 ENGINEERING March 31, 2014 ENGINEERING November 19, 2014 ENGINEERING September 10, 2015 ENGINEERING October 12, 2018 1A April 25, 2019 Change Description Preliminary specification Initial release Update MitySOM product name Update memory data Modifications for MitySOM-5CSE Update tables 1, 3 and 7 and add HPS DDR memory speed. Added module part number decoder to ordering information section. Update Altera/Intel documentation links, add additional Table 8 information and add Table 3 for JTAG debug header. General notes enhancements including add Table 3 J2 Hirose Connector, add Model Number Guide to Table 10. 23 Copyright © 2019, Critical Link LLC Specifications Subject to Change 60-000035-1A Critical Link, LLC www.CriticalLink.com MitySOM MitySOM-5CSx System on Module 25 April 2019 FOOTNOTES [1]https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclo ne-v/cv_5400a.pdf [2] https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclonev/cv_5v4.pdf [3] https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dow nload-cables.html [4] https://www.intel.com/content/www/us/en/programmable/support/supportresources/operation-and-testing/power/pow-powerplay.html [5]https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclo ne-v/pcg-01014.pdf 24 Copyright © 2019, Critical Link LLC Specifications Subject to Change 60-000035-1A
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