Critical Link, LLC
www.criticallink.com
MitySOM
MitySOM-1810 Processor Card
5-MAR-2014
FEATURES
TI AM1810 ARM9 Application Processor
-
375 MHz ARM926EJ-S MPU
16 KB L1 Program Cache
16 KB L1 Data Cache
8 KB Internal RAM
64 KB boot ROM
JTAG Emulation/Debug
Up To 256 MB mDDR2 CPU RAM
Up To 512 MB Parallel NAND FLASH
8 MB SPI based NOR FLASH
Integrated Power Management
Standard SO-DIMM-200 Interface
- 10/100 EMAC MII / RMII / MDIO
- 2 UARTS
- 2 McBSPs, 2 SPI, 2HPI
- 2 USB Ports
- Video, LCD Output
- Camera/Video Input
- MMC/SD
- SATA
- ePWM, eCAP
- EMIFA
- Single 3.3V Power Supply
(actual size)
APPLICATIONS
Process Automation
Factory Automation
Industrial Automation
Industrial Instrumentation
Embedded Control Processing
Test and Measurement
BENEFITS
Rapid Development / Deployment
Multiple Connectivity and Interface Options
Rich User Interfaces
High System Integration
High Level OS Support
- Real-Time Linux Kernel 2.6
- QNX 6.4
- Windows Embedded CE Ready
- ThreadX Real Time OS
PROFIBUS Interface
- Certified by PI International
- Real-Time Linux Drivers
- Up to 6Mbaud operation
DESCRIPTION
The MitySOM-1810 is a highly configurable, very small form-factor processor card that
features a Texas Instruments AM1810 375MHz ARM Applications Processor for
PROFIBUS, FLASH (NAND, and NOR) and mDDR2 RAM memory subsystems. The
MitySOM-1810 provides a complete and flexible CPU infrastructure necessary for the
most demanding embedded applications development.
The AM1810 includes an ARM926EJ-S micro-processor unit (MPU) capable of running
the rich software applications programming interfaces (APIs) expected by modern system
designers. The ARM architecture supports several operating systems, including Linux,
QNX and Windows XP embedded.
Linux drivers are available for all interfaces,
including the PROFIBUS interface.
1
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MitySOM
MitySOM-1810 Processor Card
5-MAR-2014
1.2V
8MB NOR Flash
(SPI interface)
For uBoot
bootloader
Up To 256MB
mDDR Memory
16-bit wide
1.8V
2.5V
Power
Management
3.3V
System
Clocks
JTAG
Header
JTAG/Emulator
Texas Instruments
AM1810
375-MHz ARM926EJ-S ™ RISC MPU
GND
Up To 512MB
NAND Flash
8-bit wide
For root FFS
3.3 V
EMIFA (16-bit)
Boot
Config
Boot Config
VPIF I/O
MMCSD 1
EMAC RMII
uPP
UHPI
LCD
Resets & RTC
SATA
USB 0,1
Timers
eCAP
eHRPWM
I2C 0,1
McASP
SPI 0,1
McBSP 0,1
MMCSD 0
UART 0,1,2
EMAC MII/MDIO
(Many pins are multiplexed between peripherals)
SO-DIMM-200 (DDR2 Connector)
Figure 1 MitySOM-1810 Block Diagram
Figure 1 provides a top level block diagram of the MitySOM-1810 processor card. As
shown in the figure, the primary interface to the MitySOM-1810 is through a standard
SO-DIMM-200 card edge interface. The interface provides power, synchronous serial
connectivity, and a rich set of interfaces available for application defined interfacing.
Details of the SO-DIMM-200 connector interface are included in the SO-DIMM-200
Interface Description, below.
PROFIBUS Interface
Texas Instruments Inc. (TI) has integrated PROFIBUS functionality into its AM1810
Sitara ARM microprocessor (MPU). The solution utilizes one of the onboard UARTS
and connects directly to the RS-485 transceiver and therefore eliminates the need of an
external PROFIBUS ASIC or FPGA. Customers using the MitySOM-1810 in their
industrial application can save cost and reduce design complexity as well as PCB space.
Furthermore, the industrial application benefits from the low-power architecture of the
Sitara ARM MPU and the MitySOM-1810 platform from TI and Critical Link.
The AM1810 Sitara ARM MPU PROFIBUS Slave solution has been certified by
PROFIBUS International (PI).
The PROFIBUS real-time frame handler (Fieldbus Data Link or FDL) is encapsulated in
the Programmable Real-Time Unit Subsystem (PRUSS), which is part of the AM1810
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MitySOM
MitySOM-1810 Processor Card
5-MAR-2014
Sitara ARM MPU on-chip peripherals. The PRUSS uses one Universal Asynchronous
Receiver/Transmitter (UART) and a timer to generate PROFIBUS-compliant frames. The
industrial application and the PROFIBUS DP-Protocol (Layer 7) are operated on the
ARM. The solution can be completed with an RS-485 transceiver suitable for harsh
environments, such as TI’s ISO1176T or ISO1176 placed on the base board to the
MitySOM-1810.
The PROFIBUS subsystem uses the PRUs that implement real-time frame handling;
PROFIBUS message transmission, frame validation and communication with the ARM
processor. The PROFIBUS subsystem interfaces with one of the UARTs in the AM1810
Sitara ARM MPU, which is designated for PROFIBUS communication at up to 6Mbaud
data rate. The PRU uses interrupts to interact with the ARM where the PROFIBUS stack
(Layer 7, DP Protocol) and the industrial application is run. All process data handling like
cyclic, acyclic and service access point (SAP) between the PROFIBUS stack on ARM
and the PRU is through the internal memory.
Additional details about the AM1810 Sitara ARM MPU, available peripherals and their
features are provided in the data sheet at the TI website (www.ti.com/am1810).
AM1810 mDDR2 Memory Interface
The AM1810 includes a dedicated DDR2 SDRAM memory interface. The MitySOM1810 includes up to 256 MB of mDDR2 RAM integrated with the AM1810 processor.
The bus interface is capable of burst transfer rates of 532 MB / second. Note that the
OSCIN frequency to the AM1810 processor on the module is 24MHz.
AM1810 SPI NOR FLASH Interface
The MitySOM-1810 includes 8 MB of SPI NOR FLASH. This FLASH memory is
intended to store a factory provided bootloader, and typically a compressed image of a
linux kernel for the ARM core processor.
EMIFA / NAND FLASH Interface
The Asynchronous External Memory Interface (EMIFA) interface available on the
AM1810 is available on the SO-DIMM-200 connector. The EMIFA interface includes 3
chip select spaces. The EMIF interface supports multiple data width transfers and bus
wait state configurations based on chip select space. 8, and 16 bit data word sizes may be
used.
Up to 512 MB of on-board NAND FLASH memory is connected to the AM1810 using
the EMIFA bus. The FLASH memory is 8 bits wide and is connected to the third chip
select line of the EMIFA (CE1). The FLASH memory is typically used to store the
following types of data:
- ARM Linux / Windows Embedded CE / QNX embedded root file-system
- runtime ARM software
- runtime application data (non-volatile storage)
3
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MitySOM
MitySOM-1810 Processor Card
5-MAR-2014
AM1810 Camera and Video Interfaces
The AM1810 includes an optional video port I/O interface commonly used to drive LCD
screens as well as a camera input interface. These interfaces have been routed directly to
the SO-DIMM-200 connector.
Debug Interface
The JTAG signals for the AM1810 processor have been brought out to a Hirose header
that is intended for use with an available Critical Link breakout adapter. This header can
be removed for production units; please contact your Critical Link representative for
details.
This adapter is not included with individual modules but is included with each Critical
Link Development Kit that is ordered. If an adapter, Critical Link (CL) part number
80-000286, is needed please contact your Critical Link representative.
Software and Application Development Support
Users of the MitySOM-1810 are encouraged to develop applications using the MitySOM1810 software development kit provided by Critical Link LLC. The development kit
includes an implementation of an OpenEmbedded board support package providing an
Angstrom based Linux distribution and compatible gcc compiler tool-chain with
debugger.
Growth Options
The MitySOM-1810 has been designed to support several upgrade options. These options
include various speed grades, memory configurations, and operating temperature
specifications including commercial and industrial temperature ranges. The available
options are listed in the section below containing ordering information. For additional
ordering information and details regarding these options, or to inquire about a particular
configuration not listed below, please contact a Critical Link sales representative.
4
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MitySOM
MitySOM-1810 Processor Card
5-MAR-2014
ABSOLUTE MAXIMUM RATINGS
OPERATING CONDITIONS
If Military/Aerospace specified cards are
required, please contact the Critical Link Sales
Office or unit Distributors for availability and
specifications.
Ambient Temperature
Range Commercial
Ambient Temperature
Range Industrial
Humidity
Maximum Supply Voltage, Vcc
3.5 V
0oC to 70oC
-40oC to 85oC
0 to 95%
Non-condensing
Contact Critical
Link for Details
MIL-STD-810F
Storage Temperature Range
Shock, Z-Axis
Shock, X/Y-Axis
-65 to 80C
±10 g
±10 g
SO-DIMM-200 Interface Description
The primary interface connector for the MitySOM-1810 is the SO-DIMM card edge
interface which contains 4 classes of signals:
Power (PWR)
Dedicated signals mapped to the AM-1810 device (D)
Dedicated signals when NAND memory is populated on the module (D*)
Multi-function signals mapped to the AM1810 device (M)
Table 1 contains a summary of the MitySOM-1810 pin mapping.
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
Ball
K14
J1
J2
L1
L2
P16
P18
P19
N19
M18
M19
K18
-
Type
PWR
PWR
PWR
PWR
PWR
D
D
D
D
D
D
D
D
D
D
D
D
D
PWR
PWR
I/O
I
O
O
I
I
I
I/O
I/O
O
I/O
I/O
O
-
Table 1 SO-DIMM Pin-Out
Signal
Pin Ball
+3.3 V in
2
+3.3 V in
4
+3.3 V in
6
GND
8
GND
10
RESET_IN#
12
SATA_TX_P
14
A4
SATA_TX_N
16
A3
SATA_RX_P
18
A2
SATA_RX_N
20
A1
USB0_ID
22
B4
USB1_D_N
24
B1
USB1_D_P
26
B2
USB0_VBUS
28
B3
USB0_D_N
30
C2
USB0_D_P
32
C3
USB0_DRVVBUS
34
C4
3V RTC Battery
36
C5
+3.3 V in
38
+3.3 V in
40
-
5
Type
PWR
PWR
PWR
PWR
PWR
D
M
M
M
M
M
M
M
M
M
M
M
M
PWR
PWR
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
Signal
+3.3 V in
+3.3 V in
+3.3 V in
GND
GND
EXT_BOOT#
GP0_7
GP0_10
GP0_11
GP0_15
GP0_6
GP0_14
GP0_12
GP0_5
GP0_13
GP0_1
GP0_4
GP0_3
+3.3 V in
+3.3 V in
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Pin
41
43
45
47
491
51
53
552
572
59
Ball
H17
G17
H16
G19
F18
G16
G18
F16
Type
PWR
D
D
D
D
M
D
D
D
M
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
61
F17
M
I/O
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
F19
E18
E16
D17
D19
C17
D16
E17
D18
C19
C18
C16
A18
B15
C15
PWR
M
M
M
M
M
M
M
M
M
M
PWR
M
M
M
D*
M
O
I
O
I/O
I
I
I
I
I
I
I
I
O
O
O
97
A15
M
O
99
C14
M
101
D15
103
MitySOM
MitySOM-1810 Processor Card
5-MAR-2014
Signal
GND
SPI1_MISO
SPI1_MOSI
SPI1_ENA
SPI1_CLK
SPI1_SCS[1]
Reserved
I2C0_SCL
I2C0_SDA
UART2_TXD
I2C1_SDA
UART2_RXD
I2C1_SCL
GND
UART1_TXD
UART1_RXD
MDIO_CLK
MDIO_D
MII_RXCLK
MII_RXDV
MII_RXD[0]
MII_RXD[1]
MII_RXD[2]
MII_RXD[3]
GND
MII_CRS
MII_RXER
EMA_CS[0]
EMA_OE
EMA_BA[0]
/
Pin
42
44
46
48
50
52
54
56
58
60
Ball
D4
E4
F4
D5
A12
C11
E12
B11
E11
Type
PWR
M
M
M
M
M
M
M
M
M
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Signal
GND
GP0_2
GP0_0
GP0_8
GP0_9
MMCSD0_DAT[7]
MMCSD0_DAT[6]
MMCSD0_DAT[5]
MMCSD0_DAT[4]
MMCSD0_DAT[3]
/
62
C10
M
I/O
MMCSD0_DAT[2]
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
A11
B10
A10
E9
D3
E3
E2
E1
F3
C1
D1
W15
V15
U18
PWR
M
M
M
M
M
M
M
M
M
M
PWR
M
D
M
M
M
I/O
I/O
I/O
O
I
O
O
O
O
O
I
I/O
I
I/O
EMA_BA[1]
98
V16
M
I/O
O
EMA_A[0]
100
R14
M
I/O
D*
O
EMA_A[1]
102
W16
M
I/O
B14
D*
O
EMA_A[2]
104
V17
M
I/O
105
D14
M
O
EMA_A[3]
106
W17
M
I/O
107
109
A14
PWR
M
O
GND
EMA_A[4]
108
110
W18
PWR
M
I/O
111
C13
M
O
EMA_A[5]
112
W19
M
I/O
113
115
117
119
121
E13
B13
A13
D12
C12
M
M
M
M
M
O
O
O
O
O
EMA_A[6]
EMA_A[7]
EMA_A[8]
EMA_A[9]
EMA_A[10]
114
116
118
120
122
V18
V19
U16
U19
T16
M
M
M
M
M
I/O
I/O
I/O
I/O
I/O
GND
MMCSD0_DAT[1]
MMCSD0_DAT[0]
MMCSD0_CMD
MMCSD0_CLK
MII_TXCLK
MII_TXD[3]
MII_TXD[2]
MII_TXD[1]
MII_TXD[0]
MII_TXEN
GND
MII_COL
NC
UPP_CHA_START
VP_CLKIN1
UPP_D[15]
/
RMII_TXD[1]
UPP_D[14]
/
RMII_TXD[0]
UPP_D[13]
/
RMII_TXEN
UPP_D[12]
/
RMII_RXD[1]
UPP_D[11]
/
RMII_RXD[0]
UPP_D[10]
/
RMII_RXER
GND
UPP_D[9]
/
RMII_REF_CLK
UPP_D[8]
/
RMII_CRS_DV
UPP_D[7]
UPP_D[6]
UPP_CHA_ENABLE
UPP_D[5]
UPP_D[4]
6
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Pin
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
1713
173
175
177
179
181
183
185
187
189
191
193
195
1974
1994
Ball
B12
D13
D11
E6
C7
B6
A6
D6
A7
D9
E10
D7
C6
E7
B5
E8
B8
A8
C9
C8
A5
D8
B7
B9
A9
A16
B17
F9
B16
T17
J3
K4
F2
D10
A17
Type
M
M
M
PWR
D*
D*
D*
D*
D*
D*
D*
D*
D*
D*
PWR
D*
D*
D*
D*
D*
D*
M
M
M
M
PWR
D*
M
M
M
M
M
D
M
M
M
PWR
M
D*
I/O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
I
O
O
O
O
MitySOM
MitySOM-1810 Processor Card
5-MAR-2014
Signal
EMA_A[11]
EMA_A[12]
EMA_A[13]
GND
EMA_D[15]
EMA_D[14]
EMA_D[13]
EMA_D[12]
EMA_D[11]
EMA_D[10]
EMA_D[9]
EMA_D[8]
EMA_D[7]
EMA_D[6]
GND
EMA_D[5]
EMA_D[4]
EMA_D[3]
EMA_D[2]
EMA_D[1]
EMA_D[0]
EMA_WEN_DQM[0]
EMA_WEN_DQM[1]
EMA_SDCKE
EMA_CLK
GND
EMA_WE
EMA_CAS
EMA_RAS
EMA_CS[2]
EMA_CS[4]
EMA_CS[5]
RESET_OUT
VP_CLKIN3
VP_CLKOUT3
LCD_MCLK
GND
EMA_A_RW
EMA_CS[3]
Pin
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
Ball
R18
R19
T15
R15
P17
U17
J4
K3
H3
G3
G2
G1
W14
P4
R3
R2
R1
T3
T2
T1
U3
U2
U1
G4
H4
V3
F1
V2
V1
W3
W2
W1
R5
B184
B194
Type
M
M
M
PWR
M
M
M
M
M
M
M
M
M
M
PWR
M
M
M
M
M
M
M
M
M
M
PWR
M
M
M
M
M
M
M
M
M
M
PWR
D*
M
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I/O
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
I/O
O
I/O
I/O
I/O
I/O
I/O
O
I
I
Signal
UPP_D[3]
UPP_D[2]
UPP_CHA_WAIT
GND
UPP_D[1]
UPP_D[0]
UPP_CHA_CLK
UPP_CHB_ENABLE
VP_CLKOUT2
VP_CLKIN2
UPP_CHB_WAIT
UPP_CHB_START
UPP_CHB_CLK
VP_CLKIN0
GND
LCD_D[15]
LCD_D[14]
LCD_D[13]
LCD_D[12]
LCD_D[11]
LCD_D[10]
LCD_D[9]
LCD_D[8]
LCD_D[7]
LCD_D[6]
GND
LCD_VSYNC
LCD_HSYNC
LCD_D[5]
LCD_PCLK
LCD_D[4]
LCD_D[3]
LCD_D[2]
LCD_D[1]
LCD_D[0]
LCD_AC_ENB_CS
GND
EMA_WAIT[0]
EMA_WAIT[1]
Note 1: Pin 49, SPI1_CLK, has a 100K Ohm pull-down resistor on the module
Note 2: Pins 55 and 57 have 4.70K pull-up resistors on the module
Note 3: Pin 171, EMA_CLK, has a 49.9 Ohm resistor in series with the signal on the
module
Note 4: Pins 197, 198, 199 and 200 have 1.00K Ohm resistors in series with the signals
on the module
The signal group description for the above pins is included in Table 2
7
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MitySOM
MitySOM-1810 Processor Card
5-MAR-2014
Table 2 Signal Group Description
Signal / Group
3.3 V in
EXT_BOOT#
RESET_IN#
Type
N/A
I
I
SPI1_*
I/O
MII_*
I/O
MDIO_DAT
MDIO_CLK
I/O
GP0_*
I/O
SATA_TX_P
SATA_TX_N
O
SATA_RX_P
SATA_RX_N
I
GND
N/A
Description
3.3 volt input power referenced to GND.
Bootstrap configuration pin. Pull low to configure booting
from external UART1.
Manual Reset. When pulled to GND for a minimum of 1
usec, resets the processor.
Serial Peripheral Interface 1 pins.
These pins are direct connects to the corresponding SPI1_*
pins on the AM1810 processor. The SPI1_* function pins are
multiplexed with other functions. These include PWM,
Timers, UARTs, I2C0, and GPIO. For details please refer to
the AM1810 processor specifications.
Media Independent Interface (Ethernet) pins.
These pins are direct connects to the corresponding MII_*
pins on the AM1810 processor. The MII_* function pins are
multiplexed with other functions. These include SPI0, PWM,
Timers, UART0, MCBSP, MCASP, and GPIO. For details
please refer to the AM1810 processor specifications.
MII/RMII Management Interface pins.
The MDIO_CLK and MDIO_DAT signals are direct connects
to the corresponding MDIO_* signals on the AM1810
processor. The MDIO_* function pins are multiplexed with
other functions. These include SPI0 and Timer functions.
For details please refer to the AM1810 processor
specifications.
General Purpose / multiplexed pins. These pins are direct
connects to the corresponding GP0[*] pins on the AM1810
processor. The include support for the McASP, general
purpose I/O, UART flow control, and McBSP 1. For details
please refer to the AM1810 processor specifications.
Serial ATA Controller Transmit pins.
These pins are direct connects to the corresponding
SATA_TX_* pins on the AM1810 processor. For details
please refer to the AM1810 processor specifications.
Serial ATA Controller Receive pins.
These pins are direct connects to the corresponding
SATA_RX_* pins on the AM1810 processor. For details
please refer to the AM1810 processor specifications.
System Digital Ground.
8
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Specifications Subject to Change
Critical Link, LLC
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Signal / Group
EMA_*
MitySOM
MitySOM-1810 Processor Card
5-MAR-2014
Type
I/O
UPP_*
I/O
RMII_*
I/O
LCD_*
I/O
VP_*
I/O
RESET_OUT
I/O
USB0_*,
USB1_*
I/O
Description
EMIF-A pins. These pins are direct connects to the
corresponding EMA_* pins on the AM1810 processor.
Alternatively, these pins can be configured as GPIOs for
modules that do not have NAND memory present. For details
please refer to the AM1810 processor specifications. Note that
pins 197, 198, 199 and 200 have 1.00K Ohm resistors in
series with the signals on the module.
Universal Parallel Port pins.
These pins are direct connects to the corresponding UPP_*
pins on the AM1810 processor. The UPP_* function pins are
multiplexed with other functions. These include RMII,
VP_DIN, MMCSD1, and GPIO. For details please refer to
the AM1810 processor specifications.
Reduced Media Independent Interface pins.
These pins are direct connects to the corresponding RMII_*
pins on the AM1810 processor. The RMII_* function pins
are multiplexed with other functions. These include UPP and
VP_DIN. For details please refer to the AM1810 processor
specifications.
Liquid Crystal Display pins.
These pins are direct connects to the corresponding LCD_*
pins on the AM1810 processor. The LCD_* function pins are
multiplexed with other functions. These include VP_DOUT,
UPP, MMCSD1, and GPIO. For details please refer to the
AM1810 processor specifications.
Video Port In/Out.
These pins are direct connects to the corresponding VP_* pins
on the AM1810 processor. The VP_* function pins are
multiplexed with other functions. These include UPP,
MMCSD1, and GPIO. For details please refer to the AM1810
processor specifications.
Reset Output pin.
This pin is a direct connect to the RESET_OUT pin on the
AM1810 processor. This pin can also be configured as a
GPIO. For details please refer to the AM1810 processor
specifications.
Universal Serial Bus 0 / 1 pins.
These pins are direct connects to the corresponding USB_*
pins on the AM1810 processor. For details please refer to the
AM1810 processor specifications.
9
Copyright © 2013, Critical Link LLC
Specifications Subject to Change
Critical Link, LLC
www.criticallink.com
MitySOM
MitySOM-1810 Processor Card
5-MAR-2014
DEBUG INTERFACE
Below is the pin-out for the Hirose 31 pin header (DF9-31P-1V(32)) that interfaces with
an available adapter board, CL part number 80-000286, to debug the AM1810.
Debug Interface Connector Description (J2)
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
I/O
-
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Table 3 AM1810 Hirose Connector
Signal
Pin
I/O
Signal
2
O
OMAP EMU1
4
O
OMAP EMU0
6
I
OMAP TCK
8
O
OMAP RTCK
10
O
OMAP TDO
12
OMAP VCC / 3.3V
14
I
OMAP TDI
16
I
OMAP TRST
18
I
OMAP TMS
20
GND
22
NC FPGA VREF / VCCAUX
24
NC FPGA TMS
26
NC FPGA TCK
28
NC FPGA TDO
30
NC FPGA TDI
10
Copyright © 2013, Critical Link LLC
Specifications Subject to Change
Critical Link, LLC
www.criticallink.com
MitySOM
MitySOM-1810 Processor Card
5-MAR-2014
ELECTRICAL CHARACTERISTICS
Table 4: Electrical Characteristics
Parameter
Conditions
Min
Symbol
V33
I33
I33-max
FCPU
FEMIF
Typ
Max
Voltage supply, 3.3 volt input.
3.2
3.3
Quiescent Current draw, 3.3 volt input
230
Max current draw, positive 3.3 volt input.
300
CPU internal clock Frequency (PLL output)
25
375
EMIF bus frequency
100
1.
Power utilization of the MitySOM-1810 is heavily dependant on end-user application.
include: ARM CPU PLL configuration, and external DDR2 RAM utilization.
Units
3.4
Volts
TBS
mA
TBS
mA
375
MHz
MHz
Major factors
ORDERING INFORMATION
The following table lists the standard module configurations. For shipping status,
availability, and lead time of these or other configurations please contact your Critical
Link representative.
Model
1810-DX-225-RC
1810-DX-225-RI
Table 5: Standard Model Numbers
NOR
ARM Speed
NAND Flash
Flash
375 MHz
8MB
256MB
375 MHz
8MB
256MB
11
RAM
128MB
128MB
Operating
Temp
0oC to 70o C
-40oC to 85o C
Copyright © 2013, Critical Link LLC
Specifications Subject to Change
Critical Link, LLC
www.criticallink.com
MitySOM
MitySOM-1810 Processor Card
5-MAR-2014
MECHANICAL INTERFACE
A mechanical outline of the MitySOM-1810 is illustrated in Figure 2, below.
Figure 2 MitySOM-1810 Mechanical Outline
REVISION HISTORY
Date
7-NOV-2010
20-NOV-2010
7-JAN-2011
12-JUL-2011
11-DEC-2012
27-MAR-2013
5-MAR-2014
Change Description
Preliminary Draft, product overview
Updates after initial review.
Add SO-DIMM pinout table.
Update NAND to indicate 8 bit data width. Update block
diagram accordingly.
Update Debug Header information, added MIL-STD-810F and
Up To notation for RAM and NAND
Added AM1810 processor pins with notes about on module
resistors for specific pins as well as the OSCIN frequency.
Update MitySOM product name.
12
Copyright © 2013, Critical Link LLC
Specifications Subject to Change
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