Critical Link, LLC
www.CriticalLink.com
www.MityDSP.com
MityDSP-Pro
MityDSP-Pro Processor Card
13 March 2012
FEATURES
TI TMS320C645x DSP
- 720 MHz, 1 GHz, & 1.2 GHz
options
- 1 MB cache or 2 MB cache
options
- Integrated 10/100/1000 EMAC
- 2 Integrated McBSPs
- JTAG Emulation/Debug
On-Board Xilinx Spartan3 FPGA
- XC3S2000 & XC3S4000 options
- 300 MHz Clock Logic
- JTAG Interface/Debug
On-Board 10/100 Ethernet PHY
connected to DSP’s EMAC
128 MB CPU DDR2 SDRAM
64 MB FPGA DDR1 SDRAM
16 MB NOR FLASH
SO-DIMM-200 Interface
- 140 FPGA User I/O Pins
- 2 McBSP Interfaces
- I2C Interface
- 10/100 Ethernet Interface
- 3.3V Power Interface
Expansion I/O Connector
- DSP Rapid IO Interface
- DSP PCI I/O Interface
- DSP Gigabit Ethernet Interface
(RGMII) to an external PHY
APPLICATIONS
Embedded Instrumentation
Rapid Development / Deployment
Embedded Digital Signal Processing
Real-time Audio / Video Processing
(3.25” x 2.7” - actual size)
DESCRIPTION
The MityDSP-Pro is a highly configurable, high performance, small form-factor
processor card that features a Texas Instruments TMS320C645x Digital Signal Processor
(DSP) tightly integrated with a Xilinx Spartan3 Field Programmable Gate Array (FPGA),
FLASH and DDR1/DDR2 SDRAM memory subsystems. Both the DSP and the FGPA
are capable of loading/executing programs and logic images developed by end users. The
MityDSP-Pro provides a complete digital processing infrastructure necessary for
embedded applications development.
Users of the MityDSP-Pro are encouraged to develop applications and FPGA firmware
using the MityDSP hardware and software development kit provided by Critical Link.
The development kit includes API libraries compatible with the TI Code Composer
Studio compiler as well as FPGA netlist components compatible with the Xilinx ISE
FPGA synthesis/implementation tools. The libraries provide the necessary functions
needed to configure the MityDSP-Pro, program standalone MityDSP embedded
applications, and interface with the various hardware components on the board. In
addition, the libraries include several interface “cores” – FPGA and DSP software
1
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MityDSP-Pro Processor Card
13 March 2012
modules designed to interface with various data converter modules (ADCs, DACs, LCD
interfaces, etc) – as well as bootloading and FLASH programming utilities.
Figure 1 provides a top-level block diagram of the MityDSP-Pro processor card. As
shown in the figure, the primary interface to the MityDSP-Pro is through a standard SODIMM-200 card edge interface. The interface provides 3.3V power, configuration
control, Ethernet connectivity, inter-integrated circuit (I2C) connectivity, synchronous
serial connectivity, and 140 pins of configurable FPGA I/O for application-defined
interfacing. Details of the SO-DIMM connector interface are included in the SO-DIMM200 Interface Description, below.
Debug
Header
Gigabit Ethernet RGMII
50 MHz
Clock
JTAG/Emulator
NOR
Flash
16 MB
JTAG
HPI / PCI
Rapid I/O
4 pair Tx/Rx
(6455 Option)
Expansion Header
Board
Identity
Bank
Control
CE3
DDR2
128MB
32-bit wide
Texas Instruments
TMS320C645x
DSP
EMIF (32-bit)
Xilinx
Spartan 3
FPGA
CE2,CE4,CE5
DDR
64 MB
16-bit wide
INT4, INT5, INT6
1.2
1.5
1.8
2.5
Power
Regulation
GND
3.3 V
Bank 7 I/O
Bank 2 I/O
Bank 1 I/O
3.3
Bank 0 I/O
Bank 7 3.3V
Bank 2 3.3V
Bank 0 3.3V
McBSP 2
I2C
Bank 1 3.3V
FPGA
Bank
3.3V
Power
Boot
Config
Logic
McBSP 1
10/100
Ethernet
PHY
MII/MDIO
Interface
SO-DIMM-200
Figure 1: MityDSP-Pro Block Diagram
2
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MityDSP-Pro
MityDSP-Pro Processor Card
13 March 2012
FPGA Bank I/O
The MityDSP-Pro provides 140 lines of FPGA I/O directly to the SO-DIMM-200 card
edge interface. The 140 lines of FPGA I/O are distributed across 4 banks of the FPGA.
These I/O lines and their associated logic are completely configurable within the FPGA.
With the Xilinx Spartan3 family of FPGA, each bank may be configured to operate on a
different electrical interface standard based on input voltage and termination
configurations. The MityDSP-Pro provides, for each of the four externally accessible
FPGA banks, a power supply pin (VCCO_N) to allow the bank to be powered to 2.5V or
3.3V. The following table outlines the various electrical interface standards that are
possible on the MityDSP-Pro:
Table 1: MityDSP-Pro FPGA Available I/O Standards
I/O Standard
2.5V LVDS with 100 ohm DCI termation
2.5V LVDS without DCI termination
2.5V CMOS (pull-up/down options in FPGA)
3.3V CMOS (pull-up/down options in FPGA)
Bank Voltage
2.5V
2.5V
2.5V
3.3V
VCCO_N pin
Open or 2.5V supply
Open or 2.5V supply
Open or 2.5V supply
3.3V supply
For complete details regarding hardware bank voltage configuration please refer to the
SO-DIMM-200 Interface description and the appropriate Spartan3 manuals from Xilinx.
Integrated DSP Communications Modules
The C6454 processor includes several on-chip communications modules. The MityDSPPro design provides access to the several of the modules through the SO-DIMM-200 card
edge interface.
The Ethernet MAC MII/MDIO interface on the DSP has been integrated with an onboard Ethernet PHY device. The Tx/Rx line-level signals of the PHY device are brought
to the SO-DIMM-200 connector. In order to leverage the Ethernet interface, application
boards need only supply appropriate Ethernet magnetics, and the RJ-45 Ethernet
connector, which are often available as a single component. The MityDSP software
developer’s kit includes a software driver and port of the LwIP TCP/IP protocol stack for
use with the Ethernet interface.
The DSP’s Gigabit Ethernet capability is accessible via the expansion I/O connector on
the bottom side of the MityDSP-Pro module. The EMAC’s Reduced Gigabit Medium
Independent Interface (RGMII) is available on this connector for connection to a PHY
device on the end application board. The signals are separate from the MII signals routed
to the on-board 10/100 PHY. Although the same EMAC module within the DSP services
both sets of signals, only one Ethernet interface can be used at a time.
The inter-integrated circuit (I2C) signals have been routed between the DSP, FPGA, and
the SO-DIMM-200 interface. Communication is allowed between any combination of
DSP, FPGA, and user board devices. TI provides several I2C interface libraries for
3
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MityDSP-Pro Processor Card
13 March 2012
integration with various data acquisition modules. The MityDSP development kit also
contains modules for implementing I2C communication using the FPGA connection. In
addition, the I2C interface may be used to boot the DSP processor (see the SO-DIMM200 interface description for details on MityDSP-Pro boot configuration).
The DSP also includes two multi-channel buffered serial ports (McBSPs) which have
been routed directly to the SO-DIMM-200 interface. Both Critical Link (as part of the
MityDSP development kit) and TI provide several McBSP interface libraries for
integration with various data acquisition modules.
EMIF Interface
The C645x DSP and the Spartan3 FPGA are connected using the DSP External Memory
Interface (EMIFA). The EMIFA interface includes 4 chip-select spaces. The EMIFA
interface supports multiple data width transfers and bus wait state configurations based
on chip select space. 8, 16, 32, and 64 bit data word sizes may be used. Three of the four
chip-select lines are reserved for the FPGA interface. The MityDSP-Pro also includes
lines between the FPGA and the DSP for the purposes of generating interrupts.
In addition to the FPGA, 16 MB of on-board NOR FLASH memory is also connected to
the DSP using the EMIF. The FLASH memory is connected to fourth chip-select line of
the EMIF (CE3). The FLASH memory is typically used to store the following types of
data:
secondary bootloader DSP software
secondary bootloader FPGA image
application DSP software
application FPGA images
application data (non-volatile storage)
The DSP EMIF interface is only capable of addressing 4 MB of data on the EMIF
interface. In order to provide access to the remaining 12 MB of FLASH memory, the
upper address lines of the FLASH are controlled by Bank Control logic. Upon reset the
Bank Control Logic defaults to bank zero for bootloading support. Following
bootloading, the bank control logic is controlled by the FPGA. Refer to the MityDSP
User’s Guide for more information on bank control logic.
System Memory
The C6454 includes a 32 KB level-1 program (L1P) cache/SRAM, a 32 KB level-1 data
(L1D) cache/SRAM, and a 1 MB level-2 (L2) cache/SRAM. The C6455 doubles the L2
cache/SRAM to 2MB. All types of cache/SRAM may be split into various amounts of
cache and SRAM. Refer to TI’s datasheets for specific details on configuring the
cache/SRAM memory blocks.
For main DSP software program and runtime data storage, a dedicated 128 MB of DDR2
memory is available via the DDR2 control interface on the DSP. The memory is 32 bits
4
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MityDSP-Pro Processor Card
13 March 2012
wide and is capable of running at 250 MHz providing a burst throughput of 2 GB per
second to the processor.
For the FPGA, a separate 64 MB of DDR1 memory is provided. The memory interface is
16 bits wide and is capable of running at 125 MHz providing a burst throughput of 500
MB per second to the FPGA. Common uses for the FPGA memory include custom data
collection systems, video frame buffers, and MicroBlaze program storage.
Debug Interface
Both the JTAG interface signals for the FPGA and the JTAG and emulator signals for the
C645x processor have been brought out to a connector/header for use with in-circuit
debugging. The JTAG chains are separate on the interface. With an appropriate breakout
cable, the interface will support the use of standard Xilinx Platform JTAG cable
programming and the Spectrum Digital processor emulator (or equivalent). Details of
the pin-outs for the debug header are included in the Debug Interface Description below.
Expansion Interface
For system expansion, the MityDSP-Pro also provides a low profile Hirose FX8-100SSV connector interface that may be used to access the Host-Port-Interface (HPI),
Peripheral-Component-Interconnect (PCI), and Gigabit Ethernet MAC ports of the C645x
bus. In addition, four lanes of transmit and receive Rapid I/O data lines (and associated
clocks) are also provided with the C6455 processor option.
Module Options
The MityDSP-Pro has been designed to support several upgrade options. These include a
selection of 3 CPU speeds with a combination of 2 FPGA types. If you do not see a
combination in Table 6 that meets your needs please contact a Critical Link sales
representative.
5
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MityDSP-Pro Processor Card
13 March 2012
Example Application
The figure below illustrates an example application utilizing the MityDSP-Pro processor
card. The example application is a 6-way signal beamformer for use in a radar system.
The card is required to capture 6 channels of IF signal data, downconvert the data to
baseband, sum the signals together with the input channels and data provided from
upstream processors, and send the results to downstream processing.
Embedded Application Card (Hex-Beam Former)
Strobes / Timing
60 Msps
60 Msps
60
Msps
ADC,
14 bit
60
Msps
ADC,
14 bit
60
ADC,
Msps
14 bit
60
ADC,
Msps
14 bit
ADC, 14 bit
ADC, 14 bit
Status
Indicators
IF Data
5
Debug
USB-B
7
84
USB
PHY
Signal
Signal
Signal
Conditioning
Signal
Conditioning
Conditioning
Signal
Conditioning
Signal
Conditioning
Conditioning
10
LVDS Output, Baseband to Downstream processors
10
LVDS Input, Baseband from Upstream Processors
MityDSP-Pro
Control
RJ-45
24 Bit
5 sps ADC
(McBSP)
Ethernet
Magnetics
Temperature
Sensors
Figure 2: Typical MityDSP-Pro Application
In the example application, a designer leverages three of the four FPGA I/O banks as
3.3V CMOS interface and is able to integrate 6 14-bit ADC circuits directly to the
MityDSP-Pro FPGA as well as various strobe signals and status indicators. The fourth
bank is reserved for LVDS signaling and is used to receive and transmit data from
upstream and downstream processors.
The user is able to utilize the McBSP interface of the MityDSP-Pro to capture on-board
temperature data for health monitoring. In addition, an Ethernet interface and a USB
interface are added to provide debug and status and control information to external
control units.
Within the MityDSP-Pro, the user is able to utilize the FPGA multiply accumulator
engines and programmable logic to capture, baseband, and integrate each of the ADC
channels on the main board. The TI processor can be used to compute complex
coefficients used in the beamforming process and provide the command and control
interface for the entire card.
With the application, the user needs only focus on the details of the application specific
problems at hand: e.g., developing the appropriate signal conditioning and application
software and firmware. The framework for the processing and interconnects is
completely designed with the integration of the MityDSP-Pro.
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MityDSP-Pro Processor Card
13 March 2012
ABSOLUTE MAXIMUM RATINGS
OPERATING CONDITIONS
If Military/Aerospace specified cards are
required, please contact the Critical Link
Sales Office or unit Distributors for
availability and specifications.
Commercial
Temperature Range
Industrial Temperature
Range
Humidity
Maximum Supply Voltage, Vcc
Storage Temperature Range
Shock, Z-Axis
Shock, X/Y-Axis
3.4 V
0 to 70C
-40 to +85C
0 to 95%
Non-condensing
-65 to 80C
±10 g
±10 g
ELECTRICAL CHARACTERISTICS
Symbol
Vcc
Icc
Icc-max
Parameter
Conditions
Voltage supply, 3.3 volt input.
Quiescent Current draw, 3.3 volt input
Max current draw, positive 3.3 volt input.
Min
Typ
Max
Units
3.3
1.5
1.7
3.4
3
3.5
Volts
Amps
Amps
10
0
TBD
KHz
Volts
Volts
Clock Frequency, Digital Inputs
Update period, digital inputs
Clock Frequency, Digital Output LVDS
clk entering deserializer
Update period, digital outputs
1.
25
1280
50
25
1280
20 / 68
MHz
ns
MHz
20
14.7 /
50
ns
Power utilization of the MityDSP-Pro is heavily dependant on end-user application. Major
factors include: CPU PLL configuration, FPGA utilization, and external SDRAM utilization.
SO-DIMM-200 Interface Description
The primary interface connector for the MityDSP-Pro is the SO-DIMM-200 card edge
interface. Table 2 lists every pin on the SO-DIMM-200 main interface connector. Table
3 describes the function of each group of signals on the main interface connector.
7
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Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
MityDSP-Pro
MityDSP-Pro Processor Card
13 March 2012
Table 2: SO-DIMM-200 Pin-Out
Signal
FPGA Bank
Signal
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
GND
GND
GND
GND
MRESET#
BOOT_MODE
ETH_TD_P
RS232_TXD
ETH_TD_N
RS232_RXD
ETH_RD_P
RS232_RTS
ETH_RD_N
RS232_CTS
FPGA_RSV1
SCL
FPGA_RSV2
SDA
CLKR0
CLKR1
CLKX0
CLKX1
DR0
DR1
DX0
DX1
FSR0
FSR1
FSX0
FSX1
VCCO_2
VCCO_1
VCCO_0
VCCO_7
GND
GND
ODD1_P.N26
2
EVN1_P.N22
ODD1_N.N25
2
EVN1_N.N21
ODD2_P.M26
2
EVN2_P.N24
ODD2_N.M25
2
EVN2_N.N23
ODD3_P.M22
2
EVN3_P.M24
ODD3_N.M21
2
EVN3_N.L23
ODD4_P.L26
2
EVN4_P.K24
ODD4_N.L25
2
EVN4_N.K23
ODD5_P.K26
2
EVN5_P.J25
ODD5_N.K25
2
EVN5_N.J24
GND
GND
ODD6_P.K22
2
EVN6_P.H24
ODD6_N.K21
2
EVN6_N.H23
ODD7_P.H26
2
EVN7_P.J23
ODD7_N.H25
2
EVN7_N.J22
ODD8_P.J21
2
EVN8_P.H21
ODD8_N.H22
2
EVN8_N.H20
ODD9_P.D26
2
EVN9_P.E24
ODD9_N.D25
2
EVN9_N.E23
ODD10_P.F21
1
EVN10_P.C23
ODD10_N.E21
1
EVN10_N.B23
GND
GND
ODD11_P.E20
1
EVN11_P.C22
ODD11_N.D20
1
EVN11_N.B22
ODD12_P.B21
1
EVN12_P.D21
ODD12_N.A21
1
EVN12_N.C21
ODD13_P.B20
1
EVN13_P.G18
ODD13_N.A20
1
EVN13_N.F18
ODD14_P.B19
1
EVN14_P.G17
8
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
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Pin
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
MityDSP-Pro
MityDSP-Pro Processor Card
13 March 2012
Signal
ODD14_N.A19
ODD15_P.F16
ODD15_N.E16
GND
ODD16_P.B15
ODD16_N.A15
ODD17_P.C14
ODD17_N.B14
ODD18_P.A13
ODD18_N.B13
ODD19_P.A12
ODD19_N.B12
ODD20_P.H13
ODD20_N.G12
GND
ODD21_P.F11
ODD21_N.G11
ODD22_P.A8
ODD22_N.B8
ODD23_P.A7
ODD23_N.B7
ODD24_P.D7
ODD24_N.E7
ODD25_P.D6
ODD25_N.E6
GND
ODD26_P.A4
ODD26_N.B4
ODD27_P.D2
ODD27_N.D1
ODD28_P.H5
ODD28_N.J6
ODD29_P.K6
ODD29_N.K5
ODD30_P.G2
ODD30_N.G1
GND
ODD31_P.H2
ODD31_N.H1
ODD32_P.K2
ODD32_N.K1
ODD33_P.L2
ODD33_N.L1
ODD34_P.M2
ODD34_N.M1
ODD35_P.N2
ODD35_N.N1
GND
3.3V
3.3V
FPGA Bank
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
-
9
Signal
EVN14_N.F17
EVN15_P.E17
EVN15_N.D17
GND
EVN16_P.F15
EVN16_N.E15
EVN17_P.E14
EVN17_N.D14
EVN18_P.F13
EVN18_N.G13
EVN19_P.C13
EVN19_N.D13
EVN20_P.E12
EVN20_N.F12
GND
EVN21_P.D11
EVN21_N.E11
EVN22_P.C10
EVN22_N.D10
EVN23_P.E10
EVN23_N.F10
EVN24_P.F9
EVN24_N.G9
EVN25_P.B6
EVN25_N.C6
GND
EVN26_P.B5
EVN26_N.C5
EVN27_P.J5
EVN27_N.J4
EVN28_P.H4
EVN28_N.H3
EVN29_P.J3
EVN29_N.J2
EVN30_P.K4
EVN30_N.K3
GND
EVN31_P.L6
EVN31_N.L5
EVN32_P.M5
EVN32_N.M6
EVN33_P.L4
EVN33_N.M3
EVN34_P.N4
EVN34_N.N3
EVN35_P.N6
EVN35_N.N5
GND
3.3V
3.3V
Pin
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
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13 March 2012
Table 3: Signal Group Description
Signal / Group
3.3 V
MRESET#
I/O
N/A
I
ETH_TD_P / N
ETH_RD_P / N
O
I
FPGA_RSV1 / 2
IO
CLKR0 / 1
CLKX0 / 1
DR0 / 1
DX0 / 1
FSR0 / 1
BOOT_MODE
IO
SCL, SDA
I/O
GND
ODDXX_P/N.YYY
EVNXX_P/N.YYY
N/A
IO
VCCO_N
N/A
I
Description
3.3 volt reference input power referenced to GND.
Manual Reset. Pulled-up on the MityDSP-Pro
module. When driven to GND for a minimum of
1 us, a module-wide reset is triggered. Can be tied
into system system-wide reset and power
monitoring circuitry.
Ethernet Transmit Data & Receive Data link lines.
These pairs of signals are connected to the
onboard 10/100 Ethernet PHY connected to the
DSP EMAC. These pairs should be routed
through appropriate 1:1 magnetics prior to
exposure to an RJ-45 type connector interface.
Reserved for Ethernet RJ45 Link & Activity LED
signals, driven by the on-board 10/100 PHY. Can
also be used as general purpose FPGA I/O.
These pins are direct connects to the
corresponding McBSP port-0 / port-1 pins on the
C645x DSP. For further interface information,
please refer to the TMS645x McBSP Users Guide
and Data Sheets.
Boot Mode Selection. Reserved for future use.
Do not connect.
These pins are connected to the I2C interface on
the C645x DSP, and also to FPGA pins. For
further interface information, please refer to the
TMS320C645x I2C Users Guide and Data Sheets.
System Digital Ground.
FPGA General Purpose I/O pin. FPGA I/O pins
have been routed to the MityDSP connector in
pairs denoted ODDXX (odd pin side of connector)
or EVNXX (even pin side of connector). When
configured for differential termination the pairs
should be used according to the _P (positive) or
_N (negative) extension. The YYY portion of the
name corresponds to the FPGA pin location
mapped to the signal.
FPGA Banks 0, 1, 2, and 7 Voltage configuration.
Leave disconnected for 2.5V bank logic
(LVCMOS25 or LVDS25). Connect to 3.3V
power supply for 3.3V bank logic (LVCMOS33 or
LVTTL). PCB trace must be capable of providing
a minimum of 200 mA.
10
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Debug Interface Description
The debug interface connector pin-out is specified in the table below.
Table 4: Debug Connector Pin-Out
Pin Signal
Signal
Pin
1
DSP_EMU0 DSP_TMS
2
3
DSP_EMU1 DSP_TDI
4
5
3.3V
DSP_TDO
6
7
GND
DSP_TCK
8
9
GND
DSP_TRST# 10
11 FPGA_TDI FPGA_TMS 12
13 FPGA_TCK FPGA_TDO 14
15 GND
2.5V
16
Expansion Interface Description
The Expansion Interface pin-out is described in the table below.
Table 5: Expansion Interface Pin-Out
Pin
Signal
Signal
Pin
1
GND
GND
2
3
RIORX0_N
RIOTX0_P
4
5
RIORX0_P
RIOTX0_N
6
7
RIORX1_P
RIOTX1_P
8
9
RIORX1_N
RIOTX1_N
10
11 RIORX2_N
RIOTX2_N
12
13 RIORX2_P
RIOTX2_P
14
15 RIORX3_P
RIOTX3_N
16
17 RIORX3_N
RIOTX3_P
18
19 RIOCLK_N
GND
20
21 RIOCLK_P
HPI_WIDTH
22
23 GND
PCI_AD27
24
25 PCI_EEAI
PCI_AD1
26
27 PCI66
PCI_AD30
28
29 PCI_EN
PCI_AD0
30
31 PCI_AD11
PCI_AD4
32
33 PCI_AD10
PCI_AD22
34
35 PCI_AD3
PCI_AD25
36
37 PCI_AD5
PCI_AD8
38
39 PCI_AD29
PCI_AD21
40
41 PCI_AD23
PCI_AD13
42
43 PCI_AD7
PCI_AD2
44
45 PCI_AD9
PCI_AD19
46
47 PCI_AD28
PCI_AD15
48
49 PCI_AD31
PCI_ERR#
50
51 PCI_AD16
PCI_AD17
52
53 PCI_AD6
PCI_AD18
54
55 PCI_AD14
PCI_STOP#
56
57 GND
PCI_AD26
58
59 PCI_CLK
PCI_AD20
60
61 GND
PCI_CBE2#
62
11
Copyright © 2007-2012, Critical Link LLC
Critical Link, LLC
www.CriticalLink.com
www.MityDSP.com
MityDSP-Pro
MityDSP-Pro Processor Card
13 March 2012
Pin
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
Signal
PCI_AD12
PCI_FRAME#
PCI_DEVSEL#
PCI_PAR
PCI_IDSEL
PCI_IRDY#
PCI_GNT#
PCI_INTA#
PCI_TRDY#
GND
RGMDCLK
RGMDIO
RGRXD3
RGRXD2
RGRXD1
RGRXD0
RGRXCTL
RGRXC
GND
12
Signal
PCI_AD24
PCI_SERR#
PCI_RST#
PCI_CBE1#
PCI_CBE0#
PCI_CBE3#
PCI_REQ#
MAC_SEL
RGMII_VREF
GND
RGREFCLK
GND
RGTXD3
RGTXD2
RGTXD1
RGTXD0
RGTXCTL
RGTXC
GND
Pin
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
Copyright © 2007-2012, Critical Link LLC
Critical Link, LLC
www.CriticalLink.com
www.MityDSP.com
MityDSP-Pro
MityDSP-Pro Processor Card
13 March 2012
ORDERING INFORMATION
The following table lists the orderable module configurations. For shipping status,
availability, and lead time of these or other configurations please contact your Critical
Link representative.
Model
CPU
Speed
6455-JE-3X5-RC
6455-IE-3X5-RI
6454-GD-3X5-RC
6454-ID-3X5-RI
1.2 GHz
1.0 GHz
720 MHz
1.0 GHz
Table 6: Orderable Model Numbers
L2
NOR CPU DDR2
FPGA
CPU
Flash
RAM
Cache
XC3S4000
2 MB
16MB
128MB
XC3S4000
2 MB
16MB
128MB
XC3S2000
1 MB
16MB
128MB
XC3S2000
1 MB
16MB
128MB
FPGA
DDR1 RAM
Operating
Temp
64MB
64MB
64MB
64MB
0oC to 70o C
-40oC to 85o C
0oC to 70o C
-40oC to 85o C
MECHANICAL INTERFACE
A mechanical outline of the MityDSP-Pro is illustrated below.
Figure 3: Dimensions 3.25" x 2.7"
13
Copyright © 2007-2012, Critical Link LLC
Critical Link, LLC
www.CriticalLink.com
www.MityDSP.com
MityDSP-Pro
MityDSP-Pro Processor Card
13 March 2012
REVISION HISTORY
Date
13-MAR-2012
Change Description
Update available model numbers and add rev history
14
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