Critical Link, LLC
www.CriticalLink.com
MityDSP-L138F System on Module
3-AUG-2022
FEATURES
• TI OMAP-L138 Dual Core Application
Processor
-
456 MHz (Max) C674x VLIW DSP
▪ Floating Point DSP
▪ 32 KB L1 Program Cache
▪ 32 KB L1 Data Cache
▪ 256 KB L2 cache
▪ 1024 KB boot ROM
▪ JTAG Emulation/Debug (option)
-
456 MHz (Max) ARM926EJ-S MPU
▪ 16 KB L1 Program Cache
▪ 16 KB L1 Data Cache
▪ 8 KB Internal RAM
▪ 64 KB boot ROM
▪ JTAG Emulation/Debug (option)
•
On-Board Xilinx Spartan-6 FPGA
- Up To XC6SLX45
▪ Up To 2,088 KBits Block RAM
▪ Up To 6,822 Slices (6 Input LUTs)
- 1050 Mbps data rate
- JTAG Interface/Debug (option)
•
•
•
•
•
Up To 256 MB mDDR2 CPU RAM
Up To 512 MB Parallel NAND FLASH
Up to 16 MB SPI based NOR FLASH
Integrated Power Management
Standard SO-DIMM-200 Interface
- 96 FPGA User I/O Pins
- 10/100 EMAC MII / MDIO
- 2 UARTS
- 2 McBSPs
- 2 USB Ports
- Video Output
- Camera/Video Input
- MMC/SD
- SATA Support (option)
- Single 3.3V Power Supply
(actual size)
APPLICATIONS
• Embedded Instrumentation
• Industrial Automation
• Industrial Instrumentation
• Medical Instrumentation
• Embedded Control Processing
• Network Enabled Data Acquisition
• Test and Measurement
• Software Defined Radio
• Bar Code Scanners
• Power Protection Systems
• Portable Data Terminals
BENEFITS
• Rapid Development / Deployment
• Multiple Connectivity and Interface Options
• Rich User Interfaces
• High System Integration
• Fixed & Floating Point Operations in Single
CPU
• High Level OS Support
- Linux
- QNX 6.4
- Windows Embedded CE Ready
- ThreadX Real Time OS
• Embedded Digital Signal Processing
DESCRIPTION
The MityDSP-L138F is a highly configurable, very small form-factor processor card that
features a Texas Instruments OMAP-L138 456 MHz (max) Applications Processor
(OMAP) tightly integrated with the Xilinx Spartan-6 Field Programmable Gate Array
(FPGA), FLASH (NAND, and NOR) and mDDR2 RAM memory subsystems. The
design of the MityDSP-L138F allows end users the capability to develop programs/logic
images for both the OMAP and the FGPA. The MityDSP-L138F provides a complete and
flexible digital processing infrastructure necessary for the most demanding embedded
applications development.
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Copyright © 2022, Critical Link LLC
Specifications Subject to Change
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Critical Link, LLC
www.CriticalLink.com
MityDSP-L138F System on Module
3-AUG-2022
The onboard OMAP-L138 processor provides a dual CPU core topology. The OMAPL138 includes an ARM926EJ-S micro-processor unit (MPU) capable of running the rich
software applications programmer interfaces (APIs) expected by modern system
designers. The ARM architecture supports several operating systems, including Linux
and Windows Embedded CE. In addition to the ARM core, the OMAP-L138 also
includes a TMS320C674x floating point digital signal processing (DSP) core. The DSP
core supports the freely provided TI DSP/BIOS real-time kernel. Users can leverage the
DSP to execute real-time compute algorithms (codecs, image/data processing,
compression techniques, filtering, etc.).
Up to 16MB
NOR Flash
(SPI interface)
For uBoot
bootloader
Up to 512MB
NAND Flash
16-bit wide
For root FFS
1.2V
1.8V
2.5V
Power
Management
3.3V
EMIFA (16-bit)
System
Clocks
JTAG/Emulator
JTAG
MMCSD 1
uPP
LCD
(Many pins are multiplexed between peripherals)
Xilinx
Spartan-6
FPGA
XC6SLX16
CSG324 pkg.
VPIF I/O
Programmable I/O
I/O Bank Power
Boot Config
Resets & RTC
SATA
USB 0,1
Timers
eCAP
eHRPWM
I2C 0,1
McASP
SPI 0,1
McBSP 0,1
MMCSD 0
UART 0,1,2
EMAC MII/MDIO
Boot
Config
FPGA I/O
Banks can be
1.8V, 2.5V, or
3.3V
GND
UHPI
3.3 V
EMAC RMII
Programmable I/O
Texas Instruments
OMAP-L138
450-MHz ARM926EJ-S ™ RISC MPU
450-MHz C674x VLIW DSP
Optional
JTAG
Header
I/O Bank Power
Up to 256MB
mDDR Memory
16-bit wide
SO-DIMM-200 (DDR2 Connector)
Figure 1 MityDSP-L138F Block Diagram
Figure 1 provides a top level block diagram of the MityDSP-L138F processor card. As
shown in the figure, the primary interface to the MityDSP-L138F is through a standard
SO-DIMM-200 card edge interface. The interface provides power, synchronous serial
connectivity, and up to 96 pins of configurable FPGA I/O for application defined
interfacing. Details of the SO-DIMM-200 connector interface are included in the SODIMM-200 Interface Description, as shown below.
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Copyright © 2022, Critical Link LLC
Specifications Subject to Change
60-000037-1C
Critical Link, LLC
www.CriticalLink.com
MityDSP-L138F System on Module
3-AUG-2022
FPGA Bank I/O
The MityDSP-L138F provides 96 lines of FPGA I/O directly to the SO-DIMM-200 card
edge interface. The 96 lines of FPGA I/O are distributed across 2 banks of the FPGA.
These I/O lines and their associated logic are completely configurable within the FPGA
at the end user’s discretion.
With the Xilinx Spartan-6 series FPGA, up to the XC6SLX45, each of the user controlled
banks may be configured to operate on a different electrical interface standard based on
input voltage provided at the card edge connector. The banks support 3.3V, 2.5V, and
1.8V standard CMOS switching level technology. In addition, the I/O lines from the
FPGA have been routed as differential pairs and support higher speed LVDS standards as
well as SSTL 2.5 switching standards. Various forms of termination (pull-up/pull-down,
digitally controlled impedance matching) are available within the FPGA switch fabric.
Refer to the Xilinx Spartan 6 user’s guide for more information.
OMAP-L138 mDDR2 Memory Interface
The OMAP-L138 includes a dedicated DDR2 SDRAM memory interface shared between
the onboard ARM and DSP cores. The MityDSP-L138F includes up to 256 MB of
mDDR2 RAM integrated with the OMAP-L138 processor. The bus interface is capable
of burst transfer rates of 600 MB / second. Note that the OSCIN frequency to the OMAPL138 processor on the module is 24MHz.
OMAP-L138 SPI NOR FLASH Interface
The MityDSP-L138F includes up to 16 MB of SPI NOR FLASH. This FLASH memory
is intended to store a factory provided bootloader, and typically a compressed image of a
Linux kernel for the ARM core processor.
EMIFA - FPGA / NAND FLASH Interface
The OMAP-L138 and the Spartan-6 FPGA are connected using the DSP Asynchronous
External Memory Interface (EMIFA). The EMIFA interface includes 3 chip select
spaces. The EMIF interface supports multiple data width transfers and bus wait state
configurations based on chip select space. 8, and 16 bit data word sizes may be used.
Two of the three chip select lines (CE2, CE3) are reserved for the FPGA interface. The
MityDSP-L138F also includes 4 lines between the FPGA and the OMAP for the purposes
of generating interrupt signals.
In addition to the FPGA, up to 512 MB of on-board NAND FLASH memory is
connected to the OMAP-L138 using the EMIFA bus. The FLASH memory is 8 bits wide
and is connected to third chip select line of the EMIFA (CE1). The FLASH memory is
typically used to store the following types of data:
-
ARM Linux / Windows Embedded CE / QNX embedded root file-system
FPGA application images
runtime DSP or ARM software
runtime application data (non-volatile storage)
3
Copyright © 2022, Critical Link LLC
Specifications Subject to Change
60-000037-1C
Critical Link, LLC
www.CriticalLink.com
MityDSP-L138F System on Module
3-AUG-2022
OMAP-L138 Camera and Video Interfaces
The OMAP-L138 includes an optional video port I/O interface commonly used to drive
LCD screens as well as a camera input interface. These interfaces have been routed to
the FPGA, which may be routed to the FPGA output pins on the SO-DIMM-200
connector. By routing the video data through the FPGA, additional user customization
and/or processing (e.g., overlays of video output, preprocessing or filtering of camera
input) may be offloaded from the OMAP-L138 to the FPGA for computation intensive
applications.
OMAP-L138 RTC
The OMAP-L138 features an integrated real-time clock, RTC. MityDSP-L138F modules
have a 32.768KHz tuning fork crystal connected to RTC XI & RTC XO of the OMAPL138 to support the RTC functionality. Additionally there is a battery input, module Pin
35, which will power the RTC when the module is off, if utilized. Please visit our
Redmine Wiki pages at support.criticallink.com for additional details about the RTC
feature.
Debug Interface
Both the JTAG interface signals for the FPGA and the JTAG and emulator signals for the
OMAP-L138 processor have been brought out to a Hirose header that is intended for use
with an available breakout adapter, Critical Link part number 80-000286. This header is
not installed on standard models. To order a module with the Hirose header installed, an
option code must be provided with the order. Please contact Critical Link at
info@criticallink.com for details.
The breakout adapter, 80-000286, is not included with individual modules but is included
with each Critical Link Development Kit that is ordered. Additional adapters are
available through Critical Link distribution partners.
Software and Application Development Support
Users of the MityDSP-L138F are encouraged to develop applications and FPGA
firmware using the hardware and software development kit provided by Critical Link.
The development kit includes a board support package providing a Linux based
distribution and compatible gcc compiler tool-chain with debugger. In addition, the
development kit includes support libraries necessary to program the DSP core using the
TI Code Composer Studio DSP compiler tool-chain.
To support rapid FPGA and applications development, netlist components - compatible
with the Xilinx ISE FPGA synthesis tool – for commonly used FPGA designs and a
corresponding set of Linux loadable kernel modules and/or DSP interface APIs are
included.
The libraries provide the necessary functions needed to configure the
MityDSP-L138F, program standalone embedded applications, and interface with the
various hardware components both on the processor board as well as a custom
application carrier card. The libraries include several interface “cores” – FPGA and DSP
software modules designed to interface with various high performance data converter
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Copyright © 2022, Critical Link LLC
Specifications Subject to Change
60-000037-1C
Critical Link, LLC
www.CriticalLink.com
MityDSP-L138F System on Module
3-AUG-2022
modules (ADCs, DACs, LCD and touchscreen interfaces, etc) – as well as bootloading
and FLASH programming utilities.
Growth Options
The MityDSP-L138F has been designed to support several upgrade options. These
options include various speed grades, memory configurations, and operating temperature
specifications including commercial and industrial temperature ranges. The available
options are listed in the section below containing ordering information. For additional
ordering information and details regarding these options, or to inquire about a particular
configuration not listed below, please contact Critical Link at info@criticallink.com.
ABSOLUTE MAXIMUM RATINGS
Maximum Supply Voltage, Vcc
Storage Temperature Range
Shock, Z-Axis
Shock, X/Y-Axis
OPERATING CONDITIONS
3.5 V
o
0oC to 70oC
Ambient Temperature
Range Commercial
Ambient Temperature
Range Industrial
Humidity
o
-65 C to 80 C
±10 g
±10 g
-40oC to 85oC
0 to 95%
Non-condensing
Contact Critical
Link for Details
MIL-STD-810F
SO-DIMM-200 Interface Description
The primary interface connector for the MityDSP-L138F is the SO-DIMM card edge
interface which contains 4 types of signals:
•
•
•
•
Power (PWR)
Dedicated signals mapped to the OMAP-L138 device (D)
Multi-function signals mapped to the OMAP-L138 device (M)
Dedicated signals mapped to the Xilinx Spartan 6 device (F)
Table 1 contains a summary of the MityDSP-L138F pin mapping.
Pin
1
3
5
7
9
11
135
155
175
Ball
K14
J1
J2
L1
Type
PWR
PWR
PWR
PWR
PWR
D
D
D
D
I/O
I
O
O
I
Table 1 SO-DIMM Pin-Out
Signal
Pin
Ball Type
+3.3 V in
2
PWR
+3.3 V in
4
PWR
+3.3 V in
6
PWR
GND
8
PWR
GND
10
PWR
RESET_IN#
12
D
SATA_TX_P
14
A4
M
SATA_TX_N
16
A3
M
SATA_RX_P
18
A2
M
5
I/O
I/O
I/O
I/O
Signal
+3.3 V in
+3.3 V in
+3.3 V in
GND
GND
EXT_BOOT#
GP0_7
GP0_10
GP0_11
Copyright © 2022, Critical Link LLC
Specifications Subject to Change
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Critical Link, LLC
www.CriticalLink.com
Pin
195
21
23
25
27
29
31
33
35
37
39
41
43
45
47
491
51
53
552
572
59
Ball
L2
P16
P18
P19
N19
M18
M19
K18
H17
G17
H16
G19
F18
G16
G18
F16
Type
D
D
D
D
D
D
D
D
D
PWR
PWR
PWR
D
D
D
D
M
D
D
D
M
I/O
I
I
I/O
I/O
O
I/O
I/O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
61
F17
M
I/O
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
F19
E18
E16
D17
D19
C17
D16
E17
D18
C19
C18
C16
U17
U18
T17
T18
P17
P18
N17
N18
M16
M18
L17
L18
PWR
M
M
M
M
M
M
M
M
M
M
PWR
M
M
F
F
F
F
F
F
F
F
PWR
F
F
F
F
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Signal
SATA_RX_N
USB0_ID
USB1_D_N
USB1_D_P
USB0_VBUS
USB0_D_N
USB0_D_P
USB0_DRVVBUS
3V RTC Battery
+3.3 V in
+3.3 V in
GND
SPI1_MISO
SPI1_MOSI
SPI1_ENA
SPI1_CLK
SPI1_SCS1
Reserved
I2C0_SCL
I2C0_SDA
UART2_TXD
I2C1_SDA
UART2_RXD
I2C1_SCL
GND
UART1_TXD
UART1_RXD
MDIO_CLK
MDIO_DAT
MII_RXCLK
MII_RXDV
MII_RXD0
MII_RXD1
MII_RXD2
MII_RXD3
GND
MII_CRS
MII_RXER
B1 _47_P.U17
B1_ 47_N.U18
B1 _45_P.T17
B1_ 45_N.T18
B1_43_P.P17
B1_43_N.P18
B1_41_P.N17
B1_41_N.N18
GND
B1_39_P.M16
B1_39_N.M18
B1_37_P.L17
B1_37_N.L18
MityDSP-L138F System on Module
3-AUG-2022
/
Pin
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
Ball
A1
B4
B1
B2
B3
C2
C3
C4
C5
D4
E4
F4
D5
A12
C11
E12
B11
E11
Type
M
M
M
M
M
M
M
M
M
PWR
PWR
PWR
M
M
M
M
M
M
M
M
M
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Signal
GP0_15
GP0_6
GP0_14
GP0_12
GP0_5
GP0_13
GP0_1
GP0_4
GP0_3
+3.3 V in
+3.3 V in
GND
GP0_2
GP0_0
GP0_8
GP0_9
MMCSD0_DAT7
MMCSD0_DAT6
MMCSD0_DAT5
MMCSD0_DAT4
MMCSD0_DAT3
/
62
C10
M
I/O
MMCSD0_DAT2
64
66
68
70
72
74
76
78
80
82
84
86
88
904
92
94
96
98
100
102
104
106
108
110
112
114
116
A11
B10
A10
E9
D3
E3
E2
E1
F3
C1
D1
R16
M14
N14
N15
N16
L12
L13
K12
K13
L15
L16
K15
K16
PWR
M
M
M
M
M
M
M
M
M
M
PWR
M
F
F
F
F
F
F
F
F
F
PWR
F
F
F
F
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
MMCSD0_DAT1
MMCSD0_DAT0
MMCSD0_CMD
MMCSD0_CLK
MII_TXCLK
MII_TXD3
MII_TXD2
MII_TXD1
MII_TXD0
MII_TXEN
GND
MII_COL
FPGA_SUSPEND
B1 _48_P.M14
B1_ 48_N.N14
B1 _46_P.N15
B1_ 46_N.N16
B1 _44_P.L12
B1_ 44_N.L13
B1 _42_P.K12
B1_ 42_N.K13
GND
B1 _40_P.L15
B1_ 40_N.L16
B1 _38_P.K15
B1_ 38_N.K16
6
Copyright © 2022, Critical Link LLC
Specifications Subject to Change
60-000037-1C
Critical Link, LLC
www.CriticalLink.com
Pin
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
Ball
K17
K18
J16
J18
H17
H18
G16
G18
F17
F18
E16
E18
D17
D18
C17
C18
B16
A16
C15
A15
B14
A14
C13
A13
B12
A12
B11
A11
C10
A10
B9
A9
B8
A8
C7
A7
-
Type
F
F
F
F
F
F
PWR
F
F
F
F
F
F
F
F
F
F
PWR
F
F
F
F
F
F
F
F
F
F
PWR
F
F
F
F
F
F
F
F
F
F
PWR
PWR
PWR
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
Signal
B1_35_P.K17
B1_35_N.K18
B1_33_P.J16
B1_33_N.J18
B1_31_P.H17
B1_31_N.H18
GND
B1_29_P.G16
B1_29_N.G18
B1_27_P.F17
B1_27_N.F18
B1_25_P.E16
B1_25_N.E18
B1_23_P.D17
B1_23_N.D18
B1_21_P.C17
B1_21_N.C18
GND
B0_19_P.B16
B0_19_N.A16
B0_17_P.C15
B0_17_N.A15
B0_15_P.B14
B0_15_N.A14
B0_13_P.C13
B0_13_N.A13
B0_11_P.B12
B0_11_N.A12
GND
B0_9_P.B11
B0_9_N.A11
B0_7_P.C10
B0_7_N.A10
B0_5_P.B9
B0_5_N.A9
B0_3_P.B8
B0_3_N.A8
B0_1_P.C7
B0_1_N.A7
GND
VCCO_1
VCCO_1
MityDSP-L138F System on Module
3-AUG-2022
Pin
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
1543
1563
1583
1603
1623
1643
166
168
1703
1723
174
176
178
180
182
184
186
188
190
192
194
196
198
200
Ball
J13
K14
H15
H16
H13
H14
F15
F16
H12
G13
F14
G14
F13
E13
D14
C14
F12
E12
D12
C12
F11
E11
D11
C11
E7
E8
D9
C9
D8
C8
D6
C6
B6
A
C5
A5
-
Type
F
F
F
F
F
F
PWR
F
F
F
F
F
F
F
F
F
F
PWR
F
F
F
F
F
F
F
F
F
F
PWR
F
F
F
F
F
F
F
F
F
F
PWR
PWR
PWR
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O3
I/O3
I/O3
I/O3
I/O3
I/O3
I/O
I/O
I/O3
I/O3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
Signal
B1 _36_P.J13
B1_ 36_N.K14
B1 _34_P.H15
B1_ 34_N.H16
B1 _32_P.H13
B1_ 32_N.H14
GND
B1 _30_P.F15
B1_ 30_N.F16
B1 _28_P.H12
B1_ 28_N.G13
B1 _26_P.F14
B1_ 26_N.G14
B0 _24_P.F13
B0_ 24_N.E13
B0 _22_P.D14
B0_ 22_N.C14
GND
B0 _20_P.F123
B0_ 20_N.E123
B0 _18_P.D123
B0_ 18_N.C123
B0 _16_P.F113
B0_ 16_N.E113
B0 _14_P.D11
B0_ 14_N.C11
B0 _12_P.E73
B0_ 12_N.E83
GND
B0 _10_P.D9
B0_ 10_N.C9
B0 _8_P.D8
B0_ 8_N.C8
B0 _6_P.D6
B0_ 6_N.C6
B0 _4_P.B6
B0_ 4_N.A6
B0 _2_P.C5
B0_ 2_N.A5
GND
VCCO_0
VCCO_0
Note 1: Pin 49, SPI1_CLK, has a 100K Ohm pull-down resistor on the module
Note 2: Pins 55 and 57 have 4.70K pull-up resistors on the module
Note 3: The Xilinx 6SLX45 FPGA does not bond I/O Buffers to balls E7, E8, F11, E11,
D12, C12, E12, and F12 of the package used for this module. For MityDSP-L138F
configurations using this FPGA option, these edge connector signals should be treated as
no-connects and will not function as FPGA I/O lines.
Note 4: Pin 90, FPGA_SUSPEND, has a 4.7K Ohm pull-down resistor on the module
7
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Note 5: The SATA peripheral interface is only supported on modules ordered with the
SATA option code. Contact Critical Link for details.
The signal group description for the above pins is included in Table 2.
8
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Table 2 Signal Group Description
Signal / Group
3.3 V in
EXT_BOOT#
I/O
N/A
I
RESET_IN#
I
SPI_XXXX
I/O
MII_XXXX
I/O
MDIO_XX
I/O
GP0_X
IO
SATA_TX_P/N
O
SATA_RX P/N
I
GND
BX_Y_P.ZZ,
BX_Y_N.ZZ
N/A
IO
Description
3.3 volt input power referenced to GND.
Bootstrap configuration pin. Pull low to configure
booting from external UART1.
Manual Reset. When pulled to GND for a minimum
of 1 usec, resets the DSP processor.
The pins with an SPI_ prefix are direct connections
to the OMAP-L138 pins supporting the SPI1
interface. The SPI1_CLK, SPI1_ENA, SPI1_MISO,
SPI1_MOSI pins must remain configured for the SPI
function in order to support interfacing to the onboard SPI boot ROM. For details please refer to the
OMAP-L138 processor specifications.
The pins with an MII_ prefix are direct connections
to the OMAP-L138 pins supporting the media
independent interface (MII) function. The MII pins
provide multiplex capability and may alternately be
used as UART, GPIO, and SPI control pins. For
details please refer to the OMAP-L138 processor
specification.
The MDIO_CLK and MDIO_DAT signals are direct
connects to the corresponding MDIO signals on the
OMAP-L138 processor.
These pins may be
configured for GPIO.
General Purpose / multiplexed pins. These pins are
direct connects to the corresponding GP0[X] pins on
the OMAP-L138 processor. The include support for
the McASP, general purpose I/O, UART flow
control, and McBSP 1. For details please refer to the
OMAP-L138 processor specifications.
These pins are direct connects to the OMAP-L138
SATA_TX differential Serial ATA controller pins.
The SATA peripheral interface is only supported on
devices ordered with the SATA option code. For
details contact Critical Link.
These pins are direct connects to the OMAP-L138
SATA_RX differential Serial ATA controller pins.
The SATA peripheral interface is only supported on
devices ordered with the SATA option code. For
details contact Critical Link.
System Digital Ground.
FPGA I/O pins. These pins are routed directly to
FPGA pins ZZ. The “X” indicates which FPGA
bank the pin is allocated. The bank is either 0 or 1.
9
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Signal / Group
MityDSP-L138F System on Module
3-AUG-2022
I/O
VCCO_X
I
USB0_XXXX,
USB1_XXXX
I/O
Description
The FPGA fabric supports routing pins in
differential pairs, the Y_P and Y_N portion of the
name indicates the pair number and polarity. The
pins have been routed in pairs with phase matched
line lengths.
FPGA Bank interface power input. These pins must
be tied to the desired voltage used for the FPGA
Bank 0 or 1 interface pins. Please refer to the
VCCO input pin specifications for the Xilinx
Spartan 6 family of devices for further information.
Typical values are 3.3V and 2.5 volts. Each
VCCO_X pair should have a 100uF X5R (or better)
capacitor place near the pins on the carrier board.
The USBN_ prefixed pins are direct connects to the
corresponding pins on the OMAP-L138 processor.
For details please refer to the OMAP-L138 processor
specifications.
DEBUG INTERFACE
Below is the pin-out for the Hirose 31 pin header (DF9-31P-1V(32)) that interfaces with
an available adapter board, Critical Link part number 80-000286, to debug the OMAPL138 and FPGA. The debug interface connector is only installed on devices ordered with
the JTAG option code. For details contact Critical Link.
Debug Interface Connector Description (J2)
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
I/O
-
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Table 3 OMAP-L138 Hirose Connector
Signal
Pin
I/O
Signal
2
O
OMAP EMU1
4
O
OMAP EMU0
6
I
OMAP TCK
8
O
OMAP RTCK
10
O
OMAP TDO
12
OMAP VCC / 3.3V
14
I
OMAP TDI
16
I
OMAP TRST
18
I
OMAP TMS
20
GND
22
O
FPGA VREF / VCCAUX
24
I
FPGA TMS
26
I
FPGA TCK
28
O
FPGA TDO
30
I
FPGA TDI
10
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ELECTRICAL CHARACTERISTICS
Table 4: Electrical Characteristics
Parameter
Conditions
Min
Symbol
V33
I33
I33-max
V3V_RTC_Battery
I3V_RTC_Battery
FCPU
FEMIF
Voltage supply, 3.3 volt input.
Quiescent Current draw, 3.3 volt input
Max current draw, positive 3.3 volt input.
Voltage supply, RTC Battery
Current, RTC Battery, V33 = 0V
CPU internal clock Frequency (PLL output)
EMIF bus frequency
1.
2.
3.2
Must be ½ CPU
25
-
Typ
Max
Units
3.3
3401,2
TBS1,2
3.0
10
300
100
3.4
TBS1,2
22001,2
5.0V
Volts
mA
mA
Volts
uA
MHz
MHz
456
-
Power utilization of the MityDSP-L138F is heavily dependent on end-user application. Major factors
include: ARM CPU PLL configuration, DSP Utilization FPGA utilization, and external DDR2 RAM
utilization.
For power utilization information please visit our Redmine Wiki pages on support.criticallink.com
ORDERING INFORMATION
The following table lists the standard module configurations. For shipping status,
availability, and lead time of these or other configurations please contact Critical Link at
info@criticallink.com.
Module P/N
L138-FG-325-RC
L138-DG-325-RI
L138-DG-325-RI-1
L138-FI-325-RC
L138-DI-325-RI
L138-DI-336-RI
L138-FI-336-RL
L138-FG-326-RC
CPU
456 MHz
375 MHz
375 MHz
456 MHz
375 MHz
375 MHz
456 MHz
456 MHz
Table 5: Standard Model Numbers*
FPGA
NOR
NAND
6SLX16
16MB
256MB
6SLX16
16MB
256MB
6SLX16
16MB
256MB
6SLX45
16MB
256MB
6SLX45
16MB
256MB
6SLX45
16MB
512MB
6SLX45
16MB
512MB
6SLX16
16MB
256MB
RAM
128MB
128MB
128MB
128MB
128MB
256MB
256MB
256MB
Temperature
0oC to 70o C
-40oC to 85o C
-40oC to 85o C
0oC to 70o C
-40oC to 85o C
-40oC to 85o C
-40oC to 70o C
0oC to 70o C
*Standard Model configurations do not include SATA support or the JTAG interface
connector, J2. Contact Critical Link for orderable option codes for either or both
features.
12
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MECHANICAL INTERFACE
The mechanical outline of the MityDSP-L138F is illustrated in Figure 2, as shown below.
Figure 2 MityDSP-L138F Mechanical Outline
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REVISION HISTORY
Rev
n/a
n/a
n/a
Date
7-NOV-2009
10-NOV-2009
15-JAN-2010
n/a
16-MAR-2010
n/a
n/a
6-APR-2010
21-APR-2010
n/a
26-JUL-2010
n/a
11-FEB-2011
n/a
02-JUN-2011
n/a
12-JUL-2011
n/a
28-NOV-2011
n/a
13-AUG-2012
n/a
11-DEC-2012
n/a
29-AUG-2013
-1A
18-JUN-2019
-1B
21-OCT-2020
-1C
3-AUG-2022
Change Description
Preliminary Draft, product overview
Updates after initial review.
Updates to features, applications and benefits
Finalize connector pin-outs. Update mechanical
outlines.
Update product photo and speed grade.
Update specifications and options.
Update ordering information, images and
mechanical drawing.
Correct edge connector Table 1. Update speed
grade to max 456 MHz. Updated DDR rate to
support 150 MHz clocking. Update model p/n
table.
Update edge connector Table 1 to indicate
unavailable FPGA pins for 6SLX45 options.
Update NAND to indicate 8 bit data width.
Update block diagram accordingly.
Update list of orderable part numbers.
Fix typo in signal names for pins 79, 81, 83, and
84
Update Debug Header information, added MILSTD-810F and Up To notation for RAM and
NAND
Added OMAP-L138 processor pins and FPGA
pins to Table 1 with notes about on module
resistors for specific pins as well as the OSCIN
frequency.
Added 16MB NOR option and model numbers
and RTC info.
Update list of orderable part numbers and VCCO
capacitor recommendation.
Updated to make SATA and JTAG connector not
part of standard configuration (option only).
14
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