nRF24AP2
nRF24AP2-1CH, nRF24AP2-8CH
Single-chip ANTTM ultra-low power
wireless network solution
Product Specification v1.2
Key Features
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Second generation single chip ANT solution
nRF24AP2-1CH supports 1 ANT (logic)
channel – ideal for sensors
nRF24AP2-8CH supports up to eight ANT
(logic) channels – ideal for hubs
World wide 2.4 GHz ISM band operation
Fully embedded, enhanced ANT protocol stack
True ultra-low power operation
Typically years of battery lifetime on a coin cell
Built-in device search and pairing
Built-in timing and power management
Built-in interference handling
Configurable channel period 5.2 ms - 2 s
Broadcast, Acknowledged and Burst
communication modes
Burst data rate up to 20 kbps
Simple to complex network topologies:
Peer-to-peer, star, tree and practical mesh
Supports public, private and managed networks
Support for ANT+ device profile
implementations enabling multivendor
interoperability
Fully interoperable with nRF24AP1 and
Dynastream ANT chipset / module based
products and other nRF24AP2 variants
Simple asynchronous/ synchronous host
interface
Single 1.9 - 3.6V power supply
RoHS compliant 5×5 mm 32-pin QFN package
Low cost external 16 MHz crystal
Optional on-chip 32.768 kHz crystal oscillator
Applications
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Sports
Wellness
Home health monitoring
Home/industrial automation
Environmental sensor networks
Active RFID
Logistics/goods tracking
Audience-response systems
All rights reserved. ANTTM is a trademark of Dynastream Innovation Inc.
Reproduction in whole or in part is prohibited without the prior written permission of the copyright holder.
June 2010
nRFAP2 Product Specification
Liability disclaimer
Nordic Semiconductor ASA reserves the right to make changes without further notice to the product to
improve reliability, function or design. Nordic Semiconductor ASA does not assume any liability arising out
of the application or use of any product or circuits described herein.
All application information is advisory and does not form part of the specification.
Limiting values
Stress above one or more of the limiting values may cause permanent damage to the device. These are
stress ratings only and operation of the device at these or at any other conditions above those given in the
specifications are not implied. Exposure to limiting values for extended periods may affect device reliability.
Life support applications
Nordic Semiconductor’s products are not designed for use in life support appliances, devices, or systems
where malfunction of these products can reasonably be expected to result in personal injury. Nordic
Semiconductor ASA customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Nordic Semiconductor ASA for any damages resulting from such
improper use or sale.
Datasheet status
Objective product specification
This product specification contains target specifications for Nordic
Semiconductor’s product development.
Preliminary product specification This product specification contains preliminary data; supplementary
data may be published from Nordic Semiconductor ASA later.
Product specification
This product specification contains final product specifications. Nordic
Semiconductor ASA reserves the right to make changes at any time
without notice in order to improve design and supply the best possible
product.
Contact details
For your nearest dealer, please see www.nordicsemi.com.
Main office:
Otto Nielsens veg 12
7004 Trondheim
Phone: +47 72 89 89 00
Fax: +47 72 89 89 89
www.nordicsemi.com
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2
nRFAP2 Product Specification
RoHS statement
Nordic Semiconductor’s products meets the requirements of Directive 2002/95/EC of the European
Parliament and of the Council on the Restriction of Hazardous Substances (RoHS). Complete hazardous
substance reports as well as material composition reports for all active Nordic Semiconductor products can
be found on our web site www.nordicsemi.com.
Revision History
Date
April 2010
Version
1.1
June 2010
1.2
Revision 1.2
Description
Updated schematics. Added section 2.4.1
on page 12, updated sections 8.1 on page
43 and 8.2 on page 46.
Updated sections 2.1 on page 8 and 2.4 on
page 11, Table 4. on page 22, section 4.2.2
on page 16, section 8.1 on page 43, and
chapter 11 on page 49.
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nRFAP2 Product Specification
Contents
1
Introduction .................................................................................................6
1.1
Prerequisites.........................................................................................6
1.2
Writing conventions ..............................................................................6
2
Product overview ........................................................................................7
2.1
Features................................................................................................8
2.2
Block diagram .......................................................................................9
2.3
Pin Assignments ...................................................................................10
2.4
Pin Functions ........................................................................................11
2.4.1
Reset pin ..........................................................................................12
3
RF Transceiver ............................................................................................13
3.1
Features................................................................................................13
3.2
Block diagram .......................................................................................14
4
ANT overview...............................................................................................15
4.1
Block diagram .......................................................................................15
4.2
Functional description...........................................................................15
4.2.1
ANT nodes .......................................................................................15
4.2.2
ANT channels...................................................................................16
4.2.3
ANT channel configuration ...............................................................17
4.2.4
Proximity search...............................................................................19
4.2.5
Continuous scanning mode..............................................................20
4.2.6
ANT network topologies ...................................................................20
4.2.7
ANT message protocol.....................................................................21
5
Host interface ..............................................................................................23
5.1
Features................................................................................................23
5.2
Asynchronous serial interface ............................................................23
5.2.1
Block diagram...................................................................................23
5.2.2
Baud rate..........................................................................................24
5.2.3
Asynchronous Port Control (RTS)......................................................24
5.2.4
Sleep enable (SLEEP) ...................................................................................... 25
5.2.5
Suspend mode control (SUSPEND) .....................................................25
5.3
Synchronous serial interface ................................................................26
5.3.1
Block diagram...................................................................................26
5.3.2
Flow Control Select (SFLOW)..............................................................27
5.3.3
Synchronous interface handshaking ................................................27
5.3.4
Synchronous messaging with byte flow control................................29
5.3.5
Synchronous timing with byte flow control .......................................31
5.3.6
Synchronous messaging with bit flow control...................................31
5.3.7
Serial enable control.........................................................................33
6
On-chip oscillator........................................................................................34
6.1
Features................................................................................................34
6.2
Block diagrams .....................................................................................34
6.3
Functional description...........................................................................35
6.3.1
16 MHz crystal oscillator ..................................................................35
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nRFAP2 Product Specification
6.3.2
External 16 MHz clock......................................................................36
6.3.3
32.768 kHz crystal oscillator.............................................................36
6.3.4
Synthesized 32.768 kHz clock .........................................................36
6.3.5
External 32.768 kHz clock................................................................37
7
Operating conditions ..................................................................................38
8
Electrical specifications .............................................................................40
8.1
Current consumption ............................................................................43
8.2
Current calculations examples..............................................................46
9
Absolute maximum ratings ........................................................................47
10 Mechanical specification ............................................................................48
11 Reference circuitry......................................................................................49
11.1
PCB guidelines .....................................................................................49
11.2
Synchronous (bit) mode schematics.....................................................50
11.3
Layout ...................................................................................................51
11.4
Synchronous (byte) mode schematics..................................................52
11.5
Layout ...................................................................................................53
11.6
Asynchronous mode schematics ..........................................................54
11.7
Layout ...................................................................................................55
11.8
Bill Of Materials (BOM) .........................................................................55
12 Ordering information ..................................................................................56
12.1
Package marking ..................................................................................56
12.1.1
Abbreviations....................................................................................56
12.2
Product options.....................................................................................56
12.2.1
RF silicon..........................................................................................56
12.2.2
Development tools............................................................................57
13 Glossary .......................................................................................................58
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nRFAP2 Product Specification
1
Introduction
nRF24AP2 is a member of Nordic Semiconductor’s low-cost, high-performance family of 2.4 GHz ISM
single-chip connectivity devices with the ANT protocol stack embedded. nRF24AP2 offers the market’s
most efficient, single chip, transceiver solution for Ultra Low Power (ULP) networks, through the integration
of the extremely power efficient ANT protocol stack, the world leading Nordic Semiconductor 2.4 GHz RF
technology as well as critical low-power oscillator and timing features.
This document covers the two products:
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1.1
nRF24AP2-1CH
nRF24AP2-8CH
Prerequisites
In order to fully understand the product specification, a good knowledge of electronics and software
engineering is necessary. Please also refer to the document ANT Message Protocol and Usage when
reading this product specification. You can download the document from Nordic’s web site
www.nordicsemi.com or from www.thisisant.com.
1.2
Writing conventions
This product specification follows a set of typographic rules to ensure that the document is consistent and
easy to read. The following writing conventions are used:
•
Commands, bit state conditions, and register names are written in Courier New.
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Pin names and pin signal conditions are written in Courier New bold.
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Cross references are underlined and highlighted in blue.
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nRFAP2 Product Specification
2
Product overview
ANT is a demonstrably superior Wireless Sensor Network (WSN) RF protocol for almost all practical ultralow power networking applications – from simple point-to-point links to complex networks. Embedded in
nRF24AP2 devices, it is paired up with Nordic Semiconductor's market leading 2.4 GHz radio technology.
The combination gives you high performance, ultra-low-power network connectivity to applications, and
requires minimal resources in the application’s microcontroller. Less than 1 kB of code space, and an
Asynchronous or Synchronous serial interface are all it takes to enable ANT connectivity in your
application.
The nRF24AP2 variants meet the specific requirements of end nodes and central nodes in a network.
nRF24AP2-1CH offers one logic communication channel (ANT channel) for end nodes like sensors to
connect to data collectors. nRF24AP2-8CH can manage up to eight ANT channels to collect data from
multiple sensors.
Figure 1. shows a network in which a network node with nRF24AP2-8CH embedded, communicates with
ANT nodes with nRF24AP2-1CH devices embedded. An example might be a sports watch collecting data
from several sensors (like heart rate-, speed- and distance sensors). Of course, the 8-channel node can
also set up ANT channels with other central nodes (gym equipment, for instance). These central nodes are
in turn connected to additional sensors.
Figure 1. Simple setup with nRF24AP2
See Figure 10. on page 21 for more complex ANT-network topologies.
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nRFAP2 Product Specification
2.1
Features
Features of the 1-channel nRF24AP2-1CH and 8-channel nRF24AP2-8CH include:
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Ultra low power 2.4 GHz transceiver
• World wide 2.4 GHz ISM band
operation
• Based on nRF24L01+ transceiver
• GFSK modulation
• 1 Mbps on-air data rate
• 1 MHz frequency resolution
• 78 RF channels
• -85 dBm sensitivity
• Up to 0 dBm output power
ANT protocol stack
• Full implementation of the physical,
data link, network- and transport
OSI layers
• Packet-based communication – 8 byte
payload per packet
• Optimized for ultra-low power
operation
ANT channels
• Logic communication channel
between ANT nodes
• nRF24AP2-1CH supports 1 channel
– ideal for sensors
• nRF24AP2-8CH support up to 8
channels – ideal for hubs
• Built-in timing and power management
• Built-in interference handling
• Configurable channel period
5.2 ms - 2 s
• Broadcast, acknowledged and burst
communication modes
• Burst data rate up to 20 kbps
Device search and pairing
• Wild-card searches
• Proximity searches
• Specific searches
• Automatic link establishment if
correct device is found
• Automatic re-link attempt if link is lost
• Configurable search timeout
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Revision 1.2
8
Network topologies
• Point-to- point and star networks using
independent ANT channels
• Shared networks: Polled data
collection (N:1) by using ANT
shared channel option
• Broadcast networks: Mass distribution
of data (1:N)
Network management / ANT+
• Supports public and private (managed)
networks
• Support for ANT+
system implementations enabling
multi-vendor interoperability
ANT core stack enhancements
• Background scanning channel
• Continuous scanning mode
• High density node support
• Improved channel search
• Channel ID management
• Improved transmission power control
on a per channel basis
• Frequency agility
• Proximity search
Power Management
• Fully controlled by ANT protocol stack
• On-chip voltage regulator
• Single DC supply operation
• 1.9 to 3.6V supply range
Ultra low power operation
• Up to 50% lower average compared
to nRF24AP1
• Up to 40% lower peak current
compared to nRF24AP1
• 20 µA average current consumption at
1 Hz broadcast
• 71 µA average current consumption
at 4 Hz broadcast
On-chip oscillators and clock inputs
• 16 MHz crystal oscillator supporting
low-cost crystals
• 16 MHz clock input
• Ultra low power 32.768 kHz
crystal oscillator
• 32.768 kHz clock input
Host interface
• Supports asynchronous and
synchronous modes
• 5-pins for asynchronous
• 6-pins for synchronous
nRFAP2 Product Specification
2.2
Block diagram
nRF24AP2 is composed of five main blocks as shown in Figure 2. The blocks indicate the interface, power
management, the ANT protocol engine, on-chip oscillators and the RF transceiver.
nRF24AP2
Application
MCU
ANT1
Host interfaces
Ultra low power
2.4 GHz
transceiver
ANT2
VDD_PA
ANT protocol
engine
VDD
DEC1
DEC2
Iref
Power
management
16 MHz
On-chip
oscillators
VSS
Figure 2. Block diagram of nRF24AP2 solution
Revision 1.2
9
32.768 kHz
XTAL or
source
(optional)
nRFAP2 Product Specification
To find more information about each block in the diagram, see Table 1.
Name
RF Transceiver
ANT protocol engine
Host interfaces
On-chip oscillators
Power management
Reference
Chapter 3 on page 13
Chapter 4 on page 15
Chapter 5 on page 23
Chapter 6 on page 34
Chapter 8 on page 40
Table 1. Block diagram cross references
VSS
IREF
VDD
SIN
25
XC2
32 31 30 29 28 27 26
XC1
SOUT
Pin Assignments
XC32K2
2.3
XC32K1 1
VDD
2
DEC1
3
DEC2
PORTSEL
4
VSS
6
24 VDD
23 VSS
nRF24AP2
22 ANT2
21 ANT1
QFN32
5x5
5
20 VDD_PA
19 RESET
UART_TX 7
VSS
18 BR2/SCLK
17 RTS/SEN
Exposed die pad
8
SLEEP/MRDY
BR1/SFLOW
BR3
VSS
SUSPEND/SRDY
VSS
UART_RX
VDD
9 10 11 12 13 14 15 16
Figure 3. nRF24AP2 pin assignment (top view) for a QFN32 5×5 mm package
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nRFAP2 Product Specification
2.4
Pin Functions
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Revision 1.2
Pin name
XC32K1
Pin functions
Description
Analog input Crystal connection for 32.768 kHz crystal oscillator,
optionally a synthesized or external 32.768 kHz clock
can be used as described in chapter 6 on page 34
VDD
Power
Power Supply (1.9-3.6V DC)
DEC1
Power
Power supply outputs for de-coupling purposes
(100nF)
DEC2
Power
Power supply outputs for de-coupling purposes
(33nF)
PORTSEL
Digital input Port Select
Asynchronous serial interface: Tie to VSS
Synchronous serial interface: Tie to VDD
VSS
Power
Ground (0V)
UART_TX
Digital IO
Asynchronous mode: Transmit data signal
Synchronous mode: Tie to VSS or VDD.
VSS
Power
Ground (0V)
VDD
Power
Power Supply (1.9-3.6V DC)
UART_RX
Digital input Asynchronous mode: Receive data signal
Synchronous mode: Tie to VDD
VSS
Power
Ground (0V)
Digital input Asynchronous mode: Suspend control
Synchronous mode: Serial port ready
SUSPEND/SRDY
VSS
Power
Ground (0V)
BR3
Digital input Asynchronous mode: Baud rate selection
Synchronous mode: Tie to VSS
BR1/SFLOW
Digital input Asynchronous mode: Suspend Control
Synchronous mode: Bit or Byte flow control select (Bit:
Tie to VDD, Byte: Tie to VSS)
Digital input Asynchronous mode: Sleep mode enable
Synchronous mode: Message ready indication
SLEEP/MRDY
Digital output Asynchronous mode: Request to send
Synchronous mode: Serial enable signal
RTS/SEN
BR2 / SCLK
Digital IO
Asynchronous mode: Baud rate selection
Synchronous mode: Clock output signal
Digital input Reset, active low. Internal pull up. Leave unconnected
if not used.
RESET
VDD_PA
Power output Power supply output (+1.8V) for on-chip RF Power
amplifier
ANT1
RF
Differential antenna connection (TX and RX)
ANT2
RF
Differential antenna connection (TX and RX)
VSS
Power
Ground (0V)
VDD
Power
Power Supply (1.9-3.6V DC)
IREF
Analog output Device reference current output. To be connected to
reference resistor on PCB.
VSS
Power
Ground (0V)
VDD
Power
Power Supply (1.9-3.6V DC)
SOUT
Digital IO
Asynchronous mode: Tie to VSS or VDD.
Synchronous mode: Data output
SIN
Digital input Asynchronous mode: Tie to VDD
Synchronous mode: Data input
XC2
Analog output Crystal connection for 16 MHz crystal oscillator
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nRFAP2 Product Specification
Pin
31
32
Pin name
XC1
XC32K2
Exposed die
pad
VSS
Pin functions
Description
Analog Input Crystal connection for 16 MHz crystal oscillator
Analog output Crystal connection for 32.768 kHz crystal oscillator,
optionally a synthesized or external 32.768 kHz clock
can be used as described in chapter 6 on page 34
Power
Connects the die pad to VSS
Table 2. nRF24AP2 pin functions
2.4.1
Reset pin
The RESET pin provides an optional reset when the nRF24AP2 is placed in a system that has a master
reset source. This pin is not needed for normal application. Pull RESET pin low for minimum 0.2 μs and
return to high, this will reset the nRF24AP2 to the default state. Leave unconnected if not used in the
application.
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nRFAP2 Product Specification
3
RF Transceiver
All transceiver operations are controlled solely by the ANT protocol stack. Configuration of the ANT
protocol stack occurs through a serial interface by issuing ANT commands to nRF24AP2.
3.1
Features
Features of the RF transceiver include:
•
•
•
•
General
• Worldwide 2.4 GHz ISM band operation
• Common antenna interface in transmit and receive
• GFSK modulation
• 1 Mbps on air data rate
Transmitter
• Programmable output power: 0, -6, -12 or -18 dBm
Receiver
• Integrated channel filters
• -85 dBm sensitivity
RF Synthesizer
• Fully integrated synthesizer
• 1 MHz frequency programming resolution
• 78 RF channels in the 2.4 GHz ISM band
• Accepts low cost ± 50 ppm 16 MHz crystal
• 1 MHz non-overlapping channel spacing
Revision 1.2
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nRFAP2 Product Specification
3.2
Block diagram
Figure 4. shows a block diagram of the RF transceiver in nRF24AP2.
RF transmitter
PA
TX
filter
GFSK
modulator
RX
filter
GFSK
demodulator
RF receiver
ANT protocol stack
ANT1
LNA
ANT2
RF synthesizer
Figure 4. Internal circuitry of RF transceiver relative to ANT
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nRFAP2 Product Specification
4
ANT overview
The ANT protocol has been engineered for simplicity and efficiency. In operation, this results in ultra-low
power consumption, maximized battery life, a minimal burden on system resources, simpler network
designs and lower implementation costs.
4.1
Block diagram
Application/Presentation layers
User defined
Higher level security
Network/Transport & low level security
Implemented by ANT
Data link layer
Physical layer
Figure 5. OSI layer model of ANT protocol stack
ANT provides carefree handling of the Physical, Data Link, Network, and Transport OSI layers. See Figure
5. In addition, it incorporates key, low-level security features that form the foundation for user-defined,
sophisticated, network-security implementations. ANT ensures adequate user control while considerably
easing the computational burden, by providing a simple yet effective wireless networking solution.
4.2
Functional description
A brief overview of the ANT concept is presented here for convenience. A complete description of the ANT
protocol is found in the ANT Message Protocol and Usage document available at www.nordicsemi.com or
www.thisisant.com.
4.2.1
ANT nodes
All ANT networks are built up of nodes. See the ANT node represented in Figure 6. on page 16. A node
can be anything from a simple sensor to a complex, collection unit like a watch or computer. Common to all
Revision 1.2
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nRFAP2 Product Specification
nodes is that they contain an ANT engine (nRF24AP2) handling all connectivity to other nodes and a host
processor handling the application features. nRF24AP2 interfaces to the host processor through a serial
interface, and all configuration and control are performed using a simple command library.
Node
Serial Interface
Host MCU
nRF24AP2
(ANT engine)
Figure 6. The ANT node
4.2.2
ANT channels
nRF24AP2 can establish one or up to eight logic channels, called ANT channels, to other ANT nodes. The
number of ANT channels available depends on the nRF24AP2 variant being used.
Node 1
Node 2
Host MCU
Host MCU
Channel A
nRF24AP2
(ANT engine)
nRF24AP2
(ANT engine)
Master
Slave
Figure 7. ANT nodes and the channel between them
The simplest ANT channel is called an independent channel and consists of two nodes, one acting as
master, the other as slave for this channel. For each ANT channel opened, nRF24AP2 will set up and
manage a synchronous wireless link, exchanging data packets with other ANT nodes at preset time
intervals called channel periods. See Figure 8. on page 17. The master controls the timing of a channel,
that is to say, it will always initiate communication between the nodes. The slave locks on to the timing set
by the master, receives the transmissions from the master and can then (if configured so) send
acknowledge and/or data (if any) back to the master.
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nRFAP2 Product Specification
Tch
Tch
Tch
Master
time
Slave
time
Channel time slot
(Always)
Forward
direction
(Optional)
Reverse
direction
Figure 8. Channel communication showing forward and reverse directions. Not to scale
At each time slot an ANT channel can transfer user data (8 bytes) both ways as simple broadcasts,
broadcast with acknowledgement from the receiver, or transfer data as bursts (this will extend the time slot
used) to accommodate transfer of larger blocks of user data. The total available payload bandwidth in an
ANT node is shared between active ANT channels through a Time Division Multiple Access (TDMA)
scheme. If a channel time slot comes up, but there is no new data from the master. The master will still
send the last packet to keep the timing of the channel and enable the slave to send data back if needed.
Each ANT channel available in the nRF24AP2 can for example be configured as a simple, uni-directional
(broadcast) or bi-directional independent channel; or as a more complex, shared channel where a master
interfaces to multiple slaves (1:N topologies). Please see the ANT Message Protocol and Usage document
for further details on shared ANT channels.
4.2.3
ANT channel configuration
Unique to ANT is that the setup of each ANT channel is independent from all the other ANT channels in the
network, including other channels in the same node. This means that one ANT node can act as master on
one ANT channel while being a slave to another. Since there is no overall ‘network master’ present in ANT
networks, ANT allows you to configure and run each ANT channel solely based on the needs of the nodes
on that channel. Search- and pairing algorithms in ANT let you easily set up and shut down ANT channels
in an ad-hoc fashion. This gives you ultimate flexibility in adjusting ANT channel parameters like data rate
and latency versus power consumption. Moreover, you only make the network as complex as it needs to
be at any given time. In order for two ANT nodes to set up an ANT channel, they must share a common
channel configuration and channel ID. The necessary configuration parameters are summarized in Table
3. on page 18.
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nRFAP2 Product Specification
Parameter
Channel period
RF frequencies
Channel type
Network type
Transmission type
Device type
Device number
Comment
Channel configuration
Time interval between data exchanges on this
channel (5.2 ms - 2 s)
Which of the 78 available RF frequencies is used
by this channel
Bi-directional slave, bi-directional master, shared
bi-directional slave, Slave Receive only
Decides if this ANT channel is going to be
generally accessible (public) to all ANT nodes, or if
it shall limit its connectivity to devices belonging to
a managed or private network
Channel ID
1 byte – Identifying characteristics of the
transmission, can for instance contain codes on
how payload is to be interpreted
1 byte - ID to identify the device type of the
channel master (Ex: heart rate belt, temperature
sensor etc.)
2 byte - Unique ID for this channel
Table 3. ANT channel ID
The channel configuration parameters are static, system parameters that must match in the master and
slave, and the channel ID is included in all transmissions identifying the two nodes for each other. For indepth details on each parameter please refer to ANT Message Protocol and Usage.
Network
In addition to setting the content of the channel ID, which is the primary ID of an ANT node, ANT nodes
can limit their connectivity to a selection of other ANT nodes by defining a network for each ANT channel.
The limited access to certain networks is managed through unique network keys
The defined ANT networks are:
1.
2.
3.
Public networks: These are open ANT networks with no limitation on connectivity. All ANT
nodes sharing the same channel configuration (by design or by accident) will be able to connect.
This is the default setting in nRF24AP2.
Managed networks: These are ANT networks managed by special interest groups or alliances.
An example is the ANT+ alliance for sport and wellness products. To join the ANT+ alliance, visit
www.thisisant.com. By joining the ANT+ alliance and complying with the ANT+ device profiles set
by the alliance, you achieve two goals:
• Limited connectivity: Only other ANT+ compliant devices can connect to this channel.
• Interoperability: Your node can connect to ANT+ compliant products from other vendors.
Private networks: Your own protected networks, and no other devices, will be able to connect to
your ANT nodes unless you share the network key with someone outside the network. Please
note that this requires purchase of a unique network key from ANT, see www.thisisant.com.
Since the network parameter can be chosen independently for each ANT channel, one ANT node ( 1
nRF24AP2-8CH) can have up to eight ANT channels, operating on different networks at the same time.
Note: The network parameter has no impact on the network topologies you can build. It is merely a
tool to protect your ANT network and prevent accidental or deliberate access from other ANT
nodes.
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nRFAP2 Product Specification
Channel ID, search and pairing
The primary parameters which two ANT nodes use to identify each other make up the channel ID. Once
an ANT channel is established, the channel ID parameters must of course match; but they don’t have to
be known by both nodes (pre-configured) to be able to establish an ANT channel.
When an nRF24AP2 configured as a master (set in channel type) opens an ANT channel, it will broadcast
its entire channel ID. Hence you must configure all three channel ID parameters before opening an ANT
channel as a master.
On the other hand, in a slave you can configure nRF24AP2 to search for and connect with both known
and unknown masters. To connect with a known master you must configure the Transmission type,
Device type and Device number in nRF24AP2 before opening the ANT channel.
You can also configure the nRF24AP2 to conduct wild-card searches on one or more of the three
parameters in the channel ID to enable it to pair up with unknown masters. You can for instance set only
the Device type of the masters you want to link up with, and set wild cards on the Transmission type and
Device number. If a new master with a matching Device type is found, the slave device will connect and
store the unknown parts of the channel ID. The new parts of the channel ID can then be stored in the host
MCU to enable specific searches for this master later.
4.2.4
Proximity search
When using the basic search and pairing algorithm a slave will automatically identify and connect to the
first master it finds matching the search criteria. In areas where you either have a high density of similar
master nodes or high density of independent ANT networks, there is always the chance that multiple
masters are found within the coverage area. This presents the risk that it is not the master you wanted to
connect to that is found first. The proximity search feature in ANT designates ‘bins’ of proximity from 1
(closest) to 10 (furthest) as shown in Figure 9.
Figure 9. Standard search (a), Proximity search (b), showing bins 1-5 (of maximum 10)
This ‘binning’ enables you to further control your search by for instance only accepting the master that is
closest (only accept masters that fall in bin 1-2). This makes it easy for a user to pair up network nodes and
prevent accidental connection to nodes possibly belonging to another network close by.
Revision 1.2
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nRFAP2 Product Specification
4.2.5
Continuous scanning mode
Continuous scanning mode allows for fully asynchronous communication between an ANT node using
continuous scanning mode, and any other ANT node using a standard master channel. This has two main
advantages over only using standard ANT channels. The first is that the latency to initiate communication
with the scanning node is reduced to zero and every message sent by a master channel in proximity will be
received by the scanning device. Secondly, the requirement to maintain communication for the purpose of
synchronization while in proximity is removed. This means that it is possible for nodes to come and go very
quickly or to turn off for long periods of time in between communication events. This saves power on the
transmitting node.
The disadvantage of continuous scanning mode is that it consumes much more power than standard ANT
channels and will therefore only typically be used on devices that are plugged in and not mobile such as a
computer (USB dongle). Another disadvantage is that a node in scanning mode can no longer be
configured to have discoverable master channels because scanning mode disables standard ANT channel
functionality. It is worth noting that two ANT nodes in scanning mode cannot communicate with one
another because neither will be able to spontaneously generate communication.
Standard ANT channels are recommended over scanning channels, even in dynamic systems where
devices are coming and going. This is because scanning channels are not recommended for mobile
networks which is the primary area of application for ANT. Scanning channels will typically be used in
statically located networks where the scanning channel node is plugged in and not mobile.
4.2.6
ANT network topologies
By combining ANT channels with different features depending on local needs, you can build anything from
very simple peer-to-peer links and star networks to complex networks as shown in Figure 10. on page 21.
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nRFAP2 Product Specification
ANT-FS
(Secure Authenticated)
PEER
TO
PEER
BROADCAST
STAR
Acknowledged
Broadcast
Bidirectional
M
14
M
M
1
12
1
12
1
12
2
11
2
11
2
11
3
10
3
10
3
10
4
9
4
9
4
9
5
8
5
8
6
7
6
7
SHARED
BI-DIRECTIONAL
n
16
1
12
2
11
3
10
4
8
?
6
7
5
9
8
SHARED
UNI-DIRECTIONAL
15
13
AD-HOC
AUTO
SHARED
7
6
SCANNING MODE
PRACTICAL MESH
Relay
Sensor
SHARED CLUSTER
Hub
Figure 10. Network topology examples supported by ANT
4.2.7
ANT message protocol
All the configuration and control of the various ANT node and channel parameters in nRF24AP2 are
handled by the host microcontroller over a simple serial interface by using the command library. See the
document ANT Message Protocol and Usage for further details on the command library.
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nRFAP2 Product Specification
Class
Config.
messages
Type
Unassign Channel
Assign Channel
Commands in ANT command library
ANT_UnassignChannel()
ANT_AssignChannel()
Channel ID
Channel Period
Search Timeout
Channel RF Frequency
Set Network
Transmit Power
ID List Add
ID List Config
Channel Transmit Power
Low Priority Search
Timeout
Enable Ext RX Mesgs
Crystal Enable
Frequency Agility
Proximity Search
Notifications Startup Message
Control
SystemReset
Messages
Open Channel
Close Channel
Open Rx Scan Mode
Request Message
Sleep Message
Data Messages Broadcast Data
Acknowledge Data
Burst Transfer Data
Channel Event Channel Response/
Messages
Event
Requested
Response
Messages
Test Mode
Ext Data
messages
Channel Status
Channel ID
ANT Version
Capabilities
CW Init
CW Test
Extended Broadcast
Data
Reply
Yes
Yes
From
Host
Host
ANT_SetChannelId()
Yes
Host
ANT_SetChannelPeriod()
ANT_SetChannelSearchTimeout()
ANT_SetChannelRFFreq()
ANT_SetNetworkKey()
ANT_SetTransmitPower()
Yes
Yes
Yes
Yes
Yes
Yes
Host
Host
Host
Host
Host
Host
ANT_AddChannelID()a
ANT_ConfigList()a
ANT_SetChannelTxPower()
ANT_SetLowPriorityChannelSearchTi
meout()
ANT_RxExtMesgsEnable()
ANT_CrystalEnable()
ANT_ConfigFrequencyAgility()
ANT_SetProximitySearch()
→ ResponseFunc( -, 0x6F)
ANT_ResetSystem()
ANT_OpenChannel()
ANT_CloseChannel()
ANT_OpenRxScanMode()a
ANT_RequestMessage()
ANT_SleepMessage()
ANT_SendBroadcastData()
→ ChannelEventFunc(Chan,EV)
ANT_SendAcknowledgedData()
→ ChannelEventFunc(Chan, EV)
ANT_SendBurstTransferPacket()
→ ChannelEventFunc(Chan, EV)
→ ChannelEventFunc(Chan,
MessageCode) or
→ ResponseFunc(Chan, MsgID)
→ ResponseFunc(Chan, 0x52)
→ ResponseFunc(Chan, 0x51)
→ ResponseFunc(Chan, 0x51)
→ ResponseFunc(-, 0x3E)
ANT InitCWTestMode()
ANT SetCWTestMode()
ANT SendExtBroadcastData()b
→ ChannelEventFunc(Chan, EV)
Yes
Host
Yes
Yes
Host
Host
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
No
No
Host
Host
Host
Host
ANT
Host
Host
Host
Host
Host
Host
Host/ANT
No
Host/ANT
No
Host/ANT
-
ANT
Yes
Yes
No
ANT
ANT
ANT
ANT
Host
Host
Host
Extended Ack. Data
ANT SendExtAcknowledgedData()b
→ ChannelEventFunc(Chan, EV)
No
Host
Extended Burst Data
ANT SendExtBurstTransferPacket()b
→ ChannelEventFunc(Chan, EV)
No
Host
a. This is only supported by the nRF24AP2-8CH.
b. nRF24AP2 does not send these ChannelEventFunctions() to the host. nRF24AP2 will send
extended messages by appending the additional bytes to standard broadcast, acknowledged
and burst data.
Table 4. ANT message summary supported by nRF24AP2
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nRFAP2 Product Specification
5
Host interface
The host microcontroller can configure and control all of the nRF24AP2 features through a simple serial
interface. Three interface options are available, enabling both high and low end microcontrollers to be
used.
5.1
Features
Serial interfaces supported by nRF24AP2:
•
•
Asynchronous (UART)
• Interface requires 5 pins to host microcontroller
• Configurable baud rate from 4800 to 57600 baud
Synchronous
• Bit or byte flow
• Interface requires 6 pins to host microcontroller
5.2
Asynchronous serial interface
The host MCU and nRF24AP2 may communicate using the asynchronous mode of the serial interface.
Asynchronous mode is selected by the PORTSEL input being tied low.
5.2.1
Block diagram
The asynchronous serial interface between nRF24AP2 and the host MCU is shown in Figure 11.
Host MCU
RTS
UART_RX
UART_TX
nRF24AP2
SLEEP
SUSPEND
BR1
BR2
BR3
PORTSEL
Tied high or low
Tied high or low
Tied high or low
Tied low
Figure 11. Asynchronous mode connections
The UART communication is for one start bit, one stop bit, 8 bits of data and no parity. Data is sent and
received LSBit first.
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nRFAP2 Product Specification
5.2.2
Baud rate
The baud rate of the asynchronous communication between the host and ANT is controlled by the speed
select signals BR1, BR2 and BR3. Table 5. shows the relationship between the states of the speed select
signals and the corresponding baud rates.
BR3
BR2
BR1
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
Baud rate
4800
19200
38400
50000
1200
2400
9600
57600
Table 5. Relationship between states of speed-select signals and corresponding baud rates
Note: The baud rate may have a significant impact on system current consumption. Refer to section
8.2 on page 46 for application-specific current consumption figures.
5.2.3
Asynchronous Port Control (RTS)
When nRF24AP2 is configured in asynchronous mode, a full duplex asynchronous serial port is provided
with flow control for data transmission from the host to ANT. The flow control is performed by the RTS
signal, which conforms to standard hardware flow control CMOS signal levels. The signal may therefore be
attached to a computer serial port (with use of an RS-232 level shifter), or to any other RS-232 device. The
RTS signal is de-asserted for approximately 50 µs after each correctly formatted message has been
received. This RTS signal duration is independent of the baud rate. Incorrect messages or partial
messages are not acknowledged.
50 µs
nRF24AP2
Host
CTS
RTS
(out)
UART_TX
(out)
RXD
TXD
A4
ML
ID
DO
D1
...
Dn
CS
UART_RX
(in)
Figure 12. RTS signal following a serial host -> nRF24AP2 transfer
When nRF24AP2 raises the RTS signal high, the host MCU may not send any more data until the RTS
signal is lowered again. There is no flow control for data being transmitted from nRF24AP2 to the host
controller, and therefore the host controller must be able to receive data at any time. RTS is toggled
following a reset.
The RTS signal is raised by nRF24AP2 after the last byte of a message has been received, and nRF24AP2
will therefore lose any bytes that were sent, or in the process of being sent, before the RTS signal is acted
upon by the host MCU, and the transmission is halted. To avoid this problem, either the messages need to
be spaced apart by the host MCU or 0-pad bytes need to be added to the end of each message being
transmitted to handle whatever byte pipeline is in place. For example, when considering computer
Revision 1.2
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nRFAP2 Product Specification
communication, two 0-bytes must be appended to every message, since computers interpret CTS at the
driver- rather than the hardware level.
nRF24AP2 will discard 0-pad bytes received. This issue usually occurs only when using burst transfers
from the host to nRF24AP2 and high data rates are expected.
5.2.4
Sleep enable (SLEEP)
The SLEEP input signal allows nRF24AP2 to sleep when the serial port is not required. The signal is
essential for conserving power when using the asynchrnous serial interface. This control mechanism is
illustrated in Figure 13.
Host MCU
nRF24AP2
SLEEP (in)
SLEEP
CTS
RTS (out)
TXD
UART_RX (in)
Figure 13. nRF24AP2 sleep control
If the SLEEP signal is not used, then it must be tied low. In this configuration, the nRF24AP2 will never
sleep and will always be ready to receive data. The SUSPEND functionality cannot be used if the SLEEP
signal is not used.
The SLEEP and RTS signals only affect the data being transferred from the host MCU to nRF24AP2.
nRF24AP2 will send data to the host, when available, regardless of the state of these two signals.
5.2.5
Suspend mode control (SUSPEND)
When using the asynchronous serial interface, you also have a SUSPEND signal available.The assertion of
the SUSPEND signal will cause nRF24AP2 to terminate all RF and serial port activity and power down. This
will happen immediately, regardless of the state of the nRF24AP2 system. This signal provides support for
use in USB applications, where USB devices are required to quickly enter a low-power state through
hardware control.
Entering and exiting from the suspend mode require the use of the SLEEP signal, in addition to the
SUSPEND signal. The assertion of SUSPEND is only recognized if SLEEP is also asserted at the time. Deassertion of the SLEEP signal is the only method for exiting from suspend mode, as shown in Figure 14. on
Revision 1.2
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nRFAP2 Product Specification
page 26. Following exit, all previous transactions and configurations will be lost – nRF24AP2 will be in its
power-up state.
Enter suspend mode
SUSPEND
Still in suspend mode
Successful exit from suspend
mode
SLEEP
SLEEP must be raised before
SUSPEND is asserted
Figure 14. SUSPEND signal use
5.3
Synchronous serial interface
This section explains in detail the synchronous serial interface between nRF24AP2 and a host MCU. This
mode is selected by connecting the PORTSEL input high.
When operating in synchronous mode, careful attention to reset behavior is required to prevent inadvertent
deadlock conditions between nRF24AP2 and the host MCU.
In synchronous mode, nRF24AP2 uses a half-duplex synchronous master serial interface with message
flow control. The host must be configured as a synchronous slave. The interface is meant to
accommodate either a hardware synchronous slave port or a simple I/O control on the host MCU. The
host MCU retains full control of the message flow and can halt incoming messages as required.
5.3.1
Block diagram
The synchronous serial interface between nRF24AP2 and the host MCU is shown in Figure 15. The
PORTSEL signal should be connected to logic high for synchronous serial mode.
Host MCU
SEN
MRDY
SOUT
SIN
SCLK
SRDY
SFLOW
Tied high or low
nRF24AP2
PORTSEL
Tied high
Figure 15. Synchronous mode connections
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nRFAP2 Product Specification
5.3.2
Flow Control Select (SFLOW)
The Flow Control Select signal is used to configure the synchronous serial port for either Byte or Bit flow
control.
SFLOW
0
1
Flow control
Byte flow control
Bit flow control
Please note that Byte flow control assumes that the host contains synchronous communication hardware
which can be configured for synchronous slave communication. Bit flow control can be used by all
microcontrollers. It is especially useful for microcontrollers that offer no hardware serial interface, and
which require the serial interface to be emulated in software on the host MCU. The differences between
byte and bit flow control are detailed in the remaining sections of this chapter.
5.3.3
Synchronous interface handshaking
A basic description of the communications mechanism follows.
•
•
•
•
•
•
The synchronous serial port provided by nRF24AP2 is a half-duplex synchronous master.
Two handshake signals (SEN, MRDY) are used to set up communication.
Being a master, the nRF24AP2 will forward all incoming radio messages to the host as they become
available.
The host must request the use of the serial port and get acknowledge from nRF24AP2 before a
transaction can take place.
SRDY enables flow control in both directions.
The first byte in each message is always sent from the nRF24AP2 and indicates the direction of this
message.
The steps needed to initiate synchronous message transfers in both directions are shown in Figure 16. on
page 27.
5.3.3.1
Synchronization
In order for the host MCU to guarantee synchronization with nRF24AP2 in startup conditions, a reset
sequence must be applied to nRF24AP2. This only applies to synchronous mode communication.
Host MCU
tReset > 250 µs Normal Transaction Begins
nRF24AP2
MESSAGE_READY
MRDY (in)
SYNC_ENABLE
SEN (out)
SERIAL_READY
SRDY (in)
SCLK (out)
SERIAL_CLK
SERIAL_IN
1 0 1 0 0 10 1
SIN (in)
SERIAL_OUT
ANT Reset
WRITE FLAG
Figure 16. Synchronization with nRF24AP2 upon startup
Revision 1.2
SOUT (out)
27
nRFAP2 Product Specification
5.3.3.2
Power up/power down
nRF24AP2 will automatically place itself into idle mode when all radio channels are closed and there is no
activity on the MRDY input signal. The host MCU should ensure these conditions during times that the
nRF24AP2 radio is not required in order to maximize product battery life. Upon every power up, the host
must apply the Synchronous Reset sequence.
Host -> nRF24AP2
nRF24AP2 -> Host
Host has message for
nRF24AP2
MESSAGE_READY
nRF24AP2
accepts message
nRF24AP2
has message for host
SEN
SEN
Transaction can start
SRDY
nRF24AP2
sends SYNC byte
SYNC = 0xA5
SYNC = 0xA4
Host sends remaining
message bytes
nRF24AP2 sends
remaining message
bytes
Figure 17. Synchronous serial communication
Figure 17. on page 28 and timing diagrams in Figure 18. on page 29 and Figure 19. on page 30 illustrate
the basic, message transaction sequence:
For a message from host->nRF24AP2:
•
The host will assert the MRDY signal indicating it has a message for the nRF24AP2.
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nRFAP2 Product Specification
For messages in either direction:
nRF24AP2 will assert SEN to indicate the start of a message transfer.
After SEN has been asserted, the host will assert SRDY to indicate it is ready for communication.
After SEN and SRDY are both asserted, nRF24AP2 always transmits the first (for example SYNC)
byte. This is output from SOUT, and clocked with SCLK (see chapter 8 on page 40 for details of
clock frequency). The LSB of the SYNC byte indicates the direction of the remaining message
bytes (0 : Message Receive, nRF24AP2 → host; 1: Message Transmit, host → nRF24AP2).
If the SYNC byte indicates a message receive (nRF24AP2->host), the additional message bytes
will be transmitted the same way as the SYNC byte.
If the SYNC byte indicates a message transmit (host->nRF24AP2), the host must output its data
to nRF24AP2 SIN at the clock rate provided by nRF24AP2 SCLK.
1.
2.
3.
4.
5.
Data is transmitted least-significant-bit (LSB) first.
5.3.4
Synchronous messaging with byte flow control
Byte flow-control mode is used when a synchronous hardware serial port is available.
The host MCU flow-control signal SRDY must be toggled for each byte and can either be implemented with
a software controlled I/O line, or in some cases may be controlled by the host’s hardware serial port. Data
bits change state on the falling edge of SCLK and are read on the rising edge of SCLK. This is true for
transactions in either direction.
The first byte in the transaction sequence is always sent from nRF24AP2 to the host MCU. The first bit of
the first byte dictates the direction for the remaining bytes in the transaction.
Figure 18. on page 29 and Figure 19. on page 30 show transactions between the host and nRF24AP2 in
byte synchronous mode.
nRF24AP2
Host MCU
MESSAGE_READY
MRDY (in)
SYNC_ENABLE
SEN (out)
SERIAL_READY
SRDY (in)
SCLK (out)
SERIAL_CLK
SERIAL_IN
0 0 1 0 0 1 0 1
CHECKSUM
SOUT (out)
SIN (in)
SERIAL_OUT
WRITE FLAG
Figure 18. nRF24AP2 → host transaction
The nRF24AP2 asserts SEN and waits for the host to assert SRDY . Once both SEN and SRDY have been
asserted, nRF24AP2 will send the SYNC byte from SOUT.
For hardware SRDY , this signal will be de-asserted on the first SCLK transition, if a software controlled I/O
line is used for SRDY, it only needs to stay asserted for 2.5 µs minimum before the host can de-assert it
again. The LSB of the SYNC byte will notify the host of the message direction (that is to say,
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29
nRFAP2 Product Specification
nRF24AP2 -> host), and once ready, the host will once again assert SRDY to receive the next message
byte from nRF24AP2. After the last message byte, SRDY must remain de-asserted until the next message
transaction is requested.
The process for nRF24AP2 to host transactions with software SRDY (Figure 21.) is very similar as for
hardware SRDY . The sole difference is that the host can just pulse SRDY and does not have to wait until
the first SCLK transition.
Host MCU
nRF24AP2
MESSAGE_READY
MRDY (in)
SYNC_ENABLE
SEN (out)
SERIAL_READY
SRDY (in)
SCLK (out)
SERIAL_CLK
SERIAL_IN
1 0 1 0 0 1 0 1
SOUT (out)
CHECKSUM
SERIAL_OUT
SIN (in)
READ FLAG
Figure 19. Host → nRF24AP2 transaction
For host to nRF24AP2 transactions with hardware SRDY (See Figure 19.) the process is very similar. The
main difference is that the host first asserts MRDY to inform nRF24AP2 that it wished to send a message.
nRF24AP2 will respond by asserting SEN and then waiting for the host to assert SRDY . Once both SEN and
SRDY have been asserted, nRF24AP2 will the send the SYNC byte. For hardware SRDY , this signal will be
de-asserted on the first SCLK transition. The first bit of the SYNC byte will notify the host of the message
direction (meaning host-> nRF24AP2), and the host will once again assert SRDY and then send the next
message byte to nRF24AP2 on host SOUT at the rate of SCLK. Again, the hardware SRDY will de-assert on
the first SCLK transition and re-assert after each byte until the entire message has been transferred. After
the last message byte, SRDY will remain de-asserted until the next message transaction is requested.
The process for host to nRF24AP2 transactions with software SRDY (See Figure 19.) is very similar as for
hardware SRDY . The only difference is that the host can pulse SRDY and does not have to wait until the
first SCLK transition.
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nRFAP2 Product Specification
5.3.5
Synchronous timing with byte flow control
Synchronous mode with byte flow is compatible with a host microcontroller, hardware SPI slave,
configured as mode 3 and polarity 1. In Figure 20. signals to the left indicate pins on the host MCU. Signals
on the right-hand side indicate pins on nRF24AP2. Shaded areas indicate “don’t care” values.
Host MCU
SERIAL_READY
nRF24AP2
tSRDYMinLow
SRDY (in)
tResponsMax
tch
tcl
SCLK (out)
SERIAL_CLK
tdh
tdc
SERIAL_OUT
C7
C6
SIN (in)
C0
tcd
SERIAL_IN
S7
SOUT (out)
S0
Figure 20. Synchronous byte flow timing
Symbol
Parameter (condition)
Notes
SCLKfrequency Synchronous clock frequency (byte
mode)
Data to SCK Setup (byte mode)
tdc
tdh
SCK to Data Hold (byte mode)
SCK to Data Valid (byte mode)
tcd
tcl
SCK Low Time (byte mode)
SCK High Time (byte mode)
tch
tSRDY MinLow
Minimum SRDY low time
tReset
Synchronous reset. SRDY falling edge
to MRDY falling edge
a
Power on reset time (supply rise time
tPOR
not included)
a
tSoftReset Software reset (synchronous reset
suspend reset and reset command)
tResponseMax Time the nRF24AP2 will take to
respond to input signal
Min
Typ
500
Max
100
20
60
900
900
2.5
1000
1000
250
Units
kHz
ns
ns
ns
ns
ns
µs
µs
2.0
ms
1.5
ms
1.0
ms
a. Defines the time before the host MCU can start to configure the nRF24AP2 after a reset.
Table 6. Synchronous serial timing
5.3.6
Synchronous messaging with bit flow control
If no hardware serial port is available on the host MCU, nRF24AP2 can still be controlled using bit flow
control. Using this method, the serial lines are implemented with software controlled I/O lines. All of the
signaling at the message transaction level remains the same as above. However, instead of pulsing after
every byte, SRDY is pulsed for each bit of the message as shown below in Figure 21. on page 32.
Revision 1.2
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nRFAP2 Product Specification
Host MCU
nRF24AP2
SCLK (out)
SERIAL_CLK
SERIAL_READY
SRDY (in)
SERIAL_IN
D0
D1
D2
Host
Read
Host
Read
Host
Read
D3
Host
Read
D6
D7
Host
Read
Host
Read
D5
D4
Host
Read
Host
Read
SOUT (out)
Figure 21. nRF24AP2 → host transaction
Host MCU
nRF24AP2
SCLK (out)
SERIAL_CLK
SRDY (in)
SERIAL_READY
SERIAL_OUT
D0
D1
D2
D3
D5
D4
D7
D6
SIN (in)
Figure 22. Host → nRF24AP2 transaction
It is important to note that the host MCU will do all bit processing on the rising edge of the SCLK signal, with
the exception being when the byte is being transmitted from the host MCU to nRF24AP2, where the first
data bit will need to be asserted prior to the first clock edge. The final rising edge of the byte transaction will
be the event to drive byte processing.
Host MCU
nRF24AP2
tResponseMax
SCLK (out)
SERIAL_CLK
SRDY (in)
SERIAL_RDY
tSRDYMinLow
SERIAL_IN
SERIAL_OUT
S0
C0
S1
C1
S7
S3
C2
C7
Figure 23. Synchronous bit flow timing
Revision 1.2
32
SOUT (out)
SIN (in)
nRFAP2 Product Specification
5.3.7
Serial enable control
The SEN signal will be asserted by nRF24AP2 prior to all message transmissions. It can therefore be used
as a serial port enable signal, which is useful in cases where the host serial port requires hardware
activation.
nRF24AP2
Host MCU
MESSAGE_READY
MRDY (in)
SYNC_ENABLE
SEN(out)
SERIAL_READY
SRDY (in)
SCLK (out)
SERIAL_CLK
SERIAL_IN
00100101
CHECKSUM
SERIAL_OUT
SIN (in)
WRITE FLAG
Figure 24. Serial enable control using nRF24AP2
Revision 1.2
SOUT (out)
33
nRFAP2 Product Specification
6
On-chip oscillator
In order to provide the necessary clocks for the ANT protocol stack, nRF24AP2 contains one high
frequency oscillator used by the RF transceiver. and two optional low frequency oscillators for ANT
protocol timing. The mandatory, high frequency clock source must be a 16 MHz crystal oscillator. The low
frequency clock source can be generated by a 32.768 kHz crystal oscillator or synthesized 32.768 kHz
from the 16 MHz crystal oscillator clock. External 16 MHz and 32.768 kHz clocks may also be used instead
of the on-chip oscillators of nRF24AP2. For ultra low-power applications, we recommend you use the
32.768 kHz crystal oscillator or provide a 32.768 kHz clock signal, to achieve the lowest possible current
consumption.
6.1
•
•
•
6.2
Features
Low-power, amplitude regulated 16 MHz crystal oscillator
Ultra low-power amplitude regulated 32.768 kHz crystal oscillator
Low power, synthesized 32.768 kHz clock from the 16 MHz crystal oscillator
Block diagrams
Amplitude
regulator
XC1
C1
XC2
Crystal
C2
Figure 25. Block diagram of 16 MHz crystal oscillator
Revision 1.2
34
nRFAP2 Product Specification
Amplitude
regulator
XC32K1
XC32K2
Crystal
C1
C2
Figure 26. Block diagram of 32.768 kHz crystal oscillator
6.3
Functional description
6.3.1
16 MHz crystal oscillator
The 16 MHz crystal oscillator is designed to be used with an AT-cut quartz crystal in parallel resonant
mode. To achieve correct oscillation frequency it is very important that the load capacitance matches the
specification in the crystal datasheet. The load capacitance is the total capacitance from the perspective of
the crystal across its terminals:
C LOAD =
C1' ⋅ C 2'
C1' + C 2'
C1' = C1 + C PCB1 + C PIN
C 2' = C 2 + C PCB 2 + C PIN
C1 and C2 are ceramic SMD capacitors connected between each crystal terminal and VSS, CPCB1 and
CPCB2 are stray capacitances on the PCB, while CPIN is the input capacitance on the XC1 and XC2 pins of
nRF24AP2 (typically 1pF). C1 and C2 should be of the same value, or as close as possible.
To ensure a functional radio link the frequency accuracy must be ± 50 ppm or better. The initial tolerance of
the crystal, drift over temperature, aging and frequency pulling due to incorrect load capacitance must all
be taken into account. For reliable operation the crystal load capacitance, shunt capacitance, equivalent
series resistance (ESR) and drive level must comply with the specifications in Table 9. on page 42. It is
recommended to use a crystal with lower than maximum ESR if the load capacitance and/or shunt
capacitance is high. This will give faster start-up and lower current consumption.
The start-up time is typically about 1 ms for a crystal with 9pF load capacitance and an ESR specification
of 60Ω max. Τhis value is valid for crystals in a 3.2×2.5 mm can. If you use the smallest crystal cans (like
2.0×2.5 mm), pay particular attention to the start-up time of the crystal. These crystals have a longer start
Revision 1.2
35
nRFAP2 Product Specification
up than crystals in larger cans. To make sure the start-up time is 25 MHz
RX selectivity with nRF24AP2 equal modulation on interfering signal (Pin = -67dBm for wanted
signal)
C/ICO
C/I co-channel
12
dBc
st
8
dBc
C/I1ST
1 ACS, C/I 1 MHz
nd
-21
dBc
C/I2ND
2 ACS, C/I 2 MHz
-30
dBc
C/I3RD
3rd ACS, C/I 3 MHz
th
-40
dBc
C/INth
N ACS, C/I f > 6 MHz
C/INth
i
C/INth
-50
Nth ACS, C/I fi > 25 MHz
dBc
RX intermodulation performance in line with Bluetooth specification version 2.0, 4th November
2004, page 42
e
P_IM(3) Input power of IM interferers at 3 and
-36
dBm
6 MHz distance from wanted signal
g
-36
dBm
P_IM(4) Input power of IM interferers at 4 and
8 MHz distance from wanted signal
g
-36
dBm
P_IM(5) Input power of IM interferers at 5 and
10 MHz distance from wanted signal
a. Usable band is determined by local regulations.
b. Data rate in each burst on-air.
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nRFAP2 Product Specification
c. The minimum channel spacing is 1 MHz.
d. Antenna load impedance = 15 Ω + j88 Ω.
e. Wanted signal level at Pin=64 dBm. Two interferers with equal input power are used. The interferer closest in frequency is unmodulated, the other interferer is modulated equal to the wanted signal. The input
power of interferers where the sensitivity equals BER=0.1% is presented.
Table 9. Transceiver characteristics
Symbol
VIH
VIL
VOH
VOL
Parameter (condition)
Input high voltage
Input low voltage
Output high voltage (IOH=0.5mA)
Output low voltage (IOH=0.5mA)
Notes
Min.
0.7×VDD
VSS
VDD-0.3
VSS
Table 10. Digital inputs/outputs
Revision 1.2
42
Typ.
Max.
VDD
0.3×VDD
VDD
0.3
Units
V
V
V
V
nRFAP2 Product Specification
8.1
Current consumption
The power nRF24AP2 consumes depends on the configuration of nRF24AP2, in specific what you use in
the way of serial interface, channel period, master-slave operation and broadcast-, acknowledge- or burst
data.
Table 11. shows peak- and base current consumption for typical applications.
Conditions: VDD = 3.0V, TA = +25ºC
Symbol
IDeepSleep
IIdle
ISuspend
IBase_32kXO
IBase_32kSynt
ISearch
IPeakRX
IPeakTX
IPeakTX-6
IPeakTX-12
IPeakTX-18
Parameter (condition)
Deep Sleep Command
No active channels—no
communications
Asynchronous suspend activated
Notes
Base active current (32.768 kHz
crystal oscillator or 32.768 kHz
external clock source )
Base active current (synthesized
32.768 kHz from 16 MHz)
Search current
Peak RX Current
Peak TX Current at 0 dBm
Peak TX Current at -6 dBm
Peak TX Current at -12 dBm
Peak TX Current at -18 dBm
Min.
ab
bc
bc
bc
bc
Typ.
0.5
2.0
Max.
Units
µA
µA
2.0
µA
3.0
µA
87
µA
2.8
17
15
13
12
11
mA
mA
mA
mA
mA
mA
a. Time of Maximum Current consumption in RX is typical 500 µs and maximum 1 ms.
b. Peak value is typically 1mA higher in asynchronous mode at 57600 baud.
c. Time of maximum TX Only Current is typical 300 µs and maximum 350 µs.
Table 11. Peak- and base current consumption for nRF24AP2
Table 12. shows average current consumption for typical applications and interfaces.
Symbol
Parameter (condition)
IMsq_Rx_ByteSyn Average current per Rx message in
byte sync mode
c
Average current per Rx message in
IMsq_Rx_BitSync bit sync mode
IMsg_Rx_57600 Average current per Rx message in
async mode at 57600 baud
IMsg_Rx_50000 Average current per Rx message in
async mode at 50000 baud
IMsg_Rx_38400 Average current per Rx message in
async mode at 38400 baud
IMsg_Rx_19200 Average current per Rx message in
async mode at 19200 baud
IMsg_Rx_9600 Average current per Rx message in
async mode at 9600 baud
IMsg_Rx_4800 Average current per Rx message in
async mode at 4800 baud
Revision 1.2
43
Notes
Min.
Typ.
21
Max.
Units
µA
30
µA
22
µA
25
µA
31
µA
40
µA
65
µA
115
µA
nRFAP2 Product Specification
Symbol
IMsg_TxAck
_ByteSync
IMsg_TxAck
_BitSync
IMsg_TxAck
_57600
IMsg_TxAck
_50000
IMsg_TxAck
_38400
IMsg_TxAck
_19200
IMsg_TxAck
_9600
IMsg_TxAck
_4800
IMsg_RxAck
_ByteSync
IMsg_RxAck
_BitSync
IMsg_RxAck
_57600
IMsg_RxAck
_50000
IMsg_RxAck
_38400
IMsg_RxAck
_19200
IMsg_RxAck
_9600
IMsg_RxAck
_4800
Parameter (condition)
Notes
Average current per Acknowledged
Tx message in byte sync mode
Average current per Acknowledged
Tx message in bit sync mode
Average current per Acknowledged
Tx message at 57600 baud
Average current per Acknowledged
Tx message at 50000 baud
Average current per Acknowledged
Tx message at 38400 baud
Average current per Acknowledged
Tx message at 19200 baud
Average current per Acknowledged
Tx message at 9600 baud
Average current/Acknowledged Tx
message at 4800 baud
Revision 1.2
44
Typ.
Max.
Units
35
µA
48
µA
54
µA
52
µA
58
µA
72
µA
112
µA
192
µA
26
µA
36
µA
28
µA
29
µA
35
µA
44
µA
69
µA
120
µA
a
17
µA
a
32
µA
a
32
µA
a
28
µA
a
34
µA
a
50
µA
a
90
µA
a
170
µA
Average current/Acknowledged Rx
message in byte sync mode
Average current/Acknowledged Rx
message in bit sync mode
Average current/Acknowledged Rx
message at 57600 baud
Average current/Acknowledged Rx
message at 50000 baud
Average current/Acknowledged Rx
message at 38400 baud
Average current/Acknowledged Rx
message at 19200 baud
Average current/Acknowledged Rx
message at 9600 baud
Average current/Acknowledged Rx
message at 4800 baud
IMsg_Tx_ByteSync Average current/Tx-only message in
byte sync mode
IMsg_Tx_BitSync Average current/Tx-only message in
bit sync mode
IMsg_Tx_57600 Average current/Tx-only message in
async mode at 57600 baud
IMsg_Tx_50000 Average current/Tx-only message in
async mode at 50000 baud
IMsg_Tx_38400 Average current/Tx-only message in
async mode at 38400 baud
IMsg_Tx_19200 Average current/Tx-only message in
async mode at 19200 baud
IMsg_Tx_9600 Average current/Tx-only message in
async mode at 9600 baud
IMsg_Tx_4800 Average current/Tx-only message in
async mode at 4800 baud
Min.
nRFAP2 Product Specification
Symbol
Parameter (condition)
IMsg_TR_ByteSync Average current/Tx message in byte
sync mode
IMsg_TR_BitSync Average current/Tx message in bit
sync mode
IMsg_TR_57600 Average current/Tx message in
async mode at 57600 baud
IMsg_TR_50000 Average current/Tx message in
async mode at 50000 baud
IMsg_TR_38400 Average current/Tx message in
async mode at 38400 baud
IMsg_TR_19200 Average current/Tx message in
async mode at 19200 baud
IMsg_TR_9600 Average current/Tx message in
async mode at 9600 baud
IMsg_TR_4800 Average current/Tx message in async
mode at 4800 baud
IAve
IAve
IAve
IAve
IAve
IAve
IAve
IAve
IAve
IAve
IAve
IAve
IAve
Broadcast Tx at 0.5 Hz in byte sync
mode
Broadcast Tx at 2 Hz in byte sync
mode
Broadcast Rx at 0.5 Hz in byte sync
mode
Broadcast Rx at 2 Hz in byte sync
mode
Acknowledged TX at 0.5 Hz in byte
sync mode
Acknowledged TX at 2 Hz in byte
sync mode
Acknowledged RX at 0.5 Hz in byte
sync mode
Acknowledged RX at 2 Hz in byte
sync mode
Burst continuous at 20 kbps in byte
sync mode
Burst continuous at 7.5 kbps in bit
sync mode
Burst continuous at 20 kbps in async
mode at 57600 baud
Burst continuous at 20 kbps in async
mode at 50000 baud
Burst continuous at 13.8 kbps in
async mode at 38400 baud
Notes
Min.
Typ.
27
Max.
Units
µA
42
µA
42
µA
40
µA
45
µA
60
µA
100
µA
180
µA
b
14
µA
b
54
µA
b
11
µA
b
42
µA
b
18
µA
b
70
µA
b
13
µA
b
52
µA
5.9
mA
6.1
mA
6.3
mA
5.9
mA
5.7
mA
a. Transmit only operation provides no ANT channel management across the air and is not recommended for
normal operation.
b. Does not include base current. See IAve examples below.
Table 12. Average current consumption for typical applications and interfaces
Revision 1.2
45
nRFAP2 Product Specification
8.2
Current calculations examples
By using the values in Table 12. on page 45 together with the formulas presented in this section, you can
calculate the current consumption for a specific application setup. Channel period is defined as the number
of data packets received or transmitted each second.
1.
Master channel with Broadcast data at 0.5 Hz with a byte synchronous serial interface using a
32.768 kHz external clock source.
I Ave = (IMsg _TxByteSync × Message _ Rate) + IBase _ 32kXO
17 μA
× 0.5 message) + 3 μA
message
= 12 μA
=(
2.
Receive channel with Acknowledged data at 2 Hz with an asynchronous serial interface at 57600
baud using a 32.768 kHz external clock source.
I Ave = (IMsg _ RxAck _ 57600 × Message _ Rate) + IBase _ 32kXO
28 μA
× 2 messages ) + 3 μA
message
= 59 μA
=(
3.
Transmit channel at 2 Hz with an asynchronous serial interface at 50000 baud using the internal
clock source .
I Ave = (IMsg _TR _ 50000 × Message _ Rate) + IBase _ 32kSynt
40 μA
× 2 messages) + 87 μA
message
= 167 μA
=(
Revision 1.2
46
nRFAP2 Product Specification
9
Absolute maximum ratings
Maximum ratings are the extreme limits to which nRF24AP2 can be exposed without permanently
damaging it. Exposure to absolute maximum ratings for prolonged periods of time may affect device
reliability.
Note: For operating conditions see Table 7. on page 38.
Operating conditions
Minimum
Maximum
Supply voltages
VDD
-0.3
+3.6
VSS
0
I/O pin voltage
VIO
-0.3
VDD +0.3,
max 3.6
Temperatures
Operating temperature
-40
+85
-40
+85
Storage temperaturea
Units
V
V
V
°C
°C
a. The device can withstand up to 125°C for short periods without
damage. Recommended long-time storage temperature
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