Electronics, Inc.
2590 North First Street, San Jose, CA 95131, U.S.A.
Tel: 408-732-5000
Fax: 408-732-5055
http://www.atpinc.com
Rev. Date: Jan. 22, 2016
ATP A4F08QD8BNPBSE
8GB DDR4-2133 UNBUFFERED ECC SODIMM
DESCRIPTION
The ATP A4F08QD8BNPBSE is a high performance 8GB DDR4-2133 Unbuffered ECC SDRAM memory
module. It is organized as 1024M x 72 in a 260-pin Small Outline Dual-In-Line Memory Module (SODIMM)
package. The module utilizes nine 1024Mx8 DDR4 SDRAMs in FBGA package. The module consists of a
512-byte serial EEPROM, which contains the module configuration information.
KEY FEATURES
High Density: 8GB (1024M x 72)
DIMM Rank: 1 Rank
Cycle Time: 0.93ns (1067MHz)
CAS Latency: 15
Power supply: VDD=1.2V ± 0.06V
VPP=2.5V± 0.125V
VDDSPD=2.2V~3.6V
Support ECC error detection and correction
Nominal and dynamic on-die termination(ODT) for data, strobe, and mask signals
Low-power auto self refresh (LPASR)
Data bus inversion(DBI) for data bus
16 internal banks(x8); 4 groups of 4 banks each
Internal self calibration through ZQ
Temperature controlled refresh (TCR)
Asynchronous Reset
7.8 s refresh interval at lower than TCASE85°C, 3.9s refresh interval at 85°C < TCASE < 95 °C
Support address and command signals parity function
Selectable BC4 or BL8 on-the fly(OTF)
Dynamic On Die Termination
Fly-by topology
Full module heat spreader
PCB Height: 1.18 inches(30mm)
Minimum Thickness of Golden Finger: 30 Micro-inch
RoHS compliant
Part No.
A4F08QD8BNPBSE
Max Freq
1067MHz (0.93ns@CL=15) x2
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Page 1 of 11
Interface
POD12
ATP A4F08QD8BNPBSE
PIN DESCRIPTION
Pin Name
A0~A16
A10/AP
A12/BC_n
BA0,BA1
BG0,BG1
RAS_n
CAS_n
WE_n
CS0_n
CK0_t
CK0_c
CKE0
C0~C2
ODT0
ACT_n
DQ0~DQ63
CB0~CB7
DQS0_t~DQS8_t
DQS0_c~DQS8_c
DQM0 ~DQM8
SCL
SDA
SA0~SA2
PARITY
VDD
VPP
VREFCA
VSS
VDDSPD
ALERT_n
RESET_n
EVENT_n
VTT
VDDQ
ZQ
NC
NF
RFU
Description
Address Inputs
Address Input/Auto precharge
Address Input/Burst chop
SDRAM Bank Address
Bank group address inputs
Row address strobe input
Column address strobe input
Write enable input
Chip Selects
Clock Inputs, positive line
Clock Inputs, negative line
Clock Enables
Chip ID
On-die termination control lines input
Command input: ACT_n indicates an ACTIVATE command.
Data Input /Output
Data check bits Input/Output
Data strobes
Data strobes, negative line
Data Mask
Serial clock for temperature sensor/SPD EEPROM
SPD Data Input /Output
Serial address inputs
Parity for command and address
Power supply
DRAM activating power supply
Reference voltage for control, command, and address pins.
Ground
SPD Power
Alert output
Active LOW asynchronous reset
Temperature sensor Event Output
SDRAM I/O termination supply
DRAM DQ power supply
Reference ball for ZQ calibration
No Connect
No function
Reserved for future use
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Tel. (408) 732-5000 Fax (408) 732-5055
Page 2 of 11
ATP A4F08QD8BNPBSE
PIN ASSIGNMENT
No.
Designation
No.
Designation
No.
Designation
No.
Designation
1
VSS
2
VSS
133
A1
134
EVENT_n
3
DQ5
4
DQ4
135
VDD
136
VDD
5
VSS
6
VSS
137
CK0_t
138
CK1_t
7
DQ1
8
DQ0
139
CK0_c
140
CK1_c
9
VSS
10
VSS
141
VDD
142
VDD
11
DQS0_c
12
DQM0
143
PARITY
144
A0
13
DQS0_t
14
VSS
15
VSS
16
DQ6
145
BA1
146
A10/AP
17
DQ7
18
VSS
147
VDD
148
VDD
KEY
19
VSS
20
DQ2
149
S0_n
150
BA0
21
DQ3
22
VSS
151
WE_n /A14
152
RAS_n/A16
23
VSS
24
DQ12
153
VDD
154
VDD
25
DQ13
26
VSS
155
ODT0
156
CAS_n/A15
27
VSS
28
DQ8
157
S1_n
158
A13
29
DQ9
30
VSS
159
VDD
160
VDD
31
VSS
32
DQS1_c
161
ODT1
162
C0,CS2_n,NC
33
DQM1
34
DQS1_t
163
VDD
164
VREFCA
35
VSS
36
VSS
165
NC,CS3_c,C1
166
SA2
37
DQ15
38
DQ14
167
VSS
168
VSS
39
VSS
40
VSS
169
DQ37
170
DQ36
41
DQ10
42
DQ11
171
VSS
172
VSS
43
VSS
44
VSS
173
DQ33
174
DQ32
45
DQ21
46
DQ20
175
VSS
176
VSS
47
VSS
48
VSS
177
DQS4_c
178
DQM4
49
DQ17
50
DQ16
179
DQS4_t
180
VSS
51
VSS
52
VSS
181
VSS
182
DQ39
53
DQS2_c
54
DQM2
183
DQ38
184
VSS
55
DQS2_t
56
VSS
185
VSS
186
DQ35
57
VSS
58
DQ22
187
DQ34
188
VSS
59
DQ23
60
VSS
189
VSS
190
DQ45
61
VSS
62
DQ18
191
DQ44
192
VSS
63
DQ19
64
VSS
193
VSS
194
DQ41
65
VSS
66
DQ28
195
DQ40
196
VSS
67
DQ29
68
VSS
197
VSS
198
DQS5_c
69
VSS
70
DQ24
199
DQM5
200
DQS5_t
71
DQ25
72
VSS
201
VSS
202
VSS
73
VSS
74
DQS3_c
203
DQ46
204
DQ47
75
DQM3
76
DQS3_t
205
VSS
206
VSS
77
VSS
78
VSS
207
DQ42
208
DQ43
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Page 3 of 11
ATP A4F08QD8BNPBSE
No.
Designation
No.
Designation
No.
Designation
No.
Designation
79
DQ30
80
DQ31
209
VSS
210
VSS
81
VSS
82
VSS
211
DQ52
212
DQ53
83
DQ26
84
DQ27
213
VSS
214
VSS
85
VSS
86
VSS
215
DQ49
216
DQ48
87
CB5
88
CB4
217
VSS
218
VSS
89
VSS
90
VSS
219
DQS6_c
220
DQM6
91
CB1
92
CB0
221
DQS6_t
222
VSS
93
VSS
94
VSS
223
VSS
224
DQ54
95
DQS8_c
96
DQM8
225
DQ55
226
VSS
97
DQS8_t
98
VSS
227
VSS
228
DQ50
99
VSS
100
CB6
229
DQ51
230
VSS
101
CB2
102
VSS
231
VSS
232
DQ60
103
VSS
104
CB7
233
DQ61
234
VSS
105
CB3
106
VSS
235
VSS
236
DQ57
107
VSS
108
RESET_n
237
DQ56
238
VSS
109
CKE0
110
CKE1
239
VSS
240
DQS7_c
111
VDD
112
VDD
241
DQM7
242
DQS7_t
113
BG1
114
ACT_n
243
VSS
244
VSS
115
BG0
116
ALERT_n
245
DQ62
246
DQ63
117
VDD
118
VDD
247
VSS
248
VSS
119
A12/BC_n
120
A11
249
DQ58
250
DQ59
121
A9
122
A7
251
VSS
252
VSS
123
VDD
124
VDD
253
SCL
254
SDA
125
A8
126
A5
255
VDDSPD
256
SA0
127
A6
128
A4
257
VPP
258
VTT
129
VDD
130
VDD
259
VPP
260
SA1
131
A3
132
A2
Note:
1. VPP is 2.5V DC
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Tel. (408) 732-5000 Fax (408) 732-5055
Page 4 of 11
ATP A4F08QD8BNPBSE
FUNCTIONAL BLOCK DIAGRAM (PART1 OF 2)
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Tel. (408) 732-5000 Fax (408) 732-5055
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ATP A4F08QD8BNPBSE
FUNCTIONAL BLOCK DIAGRAM (PART2 OF 2)
CS0_n
ODT0
CKE0
CS0_n
ODT0
CKE0
CKE ODT CS_n
U1
DQS
DQS
DQS0_t
DQS0_c
DQ0~7
CKE ODT CS_n
ZQ
DQ0~7
DQS
DQS
DQS4_t
DQS4_c
VSS
DQ32~39
DQ8~15
DQS
DQS
DQS5_t
DQS5_c
ZQ
DQ0~7
VSS
DQ40~47
DQ16~23
DQS
DQS
DQS6_t
DQS6_c
ZQ
DQ0~7
VSS
DQ48~55
DQ24~31
VSS
DQ56~63
BG[0:1]
BA[0:1]
A0-A16
PARITY,ACT_n
CKE0
ODT0
CS0_n
CK0_t
CK0_c
CKE ODT CS_n
DQS
DQS
DQS8_t
DQS8_c
CB0~7
U7
ZQ
DQ0~7
VSS
Serial PD w/ integrated Thermal sensor
Integrated Thermal sensor in SPD
SDA
SCL
EVENT
EVENT A0
SA0
A1
SA1
DQS
DQS
DQS7_t
DQS7_c
ZQ
DQ0~7
ZQ
VSS
CKE ODT CS_n
U8
DQS
DQS
VSS
U5
DQ0~7
CKE ODT CS_n
DQS3_t
DQS3_c
ZQ
CKE ODT CS_n
U2
DQS
DQS
U3
DQ0~7
CKE ODT CS_n
DQS2_t
DQS2_c
VSS
CKE ODT CS_n
U9
DQS
DQS
ZQ
DQ0~7
CKE ODT CS_n
DQS1_t
DQS1_c
U6
A2
SA2
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Page 6 of 11
VDDSPD
U4
ZQ
DQ0~7
SDRAMs: U1-U9
SDRAMs: U1-U9
SDRAMs: U1-U9
SDRAMs: U1-U9
SDRAMs: U1-U9
SDRAMs: U1-U9
SDRAMs: U1-U9
SDRAMs: U1-U9
SDRAMs: U1-U9
SPD
VPP
All SDRAMs
VDD
All SDRAMs
VREFCA
All SDRAMs
VTT
All SDRAMs
VSS
All SDRAMs
VSS
ATP A4F08QD8BNPBSE
ABSOLUTE MAXIMUM DC RATINGS
Item
Voltage on VDD pin relative to VSS
Voltage on VDDQ pin relative to VSS
Voltage on VPP pin relative to VSS
Voltage on any pin relative to VSS
Storage Temperature
Operating Temperature
Symbol
VDD
VDDQ
VPP
VIN, VOUT
TSTG
TCASE
Rating
-0.4V ~ 1.5V
-0.4V ~ 1.5V
-0.4V ~ 3.0V
-0.4V ~ 1.975V
-55 to +100
0 to +95
Units
V
V
V
V
o
C
o
C
Notes
1,3
1,3
4
1
1,2
1,2
Note:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300 mV of each other at all times;and VREFCA must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500 mV;
VREFCA may be equal to or less than 300 mV
4. VPP must be equal or greater than VDD/VDDQ at all times.
AC & DC OPERATING CONDITIONS
Recommended operating conditions
Item
1,2,3
Supply Voltage
Supply Voltage for Output 1,2,3
DRAM Activating Power Supply3
Input reference voltage command/
address bus
Termination reference voltage (DC) –
command/address bus4
Input High Voltage (DC)
Input High Voltage (AC)
Input Low Voltage (DC)
Input Low Voltage (AC)
Symbol
VDD
VDDQ
VPP
VREFCA(DC)
Min.
1.14
1.14
2.375
0.49 * VDD
Typical
1.2
1.2
2.5
0.50 * VDD
Max.
1.26
1.26
2.75
0.51 * VDD
Units
V
V
V
V
VTT
0.49 * VDD20mA
VREF + 0.075
VREF + 0.1
VSS
-
0.50 * VDD
0.51 * VDD+
20mA
VDD
VREF - 0.075
VREF - 0.1
V
VIH (DC)
VIH (AC)
VIL (DC)
VIL (AC)
-
V
V
V
V
Note:
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
3. DC bandwidth is limited to 20MHz.
4. VTT termination voltages in excess of specification limit will adversely affect command and address signals' voltage margins, and reduce timing margins.
RELIABILITY
MTBF @25 oC (Hours) 1
FIT @ 25 oC 2
MTBF @40 oC (Hours) 1
FIT @ 40 oC2
8,403,575
119
4,213,466
237
Note:
1. The Mean Time between Failures (MTBF) is calculated using a prediction methodology, Bellcore Prediction, which based on reliability data of the individual
components in the module. It assumes nominal voltage, with all other parameters within specified range.
2. Failures per Billion Device-Hours
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Page 7 of 11
ATP A4F08QD8BNPBSE
IDD SPECIFICATION PARAMETER & POWER CONSUMPTION (PART1 OF 2)
Values are for the DDR4 SDRAM only and are computed from values specified in the vendor’s component data sheet)
Symbol
Proposed Conditions
Value
Units
450
mA
63
mA
540
mA
290
mA
310
mA
200
mA
280
mA
420
mA
54
mA
270
mA
1,000
mA
Operating One Bank Active-Precharge Current (AL=0)
IDD0
IPP0
CKE: High; External clock: On; tCK, nRC, nRAS, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: High
between ACT and PRE; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling; Data IO: VDDQ; DM_n:
stable at 1; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode
Registers2; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
Operating One Bank Active-Precharge IPP Current
Same condition with IDD0
Operating One Bank Active-Read-Precharge Current (AL=0)
IDD1
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n:
High between ACT, RD and PRE; Command, Address, Bank Group Address, Bank Address Inputs, Data IO: partially toggling;
DM_n: sta-ble at 1; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode
Registers2; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
Precharge Standby Current (AL=0)
IDD2N
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: stable at 1;
Command, Address, Bank Group Address, Bank Address Inputs: partially toggling ; Data IO: VDDQ; DM_n: stable at 1; Bank
Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: Refer to
Component Datasheet for detail pattern
Precharge Standby ODT Current
IDD2NT
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: stable at 1;
Command, Address, Bank Group Address, Bank Address Inputs: partially toggling ; Data IO: VSSQ; DM_n: stable at 1; Bank
Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: toggling according ; Pattern Details:
Refer to Component Datasheet for detail pattern
Precharge Power-Down Current
IDD2P
CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: stable at 1;
Command, Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: all
banks closed; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0
IDD2Q
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: stable at 1;
Command, Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable at 1;Bank Activity: all
banks closed; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0
Precharge Quiet Standby Current
Active Standby Current
IDD3N
IPP3N
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: stable at 1;
Command, Address, Bank Group Address, Bank Address Inputs: partially toggling ; Data IO: VDDQ; DM_n: stable at 1;Bank
Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details:Refer to
Component Datasheet for detail pattern
Active Standby IPP Current
Same condition with IDD3N
Active Power-Down Current
IDD3P
CKE: Low; External clock: On; tCK, CL: sRefer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: stable at 1;
Command, Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: all
banks open; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0
Operating Burst Read Current
IDD4R
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 82; AL: 0; CS_n: High between RD;
Command, Address, Bank Group Address, Bank Address Inputs: partially toggling ; Data IO: seamless read data burst with different
data between one burst and the next one according ; DM_n: stable at 1; Bank Activity: all banks open, RD commands cycling
through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: Refer
to Component Datasheet for detail pattern
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Page 8 of 11
ATP A4F08QD8BNPBSE
IDD SPECIFICATION PARAMETER & POWER CONSUMPTION (PART2 OF 2)
Values are for the DDR4 SDRAM only and are computed from values specified in the vendor’s component data sheet)
Symbol
Proposed Conditions
Value
Units
840
mA
1,530
mA
189
mA
220
mA
290
mA
170
mA
220
mA
1,470
mA
95
mA
Operating Burst Write Current
IDD4W
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: High between WR;
Command, Address, Bank Group Address, Bank Address Inputs: partially toggling ; Data IO: seamless write data burst with different
data between one burst and the next one ; DM_n: stable at 1; Bank Activity: all banks open, WR commands cycling through banks:
0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at HIGH; Pattern Details: Refer to
Component Datasheet for detail pattern
Burst Refresh Current (1X REF)
IDD5B
IPP5B
CKE: High; External clock: On; tCK, CL, nRFC: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: High
between REF; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling ; Data IO: VDDQ; DM_n: stable at
1; Bank Activity: REF command every nRFC ; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern
Details: Refer to Component Datasheet for detail pattern
Burst Refresh Write IPP Current (1X REF)
Same condition with IDD5B
Self Refresh Current: Normal Temperature Range
IDD6N
TCASE: 0 - 85°C; Low Power Array Self Refresh (LP ASR) : Normal4; CKE: Low; External clock: Off; CK_t and CK_c#: LOW; CL:
Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n#, Command, Address, Bank Group Address, Bank Address,
Data IO: High; DM_n: stable at 1; Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2; ODT
Signal: MID-LEVEL
Self-Refresh Current: Extended Temperature Range)
IDD6E
TCASE: 0 - 95°C; Low Power Array Self Refresh (LP ASR) : Extended4; CKE: Low; External clock: Off; CK_t and CK_c: LOW; CL:
Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n, Command, Address, Bank Group Address, Bank Address,
Data IO: High; DM_n:stable at 1; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in
Mode Registers2; ODT Signal: MID-LEVEL
Self-Refresh Current: Reduced Temperature Range
IDD6R
TCASE: 0 - TBD (~35-45)°C; Low Power Array Self Refresh (LP ASR) : Reduced4; CKE: Low; External clock: Off; CK_t and CK_c#:
LOW; CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n#, Command, Address, Bank Group Address, Bank
Address, Data IO: High; DM_n:stable at 1; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT:
Enabled in Mode Registers2; ODT Signal: MID-LEVEL
Auto Self-Refresh Current
IDD6A
TCASE: 0 - 95°C; Low Power Array Self Refresh (LP ASR) : Auto4;Partial Array Self-Refresh (PASR): Full Array; CKE: Low;
External clock: Off; CK_t and CK_c#: LOW; CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n#, Command,
Address, Bank Group Address, Bank Address, Data IO: High; DM_n:stable at 1; Bank Activity: Auto Self-Refresh operation; Output
Buffer and RTT: Enabled in Mode Registers2; ODT Signal: MID-LEVEL
Operating Bank Interleave Read Current
IDD7
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: Refer to Component Datasheet for detail pattern; BL:
81; AL: CL-1; CS_n: High between ACT and RDA; Command, Address, Bank Group Address, Bank Address Inputs: partially
toggling ; Data IO: read data bursts with different data between one burst and the next one ; DM_n: stable at 1; Bank Activity: two
times interleaved cycling through banks (0, 1, ...7) with different addressing; Output Buffer and RTT: Enabled in Mode Registers2;
ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
IPP7
Operating Bank Interleave Read IPP Current
IDD8
Maximum Power Down Current
36
mA
Power Consumption per DIMM
1,940
mW
PDIMM
Same condition with IDD7
System is operating at 1067MHz clock with VDD = 1.2V. This parameter is calculated at a common loading.
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Page 9 of 11
ATP A4F08QD8BNPBSE
TIMING PARAMETER
Parameter
Symbol
Clock cycle time at CL=15, CWL=11
Internal read command to first data
ACT to internal read or write delay time
PRE command period
ACT to ACT or REF command period
ACTIVE to PRECHARGE command period
Average clock high pulse width
Average clock low pulse width
DQS, DQS to DQ skew, per group, per access
DQ output hold time from DQS, DQS
DQ low-impedance time from CK, CK
DQ high-impedance time from CK, CK
DQS, DQS READ Preamble
DQS, DQS differential READ Postamble
DQS, DQS output high time
DQS, DQS output low time
DQS, DQS WRITE Preamble
DQS, DQS WRITE Postamble
DQS, DQS low-impedance time (Referenced from RL-1)
DQS, DQS high-impedance time (Referenced from RL+BL/2)
DQS, DQS differential input low pulse width
DQS, DQS differential input high pulse width
DQS, DQS rising edge to CK, CK rising edge
DQS, DQS falling edge setup time to CK, CK rising edge
DQS, DQS falling edge hold time to CK, CK rising edge
tCK
tAA
tRCD
tRP
tRC
tRAS
tCH(avg)
tCL(avg)
tDQSQ
tQH
tLZ(DQ)
tHZ(DQ)
tRPRE
tRPST
tQSH
tQSL
tWPRE
tWPST
tLZ(DQS)
tHZ(DQS)
tDQSL
tDQSH
tDQSS
tDSS
tDSH
tDLLK
tRTP
0.938
14.06
14.06
14.06
47.06
33
0.48
0.48
TBD
-360
0.9
TBD
0.4
0.4
0.9
TBD
-360
0.46
0.46
-0.27
0.18
0.18
768
max(4nCK,7.5ns)
tWTR_S
max(2nCK,2.5ns)
DLL locking time
Internal READ Command to PRECHARGE Command delay
Delay from start of internal write trans-action to internal read command for different bank
group
Delay from start of internal write trans-action to internal read command for same bank group
WRITE recovery time
Mode Register Set command cycle time
Mode Register Set command update delay
CAS to CAS command delay for same bank group
Auto precharge write recovery + precharge time
Multi-Purpose Register Recovery Time
ACTIVE to ACTIVE command delay to same bank group for 1KB page size
Four activate window for 1KB page size
Command and Address setup time to CK, CK referenced to Vih(ac) / Vil(ac) levels
Command and Address hold time from CK, CK referenced to Vih(ac) / Vil(ac) levels
Power-up and RESET calibration time
Normal operation Full calibration time
Normal operation short calibration time
tWTR_L
tWR
tMRD
tMOD
tCCD
tDAL
tMPRR
tRRD
tFAW
tIS(base)
tIH(base)
tZQinit
tZQoper
tZQCS
Exit Reset from CKE HIGH to a valid command
tXPR
Exit Power Down with DLL on to any valid command; Exit Precharge Power Down with DLL
frozen to commands not requiring a locked DLL
Asynchronous RTT turn-on delay (Power-Down with DLL frozen)
Asynchronous RTT turn-off delay (Power-Down with DLL frozen)
RTT dynamic change skew
8Gb REFRESH to REFRESH OR REFRESH to ACTIVE command interval
Average periodic refresh interval (0°C ≤ TCASE ≤ 85 °C)
Average periodic refresh interval (85°C ≤ TCASE ≤ 95 °C)
Exit Self Refresh to commands not requiring a locked DLL
Exit Self Refresh to commands requiring a locked DLL
Power Down Entry to Exit Timing
Write leveling output delay
Write leveling output error
Note:
1. Unit ’nCK’ represents one clock cycle of the input clock, counting the actual clock edges.
Your Ultimate Memory Solution!
2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com
Tel. (408) 732-5000 Fax (408) 732-5055
Page 10 of 11
DDR4-2133
Min
Max