AW24P7228BLK0M

Electronics, Inc. 2590 North First Street, San Jose, CA 95131, U.S.A. Tel: 408-732-5000 Fax: 408-732-5055 http://www.atpinc.com Rev. Date: Nov. 26, 2015 ATP AW24P7228BLK0M 8GB DDR3-1600 UNBUFFERED ECC SODIMM DESCRIPTION The ATP AW24P7228BLK0M is a high performance 8GB DDR3-1600 Unbuffered ECC SODIMM SDRAM memory module. It is organized as 1024M x 72 in a 204-pin Small Outline Dual-In-Line Memory Module (SODIMM) package. The module utilizes eighteen 512Mx8 DDR3 SDRAMs in FBGA package. The module consists of a 256-byte serial EEPROM, which contains the module configuration information. KEY FEATURES  High Density: 8GB (1024M x 72)  DIMM Rank: 2 Ranks  Cycle Time: 1.25ns (800MHz)  CAS Latency: 11  Power supply: 1.35V(1.28V~1.45V) Backward compatible to 1.5V ±0.075V  Internal self calibration through ZQ  On-board I2C temperature sensor with integrated (SPD) EEPROM  Burst lengths: 8  Auto & Self refresh Part No. AW24P7228BLK0M        Asynchronous Reset Minimum Thickness of Golden Finger: 30 Micro-inch 7.8 s refresh interval at lower than TCASE 85°C, 3.9s refresh interval at 85°C < TCASE < 95 °C Dynamic On Die Termination Fly-by topology PCB Height: 1.18 inches RoHS compliant Max Freq 800MHz (1.25ns@CL=11) x2 Interface SSTL_15 PIN DESCRIPTION Pin Name Description Pin Name Description A0~A9, A11,A13~A15 A10/AP BA0~BA2 CAS CK0~CK1 CK0 ~ CK1 CKE0,CKE1 DM0~DM8 DQ0~DQ63 DQS0~DQS8 Address Inputs Address Input/Auto precharge SDRAM Bank Address Column Address Strobe Clock Inputs, positive line Clock Inputs, negative line Clock Enables Data Masks Data Input/Output Data strobes ODT0,ODT1 RAS CS0 , CS1 SA0~SA1 SCL SDA VDD VDDSPD VSS RESET On die termination Row Address Strobe Chip Selects SPD address Serial Presence Detect (SPD) Clock Input SPD Data Input/Output Core Power SPD Power Ground This signal resets the DDR3 SDRAM DQS0 ~ DQS8 VREFDQ REFCA A12/ BC VTT CB0~CB7 Data strobes, negative line Input/Output Reference Address Input/Burst chop Termination voltage DIMM ECC Check bits WE Event NC Write Enable Temperature sensor Event output No Connect Logic Analyzer specific test pin (No connect on SO-DIMM) TEST Your Ultimate Memory Solution! Page 1 of 7 ATP AW24P7228BLK0M PIN ASSIGNMENT No. Designation No. Designation No. Designation No. Designation 1 3 5 7 9 VREFDQ VSS DQ0 DQ1 VSS 2 4 6 8 10 105 107 109 111 113 A2 BA1 VDD CK1 DM0 DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1 DQS1 VSS 12 14 16 18 20 22 24 26 28 30 116 118 120 122 124 126 128 130 132 134 CK1 VDD NC NC RAS VDD ODT0 ODT1 A13 VDD DQ36 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2 DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 DM3 VSS DQ26 DQ27 VSS CB0 CB1 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 RESET VSS DQ14 DQ15 VSS DQ20 DQ21 DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3 DQS3 VSS DQ30 DQ31 VSS CB4 115 117 119 121 123 125 127 129 131 133 A1 A0 VDD CK0 CK0 VDD A10/AP BA0 WE VDD CAS CS0 CS1 VDD DQ32 106 108 110 112 114 11 13 15 17 19 21 23 25 27 29 VSS DQ4 DQ5 VSS DQS0 DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 73 75 VSS 74 76 CB5 DM8 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 DQ33 VSS DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6 DQS6 VSS DQ50 DQ51 VSS 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 DQ37 VSS DM4 DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5 DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 DQ54 DQ55 VSS DQ60 DQ61 78 80 82 84 86 88 90 92 VSS CB6 CB7 VREFCA VDD A15 A14 A9 183 185 187 189 191 193 195 197 DQ56 DQ57 VSS DM7 DQ58 DQ59 VSS SA0 184 186 188 190 192 194 196 198 VSS DQS7 DQS7 VSS DQ62 DQ63 VSS 94 96 VDD A11 199 201 VDDSPD SA1 200 202 SCL 98 100 102 104 A7 A6 VDD A4 203 VTT 204 VTT 77 79 81 83 85 87 89 91 93 95 97 99 101 103 DQS8 DQS8 VSS CB2 CB3 VDD CKE0 CKE1 BA2 VDD A12/ BC A8 A5 VDD A3 Event SDA Notes:1. This address might be connected to NC balls of the DRAMs (depending on density); either way they will be connected to the termination resistor. Your Ultimate Memory Solution! 2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com Tel. (408) 732-5000 Fax (408) 732-5055 Page 2 of 7 ATP AW24P7228BLK0M FUNCTIONAL BLOCK DIAGRAM VTT VTT VDD VDD ZQ U4 VDDSPD DQ0~7 ZQ SPD CS CAS RAS WE ODT CK CK CKE A[14:0]/BA[2:0] CS CAS RAS WE ODT CK CK CKE A[14:0]/BA[2:0] ZQ DQ0~7 U15 DQ48~55 ZQ U13 CS CAS RAS WE ODT CK CK CKE A[14:0]/BA[2:0] ZQ DQ0~7 ZQ DQS5 DQS5 DM5 DQ40~47 CS CAS RAS WE ODT CK CK CKE A[14:0]/BA[2:0] DQ0~7 DQS4 DQS4 DM4 U16 CS CAS RAS WE ODT CK CK CKE A[14:0]/BA[2:0] U7 CS CAS RAS WE ODT CK CK CKE A[14:0]/BA[2:0] ZQ DQ32~39 ODT1 CK1 CK1 CKE1 CS CAS RAS WE ODT CK CK CKE A[14:0]/BA[2:0] DQ0~7 DQ0~7 U17 DQS DQS DM DQ0~7 DQS DQS DQS DQS DM ZQ DQS DQS DM U8 DQS DQS DM ZQ DQS DQS DM DQS DQS DM DQ0~7 CB0~CB7 DQS DQS DM CS CAS RAS WE ODT CK CK CKE A[14:0]/BA[2:0] ZQ U18 DQ0~7 ZQ DQS DQS DM U6 DQ0~7 ZQ U5 U14 CS CAS RAS WE ODT CK CK CKE A[14:0]/BA[2:0] DQ24~31 U3 DQ0~7 ZQ U12 DQS DQS DM ZQ DQ0~7 U11 DQS DQS DM DQ0~7 U9 CS CAS RAS WE ODT CK CK CKE A[14:0]/BA[2:0] DQS3 DQS3 DM3 U2 ZQ CS CAS RAS WE ODT CK CK CKE A[14:0]/BA[2:0] DQ16~23 DQS DQS DM DQ0~7 DQ0~7 CS CAS RAS WE ODT CK CK CKE A[14:0]/BA[2:0] DQS2 DQS2 DM2 U10 DQS DQS DM ZQ CS CAS RAS WE ODT CK CK CKE A[14:0]/BA[2:0] DQ8~15 U1 DQS DQS DM CS CAS RAS WE ODT CK CK CKE A[14:0]/BA[2:0] DQS1 DQS1 DM1 DQ0~7 CS CAS RAS WE ODT CK CK CKE A[14:0]/BA[2:0] DQ0~7 DQS DQS DM CS CAS RAS WE ODT CK CK CKE A[14:0]/BA[2:0] DQS DQS DM CS1 CS0 CAS RAS WE ODT0 CK0 CK0 CKE0 A[14:0]/BA[2:0] ZQ DQS8 DQS8 DM8 CS CAS RAS WE ODT CK CK CKE A[14:0]/BA[2:0] DQ0~7 DQS0 DQS0 DM0 DQS DQS DM CS CAS RAS WE ODT CK CK CKE A[14:0]/BA[2:0] DQS DQS DM DQ0~7 ZQ DQS6 DQS6 DM6 DQS7 DQS7 DM7 DQ56~63 Serial PD w/ integrated Thermal sensor VDD DDR3 SDRAMS U1-U18 VREFDQ DDR3 SDRAMS U1-U18 VREFCA DDR3 SDRAMS U1-U18 VTT DDR3 SDRAMS U1-U18 VSS DDR3 SDRAMS U1-U18 Integrated Thermal sensor in SPD SDA SCL EVENT EVENT A0 SA0 Your Ultimate Memory Solution! 2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com Tel. (408) 732-5000 Fax (408) 732-5055 Page 3 of 7 A1 SA1 A2 SA2 BA0-BA2 DDR3 SDRAMS U1-U18 A0-A15 RAS DDR3 SDRAMS U1-U18 DDR3 SDRAMS U1-U18 CAS DDR3 SDRAMS U1-U18 WE DDR3 SDRAMS U1-U18 RESET CK0~CK1 DDR3 SDRAMS U1-U18 CK0~CK1 DDR3 SDRAMS U1-U18 DDR3 SDRAMS U1-U18 ATP AW24P7228BLK0M ABSOLUTE MAXIMUM DC RATINGS Item Voltage on VDD pin relative to VSS Voltage on VDDQ pin relative to VSS Voltage on any pin relative to VSS Storage Temperature Operating Temperature Symbol Rating Units Notes VDD VDDQ VIN, VOUT TSTG TCASE -0.4V ~ 1.975V -0.4V ~ 1.975V -0.4V ~ 1.975V -55 to +100 0 to +95 V V V o C o C 1 1 1 1 1,2,3 Note: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. It is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3. At 85 - 95 oC operation temperature range, doubling refresh commands in frequency to a 32ms period ( Refresh interval =3.9 µs ) is required, and to enter to self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate. AC & DC OPERATING CONDITIONS (SSTL-15) Recommended operating conditions Item Supply Voltage Supply Voltage for Output 4 VREF CA(DC) VREF DQ(DC) Input High Voltage (DC) Input High Voltage (AC) Input Low Voltage (DC) Input Low Voltage (AC) Symbol Min. Typical Max. Units VDD VDDQ I/O I/O VIH (DC) VIH (AC) VIL (DC) VIL (AC) 1.283 1.283 0.49 * VDD 0.49 * VDD VREF + 0.09 VREF + 0.135 VSS - 1.35 1.35 0.50 * VDD 0.50 * VDD - 1.45 1.45 0.51 * VDD 0.51 * VDD VDD VREF - 0.09 VREF - 0.135 V V V V V V V V Note: 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. 2. Peak to peak AC noise on VREF may not exceed 2% VREF (DC). 3. VTT of transmitting device must track VREF of receiving device. 4. AC parameters are measured with VDD, VDDQ and VDDL tied together. RELIABILITY MTBF @25 oC (Hours) 1 FIT @ 25 oC 2 MTBF @40 oC (Hours) 1 FIT @ 40 oC2 8,665,000 115 4,458,000 224 Note: 1. The Mean Time between Failures (MTBF) is calculated using a prediction methodology, Bellcore Prediction, which based on reliability data of the individual components in the module. It assumes nominal voltage, with all other parameters within specified range. 2. Failures per Billion Device-Hours Your Ultimate Memory Solution! 2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com Tel. (408) 732-5000 Fax (408) 732-5055 Page 4 of 7 ATP AW24P7228BLK0M IDD SPECIFICATION PARAMETER & POWER CONSUMPTION (IDD values are for full operating range of Voltage and Temperature) Symbol Proposed Conditions Value Units 400 mA 540 mA 180 mA 200 mA 290 mA 360 mA 270 mA 270 mA 330 mA 960 mA 1,060 mA 1,520 mA 270 mA 1,320 mA 2,060 mW Operating one bank active-precharge current; IDD0 CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Timing table ; BL: 8; AL: 0;/ CS: High between ACT and PRE; Command, Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,...; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0; Operating one bank active-read-precharge current; IDD1 CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Timing table ; BL: 8; AL: 0; /CS: High between ACT, RD and PRE; Command, Address, Bank Address Inputs, Data IO: partially toggling ; DM:stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,...; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0; Precharge Power-Down Current Slow Exit IDD2P0 CKE: Low; External clock: On; tCK, CL: see Timing table ; BL: 8; AL: 0; /CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pre-charge Power Down Mode: Slow Exit Precharge Power-Down Current Fast Exit IDD2P1 CKE: Low; External clock: On; tCK, CL: see Timing table; BL: 81); AL: 0; /CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0; Pre-charge Power Down Mode: Fast Exit Precharge standby current; IDD2N CKE: High; External clock: On; tCK, CL: see Timing table ; BL: 8; AL: 0; /CS: stable at 1; Command, Address, Bank Address Inputs: partially tog-gling; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0; Precharge Standby ODT Current IDD2NT CKE: High; External clock: On; tCK, CL: see Timing table ; BL: 8; AL: 0; /CS: stable at 1; Command, Address, Bank Address Inputs: partially tog-gling ; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers Precharge quiet standby current; IDD2Q CKE: High; External clock: On; tCK, CL: see Timing table; BL: 8; AL: 0; /CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0 IDD3P CKE: Low; External clock: On; tCK, CL: see Timing table ; BL: 8; AL: 0; /CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0 IDD3N CKE: High; External clock: On; tCK, CL: see Timing table ; BL: 8; AL: 0; /CS: stable at 1; Command, Address, Bank Address Inputs: partially tog-gling ; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0; Active Power-Down Current Active Standby Current Operating Burst Read Current IDD4R CKE: High; External clock: On; tCK, CL: see Timing table; BL: 8; AL: 0; /CS: High between RD; Command, Address, Bank Address Inputs: par-tially toggling ; Data IO: seamless read data burst with different data between one burst and the next one; DM:stable at 0; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0; Operating Burst Write Current IDD4W CKE: High; External clock: On; tCK, CL: see Timing table ; BL: 8; AL: 0; CS: High between WR; Command, Address, Bank Address Inputs: par-tially toggling ; Data IO: seamless write data burst with different data between one burst and the next one; DM: stable at 0; Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,...; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at HIGH; Burst Refresh Current IDD5B CKE: High; External clock: On; tCK, CL, nRFC: see Timing table ; BL: 8; AL: 0; CS: High between REF; Command, Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING;DM:stable at 0; Bank Activity: REF command every nRFC; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0; Self Refresh Current: Normal Temperature Range TCASE: 0 - 85°C; IDD6 Auto Self-Refresh (ASR): Disabled; Self-Refresh Temperature Range (SRT): Normale); CKE: Low; External clock: Off; CK and CK: LOW; CL: see Timing table ; BL: 8; AL: 0; /CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0; Bank Activity: Self- Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: FLOATING Operating Bank Interleave Read Current IDD7 PDIMM CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see Timing table ; BL: 8; AL: CL-1; /CS: High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling; Data IO: read data bursts with different data between one burst and the next one ; DM:stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0; Power Consumption per DIMM System is operating at 800 MHz clock with VDD = 1.35V. This parameter is calculated at a common loading. Your Ultimate Memory Solution! 2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com Tel. (408) 732-5000 Fax (408) 732-5055 Page 5 of 7 ATP AW24P7228BLK0M TIMING PARAMETER Parameter Symbol Clock cycle time at CL=11, CWL=8 Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACTIVE to PRECHARGE command period Average high pulse width Average low pulse width DQS, DQS to DQ skew, per group, per access DQ output hold time from DQS, DQS DQ low-impedance time from CK, CK DQ high-impedance time from CK, CK Data setup time to DQS, DQS referenced to Vih(ac)Vil(ac) levels Data hold time to DQS, DQS referenced to Vih(ac)Vil(ac) levels DQS, DQS READ Preamble DQS, DQS differential READ Postamble DQS, DQS output high time DQS, DQS output low time DQS, DQS WRITE Preamble DQS, DQS WRITE Postamble DQS, DQS rising edge output access time from rising CK， CK DQS, DQS low-impedance time (Referenced from RL-1) DQS, DQS high-impedance time (Referenced from RL+BL/2) DQS, DQS differential input low pulse width DQS, DQS differential input high pulse width DQS, DQS rising edge to CK, CK rising edge DQS, DQS falling edge setup time to CK, CK rising edge DQS, DQS falling edge hold time to CK, CK rising edge DLL locking time Internal READ Command to PRECHARGE Command delay Delay from start of internal write transaction to internal read command WRITE recovery time Mode Register Set command cycle time Mode Register Set command update delay CAS to CAS command delay Auto precharge write recovery + precharge time Multi-Purpose Register Recovery Time ACTIVE to ACTIVE command period for 1KB page size Four activate window for 1KB page size Command and Address setup time to CK, CK referenced to Vih(ac) / Vil(ac) levels Command and Address hold time from CK, CK referenced to Vih(ac) / Vil(ac) levels Power-up and RESET calibration time Normal operation Full calibration time Normal operation short calibration time Exit Reset from CKE HIGH to a valid command Exit Power Down with DLL on to any valid command; Exit Precharge Power Down with DLL frozen to commands not requiring a locked DLL Asynchronous RTT turn-on delay (Power-Down with DLL frozen) Asynchronous RTT turn-off delay (Power-Down with DLL frozen) ODT turn-on RTT_NOM and RTT_WR turn-off time from ODTLoff reference RTT dynamic change skew 4Gb REFRESH to REFRESH OR REFRESH to ACTIVE command interval Average periodic refresh interval (0°C ≤ TCASE ≤ 85 °C) Average periodic refresh interval (85°C ≤ TCASE ≤ 95 °C) Exit Self Refresh to commands not requiring a locked DLL Exit Self Refresh to commands requiring a locked DLL Power Down Entry to Exit Timing Write leveling output delay Write leveling output error tCK tAA tRCD tRP tRC tRAS tCH(avg) tCL(avg) tDQSQ tQH tLZ(DQ) tHZ(DQ) tDS(base) tDH(base) tRPRE tRPST tQSH tQSL tWPRE tWPST tDQSCK tLZ(DQS) tHZ(DQS) tDQSL tDQSH tDQSS tDSS tDSH tDLLK tRTP tWTR tWR tMRD tMOD tCCD tDAL tMPRR tRRD tFAW tIS(base) tIH(base) tZQinitI tZQoper tZQCS tXPR tXP tAONPD tAOFPD tAON tAOF tADC tRFC tREFI tREFI tXS tXSDLL tPD tWLO tWLOE DDR3-1600 min 1.25 13.75(13.1252) 13.75(13.1252) 13.75(13.1252) 48.75(48.1252) 35 0.47 0.47 0.38 -450 10 45 0.9 0.3 0.4 0.4 0.9 0.3 -225 -450 0.45 0.45 -0.27 0.18 0.18 512 max(4nCK,7.5ns) max (4nCK,7.5ns) 15 4 max(12nCK,15ns) 4 tWR + roundup (tRP / tCK) 1 max(4nCK,6ns) 30 45 120 512 256 64 max(5nCK, tRFC+ 10ns) 2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com Tel. (408) 732-5000 Fax (408) 732-5055 Page 6 of 7