AL24P72L8BLK0M

Electronics, Inc. 2590 North First Street, San Jose, CA 95131, U.S.A. Tel: 408-732-5000 Fax: 408-732-5055 http://www.atpinc.com Rev. Date: Dec. 03, 2015 ATP AL24P72L8BLK0M 8GB DDR3-1600 REGISTERED ECC DIMM DESCRIPTION The ATP AL24P72L8BLK0M is a high performance 8GB DDR3-1600 Registered ECC SDRAM memory module. It is organized as 1024M x 72 in a 240-pin Dual-In-Line Memory Module (DIMM) package. The module utilizes eighteen 512Mx8 DDR3 SDRAMs in FBGA package. The module consists of a 256-byte serial EEPROM, which contains the module configuration information. KEY FEATURES  High Density: 8GB (1024M x 72)  DIMM Rank: 2 Ranks  Cycle Time: 1.25ns (800MHz)  CAS Latency: 11  Power supply: 1.35V(1.28V~1.45V) Backward compatible to 1.5V ±0.075V  Internal self calibration through ZQ  Burst lengths: 8  On-board I2C temperature sensor with integrated (SPD) EEPROM  Auto & Self refresh  Asynchronous Reset Part No. AL24P72L8BLK0M        Minimum Thickness of Golden Finger: 30 Micro-inch 7.8 s refresh interval at lower than TCASE 85°C, 3.9s refresh interval at 85°C < TCASE < 95 °C Support address and command signals parity function Dynamic On Die Termination Fly-by topology PCB Height: 0.74 inches RoHS compliant Max Freq 800MHz (1.25ns@CL=11) x2 Interface SSTL_15 PIN DESCRIPTION Pin Name Description Pin Name Description A0~A9, A11~A15 A10/AP BA0~BA2 Address Inputs Address Input/Auto precharge SDRAM Bank Address Column Address Strobe Data check bits Input/Output Clock Inputs, positive line Clock Inputs, negative line Clock Enables Data Masks Temperature sensor Event output Data Input/Output Data strobes Data strobes, negative line ODT0, ODT1 Par_In RAS RESET WE CS0 , CS1 SA0~SA2 SCL SDA TEST VDD VDDQ ,VDDSPD VREFDQ ,VREFCA On die termination Parity bit for the Address and Control bus Row Address Strobe Register and PLL control pin Write Enable Chip Selects SPD address Serial Presence Detect (SPD) Clock Input SPD Data Input/Output Memory bus test tool Core Power I/O Power, SPD Power Reference Voltage for DQ ,CA Termination Data Strobe Termination Data Strobe, negative line Parity error found in the Address and Control bus VSS NC RFU VTT Ground No Connect Reserved for Future Use Termination Voltage CAS CB0~CB7 CK0 CK0 CKE0, CKE1 DM0~DM8 Event DQ0~DQ63 DQS0~DQS8 DQS0 ~ DQS8 TDQS9~TDQS17 TDQS9 ~ TDQS17 Err_Out Your Ultimate Memory Solution! Page 1 of 7 ATP AL24P72L8BLK0M PIN ASSIGNMENT No. Designation 1 2 3 4 5 6 VREFDQ VSS DQ0 DQ1 VSS 7 8 9 10 11 12 13 14 15 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 DQS0 DQS1 DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2 DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DQS3 DQS3 VSS DQ26 DQ27 VSS CB0 CB1 VSS DQS8 DQS8 VSS CB2 CB3 VSS VTT VTT CKE0 VDD BA2 ERR_OUT VDD A11 A7 VDD A5 A4 VDD No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 KEY 169 170 171 172 173 174 175 176 177 178 179 180 Designation VSS DQ4 DQ5 VSS TDQS9 TDQS9 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS TDQS10 TDQS10 VSS DQ14 DQ15 VSS DQ20 DQ21 VSS TDQS11 TDQS11 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS TDQS12 TDQS12 VSS DQ30 DQ31 VSS CB4 CB5 VSS TDQS17 TDQS17 VSS CB6 CB7 VSS NC (TEST) RESET CKE1 VDD A15 A14 VDD A12/ BC A9 VDD A8 A6 VDD A3 No. Designation No. Designation 61 62 63 64 65 66 A2 VDD NC NC VDD VDD 181 182 183 184 185 186 A1 VDD VDD CK0 CK0 VDD 67 68 69 70 71 72 73 74 75 VREFCA PAR_IN VDD A10/AP BA0 VDD WE CAS VDD 187 188 189 190 191 192 193 194 195 EVENT A0 VDD BA1 VDD RAS CS0 VDD ODT0 76 77 78 79 80 81 82 83 84 CS1 ODT1 VDD NC VSS DQ32 DQ33 VSS DQS4 196 197 198 199 200 201 202 203 204 A13 VDD NC VSS DQ36 DQ37 VSS TDQS13 85 86 87 88 89 90 91 92 93 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DQS5 205 206 207 208 209 210 211 212 213 94 95 96 97 98 99 100 101 102 214 215 216 217 218 219 220 221 222 103 104 105 106 107 108 DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 223 224 225 226 227 228 TDQS14 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS TDQS15 TDQS15 VSS DQ54 DQ55 VSS DQ60 DQ61 109 110 111 112 113 114 115 DQ57 VSS DQS7 DQS7 VSS DQ58 DQ59 229 230 231 232 233 234 235 VSS TDQS16 TDQS16 VSS DQ62 DQ63 VSS 116 117 118 119 120 VSS SA0 SCL SA2 VTT 236 237 238 239 240 VDDSPD SA1 SDA VSS VTT Your Ultimate Memory Solution! 2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com Tel. (408) 732-5000 Fax (408) 732-5055 Page 2 of 7 TDQS13 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS TDQS14 ATP AL24P72L8BLK0M DQS8 DQS8 TDQS17 TDQS17 CB0~7 DQS DQS TDQS TDQS DQ0~7 ZQ U9 DQS DQS TDQS TDQS DQ0~7 RODT1B RCK1B RCK1B RCKE1B RCS1B CS CAS RAS WE ODT CK CK CKE A[12:0]/BA[2:0] CS CAS RAS WE ODT CK CK CKE A[12:0]/BA[2:0] RCS0B RCASB RRASB RWEB RODT0B RCK0B RCK0B RCKE0B RA[13:0]B/RBA[2:0]B U15 DQS DQS TDQS TDQS DQ0~7 CS CAS RAS WE ODT CK CK CKE A[12:0]/BA[2:0] ZQ DQS DQS TDQS TDQS DQ0~7 DQS DQS TDQS TDQS DQ0~7 U16 DQS DQS TDQS TDQS DQ0~7 DQS DQS TDQS TDQS DQ0~7 U17 U6 ZQ U7 ZQ U8 ZQ ZQ ZQ ZQ CS CAS RAS WE ODT CK CK CKE A[12:0]/BA[2:0] U4 CS CAS RAS WE ODT CK CK CKE A[12:0]/BA[2:0] ZQ CS CAS RAS WE ODT CK CK CKE A[12:0]/BA[2:0] DQS DQS TDQS TDQS DQ0~7 ZQ CS CAS RAS WE ODT CK CK CKE A[12:0]/BA[2:0] CS CAS RAS WE ODT CK CK CKE A[12:0]/BA[2:0] U3 DQS DQS TDQS TDQS DQ0~7 ZQ DQS DQS TDQS TDQS DQ0~7 CS CAS RAS WE ODT CK CK CKE A[12:0]/BA[2:0] CS CAS RAS WE ODT CK CK CKE A[12:0]/BA[2:0] DQS DQS TDQS TDQS DQ0~7 ZQ U14 U5 ZQ CS CAS RAS WE ODT CK CK CKE A[12:0]/BA[2:0] RODT1A RCK1A RCK1A RCKE1A U13 DQS7 DQS7 TDQS16 TDQS16 DQ56~63 CS CAS RAS WE ODT CK CK CKE A[12:0]/BA[2:0] U12 DQS6 DQS6 TDQS15 TDQS15 DQ48~55 CS CAS RAS WE ODT CK CK CKE A[12:0]/BA[2:0] U2 DQS DQS TDQS TDQS DQ0~7 ZQ DQS DQS TDQS TDQS DQ0~7 DQS DQS TDQS TDQS DQ0~7 ZQ VTT U18 CS CAS RAS WE ODT CK CK CKE A[12:0]/BA[2:0] DQS3 DQS3 TDQS12 TDQS12 DQ24~31 U11 DQS5 DQS5 TDQS14 TDQS14 DQ40~47 DQS DQS TDQS TDQS DQ0~7 ZQ CS CAS RAS WE ODT CK CK CKE A[12:0]/BA[2:0] DQS2 DQS2 TDQS11 TDQS11 DQ16~23 U10 DQS4 DQS4 TDQS13 TDQS13 DQ32~39 CS CAS RAS WE ODT CK CK CKE A[12:0]/BA[2:0] DQ8~15 U1 DQS DQS TDQS TDQS DQ0~7 DQS DQS TDQS TDQS DQ0~7 ZQ CS CAS RAS WE ODT CK CK CKE A[12:0]/BA[2:0] DQS1 DQS1 TDQS10 TDQS10 DQ0~7 DQS DQS TDQS TDQS DQ0~7 CS CAS RAS WE ODT CK CK CKE A[12:0]/BA[2:0] DQS0 DQS0 TDQS9 TDQS9 RCS1A RCS0A RCASA RRASA RWEA RODT0A RCK0A RCK0A RCKE0A RA[13:0]A/RBA[2:0]A FUNCTIONAL BLOCK DIAGRAM ZQ CS0 RCS0->DDR3 SDRAMs: U1-U9 CS1 RCS1->DDR3 SDRAMs: U10-U18 BA0-BA2 1:2 RBA0-RBA2->DDR3 SDRAMs: U1-U18 A0-A15 R E G I S T E R & P L L RA0-RA15 -> DDR3 SDRAMs: U1-U18 RAS CAS WE CKE0 VTT CKE1 VDDSPD Serial PD w/ integrated Thermal sensor VDD SDRAMS U1-U18 VREFDQ SDRAMS U1-U18 SCL SDA EVENT A0 SA0 A1 SA1 ODT0 ODT1 CK0 Integrated Thermal sensor in SPD EVENT SPD A2 SA2 VREFCA SDRAMS U1-U18 VTT SDRAMS U1-U18 VSS SDRAMS U1-U18 RRAS -> DDR3 SDRAMs: U1-U18 RCAS -> DDR3 SDRAMs: U1-U18 RWE -> DDR3 SDRAMs: U1-U18 RCKE0 -> DDR3 SDRAMs: U1-U9 RCKE1 -> DDR3 SDRAMs: U10-U18 RODT0 -> DDR3 SDRAMs: U1-U9 RODT1 -> DDR3 SDRAMs: U10-U18 PCK0 -> DDR3 SDRAMs: U1-U9 CK0 PCK0 -> DDR3 SDRAMs: U1-U9 CK1 PCK1 -> DDR3 SDRAMs: U10-U18 PCK1 -> DDR3 SDRAMs: U10-U18 CK1 QERR PAR_IN Err_Out RESET RESET:SDRAM U1~U18 Your Ultimate Memory Solution! Page 3 of 7 ATP AL24P72L8BLK0M ABSOLUTE MAXIMUM DC RATINGS Item Voltage on VDD pin relative to VSS Voltage on VDDQ pin relative to VSS Voltage on any pin relative to VSS Storage Temperature Operating Temperature Symbol Rating Units Notes VDD VDDQ VIN, VOUT TSTG TCASE -0.4V ~ 1.975V -0.4V ~ 1.975V -0.4V ~ 1.975V -55 to +150 0 to +95 V V V o C o C 1 1 1 1 1,2,3 Note: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. It is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3. At 85 - 95 oC operation temperature range, doubling refresh commands in frequency to a 32ms period ( Refresh interval =3.9 µs ) is required, and to enter to self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate. AC & DC OPERATING CONDITIONS (SSTL-15) Recommended operating conditions Item Supply Voltage Supply Voltage for Output 4 VREF CA(DC) VREF DQ(DC) Input High Voltage (DC) Input High Voltage (AC) Input Low Voltage (DC) Input Low Voltage (AC) Symbol Min. Typical Max. Units VDD VDDQ I/O I/O VIH (DC) VIH (AC) VIL (DC) VIL (AC) 1.283 1.283 0.49 * VDD 0.49 * VDD VREF + 0.09 VREF + 0.135 VSS - 1.35 1.35 0.50 * VDD 0.50 * VDD - 1.45 1.45 0.51 * VDD 0.51 * VDD VDD VREF - 0.09 VREF - 0.135 V V V V V V V V Note: 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. 2. Peak to peak AC noise on VREF may not exceed 2% VREF (DC). 3. VTT of transmitting device must track VREF of receiving device. 4. AC parameters are measured with VDD, VDDQ and VDDL tied together. RELIABILITY MTBF @25 oC (Hours) 1 FIT @ 25 oC 2 MTBF @40 oC (Hours) 1 FIT @ 40 oC2 5,598,000 178 3,339,000 299 Notes: 1. The Mean Time between Failures (MTBF) is calculated using a prediction methodology, Bellcore Prediction, which based on reliability data of the individual components in the module. It assumes nominal voltage, with all other parameters within specified range. 2. Failures per Billion Device-Hours Your Ultimate Memory Solution! 2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com Tel. (408) 732-5000 Fax (408) 732-5055 Page 4 of 7 ATP AL24P72L8BLK0M IDD SPECIFICATION PARAMETER & POWER CONSUMPTION (IDD values are for full operating range of Voltage and Temperature) Symbol Proposed Conditions Value Units 1,080 mA 1,240 mA 610 mA 630 mA 920 mA 990 mA 880 mA 710 mA 950 mA 1,700 mA 1,820 mA 2,170 mA 280 mA 2,120 mA 2,930 mW Operating one bank active-precharge current; IDD0 CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Timing table ; BL: 8; AL: 0;/ CS: High between ACT and PRE; Command, Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,...; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0; Operating one bank active-read-precharge current; IDD1 CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Timing table ; BL: 8; AL: 0; /CS: High between ACT, RD and PRE; Command, Address, Bank Address Inputs, Data IO: partially toggling ; DM:stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,...; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0; Precharge Power-Down Current Slow Exit IDD2P0 CKE: Low; External clock: On; tCK, CL: see Timing table ; BL: 8; AL: 0; /CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pre-charge Power Down Mode: Slow Exit Precharge Power-Down Current Fast Exit IDD2P1 CKE: Low; External clock: On; tCK, CL: see Timing table; BL: 81); AL: 0; /CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0; Pre-charge Power Down Mode: Fast Exit IDD2N CKE: High; External clock: On; tCK, CL: see Timing table ; BL: 8; AL: 0; /CS: stable at 1; Command, Address, Bank Address Inputs: partially tog-gling; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0; Precharge standby current; Precharge Standby ODT Current IDD2NT CKE: High; External clock: On; tCK, CL: see Timing table ; BL: 8; AL: 0; /CS: stable at 1; Command, Address, Bank Address Inputs: partially tog-gling ; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers Precharge quiet standby current; IDD2Q CKE: High; External clock: On; tCK, CL: see Timing table; BL: 8; AL: 0; /CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0 IDD3P CKE: Low; External clock: On; tCK, CL: see Timing table ; BL: 8; AL: 0; /CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0 IDD3N CKE: High; External clock: On; tCK, CL: see Timing table ; BL: 8; AL: 0; /CS: stable at 1; Command, Address, Bank Address Inputs: partially tog-gling ; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0; Active Power-Down Current Active Standby Current Operating Burst Read Current IDD4R CKE: High; External clock: On; tCK, CL: see Timing table; BL: 8; AL: 0; /CS: High between RD; Command, Address, Bank Address Inputs: par-tially toggling ; Data IO: seamless read data burst with different data between one burst and the next one; DM:stable at 0; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0; Operating Burst Write Current IDD4W CKE: High; External clock: On; tCK, CL: see Timing table ; BL: 8; AL: 0; CS: High between WR; Command, Address, Bank Address Inputs: par-tially toggling ; Data IO: seamless write data burst with different data between one burst and the next one; DM: stable at 0; Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,...; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at HIGH; Burst Refresh Current IDD5B CKE: High; External clock: On; tCK, CL, nRFC: see Timing table ; BL: 8; AL: 0; CS: High between REF; Command, Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING;DM:stable at 0; Bank Activity: REF command every nRFC; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0; Self Refresh Current: Normal Temperature Range TCASE: 0 - 85°C; IDD6 Auto Self-Refresh (ASR): Disabled; Self-Refresh Temperature Range (SRT): Normale); CKE: Low; External clock: Off; CK and CK: LOW; CL: see Timing table ; BL: 8; AL: 0; /CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0; Bank Activity: Self- Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: FLOATING Operating Bank Interleave Read Current IDD7 PDIMM CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see Timing table ; BL: 8; AL: CL-1; /CS: High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling; Data IO: read data bursts with different data between one burst and the next one ; DM:stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0; Power Consumption per DIMM System is operating at 800 MHz clock. This parameter is calculated at a common loading. Your Ultimate Memory Solution! 2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com Tel. (408) 732-5000 Fax (408) 732-5055 Page 5 of 7 ATP AL24P72L8BLK0M TIMING PARAMETER Parameter DDR3-1600 min Symbol Clock cycle time at CL=11, CWL=8 Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACTIVE to PRECHARGE command period Average high pulse width Average low pulse width DQS, DQS to DQ skew, per group, per access DQ output hold time from DQS, DQS DQ low-impedance time from CK, CK DQ high-impedance time from CK, CK Data setup time to DQS, DQS referenced to Vih(ac)Vil(ac) levels Data hold time to DQS, DQS referenced to Vih(ac)Vil(ac) levels DQS, DQS READ Preamble DQS, DQS differential READ Postamble DQS, DQS output high time DQS, DQS output low time DQS, DQS WRITE Preamble DQS, DQS WRITE Postamble DQS, DQS rising edge output access time from rising CK， CK DQS, DQS low-impedance time (Referenced from RL-1) DQS, DQS high-impedance time (Referenced from RL+BL/2) DQS, DQS differential input low pulse width DQS, DQS differential input high pulse width DQS, DQS rising edge to CK, CK rising edge DQS, DQS falling edge setup time to CK, CK rising edge DQS, DQS falling edge hold time to CK, CK rising edge DLL locking time Internal READ Command to PRECHARGE Command delay Delay from start of internal write transaction to internal read command WRITE recovery time Mode Register Set command cycle time Mode Register Set command update delay CAS to CAS command delay Auto precharge write recovery + precharge time Multi-Purpose Register Recovery Time ACTIVE to ACTIVE command period for 1KB page size Four activate window for 1KB page size Command and Address setup time to CK, CK referenced to Vih(ac) / Vil(ac) levels Command and Address hold time from CK, CK referenced to Vih(ac) / Vil(ac) levels Power-up and RESET calibration time Normal operation Full calibration time Normal operation short calibration time Exit Reset from CKE HIGH to a valid command Exit Power Down with DLL on to any valid command; Exit Precharge Power Down with DLL frozen to commands not requiring a locked DLL Asynchronous RTT turn-on delay (Power-Down with DLL frozen) Asynchronous RTT turn-off delay (Power-Down with DLL frozen) ODT turn-on RTT_NOM and RTT_WR turn-off time from ODTLoff reference RTT dynamic change skew 2Gb REFRESH to REFRESH OR REFRESH to ACTIVE command interval Average periodic refresh interval (0°C ≤ TCASE ≤ 85 °C) Average periodic refresh interval (85°C ≤ TCASE ≤ 95 °C) Exit Self Refresh to commands not requiring a locked DLL Exit Self Refresh to commands requiring a locked DLL Power Down Entry to Exit Timing Write leveling output delay Write leveling output error tCK tAA tRCD tRP tRC tRAS tCH(avg) tCL(avg) tDQSQ tQH tLZ(DQ) tHZ(DQ) tDS(base) tDH(base) tRPRE tRPST tQSH tQSL tWPRE tWPST tDQSCK tLZ(DQS) tHZ(DQS) tDQSL tDQSH tDQSS tDSS tDSH tDLLK tRTP tWTR tWR tMRD tMOD tCCD tDAL tMPRR tRRD tFAW tIS(base) tIH(base) tZQinitI tZQoper tZQCS tXPR tXP tAONPD tAOFPD tAON tAOF tADC tRFC tREFI tREFI tXS tXSDLL tPD tWLO tWLOE 1.25 13.75(13.1252) 13.75(13.1252) 13.75(13.1252) 48.75(48.1252) 35 0.47 0.47 0.38 -450 2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com Tel. (408) 732-5000 Fax (408) 732-5055 Page 6 of 7