SGV02G72A1BD1MT-CCRT

Data Sheet Rev.1.0 20.06.2011 2048MB DDR3 – SDRAM ECC XR-DIMMTM 240 Pin ECC XR-DIMMTM Features: SGV02G72A1BC1SA-xxRT  2GB in FBGA Technology  RoHS compliant Options:  Data Rate / Latency DDR3 1066 MT/s CL7 DDR3 1333 MT/s CL9  Module density 2048MB with 9 dies and 1 rank  Standard Grade Marking -BB -CC (TA) (TC) (TA) (TC) 0°C to 70°C 0°C to 85°C -40°C to 85°C -40°C to 95°C Environmental Requirements:        Grade W         Operating temperature (ambient) Standard Grade 0°C to 70°C Grade W -40°C to 85°C Operating Humidity 10% to 90% relative humidity, noncondensing Operating Pressure 105 to 69 kPa (up to 10000 ft.) Storage Temperature -55°C to 100°C Storage Humidity 5% to 95% relative humidity, noncondensing Storage Pressure 1682 PSI (up to 5000 ft.) at 50°C       eXtreme Rugged 240-pin 72-bit DDR3 Small Outline Double Data Rate synchronous DRAM Module 67.5 mm x 38 mm module that stacks 7.36mm above CPU board Samtec BSH-120-01-X-D-A connector Socket ANSI/VITA 47-2005 shock and vibration compliant Module organization: single rank 256M x 72 VDD = 1.5V ±0.075V, VDDQ 1.5V ±0.075V 1.5V I/O ( SSTL_15 compatible) Fly-by-bus with termination for C/A & CLK bus On-board I2C temperature sensor with integrated serial presence-detect (SPD) EEPROM Compatible to XR-DIMM™ 2.0 specification of SFF-SIG (see www.sff-sig.org) The pcb and all components are manufactured according to the RoHS compliance specification [EU Directive 2002/95/EC Restriction of Hazardous Substances (RoHS)] DDR3 - SDRAM component Samsung K4B2G0846C 256Mx8 DDR3 SDRAM in PG-TFBGA-78 package 8-bit prefetch architecture Programmable CAS Latency, CAS Write Latency, Additive Latency, Burst Length and Burst Type. On-Die-Termination (ODT) and Dynamic ODT for improved signal integrity. Refresh, Self Refresh and Power Down Modes. Figure: mechanical dimensions 1 1 if no tolerances specified ± 0.15mm Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 1 of 16 Data Sheet Rev.1.0 20.06.2011 This Swissbit module is a highly ruggedized 240-pin 72bit DDR3 SDRAM ECC Small Outline module which is organized as 256Mx72 high speed CMOS memory arrays. Enhanced ruggedness is obtained through the use of a high-performance, 240-pin socket connector system and the use of standoffs with screw attachment firmly holding the CPU and memory module together. The module uses internally configured octal-bank DDR3 SDRAM devices. The module uses double data rate architecture to achieve high-speed operation. DDR3 SDRAM modules operate from a differential clock (CK and CK#). READ and WRITE accesses to a DDR3 SDRAM module is burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. The burst length is either four or eight locations. An auto precharge function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst access. The DDR3 SDRAM devices have a multibank architecture which allows a concurrent operation that is providing a high effective bandwidth. A self refresh mode is provided and a power-saving ―power-down‖ mode. All inputs and all full drivestrength outputs are SSTL_15 compatible. The DDR3 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM 2 using the standard I C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are utilized by the XR-DIMM manufacturer (Swissbit) to identify the module type, the module’s organization and several timing parameters. The second 128 bytes are available to the end user. Module Configuration Organization DDR3 SDRAMs used Row Addr. Device Bank Addr. 256M x 72bit 9 x 256M x 8bit (2048Mbit) 15 BA0, BA1, BA2 Column Refresh Addr. 10 8k Module Bank Select S0# Module Dimensions in mm 67.5mm (long) x 38mm(high) x 7.36mm(standoff from CPU board) Timing Parameters Part Number Module Density Transfer Rate Clock Cycle/Data bit rate Latency SGV02G72A1BC1SA-BB[W]RT 2048 MB 8.5 GB/s 1.87ns/1066MT/s 7-7-7 SGV02G72A1BC1SA-CC[W]RT 2048 MB 10.6 GB/s 1.5ns/1333MT/s 9-9-9 Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 2 of 16 Data Sheet Rev.1.0 20.06.2011 Pin Name Symbol Type A0–A14 IN BA0–BA2 Polarity Function — During a Bank Activate command cycle, address input defines the row address (RA0– RA14). During a Read or Write command cycle, address input defines the column address. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0, BA1, BA2 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0, BA1, BA2 to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0, BA1 or BA2. If AP is low, BA0, BA1 and BA2 are used to define which bank to precharge. A12(BC_n) is sampled during READ and WRITE commands to determine if burst chop (on-the-fly) will be performed (HIGH, no burst chop; LOW, burst chopped). Selects which SDRAM bank of eight is activated. IN — CK0_t–CK1_t CK0_c–CK1_c IN Differential crossing CK_t and CK_c are differential clock inputs. All the DDR3 SDRAM addr/cntl inputs are sampled on the crossing of positive edge of CK_t and negative edge of CK_c. Output (read) data is referenced to the crossing of CK_t and CK_c (Both directions of crossing). CKE0 IN Active High Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode. DM0–DM8 IN Active High DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with that input data during a write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. DQ0–DQ63, CB0–CB7 I/0 — DQS0_t–DQS8_t DQS0_c–DQS8_c I/O Differential crossing Data strobe for input and output data. For raw cards using x16 organized DRAMs, Pins DQ0–DQ7 are associated with the LDQS_t and LDQS_c pins and Pins DQ8–DQ15 are associated with UDQS_t and UDQS_c pins. ODT0 IN Active High When high, termination resistance is enabled for all DQ, DQS_t, DQS_c and DM pins, assuming this function is enabled on the DRAM. RAS_n, CAS_n, WE_n IN Active Low RAS_n, CAS_n, and WE_n (along with S_n) define the command being entered. RESET_n IN Active Low The RESET_n pin is connected to the RESET_n pin on each DRAM. When low, all DRAMs are set to a known state. S0_n IN Active Low Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. This signal provides for external rank selection on systems with multiple ranks. VDD, VSS Supply Power and ground for the DDR3 SDRAM input buffers, and core logic. VDD and VDDQ pins are tied to VDD/VDDQ planes on these modules. VDDQ Supply Power supply for the DDR3 SDRAM output buffers to provide improved noise immunity. For the DDR3 XR-DIMM designs, VDDQ shares the same power plane as VDD pins. VTT Supply Termination voltage for C/A & Control bus, by default at VDD/2 VDDSPD Supply Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power plane. EEPROM supply is operable from 3.0V to 3.6V. VREFDQ Supply Reference voltage for I/O inputs, by default at VDD/2 VREFCA Supply Reference voltage for command/address/control inputs, by default at VDD/2 SA0–SA2 IN — These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range. SDA I/O — This bidirectional pin is used to transfer data into or out of the SPD EEPROM. An external resistor may be connected from the SDA bus line to VDDSPD to act as a pullup on the system board. SCL IN — This signal is used to clock data into and out of the SPD EEPROM. An external resistor may be connected from the SCL bus time to VDDSPD to act as a pullup on the system board. EVENT_n Output (Open Drain) Active Low NC(TEST) NC Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen Data and Check Bit Input/Output pins. This signal indicates that a thermal event has been detected in the thermal sensing device. The system should guarantee the electrical level requirement is met for the EVENT_n pin on the TS/SPD part. Used by memory bus analysis tools (unused (NC) on memory module) Not connected Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 3 of 16 Data Sheet Rev.1.0 20.06.2011 Pin Configuration Pin# Symbol Pin# Symbol Pin# 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 VSS VSS DQ0 DQ1 VSS DQS0_c DQS0_t VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1_c DQS1_t VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2_c 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 DQS2_t VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DQS3_c DQS3_t VSS DQ26 DQ27 VSS CB0 CB1 VSS DQS8_c DQS8_t VSS CB2 CB3 VSS VTT 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 Pin# Symbol Pin# Symbol 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 VSS VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS DQ14 DQ15 VSS DQ20 DQ21 VSS VREFDQ NC (TEST) VSS 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DM3 VSS DQ30 DQ31 VSS CB4 CB5 VSS DM8 VSS CB6 CB7 VSS RESET_n NC (ERR_OUT_n) VTT Odd Row Symbol CKE0 VDD BA2 VDD A11 A7 VDD A5 A4 VDD A2 VDD CK1_t CK1_n VDD VREFCA NC (PAR_IN) VDD A10/AP BA0 VDD WE_n CAS_n VDD Even Row Pin# Symbol 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 NC (CKE1) VDD NC (A15) A14 VDD A12/BC A9 VDD A8 A6 VDD A3 A1 VDD CK0_t CK0_c VDD EVENT_n A0 VDD BA1 VDD RAS_n S0_n Pin# Symbol Pin# Symbol 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 NC (S1_n) NC (ODT1) VDD NC (S3_n) VSS DQ32 DQ33 VSS DQS4_c DQS4_t VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DQS5_c DQS5_t VSS DQ42 DQ43 VSS DQ48 193 195 197 199 201 203 205 207 209 211 213 215 217 219 221 223 225 227 229 231 233 235 237 239 DQ49 VSS DQS6_c DQS6_t VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DQS7_c DQS7_t VSS DQ58 DQ59 VSS SA2 VSS NC (SATA_RX_p) NC (SATA_RX_n) VSS VTT VTT Pin# Symbol Pin# Symbol 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 VDD ODT0 A13 VDD NC (S2_n) VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DM5 VSS DQ46 DQ47 VSS DQ52 DQ53 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7 VSS DQ62 DQ63 VSS VDDSPD SA0 SA1 SCL SDA VSS NC (SATA_TX_n) NC (SATA_TX_p) VSS VTT (Sig): Signal in brackets may be routed to the socket connector, but is not used on the module Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 4 of 16 Data Sheet Rev.1.0 20.06.2011 Mechanical Specifications Connector on Memory Module (BSH-120-01-X-D-A) Top view: Bottom view: Front view: Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 5 of 16 Data Sheet Rev.1.0 20.06.2011 FUNCTIONAL BLOCK DIAGRAMM 2048MB DDR3 SDRAM XR-DIMM, 1 RANK AND 9 COMPONENTS S0 DQS4 DQS4 DM4 DQS0 DQS0 DM0 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DM DQS DQS D0 ZQ DQ32 DQ33 DQ34 I/O 0 I/O 1 I/O 2 DQ35 DQ36 DQ37 DQ38 DQ39 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ40 DQ41 DQ42 I/O 0 I/O 1 I/O 2 DQ43 DQ44 DQ45 DQ46 DQ47 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ48 DQ49 DQ50 I/O 0 I/O 1 I/O 2 DQ51 DQ52 DQ53 DQ54 DQ55 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ56 DQ57 DQ58 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D4 ZQ DQS5 DQS5 DM5 DQS1 DQS1 DM1 DM DQ8 DQ9 DQ10 I/O 0 I/O 1 I/O 2 DQ11 DQ12 DQ13 DQ14 DQ15 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DM DQS DQS D1 ZQ CS DQS DQS D5 ZQ DQS6 DQS6 DM6 DQS2 DQS2 DM2 DM DQ16 DQ17 DQ18 I/O 0 I/O 1 I/O 2 DQ19 DQ20 DQ21 DQ22 DQ23 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DM DQS DQS D2 ZQ CS DQS DQS D6 ZQ DQS7 DQS7 DM7 DQS3 DQS3 DM3 DM DQ24 DQ25 DQ26 I/O 0 I/O 1 I/O 2 DQ27 DQ28 DQ29 DQ30 DQ31 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CB0 CB1 CB2 I/O 0 I/O 1 I/O 2 CB3 CB4 CB5 CB6 CB7 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DM DQS DQS D3 ZQ DQ59 DQ60 DQ61 DQ62 DQ63 CS DQS DQS D7 ZQ DQS8 DQS8 DM8 DM BA0-BA2 A0-A14 RAS CAS WE ODT0 CKE0 CK0 CK0 RESET CS DQS DQS D8 ZQ SPD D0-D8 VREFDQ D0-D8 VREFCA D0-D8 VSS D0-D8 Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S relationship must be maintained as shown. 3. DQ, DM, DQS/DQS resistors: Refer to associated topology diagram. 4. Refer to the appropriate clock wiring topology under the DIMM wiring details section of the JEDED document. 5. For each DRAM, a unique ZQ resistor is connected to GND. The ZQ resistor is 240O±1%. 6. Refer to associated figure for SPD details. BA0-BA2: SDRAM D0-D8 A0-A14: SDRAM D0-D8 RAS: SDRAM D0-D8 CAS: SDRAM D0-D8 WE: SDRAM D0-D8 ODT: SDRAM D0-D8 CKE: SDRAM D0-D8 CK: SDRAM D0-D8 CK: SDRAM D0-D8 RESET: SDRAM D0-D8 Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen VDDSPD VDD/VDDQ Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 6 of 16 Data Sheet Rev.1.0 20.06.2011 MAXIMUM ELECTRICAL DC CHARACTERISTICS PARAMETER/ CONDITION Supply Voltage I/O Supply Voltage VDDL Supply Voltage Voltage on any pin relative to VSS INPUT LEAKAGE CURRENT SYMBOL VDD VDDQ VDDL VIN, VOUT Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 0.95V (All other pins not under test = 0V) MIN -0.4 -0.4 -0.4 -0.4 MAX 1.975 1.975 1.975 1.975 II UNITS V V V V µA Command/Address -16 16 IOZ -16 -2 -5 16 2 5 µA IVREF -8 8 µA RAS#, CAS#, WE#, S#, CKE CK, CK# DM OUTPUT LEAKAGE CURRENT (DQ’s and ODT are disabled; 0V ≤ VOUT ≤ VDDQ) DQ, DQS, DQS# VREF LEAKAGE CURRENT ; VREF is on a valid level DC OPERATING CONDITIONS PARAMETER/ CONDITION Supply Voltage I/O Supply Voltage VDDL Supply Voltage I/O Reference Voltage I/O Termination Voltage (system) Input High (Logic 1) Voltage Input Low (Logic 0) Voltage SYMBOL MIN VDD 1.425 VDDQ 1.425 VDDL 1.425 VREF 0.49 x VDDQ VTT 0.49 x VDDQ-20mV VIH (DC) VREF + 0.1 VIL (DC) -0.3 NOM 1.5 1.5 1.5 0.50 x VDDQ 0.50 x VDDQ MAX 1.575 1.575 1.575 0.51x VDDQ 0.51x VDDQ+20mV VDDQ + 0.3 VREF – 0.1 UNITS V V V V V V V AC INPUT OPERATING CONDITIONS PARAMETER/ CONDITION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage SYMBOL VIH (AC) VIL (AC) MIN VREF + 0.175 - MAX VREF - 0.175 UNITS V V CAPACITANCE At DDR3 data rates, it is recommended to simulate the performance of the module to achieve optimum values. When inductance and delay parameters associated with trace lengths are used in simulations, they are significantly more accurate and realistic than a gross estimation of module capacitance. Simulations can then render a considerably more accurate result. DDR3 modules are now designed by using simulations to close timing budgets. Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 7 of 16 Data Sheet Rev.1.0 20.06.2011 IDD Specifications and Conditions (0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.5V ± 0.075V, VDD = +1.5V ± 0.075V) Parameter & Test Condition Symbol OPERATING CURRENT *) : One device bank Active-Precharge; tRC= tRC (IDD); tCK = tCK (IDD); CKE is HIGH, CS# is HIGH between valid commands; DQ inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles OPERATING CURRENT *) : One device bank; Active-Read-Precharge; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC= tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address inputs changing once every two clock cycles; Data Pattern is same as IDD4W Fast Exit PRECHARGE POWER-DOWN CURRENT: All device banks idle; Power-down mode; tCK = tCK (IDD); CKE is LOW; All Control and Slow Exit Address bus inputs are not changing; DQ’s are floating at VREF PRECHARGE QUIET STANDBY CURRENT: All device banks idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; All Control and Address bus inputs are not changing; DQ’s are floating at VREF PRECHARGE STANDBY CURRENT: All device banks idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; All other Control and Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle ACTIVE POWER-DOWN CURRENT: All device banks open; tCK = tCK (IDD); CKE is LOW; All Control and Address bus inputs are not changing; DQ’s are floating at VREF (always fast exit) ACTIVE STANDBY CURRENT: All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid commands; All other Control and Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle OPERATING READ CURRENT: All device banks open, Continuous burst reads; One module rank active; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 max. Unit 10600-999 8500-777 IDD0 540 495 mA IDD1 675 630 mA IDD2P 180 180 mA 108 108 IDD2Q 270 270 mA IDD2N 315 270 mA IDD3P 270 270 mA IDD3N 495 450 mA IDD4R 1035 900 mA www.swissbit.com eMail: info@swissbit.com Page 8 of 16 Data Sheet Parameter & Test Condition Rev.1.0 Symbol OPERATING WRITE CURRENT: All device banks open, Continuous burst writes; One module rank active; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle BURST REFRESH CURRENT: tCK = tCK (IDD); refresh command at every tRFC (IDD) interval, CKE is HIGH, CS# is HIGH between valid commands; All other Control and Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle SELF REFRESH CURRENT: CK and CK# at 0V; CKE ≤ 0.2V; All other Control and Address bus inputs are floating at VREF; DQ’s are floating at VREF OPERATING CURRENT *) : Four device bank interleaving READs, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) – 1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are not changing during DESELECT; DQ inputs changing once per clock cycle 20.06.2011 max. Unit 10600-999 8500-777 IDD4W 1260 1035 mA IDD5 1530 1530 mA IDD6 108 108 mA IDD7 1890 1530 mA *) Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW) mode. TIMING VALUES USED FOR IDD MEASUREMENT IDD MEASUREMENT CONDITIONS SYMBOL 10600-999 8500-777 9 7 CL (IDD) 13.5 13.125 tRCD (IDD) 49.5 50.625 tRC (IDD) 6 7.5 tRRD (IDD) 1.5 1.87 tCK (IDD) 36 37.5 tRAS MIN (IDD) 70’200 70’200 tRAS MAX (IDD) 13.5 13.125 tRP (IDD) 160 160 tRFC (IDD) Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen Unit tCK ns ns ns ns ns ns ns ns Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 9 of 16 Data Sheet Rev.1.0 20.06.2011 DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.5V ± 0.075V, VDD = +1.5V ± 0.075V) AC CHARACTERISTICS PARAMETER Clock cycle time CL = 10 CL = 9 CL = 8 CL = 7 CL = 6 CK high-level width CK low-level width Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# DQ and DM input setup time relative to DQS tCK (10) tCK (9) tCK (8) tCK (7) tCK (6) tCH (avg) tCL (avg) tHZ 10600-999 MIN MAX 1.5