SDN06464D1BJ1SA-50R

Data Sheet 512MB DDR Features: SDN06464D1BJ1SA-xx(W)R  512MByte in FBGA Technology        RoHS compliant Options:  Data Rate / Latency DDR 400 MT/s CL3 DDR 333 MT/s CL2.5  Module density 512MB with 8 dies and 1 rank  Standard Grade W-Grade (TA) (TA) Marking -50 -60 0°C to 70°C -40°C to 85°C Environmental Requirements:  Operating temperature (ambient) Standard Grade 0°C to 70°C W-Grade -40°C to 85°C    200-pin 64-bit DDR1 Small Outline Dual-In-Line Double Data Rate Synchronous DRAM module Module organization: single rank 64M x 64 VDD = 2.5V ±0.2V, VDDQ 2.5V ±0.2V VDD = 2.6V ±0.1V, VDDQ 2.6V ±0.1V (DDR400) 2.5V I/O ( SSTL_2 compatible) Serial Presence Detect with EEPROM Gold-contact pads This module is fully pin and functional compatible to the JEDEC PC-3200 spec. and JEDEC- Standard MO-224. (see www.jedec.org) The pcb and all components are manufactured according to the RoHS compliance specification [EU Directive 2002/95/EC Restriction of Hazardous Substances (RoHS)]  *) The refresh rate has to be doubled when 85°C= VIH(min); tCK=6ns for DDR333, 5ns for DDR400; Address and other control iputs stable at >=VIH(min) or =< VIL(max); VIN=VREF for DQ, DQS and DM ACTIVE POWER-DOWN STANDBY CURRENT; One device bank active; Power-down mode; tCK = tCK (Min);CKE = LOW ACTIVE STANDBY CURRENT; CS# = HIGH; CKE = HIGH; One device bank; Active-Precharge; tRC= tRAS (Max); tCK = tCK (Min); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT; Burst = 2; Reads; Continous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (Min); IOUT = 0mA OPERATING CURRENT; Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (Min); DQ, DM, and DQS inputs changing twice per clock cycle AUTO REFRESH CURRENT; tRC = tRC (Min) SELF REFRESH CURRENT; CKE ≤ 0.2V;External clock on; Tck=6ns for DDR333, 5ns for DDR400 OPERATING CURRENT – FOUR BANK OPERATION; Four bank interleaving with BL=4 Symbol max. 3200-3.033 2700-2.533 Unit IDD0 520 480 mA IDD1 600 560 mA IDD2P 40 40 mA IDD2F 184 184 mA IDD2Q 160 160 mA IDD3P 120 120 mA IDD3N 280 280 mA IDD4R 800 720 mA IDD4W 720 640 mA IDD5 960 800 mA IDD6(normal) 40 40 mA IDD6(Low power) 24 24 mA IDD7A 1600 1440 mA *) Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW) mode. Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com email: info@swissbit.com Page 7 of 14 Data Sheet Rev.1.1 28.11.2012 DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (0°C ≤ TA ≤ + 70°C; VDDQ = +2.5V ± 0.2V, VDD = +2.5V ± 0.2V) see Note 1 on Page 9 AC CHARACTERISTICS PARAMETER SYMBOL Access window of DQS CK/CK# tAC CK high-level width tCH CK low-level width tCL Clock cycle time CL=2.0 tCK (2.0) CL=2.5 tCK(2.5) CL=3.0 tCK (3.0) DQ and DM input hold time relative tDH to DQS DQ and DM input setup time relative tDS to DQS DQ and DM input pulse width tDIPW ( for each input ) Access window of DQS from tDQSCK CK/CK# DQS input high pulse width tDQSH DQS input low pulse width tDQSL DQS –DQ skew, DQS to last DQ tDQSQ valid, per group, per access Write command to first DQS latching tDQSS transition DQS falling edge to CK rising- setup tDSS time DQS falling edge from CK risingtDSH hold time Half clock period tHP Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# Address and control input hold time ( fast slew rate ) Address and control input setup time ( fast slew rate ) Address and control input hold time ( slow slew rate ) Address and control input setup time ( slow slew rate ) LOAD MODE REGISTER command cycle time Adress and control input pulse width (for each input) DQ-DQS hold, DQS to first DQ to go non-valid, per access Data hold skew factor Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen 3200-3.0-3-3 MIN MAX -0.65 +0.65 0.45 0.55 0.45 0.55 7.5 13.0 6.0 13.0 5.0 13.0 2700-2.5-3-3 MIN MAX -0.65 +0.65 0.45 0.55 0.45 0.55 7.5 13.0 6.0 13.0 0.40 - 0.45 - ns 0.40 - 0.45 - ns 1.75 - 1.75 - ns -0.6 +0.6 -0.6 +0.6 ns 0.35 0.35 - 0.35 0.35 - tCK tCK 0.40 - 0.45 ns 0.72 1.28 0.75 1.25 tCK 0.2 - 0.2 - tCK 0.2 - 0.2 - tCK tch, tcl - tch, tcl - ns tHZ -0.7 +0.7 -0.7 +0.7 ns tLZ -0.7 +0.7 -0.7 +0.7 ns tIHF 0.6 - 0.75 - ns tISF 0.6 - 0.75 - ns tIHS 0.7 - 0.8 - ns tISS 0.6 - 0.8 - ns tMRD 10 - 12 - ns tIPW 2.2 - 2.2 - ns tQH tQHS tHP - tQHS - Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 0.5 tHP - tQHS - 0.6 Unit ns tCK tCK ns ns ns www.swissbit.com email: info@swissbit.com Page 8 of 14 Data Sheet AC CHARACTERISTICS PARAMETER ACTIVE to PRECHARGE command ACTIVE to READ with Auto precharge command ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS write preamble setup time DQS write postamble Write recovery time Internal WRITE to READ command delay Data valid output window REFRESH to REFRESH command interval Average periodic refresh interval 0 °C ≤ TCASE ≤ 85°C SYMBOL tRAS tRAP 3200-3.0-3-3 MIN MAX 40 70.000 Rev.1.1 2700-2.5-3-3 MIN MAX 42 70.000 28.11.2012 Unit ns 15 - 15 - ns 55 - 60 - ns tRFC tRCD tRP tRPRE tRPST tRRD 70 15 15 0.9 0.4 1.1 0.6 72 18 18 0.9 0.4 1.1 0.6 10 - 12 - ns ns ns tCK tCK ns tWPREH tWPRES tWPST tWR tWTR 0.25 0 0.4 15 0.6 - 0.25 0 0.4 15 0.6 - 2 - 1 - tRC N/A tREFC tREFI 85 °C < TCASE ≤ 95°C tREFI (IT) Terminating voltage delay to VDD Exit SELF REFRESH to non-READ command Exit SELF REFRESH to READ command tVTD tXSNR tXSRD tQH - tDQSQ tCK ns tCK ns tCK tQH - tDQSQ - 70.3 - 70.3 - 7.8 - 7.8 0 3.9 - 0 3.9 - 70 - 75 - 200 - 200 - ns µs µs ns ns tCK Note 1: Values for AC timing, IDD, and electrical AC and DC characteristics might have been collected within the standard temperature range and at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified and for the corresponding field of operation according to the actual temperature grade of the module (extended E, I or W; refer to the environmental conditions for more details). Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com email: info@swissbit.com Page 9 of 14 Data Sheet Rev.1.1 28.11.2012 SERIAL PRESENCE-DETECT MATRIX BYTE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36-40 41 42 43 44 45 DESCRIPTION NUMBER OF SPD BYTES USED TOTAL NUMBER OF BYTES IN SPD DEVICE FUNDAMENTAL MEMORY TYPE NUMBER OF ROW ADDRESSES ON ASSEMBLY NUMBER OF COLUMN ADDRESSES ON ASSEMBLY NUMBER OF PHYSICAL BANKS ON DIMM MODULE DATA WIDTH MODULE DATA WIDTH (continued) MODULE VOLTAGE INTERFACE LEVELS (VDDQ) SDRAM CYCLE TIME, (tCK ) (CAS LATENCY =2.5 (2700, 2100) ; CL=3* (3200) SDRAM ACCESS FROM CLOCK, (tAC) (CAS LATENCY =2.5 (2700, 2100); CL=3* (3200)) MODULE CONFIGURATION TYPE REFRESH RATE/ TYPE SDRAM DEVICE WIDTH (PRIMARY SDRAM) ERROR- CHECKING SDRAM DATA WIDTH MINIMUM CLOCK DELAY, BACK- TO- BACK RANDOM COLUMN ACCESS BURST LENGTHS SUPPORTED NUMBER OF BANKS ON SDRAM DEVICE CAS LATENCIES SUPPORTED CS LATENCY WE LATENCY SDRAM MODULE ATTRIBUTES SDRAM DEVICE ATTRIBUTES: GENERAL SDRAM CYCLE TIME, (tCK) (CAS LATENCY=2(2700, 2100) CL=2,5*(3200)) SDRAM ACCESS FROM CK, (tAC) (CAS LATENCY=2(2700, 2100) CL=2.5*(3200) SDRAM CYCLE TIME, (tCK) (CAS LATENCY=1.5(2700, 2100) CL=2*(3200)) SDRAM ACCESS FROM CK, (tAC) (CAS LATENCY=1.5(2700, 2100) CL=2*(3200) MINIMUM ROW PRECHARGE TIME, (tRP) MINIMUM ROW ACTIVE TO ROW ACTIVE, (tRRD) MINIMUM RAS# TO CAS# DELAY, (tRCD) MINIMUM RAS# PULSE WIDTH, (tRAS) MODULE BANK DENSITY ADDRESS AND COMMAND SETUP TIME, (tIS) ADDRESS AND COOMAND HOLD TIME, (tIH) DATA/DATA MASK INPUT SETUP TIME, (tDS) DATA/DATA MASK INPUT HOLD TIME, (tDH) RESERVED MIN ACTIVE AUTO REFRESH TIME (tRC) MINIMUM AUTO REFRESH TO ACTIVE/ AUTO REFRESH COMMAND PERIOD, (tRFC) SDRAM DEVICE MAX CYCLE TIME (tCKMAX) SDRAM DEVICE MAX DQS-DQ SKEW TIME (tDQSQ) SDRAM DEVICE MAX READ DATA HOLD SKEW FACTOR (tQHS) Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 3200-3.0-3-3 2700-2.5-3-3 0x80 0x08 0x07 0x0D 0x0B 0x01 0x40 0x00 0x04 0x50 0x60 0x65 0x00 0x82 0x08 0x00 0x01 0x0E 0x04 0x1C 0x0C 0x01 0x02 0x20 0xC1 0x60 0x75 0x70 0x75 0x00 0x75 0x00 0x3C 0x28 0x3C 0x28 0x48 0x30 0x48 0x2A 0x80 0x60 0x60 0x40 0x40 0x75 0x75 0x45 0x45 0x00 0x37 0x3C 0x46 0x48 0x28 0x30 0x28 0x2D 0x50 0x55 www.swissbit.com email: info@swissbit.com Page 10 of 14 Data Sheet Rev.1.1 28.11.2012 SERIAL PRESENCE-DETECT MATRIX (continued) BYTE 46-61 62 63 64 65 66 67 72 73-90 91 92 93 94 95-98 99-127 DESCRIPTION RESERVED SPD REVISION CHECKSUM FOR BYTES 0-62 MANUFACTURER`S JEDEC ID CODE MANUFACTURER`S JEDEC ID CODE(continued) MANUFACTURER`S JEDEC ID CODE(continued) MANUFACTURER`S JEDEC ID CODE(continued) MANUFACTURING LOCATION MODULE PART NUMBER (ASCII) PCB IDENTIFICATION CODE PCB IDENTIFICATION CODE (continued) YEAR OF MANUFACTURE IN BCD WEEK OF MANUFACTURE IN BCD MODULE SERIAL NUMBER MANUFACTURER-SPECIFIC DATA (RSVD) 3200-3.0-3-3 2700-2.5-3-3 0x00 0x11 0xAE 0x48 7F 7F 7F DA 0x01 = CH 0x02 = GE 0x03 = USA “SDN06464D1BJ1SA-xx” X X X X X X Part Number Code S D N 064 64 D1 B J 1 SA 1 2 3 4 5 6 7 8 9 10 - 50 * R 11 12 13 *RoHs compl. DDR-400MT/s Swissbit AG SDRAM DDR 200 Pin Unbuffered 2.5V Depth (512MB) Width PCB-Type (S1D3E1.00) Chip Vendor (Samsung) 1 Module Rank Chip Rev. J Chip organisation x8 * optional / additional information Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com email: info@swissbit.com Page 11 of 14 Data Sheet Rev.1.1 28.11.2012 Revision History Revision Changes Date 1.0 Initial Revision 31.10.2012 1.1 New IDD-Values added, Extended Temperature-Grade (W-Grade) added 20.11.2012 Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com email: info@swissbit.com Page 12 of 14 Data Sheet Rev.1.1 28.11.2012 Locations Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen Switzerland Phone: +41 (0)71 913 03 03 Fax: +41 (0)71 913 03 15 _____________________________ Swissbit Germany GmbH Wolfener Strasse 36 D – 12681 Berlin Germany Phone: +49 (0)30 93 69 54 – 0 Fax: +49 (0)30 93 69 54 – 55 _____________________________ Swissbit NA, Inc. 1117 E Plaza Drive Unit E Suites 105/205 Eagle, ID 83616 USA Phone: +1 208 258-6254 Fax: +1 208 938-4525 _____________________________ Swissbit Japan, Inc. 3F Core Koenji, 2-1-24 Koenji-Kita, Suginami-Ku, Tokyo 166-0002 Japan Phone: +81 3 5356 3511 Fax: +81 3 5356 3512 ________________________________ Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com email: info@swissbit.com Page 13 of 14 Data Sheet Rev.1.1 28.11.2012 Declaration of Conformity We Manufacturer: Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen Switzerland declare under our sole responsibility that the product Product Type: Brand Name: Product Series: Part Number: 512MB DDR1 SODIMM SWISSMEMORY™ DDR1 SODIMM SDN06464D1BJ1SA-xxxR to which this declaration relates is in conformity with the following directives: 2002/96/EC Category 3 (WEEE) following the provisions of Directive Restriction of the use of certain hazardous substances 2011/65/EU Swissbit AG, November 2012 Manuela Kögel Head of Quality Management Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com email: info@swissbit.com Page 14 of 14 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Swissbit: SDN06464D1BJ1SA-50WR SDN06464D1BJ1SA-50R