SLN08G72G2BE2MT-DCRT

preliminary Data Sheet Rev.0.9 14.12.2012 8GB DDR3 – SDRAM ECC SO-DIMM Features: 204 Pin ECC SO-UDIMM SLN08G72G2BE2MT-xxRT  8GByte in FBGA Technology       RoHS compliant Options:  Data Rate / Latency DDR3 1333 MT/s CL9 DDR3 1600 MT/s CL11  Module density 8GB with 18 dies and 2 rank  Standard Grade (TA) (TC) Marking -CC -DC    0°C to 70°C 0°C to 85°C  Environmental Requirements:  Operating temperature (ambient) Standard Grade 0°C to 70°C  Operating Humidity 10% to 90% relative humidity, noncondensing Operating Pressure 105 to 69 kPa (up to 10000 ft.) Storage Temperature -55°C to 100°C Storage Humidity 5% to 95% relative humidity, noncondensing Storage Pressure 1682 PSI (up to 5000 ft.) at 50°C            204-pin 72-bit DDR3 Small Outline, Dual-In-Line Double Data Rate synchronous DRAM Module Module organization: dual rank 1024M x 72 VDD = 1.35V and 1.5V VDDQ = 1.35V and 1.5V 1.5V I/O ( SSTL_15 compatible) Fly-by-bus with termination for C/A & CLK bus 2 On-board I C temperature sensor with integrated serial presence-detect (SPD) EEPROM Gold-contact pad This module is fully pin and functional compatible to the JEDEC EP3-12800 DDR3 SDRAM 72bit-SO-DIMM design spec. and JEDEC- Standard MO-268. (see www.jedec.org) The pcb and all components are manufactured according to the RoHS compliance specification [EU Directive 2002/95/EC Restriction of Hazardous Substances (RoHS)] DDR3 - SDRAM component Micron MT41K512M8RH-125:E 512Mx8 DDR3 SDRAM in PG-TFBGA-78 package 8-bit prefetch architecture Programmable CAS Latency, CAS Write Latency, Additive Latency, Burst Length and Burst Type. On-Die-Termination (ODT) and Dynamic ODT for improved signal integrity. Refresh, Self Refresh and Power Down Modes. ZQ Calibration for output driver and ODT. System Level Timing Calibration Support via Write Leveling and Multi Purpose Register (MPR) Read Pattern. Figure: mechanical dimensions 1 1 if no tolerances specified ± 0.15mm Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 1 of 17 preliminary Data Sheet Rev.0.9 14.12.2012 This Swissbit module is an industry standard 204-pin 8-byte DDR3 SDRAM ECC Small Outline Dual-In-line Memory Module (SO-UDIMM) which is organized as x72 high speed CMOS memory arrays. The module uses internally configured octal-bank DDR3 SDRAM devices. The module uses double data rate architecture to achieve high-speed operation. DDR3 SDRAM modules operate from a differential clock (CK and CK#). READ and WRITE accesses to a DDR3 SDRAM module is burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. The burst length is either four or eight locations. An auto precharge function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst access. The DDR3 SDRAM devices have a multibank architecture which allows a concurrent operation that is providing a high effective bandwidth. A self refresh mode is provided and a power-saving “powerdown” mode. All inputs and all full drive-strength outputs are SSTL_15 compatible. The DDR3 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM 2 using the standard I C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are utilized by the SO-UDIMM manufacturer (Swissbit) to identify the module type, the module’s organization and several timing parameters. The second 128 bytes are available to the end user. Module Configuration Organization DDR3 SDRAMs used Row Addr. Device Bank Addr. 1G x 72bit 18 x 512M x 8bit (4Gbit) 16 BA0, BA1, BA2 Column Refresh Addr. 10 Module Bank Select 8k S0#, S1# Module Dimensions in mm 67.60 (long) x 30(high) x 3.80 [max] (thickness) Timing Parameters Part Number Module Density Transfer Rate Clock Cycle/Data bit rate Latency SLN08G72G2BE2MT-CCRT 8GByte 10.6 GB/s 1.5ns/1333MT/s 9-9-9 SLN08G72G2BE2MT-DCRT 8GByte 12.8 GB/s 1.25ns/1600MT/s 11-11-11 Pin Name A0-9, A11 – A15 Address Inputs A10/AP Address Input / Autoprecharge Bit BA0 – BA2 Bank Address Inputs DQ0 – DQ63 Data Input / Output CB0 – CB07 ECC check bits DM0-DM8 Input Data Mask DQS0 – DQS8 Data Strobe, positive line DQS0# - DQS8# Data Strobe, negative line (only used when differential data strobe mode is enabled) RAS# Row Address Strobe CAS# Column Address Strobe WE# Write Enable CKE0 – CKE1 Clock Enable S0#, S1# Chip Select CK0 – CK1 Clock Inputs, positive line CK0# - CK1# Clock Inputs, negative line Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 2 of 17 preliminary Data Sheet Rev.0.9 14.12.2012 Event# Temperature event: The EVENT# pin is asserted by the temperature sensor when critical VDD Supply Voltage (1.5V± 0.075V) VREFDQ Reference voltage: DQ, DM (VDD/2) VREFCA Reference voltage: Control, command, and address (VDD/2) VSS Ground VTT Termination voltage: Used for control, command, and address (V DD/2). VDDSPD Serial EEPROM Positive Power Supply SCL Serial Clock for Presence Detect SDA Serial Data Out for Presence Detect SA0 – SA1 Presence Detect Address Inputs ODT0, ODT1 On-Die Termination NC No Connection Pin Configuration Frontside Symbol PIN PIN Symbol PIN Symbol PIN 1 VREFDQ 53 VSS 3 VSS 55 DQ24 5 DQ0 57 7 DQ1 9 103 A3 155 VSS 105 A1 157 DM5 DQ25 107 A0 159 DQ42 59 DM3 109 VDD 161 DQ43 VSS 61 VSS 111 CK0 163 VSS 11 DM0 63 DQ26 113 CK0# 165 DQ48 13 DQ2 65 DQ27 115 VDD 167 DQ49 15 DQ3 67 VSS 117 A10/AP 169 VSS 17 VSS 69 CB0 119 BA0 171 DQS6# 19 DQ8 71 CB1 121 WE# 173 DQS6 21 DQ9 123 VDD 175 VSS 23 VSS 73 VSS 125 CAS# 177 DQ50 25 DQS1# 75 DQS8# 127 S0# 179 DQ51 27 DQS1 77 DQS8 129 S1# 181 VSS 29 VSS 79 VSS 131 VDD 183 DQ56 31 DQ10 81 CB2 133 DQ32 185 DQ57 33 DQ11 83 CB3 135 DQ33 187 VSS 35 VSS 85 VDD 137 VSS 189 DM7 37 DQ16 87 CKE0 139 DQS4# 191 DQ58 39 DQ17 89 CKE1 141 DQS4 193 DQ59 41 VSS 91 BA2 143 VSS 195 VSS 43 DQS2# 93 VDD 145 DQ34 197 SA0 45 DQS2 95 A12/BC# 147 DQ35 199 VDDSPD 47 VSS 97 A8 149 VSS 201 SA1 49 DQ18 99 A5 151 DQ40 203 VTT 51 DQ19 101 VDD 153 DQ41 Key Symbol (Sig): Signal in brackets may be routed to the socket connector, but is not used on the module Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 3 of 17 preliminary Data Sheet Rev.0.9 14.12.2012 Backside Pin Symbol Pin Symbol Pin Symbol Pin Symbol 2 VSS 54 DQ28 104 A4 156 DQS5 4 DQ4 56 DQ29 106 A2 158 VSS 6 DQ5 58 VSS 108 BA1 160 DQ46 8 VSS 60 DQS3# 110 VDD 162 DQ47 10 DQS0# 62 DQS3 112 CK1 164 VSS 12 DQS0 64 VSS 114 CK1# 166 DQ52 14 VSS 66 DQ30 116 VDD 168 DQ53 16 DQ6 68 DQ31 118 NC(S3#) 170 VSS 18 DQ7 70 VSS 120 NC(S2#) 172 DM6 20 VSS 72 CB4 122 RAS# 174 DQ54 22 DQ12 124 VDD 176 DQ55 24 DQ13 74 CB5 126 ODT0 178 VSS 26 VSS 76 DM8 128 ODT1 180 DQ60 28 DM1 78 VSS 130 A13 182 DQ61 30 Reset# 80 CB6 132 VDD 184 VSS 32 VSS 82 CB7 134 DQ36 186 DQS7# 34 DQ14 84 VREFCA 136 DQ37 188 DQS7 36 DQ15 86 VDD 138 VSS 190 VSS 38 VSS 88 A15 140 DM4 192 DQ62 40 DQ20 90 A14 142 DQ38 194 DQ63 42 DQ21 92 A9 144 DQ39 196 VSS 44 DM2 94 VDD 146 VSS 198 EVENT# 46 VSS 96 A11 148 DQ44 200 SDA 48 DQ22 98 A7 150 DQ45 202 SCL 50 DQ23 100 A6 152 VSS 204 VTT 52 VSS 102 VDD 154 DQS5# Key (Sig): Signal in brackets may be routed to the socket connector, but is not used on the module Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 4 of 17 preliminary Data Sheet Rev.0.9 14.12.2012 FUNCTIONAL BLOCK DIAGRAMM 8GB DDR3 SDRAM SO-UDIMM, 2 RANK AND 18 COMPONENTS S1 S0 DQS4 DQS4 DM4 DQS0 DQS0 DM0 DM DQ0 DQ1 DQ2 I/O 0 I/O 1 I/O 2 DQ3 DQ4 DQ5 DQ6 DQ7 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DM DQS DQS I/O 0 I/O 1 I/O 2 D0 ZQ CS DQS DQS DM D9 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ DQ32 DQ33 DQ34 I/O 0 I/O 1 I/O 2 DQ35 DQ36 DQ37 DQ38 DQ39 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ40 DQ41 DQ42 I/O 0 I/O 1 I/O 2 DQ43 DQ44 DQ45 DQ46 DQ47 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ48 DQ49 DQ50 I/O 0 I/O 1 I/O 2 DQ51 DQ52 DQ53 DQ54 DQ55 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ56 DQ57 DQ58 I/O 0 I/O 1 I/O 2 CS DM DQS DQS I/O 0 I/O 1 I/O 2 D4 ZQ CS DQS DQS D13 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ DQS5 DQS5 DM5 DQS1 DQS1 DM1 DM DQ8 DQ9 DQ10 I/O 0 I/O 1 I/O 2 DQ11 DQ12 DQ13 DQ14 DQ15 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DM DQS DQS I/O 0 I/O 1 I/O 2 D1 ZQ CS DM DQS DQS D10 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ CS DM DQS DQS I/O 0 I/O 1 I/O 2 D5 ZQ CS DQS DQS D14 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ DQS6 DQS6 DM6 DQS2 DQS2 DM2 DM DQ16 DQ17 DQ18 I/O 0 I/O 1 I/O 2 DQ19 DQ20 DQ21 DQ22 DQ23 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DM DQS DQS I/O 0 I/O 1 I/O 2 D2 ZQ CS DM DQS DQS D11 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ CS DM DQS DQS I/O 0 I/O 1 I/O 2 D6 ZQ CS DQS DQS D15 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ DQS7 DQS7 DM7 DQS3 DQS3 DM3 DM DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 I/O 0 I/O 1 I/O 2 CS I/O 0 I/O 1 I/O 2 D3 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS DQS ZQ CS D12 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS DQS ZQ DQ59 DQ60 DQ61 DQ62 DQ63 CS DM DQS DQS I/O 0 I/O 1 I/O 2 D7 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D16 ZQ DQS8 DQS8 DM8 DM CB0 CB1 CB2 I/O 0 I/O 1 I/O 2 CB3 CB4 CB5 CB6 CB7 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 BA0-BA2 A0-A15 RAS CAS WE ODT0 ODT1 CKE0 CKE1 CK0,CK1 CK0,CK1 RESET Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen CS DM DQS DQS I/O 0 I/O 1 I/O 2 D8 ZQ I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D17 VDDSPD VDD/VDDQ SPD VREFDQ D0-D17 VREFCA D0-D17 VSS D0-D17 D0-D17 ZQ BA0-BA2: SDRAM D0-D17 A0-A15: SDRAM D0-D17 RAS: SDRAM D0-D17 CAS: SDRAM D0-D17 WE: SDRAM D0-D17 ODT: SDRAM D0-D8 ODT: SDRAM D9-D17 CKE: SDRAM D0-D8 CKE: SDRAM D9-D17 CK: SDRAM D0-D17 CK: SDRAM D0-D17 RESET: SDRAM D0-D17 Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S relationship must be maintained as shown. 3. DQ, DM, DQS/DQS resistors: Refer to associated topology diagram. 4. Refer to the appropriate clock wiring topology under the DIMM wiring details section of the JEDED document. 5. For each DRAM, a unique ZQ resistor is connected to GND. The ZQ resistor is 240O±1%. 6. Refer to associated figure for SPD details. www.swissbit.com eMail: info@swissbit.com Page 5 of 17 preliminary Data Sheet Rev.0.9 14.12.2012 MAXIMUM ELECTRICAL DC CHARACTERISTICS PARAMETER/ CONDITION Supply Voltage I/O Supply Voltage Voltage on any pin relative to VSS INPUT LEAKAGE CURRENT SYMBOL VDD VDDQ VIN, VOUT Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 0.95V (All other pins not under test = 0V) MIN -0.4 -0.4 -0.4 MAX 1.975 1.975 1.975 II UNITS V V V µA Command/Address -16 16 IOZ -16 -2 -5 16 2 5 µA IVREF -8 8 µA RAS#, CAS#, WE#, S#, CKE CK, CK# DM OUTPUT LEAKAGE CURRENT (DQ’s and ODT are disabled; 0V ≤ VOUT ≤ VDDQ) DQ, DQS, DQS# VREF LEAKAGE CURRENT ; VREF is on a valid level DC OPERATING CONDITIONS PARAMETER/ CONDITION Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage (system) Input High (Logic 1) Voltage Input Low (Logic 0) Voltage SYMBOL MIN VDD 1.425 VDDQ 1.425 VREF 0.49 x VDDQ VTT 0.49 x VDDQ-20mV VIH (DC) VREF + 0.1 VIL (DC) -0.3 NOM 1.5 1.5 0.50 x VDDQ 0.50 x VDDQ MAX 1.575 1.575 0.51x VDDQ 0.51x VDDQ+20mV VDDQ + 0.3 VREF – 0.1 UNITS V V V V V V AC INPUT OPERATING CONDITIONS PARAMETER/ CONDITION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage SYMBOL VIH (AC) VIL (AC) MIN VREF + 0.175 - MAX VREF - 0.175 UNITS V V CAPACITANCE At DDR3 data rates, it is recommended to simulate the performance of the module to achieve optimum values. When inductance and delay parameters associated with trace lengths are used in simulations, they are significantly more accurate and realistic than a gross estimation of module capacitance. Simulations can then render a considerably more accurate result. JEDEC modules are now designed by using simulations to close timing budgets. Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 6 of 17 preliminary Data Sheet Rev.0.9 14.12.2012 IDD Specifications and Conditions (0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.5V ± 0.075V, VDD = +1.5V ± 0.075V) Parameter & Test Condition OPERATING CURRENT *) : One device bank Active-Precharge; tRC= tRC (IDD); tCK = tCK (IDD); CKE is HIGH, CS# is HIGH between valid commands; DQ inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles OPERATING CURRENT *) : One device bank; Active-Read-Precharge; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC= tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address inputs changing once every two clock cycles; Data Pattern is same as IDD4W Fast Exit PRECHARGE POWER-DOWN CURRENT: All device banks idle; Power-down mode; tCK = tCK (IDD); CKE is LOW; All Control and Slow Exit Address bus inputs are not changing; DQ’s are floating at VREF PRECHARGE QUIET STANDBY CURRENT: All device banks idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; All Control and Address bus inputs are not changing; DQ’s are floating at VREF PRECHARGE STANDBY CURRENT: All device banks idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; All other Control and Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle ACTIVE POWER-DOWN CURRENT: All device banks open; tCK = tCK (IDD); CKE is LOW; All Control and Address bus inputs are not changing; DQ’s are floating at VREF (always fast exit) ACTIVE STANDBY CURRENT: All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid commands; All other Control and Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle OPERATING READ CURRENT: All device banks open, Continuous burst reads; One module rank active; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 Symbol max. Unit 12800 CL11 10600 CL9 IDD0 495 495 mA IDD1 585 585 mA IDD2P 270 270 mA 270 270 IDD2Q 360 360 mA IDD2N 450 360 mA IDD3P 360 360 mA IDD3N 540 540 mA IDD4R 900 765 mA www.swissbit.com eMail: info@swissbit.com Page 7 of 17 preliminary Data Sheet Parameter & Test Condition OPERATING WRITE CURRENT: All device banks open, Continuous burst writes; One module rank active; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle BURST REFRESH CURRENT: tCK = tCK (IDD); refresh command at every tRFC (IDD) interval, CKE is HIGH, CS# is HIGH between valid commands; All other Control and Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle SELF REFRESH CURRENT: CK and CK# at 0V; CKE ≤ 0.2V; All other Control and Address bus inputs are floating at VREF; DQ’s are floating at VREF OPERATING CURRENT*) : Four device bank interleaving READs, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) – 1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are not changing during DESELECT; DQ inputs changing once per clock cycle Symbol Rev.0.9 14.12.2012 max. Unit 12800 CL11 10600 CL9 IDD4W 945 810 mA IDD5 2610 2160 mA IDD6 270 270 mA IDD7 1665 1305 mA *) Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW) mode. TIMING VALUES USED FOR IDD MEASUREMENT IDD MEASUREMENT CONDITIONS SYMBOL 128000 CL11 11 CL (IDD) 13.75 tRCD (IDD) 48.75 tRC (IDD) 5 tRRD (IDD) 1.25 tCK (IDD) 35 tRAS MIN (IDD) 70’200 tRAS MAX (IDD) 13.75 tRP (IDD) 260 tRFC (IDD) Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen 10600 CL9 9 13.5 49.5 6 1.5 36 70’200 13.5 260 Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 Unit tCK ns ns ns ns ns ns ns ns www.swissbit.com eMail: info@swissbit.com Page 8 of 17 preliminary Data Sheet Rev.0.9 14.12.2012 DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.5V ± 0.075V, VDD = +1.5V ± 0.075V) AC CHARACTERISTICS PARAMETER CL = 11 CL = 10 CL = 9 CL = 8 CL = 7 CL = 6 Internal READ command to first data CK high-level width CK low-level width Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# DQ and DM input setup time relative to DQS SYMBOL tCK (11) tCK (10) tCK (9) tCK (8) tCK (7) tCK (6) tAA tCH (AVG) tCL (AVG) tHZ tLZ tDS (base) 12800 CL11 MIN MAX 1.25