SEU01G64A3BF1SA-25R

Data Sheet Rev.1.2 18.11.2010 1GB DDR2 – SDRAM UDIMM Features: 240 Pin UDIMM SEU01G64A3BF1SA-25R 1GB PC2-6400 in FBGA Technology RoHS compliant Options:  Data Rate / Latency DDR2 800 MT/s CL6 DDR2 667 MT/s CL5  Module Density 1024MB with 8 dies and 1 rank  Standard Grade Marking -25 -30       240-pin 64-bit Dual-In-Line Double Data Rate Synchronous DRAM Module  Module organization: single rank 128M x 64    VDD = 1.8V ±0.1V, VDDQ 1.8V ±0.1V 1.8V I/O ( SSTL_18 compatible) Auto Refresh (CBR) and Self Refresh 8k Refresh every 64ms Serial Presence Detect with EEPROM Gold-contact pad This module is fully pin and functional compatible to the JEDEC PC2-6400 spec. and JEDEC- Standard MO-237. (see www.jedec.org) The pcb and all components are manufactured according to the RoHS compliance specification [EU Directive 2002/95/EC Restriction of Hazardous Substances (RoHS)]     (TA) (Tc) 0°C to 70°C 0°C to 85°C Environmental Requirements:   Operating temperature (ambient) standard Grade 0°C to 70°C Operating Humidity 10% to 90% relative humidity, noncondensing Operating Pressure 105 to 69 kPa (up to 10000 ft.) Storage Temperature -55°C to 100°C Storage Humidity 5% to 95% relative humidity, noncondensing Storage Pressure 1682 PSI (up to 5000 ft.) at 50°C            DDR2 - SDRAM component SAMSUNG K4T1G084QF DIE Rev. F 128Mx8 DDR2 SDRAM in FBGA-60 package 4-bit prefetch architecture DLL to align DQ and DQS transitions with CK Multiple internal device banks for concurrent operation Programmable CAS latency (CL) Posted CAS additive latency (AL) WRITE latency = READ latency – 1 tCK Programmable burst length: 4 or 8 Adjustable data-output drive strength On-die termination (ODT) Figure: mechanical dimensions 1 1 if no tolerances specified ± 0.15mm Swissbit AG Industriestrass 4 CH-9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 1 of 14 Data Sheet Rev.1.2 18.11.2010 This Swissbit module is an industry standard 240-pin 8-byte DDR2 SDRAM Dual-In-line Memory Module (UDIMM) which is organized as x64 high speed CMOS memory arrays. The module uses internally configured octal-bank DDR2 SDRAM devices. The module uses double data rate architecture to achieve high-speed operation. DDR2 SDRAM modules operate from a differential clock (CK and CK#). READ and WRITE accesses to a DDR2 SDRAM module is burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. The burst length is either four or eight locations. An auto precharge function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst access. The DDR2 SDRAM devices have a multibank architecture which allows a concurrent operation that is providing a high effective bandwidth. A self refresh mode is provided and a power-saving “power-down” mode. All inputs and all full drive-strength outputs are SSTL_18 compatible. The DDR2 SDRAM module uses the optional serial presence detect (SPD) function implemented via serial 2 EEPROM using the standard I C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are utilized by the DIMM manufacturer (swissbit) to identify the module type, the module’s organization and several timing parameters. The second 128 bytes are available to the end user. Module Configuration Organization DDR2 SDRAMs used Row Addr. Device Bank Addr. Column Addr. Refresh Module Bank Select 128M x 64bit 8 x 128M x 8bit (1024Mbit) 14 BA0, BA1, BA2 10 8k S0# Module Dimensions in mm 133.35 (long) x 30(high) x 2.70 [max] (thickness) Timing Parameters Part Number SEU01G64A3BF1SA-25R SEU01G64A3BF1SA-30R Module Density 1024 MB 1024 MB Transfer Rate 6.4 GB/s 5.3 GB/s Clock Cycle/Data bit rate 2.5ns/800MT/s 3.0ns/667MT/s Latency 6-6-6 5-5-5 Pin Name A0-9, A11 – A13 Address Inputs A10/AP Address Input / Autoprecharge Bit BA0 – BA2 Bank Address Inputs DQ0 – DQ63 Data Input / Output DM0-DM7 Input Data Mask DQS0 - DQS7 Data Strobe, positive line DQS0# - DQS7# Data Strobe, negative line (only used when differential data strobe mode is enabled) RAS# Row Address Strobe CAS# Column Address Strobe WE# Write Enable CKE0 Clock Enable S0# Chip Select Swissbit AG Industriestrass 4 CH-9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 2 of 14 Data Sheet Rev.1.2 CK0 Clock Inputs, positive line CK0# Clock Inputs, negative line VDD Supply Voltage (1.8V± 0.1V) VREF Input / Output Reference VSS Ground VDDSPD Serial EEPROM Positive Power Supply SCL Serial Clock for Presence Detect SDA Serial Data Out for Presence Detect SA0 – SA1 Presence Detect Address Inputs ODT0 On-Die Termination NC No Connection 18.11.2010 Pin Configuration PIN # Front Side PIN # Back Side PIN # Front Side PIN # Back Side 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS NC(RESET#) NC VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 VSS DQ4 DQ5 VSS DM0 (DQS9) NC (DQS9#) VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 (DQS10) NC (DQS10#) VSS NC (CK1) NC (CK1#) VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 (DQS11) NC (DQS11#) VSS DQ22 DQ23 VSS DQ28 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 A4 VDDQ A2 VDD VSS VSS VDD NC (Par_In) VDD A10/AP BA0 VDDQ WE# CAS# VDDQ NC (S1#) NC (ODT1) VDDQ VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DQS5# 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 VDDQ A3 A1 VDD CK0 CK0# VDD A0 VDD BA1 VDDQ RAS# S0# VDDQ ODT0 A13 VDD VSS DQ36 DQ37 VSS DM4 (DQS13) NC (DQS13#) VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DM5 (DQS14) NC (DQS14#) Swissbit AG Industriestrass 4 CH-9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 3 of 14 Data Sheet Rev.1.2 18.11.2010 PIN # Front Side PIN # Back Side PIN # Front Side PIN # Back Side 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 DQ24 DQ25 VSS DQS3# DQS3 VSS DQ26 DQ27 VSS NC (CB0) NC (CB1) VSS NC (DQS8#) NC (DQS8) VSS NC (CB2) NC (CB3) VSS VDD CKE0 VDD BA2 NC(Par_Out) VDDQ A11 A7 VDD A5 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 DQ29 VSS DM3 (DQS12) NC (DQS12#) VSS DQ30 DQ31 VSS NC (CB4) NC (CB5) VSS NC (DM8,DQS17) NC (DQS17#) VSS NC (CB6) NC (CB7) VSS VDDQ NC (CKE1) VDD NC (A15) NC (A14) VDDQ A12 A9 VDD A8 A6 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS SA2 NC (TEST) VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DQS7# DQS7 VSS DQ58 DQ59 VSS SDA SCL 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK2/RFU CK2#/RFU VSS DM6 (DQS15) NC (DQS15#) VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7 (DQS16) NC (DQS16#) VSS DQ62 DQ63 VSS VDDSPD SA0 SA1 (Sig): Signal in brackets may be routed to the socket connector, but is not used on the module Swissbit AG Industriestrass 4 CH-9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 4 of 14 Data Sheet Rev.1.2 18.11.2010 FUNCTIONAL BLOCK DIAGRAMM 1024MB DDR2 SDRAM DIMM, 1 RANK AND 8 COMPONENTS Swissbit AG Industriestrass 4 CH-9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 5 of 14 Data Sheet Rev.1.2 18.11.2010 MAXIMUM ELECTRICAL DC CHARACTERISTICS PARAMETER/ CONDITION Supply Voltage I/O Supply Voltage VDDL Supply Voltage Voltage on any pin relative to VSS INPUT LEAKAGE CURRENT SYMBOL VDD VDDQ VDDL Vin, Vout Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 0.95V (All other pins not under test = 0V) MIN -1.0 -0.5 -0.5 -0.5 MAX 2.3 2.3 2.3 2.3 II UNITS V V V V µA Command/Address -40 40 IOZ -20 -5 -5 20 5 5 µA IVREF -16 16 µA NOM 1.8 1.8 1.8 0.50 x VDDQ VREF MAX 1.9 1.9 1.9 0.51x VDDQ VREF + 0.04 VDDQ + 0.3 VREF – 0.125 UNITS V V V V V V V MIN VREF + 0.25 - MAX VREF - 0.25 UNITS V V RAS#, CAS#, WE#, S#, CKE CK, CK# DM OUTPUT LEAKAGE CURRENT (DQ’s and ODT are disabled; 0V ≤ VOUT ≤ VDDQ) DQ, DQS, DQS# VREF LEAKAGE CURRENT ; VREF is on a valid level DC OPERATING CONDITIONS PARAMETER/ CONDITION Supply Voltage I/O Supply Voltage VDDL Supply Voltage I/O Reference Voltage I/O Termination Voltage (system) Input High (Logic 1) Voltage Input Low (Logic 0) Voltage SYMBOL VDD VDDQ VDDL VREF VTT VIH (DC) VIL (DC) MIN 1.7 1.7 1.7 0.49 x VDDQ VREF – 0.04 VREF + 0.125 -0.3 AC INPUT OPERATING CONDITIONS PARAMETER/ CONDITION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage SYMBOL VIH (AC) VIL (AC) CAPACITANCE At DDR2 data rates, it is recommended to simulate the performance of the module to achieve optimum values. When inductance and delay parameters associated with trace lengths are used in simulations, they are significantly more accurate and realistic than a gross estimation of module capacitance. Simulations can then render a considerably more accurate result. JEDEC modules are now designed by using simulations to close timing budgets. Swissbit AG Industriestrass 4 CH-9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 6 of 14 Data Sheet Rev.1.2 18.11.2010 IDD Specifications and Conditions (0°C ≤ TCASE ≤ + 85°C ; VDDQ = +1.8V ± 0.1V, VDD = +1.8V ± 0.1V) Parameter & Test Condition OPERATING CURRENT *) : One device bank Active-Precharge; tRC= tRC (IDD); tCK = tCK (IDD); CKE is HIGH, CS# is HIGH between valid commands; DQ inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles OPERATING CURRENT *) : One device bank; Active-Read-Precharge; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC= tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address inputs changing once every two clock cycles; Data Pattern is same as IDD4W PRECHARGE POWER-DOWN CURRENT: All device banks idle; Power-down mode; tCK = tCK (IDD); CKE is LOW; All Control and Address bus inputs are not changing; DQ’s are floating at VREF PRECHARGE QUIET STANDBY CURRENT: All device banks idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; All Control and Address bus inputs are not changing; DQ’s are floating at VREF PRECHARGE STANDBY CURRENT: All device banks idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; All other Control and Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle Fast PDN Exit ACTIVE POWER-DOWN MR[12] = 0 CURRENT: All device banks open; tCK = tCK Slow PDN Exit (IDD); CKE is LOW; All Control MR[12] = 1 and Address bus inputs are not changing; DQ’s are floating at VREF ACTIVE STANDBY CURRENT: All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid commands; All other Control and Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle OPERATING READ CURRENT*) : All device banks open, Continuous burst reads; One module rank active; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle Swissbit AG Industriestrass 4 CH-9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 Symbol max. Unit 6400-666 5300-555 IDD0 360 344 mA IDD1 408 384 mA IDD2P 80 80 mA IDD2Q 160 160 mA IDD2N 200 192 mA IDD3P 184 176 mA 120 120 IDD3N 256 240 mA IDD4R 640 560 mA www.swissbit.com eMail: info@swissbit.com Page 7 of 14 Data Sheet Parameter & Test Condition OPERATING WRITE CURRENT*) : All device banks open, Continuous burst writes; One module rank active; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle BURST REFRESH CURRENT: tCK = tCK (IDD); refresh command at every tRFC (IDD) interval, CKE is HIGH, CS# is HIGH between valid commands; All other Control and Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle SELF REFRESH CURRENT: CK and CK# at 0V; CKE ≤ 0.2V; All other Control and Address bus inputs are floating at VREF; DQ’s are floating at VREF OPERATING CURRENT*) : Four device bank interleaving READs, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) – 1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are not changing during DESELECT; DQ inputs changing once per clock cycle Rev.1.2 18.11.2010 Max. Symbol Unit 6400-666 5300-555 IDD4W 536 480 mA IDD5 840 800 mA IDD6 80 80 mA IDD7 1280 1160 mA *) Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW) mode. TIMING VALUES USED FOR IDD MEASUREMENT IDD MEASUREMENT CONDITIONS SYMBOL 6400-666 CL (IDD) 6 tRCD (IDD) 15 tRC (IDD) 60 tRRD (IDD) 7.5 tCK (IDD) 2.5 tRAS MIN (IDD) 45 tRAS MAX 70,000 (IDD) tRP (IDD) 15 tRFC (IDD) 105 Swissbit AG Industriestrass 4 CH-9552 Bronschhofen 5300-555 5 15 60 7.5 3.0 45 Unit 70,000 ns 15 105 ns ns Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 tCK ns ns ns ns ns www.swissbit.com eMail: info@swissbit.com Page 8 of 14 Data Sheet Rev.1.2 18.11.2010 DDR2 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (0°C ≤ TCASE ≤ + 85°C ; VDDQ = +1.8V ± 0.1V, VDD = +1.8V ± 0.1V) AC CHARACTERISTICS PARAMETER Clock cycle time CL = 6 CL = 5 CL = 4 CL = 3 CK high-level width CK low-level width Half clock period Access window (output) of DQS from CK/CK# Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# DQ and DM input setup time relative to DQS DQ and DM input hold time relative to DQS DQ and DM input pulse width ( for each input ) Data hold skew factor DQ-DQS hold, DQS to first DQ to go non-valid, per access Data valid output window DQS input high pulse width DQS input low pulse width DQS falling edge to CK rising - setup time DQS falling edge from CK rising - hold time DQS –DQ skew, DQS to last DQ valid, per group, per access DQS read preamble DQS read postamble DQS write preamble DQS write preamble setup time DQS write postamble Positive DQS latching edge to associated clock edge Write command to first DQS latching transition Address and control input pulse width ( for each input ) Address and control input setup time Swissbit AG Industriestrass 4 CH-9552 Bronschhofen SYMBOL tCK (6) tCK (5) tCK (4) tCK (3) tCH tCL tHP tAC 6400-666 MIN MAX 2.5 8.0 3.08.03.75 8.0 0.48 0.52 0.48 0.52 min (tCH, tCL) -0.40 tHZ +0.40 5300-555 MIN MAX Unit ns ns ns ns tCK tCK 3.0 3.75 5.0 0.48 0.48 min (tCH, tCL) 8.0 8.0 8.0 0.52 0.52 -0.45 +0.45 ns +0.45 ns tAC max ps (= tAC max) -0.45 +0.45 (= tAC min) (= tAC max) tLZ tAC min tDS 0.05 0.10 ns tDH 0.125 0.175 ns tDIPW 0.35 0.35 tCK tQHS tAC max 0.3 0.34 ns ns tHP - tQHS tHP - tQHS tQH - tDQSQ tQH - tDQSQ 0.35 0.35 0.35 0.35 ns tCK tCK tDSS 0.2 0.2 tCK tDSH 0.2 0.2 tCK tQH tDVW tDQSH tDQSL tDQSQ tRPRE tRPST tWPRE tWPRES tWPST tDQSS tIPW tIS 0.2 ns 0.24 ns 1.1 0.6 0.6 tCK tCK tCK ns tCK 0.9 0.4 0.35 0 0.4 1.1 0.6 0.6 0.9 0.4 0.35 0 0.4 - 0.25 + 0.25 - 0.25 + 0.25 tCK WLtDQSS WL+ tDQSS WLtDQSS WL+ tDQSS tCK 0.6 0.6 tCK 0.175 0.2 ns Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 9 of 14 Data Sheet Rev.1.2 18.11.2010 DDR2 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued) (0°C ≤ TCASE ≤ + 85°C ; VDDQ = +1.8V ± 0.1V, VDD = +1.8V ± 0.1V) AC CHARACTERISTICS PARAMETER Address and control input hold time CAS# to CAS# command delay ACTIVE to ACTIVE (same bank) command period ACTIVE bank a to ACTIVE bank b command ACTIVE to READ or WRITE delay Four bank Activate period ACTIVE to PRECHARGE command Internal READ to precharge command delay Write recovery time Auto precharge write recovery + precharge time Internal WRITE to READ command delay PRECHARGE command period PRECHARGE ALL command period LOAD MODE command cycle time CKE low to CK, CK# uncertainty REFRESH to ACTIVE or REFRESH to REFRESH command interval Average periodic refresh interval Exit SELF REFRESH to nonREAD command Exit SELF REFRESH to READ command Exit SELF REFRESH timing reference ODT turn-on delay ODT turn-on SYMBOL tIH 6400-666 MIN MAX 0.25 5300-555 MIN MAX 0.275 Unit ns tCCD tRC 2 60 2 60 tCK ns tRRD 7.5 7.5 ns tRCD 15 15 ns tFAW tRAS 37.5 45 tRTP 7.5 7.5 ns tWR tDAL 15 tWR + tRP 15 tWR + tRP ns ns tWTR 7.5 7.5 ns tRP tRPA 15 tRP + tCK 15 tRP + tCK ns ns tMRD 2 2 tCK tDELAY tRFC tREFI tXSNR 70,000 tIS + tCK + tIH 105 70,000 37.5 45 70,000 tIS + tCK + tIH 105 70,000 7.8 7.8 ns ns tCK ns µs ns tRFC(min) + 10 tRFC(min) + 10 tXSRD 200 200 tCK tISXR tIS tIS ps tAOND tAON 2 2 2 2 tAC(min) tAC(max) + 1,000 tAC(min) tAC(max) + 1,000 ODT turn-off delay ODT turn-off tAOFD tAOF 2.5 2.5 2.5 2.5 tAC(min) tAC(min) ODT turn-on (power-down mode) tAONPD tAC(min) + 2,000 ODT turn-off (power-down mode) tAOFPD tAC(min) + 2,000 tAC(max) + 600 2 x tCK + tAC(max) + 1,000 2.5 x tCK + tAC(max) + 1,000 ODT to power-down entry latency tANPD 3 Swissbit AG Industriestrass 4 CH-9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 tAC(max) + 600 tAC(min) + 2 x tCK + 2,000 tAC(max) + 1,000 tAC(min) + 2.5 x tCK + 2,000 tAC(max) + 1,000 3 tCK ps tCK ps ps ps tCK www.swissbit.com eMail: info@swissbit.com Page 10 of 14 Data Sheet Rev.1.2 18.11.2010 DDR2 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued) (0°C ≤ TCASE ≤ + 85°C ; VDDQ = +1.8V ± 0.1V, VDD = +1.8V ± 0.1V) AC CHARACTERISTICS PARAMETER ODT power-down exit latency ODT enable from MRS command Exit active power-down to READ command, MR [bit 12 = 0] Exit active power-down to READ command, MR [bit 12 = 1] Exit precharge power-down to any non-READ command CKE minimum high/low time Swissbit AG Industriestrass 4 CH-9552 Bronschhofen SYMBOL tAXPD tMOD 6400-666 MIN MAX 8 12 5300-555 MIN MAX 8 12 Unit tCK ns tXARD 2 2 tCK tXARDS 8 – AL 7 - AL tCK tXP 2 2 tCK tCKE 3 3 tCK Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 11 of 14 Data Sheet Rev.1.2 18.11.2010 SERIAL PRESENCE-DETECT MATRIX BYTE DESCRIPTION 6400-666 5300-555 0 NUMBER OF SPD BYTES USED 0x80 1 2 TOTAL NUMBER OF BYTES IN SPD DEVICE FUNDAMENTAL MEMORY TYPE 0x08 0x08 3 0x0E 5 NUMBER OF ROW ADDRESSES ON ASSEMBLY NUMBER OF COLUMN ADDRESSES ON ASSEMBLY DIMM HIGHT AND MODULE RANKS 6 7 MODULE DATA WIDTH MODULE DATA WIDTH (continued) 0x40 0x00 8 MODULE VOLTAGE INTERFACE LEVELS (VDDQ) SDRAM CYCLE TIME, (tCK ) [max CL] CAS LATENCY = 6 (6400), CL = 5 (5300) 0x05 4 9 0x0A 0x60 0x25 0x30 0x40 0x45 10 SDRAM ACCESS FROM CLOCK, (tAC) [max CL] CAS LATENCY = 6 (6400); CL = 5 (5300) 11 12 MODULE CONFIGURATION TYPE REFRESH RATE / TYPE 0x00 0x82 13 14 SDRAM DEVICE WIDTH (PRIMARY SDRAM) ERROR- CHECKING SDRAM DATA WIDTH 0x08 0x00 16 MINIMUM CLOCK DELAY, BACK-TO-BACK RANDOM COLUMN ACCESS BURST LENGTHS SUPPORTED 17 18 NUMBER OF BANKS ON SDRAM DEVICE CAS LATENCIES SUPPORTED 19 20 MODULE THICKNESS DDR2 DIMM TYPE 0x01 0x02 21 SDRAM MODULE ATTRIBUTES 0x00 22 SDRAM DEVICE ATTRIBUTES: Weak Driver and 50 ODT 0x07 15 23 24 25 SDRAM CYCLE TIME, (tCK) [max CL – 1] CAS LATENCY = 5 (6400), CL = 4 (5300) SDRAM ACCESS FROM CK, (tAC) [max CL – 1] CAS LATENCY = 5 (6400), CL = 4 (5300) SDRAM CYCLE TIME, (tCK) [max CL – 2] CAS LATENCY = 4 (6400), CL = 3 (5300) 0x00 0x0C 0x08 0x70 0x38 0x30 0x3D 0x45 0x50 0x3D 0x50 0x50 0x60 26 SDRAM ACCESS FROM CK, (tAC) [max CL – 2] CAS LATENCY = 4 (6400), CL = 3 (5300) 27 28 MINIMUM ROW PRECHARGE TIME, (tRP) MINIMUM ROW ACTIVE TO ROW ACTIVE, (tRRD) 0x3C 0x1E 29 30 MINIMUM RAS# TO CAS# DELAY, (tRCD) MINIMUM RAS# PULSE WIDTH, (tRAS) 0x3C 0x2D 31 MODULE BANK DENSITY 0x01 Swissbit AG Industriestrass 4 CH-9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 12 of 14 Data Sheet Rev.1.2 18.11.2010 SERIAL PRESENCE-DTECT MATRIX (continued) BYTE DESCRIPTION 6400-666 5300-555 32 ADDRESS AND COMMAND SETUP TIME, (tISb) 0x17 0x20 33 ADDRESS AND COMMAND HOLD TIME, (tIHb) 0x25 0x27 34 DATA / DATA MASK INPUT SETUP TIME, (tDSb) 0x05 0x10 35 DATA / DATA MASK INPUT HOLD TIME, (tDHb) 0x12 36 WRITE RECOVERY TIME, (tWR) 0x3C 37 WRITE to READ Command Delay, (tWTR) 0x1E 38 READ to PRECHARGE Command Delay, (tRTP) 0x1E 39 Mem Analysis Probe 0x00 40 41 Extension for Bytes 41 and 42 MIN ACTIVE AUTO REFRESH TIME, (tRC) MINIMUM AUTO REFRESH TO ACTIVE / AUTO REFRESH COMMAND PERIOD, (tRFC) SDRAM DEVICE MAX CYCLE TIME, (tCKMAX) 0x06 0x3C 42 43 44 45 46 47-61 SPD REVISION 63 CHECKSUM FOR BYTES 0-62 0x18 0x1E 0x22 0x00 0x00 0x13 MANUFACTURER`S JEDEC ID CODE 68-71 MANUFACTURER`S JEDEC ID CODE (continued) 73-90 0x80 0x14 0xE1 64-67 72 0x7F SDRAM DEVICE MAX DQS-DQ SKEW TIME, (tDQSQ) SDRAM DEVICE MAX READ DATA HOLD SKEW FACTOR, (tQHS) PLL Relock Time Optional Features, not supported 62 0x17 0x17 0x7F7F7FDA 0x00 MANUFACTURING LOCATION X “SEU01G64A3BF1SA-xx” MODULE PART NUMBER (ASCII) 91 PCB IDENTIFICATION CODE X 92 IDENTIFICATION CODE (continued) X 93 YEAR OF MANUFACTURE IN BCD X 94 WEEK OF MANUFACTURE IN BCD X 95-98 99-127 MODULE SERIAL NUMBER MANUFACTURER-SPECIFIC DATA (RSVD) X X 128-255 Open for customer use 0xff Part Number Code S E U 01G 64 A3 B F 1 SA 1 2 3 4 5 6 7 8 9 10 - 25 * R 11 12 13 *RoHs compl. DDR2 800MT/s Swissbit AG SDRAM DDR2 240 Pin Unbuffered 1.8V Depth (1024MB) Width PCB-Type (B62URCD) Chip Vendor (Samsung) 1 Module Rank Chip Rev. F Chip organisation x8 * optional / additional information Swissbit AG Industriestrass 4 CH-9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 13 of 14 Data Sheet Rev.1.2 18.11.2010 Locations Swissbit AG Industriestrasse 4 – 8 CH – 9552 Bronschhofen Switzerland Phone: +41 (0)71 913 03 03 Fax: +41 (0)71 913 03 15 _____________________________ Swissbit Germany GmbH Wolfener Strasse 36 D – 12681 Berlin Germany Phone: +49 (0)30 93 69 54 – 0 Fax: +49 (0)30 93 69 54 – 55 _____________________________ Swissbit NA, Inc. 14 Willett Avenue, Suite 301A Port Chester, NY 10573 USA Phone: +1 914 935 1400 Fax: +1 914 935 9865 _____________________________ Swissbit NA, Inc. 3913 Todd Lane, Suite – 307 Austin, TX 78744 USA Phone: +1 512 302 9001 Fax: +1 512 302 4808 _____________________________ Swissbit Japan, Inc. 3F Core Koenji, 2-1-24 Koenji-Kita, Suginami-Ku, Tokyo 166-0002 Japan Phone: +81 3 5356 3511 Fax: +81 3 5356 3512 Swissbit AG Industriestrass 4 CH-9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 14 of 14