nRF2460
2.4 GHz wireless mono audio streamer
Product Specification v1.0
Features
•
•
•
•
•
•
•
•
•
•
•
•
World-wide 2.4 GHz ISM band operation
6x6 mm 36 pin QFN package
4 Mbps on-air data rate
Mono 32 kHz audio rate
16 bit resolution
I2S interface for audio support
SPI or 2-wire interface to transfer
bi-directional control data
On-chip voltage regulators
Few external components
Programmable latency
Quality of Service engine
Option to synchronize two pairs of audio
receivers
Applications
•
•
Wireless microphone
Subwoofer
All rights reserved.
Reproduction in whole or in part is prohibited without the prior written permission of the copyright holder.
2011-6-28
nRF2460 Product Specification
Liability disclaimer
Nordic Semiconductor ASA reserves the right to make changes without further notice to the product to
improve reliability, function or design. Nordic Semiconductor ASA does not assume any liability arising out
of the application or use of any product or circuits described herein. Except where mandated by
government requirements, testing of all parameters of each product is not necessarily performed.
Life support applications
Nordic Semiconductor’s products are not designed for use in life support appliances, devices, or systems
where malfunction of these products can reasonably be expected to result in personal injury. Nordic
Semiconductor ASA customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Nordic Semiconductor ASA for any damages resulting from such
improper use or sale.
Datasheet status
Objective Product Specification
Preliminary Product Specification
Product Specification
This product specification contains target specifications for
product development.
This product specification contains preliminary data,
supplementary data may be published from Nordic
Semiconductor ASA later.
This product specification contains final product
specifications. Nordic Semiconductor ASA reserves the
right to make changes at any time without notice to improve
design and supply the best possible product.
Contact details
For your nearest dealer, please see www.nordicsemi.com
Main office:
Otto Nielsens veg 12
7004 Trondheim
Phone: +47 72 89 89 00
Fax: +47 72 89 89 89
Revision 1.0
Page 2 of 56
nRF2460 Product Specification
Revision History
Date
June 2011
Version
v1.0
Description
RoHS statement
Nordic Semiconductor’s products meet the requirements of Directive 2002/95/EC of the European
Parliament and of the Council on the Restriction of Hazardous Substances (RoHS). Complete hazardous
substance reports as well as material composition reports for all active Nordic Semiconductor products can
be found on our web site www.nordicsemi.com.
Revision 1.0
Page 3 of 56
nRF2460 Product Specification
Contents
1
Introduction .................................................................................................6
1.1
Prerequisites.........................................................................................6
1.2
Writing Conventions..............................................................................6
2
Product overview ........................................................................................7
2.1
Features................................................................................................7
2.2
Block diagram .......................................................................................7
2.2.1
Pin assignments ...............................................................................8
2.3
Pin functions .........................................................................................9
2.3.1
Modes of operation...........................................................................10
2.3.2
Communication and data transfer principle......................................10
2.3.3
Mode- and interface alternatives ......................................................12
2.3.4
Audio transmitter (ATX)....................................................................13
2.3.5
Audio Receiver (ARX) ......................................................................14
2.3.6
Blocks and functionality common to ATX and ARX..........................15
3
Operation overview .....................................................................................17
3.1
Power on / RESET sequence ...............................................................17
3.2
RF link initialization ...............................................................................17
3.2.1
Idle state...........................................................................................17
3.2.2
Link-locate state ...............................................................................17
3.2.3
Synchronization state .......................................................................18
3.3
Audio channel .......................................................................................18
3.3.1
Audio receiver clock rate generation ................................................18
3.3.2
Audio transmitter clock rate generation............................................18
3.4
Control channel.....................................................................................18
3.5
Register map ........................................................................................19
4
Digital I/O......................................................................................................21
4.1
Digital I/O behavior during RESET .......................................................21
4.2
Audio interface......................................................................................21
4.2.1
I2S audio interface ...........................................................................21
4.2.2
Audio interface functionality .............................................................22
4.2.3
ATX audio interface control ..............................................................23
4.2.4
ARX audio interface control..............................................................24
4.2.5
I2S audio interface timing.................................................................25
4.3
Control interfaces..................................................................................26
4.3.1
Slave interface and pin configuration ...............................................26
4.3.2
SPI slave interface ...........................................................................26
4.3.3
2-wire slave interface .......................................................................27
4.3.4
Control interface timing ....................................................................29
4.4
Data channel.........................................................................................31
4.4.1
Typical transfer of data from ATX to ARX ........................................32
4.4.2
Typical transfer of data from ARX to ATX ........................................32
5
Quality of Service (QoS) and RF protocol.................................................33
5.1
Link establishment ................................................................................33
5.2
RF protocol ...........................................................................................33
Revision 1.0
Page 4 of 56
nRF2460 Product Specification
5.3
Adaptive Frequency Hopping (AFH).....................................................33
5.3.1
Adapting to the RF environment.......................................................35
5.4
Link registers ........................................................................................36
5.4.1
Mute behavior...................................................................................36
5.4.2
RF link latency..................................................................................37
5.5
RF output power ...................................................................................37
5.6
Sync delay signal..................................................................................38
6
Interrupts......................................................................................................39
7
RESET output ..............................................................................................40
8
Power-down control....................................................................................41
8.1
Activation of power-down mode............................................................41
8.2
Wake up from power down ...................................................................41
8.3
Power down current..............................................................................41
9
Register update over the control channel ................................................42
9.1
Register update and device relink ........................................................43
10 Test mode ....................................................................................................44
11 Electrical specifications .............................................................................45
12 Absolute maximum ratings ........................................................................47
13 Mechanical specifications ..........................................................................48
14 Ordering information ..................................................................................50
14.1
Package marking ..................................................................................50
14.2
Abbreviations ........................................................................................50
14.3
Product options.....................................................................................50
14.3.1
RF silicon..........................................................................................50
14.3.2
Development tools............................................................................50
15 Application information ..............................................................................51
15.1
Crystal specification..............................................................................51
15.2
Bias reference resistor..........................................................................51
15.3
Internal digital supply de-coupling ........................................................51
15.4
PCB layout and de-coupling guidelines ................................................51
16 Reference circuits .......................................................................................53
16.1
Schematic .............................................................................................53
16.2
Layout ...................................................................................................54
16.3
Bill of Materials .....................................................................................55
17 Glossary .......................................................................................................56
Revision 1.0
Page 5 of 56
nRF2460 Product Specification
1
Introduction
The nRF2460 provides a solution for mono 16 bit 32 kHz LPCM audio streaming. The I2S interface is
supported for audio- input or output. The device features seamless interfacing of low cost A/D and D/A for
analog audio input and output. An external microcontroller controls the nRF2460 through a slave SPI or 2wire (I2C compatible) control interface.
1.1
Prerequisites
In order to fully understand this product specification, a good knowledge of electronic- and software
engineering is necessary.
1.2
Writing Conventions
This document follows a set of typographic rules to make the document consistent and easy to read. The
following writing conventions are used:
•
•
•
•
Pin names are written in Courier New bold.
Commands, bit state conditions, and register names are written in Courier New.
File names and User Interface components are written in regular bold.
Cross references are underlined and highlighted in blue.
Revision 1.0
Page 6 of 56
nRF2460 Product Specification
2
Product overview
The nRF2460 is a 4 Mbps single-chip RF transceiver that operates in the worldwide, 2.4 GHz license-free
ISM band. The nRF2460 is based on the ShockBurst™ link layer from Nordic Semiconductor.
2.1
Features
The device offers a wireless channel for seamless streaming of mono LPCM in parallel with a low, data
rate control channel. To enable this, the device has the following features:
•
•
•
Standard digital audio interface (I2S)
SPI or 2-wire slave control interfaces
Fully embedded Quality of Service engine handling all RF protocol and RF link tasks
As all processing related to audio I/O, RF protocol, and RF link management are embedded, the device
offers a transparent audio channel with a capacity of 512 kbits, with no true time processing needed. The
nRF2460 is used in conjunction with a microcontroller that only needs to handle low speed tasks through
the control interface (for example: volume up/down).
2.2
Block diagram
Figure 1. is a block schematic of a typical nRF2460 based system.
Figure 1. Typical audio application using nRF2460
In this system a microphone is connected to an nRF2460 by way of an ADC using standard audio format
(I2S). An nRF2460 pair transfers audio data from the source and presents it to a DAC on the receiving
side. Application-wise, the nRF2460 link will appear as a transparent channel (like a cable).
Initial configuration of nRF2460 is done by the microcontroller through an SPI or 2-wire control interface.
The microcontrollers on both sides are also able to monitor link status and turn the link on and off. When a
link is established, there is also a low data-rate reliable control link between the two microcontrollers.
Revision 1.0
Page 7 of 56
nRF2460 Product Specification
2.2.1
Pin assignments
Table 1. on page 10 shows the nRF2460 pin functions. Note that pin functions depend on the operational
mode of the device and the slave interface of choice.
Figure 2. Pin assignment nRF2460
Revision 1.0
Page 8 of 56
nRF2460 Product Specification
2.3
Pin functions
The nRF2460 can be set up as either an audio transmitter (ATX) or audio receiver (ARX), controlled by the
logic level of the MODE pin.
Serial slave interface is controlled by the logic level of the SSEL pin. See Table 1. on page 10.
Pin no.
1
2
3
4
5
6
71
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Revision 1.0
Pin name
Pin function
Description
SSEL
Digital input
Slave interface select 0: SPI, 1:2-wire
SMISO
Digital output
Slave SPI serial out (SSEL=0)
........... ....................... ...........................
Digital I/O
Slave 2-wire data (SSEL=1)
SSDA
SSCK
Digital input
Slave SPI clock (SSEL=0)
........... ....................... ...........................
SSCL
Digital I/O
Slave 2-wire clock (SSEL=1)
SCSN
Digital input
Slave SPI slave select (SSEL=0)
........... ....................... ...........................
SADR
Digital input
Address select 2-wire slave (SSEL=1)
VDD
Power
Power supply
SMOSI
Digital input
Slave serial in (SSEL=0)
...........................
Connect to ground (0V) (SSEL=1)
SYNDR
Digital input
Select SYNC direction 0: Output,
1: Input
SYNC
Digital output
No synchronization (default)
SYNDR=0
....................... ...........................
Digital input
Optional signal to synchronize 2 ARX
(SYNDR=1)
T1
Digital input
Reserved, connect to ground (0V)
CLK
Digital I/O
I2S bit clock (MODE=1)
....................... ...........................
Digital output
I2S bit clock (MODE=0)
WS
Digital I/O
I2S word clock (MODE=1)
....................... ...........................
Digital output
I2S word clock (MODE=0)
DATA
Digital input
I2S data signal (MODE=1)
....................... ...........................
Digital output
I2S data signal (MODE=0)
T2
Digital Input
Reserved, connect to ground(0V)
MCLK
Digital Output
256X sample rate clock to ADC or
DAC
DVDD
Regulator output
Internal voltage regulator output for
decoupling
VSS
Power
Ground (0V)
XC2
Analog output
Crystal connection for 16 MHz crystal
oscillator
XC1
Analog input
Crystal connection for 16 MHz crystal
oscillator
VDD
Power
Power supply
VDD_PA
Regulator output
Power supply output (+1.8V) for onchip RF Power amplifier
ANT1
RF
Differential antenna connection (TX
and RX)
Page 9 of 56
nRF2460 Product Specification
Pin no.
22
Pin name
ANT2
Pin function
RF
23
24
VSS_PA
IREF
Power
Analog output
25
26
VSS
MODE
Power
Digital Input
27
RESET
Digital Input
28
29
30
31
32
33
34
35
36
RESO
NC
NC
NC
VSS
VDD
VSS
NC
IRQ
Digital Output
Digital Output
Digital Input
Digital Output
Power
Power
Power
Digital Output
Digital Output
Description
Differential antenna connection (TX
and RX)
Ground (0V)
Device reference current output. To
be connected to reference resistor on
PCB
Ground (0V)
Mode 1:audio transmitter (ATX),
0:audio receiver (ARX)
Active high reset, connect to
ground(0V) if not used
Optional RESET pulse for ADC
Reserved, leave unconnected
Reserved, connect to ground(0V)
Reserved, leave unconnected
Ground (0V)
Power Supply
Ground (0V)
Reserved, leave unconnected
Interrupt request
1. Must be connected to ground (0V) if synchronization is not required.
Table 1. nRF2460 pin functions
2.3.1
Modes of operation
A wireless system streaming audio will have an asymmetrical load on the RF link as audio data is fed from
an audio source (as in a microphone) to a destination (as in loud speakers). From the destination back to
the audio source, only service- and control communication are needed.
The nRF2460 is used both on the audio source side (for example in a microphone) transmitting audio data,
and on the destination side (for example in a loudspeaker) receiving audio data.
Due to the asymmetry, nRF2460 has two operational modes set by the external pin MODE, depending on
whether it represents the transmitter or the receiver. The two modes show significant differences both in
internal and I/O functionality. The operational mode is selected by the logic level on the MODE pin:
MODE
0
1
Description
Audio destination
Audio source
Table 2. Operation modes set by MODE pin
The MODE pin is read during power-up and reset only.
In this context, the abbreviations ATX (for audio transmitter) and ARX (for audio receiver) refer to the
directional flow of the audio, while the nRF2460 radio transceiver always operates in half-duplex (bidirectional) mode.
2.3.2
Communication and data transfer principle
To differentiate between audio data and other control and status information, we have organized the
information about the data traffic between the ATX/ARX in this document, into two data channels.
Revision 1.0
Page 10 of 56
nRF2460 Product Specification
The audio channel is defined as the communication channel sourcing audio data from the ATX to the ARX.
The audio data is divided into two categories; real time data from the audio source and retransmitted audio
information.
If there is audio information lost, the ARX requests re-transmission of the lost packets. The real-time audio
bit rate is constant, whereas the amount of retransmitted audio varies across time.
The control channel is a two-way, low data rate channel superimposed on the audio stream.
Figure 3. nRF2460 communication channel concept
Revision 1.0
Page 11 of 56
nRF2460 Product Specification
2.3.3
Mode- and interface alternatives
A number of interfaces are available for the nRF2460 device. The available interfaces depend on the
nRF2460 mode of operation and the type of data to be transferred. Data is divided into two categories;
audio data (audio channel) and configuration/status data (control channel). Figure 4. illustrates the
available data interfaces for the various modes of operation. Interface options are illustrated by grey
circles, whilst functionality / operation modes are shown in white. Relevant configuration settings are
shown in the lines drawn between the circles.
Note: A choice about interface is made by a combination of pin and register settings. Refer to
Chapter 4 on page 21 for details.
Figure 4. nRF2460 functional modes and interface alternatives
Revision 1.0
Page 12 of 56
nRF2460 Product Specification
2.3.4
Audio transmitter (ATX)
When an nRF2460 is applied at the audio source side of the RF link, the MODE pin must be set high and
nRF2460 will become an audio transmitter. The block schematic of nRF2460 in ATX mode can be seen in
Figure 5.
Figure 5. nRF2460 ATX mode block diagram
2.3.4.1
I2S audio input
I2S is the audio interface to the nRF2460. The I2S interface consists of pins CLK, DATA and WS. This
interface supports a sampling rate of 32 kHz.
I2S may be used with an external stereo or mono ADC for analog audio sources. The nRF2460 offers a
sampling rate clock (fS) of 256 times the audio sampling rate. The sample rate clock is available on the
MCLK pin and may be used as system clock for the ADC. Only mono 32 kHz audio is streamed from ATX to
ARX. Data is in a 16-bit format.
Revision 1.0
Page 13 of 56
nRF2460 Product Specification
2.3.5
Audio Receiver (ARX)
When nRF2460 is put at the destination side of the RF link, MODE must be low and nRF2460 becomes
the audio receiver (ARX). A block schematic of nRF2460 in ARX mode can be seen in Figure 6. I2S is now
used for audio real time data output.
Figure 6. nRF2460 ARX mode block diagram
2.3.5.1
I2S audio output
The audio output (typically a DAC) is driven by the I2S output (pins CLK, DATA and WS). In audio receiver
mode, the MCLK pin provides a sampling rate clock (fS) of 256 times the audio sampling rate for an external
DAC.
Revision 1.0
Page 14 of 56
nRF2460 Product Specification
2.3.6
Blocks and functionality common to ATX and ARX
2.3.6.1
Serial control (slave) interfaces
Both ATX and ARX are controlled by an external MCU, and configuration and control data may be entered
through a 2-wire or SPI slave serial interface. The same interface is used for reading back status
information. The register map is identical to both interfaces, but only one of the interfaces (selected by the
SSEL pin) may be used in a given application:
SSEL
0
1
Description
SPI (pin functions SCSN, SSCK, SMISO, SMOSI)
2-wire (pins SADR, SSCL and SSDA)
Table 3. Serial interface set by SSEL pin
The SSEL pin is read during power-up and reset only.
Pin SADR is not part of a standard 2-wire interface, but selects one of two possible bus addresses for the
nRF2460.
2.3.6.2
Interrupt output
The nRF2460 can interrupt the external application through pin IRQ based on a number of sources. Once
IRQ has triggered the external MCU, interrupt status can be read through the serial slave interface.
2.3.6.3
XTAL oscillator
The crystal oscillator will provide a stable, reference frequency with low phase noise for the radio and
audio functions. See section 15.1 on page 51.
2.3.6.4
Radio transceiver
The RF transceiver part of the circuit is a member of the nRF family of low power highly integrated 2.4 GHz
ShockBurst™ transceivers. The transceiver interface is optimized for high speed streaming of up to 4
Mbps. Output power and some radio protocol parameters can be controlled by the user through the Quality
of Service (QoS) module.
2.3.6.5
Quality of Service (QoS) engine
The primary function of the QoS engine is to ensure robust communication between the ATX and the ARX
in an audio streaming application.
Various data streams with different properties are handled. The available bandwidth is shared among
audio data, service data and remote data.
Data integrity is ensured through a number of RF protocol features:
1.
2.
3.
Packets of data are organized in frames with each packet consisting of an RF address, payload
and CRC.
Packets that are lost or received with errors are handled by the error correction level of the QoS
engine; a two way, acknowledge protocol: When a packet is received by ARX, it is registered and
CRC is verified. After ARX has received a frame, it sends a packet back to ATX acknowledging
the packets successfully transferred. Packets lost or received with errors, are re-transmitted from
ATX in the next frame.
The information (audio data) is dispersed across the 2.4 GHz band by use of an adaptive
frequency hopping algorithm. This enables the nRF2460 link to cope with RF propagation
Revision 1.0
Page 15 of 56
nRF2460 Product Specification
challenges like reflections, multi-path fading and avoid heavily trafficked areas of the 2.4 GHz
band. Handling co-existence scenarios with contemporary RF systems such as Bluetooth, WLAN
as well as other nRF applications, is increasingly important.
The main function of the QoS is to constantly monitor the quality of the RF link.
The secondary function of the QoS module is to run a link initialization algorithm which manages initial
connect and re-connect if link is lost (ex: out of range) between paired nRF2460s.
2.3.6.6
Power-supply regulators
The nRF2460 has an internal, linear-regulated, power supply to all internal parts of the device. This makes
it very robust with respect to external voltage supply noise and isolates (audio) devices (in an application)
from any noise generated by the nRF2460.
2.3.6.7
Bias reference
The IREF pin sets up the bias reference for the nRF2460 by use of an external resistor. See section 15.2
on page 51.
Revision 1.0
Page 16 of 56
nRF2460 Product Specification
3
Operation overview
3.1
Power on / RESET sequence
When a power supply voltage is connected, nRF2460 performs a power-on reset. Reset is held until the
supply voltage has been above the minimum supply voltage for a few milliseconds. Pulling RESET pin high
also puts the device into reset.
After reset (power on or RESET high) is released, the device needs to be configured. An external
microcontroller must configure the nRF2460 ATX and ARX through the slave SPI or 2-wire serial interface.
The nRF2460 will then start a link initialization procedure based on the link configuration data. The value of
the MODE pin determines whether it will be in ATX or ARX mode.
It is important that all configuration data are set before the RF transceiver is enabled, by writing to the
TXMOD (for the ATX) or RXMOD (for the ARX) registers.
3.2
RF link initialization
The process of establishing a communication link between the ATX and the ARX is referred to as RF link
initialization. This involves the ATX systematically probing the frequency band in search for an active ARX
with the identical address. Once found, the ATX and ARX are synchronized before audio transmission
starts.
Figure 7. Link initialization algorithm
3.2.1
Idle state
The nRF2460 link initialization algorithm will be in idle state when a link is established. Once established,
the frequency hopping engine is initiated and synchronized.
3.2.2
Link-locate state
A special link-locate routine is initiated on both sides in order to (re-)establish a link, see Figure 7. During
initialization, nRF2460 uses the NLCH first positions of the frequency hopping table.
3.2.2.1
Link-locate state on ATX
The ATX tries to establish a link with ARX by iteratively sending short search packets on all available
channels until an acknowledge signal is received from the ARX. The ATX will send one packet on each
channel and wait for acknowledge long enough to secure that the ARX has time to respond. The
accumulated time used by the ATX while looping through all available channels, is defined as the ATXloop-time. After receiving an acknowledge packet from the ARX, the ATX will enter the synchronization
state as illlustrated in Figure 7. on page 17 . The dwell time for linking is approximately 600 s. The dwell
time is defined as the time duration for which the ATX is active at a given frequency before changing
frequency position.
Revision 1.0
Page 17 of 56
nRF2460 Product Specification
3.2.2.2
Link-locate state on ARX
The ARX tries to establish a link with the ATX by listening for incoming search packets on all available
channels. When a search packet is received, the ARX will proceed by sending one acknowledge packet to
confirm a feasible link. The ARX will listen for incoming search packets on each channel for a fixed time
longer than the ATX-loop-time. This guarantees at least one search packet to get through on each
available channel used by the ARX, as long as this channel is not being occupied by another radio device.
After sending the acknowledge packet, the ARX will enter the synchronization state. The dwell time for
ARX is approx. (NLCH+1)× 600 s.
3.2.3
Synchronization state
This state synchronizes the frequency hopping engine on ATX and ARX, ensuring that both units follow the
same hopping sequence. The initial start frequency is found in link-locate mode.
3.3
Audio channel
The input audio data can be one of the following common digital audio formats:
•
•
Left justified
I2S
In the ATX, the input audio stream format is converted to the nRF2460 RF protocol and transferred over
the air.
Upon reception in the ARX, the received data is validated and converted to the specified audio output
format and fed to the audio output interface.
3.3.1
Audio receiver clock rate generation
The ARX will lock MCLK to its XC1 clock input and derive CLK and WS by dividing the MCLK by the
appropriate divisor for the audio rate.
3.3.2
Audio transmitter clock rate generation
Maintaining equal data rates on both sides of the RF link is crucial in any RF system streaming true-time
data. This implies keeping the master clock frequency (MCLK) for the ADC on the transmitting side equal
to the clock frequency used to output audio samples from the RF device on the receiver side.
If these two clocks are not identical, the receiving end will either run out of samples for the DAC (ARX clock
frequency > ATX clock frequency) or overflow (ARX clock frequency < ATX clock frequency), skipping
samples.
This problem is solved in the nRF2460 device without the need for a tight tolerance crystal or extensive
digital filtering.
As long as the nRF2460 QoS engine is able to maintain the RF link, the ATX locks its master clock output
(MCLK) to the rate of the incoming audio stream. The MCLK signal on the ATX side is locked to the
reference (crystal) of the ARX side.
3.4
Control channel
A two-way, low bit rate, control and signaling channel runs in parallel with the audio stream. This control
channel is a part of the QoS overhead, meaning the difference between on- the- air data rate (4 Mbits) and
Revision 1.0
Page 18 of 56
nRF2460 Product Specification
the nominal audio data rate 0.5 Mbps. Hence the data channel rate cannot be traded for higher audio data
rate. The functionality of the control channel is illustrated in Figure 8.
Figure 8. nRF2460 control channel transfer principle
3.5
Register map
The nRF2460 control and status registers are listed in Table 4. on page 20. The registers may be accessed
by an external MCU through the slave interface (SPI or 2-wire). The registers are organized functionally
into six groups. All registers are present both in audio transmitter and audio receiver. Registers are
functional on both sides and the values should match on both sides of the link. DATA channel registers are
also functional on both sides, thus creating a bi-directional data channel between the two microcontrollers.
Revision 1.0
Page 19 of 56
nRF2460 Product Specification
Address HEX
ATX
0x01
0x02
0x5A
0x52
0x53
0x54
0x56
0x50
LINK status
0x03
LINK control
0x0C-0x31
0x32
0x33
0x34
0x35
0x36
0x0B
0x39-0x3D
Register
R/W
Initial value
Description
TXSTA
INTSTA
TXMOD
TXLAT
INTCF
I2SCNF_IN
TXPWR
TXRESO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x50
0x00
0x03
0x06
0x00
0x80
0x03
0x08
Table 8. on page 23
Table 22. on page 39
Table 8. on page 23
Table 19. on page 37
Table 22. on page 39
Table 8. on page 23
Table 20. on page 37
Table 23. on page 40
LNKSTA
R/W
0x00
Table 17. on page 36
CH[0:37]
BCHD
NBCH
NACH
R/W
R/W
R/W
R/W
0x0A
0x12
Table 15. on page 34
Table 16. on page 35
Table 16. on page 35
Table 16. on page 35
NLCH
LNKMOD
MDUR
ADDR[0:4]
R/W
R/W
R/W
R/W
LNKCSTATE
0x3E
DATA channel
DTXSTA
0x4E
RXCOUNT
0x5B
TXCOUNT
0x5C
0x5D-0x5f RXBUF[0:2]
0x65-0x67 TXBUF[0:2]
ARX
0x4A
RXMOD
0x44
I2SCNF_OUT
0x49
RXPWR
0x37
SYNCDL
Test
0x7E
TESTREG
0x7F
TESTCH
0x7D
REVBYT
R/W
0x26
0x26
0x00
0x00
0x98-38-A234-85
0x00
R
R
R/W
R
R/W
0x00
0x00
0x00
0x00
0x00
Table 25. on page 42
Table 13. on page 31
Table 13. on page 31
Table 13. on page 31
Table 13. on page 31
R/W
R/W
R/W
R/W
0x00
0x00
0x03
0x77
Table 9. on page 24
Table 9. on page 24
Table 20. on page 37
Table 21. on page 38
R/W
R/W
R
0x00
0x00
0x05
Table 27. on page 44
Table 27. on page 44
Revision byte
Table 4. nRF2460 register listing
Revision 1.0
Page 20 of 56
Table 16. on page 35
Table 17. on page 36
Table 18. on page 36
Table 14. on page 33
Table 25. on page 42
nRF2460 Product Specification
4
Digital I/O
This chapter describes the digital I/O pins, control registers and important interface timing of the nRF2460.
The digital I/O pins are divided into two groups:
•
•
4.1
Audio interface
Serial slave interfaces
Digital I/O behavior during RESET
During RESET, all digital pins are set as inputs to avoid driving conflicts with external devices. All pins will
maintain their respective directions until any of the configuration read routines described in section 3.1 on
page 17 are completed. The I/O pins are then set according to the new configuration data.
4.2
Audio interface
The audio interfaces consist of the I2S interface plus the MCLK pin.
Pin name
CLK
WS
DATA
MCLK
Function
bit clock
word sync clock
audio data
256 x CLK
Table 5. Serial audio port pins
4.2.1
I2S audio interface
The nRF2460 has a three-wire serial audio interface which can be configured to be compatible with
various serial audio formats. In ATX mode, the audio interface is in slave or master input mode. In ARX
mode, the audio interface is in master output mode. The audio interface consists of 4 pins in total, see
Table 5.
Figure 9. Serial audio formats I2S and left-justified
Revision 1.0
Page 21 of 56
nRF2460 Product Specification
Audio format
Left justified
I2S
I2SCNF[3:0] value
0xA
0x0
Table 6. Settings for two common serial audio formats
4.2.2
Audio interface functionality
The functionality and direction of the pins in the audio interfaces are listed in Table 7.
Pin number
Pin name
ARX direction
10
11
12
14
CLK
WS
DATA
MCLK
OUT
OUT
OUT
OUT
ATX direction
(I2SCNF_IN[7]=1)
OUT
OUT
IN
OUT
ATX direction
(I2SCNF_IN[7]=0)
IN
IN
IN
OUT
Table 7. nRF2460 operational modes and audio interface pin functions
Revision 1.0
Page 22 of 56
nRF2460 Product Specification
4.2.3
ATX audio interface control
The audio interfaces in ATX mode are controlled by the registers listed in Table 8. on page 23.
Address
HEX
0x01
Register
R/W
TXSTA
R/W
Description
ATX audio input rate register
Interpretation
Reserved. Must be “010”
Value
Description
00
Reserved
01
Reserved
10
32 kHz
11
Reserved
2:0
Reserved, MBZ
ATX modes of operation
7
RF transceiver enable
6
Audio transmitter power down
5:2
Reserved, MBZ
1:0
MCLK output control
00
MCLK off (logic 0)
01
Reserved
10
Reserved
11
Output 256 × 32 kHz
ATX I2S interface configuration. See Table 6. on page 22
7
I2S audio in clock mode
0
Slave mode, WS, CLK, DATA are
input (needs to be coherent with
MCLK)
1
Master mode, WS, CLK are
output, DATA is input
6:5
Reserved, MBZ
4
Mono sample location
0
Use left channel samples
1
Use right channel samples
3
WS polarity
0
WS=0 for left sample
1
WS=1 for left sample
2
Reserved, MBZ
1
WS to MSB delay
0
1 clock cycle
1
0 clock cycle
0
Reserved, MBZ
Bit
7:5
4:3
0x5A
TXMOD
R/W
0x54
I2SCNF_IN
R/W
Table 8. ATX audio interface control registers
The nRF2460 offers a 256 x clock output on pin MCLK. Clock frequency is set in register TXMOD [1:0]. This
clock shall be used as master clock to the device that drives the I2S data input on the ATX side.
Revision 1.0
Page 23 of 56
nRF2460 Product Specification
4.2.4
ARX audio interface control
In ARX mode the audio interfaces are controlled by registers RXMOD and I2SCNF_OUT listed below.
Address
HEX
0x4A
0x44
Register
R/W
Description
RXMOD
R/W
I2SCNF_OUT
R/W
ARX modes of operation
Bit
Interpretation
7
Audio receiver power down
6
Reserved, MBZ
5
RF transceiver enable
4:0
Reserved, MBZ
ARX I2S interface configuration for audio output. See Table 6. on
page 22
Bit
Interpretation
7
Reserved, MBZ
6
Mute sound output
5:4
Reserved, MBZ
3
WS polarity
0
WS=0 for left sample
1
WS=1 for left sample
2
Data to Bit Clock relation (data valid at clock
edge)
0
Rising edge
1
Falling edge
1
WS to MSB delay
0
1 clock cycle
1
0 clock cycle
0
Reserved, MBZ
Table 9. ARX audio interface control registers
The Mute bit holds the last audio sample and holds it until the Mute bit is cleared again. Then a simple
three-sample interpolation scheme is applied between the last sample value and the first unmuted sample
value. The same mute behavior is also applied to audio packet loss. Mute on and off is synchronized to the
next audio packet boundary.
Revision 1.0
Page 24 of 56
nRF2460 Product Specification
4.2.5
I2S audio interface timing
4.2.5.1
I2S input (ATX) timing
The I2S input protocol may be configured in register I2SCNF_IN to handle various I2S formats. This
section describes the detailed bit-, clock- and word timing requirements for audio slave and audio master
mode (as set by I2SCNF_IN [7]).
Figure 10. I2S input timing in audio slave mode (I2SCNF_IN[7]=0)
Figure 11. I2S input timing in audio master mode (I2SCNF_IN[7]=1)
Revision 1.0
Page 25 of 56
nRF2460 Product Specification
4.2.5.2
I2S output (ARX) timing
The I2S output protocol is configurable in register I2SCNF_OUT and is compatible with most I2S DACs and
CODECs.
Figure 12. I2S output timing
Refer to Table 28. on page 46 for values.
4.3
Control interfaces
Both ATX and ARX are setup with SPI or 2-wire slave interfaces.
4.3.1
Slave interface and pin configuration
One of two interfaces can be chosen (set by input pin SSEL):
nRF2460 serial slave interface
pins
Pin number
Name
1
SSEL
2
SMISO/SSDA
3
SSCK/SSCL
4
SCSN/SADR
6
SMOSI
36
IRQ
Device control: SPI mode
(SSEL=0)
Function
Direction
SSEL
IN
SMISO
OUT
SSCK
IN
SCSN
IN
SMOSI
IN
IRQ
OUT
Device control: 2-wire mode
(SSEL=1)
Function
Direction
SSEL
IN
SSDA
IN/OUT
SSCL
IN/OUT
SADR
IN
Ground(0V)
IRQ
OUT
Table 10. Control pins functionality
4.3.2
SPI slave interface
The first byte of the SPI transaction specifies the address for the register and whether it has a read or a
write access. The seven least significant bits in the first byte are the nRF2460 register address, while the
most significant bit is the read/write indicator (read=1, write=0), see Table 11.
B7
R/W
B6
B5
B4
B3
Register address
B2
Table 11. SPI command byte encoding
Revision 1.0
Page 26 of 56
B1
B0
nRF2460 Product Specification
4.3.2.1
Write transaction
The next byte on SMOSI will be put into the register with the address specified in the first byte. Writing
additional bytes will increment the register address automatically.
4.3.2.2
Read transaction
The next byte on SMISO will be the contents of the register with the address as specified in the first byte.
Reading more bytes will increment the register address automatically.
4.3.2.3
SCSN active low
Consecutive accesses with SCSN low will auto-increment the address.
4.3.3
2-wire slave interface
This interface is similar to what is found on serial memories and data converter devices. The seven-bit
device address of nRF2460 is ‘a101001’, where ‘a’ is the logic level of the SADR input pin (read during
power-up and reset only).
Each 2-wire transaction is started with the “Start condition” followed by the first byte containing the sevenbit-long device address and one read/write bit. This byte is hereafter referred to as the “address/read
command byte” or the “address/write command byte” depending on the state of the read/write bit (read=1,
write=0).
The second byte contains the register address, specifying the register to be accessed. This address will be
written into the nRF2460, and it is therefore necessary that the first byte after the first start condition is an
address/write command. Further actions on the 2-wire interface depend on whether the access is a read or
write access. The 2-wire command byte is illustrated in Table 12.
B7
a
B6
1
B5
0
B4
1
B3
0
B2
0
B1
1
B0
R/W
Table 12. 2-wire command byte encoding
4.3.3.1
2-wire write access
Figure 13. illustrates a simple write operation, where one byte is written to the nRF2460.
Figure 13. 2-wire write operation example
A write access is composed by a start condition, an address/write command byte, a register address byte
and the corresponding data byte. Each byte will be acknowledged by the 2-wire slave by pulling the data
Revision 1.0
Page 27 of 56
nRF2460 Product Specification
line (SDA) low. To stop the write access, a stop condition is applied on the 2-wire interface. See Figure 15.
for an example. Consecutive write access is performed by postponing the stop condition.
4.3.3.2
2-wire read access
Figure 14. illustrates a simple read operation, where one byte is read back from the nRF2460.
Figure 14. 2-wire read operation
A read access is composed by a start condition, an address/write command byte and a register address
byte. These two bytes are acknowledged by the 2-wire slave. This scenario is followed by a repeated start
condition and an address/read control byte. This byte is also acknowledged by the 2-wire slave. After the
acknowledge bit has been sent from the 2-wire slave, the register value corresponding to the register
address byte is supplied by the 2-wire slave. This byte must be acknowledged by the 2-wire master if
consecutive register read operations are intended. The read access is stopped by not acknowledging the
last byte read, followed by a stop condition. See Figure 15.
Figure 15. 2-wire waveform example
Revision 1.0
Page 28 of 56
nRF2460 Product Specification
4.3.4
Control interface timing
4.3.4.1
2-wire slave timing
The interface supports data transfer rates of 100 kHz, 400 kHz and 1 MHz.
Figure 16. 2-wire slave timing diagram
Refer to Table 28. on page 46 for values.
Revision 1.0
Page 29 of 56
nRF2460 Product Specification
4.3.4.2
SPI slave timing
Normal SPI slave clock frequency is up to 8 MHz. Note the minimum pause interval tSRD between writing/
reading of a byte.
Figure 17. SPI slave timing diagram
TSSCK: SSCK cycle time
tdSSCK: time from SCSN active to first SSCK pulse
tdSSPI: delay from negative edge SSCK to new SMISO output data
tsuSSPI: SMOSI setup time to positive edge SSCK
thdSSPI: SMOSI hold time to positive edge SSCK
tSRD: minimum pause between each byte read from or written to slave SPI
tSREADY: time from SSCK negative edge to SCSN rising edge
Refer to Table 28. on page 46 for values.
Revision 1.0
Page 30 of 56
nRF2460 Product Specification
4.4
Data channel
The nRF2460 data channel is implemented by the data channel registers TXCOUNT, TXBUF, RXCOUNT,
RXBUF and DTXSTA. The MCU on the ATX side can control its set of the registers, and the MCU on the
ARX side can control its set of the registers.
Transfer can occur in both directions, and at the same time.
Address
HEX
0x5C
Register
R/W
Description
TXCOUNT
R/W
0x5B
RXCOUNT
R
0x4E
DTXSTA
R
0x5D-0x5F
RXBUF[0:2]
R
0x65-0x67
TXBUF[0:2]
R/W
Number of bytes to be transmitted (max 3), from
ATX to ARX or from ARX to ATX. Writing to this
register will start transmission of the bytes in
TXBUF. The TXCOUNT register in ATX and ARX
respectively may be written at the same time.
Number of bytes received by ATX or ARX
respectively.
RXCOUNT received bytes are now ready to be read
from the RXBUF registers. An interrupt (flag
INTSTA[3]) may be delivered upon successful
reception of RXCOUNT bytes.
Data transfer status register.
An interrupt (flag INTSTA[4]) may be delivered
upon successful completion of the TXCOUNT
command. Returned values are :
0 : idle, last transfer was successful
1 : busy with on-going transfer
2 : timeout error, last transfer was unsuccessful
Received bytes (maximum 3), local buffers in ATX
and ARX respectively.
Bytes to be transferred (maximum 3) from ATX to
ARX or from ARX to ATX. Local buffers in ATX
and ARX respectively.
Note: Data transferred by TXCOUNT may be lost even though transfer finished is received. Data
transfer should be hand-shaken by application firmware if data transfer is critical.
Table 13. Data channel registers
Revision 1.0
Page 31 of 56
nRF2460 Product Specification
4.4.1
Typical transfer of data from ATX to ARX
The ATX MCU must:
•
•
Write up to three data bytes into TXBUF [0:2]
Write value 3 to TXCOUNT (this starts the transfer)
If enabled (INTCF[4]), an ATX interrupt will come when the transfer of the three bytes is finished, or the
DTXSTA register may be polled. DTXSTA will be 1 until the transfer is finished. Another three bytes may be
sent in the same way.
The ARX MCU may:
•
•
•
4.4.2
Enable data receive interrupt, INTCF [3]=1
If enabled, an ARX interrupt will come when three bytes are received, or alternatively the INTSTA [3]
bit may be polled.
Read the three bytes from RXBUF [0:2]
Typical transfer of data from ARX to ATX
The ARX MCU must:
•
•
Write up to three data bytes into TXBUF [0:2]
Write value three to TXCOUNT (this starts the transfer)
If enabled (INTCF [4]), an ARX interrupt will come when the transfer of the three bytes is finished, or the
DTXSTA register may be polled. DTXSTA will be 1 until the transfer is finished.
Another three bytes may be sent in the same way.
The ATX MCU may:
•
•
Enable data receive interrupt, INTCF [3]=1. If enabled, an ATX interrupt will come when three bytes
are received, or alternatively the INTCF [3] bit may be polled.
Read the three bytes from RXBUF [0:2]
Revision 1.0
Page 32 of 56
nRF2460 Product Specification
5
Quality of Service (QoS) and RF protocol
The purpose of the QoS-engine is to maintain audio quality across time during normal operation. This
involves:
•
•
•
•
Ensuring that corrupt or lost information sent from the ATX is automatically detected and
retransmitted to the ARX
Monitoring and avoiding channels used by other 2.4 GHz equipment or which have poor radio
propagation properties (for example fading effects)
Reducing the audible effect of corrupt data when retransmission fails within the latency time frame
Establishing a new link in case of communication loss
The control channel is used to monitor radio link status information.
It should be noted that at some point, the QoS-engine is unable to maintain a flawless audio link. This may
be the result of stretched range, excessive interference noise or both.
The RF-protocol is an integral part of the QoS-engine and is therefore not subject to user modification.
5.1
Link establishment
The procedure for establishing a link is fully managed on-chip.
5.2
RF protocol
The RF-protocol is controlled on-chip. The only parameter configurable by the application is the address.
This enables separate nRF2460 devices to be identified and accessed independently in the same physical
area. The RF protocol address length is five bytes and the address bytes are set in registers ADDR [0:4],
listed in Table 14.
Address Hex
0x39
0x3A
0x3B
0x3C
0x3D
Register
ADDR[0]
ADDR[1]
ADDR[2]
ADDR[3]
ADDR[4]
R/W
R/W
R/W
R/W
R/W
R/W
Description
Address byte #0 (LSB)
Address byte #1
Address byte #2
Address byte #3
Address byte #4 (MSB)
Table 14. RF protocol address
The contents of ADDR [0:4] are sent to the ARX when 0x01 is written to LNKCSTATE. To enable the new
ADDR [0:4] a force reconfiguration must be performed by writing to LNKMOD [4], this will make the ATX and
ARX re-link with the new address.
5.3
Adaptive Frequency Hopping (AFH)
Adaptive Frequency Hopping is an integral part of the QoS-engine functionality. The audio data is split into
packets which are transmitted at different frequencies known by the transmitter and receiver. The
frequencies used change across time as active noise sources in the frequency band appear and
disappear. AFH also enables the nRF2460 link to handle challenges such as signal cancellation due to
multi-path fading effects. The frequencies used by the AFH-algorithm are specified in up to 38 frequency
registers shown in Table 15. on page 34. The contents of CH0-37 cannot be sent from the ATX to the ARX.
Register values of CH0-37 must be configured locally by the MCU.
Revision 1.0
Page 33 of 56
nRF2460 Product Specification
Address Hex
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
Register
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
CH16
CH17
CH18
CH19
CH20
CH21
CH22
CH23
CH24
CH25
CH26
CH27
CH28
CH29
CH30
CH31
CH32
CH33
CH34
CH35
CH36
CH37
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0x06
0x1C
0x34
0x4C
0x18
0x30
0x48
0x14
0x2C
0x44
0x10
0x28
0x40
0x0C
0x24
0x3C
0x08
0x20
0x38
0x04
0x1E
0x36
0x4E
0x1A
0x32
0x4A
0x16
0x2E
0x46
0x12
0x2A
0x42
0x0E
0x26
0x3E
0x0A
0x22
0x3A
Description
Frequency positions for the
hopping sequence. The
frequency position frequency
is equal to the position
number multiplied by 1 MHz
relative to 2400 MHz.
Example: To define a
frequency hopping scheme
starting at f=2420 MHz, and
then hopping to f=2440 MHz,
the following values must be
set: CH0=0x14, CH1=0x28.
Table 15. Frequency hopping table registers
Revision 1.0
Page 34 of 56
nRF2460 Product Specification
5.3.1
Adapting to the RF environment
In an environment without other 2.4 GHz applications or noise sources, the nRF2460 will use all the
frequency positions listed in Table 15. on page 34. In the presence of an active RF system, occasional
packet collisions are likely, resulting in RF packets being lost.
When an operating frequency resulting in unacceptable packet loss is detected, the ATX may remove it
from the list of frequency positions used by the AFH algorithm. The corresponding list in the ARX is
synchronized by use of the control channel, and as a consequence this method cannot be applied during
link initialization.
Frequency positions removed from the frequency hopping sequence are added to a FIFO list of
frequencies temporarily banned for use by the AFH-algorithm. The length of the list of banned frequencies
is configurable (see Table 16. ) The maximum number of banned channels is 18. A banned channel will
remain in the list of banned frequencies until it is pushed out by a new candidate or as defined by BCHD
register.
Note: The list of hopping positions does not need to contain solely non-overlapping channels in
order to achieve optimal effect. Generally, the frequency positions should be distributed over
the available frequency band.
Address
Hex
0x32
Register
R/W
Description
BCHD
R/W
0x33
NBCH
R/W
0x34
NACH
R/W
0x35
NLCH
R/W
Banned channel duration. The duration of
transmission ban, in number of frequency hops. The
time before a banned channel is earliest released
from the banned list, is (BCHD+1)×NBCH×3.0 ms
Number of banned channels. The number of
frequency positions subject to ban at any time.
Maximum register value is 18.
Number of frequency positions used in normal audio
streaming mode. The frequency locations used are
the first NACH-locations of Table 15. on page 34.
Number of link channels used in link mode. The
frequency locations used are the first NLCHlocations of Table 15. on page 34.
Table 16. Frequency hopping configuration registers
To minimize linking time, the same basic frequency hopping scheme must be set on the ATX and ARX
side.
Revision 1.0
Page 35 of 56
nRF2460 Product Specification
5.4
Link registers
The link functional status is reported in register LNKSTA. Registers LNKSTA and LNKMOD are listed in Table
17.
Address
Hex
0x03
0x36
Register
R/W
Description
LNKSTA
R/W
LNKMOD
R/W
Link status register
Bit
Interpretation
7:1
Reserved, MBZ
0
1:Link established
Link status register
Bit
Interpretation
7
Reserved, MBZ
6
1: ATX and ARX reset to initial (reset) register
contents if no counterpart is found on the next link
initialization.
5
Reserved, MBZ
4
1: Force reconfiguration with new configuration data
3
Reserved, MBZ
2
1: Disables adaptive frequency hopping
1
Reserved, MBZ
0
1: Enables use of Mute duration feature, see MDUR
register
Table 17. Link status/mode registers
5.4.1
Mute behavior
There is an option to set the minimum mute interval length, to avoid fast toggling between audio and muted
audio during audio loss.
Address
Hex
0x0B
Register
R/W
Description
MDUR
R/W
Mute duration feature. After muting, the ARX must
wait MDUR × 24 consecutive audio packets without
errors before un-muting. This feature is enabled by
LNKMOD bit 0.
Table 18. Mute duration register
Revision 1.0
Page 36 of 56
nRF2460 Product Specification
5.4.2
RF link latency
Link robustness may be traded with link latency. In systems where latency is not critical, the high latency
option should be used. Latency is set in the TXLAT register as shown in Table 20.
Address
Hex
0x52
Register
R/W
Description
TXLAT1
R/W
ATX to ARX latency in milliseconds
Value
Description Latency
4
Medium
20 ms
6
High
26 ms
1. Latency values listed are without ADC/DAC delay digital in/out
Table 19. TXLAT register
5.5
RF output power
The only configurable parameter in the RF subsystem is the RF transmitter output power. ATX output
power is set in register TXPWR. ARX output power is set in register RXPWR.
Address
Hex
0x56
0x49
Register
R/W
TXPWR
R/W
RXPWR
R/W
Description
ATX output power
Value
Interpretation
0
-20 dBm
1
-10 dBm
2
-5 dBm
3
0 dBm
ARX output power
Value
Interpretation
0
-20 dBm
1
-10 dBm
2
-5 dBm
3
0 dBm
Table 20. TXPWR and RXPWR registers
Revision 1.0
Page 37 of 56
nRF2460 Product Specification
5.6
Sync delay signal
The nRF2460 supports synchronization of two ARX placed on the same PCB. The synchronization is
achieved by setting the logic level of the SYNDR pin and by connecting the SYNC pins together. A typical
setup is shown below.
Figure 18. Typical connection for synchronizing two ARX
For best performance the two ARX should be set up with different RF addresses and hopping tables.
The SYNCDL register can be used to change the timing of the SYNC signal. The default value is 119
(decimal) which gives approximately zero delay. Values below 119 give negative delay, while values
higher than 119 give positive delay, in steps of approximately 16 s.
SYNCDL (decimal)
119
255
0
SYNC signal delay
0
2.2 ms
-1.9 ms
Comment
Default value
Maximum positive delay
Maximum negative delay
Table 21. Configurable sync delay between ARX pairs
The SYNCDL value must be set before RXMOD[5] is set.
Revision 1.0
Page 38 of 56
nRF2460 Product Specification
6
Interrupts
The nRF2460 can be configured to deliver interrupts to any external system connected to pin IRQ.
Interrupt sources are defined by register INTCF. Interrupt status flags are available in register INTSTA
(0x02). After interrupt initiation, the IRQ will stay active (logic 0 with INTCF [7] = 0, logic 1 with INTCF [7] =
1) until a logic 1 is written to the corresponding interrupt flag in the INTSTA register. All interrupt flags may
be cleared by writing 0x7F to INTSTA.
Address Hex
0x02
Register
INTSTA
R/W
R/W
0x53
INTCF
R/W
Description
Interrupt status register. Register
contents and interrupt are cleared upon
writing a “1” to the respective bit. See
register INTCF for interrupt enabling.
Bit
Interpretation
7
Reserved MBZ
6
Link broken status flag
5
Reserved, MBZ
4
Remote transfer done status
flag, set upon completion of
a TXCOUNT or
LNKCSTATE command
3
Data received, RXCOUNT
bytes available in
RXBUF[0:2]
2
Reserved, MBZ
1
Reserved, MBZ
0
Reserved, MBZ
Interrupt configuration. Select events
that can generate interrupt on the IRQ
pin.
Bit
Interpretation
7
IRQ pin polarity, 1 is active
high, 0 is active low
6
Enable link broken interrupt
5
Reserved, MBZ
4
Enable remote transfer done
interrupt
3
Enable data received
interrupt
2
Reserved, MBZ
1
Reserved, MBZ
0
Reserved, MBZ
Table 22. Registers INTCF and INTSTA
Revision 1.0
Page 39 of 56
nRF2460 Product Specification
7
RESET output
An nRF2460 in ATX mode has a configurable RESET output pin RESO, which may be used to provide a
RESET pulse to peripherals such as an ADC. The RESET pulse is executed as a part of the configuration
routine performed immediately after power-on-reset and after device reconfiguration.
RESO pin behavior is controlled by register TXRESO for the ATX. This function is not available for the ARX.
Address Hex
0x50
Register
TXRESO
R/W
Description
R/W Enabling of optional RESET pulse output
from ATX
Bit
Interpretation
7:4 Reserved, MBZ
3:1 0: no RESET output
1,2,3: Reserved, MBZ
4: RESET output on pin 28 RESO
5,6,7: Reserved, MBZ
0 ATX RESET output polarity
0: active low
1: active high
Reset pulse duration is
approximately 285 s.
Table 23. TXRESO register
Revision 1.0
Page 40 of 56
nRF2460 Product Specification
8
Power-down control
8.1
Activation of power-down mode
Power-down mode can only be activated by the external microcontroller. The ATX power-down mode is
initiated by setting register TXMOD [6]=1. The ARX power-down mode is initiated by setting register RXMOD
[7]=1. Register TXMOD is described in Table 8. on page 23 and register RXMOD is described in Table 9. on
page 24.
8.2
Wake up from power down
The device will wake you up again upon a negative transition on pin 2 (SSDA) or pin 4 (SCSN), depending
on which slave interface is selected. See Table 24.
SSEL
0
1
Description
SPI slave interface
selected
2-wire interface selected
Wake up pin
Pin 4, SCSN
Pin 2, SSDA
Table 24. Wake-up pin selection
All register content will be kept during power down.
8.3
Power down current
The power down current depends on the direction of the audio interface pins, so to achieve minimum
power down current, the pins which are configured as inputs, must not be left floating by the external audio
circuitry. Whether the pins are left floating or not depends on how the device is configured.
After power on, all audio interface pins are default configured as input pins and will remain so until an audio
link is established.
When in audio-streaming mode, the direction of the audio interface pins is as shown in Table 7. on page
22.
Revision 1.0
Page 41 of 56
nRF2460 Product Specification
9
Register update over the control channel
The LNKCSTATE register can be used by the ATX MCU to update the ARX link control registers through
the control channel. Writing to LNKCSTATE from the ARX MCU is illegal, and LNKCSTATE must not be
written to, if it is not idle.
When LNKCSTATE is set to 0x01, the ATX will send all the link control registers, except the CH-registers, to
the ARX. LNKCSTATE is then automatically reset to 0x00 after all register values have been successfully
transferred. When LNKCSTATE reads 0x01, the ATX is busy sending the register values to the ARX. When
LNKCSTATE reads 0x02, that means the last transfer was unsuccessful. A value of 0x02 may indicate a
radio link problem.
Address
Hex
0x3E
Register
R/W
LNKCSTATE
R/W
Description
Controls when to send ATX side link control registers
over the data link to the ARX.
Status values are:
0 : idle, last transfer was successful
1 : busy, registers may not be accessed
2 : idle, last transfer was unsuccessful
When idle, data may be written to the link control
registers.
Setting LNKCSTATE = 1 triggers the ATX to send link
control register values to the ARX. LNKCSTATE will be
reset to 0 by the ATX upon successful transfer to the
ARX. The external MCU should poll this register before
accessing any link control registers.
Table 25. Register update registers
Revision 1.0
Page 42 of 56
nRF2460 Product Specification
9.1
Register update and device relink
Some register updates can only be changed while the RF transceiver is disabled, or require a force
reconfiguration, if changed.
The ATX and ARX will always be reconfigured after a link has been established. They can also be
reconfigured by forcing a re-link if any of the following registers change value. This can be done by setting
“Force reconfiguration” by LNKMOD [4] = 1.
Register
Register name
category
ATX registers
TXLAT
TXSTA
TXMOD[1:0]
I2SCNF_IN
LINK registers
ADDR0,
ADDR1,
ADDR2,
ADDR3,
ADDR4,
NBCH,NACH,
NLCH,BCHD
ARX registers I2SCNF_OUT
[3:1]
Test registers
TESTREG
TESTCH
Comment
Must be set locally, with identical values in ATX and
ARX
Can be set locally, with identical values in ATX and
ARX; or ATX values may be transferred to ARX by
use of LNKCSTATE
Must be set locally, with identical values in ATX and
ARX
Must be set locally
Table 26. Registers requiring device re-configuration, if changed
Revision 1.0
Page 43 of 56
nRF2460 Product Specification
10
Test mode
An nRF2460 test mode is initiated by writing to test registers TESTREG and TESTCH, followed by setting bit
4 of the LNKMOD register. This will force the device to restart in test mode according to the TESTREG and
TESTCH register settings.
The nRF2460 will remain in test mode until it is reset. Test mode can only be aborted by the use of reset.
Moreover, test mode changes can only be performed upon device reset. This applies to both the ATX and
ARX.
The test registers can be accessed through the SPI- or 2-wire slave interface.
Address Hex
0x7E
Register
TESTREG
R/W
W
0x7F
TESTCH
W
Description
Test mode register:
Code 1: 0110 0011 – Single channel test.
Code 2: 0111 0011 – Channel sweep test.
Sweeps all channels from frequencies from
2400 MHz to 2480 MHz in steps of 1 MHz.
Bit
Interpretation
7
1: TX, 0: RX
Initiates the mode
described in TESTREG in
RX/TX mode.
6:0
Channel number when
TESTREG is set to Code
1 (single channel),
number is in 1 MHz step
relative to 2400 MHz.
Table 27. Test mode registers
Output power in test mode is always 0dBm, and any other setting in TXPWR and RXPWR registers is ignored
in test mode.
To enable test mode, the “Force reconfiguration” bit in LNKMOD [4] must be set after writing TESTREG and
TESTCH.
Revision 1.0
Page 44 of 56
nRF2460 Product Specification
11
Electrical specifications
Symbol
VDD
TEMP
VIH
VIL
VOH
VOL
IPD
fOP
'f
RGFSK
BWMOD
fXTAL
Cload
'fXTAL
PRF 0dBm
PRF -5dBm
PRF -10
dBm
PRF-20dBm
PRFC
PRFCR
PBW
RXSENS
RXMAX
IATX 0dBm
IATXmax
IATX -5dMm
Revision 1.0
Parameter (condition)
Notes
Operating conditions
Supply voltage
Operating temperature
Digital input pins
HIGH level input voltage
LOW level input voltage
Digital output pins
HIGH level output voltage
(IOH= - 0.5mA)
LOW level output voltage
(IOL=0.5mA)
General electrical specification
Supply current in power down
mode
General RF conditions
1
Operating frequency
Frequency deviation
GFSK data rate
Modulation bandwidth
2
Crystal frequency
2
Crystal load capacitance
2
Crystal frequency tolerance
RF transmit mode
3
Maximum output power
(TXPWR=3)
3
Maximum output power
(TXPWR=2)
3
Maximum output power
(TXPWR=1)
3
Maximum output power
(TXPWR=0)
RF power control range
RF power control range
resolution
20 dB bandwidth for
modulated carrier
RF receive mode
Sensitivity at 0.1% BER
Maximum received signal
ATX current consumption
4
Average supply current in
audio streaming mode @
5
0dBm output power
5
Peak supply current in audio
streaming mode
Average supply current at
-5dBm output power
Min.
Nom.
Max.
Units
2.2
0
3.0
27
3.3
60
V
ºC
0.7×VDD
VSS
VDD
0.3×VDD
V
VDD - 0.3
VDD
V
VSS
0.3
V
A
5
2400
2404 to 2478
+/- 640
4000
2521
16
+/-50
MHz
kHz
kbps
MHz
MHz
pF
ppm
0
3
dBm
-5
0
dBm
-10
-5
dBm
-20
-12
dBm
+/-3
dB
dB
4000
kHz
4
8
16
16
12
20
2500
-80
dBm
dBm
13
mA
34
mA
12
mA
0
Page 45 of 56
nRF2460 Product Specification
Symbol
IATX -10dMm
Parameter (condition)
Average supply current at
-10dBm output power
IATX-20dBm
Average supply current at
-20dBm output power
IARX link
IARX au
TI2S
TsI2S
ThI2S
TdI2S
'fMCLK
JRMS
TSSCK
tsuSSPI
thdSSPI
tdSSPI
tdSSCK
tSRD
tSREADY
TSSCL
tSW2 dsu
tSW2 dhd
tSW2 od
1.
2.
3.
4.
5.
ARX current consumption
Average supply current in link
mode
Average supply current in
audio streaming mode
Notes
Min.
5
Nom.
12
Units
mA
12
mA
33
mA
32
mA
I2S interface timing (See Figure 10. on page 25, Figure 11. on page 25 and Figure 12. on
page 26)
I2S clock period
150
ns
DATA and WS (input) setup
20
ns
time to CLK
DATA and WS (input) hold time
20
ns
from CLK
DATA and WS (output) delay
40
ns
from CLK
MCLK (256 x 32 kHz)
Locking range versus nominal
-500
+500
ppm
MCLK frequency
RMS jitter
250
310
ps
0 to 25 kHz
Slave SPI interface timing (See Figure 17. on page 30)
SSCK clock period
124
ns
SMOSI setup time to SSCK
10
ns
SMOSI hold time from SSCK
10
SMISO delay from SSCK
55
ns
SCSN setup time to SSCK
500
s
SPI slave ready
500
s
SCSN hold time to SSCK
500
s
Slave 2-wire interface timing (See Figure 16. on page 29)
2-wire clock period
1000
ns
SSDA setup time to SSCL
50
ns
SSDA hold time from SSCL
65
ns
SSDA 1 ->0 delay from SSCL
170
ns
Usable band is determined by local regulations.
For further details on crystal specifications, see section 15.1 on page 51.
Antenna load impedance=100:j175:, see chapter 15 on page 51.
With a good quality link and little retransmission
CMCLK| 8pF
Table 28. nRF2460 electrical specifications
Revision 1.0
Max.
Page 46 of 56
nRF2460 Product Specification
12
Absolute maximum ratings
Parameter
Supply voltages
VDD
VSS
Input voltage
VI
VO
Temperatures
Operating
temperature
Storage
temperature
Minimum
Maximum
Unit
-0.3
+3.6
0
V
V
-0.3
-0.3
VDD+0.3
VDD+0.3
V
V
0
60
qC
-40
+125
qC
Note: Stress exceeding one or more of the limiting values may cause permanent damage to the
device.
Attention!
Observe precaution for handling
Electrostatic Sensitive Device.
HBM (Human Body Model): Class 1A
Revision 1.0
Page 47 of 56
nRF2460 Product Specification
13
Mechanical specifications
The nRF2460 is packaged in a 36 pin 6 by 6 QFN.
Figure 19. QFN36 pin 6x6
Revision 1.0
Page 48 of 56
nRF2460 Product Specification
Package
QFN36
(6x6mm)
Min
Nom
Max
A
A1
A2
0.8
0
-
A3
b
0.203 0.2
REF
0.85 0.035 0.65 0.203 0.25
REF
0.9 0.05 0.67 0.203 0.3
REF
D/E
e
6
0.5
BSC BSC
6
0.5
BSC BSC
6
0.5
BSC BSC
Table 29. QFN36 dimensions in mm
Revision 1.0
Page 49 of 56
4.47
aaa/
bbb/
L
ddd/
eee
0.35 0.1
4.57
0.4
0.1
0.08
4.67
0.45
0.1
0.08
J/K
ccc
0.08
nRF2460 Product Specification
14
Ordering information
14.1
Package marking
n
2
Y
R
4
Y
F
6
W
0
W
B
X
L
L
Figure 20. nRF2460 package marking layout
14.2
Abbreviations
Abbreviation
Definition
2460
Product number
B
Build code, that is, unique code for production sites, package
type and test platform. Variable.
X
“X” grade, that is, Engineering Samples (optional)
YY
Two-digit year number
WW
Two-digit week number
LL
Two-letter wafer-lot number code
Table 30. Abbreviations
14.3
Product options
14.3.1
RF silicon
Ordering code
nRF2460-R
nRF2460-T
Package
Container
6x6mm 36-pin QFN
6x6mm 36-pin QFN
Tape-and-reel
Tray
MOQ1 MSL level2
2500
2
490
2
1. Minimum Order Quantity
2. The Moisture Sensitivity Level rating according to the JEDEC industry standard classification
Table 31. nRF2460 silicon options
14.3.2
Development tools
Type Number
nRF6700
nRF2460-DK
nRF6915
Description
nRFgo Starter Kit
nRFgo Development Kit for nRF2460
nRFready Microphone Reference Design
Table 32. nRF2460 solution options
Revision 1.0
Page 50 of 56
nRF2460 Product Specification
15
Application information
To ensure optimal performance it is essential that you follow the schematics- and layout references closely.
Especially in the case of the antenna matching circuitry (components between device pins ANT1, ANT2,
VDD_PA and the antenna), any changes to the layout can change the behavior, resulting in degradation of
RF performance or a need to change component values. All the reference circuits are designed for use
with a 50ȍ single end antenna.
15.1
Crystal specification
Tolerance includes initial accuracy and tolerance over temperature and aging.
Frequency
16 MHz
CL
8pF to 16pF
ESR
100
C0max
7.0pF
Tolerance
+/-50 ppm
Table 33. Crystal specification for nRF2460
In order to obtain a crystal setup with low power consumption and fast start-up time, a crystal with low
crystal load capacitance is recommended.
The crystal load capacitance, CL, is given by:
C1 and C2 are SMD capacitors as shown in the application schematic. CPCB1 and CPCB2 are the layout
parasitic on the circuit board. CI1 and CI2 are the capacitance seen into the XC1 and XC2 pin respectively,
the value is typical 1pF.
15.2
Bias reference resistor
A resistor between pin IREF (pin 24) and ground sets up the bias reference for the nRF2460. A 22 k
(1%) resistor is to be fitted. Changing the value of this resistor will degrade nRF2460 performance.
15.3
Internal digital supply de-coupling
Pin DVDD (pin15) is a regulated output of the internal digital power supply of nRF2460. The pin is purely for
de-coupling purposes and only a 33nF (X7R) capacitor is to be connected. The pin must not be connected
to external VDD and cannot be used as power supply for external devices.
15.4
PCB layout and de-coupling guidelines
A well-designed PCB is especially necessary in order to achieve good RF performance. Keep in mind that
a poor layout may lead to loss of performance, or even functionality if due care is not taken. A fully qualified
RF-layout for the nRF2460 and its surrounding components, including antenna matching network, can be
downloaded from www.nordicsemi.com.
Revision 1.0
Page 51 of 56
nRF2460 Product Specification
A PCB with a minimum of two layers with ground planes is recommended for optimum performance. The
nRF2460 DC supply voltage must be de-coupled as close as possible to the VDD pins, see chapter 16 on
page 53. A large value capacitor (for example 4.7F to 10F) should be placed in parallel with the smaller
value capacitors. The nRF2460 supply voltage must be filtered and routed separately from the supply
voltages of other circuitry. When the nRF2460 is used in combination with A/D and D/A converters, it is
very important to avoid power supply noise generated by the nRF2460 from reaching the analogue supply
pins of the A/D and D/A converters. Hence, star-routing directly from a low-noise supply source (for
example a linear voltage regulator) is highly recommended, and where the nRF2460 has its own power
supply line from the supply source and also the A/D and D/A converters have their own separate digital
and analogue supply lines.
Long power supply lines on the PCB should be avoided. All device grounds, VDD connections and VDD
bypass capacitors must be connected as close as possible to the nRF2460 IC. For a PCB with a topside
RF ground plane, the VSS pins should be connected directly to the ground plane. For a PCB with a bottom
ground plane, the best technique is to place Via holes as close as possible to the VSS pins. A minimum of
one Via hole should be used for each VSS pin.
Full swing digital data or control signals should not be routed close to the reference crystal or the power
supply lines.
Revision 1.0
Page 52 of 56
nRF2460 Product Specification
16
Reference circuits
This chapter shows a typical schematic and reference layout for both ATX and ARX.
16.1
Schematic
VTG'
VTG'
36
35
34
33
32
31
30
29
28
U1
nRF2460
C2
1.0nF
C9
10nF
nRF2460_IRQ
nRF2460_SSEL
nRF2460_SDA
nRF2460_SCL
nRF2460_SADR
nRF2460_SMOSI
R3
22k
IRQ
NC
VSS
VDD
VSS
NC
NC
NC
RESO
C1
4.7μF
VTG'
VTG'
1
2
3
4
5
6
7
8
9
nRF2460
SSEL
SMISO/SSDA
SSCK/SSCL
SCSN/SADR
VDD
SMOSI
SYNDR
SYNC
T1
QFN36 6x6
R2
RESET
MODE
VSS
IREF
VSS_PA
ANT2
ANT1
VDD_PA
VDD
27
26
25
24
23
22
21
20
19
22k
R1
nRF2460_RESET
nRF2460_MODE
C6
1.2pF
22k
C7
L3
Antenna
5.6nH
1.5pF
L1
4.7nH
C8
1.2pF
L2
10
11
12
13
14
15
16
17
18
CLK
WS
DATA
T2
MCLK
DVDD
VSS
XC2
XC1
8.2nH
C5
1.2pF
nRF2460_CLK
nRF2460_WS
nRF2460_DATA
nRF2460_MCLK
C3
2.2nF
C4
N.C.
X1
C10
33nF
16MHz
R4
1M0
C11
15pF
C12
15pF
Figure 21. nRF2460 schematic
Resistor R3 is not necessary for device functionality. R3 is added to guarantee that no nRF2460 register is
written to if the external MCU is resetting.
Revision 1.0
Page 53 of 56
nRF2460 Product Specification
16.2
Layout
No components
in bottom layer
Top silk screen
Top view
Bottom view
Figure 22. nRF2460 PCB layout
Revision 1.0
Page 54 of 56
nRF2460 Product Specification
16.3
Bill of Materials
Designator
C1
C2
C3
C5, C6, C8
C7
C9
C10
C11, C12
L1
L2
L3
R1
R2, R3
R4
U1
X1
Value
4.7F
1.0 nF
2.2nF
1.2pF
1.5pF
10nF
33nF
15pF
4.7nH
8.2nH
5.6nH
22k:
22k:
1M0
nRF2460
16 MHz
Footprint
0805
0402s
0402s
0402s
0402s
0402s
0402s
0402s
0402s
0402s
0402s
0402s
0402s
0402s
QFN36
3.2x2.5mm
Description
X7R+/-10%
X7R+/-10%
X7R+/-10%
NP0 +/-0.1pF
NP0 +/-0.1pF
X7R+/-10%
X7R+/-10%
NP0 +/-2%
High frequency chip inductor +/-5%
High frequency chip inductor +/-5%
High frequency chip inductor +/-5%
1%
5%
5%
6x6mm package
SMD-3225, 16 MHz, CL=9pF, +/-50
ppm
Table 34. nRF2460 BOM
Revision 1.0
Page 55 of 56
nRF2460 Product Specification
17
Glossary
Term
ADC
AFH
ARX
ATX
BER
BOM
CD
CPHA
CLK
CPOL
CRC
CSN
DAC
FIFO
Flash
GFSK
GPIO
I2S
ISM
Latency
LPCM
LSB
Mbps
MBZ
MSB
PCB
QoS
SPI
2-wire
Description
Analog to Digital Converter
Adaptive Frequency Hopping
Audio Receiver
Audio Transmitter
Bit Error Rate
Bill Of Materials
Carrier Detect
SPI Clock Phase
Clock
CSPI Clock Polarity
Cyclic Redundancy Check
Chip Select Not
Digital to Analog Converter
First In First Out
Flash memory
Gaussian Frequency Shift Keying
General Purpose In Out
Three-wire audio serial interface
Industrial Scientific Model
Audio delay from ATX input to ARX output
Linear PCM (pulse code modulation)
Least Significant Bit
Megabits per second
Must Be Zero (0)
Most Significant Bit
Printed Circuit Board
Quality of Service
Serial Peripheral Interface
2-wire serial interface compatible with I2C
Figure 23. Glossary of terms
Revision 1.0
Page 56 of 56
工商网监
湘ICP备2023018690号
