LMS6002D
Multi-band Multi-standard
Transceiver with Integrated
Dual DACs and ADCs
SUMMARY FEATURES
TXINI
TXINQ
2
DEMUX
TXD[11:0]
12
TX_IQ_SEL
Femtocell and Picocell base stations
Repeaters
Broadband wireless communication devices for
WCDMA/HSPA, LTE, GSM, CDMA2000, IEEE® 802.16x
radios
2
IQ DACs
12
APPLICATIONS
TX Power
Control
TXLPF
TXVGA1 DAC
TX Gain
Control
TXVGA2
TXMIX
PA1
LO Leakage
QDAC
12
TX_CLK
DAC
0o
90o
TXPLL
/2
LMS6002D
RX_CLK_OUT
/2
RX_CLK
RXPLL
0o
90o
12
RXD[11:0]
IADC
MUX
RX_IQ_SEL
12
2
TXOUT1
IDAC
12
QADC
IQ ADCs
RXVGA2
RXLPF
RXVGA1
RXMIX
PA2
LNA1
2
LNA2
2
2
RX Power
Control
RX Gain
Control
RXIN1
RXIN2
2
RXIN3
SPI
SEN
SCLK
SDIO
SDO
RXOUTI
RXOUTQ
2
TXOUT2
LNA3
RXLNA
RXOUTSW
2
AUXPA
RF loopback
120 pin DQFN package
Power down option
Serial port interface
PLLCLK
Single chip transceiver covering 0.3-3.8GHz
frequency range
Digital interface to baseband with integrated 12 bit
D/A and A/D converters
Fully differential baseband signals
Few external components
Programmable modulation bandwidth: 1.5, 1.75, 2.5,
2.75, 3, 3.84, 5, 5.5, 6, 7, 8.75, 10, 12, 14, 20 and 28MHz
Supports both TDD and FDD operation modes
Low voltage operation, 1.8V and 3.3V
PLLCLKOUT
Figure 1: Functional block diagram
GENERAL DESCRIPTION
LNA, PA driver, RX/TX mixers, RX/TX filters, synthesizers, RX gain
control, and TX power control with very few external components.
The LMS6002D is a fully integrated, multi-band, multi-standard RF
transceiver for 3GPP (WCDMA/HSPA, LTE), 3GPP2 (CDMA2000) and
4G LTE applications, as well as for GSM pico BTS. It combines the
Document version: 1.1.0
Last modified: 03/12/2012
© Copyright Lime Microsystems
The information contained in this document is subject to change
without prior notice. Lime Microsystems assumes no responsibility
for its use, nor for infringement of patents or other rights of third
parties. Lime Microsystems' standard terms and conditions apply at
all times.
LMS6002D - Multi-band Multi-standard
Transceiver with Integrated Dual DACs and ADCs
The top level architecture of LMS6002D transceiver is shown in Figure
1. Both transmitter and receiver are implemented as zero IF
architectures providing up to 28MHz modulation bandwidth (equivalent
to 14MHz baseband IQ bandwidth).
mixed with the receive PLL (RXPLL) output to directly down convert to
baseband. Large AGC steps can be implemented by an IF amplifier
(RXVGA1) prior to the programmable bandwidth lowpass channel
select filters (RXLPF). The received IQ signal is further amplified by a
programmable gain amplifier RXVGA2. DC offset is applied at the input
of RXVGA2 to prevent saturation and to preserve receive the ADC(s)
dynamic range. The resulting analog receive IQ signals are converted
into the digital domain using the on chip receive ADCs and provided as
an output to the baseband processor on a multiplexed 12 bit CMOS
output level parallel bus. The receive clock, RX_CLK, is provided off
chip at the RX_CLK_OUT pin and can be used to synchronise with the
baseband digital receive data sampling clock.
On the transmit side, IQ DAC samples from the baseband processor
are provided to the LMS6002D on a 12 bit multiplexed parallel CMOS
input level bus. Analog IQ signals are generated by on chip transmit
DACs. These are fed to the TXINI and TXINQ inputs. Transmit low pass
filters (TXLPF) remove the images generated by zero hold effect of the
DACs. The IQ signals are then amplified (TXVGA1) and DC offset is
inserted in the IQ path by LO leakage DACs in order to cancel the LO
leakage. The IQ signals are then mixed with the transmit PLL (TXPLL)
output to produce a modulated RF signal. This RF signal is then split
and amplified by two separate variable gain amplifiers (TXVGA2) and
two off chip outputs are provided as RF output.
By closing the RXOUT switch and powering down RXVGA2, the
RXOUTI and RXOUTQ pins can be used as IQ ADCs inputs. In this
configuration the ADCs can be used to measure two external signals,
such as an off chip PA temperature sensor or peak detector.
Transmitter gain control range of 56dB is provided by IF (TXVGA1,
31dB range) and RF (TXVGA2, 25 dB range) variable gain amplifiers.
Both TXVGAs have 1dB gain step control.
Two transmitter outputs (TXOUT1, TXOUT2) and three receiver inputs
(RXIN1, RXIN2, RXIN3) are provided to facilitate multi-band operation.
The LMS6002D provides an RF loop back option (see Figure 1) which
enables the TX RF signal to be fed back into the baseband for
calibration and test purposes. The RF loop back signal is amplified by
an auxiliary PA (AUXPA) in order to increase the dynamic range of the
loop.
On the receive side, three separate inputs are provided each with a
dedicated LNA. Each port preconditioned RF signal is first amplified by
a programmable low noise amplifier (RXLNA). The RF signal is then
Parameter
The functionality of the LMS6002D is fully controlled by a set of internal
registers which can be accessed through a serial port.
In order to enable full duplex operation, the LMS6002D contains two
separate synthesizers (TXPLL, RXPLL) both driven from the same
reference clock source PLLCLK. The PLLCLK signal is provided at the
PLLCLKOUT output pin and can be used as the baseband clock.
Differential signalling is done in the receive and transmit analog paths
throughout the chip.
Condition/Comment
TRX RF Frequency Range
Min
Typ
0.3
Baseband Bandwidth
0.75
Frequency Resolution
3.1
TRX 1.8V Supply
1.7
Unit
3.8
GHz
14
MHz
2.4
Hz
3.3
3.5
V
1.8
1.9
V
Using 41MHz PLL reference clock
TRX 3.3V Supply
Max
TX Supply Current
At maximum gain
280
mA
RX Supply Current
At maximum gain
220
mA
Digital Core Supply Voltage
Digital Peripheral (IO)
Supply Voltage
Ambient Temperature
Can go below 3.3V nominal to
support LV CMOS signalling
Storage Temperature
Continuous wave
Absolute Maximum RF Input
Power
No damage
PLL Phase Noise
1.8
1.9
V
1.7
3.3
3.5
V
-40
25
85
o
125
o
-65
Maximum RF Output Power
PLL Reference Clock
1.7
6
LMS6002D
2
© Copyright Lime Microsystems
dBm
23
Table 1: General specifications
C
dBm
23
For continuous LO frequency
range
1MHz offset
C
41
-125
MHz
dBc/Hz
Parameter
Condition/Comment
Min
TRX RF Bandwidth
Typ
Max
0.3
Unit
3.8
GHz
Transmit Input Impedance
Differential, programmable
100
Ohms
Transmit Load Impedance
Differential
65
Ohms
Transmit Differential I and Q
Input Voltages
Differential
Common mode
250
65
mVpp
mV
Transmit Gain Control Range
TXVGA1, TXVGA2
56
dB
1
dB
Transmit Gain Control Step
TX LO Leakage
LO leakage not calibrated
-50
RX LNA1 Frequency Range
Narrow band
0.3
2.8
dBc
GHz
RX LNA2 Frequency Range
Narrow band
1.5
3.8
GHz
RX LNA3 Frequency Range
Broad band
0.3
3.0
GHz
RX LNA1 Input Impedance
Differential
RX LNA2 Input Impedance
RX LNA3 Input Impedance
Receive Load Impedance
50
Ohms
Differential
50
Ohms
Differential
200
Ohms
Differential
2k
Ohms
Noise Figure
5
3.5
5.5
10
pF
LNA1 at 0.95GHz
LNA2 at 1.95GHz
LNA3 at 1.95GHz
3rd Order Input Referred
Intercept Point
LNA2 at Mid. Gain
-1
dBm
RXLNA, RXVGA1, RXVGA2
RXVGA1, not log-linear
RXVGA2
61
Receive Load Capacitance
Receive Gain Control Range
Receive Gain Control Step
dB
dB
1
dB
3
Table 2: General RF specifications
The LMS6002D transmitter has two programmable gain stages,
TXVGA1 is located in the IF section and TXVGA2 is in the RF section,
(see Figure 2). TXVGA1 is implemented on the I and Q branches but
controlled by a single control word. TXVGA2 consists of 2 amplifiers
one for each of the transmitter outputs, however only one of these
output amplifiers can be active at any time.
TXINQ TXINI
TXVGA2
Note: The TXLPF has a gain of 6dB or 0dB when bypassed.
2
TXLPF TXVGA1 DAC
2
TXMIX
PA1
LO Leakage
2
DAC
0o
o
90
2
PA2
TXPLL
Figure 2: TX gain control architecture
Parameter
TXLPF Gain
Condition
0 dB gain when bypassed
TXVGA1 Gain Control Range
TXVGA1 Gain Step Size
Guaranteed monotonic
TXVGA2 Gain Control Range
TXVGA2 Gain Step Size
Guaranteed monotonic
Table 3: TX gain control
LMS6002D
3
© Copyright Lime Microsystems
Min
Typ
0
Max
6
Unit
dB
31
dB
1
dB
25
dB
1
dB
TXOUT2 TXOUT1
TX GAIN CONTROL
RXOUTQ RXOUTI
The LMS6002D receiver has three gain control elements, RXLNA,
RXVGA1, and RXVGA2 (see Figure 3). RXLNA gain control consists of
a single 6dB step for AGC when large in co-channel blockers are
present and a reduction in system NF is acceptable. The main LNAs
(LNA1 and LNA2) have fine gain control via a 6 bit word which offers
±6dB control intended for frequency correction when large input
bandwidths are required.
RXVGA1 offers 25dB of control range, a 7 bit control word is used and
the response is not log-linear. Maximum step size is 1dB. RXVGA1 is
intended for AGC steps needed to reduce system gain prior to the
channel filters when large in band blockers are present. This gain can
be under control of the baseband or fixed on calibration.
RXPLL
o
0
90o
LNA1
2
LNA2
2
LNA3
2
2
2
RXVGA2 RXLPF RXVGA1 RXMIX
RXLNA
RXVGA2 provides the bulk of gain control for AGC if a constant RX
signal level at the ADC input is required. It has 30dB gain range control
in 3dB steps.
RXIN3 RXIN2 RXIN1
RX GAIN CONTROL
Figure 3: RX gain control architecture
Note: RXLPF has a gain of 0dB when bypassed.
Parameter
RXLNA Gain Control Range
Condition
Min
Single step
Typ
6
RXVGA1 Gain Control Range
25
RXVGA1 Gain Step Size
Not log-linear
RXLPF Gain
0 dB gain when bypassed
Unit
dB
dB
0
RXVGA2 Gain Control Range
RXVGA2 Gain Step Size
Max
0
1
dB
6
dB
30
dB
3
dB
Guaranteed monotonic
Table 4: RX gain control
SYNTHESIZERS
PFD
0o
CHP
VCO
o
90
/N
SD
NINT, NFRAC
Figure 4: PLL architecture
LMS6002D
4
© Copyright Lime Microsystems
Output
Divider
T(R)CPOUT
PLLCLK
The LMS6002D can accept clipped sine as well as the CMOS level
signals as the PLL reference clock. Both DC and AC coupling are
supported as shown in Figure 5. Internal buffer self biasing must be
enabled for AC coupling mode. PLL reference clock input can also be
low voltage CMOS (2.5V or 1.8V, for example) which is implemented by
lowering clock buffer supply PVDDSPI33.
T(R)XVTUNE
External
Loop
Filter
LMS6002D has two low phase noise synthesizers to enable full duplex
operation. Both synthesizers are capable of output frequencies up to
3.8GHz. Each synthesizer uses a fractional-N PLL architecture as
shown in Figure 4. The same reference frequency is used for both
synthesisers and is flexible between 23 to 41MHz. The synthesizers
produce a complex output with suitable level to drive IQ mixers in both
the TX and the RX paths.
LMS6002D - Multi-band Multi-standard
Transceiver with Integrated Dual DACs and ADCs
PVDDSPI33
PVDDSPI33
PLLCLK
TXCO
External
TXCO
External
CLKBUF
LMS6002D
PLLCLK
VSS
LMS6002D
(a)
CLKBUF
VSS
(b)
Figure 5: PLL reference clock input buffer, (a) DC coupled (b) AC coupled
Parameter
Frequency Range
Reference Amplitude
Reference Frequency
Frequency Step Size
Phase Noise
10 KHz offset
100 KHz offset
1 MHz offset
Condition
At PVDDSPI33=3.3V
For continuous LO frequency range
At 41MHz reference clock
800MHz
1.9GHz
Phase Noise
10 KHz offset
100 KHz offset
1 MHz offset
Reference Spurious
Outputs
Other Spurious
Outputs
2.6GHz
IQ Amplitude Error
PLL settling time
Typ
0.8
Max
3.8
3.3
41
2.4
Unit
GHz
Vpp
MHz
Hz
-94
-113
-130
Phase Noise
10 KHz offset
100 KHz offset
1 MHz offset
IQ Phase Error
Min
0.3
0.2
23
-89
-95
-125
dBc/Hz
-86
-90
-125
800MHz
1.9GHz
2.6GHz
To 1ppm, 50kHz loop bandwidth
1
3
9
0.4
20
-50
dBc
-50
dBc
deg
dB
μs
Table 5: Synthesizer specifications
RF PORTS
TX and RX LOW PASS FILTERS
LMS6002D has two transmitter outputs and three receiver inputs.
LMS6002D integrates highly selective low pass filters in both TX and
RX paths. Filters have a programmable pass band in order to provide
more flexibility on the DAC/ADC clock frequency and also to provide
excellent adjacent channel rejection in the receive chain. The following
LPF pass bands are supported: 14, 10, 7, 6, 5, 4.375, 3.5, 3, 2.75, 2.5,
1.92, 1.5, 1.375, 1.25, 0.875, and 0.75MHz. Filters are also tunable to
compensate for process/temperature variation. The TX and RX filters
are the same but controlled via SPI link independently. Measured
amplitude responses are shown in Figure 6.
The transmitter output ports are optimized for a 65Ω differential load,
the final stage amplifiers are open drain and require +3.3V voltage
supply, see LMS6002D typical application circuit in Figure 19.
The receiver inputs are all different. RXIN1 is the low frequency input
and can operate in the range 0.3 – 2.8GHz, RXIN2 is the high
frequency input and can operate in the range 1.5 – 3.8GHz. Both
RXIN1 and RXIN2 require matching circuits for optimum performance.
A simple match is shown in Figure 19. RXIN3 is a broadband input
covering the range 0.3 – 3.0GHz, it is 200Ω differential and is typically
matched with a wideband transformer.
Assuming 40MHz DAC/ADC clock, 28MHz modulation bandwidth
(equivalent to 14MHz baseband IQ bandwidth) and 28MHz channel
spacing, performance of the TRX filters is summarised as below.
TX low pass filter:
First DAC image attenuation
Second DAC image attenuation
LMS6002D
5
© Copyright Lime Microsystems
>= 55dB
>= 70dB
LMS6002D - Multi-band Multi-standard
Transceiver with Integrated Dual DACs and ADCs
RX low pass filter
Alias attenuation
First adjacent channel attenuation
Second adjacent channel attenuation
Recommended LMS6002D initialization sequence is as follows:
>= 50dB
>= 45 dB
>= 70 dB
1.
2.
3.
10
4.
0
-10
Normalized Gain [dB]
5.
0.75MHz
-20
0.875MHz
1.25MHz
6.
1.375MHz
-30
1.5MHz
1.92MHz
2.5MHz
-40
2.75MHz
-50
-60
-70
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
7.
8.
9.
6.5
Frequency [MHz]
Apply RESET pulse (active low). This sets all the
configuration registers to their default values.
Set target LO frequency and gain for both TX and RX chains.
LPF tuning
a. DC offset cancellation of the tuning module
b. Execute LPF bandwidth tuning procedure
TXLPF
a. DC offset cancellation of I filter
b. DC offset cancellation of Q filter
RXLPF
a. DC offset cancellation of I filter
b. DC offset cancellation of Q filter
RXVGA2
a. DC offset cancellation of the reference generator
b. DC offset cancellation of the first gain stage, I
branch
c. DC offset cancellation of the first gain stage, Q
branch
d. DC offset cancellation of the second gain stage, I
branch
e. DC offset cancellation of the second gain stage, Q
branch
TX LO leakage cancellation
TX IQ gain/phase error calibration
RX IQ gain/phase error calibration
Once the device is calibrated, register values can be stored and
uploaded back into LMS6002D at the next power up/reset point which
will shorten the initialization time.
10
0
Refer to “LMS6002D Programming and Calibration Guide” for more
details.
3MHz
-20
DIGITAL IQ DATA INTERFACE
3.5MHz
4.375MHz
5MHz
6MHz
Description
7MHz
10MHz
-50
-60
-70
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
Frequency [MHz]
IQ DACs
Figure 6: Measured TX/RX LPF amplitude responses
TXD[11:0]
12
CALIBRATION AND INITIALIZATION
TX_IQ_SEL
There are a number of calibrations which the LMS6002D can carry out
internally when instructed via the SPI. These calibrations can be
initiated on power up/reset to produce optimum settings. The following
auto calibration options are available:
DC offset cancellation within the various blocks
TRX LPF bandwidth tuning
QDAC
TX_CLK
/2
RX_CLK
/2
12
RX_IQ_SEL
Additionally, LMS6002D provides the blocks such as LO leakage DACs
and RF loop back to further facilitate the following calibrations:
IDAC
12
IADC
MUX
12
RXD[11:0]
12
12
QADC
IQ ADCs
LO leakage in the transmit chain
IQ gain and phase mismatch in both transmit and receive
chains
Figure 7: Baseband data interface
Note that these calibrations require the loop to be closed externally via
the baseband.
1
LMS6002D
LimeLight™
6
© Copyright Lime Microsystems
LimeLight™ is trademark of Lime Microsystems Ltd
TXINQ TXINI
The functionality of LMS6002D transceiver implements a subset of the
LimeLight™ LMS600X-01008031 digital IQ interface with a 12 bit
multiplexed transmit path and a 12 bit multiplexed receive path as
shown in Figure 7. TX and RX interfaces require a clock running at
twice the data converters sample rate. Separate clocks can be provided
for the TX and RX interface. Location of the IQ samples in the
multiplexed stream is flagged by the IQ select signals which are
required as an input to the transmit path and provided as an output from
the receive path.
14MHz
RXOUTI
-40
RXOUTQ
-30
DEMUX
Normalized Gain [dB]
-10
LMS6002D - Multi-band Multi-standard
Transceiver with Integrated Dual DACs and ADCs
tSETUP
tHOLD
For both TX and RX interfaces IQ_SEL (frame sync) polarity and
interleave mode are independently programmable via the SPI link, see
Figure 8. Here, the frame is defined as two consecutive T(R)X_CLK, i.e.
one T(R)X_IQ_SEL, periods while IQ data from the same sampling
point are present on the multiplexed bus.
TX_CLK
TX_IQ_SEL
Frame
Frame
TXD[11:0]
T(R)X_ IQ_SEL
Positive IQ_SEL polarity
T(R)X_IQ_SEL
Negative IQ_SEL polarity
T(R)XD[11:0]
I0
Q0
Q1
I1
I_DATA[11:0]
I0
I1
Q_DATA[11:0]
Q0
Q1
IQ interleave mode
Q0
Q1
I1
TX_CLK/2
I2
QI interleave mode
T(R)XD[11:0]
Q0
I0
I0
External Signals
I1
Q1
Q2
Internal Signals
Figure 10: TX IQ interface signals
Some examples of the TX interface data rates are provided below:
Figure 8: Frame sync polarity and interleave modes
Transmitter Data Interface
More detailed functional diagram of the TX data interface is shown in
Figure 9. Corresponding waveforms are given in Figure 10. The
interface is a 12 bit parallel bus from the base band IC carrying
multiplexed IQ data samples for the transmit DACs. The interface data
rate is twice the DACs sample rate. TX_IQ_SEL flag is used to identify I
and Q samples on the multiplexed bus. Note that the DACs sampling
clock is not derived by dividing TX_CLK by two as indicated in Figure 7.
Instead, registered version of TX_IQ_SEL is used. Hence, for the DACs
to receive sampling clock TX_IQ_SEL must be provided and toggled as
in Figure 8. DACs sampling edge is also programmable via SPI link.
RX digital IQ interface related pins are described as follows:
RX_CLK
RX interface data clock, positive edge
sensitive (input)
RXD[11:0]
12 bit multiplexed IQ data bus (output)
RX_IQ_SEL Indicates the location of I and Q data on the
multiplexed bus (output)
adc_clk_pol
Q
CLK
Divide by 2
TX_CLK/2
tx_interleave_mode
Figure 9: TX data interface
QN
rx_interleave_mode
rx_fsinc_polarity
Figure 11: RX data interface
7
© Copyright Lime Microsystems
Q
CLK
dac_clk_pol
LMS6002D
D
DFF
B
D
QN
RX_IQ_SEL
B
Y
DFF
Y
SEL
MUX
A
RX_CLK/2
Y
RX_CLK
QN
B
SEL
CLK
A
A
MUX
Q
D[11:0]
CLK
MUX
DAC
CLK
ADC
SEL
D[11:0]
B[11:0]
D[11:0] Q[11:0]
Y[11:0]
RXD[11:0]
Dual ADC
Dual DAC
CLK
D
Q_DATA[11:0]
RXOUTQ
B[11:0]
Y[11:0]
A[11:0]
CLK
TXINQ
CLK
Q_DATA[11:0]
MUX
A[11:0]
I_DATA[11:0]
REG
D[11:0]
MUX
DAC
SEL
REG
D[11:0] Q[11:0]
tx_fsinc_polarity
LimeLight™
ADC
SEL
TXINI
D[11:0]
More detailed functional diagram of the RX data interface is shown in
Figure 11. Corresponding waveforms are given in Figure 12. The
interface is a 12 bit parallel bus output from the LMS6002D to the base
band IC carrying multiplexed IQ data samples from the receive ADCs.
The interface data rate is twice the ADCs sample rate. RX_IQ_SEL flag
is provided to identify I and Q samples on the multiplexed bus. The
receive clock coming from the baseband is on chip divided by two
before being used by the ADC’s. The ADCs sampling edge is also
programmable via SPI link.
RXOUTI
B[11:0]
Y[11:0]
Receiver Data Interface
CLK
DFF
TX_IQ_SEL
TX_CLK
MUX
CLK
TXD[11:0]
CLK
A[11:0]
SEL
REG
D[11:0] Q[11:0]
REG
D[11:0] Q[11:0]
I_DATA[11:0]
The TX digital IQ interface related pins are described as follows:
TX_CLK
TX interface data clock, positive edge
sensitive (input)
TXD[11:0]
12 bit multiplexed IQ data bus (input)
TX_IQ_SEL Indicates the location of I and Q data on the
multiplexed bus (input)
DACs sample rate
o
WCDMA
15.36 MS/s
o
GSM
1.083 MS/s
TX IQ interface data rate
o
WCDMA
30.72 MS/s
o
GSM
2.167 MS/s
LMS6002D - Multi-band Multi-standard
Transceiver with Integrated Dual DACs and ADCs
Some examples of the RX interface data rates are provided below:
tOD
RX_CLK
RX_CLK/2
I_DATA[11:0]
I0
I1
Q_DATA[11:0]
Q0
Q1
RXD[11:0]
I0
Q0
I1
IQ Interface Timing Parameters
Q1
Parameter
TX Setup Time (tSETUP)
TX Hold Time (tHOLD )
RX Output Delay (tOD) at 15pF load
RX_IQ_SEL
External Signals
ADCs sample rate
o
WCDMA
15.36 MS/s
o
GSM
1.083 MS/s
RX IQ interface data rate
o
WCDMA
30.72 MS/s
o
GSM
2.167 MS/s
Min
1
0.2
Typ
Max
6
Internal Signals
Table 6: Digital IQ interface timing
parameters at 3.3V IO supply
Figure 12: RX data interface signals
DACs Electrical Specifications
(At TA = 25°C, TAVDD33 = 3.3 V, FCLK = 40 MSPS, FOUT = 4 MHz, internal references, -1 dBFS input signal unless otherwise noted)
Parameter
Condition
Digital Core Supply
Analog Supply
Number of Bits
Min
Typ
Max
1.7
1.8
1.9
V
3.1
3.3
3.5
V
Two’s complement format
12
DAC Sampling Rate
Unit
bits
40
MHz
Full Scale Current
Programmable
2.5
mA
Output Amplitude
At 100 Ohm differential load
250
mVpp diff
SFDR
60
dBc
ENOB
10
bits
Table 7: DACs electrical specifications
ADCs Electrical Specifications
(At TA = 25°C, RAVDD18 = 1.8 V, FCLK = 40 MSPS, FOUT = 4 MHz, internal references, -1 dBFS input signal unless otherwise noted)
Parameter
Min
Typ
Max
Digital Core Supply
1.7
1.8
1.9
V
Analog Supply
1.7
1.8
1.9
V
Number of Bits
Condition
Two’s complement format
12
ADC Sampling Rate
Input Amplitude
Differential
1
Input Common Mode Voltage
Input buffer off
0.9
Unit
bits
40
MHz
1.8
Vpp
V
Input Impedance
2
kOhm
ENOB
10
bits
Table 8: ADCs electrical specifications
LMS6002D
LimeLight™
8
© Copyright Lime Microsystems
Unit
ns
ns
ns
LMS6002D - Multi-band Multi-standard
Transceiver with Integrated Dual DACs and ADCs
Digital IQ Interface IO Buffers Specifications
Parameter
Condition
Can go below 3.3V nominal to support
LV CMOS signalling
Supply Voltage (PVDD)
Input High VIH
Input Low VIL
Output High VOH
Output Low VOL
Input Pad Capacitance CIN
Output Drive Current1
1
Min
Typ
Max
1.7
3.3
3.5
PVDD-0.8
0.8
PVDD-0.4
0.4
3.5
8
Unit
V
V
V
V
V
pF
mA
Maximum peak current that flows when the output digital lines change state and begin charging the load capacitance.
Table 9: Digital IO buffers specifications at 3.3V supply
Both write and read SPI operations are supported. The serial port can
be configured to run in 3 or 4 wire mode with the following pins used:
SEN
serial port enable, active low
SCLK
serial clock, positive edge sensitive
SDIO
serial data in/out in 3 wire mode
serial data input in 4 wire mode
SDO
serial data out in 4 wire mode
don’t care in 3 wire mode
Implementing Low Voltage Digital IQ Interface
Digital IO buffers in LMS6002D are supplied using four pins
(PVDDAD33A - PVDDAD33D). All these pins must be supplied by the
same supply PVDD. There is one additional supply pin (PVDDVGG)
dedicated for ESD protection diodes supply. PVDDVGG must be
supplied by +3.3V. However, PVDD can go below 3.3V to implement
low voltage signaling. For example, if PVDD=2.5V then all data lines in
Figure 13 are set to 2.5V CMOS IOs. Having PVDDVGG=3.3V sets all
inputs to be 3.3V tolerant. Minimum PVDD is 1.8V.
PVDD
1.8 - 3.3 V
+3.3 V
0 - PVDD CMOS
Logic Levels
Base Band
12
12
PVDDAD33A
PVDDAD33B
PVDDAD33C
PVDDAD33D
IO Buffers
Supplies
PVDDVGG
ESD Diodes
Supply
TXD[11:0]
TX_IQ_SEL
TX_CLK
TX (DAC)
Interface
Serial port key features:
16 SPI clock cycles are required to complete write operation.
16 SPI clock cycles are required to complete read operation.
Multiple write/read operations are possible without toggling serial
port enable signal.
All configuration registers are 8-bit wide. Write/read sequence consists
of 8-bit instruction followed by 8-bit data to write or read. MSB of the
instruction bit stream is used as SPI command where CMD=1 for write
and CMD=0 for read. Remaining 7 bits of the instruction represent
register address.
The write/read cycle waveforms are shown in Figures 14, 15 and 16.
Note that the write operation is the same for both 3-wire and 4-wire
modes. Although not shown in the figures, multiple byte write/read is
possible by repeating the instruction/data sequence while keeping SEN
low.
RX_CLK_OUT
RX_CLK
RX (ADC)
RX_IQ_SEL
Interface
RXD[11:0]
SPI Timing Parameters
LMS6002D
Parameter
Clock Frequency,
Figure 13: Digital IQ interface supplies
4-wire mode
3-wire mode
Enable Setup Time (tES)
Enable Hold Time (tEH)
Data Setup Time (tDS)
Data Hold Time (tDH)
Data Output Delay (tOD) at 12pF load
SERIAL PORT INTERFACE
Description
The functionality of LMS6002D transceiver is fully controlled by a set of
internal registers which can be accessed through a serial port interface.
Min
Typ
Max
50
20
2
0.2
1
0.2
9
Table 10: SPI timing parameters at 3.3V IO supply
LMS6002D
LimeLight™
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© Copyright Lime Microsystems
Unit
MHz
MHz
ns
ns
ns
ns
ns
Write Operation
tES
tEH
tDS
tDH
SEN
SCLK DON'T CARE
SDIO
DON'T CARE
DON'T CARE
1
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
WRITE INSTRUCTION
D4
D3
D2
D1
DON'T CARE
D0
DATA
Figure 14: SPI write cycle, 3-wire and 4-wire modes
Read Operation
tES
tOD
tDS
tEH
tDH
SEN
SCLK DON'T CARE
SDIO
DON'T CARE
DON'T CARE
A6
0
A5
A4
A3
A2
A1
DON'T CARE
A0
READ INSTRUCTION
SDO
D7
DON'T CARE
D6
D5
D4
D3
D2
D1
DON'T CARE
D0
OUTPUT DATA
Figure 15: SPI read cycle, 4-wire mode (default)
tES
tDS
tOD
tEH
tDH
SEN
SCLK DON'T CARE
SDIO
DON'T CARE
DON'T CARE
0
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
READ INSTRUCTION
D4
D3
D2
D1
D0
DON'T CARE
OUTPUT DATA
Figure 16: SPI read cycle, 3-wire mode
SPI Memory Map
The LMS6002D configuration registers are divided into eight logical
blocks as shown in Table 11. 3 MSBs of the available 7-bit address are
used as block address while the remaining 4 bits are used to address
particular registers within the block.
Integer and fractional part of the PLL divider are stored in four bytes of
configuration memory. To change their values, four write cycles are
required. Hence, the controlled PLL should see new NINT and NFRAC
when all four bytes are updated, otherwise it will generate unpredicted
and wrong LO frequency while being configured. Such parameters are
provided through a shadow register. Shadow register outputs new
values only when SEN is high, i.e. there is no access to configuration
memory. For that reason, DSM (PLL) SPI synchronization clock,
derived from the PLL reference, must be enabled while writing to or
reading from the PLL configuration registers and should last at least two
cycles more after SEN goes high.
Address (7 bits)
000:xxxx
001:xxxx
Description
Top level configuration
TX PLL
© Copyright Lime Microsystems
010:xxxx
011:xxxx
100:xxxx
101:xxxx
110:xxxx
111:xxxx
RX PLL
TX LPF
TX RF
RX LPF, DACs and ADCs
RX VGA2
RX RF
Table 11: LMS6002D SPI memory map
Implementing Low Voltage SPI
Digital IO buffers and ESD protection diodes in the SPI region are all
supplied from a single pin PVDDSPI33. PVDDSPI33 can go below 3.3V
to implement low voltage signaling. For example, if PVDDSPI33=2.5V
then all data lines in Figure 17, including PLL reference clock input, are
set to 2.5V CMOS IOs. There is no dedicated ESD protection diodes
supply here so when PVDDSPI33 is less than 3.3V, inputs will not be
3.3V tolerant. Minimum PVDDSPI33 is 1.8V.
Base Band
0 - PVDDSPI CMOS
Logic Levels
1.8 - 3.3 V
PVDDSPI
IO Buffers and
PVDDSPI33 ESD Diodes
Supply
SEN
SDO
SDIO
CLK
SPI
RESET
TXEN
RXEN
Chip
Control
PLLCLK
Reference
Clock
LMS6002D
Figure 17: SPI supplies
LMS6002D
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© Copyright Lime Microsystems
PACKAGE OUTLINE AND PIN DESCRIPTION
9 mm
6.5 mm
NC
116
114 112
115
7
101
99
96
97
94
95
92
93
90
91
88
89
87
2
86
4
84
6
82
8
80
10
78
85
83
81
79
9
11
7 mm
9 mm
13
DQFN120
9 x 9 mm
0.5 mm pitch
12
14
15
16
17
18
77
76
75
74
73
72
71
70
19
69
20
68
22
66
24
64
26
62
28
60
21
67
23
65
25
63
27
61
29
59
31
NC
30
33
32
35
34
37
36
39
38
41
40
43
42
45
44
47
46
49
48
51
50
53
52
55
54
57
56
0.5 mm
7 mm
Figure 18: DQFN120 package (top view)
LMS6002D
LimeLight™
NC
12
© Copyright Lime Microsystems
58
NC
8.5 mm
5
109 107 105 103
98
7.5 mm
3
113 111
104 102 100
6.5 mm
1
110 108 106
Pin No
Pin Name
Type
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
PVDDAD33A
RXD11
RXD10
RXD9
RXD8
RXD7
PVDDVGG
RXD5
RXD6
RXD3
RXD4
PVDDAD33B
RXD2
pads supply
out cmos
out cmos
out cmos
out cmos
out cmos
esd supply
out cmos
out cmos
out cmos
out cmos
pads supply
out cmos
ADCs/DACs IOs supply (3.3V)
ADCs digital output, bit 11 (MSB)
ADCs digital output, bit 10
ADCs digital output, bit 9
ADCs digital output, bit 8
ADCs digital output, bit 7
ADCs/DACs IOs ESD supply (3.3V)
ADCs digital output, bit 5
ADCs digital output, bit 6
ADCs digital output, bit 3
ADCs digital output, bit 4
ADCs/DACs IOs supply (3.3V)
ADCs digital output, bit 2
14
15
16
17
18
19
20
21
22
23
24
RXD1
RXD0
RX_IQ_SEL
RX_CLK
PVDDAD33C
TX_CLK
TX_IQ_SEL
TXD0
TXD1
TXD2
TXD3
out cmos
out cmos
out cmos
in cmos
pads supply
in cmos
in cmos
in cmos
in cmos
in cmos
in cmos
ADCs digital output, bit 1
ADCs digital output, bit 0 (LSB)
RX digital interface IQ flag
RX digital interface clock
ADCs/DACs IOs supply (3.3V)
TX digital interface clock
TX digital interface IQ flag
DACs digital input, bit 0 (LSB)
DACs digital input, bit 1
DACs digital input, bit 2
DACs digital input, bit 3
25
26
27
28
29
30
TXD4
TXD5
TXD6
TXD7
TXD8
TXD9
in cmos
in cmos
in cmos
in cmos
in cmos
in cmos
DACs digital input, bit 4
DACs digital input, bit 5
DACs digital input, bit 6
DACs digital input, bit 7
DACs digital input, bit 8
DACs digital input, bit 9
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
TXD10
TXD11
RDVDD18
PVDDAD33D
RAVDD18
TDVDD18
TAVDD33
VREFAD
XRESAD
RX_CLK_OUT
PLLCLKOUT
ATP
TXVCCLPF33
TXOUT2N
TXVCCMIX33
TXOUT2P
TXPVDD33
in cmos
in cmos
digital supply
pads supply
analogue supply
digital supply
analogue supply
in/out
in/out
out cmos
out cmos
out
analogue supply
out
analogue supply
out
esd supply
DACs digital input, bit 10
DACs digital input, bit 11 (MSB)
ADCs digital supply (1.8V)
ADCs/DACs pads supply (3.3V)
ADCs analogue supply (1.8V)
DACs digital supply (1.8V)
DACs analogue supply (3.3V)
External capacitor for ADCs/DACs (>100nF)
External resistor for ADCs/DACs
Buffered RX_CLK (ADCs) clock, CMOS level
Buffered PLLCLK (PLL reference) clock, CMOS level
Analogue test point
TXLPF supply (3.3V)
TX output 2, negative
TXMIX supply (3.3V)
TX output 2, positive
TX pads ESD supply (3.3V)
48
49
50
51
52
53
54
55
56
57
58
59
60
TXOUT1P
TXVCCDRV33
TXOUT1N
TXININ
TXINIP
UNUSED
TXINQP
UNUSED
TXINQN
TXVTUNE
TXPVDDPLL33A
TXVCCVCO33
TXVDDVCO18
out
analogue supply
out
in/out
in/out
TX output 1, positive
TXVGA2 supply (3.3V)
TX output 1, negative
TXDAC output / TXLPF input
TXDAC output / TXLPF input
in/out
TXDAC output / TXLPF input
in/out
in/out
esd supply
analogue supply
analogue supply
TXDAC output / TXLPF input
TXPLL loop filter output
TXPLL pads ESD supply (3.3V)
TXPLL 3.3V supply (3.3V)
TXPLL VCO supply (1.8V)
Note
Can be lowered down to 1.8V to support LV signalling
Two's complement
Can be lowered down to 1.8V to support LV signalling
Can be lowered down to 1.8V to support LV signalling
Two's complement
Can be lowered down to 1.8V to support LV signalling
Can be used to align RXD[11:0] sampling clock in BB.
Can be used as BB clock.
Connect to ground
Connect to ground
Table 12: Pin descriptions
LMS6002D
13
© Copyright Lime Microsystems
Pin No
Pin Name
61
62
63
64
65
66
67
68
69
70
TXVCCPLL18
TXPVDDPLL33B
TXVCCCHP33
TXCPOUT
TSTD_out1
TXEN
SEN
SDO
SDIO
SCLK
71
PLLCLK
72
TRXVDDDSM18
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Type
Description
digital supply
esd supply
analogue supply
in/out
out cmos
in cmos
in cmos
out cmos
in/out cmos
in cmos
in, cmos or
clipped sine
digital supply
TX PLL modules 1.8V supply (1.8V)
TX PLL pads ESD supply (3.3V)
TX PLL charge pump supply (3.3V)
Transmit PLL loop filter input
TX and RX PLLs digital test point
Transmitter enable, active high
Serial port enable, active low
Serial port data out
Serial port data in/out
Serial port clock, positive edge sensitive
VSPI18
PVDDSPI33
RESET
RXEN
TSTD_out2
RXVCCCHP33
RXVCCLOB33
RXCPOUT
RXPVDDPLL33B
RXVCCVCO33
RXVCCPLL18
RXVDDVCO18
RXVCCPLL33
RXPVDDPLL33A
RXVTUNE
UNUSED
XRES12k
digital supply
esd supply
in cmos
in cmos
out cmos
analogue supply
analogue supply
in/out
esd supply
analogue supply
digital supply
analogue supply
analogue supply
esd supply
in/out
SPI digital core supply (1.8V)
SPI pads and ESD Supply (3.3V)
Hardware reset, active low
Receiver enable, active high
TX and RX PLLs digital test point
RXPLL charge pump supply (3.3V)
RXPLL LO buffer supply (3.3V)
RXPLL loop filter input
RXPLL pads ESD supply (3.3V)
RXPLL 3.3V supply (3.3V)
RXPLL 1.8V supply (1.8V)
RX PLL VCO supply (1.8V)
RX PLL 3.3V supply
RXPLL pads ESD supply (3.3V)
RXPLL loop filter output
in/out
External 12k 1% resistor to ground
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
RXVCCMIX33
OEXLNA1P
IEXMIX1P
UNUSED
IEXMIX1N
OEXLNA1N
RXIN1P
RXIN1EP
RXIN1N
RXIN1EN
RXIN2P
RXVCCLNA33
RXIN2N
OEXLNA2P
IEXMIX2P
OEXLNA2N
IEXMIX2N
RXPVDD33
analogue supply
out
in
RXMIX supply (3.3V)
LNA1 output positive
Mixer input 1 positive
in
out
in
in
in
in
in
analogue supply
in
out
in
out
in
esd supply
Mixer input 1 negative
LNA1 output negative
RX1 (LNA1) input
LNA1 external emitter inductance
RX1 (LNA1) input
LNA1 external emitter inductance
RX2 (LNA2) input
RX LNA supply (3.3V)
RX2 (LNA2) input
LNA2 output positive
Mixer input 2 positive
LNA 2 output negative
Mixer input 2 negative
RX pads ESD supply (3.3V)
108
109
110
111
112
113
114
115
116
117
RXIN3P
RXVCCTIA33
RXIN3N
RXVCCLPF33
RXVCCVGA33
RXOUTQP
RXOUTQN
RXOUTIN
RXOUTIP
GLOBAL GND
in
analogue supply
in
analogue supply
analogue supply
in/out
in/out
in/out
in/out
GLOBAL GND
RX3 (LNA3) input
RXTIA (RXVGA1) supply (3.3V)
RX3 (LNA3) input
RXLPF supply (3.3V)
RXVGA2 supply (3.3V)
RXVGA2 output / RX ADC input
RXVGA2 output / RX ADC input
RX VGA2 output / RX ADC input
RX VGA2 output / RX ADC input
Package paddle ground
PLL reference clock input (23MHz - 41 MHz)
Note
High Z when SEN=1
Minimum input level is 0.2Vpp. Both DC and AC coupling
supported.
Delta sigma digital core supply (1.8V)
Can be lowered down to 1.8V to support LV signalling
Connect to ground
Connect to ground
Connect to ground
Connect to ground
Table 12: Pin descriptions (continued)
LMS6002D
14
© Copyright Lime Microsystems
LMS6002D - Multi-band Multi-standard
Transceiver with Integrated Dual DACs and ADCs
TYPICAL APPLICATION
Typical application circuit of LMS6002D is given in Figure 19. Note that
only RF part is shown. It is recommended all unused pins to be
grounded, digital test pins should be left open while RF pins should
be connected as in Figure 19. As shown, RF ports are matched for
UMTS bands I and V while TXOUT2 and RXIN3 are broadband
matched. Refer to “LMS6002D Reference Design and PCB Layout
Recommendations” for more details.
Figure 19: LMS6002D Typical Application Circuit Diagram – RF part
Lime Microsystems
Surrey Tech Centre Occam Road
The Surrey Research Park Guildford
Surrey, GU2 7YG
UNITED KINGDOM
Tel: +44 (0) 1428 653 335
Fax: +44 (0) 1483 683 481
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