Product Specifications
PART NO.:
VL470T2863A-E6S-I
REV: 1.0
General Information
1GB 128Mx64 DDR2 SDRAM NON-ECC UNBUFFERED SODIMM 200-PIN
Description
The VL470T2863A is a 128Mx64 DDR2 SDRAM high density SODIMM. This single rank memory module consists of
eight CMOS 128Mx8 bits with 8 banks DDR2 synchronous DRAMs in BGA packages and a 2K EEPROM in an 8-pin
TSSOP package. This module is a 200-pin small-outline dual in-line memory module and is intended for mounting
into an edge connector socket. Decoupling capacitors are mounted on the printed circuit board for each DDR2
SDRAM.
Features
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Pin Description
200-pin, small-outline dual in-line memory module (SODIMM)
JEDEC pin out
Fast data transfer rate: PC2-5300
VDD = VDDQ = 1.8V +/-0.1V
JEDEC standard 1.8V (SSTL_18 compatible)
VDDSPD = 1.7V to 3.6V
Differential data strobe (DQS, DQS# ) option
Differential clock inputs (CK, CK#)
Four-bit pre-fetch architecture
DLL aligns DQ and DQS transition with CK
Nominal and dynamic on-die termination (ODT)
Programmable CAS# latency: 5 (DDR2-667)
Write latency = Read latency - 1 tCK
Eight internal component banks for concurrent operation
Programmable burst; length (4, 8)
Adjustable data-output drive strength
Auto & self refresh, (8K/64ms refresh)
Serial presence detect (SPD) with EEPROM
Gold edge contacts
Lead-free, RoHS compliant
PCB: Height 30.00mm (1.181”), double sided component
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Industrial temperature (TOPER): -40 C to +95 C (module screening using
commercial DRAM)
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Pin Name
Function
A0~A13
Address Inputs
A10/AP
Address Input/ Autoprecharge
BA0~BA2
Bank Address Inputs
DQ0~DQ63
Data Input/Output
DQS0~DQS7
Data Strobes
DQS0#~DQS7#
Data Strobes Complement
DM0~DM7
Data Masks
CK0, CK0#,
CK1, CK1#
Clock Inputs
ODT0
On-die Termination Control
CKE0
Clock Enables
CS0#
Chip Selects
RAS#
Row Address Strobes
CAS#
Column Address Strobes
WE#
Write Enable
VDD
Voltage Supply
VSS
Ground
SA0~SA1
SPD Address
SDA
SPD Data Input/Output
SCL
SPD Clock Input
VDDSPD
SPD Voltage Supply
VREF
SSTL_18 Reference Voltage
NC
No Connect
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Notes: Double refresh rate is required when 85 C < TOPER
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