VL-MM7-1EBN

Product Specifications PART NO.: VL47B2863A-F8SE-I REV: 1.0 General Information 1GB 128Mx64 DDR3 SDRAM NON-ECC UNBUFFERED SODIMM 204-PIN Description The VL47B2863A is a 128Mx64 DDR3 SDRAM high density SODIMM. This single rank memory module consists of eight CMOS 128Mx8 bits with 8 banks DDR3 Synchronous DRAMs in BGA packages and a 2K EEPROM with thermal sensor in an 8-pin MLF package. This module is a 204-pin small-outline dual in-line memory module and is intended for mounting into an edge connector socket. Decoupling capacitors are mounted on the printed circuit board for each DDR3 SDRAM. Features • • • • • • • • • • • • • • • • • • • • • • • Pin Description 204-pin, small-outline dual in-line memory module (SODIMM) Fast data transfer rate: PC3-8500 VDD = VDDQ = 1.5V +/-0.075V JEDEC standard 1.5V +/-0.075V I/O (SSTL_15 compatible) VDDSPD = 3.0V to 3.6V Eight internal component banks for concurrent operation 8-bit pre-fetch architecture Bi-directional differential data-strobe Nominal and dynamic on-die termination (ODT) ZQ calibration support Programmable CAS# latency: 7 (DDR3-1066) Programmable burst; length (8) Average refresh period 7.8 us Asynchronous reset Fly-by topology On board terminated command, address, and control bus Serial presence detect (SPD) EEPROM with thermal sensor o o o Thermal sensor range: -40 C to +125 C (Max +/-3 C accuracy) JEDEC pinout Gold edge contacts Lead-free, RoHS compliant PCB: Height 30.00mm (1.181”), double sided component o o Industrial temperature (TOPER): -40 C to +95 C (module screening using commercial DRAM) o Order Information: VL47B2863A - F8 S E - I . OPERATING TEMPERATURE Industrial screening Function A0~A13 Address Inputs A10/AP Address Input/ Autoprecharge A12/BC# Address Input/ Burst Chop BA0~BA2 Bank Address Inputs DQ0~DQ63 Data Input/Output DQS0~DQS7 Data Strobes DQS0#~DQS7# Data Strobes Complement DM0~DM7 Data Masks CK0, CK0# Clock Input ODT0 On-die Termination Control CKE0 Clock Enables CS0# Chip Selects RAS# Row Address Strobes CAS# Column Address Strobes WE# Write Enable RESET# Register and SDRAM Control VDD Voltage Supply VSS Ground SA0~SA1 SPD Address SDA SPD Data Input/Output SCL SPD Clock Input EVENT# Temperature Event Output VREFCA Reference Voltage for CA VREFDQ Reference Voltage for DQ VDDSPD SPD Voltage Supply VTT Termination Voltage NC No Connect o Notes: Double refresh rate is required when 85 C < TOPER