FT25C08A-USR-T

FT25C08A DS Fremont Micro Devices SPI Serial EEPROM 8K (8-bit wide) FEATURES  Serial Peripheral Interface (SPI) Compatible  Supports SPI Modes 0 (0,0) and 3 (1,1)  Low voltage and low power operations FT25C08A VCC = 1.8V to 5.5V l  Data Sheet Describes Mode 0 Operation tia  20MHz clock rate (5V)  Maximum Standby current < 1µA (typically 0.02µA and 0.06µA @ 1.8V and 5.5V respectively)  Partial page write operation allowed (32 bytes page write mode)  Self-timed programming cycle (5 ms max)  Block Write Protection (Protect 1/4, 1/2, or Entire Array)  Write protect pin for hardware data protection  High reliability: typically 1,000,000 cycles endurance  100 years data retention  Industrial temperature range (-40℃to 85℃)  Standard 8-pin DIP/SOP/TSSOP Pb-free packages on fid en  C DESCRIPTION The FT25C08A is 8192 bits of serial Electrical Erasable and Programmable Read Only Memory, commonly known as EEPROM. They are organized as 1024 words of 8 bits (1 byte) each. The devices are fabricated with proprietary advanced CMOS process for low power and low voltage applications. These devices are D available in standard 8-lead DIP, 8-lead SOP and 8-lead TSSOP packages. The memory is accessed via a FM simple Serial Peripheral Interface (SPI) compatible serial bus. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. While the device is paused, transitions on its inputs will be ignored. Our extended VCC range (1.8V to 5.5V) devices enables wide spectrum of applications. © 2014 Fremont Micro Devices Inc. Confidential Rev0.80 DS25C08A - Page1 FT25C08A DS Fremont Micro Devices PIN CONFIGURATION Pin Name Pin Function Pin Name Pin Function CS Chip Select GND Ground SCL Serial Clock Input VCC Power Supply SI Serial Data Input WP Write Protest SO Serial Data Output HOLD Suspends Serial Input All these packaging types come in conventional or Pb-free certified. W P G N D 8 7 6 5 tia S O 1 2 3 4 V C C H O L D S C L S I en CS l FT25C08A fid 8 L D IP 8L SO P 8L TSSO P on Figure 1: Packaging Types ABSOLUTE MAXIMUM RATINGS C Industrial operating temperature………………………………………………………………………-40℃ to 85℃ Storage temperature…………………………………………………………………………………-50℃ to 125℃ Input voltage on any pin relative to ground……………………………………………………-0.3V to VCC + 0.3V D Maximum voltage……………………………………………………………………………………………………8V FM ESD protection on all pins……………………………………………………………………………………>2000V * Stresses exceed those listed under “Absolute Maximum Rating” may cause permanent damage to the device. Functional operation of the device at conditions beyond those listed in the specification is not guaranteed. Prolonged exposure to extreme conditions may affect device reliability or functionality. © 2014 Fremont Micro Devices Inc. Confidential Rev0.80 DS25C08A - Page2 FT25C08A DS Fremont Micro Devices Block Diagram VCC STATUS REGISTER GND MEMORY ARRAY ADDRESS DECODER tia l DATA REGISTER SI MODE DECODE LOGIC fid CS WP en OUTPUT BUFFER CLOCK GENERATOR SO on SCK HOLD FM D C Figure 2: Block Diagram © 2014 Fremont Micro Devices Inc. Confidential Rev0.80 DS25C08A - Page3 FT25C08A DS Fremont Micro Devices PIN DESCRIPTIONS (A) CHIP SELECT ( CS ) The FT25C08A is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state. (B) Serial Input (SI) The SI pin is used to transfer data into the device. It receives instructions, addresses, and data. Data is tia l latched on the rising edge of the serial clock. (C) Serial Output (SO) The SO pin is used to transfer data out of the FT25C08A. During a read cycle, data is shifted out on this pin en after the falling edge of the serial clock. (D) Serial Clock (SCK) The SCK is used to synchronize the communication between a master and the FT25C08A. Instructions, fid addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin is updated after the falling edge of the clock input. on (E) Write Protect ( WP ) This pin is used in conjunction with the WPEN bit in the status register to prohibit writes to the non-volatile bits in the status register. When WP is low and WPEN is high, writing to the non-volatile bits in the status C register is disabled. All other operations function normally. When WP is high, all functions, including writes to the non-volatile bits in the status register operate normally. If the WPEN bit is set, WP low during a status register write sequence will disable writing to the status register. If an internal write cycle has D already begun, WP going low will have no effect on the write. The WP pin function is blocked when the WPEN bit in the status register is low. This allows the user to install the FT25C08A in a system with WP FM pin grounded and still be able to write to the status register. The WP pin functions will be enabled when the WPEN bit is set high. (F) Hold ( HOLD ) The HOLD pin is used in conjunction with the CS pin to select the FT25C08A. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD ). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. MEMORY ORGANIZATION The FT25C08A devices have 32 pages respectively. Since each page has 32 bytes, random word addressing to FT25C08A will require 10 bits data word addresses respectively. © 2014 Fremont Micro Devices Inc. Confidential Rev0.80 DS25C08A - Page4 FT25C08A DS Fremont Micro Devices DEVICE OPERATION The FT25C08A utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in Table A. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low CS transition. Table A Instruction Set for the FT25C08A Instruction Format Operation WREN 0000 X110 Set Write Enable Latch WRDI 0000 X100 Reset Write Enable Latch RDSR 0000 X101 Read Status Register WRSR 0000 X001 Write Status Register READ 0000 X011 Read Data from Memory Array WRITE 0000 X010 Write Data to Memory Array (A) STATUS REGISTER OPERATION Table B Status Register Format Bit 6 Bit 5 Bit 4 Bit 3 WPEN X X X BP1 Bit2 Bit 1 Bit 0 BP0 WEN RDY fid Bit 7 en tia l Instruction Name on WRITE ENABLE (WREN): The device will power up in the write disable state when VCC is applied. All programming instructions must therefore be preceded by a Write Enable instruction. WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction C disables all programming modes. The WRDI instruction is independent of the status of the WP pin. READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to the status register. The READY/BUSY and Write Enable status of the device can be determined by the RDSR D instruction. Similarly, the block write protection bits indicate the extent of protection employed. These bits are set by using the WRSR instruction. FM Table C Status Register Bit Definition Bit Bit 0 ( RDY ) Bit 1 (WEN) Definition Bit 0 = “0” ( RDY ) indicates the device is READY. Bit 0 = “1” indicates the write cycle is in progress. Bit 1= “0” indicates the device is not WRITE ENABLED. Bit 1 = “1” indicates the device is write enabled. Bit 2 (BP0) See table D. Bit 3 (BP1) See table D. Bits 4-6 are “0”s when device is not in an internal write cycle. Bit 7 (WPEN) See table E. Bits 0-7 are “1” during an internal write cycle. © 2014 Fremont Micro Devices Inc. Confidential Rev0.80 DS25C08A - Page5 FT25C08A DS Fremont Micro Devices WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protection. The FT25C08A is divided into four array segments. One-quarter, one-half, or all of the memory segments can be protected. Any of the data within any selected segment will therefore be read only. The block write protection levels and corresponding status register control bits are shown in Table D. The three bits BP0, BP1, and WPEN are nonvolatile cells that have the same properties and functions as the regular memory cells. Table D Block Write Protect Bits Status Register Bits 0 0 0 None 1(1/4) 0 1 0300-03FF 2(1/2) 1 0 0200-03FF 3(All) 1 1 0000-03FF en BP0 l Array Address Protected BP1 tia Level The WRSR instruction also allows the user to enable or disable the write protect ( WP ) pin through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and fid the WPEN bit is “1”. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is “0”. When the device is hardware write protected, writes to the status register, including the block protect bits and the WPEN bit, and the block-protected sections in the memory array are disabled. Writes on are only allowed to sections of the memory that are not block-protected. NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to “0” as long as the WP pin is held low. WPEN C Table E WPEN Operation WEN X D 0 WP Protected Unprotected Status Register Blocks Blocks 0 Protected Protected Protected X 1 Protected Writeable Writeable 1 Low 0 Protected Protected Protected 1 Low 1 Protected Writeable Protected X High 0 Protected Protected Protected X High 1 Protected Writeable Writeable FM 0 (B) EEPROM OPERATION READ SEQUENCE (READ): Reading the FT25C08A via the serial output (SO) pin requires the following sequence. After the CS line is pulled low to select a device, the read op-code is transmitted via the SI line followed by the byte address to be read (A15−A0, see Table F). Upon completion, any data on the SI line will be ignored. The data (D7−D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be driven high after the data comes out. The read sequence can be continued since the byte address is automatically incremented and data will continue to be shifted out. When the highest address is reached, the address counter will roll over to the lowest address (0000h), © 2014 Fremont Micro Devices Inc. Confidential Rev0.80 DS25C08A - Page6 FT25C08A DS Fremont Micro Devices allowing the entire memory to be read in one continuous read cycle. WRITE SEQUENCE (WRITE): In order to program the FT25C08A, two separate instructions must be executed. First, the device must be write enabled via the WREN instruction. Then a Write (WRITE) instruction may be executed. Also, the address of the memory location(s) to be programmed must be outside the protected address field location selected by the block write protection level. During an internal write cycle, all commands will be ignored except the RDSR instruction. A Write instruction requires the following sequence. After the CS line is pulled low to select the device, the WRITE op-code is transmitted via the SI line followed by the byte address (A15−A0) and the data (D7–D0) l to be programmed (See Table F). Programming will start after the CS pin is brought high. The low-to-high tia transition of the CS pin must occur during the SCK low-time immediately after clocking in the D0 (LSB) data bit. The FT25C08A is capable of a 32-byte page write operation. After each byte of data is received, the five en low-order address bits are internally incremented by one; the high order bits of the address will remain constant. If more than 32 bytes of data are transmitted, the address counter will roll over and the previously written data will be overwritten. The FT25C08A is automatically returned to the write disable state at the fid completion of a write cycle. NOTE: If the device is not write enabled (WREN), the device will ignore the write instruction and will return on to the standby state, when CS is brought high. A new CS falling edge is required to reinitiate the serial communication. The READY/BUSY status of the device can be determined by initiating a read status register (RDSR) instruction. If Bit 0 = “1”, the write cycle is still in progress. If Bit 0 = “0”, the write cycle has ended. Only the Table F Address Key C RDSR instruction is enabled during the write programming cycle. FT25C08A D Address A9-A0 Don’t Care Bits A15-A10 FM AN © 2014 Fremont Micro Devices Inc. Confidential Rev0.80 DS25C08A - Page7 FT25C08A DS Fremont Micro Devices CS tHDN tHDN SCL tHDS tHDS HOLD SO en Figure 3: HOLD Timing VIH VIL tCSS VIH SCL VIL tSU VIH SI tCS tCSH tWL on tWH fid CS tia tLZ l tHZ tH VALID IN VOH SO HI-Z C VIL tHO tV tDIS HI-Z FM D VOL Figure 4: Synchronous Data Timing (for Mode 0) CS SCL SI SO WREN INST HI-Z Figure 5: WREN Timing © 2014 Fremont Micro Devices Inc. Confidential Rev0.80 DS25C08A - Page8 FT25C08A DS Fremont Micro Devices CS SCL SI WRDI INST HI-Z SO tia CS 0 1 2 3 4 5 6 7 H I-Z SO 9 10 11 fid R D S R IN S T SI 8 12 13 14 15 2 1 0 en SCL l Figure 6: WRDI Timing 7 6 5 4 3 MSB CS 1 2 SI 4 5 6 7 8 9 10 11 12 13 14 15 DATA IN 7 3 2 D WRSR INST HI-Z FM SO 3 C 0 SCL on Figure 7: RDSR Timing Figure 8: WRSR Timing CS SCL 0 1 2 3 4 5 6 7 8 9 15 14 22 23 24 25 26 27 7 6 5 4 28 29 30 31 1 0 Byte Address SI SO READ INST 1 0 DATA OUT HI-Z 3 2 MSB Figure 9: READ Timing © 2014 Fremont Micro Devices Inc. Confidential Rev0.80 DS25C08A - Page9 FT25C08A DS Fremont Micro Devices CS SCL 0 1 2 3 4 5 6 7 8 9 15 14 22 23 24 25 26 27 0 7 6 5 4 WRITE INST 29 30 31 1 0 DATA IN Byte Address SI 28 1 3 2 HI-Z SO tia l Figure 10: WRITE Timing en AC CHARACTERISTICS Applicable over recommended operating range from: TAI =-40℃ to +85℃，VCC = As Specified, CL= 1 TTL Gate and 30 pF (unless otherwise noted) FT25C08A Parameter fid Symbol 1.8-2.7 V Min Clock frequency, SCK tRI Input Rise Time tFI Input Fall Time tWH SCK High Time tWL SCK Low Time tCS Min 5 Max 4.5-5.5 V Min Unit Max 10 20 MHz 2 2 2 µs 2 2 2 µs on fSCK Max 2.7-4.5 V 40 20 ns 80 40 20 ns CS High Time 100 50 25 ns tCSS CS Setup Time 100 50 25 ns tCSH CS Hold Time 100 50 25 ns tSU Data In Setup Time 20 10 5 ns tH Data In Hold Time 20 10 5 ns tHD HOLD Setup Time 20 10 5 ns tCD HOLD Hold Time 20 10 5 ns tV Output Valid 0 tHO Output Hold Time 0 tLZ HOLD to Output Low Z 0 tHZ HOLD to Output High Z 200 tDIS Output Disable Time tWC Write Cycle Time FM D C 80 © 2014 Fremont Micro Devices Inc. 80 0 40 0 100 0 0 20 0 50 ns 25 ns 80 40 ns 200 80 40 ns 5 5 5 ms Confidential Rev0.80 0 ns DS25C08A - Page10 FT25C08A DS Fremont Micro Devices DC CHARACTERISTICS Applicable over recommended operating range from:TAI =-40℃ to +85℃，VCC = +1.8V to +5.5V(unless otherwise noted) Symbol Parameter Test Conditions Min Typical Max Unit VCC1 Supply Voltage 1.8 5.5 V VCC2 Supply Voltage 2.7 5.5 V VCC3 Supply Voltage 4.5 5.5 V ICC1 Supply Current 10.0 mA ICC2 Supply Current ICC3 Supply Current ISB1 Standby current VCC = 1.8V, CS = VCC ISB2 Standby current VCC = 2.7V, CS = VCC ISB3 Standby current VCC = 5.0V, CS = VCC IIL Input leakage IOL Output leakage VIL (1) Input low level VIH(1) Input high level VOL1 Output low level VOH1 Output High level VOL2 Output low level 1.8V≤VCC≤3.6V, IOL = 0.15mA VOH2 Output High level 1.8V≤VCC≤3.6V, IOH =-100uA VCC=5.0V @ 20MHz, SO=Open, 7.5 VCC=5.0V @ 20MHz, SO=Open, tia l Read 4.0 10.0 mA 4.0 6.0 mA 1.0 µA 1.0 µA 1.0 µA VIN = VCC or VSS 3.0 µA VIN = VCC or VSS 3.0 µA -0.6 VCC 0.3 V VCC 0.7 VCC  0.5 V 0.4 V 0.2 V Read, Write on fid Read, Write en VCC=5.0V @ 5MHz, SO=Open, 3.6V≤VCC≤5.5V, IOL = 3.0mA C 3.6V≤VCC≤5.5V, IOH =-1.6mA 0.07 VCC  VCC  FM D Notes:1. VIL min and VIH max are reference only and are not tested. © 2014 Fremont Micro Devices Inc. Confidential Rev0.80 DS25C08A - Page11 FT25C08A DS Fremont Micro Devices ORDERING INFORMATION: FT25C08A - X X X - X Circuit Type Packaging B: Tube T: Tape and Reel HSF U: -40℃-85℃ R: RoHS l Temp. Range tia G: Green Package D: DIP8 S: SOP8 Package Temperature Range -40℃-85℃ Vcc 1.8V-5.5V HSF Packaging Ordering Code RoHS Tube FT25C08A-UDR-B Green Tube FT25C08A-UDG-B Tube FT25C08A-USR-B Tape and Reel FT25C08A-USR-T Tube FT25C08A-USG-B Tape and Reel FT25C08A-USG-T Tube FT25C08A-UTR-B Tape and Reel FT25C08A-UTR-T Tube FT25C08A-UTG-B Tape and Reel FT25C08A-UTG-T on DIP8 fid Density en T: TSSOP8 RoHS SOP8 1.8V-5.5V Green C 8kbits -40℃-85℃ -40℃-85℃ 1.8V-5.5V Green FM D TSSOP8 RoHS © 2014 Fremont Micro Devices Inc. Confidential Rev0.80 DS25C08A - Page12 FT25C08A DS Fremont Micro Devices fid en tia l DIP8 PACKAGE OUTLINE DIMENSIONS Min on Dimensions In Millimeters Symbol 3.710 A1 0.510 A2 B C A Max Min Max 4.310 0.146 0.170 0.020 3.200 3.600 0.126 0.142 0.380 0.570 0.015 0.022 1.524（BSC） D B1 Dimensions In Inches 0.060（BSC） 0.204 0.360 0.008 0.014 D 9.000 9.400 0.354 0.370 E 6.200 6.600 0.244 0.260 E1 7.320 7.920 0.288 0.312 FM C e 2.540 (BSC) 0.100（BSC） L 3.000 3.600 0.118 0.142 E2 8.400 9.000 0.331 0.354 © 2014 Fremont Micro Devices Inc. Confidential Rev0.80 DS25C08A - Page13 FT25C08A DS Fremont Micro Devices C on fid en tia l SOP8 PACKAGE OUTLINE DIMENSIONS Dimensions In Millimeters D Symbol Dimensions In Inches Max Min Max A 1.350 1.750 0.053 0.069 A1 0.100 0.250 0.004 0.010 A2 1.350 1.550 0.053 0.061 b 0.330 0.510 0.013 0.020 c 0.170 0.250 0.006 0.010 D 4.700 5.100 0.185 0.200 E 3.800 4.000 0.150 0.157 E1 5.800 6.200 0.228 0.244 FM Min e 1.270 (BSC) 0.050 (BSC) L 0.400 1.270 0.016 0.050 θ 0° 8° 0° 8° © 2014 Fremont Micro Devices Inc. Confidential Rev0.80 DS25C08A - Page14 FT25C08A DS Fremont Micro Devices Dimensions In Millimeters Dimensions In Inches Max Min Max D 2.900 3.100 0.114 0.122 E 4.300 4.500 0.169 0.177 b 0.190 0.300 0.007 0.012 c 0.090 0.200 0.004 0.008 E1 6.250 6.550 0.246 0.258 FM Min D Symbol C on fid en tia l TSSOP8 PACKAGE OUTLINE DIMENSIONS A 1.100 0.043 A2 0.800 1.000 0.031 0.039 A1 0.020 0.150 0.001 0.006 e L 0.65 (BSC) 0.500 H θ 0.026 (BSC) 0.700 0.020 0.25 (TYP) 1° © 2014 Fremont Micro Devices Inc. 0.028 0.01 (TYP) 7° 1° Confidential Rev0.80 7° DS25C08A - Page15 FT25C08A DS Fremont Micro Devices Fremont Micro Devices (SZ) Limited #5-8, 10/F, Changhong Building, Ke-Ji Nan 12 Road, Nanshan District, Shenzhen, Guangdong 518057 Tel: (86 755) 86117811 Fax: (86 755) 86117810 Fremont Micro Devices (Hong Kong) Limited l #16, 16/F, Blk B, Veristrong Industrial Centre, 34-36 Au Pui Wan Street, Fotan, Shatin, Hong Kong tia Tel: (852) 27811186 en Fax: (852) 27811144 Fremont Micro Devices (USA), Inc. 42982 Osgood Road Fremont, CA 94539 fid Tel: (1-510) 668-1321 on Fax: (1-510) 226-9918 FM D C Web Site: http://www.fremontmicro.com/ * Information furnished is believed to be accurate and reliable. However, Fremont Micro Devices, Incorporated (BVI) assumes no responsibility for the consequences of use of such information or for any infringement of patents of other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of Fremont Micro Devices, Incorporated (BVI). Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. Fremont Micro Devices, Incorporated (BVI) products are not authorized for use as critical components in life support devices or systems without express written approval of Fremont Micro Devices, Incorporated (BVI). The FMD logo is a registered trademark of Fremont Micro Devices, Incorporated (BVI). All other names are the property of their respective owners. © 2014 Fremont Micro Devices Inc. Confidential Rev0.80 DS25C08A - Page16