M480
Arm® Cortex® -M
32-bit Microcontroller
NuMicro® Family
M480 Series
Datasheet
Nuvoton is providing this document only for reference purposes of NuMicro® microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
May 08, 2020
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The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
M480
TABLE OF CONTENTS
1 GENERAL DESCRIPTION............................................................................. 16
2 FEATURES .................................................................................................... 17
3 PARTS INFORMATION ................................................................................. 31
3.1 Package Type .............................................................................................................. 31
3.2 M480 Series Selection Guide .................................................................................... 32
3.2.1 M481 Base Series (M481xIDAE) ................................................................................. 32
3.2.2 M481 Base Series (M481xGCAE / M481xE8AE) ...................................................... 33
3.2.3 M482 USB FS OTG Series (M482xIDAE) .................................................................. 34
3.2.4 M482 USB FS OTG Series (M482xGCAE / M482xE8AE) ....................................... 35
3.2.5 M483 CAN Series (M483xIDAE) .................................................................................. 36
3.2.6 M483 CAN Series (M483xGCAE / M483xE8AE) ...................................................... 37
3.2.7 M484 USB HS OTG Series ........................................................................................... 38
3.2.8 M485 Crypto Series ....................................................................................................... 39
3.2.9 M487 Ethernet Series .................................................................................................... 40
3.3 M480 Selection Code.................................................................................................. 41
4 PIN CONFIGURATION .................................................................................. 42
4.1 Pin Configuration ......................................................................................................... 42
4.1.1 QFN-33 Pin Diagram ..................................................................................................... 42
4.1.2 LQFP-48 Pin Diagram (0/1 USB FS) ........................................................................... 43
4.1.3 LQFP-64 Pin Diagram (0/1 USB FS) ........................................................................... 44
4.1.4 LQFP-64 Pin Diagram (0/1 USB FS with VBAT) .......................................................... 45
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4.1.5 LQFP-64 Pin Diagram (1 USB HS) .............................................................................. 46
4.1.6 LQFP-64 Pin Diagram (USB FS + USB HS) .............................................................. 47
4.1.7 LQFP-128 Pin Diagram (1 USB FS) ............................................................................ 48
4.1.8 LQFP-128 Pin Diagram (1 USB FS with VBAT) ........................................................... 49
4.1.9 LQFP-128 Pin Diagram (USB FS + USB HS) ............................................................ 50
4.1.10 LQFP-128 Pin Diagram (USB FS + USB HS) ............................................................ 51
4.1.11 LQFP-144 Pin Diagram ................................................................................................. 52
4.2 M48xxIDAE Pin Description ....................................................................................... 53
4.2.1 M481 Series Pin Description ........................................................................................ 53
4.2.2 M482 Series Pin Description ........................................................................................ 70
4.2.3 M483 Series Pin Description ........................................................................................ 99
4.2.4 M484 Series Pin Description ......................................................................................127
4.2.5 M485 Series Pin Description ......................................................................................155
4.2.6 M487 Series Pin Description ......................................................................................183
4.3 M48xxE8AE/M48xxGCAE Pin Description ............................................................ 215
4.3.1 M481 Series Pin Description ......................................................................................215
4.3.2 M482 Series Pin Description ......................................................................................232
4.3.3 M483 Series Pin Description ......................................................................................261
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4.4 M487KMCAN Pin Description ................................................................................. 289
5 BLOCK DIAGRAM ....................................................................................... 317
5.1 M480 Block Diagram................................................................................................. 317
6 FUNCTIONAL DESCRIPTION ..................................................................... 319
6.1 Arm® Cortex®-M4F Core ........................................................................................... 319
6.2 System Manager........................................................................................................ 322
6.2.1 Overview ........................................................................................................................322
6.2.2 System Reset ................................................................................................................322
6.2.3 System Power Distribution ..........................................................................................328
6.2.4 Power Modes and Wake-up Sources ........................................................................330
6.2.5 Power Modes and Power Level Transition ...............................................................334
6.2.6 System Memory Map ...................................................................................................335
6.2.7 SRAM Memory Orginization .......................................................................................338
6.2.8 Bus Matrix ......................................................................................................................341
6.2.9 HIRC Auto Trim .............................................................................................................341
6.2.10 Register Lock Control ..................................................................................................342
6.2.11 System Timer (SysTick) ...............................................................................................345
6.2.12 Nested Vectored Interrupt Controller (NVIC) ............................................................346
6.3 Clock Controller ......................................................................................................... 347
6.3.1 Overview ........................................................................................................................347
6.3.2 Clock Generator ............................................................................................................350
6.3.3 System Clock and SysTick Clock ...............................................................................351
6.3.4 Peripherals Clock .........................................................................................................352
6.3.6 Clock Output..................................................................................................................353
6.3.7 USB Clock Source ........................................................................................................354
6.4 True Random Number Generator (TRNG) ............................................................ 355
6.4.1 Overview ........................................................................................................................355
6.4.2 Features .........................................................................................................................355
6.5 Flash Memeory Controller (FMC) ........................................................................... 356
6.5.1 Overview ........................................................................................................................356
6.5.2 Features .........................................................................................................................356
6.6 General Purpose I/O (GPIO) ................................................................................... 358
6.6.1 Overview ........................................................................................................................358
6.6.2 Features .........................................................................................................................358
6.7 PDMA Controller (PDMA) ......................................................................................... 359
6.7.1 Overview ........................................................................................................................359
6.7.2 Features .........................................................................................................................359
6.8 Timer Controller (TMR) ............................................................................................. 360
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6.3.5 Power-down Mode Clock ............................................................................................353
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6.8.1 Overview ........................................................................................................................360
6.8.2 Features .........................................................................................................................360
6.9 Watchdog Timer (WDT) ............................................................................................ 362
6.9.1 Overview ........................................................................................................................362
6.9.2 Features .........................................................................................................................362
6.10
Window Watchdog Timer (WWDT) ................................................................... 363
6.10.1 Overview ........................................................................................................................363
6.10.2 Features .........................................................................................................................363
6.11
Real Time Clock (RTC) ....................................................................................... 364
6.11.1 Overview ........................................................................................................................364
6.11.2 Features .........................................................................................................................364
6.12
EPWM Generator and Capture Timer (EPWM) .............................................. 365
6.12.1 Overview ........................................................................................................................365
6.12.2 Features .........................................................................................................................365
6.13
Basic PWM Generator and Capture Timer (BPWM) ...................................... 367
6.13.1 Overview ........................................................................................................................367
6.13.2 Features .........................................................................................................................367
6.14
Quadrature Encoder Interface (QEI) ................................................................ 368
6.14.1 Overview ........................................................................................................................368
6.14.2 Features .........................................................................................................................368
6.15
Enhanced Input Capture Timer (ECAP) ........................................................... 369
6.15.1 Overview ........................................................................................................................369
6.15.2 Features .........................................................................................................................369
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6.16
UART Interface Controller (UART).................................................................... 370
6.16.1 Overview ........................................................................................................................370
6.16.2 Features .........................................................................................................................370
6.17
Ethernet MAC Controller (EMAC) ..................................................................... 372
6.17.1 Overview ........................................................................................................................372
6.17.2 Features .........................................................................................................................372
6.18
Smart Card Host Interface (SC) ........................................................................ 373
6.18.1 Overview ........................................................................................................................373
6.18.2 Features .........................................................................................................................373
6.19
I2S Controller (I2S) ............................................................................................... 374
6.19.1 Overview ........................................................................................................................374
6.19.2 Features .........................................................................................................................374
6.20
Serial Peripheral Interface (SPI)........................................................................ 375
6.20.1 Overview ........................................................................................................................375
6.20.2 Features .........................................................................................................................375
6.21
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6.21.1 Overview ........................................................................................................................376
6.21.2 Features .........................................................................................................................376
6.22
SPI Synchronous Serial Interface Controller (SPI Master mode) ................ 377
6.22.1 Overview ........................................................................................................................377
6.22.2 Features .........................................................................................................................377
6.23
I2C Serial Interface Controller (I2C) ................................................................... 378
6.23.1 Overview ........................................................................................................................378
6.23.2 Features .........................................................................................................................378
6.24
USCI - Universal Serial Control Interface Controller (USCI)......................... 379
6.24.1 Overview ........................................................................................................................379
6.24.2 Features .........................................................................................................................379
6.25
USCI – UART Mode ............................................................................................ 380
6.25.1 Overview ........................................................................................................................380
6.25.2 Features .........................................................................................................................380
6.26
USCI - SPI Mode ................................................................................................. 381
6.26.1 Overview ........................................................................................................................381
6.26.2 Features .........................................................................................................................381
6.27
USCI - I2C Mode .................................................................................................. 383
6.27.1 Overview ........................................................................................................................383
6.27.2 Features .........................................................................................................................383
6.28
Controller Area Network (CAN) ......................................................................... 384
6.28.1 Overview ........................................................................................................................384
6.28.2 Features .........................................................................................................................384
Secure Digital Host Controller (SDH) ............................................................... 385
6.29.1 Overview ........................................................................................................................385
6.29.2 Features .........................................................................................................................385
6.30
External Bus Interface (EBI) .............................................................................. 386
6.30.1 Overview ........................................................................................................................386
6.30.2 Features .........................................................................................................................386
6.31
USB 1.1 Device Controller (USBD) .................................................................. 387
6.31.1 Overview ........................................................................................................................387
6.31.2 Features .........................................................................................................................387
6.32
High Speed USB 2.0 Device Controller (HSUSBD) ....................................... 388
6.32.1 Overview ........................................................................................................................388
6.32.2 Features .........................................................................................................................388
6.33
USB 1.1 Host Controller (USBH) ...................................................................... 389
6.33.1 Overview ........................................................................................................................389
6.33.2 Features .........................................................................................................................389
6.34
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USB 2.0 Host Controller (USBH) ...................................................................... 390
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6.29
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6.34.1 Overview ........................................................................................................................390
6.34.2 Features .........................................................................................................................390
6.35
USB On-The-Go (OTG) ...................................................................................... 391
6.35.1 Overview ........................................................................................................................391
6.35.2 Features .........................................................................................................................391
6.36
High Speed USB On-The-Go (HSOTG) .......................................................... 392
6.36.1 Overview ........................................................................................................................392
6.36.2 Features .........................................................................................................................392
6.37
CRC Controller (CRC) ........................................................................................ 393
6.37.1 Overview ........................................................................................................................393
6.37.2 Features .........................................................................................................................393
6.38
Cryptographic Accelerator (CRYPTO) .............................................................. 394
6.38.1 Overview ........................................................................................................................394
6.38.2 Features .........................................................................................................................394
6.39
Camera Capture Interface Controller (CCAP) ................................................ 396
6.39.1 Overview ........................................................................................................................396
6.39.2 Features .........................................................................................................................396
6.40
Enhanced 12-bit Analog-to-Digital Converter (EADC) ................................... 397
6.40.1 Overview ........................................................................................................................397
6.40.2 Features .........................................................................................................................397
6.41
Digital to Analog Converter (DAC) .................................................................... 399
6.41.1 Overview ........................................................................................................................399
6.41.2 Features .........................................................................................................................399
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6.42
Analog Comparator Controller (ACMP)............................................................ 400
6.42.1 Overview ........................................................................................................................400
6.42.2 Features .........................................................................................................................400
6.43
OP Amplifier (OPA) .............................................................................................. 401
6.43.1 Overview ........................................................................................................................401
6.43.2 Features .........................................................................................................................401
6.44
Peripherals Interconnection ............................................................................... 402
6.44.1 Overview ........................................................................................................................402
6.44.2 Peripherals Interconnect Matrix Table .......................................................................402
6.44.3 Functional Description .................................................................................................402
7 APPLICATION CIRCUIT .............................................................................. 406
7.1 Power Supply Scheme with External VREF............................................................. 406
7.2 Power Supply Scheme with Internal VREF .............................................................. 407
7.3 Power Supply Scheme with VREF and External RTC with Battery Power ......... 408
7.4 Power Supply Scheme with VREF and Internal RTC with Battery Power........... 409
7.5 Peripheral Application Scheme ............................................................................... 410
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8 ELECTRICAL CHARACTERISTICS FOR M48XID/M487KMCAN .............. 412
8.1 Absolute Maximum Ratings ..................................................................................... 412
8.1.1 Voltage Characteristics ................................................................................................412
8.1.2 Current Characteristics ................................................................................................412
8.1.3 Thermal Characteristics...............................................................................................412
8.1.4 EMC Characteristics .....................................................................................................413
8.2 General Operating Conditions ................................................................................. 414
8.3 DC Electrical Characteristics ................................................................................... 415
8.3.1 Typical Current Consumption(M487xID) ...................................................................415
8.3.2 Typical Current Consumption(M487KMCAN) ..........................................................422
8.3.3 On-chip Peripheral Current Consumption .................................................................426
8.3.4 Wakeup Time ................................................................................................................427
8.3.5 PIN DC Characteristics ................................................................................................428
8.4 AC Electrical Characteristics ................................................................................... 430
8.4.1 External 4~24 MHz High Speed Crystal (HXT) Characteristics ............................430
8.4.2 External 4~24 MHz High Speed Clock Input (OSC) Characteristics ....................431
8.4.3 External 32.768 kHz Low Speed Crystal (LXT) Characteristics ............................432
8.4.4 External 32.768 kHz Low Speed Clock Input (OSC) Characteristics ...................433
8.4.5 12 MHz Internal High Speed RC Oscillator (HIRC) .................................................433
8.4.6 10 kHz Internal Low Speed RC Oscillator (LIRC)....................................................434
8.4.7 PLL Characteristics ......................................................................................................434
8.4.8 PIN AC Characteristics ................................................................................................434
8.5 Analog Electrical Characteristics ............................................................................ 436
8.5.2 Low-Voltage Reset .......................................................................................................436
8.5.3 Brown-out Detector ......................................................................................................436
8.5.4 Power-on Reset ............................................................................................................437
8.5.5 Internal Voltage Reference .........................................................................................437
8.5.6 12-bit ADC .....................................................................................................................438
8.5.7 Temperature Sensor.....................................................................................................441
8.5.8 Digital to Analog Converter (DAC) .............................................................................441
8.5.9 Analog Comparator Controller (ACMP) .....................................................................443
8.5.10 OP Amplifier (OPA) .......................................................................................................444
8.6 Flash DC Electrical Characteristic .......................................................................... 445
8.7 I2C Dynamic Characteristics .................................................................................... 446
8.8 SPI Dynamic Characteristics ................................................................................... 447
8.9 I2S Dynamic Characteristics .................................................................................... 450
8.10
USCI - I2C Dynamic Characteristics ................................................................. 452
8.11
USCI - SPI Dynamic Characteristics ................................................................ 453
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8.5.1 LDO ................................................................................................................................436
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8.12
USB Characteristics ............................................................................................ 456
8.12.1 USB Full-Speed ............................................................................................................456
8.12.2 USB Full-Speed PHY Characteristics........................................................................456
8.12.3 USB High-Speed Characteristics ...............................................................................456
8.13
Ethernet Characteristics ..................................................................................... 457
8.13.1 RMII Interface Timing ...................................................................................................457
8.13.2 Ethernet PHY Management Interface Timing ...........................................................457
8.14
SDIO Characteristics........................................................................................... 459
8.14.1 Default Mode Timing ....................................................................................................459
8.14.2 SDIO Dynamic Characteristics ...................................................................................459
8.15
SPI Flash Characteristics (M487KMCAN) ....................................................... 461
9 ELECTRICAL CHARACTERISTICS FOR M48XGC/M48XE8 ..................... 462
9.1 Absolute Maximum Ratings ..................................................................................... 462
9.1.1 Voltage Characteristics ................................................................................................462
9.1.2 Current Characteristics ................................................................................................462
9.1.3 Thermal Characteristics...............................................................................................464
9.1.4 EMC Characteristics ....................................................................................................465
9.1.5 Package Moisture Sensitivity(MSL) ...........................................................................466
9.1.6 Soldering Profile ...........................................................................................................467
9.2 General Operating Conditions ................................................................................. 468
9.3 DC Electrical Characteristics ................................................................................... 469
9.3.1 Supply Current Characteristics ...................................................................................469
9.3.2 On-Chip Peripheral Current Consumption ................................................................473
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9.3.3 Wakeup Time from Low-Power Modes .....................................................................474
9.3.4 I/O Current Injection Characteristics ..........................................................................476
9.3.5 I/O DC Characteristics .................................................................................................476
9.4 AC Electrical Characteristics ................................................................................... 478
9.4.1 48 MHz Internal High Speed RC Oscillator (HIRC48M) .........................................478
9.4.2 12 MHz Internal High Speed RC Oscillator (HIRC) .................................................479
9.4.3 10 kHz Internal Low Speed RC Oscillator (LIRC)....................................................480
9.4.4 External 4~24 MHz High Speed Crystal/Ceramic Resonator (HXT)
Characteristics .........................................................................................................................481
9.4.5 External 4~24 MHz High Speed Clock Input Signal Characteristics ....................483
9.4.6 External 32.768 kHz Low Speed Crystal/Ceramic Resonator (LXT)
Characteristics .........................................................................................................................484
9.4.7 External 32.768 kHz Low Speed Clock Input Signal Characteristics ...................485
9.4.8 PLL Characteristics ......................................................................................................486
9.4.9 I/O AC Characteristics .................................................................................................487
9.5 Analog Characteristics .............................................................................................. 490
9.5.1 LDO ................................................................................................................................490
9.5.2 Reset and Power Control Block Characteristics ......................................................490
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9.5.3 12-bit SAR ADC ............................................................................................................492
9.5.4 Temperature Sensor.....................................................................................................496
9.5.5 Analog Comparator Controller (ACMP) .....................................................................498
9.5.6 Digital to Analog Converter (DAC) .............................................................................499
9.5.7 Internal Voltage Reference .........................................................................................501
9.6 Communications Characteristics ............................................................................ 502
9.6.1 SPI Dynamic Characteristics ......................................................................................502
2
9.6.2 SPI - I S Dynamic Characteristics .............................................................................505
2
9.6.3 I S Dynamic Characteristics .......................................................................................507
2
9.6.4 I C Dynamic Characteristics .......................................................................................509
9.6.5 USB Characteristics .....................................................................................................510
9.6.6 SDIO Characteristics ...................................................................................................511
9.6.7 Camera Capture Interface (CCAP) Characteristics ................................................513
9.7 Flash DC Electrical Characteristics ........................................................................ 514
10 ABBREVIATIONS ........................................................................................ 515
10.1
Abbreviations ........................................................................................................ 515
11 PACKAGE DIMENSIONS ............................................................................ 517
11.1
QFN 33L (5x5x0.8 mm3 Pitch 0.5 mm)............................................................. 517
11.2
LQFP 48L (7x7x1.4 mm3 Footprint 2.0mm) ..................................................... 518
11.3
LQFP 64L (7x7x1.4 mm3 footprint 2.0 mm) ..................................................... 519
11.4
LQFP 128L (14x14x1.4 mm3 footprint 2.0 mm) .............................................. 520
11.5
LQFP 144L (20x20x1.4 mm3 footprint 2.0 mm) .............................................. 521
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12 REVISION HISTORY ................................................................................... 522
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LIST OF FIGURES
Figure 4.1-1 QFN-33 Pin Diagram (0/1 USB FS) ........................................................................... 42
Figure 4.1-2 LQFP-48 Pin Diagram (0/1 USB FS) ......................................................................... 43
Figure 4.1-3 LQFP-64 Pin Diagram (0/1 USB FS) ......................................................................... 44
Figure 4.1-4 LQFP-64 Pin Diagram (0/1 USB FS with VBAT) ......................................................... 45
Figure 4.1-5 LQFP-64 Pin Diagram (1 USB HS) ........................................................................... 46
Figure 4.1-6 LQFP-64 Pin Diagram (USB FS + USB HS) ............................................................. 47
Figure 4.1-7 LQFP-128 Pin Diagram (1 USB FS) .......................................................................... 48
Figure 4.1-8 LQFP-128 Pin Diagram (1 USB FS) .......................................................................... 49
Figure 4.1-9 LQFP-128 Pin Diagram (USB FS + USB HS) ........................................................... 50
Figure 4.1-10 LQFP-128 Pin Diagram (USB FS + USB HS) ......................................................... 51
Figure 4.1-11 LQFP-144 Pin Diagram ........................................................................................... 52
®
Figure 5.1-1 NuMicro M480 Block Diagram (M48xID) ............................................................... 317
®
Figure 5.1-2 NuMicro M480 Block Diagram (M487KMCAN)...................................................... 317
®
Figure 5.1-3 NuMicro M480 Block Diagram (M48xGC) ............................................................. 318
®
Figure 5.1-4 NuMicro M480 Block Diagram (M48xE8) .............................................................. 318
®
Figure 6.1-1 Cortex -M4F Block Diagram .................................................................................... 319
Figure 6.2-1 System Reset Sources ............................................................................................ 323
Figure 6.2-2 nRESET Reset Waveform ....................................................................................... 325
Figure 6.2-3 Power-on Reset (POR) Waveform .......................................................................... 325
Figure 6.2-4 Low Voltage Reset (LVR) Waveform ....................................................................... 326
Figure 6.2-5 Brown-out Detector (BOD) Waveform ..................................................................... 327
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®
Figure 6.2-6 NuMicro M480 Power Distribution Diagram ........................................................... 328
Figure 6.2-7 Power Mode State Machine .................................................................................... 331
®
Figure 6.2-8 NuMicro M480 Power Distribution Diagram ........................................................... 335
Figure 6.2-9 SRAM Block Diagram .............................................................................................. 338
Figure 6.2-10 SRAM Memory Organization ................................................................................. 340
®
Figure 6.2-11 NuMicro M480 Bus Matrix Diagram ..................................................................... 341
Figure 6.3-1 Clock Generator Global View Diagram (M48xID/M487KMCAN)............................. 348
Figure 6.3-2 Clock Generator Global View Diagram (M48xGC/M48xE8) .................................... 349
Figure 6.3-3 Clock Generator Block Diagram .............................................................................. 350
Figure 6.3-4 System Clock Block Diagrams ................................................................................ 351
Figure 6.3-5 HXT Stop Protect Procedure ................................................................................... 352
Figure 6.3-6 SysTick Clock Control Block Diagram ..................................................................... 352
Figure 6.3-7 Clock Output Block Diagram ................................................................................... 353
Figure 6.3-8 USB Clock Source (M48xID/M487KMCAN) ............................................................ 354
Figure 6.3-9 USB Clock Source (M48xGC/M48xE8) ................................................................... 354
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Figure 6.26-1 SPI Master Mode Application Block Diagram ........................................................ 381
Figure 6.26-2 SPI Slave Mode Application Block Diagram .......................................................... 381
2
Figure 6.27-1 I C Bus Timing ....................................................................................................... 383
Figure 8.3-1 Current Consumption Versus Temperature in Normal Run Mode, VDD = 3.3V , All
Peripherals Disabled, PLL Source From HIRC..................................................................... 416
Figure 8.3-2 Current Consumption Versus Temperature in Normal Run Mode, VDD = 3.3V , All
Peripherals Enabled, PLL Source From HIRC ..................................................................... 416
Figure 8.3-3 Current Consumption Versus Temperature in Normal Run Mode, VDD = 3.3V , All
Peripherals Disabled, PLL Source From HXT ...................................................................... 417
Figure 8.3-4 Current Consumption Versus Temperature in Normal Run Mode, VDD = 3.3V , All
Peripherals Enabled, PLL Source From HXT ....................................................................... 417
Figure 8.3-5 Current Consumption Versus Temperature in Idle Mode, VDD = 3.3V , All Peripherals
Disabled, PLL Source From HIRC ........................................................................................ 419
Figure 8.3-6 Current Consumption Versus Temperature in Idle Mode, VDD = 3.3V , All Peripherals
Enabled, PLL Source From HIRC ......................................................................................... 419
Figure 8.3-7 Current Consumption Versus Temperature in Idle Mode, VDD = 3.3V , All Peripherals
Disabled, PLL Source From HXT.......................................................................................... 420
Figure 8.3-8 Current Consumption Versus Temperature in Idle Mode, VDD = 3.3V , All Peripherals
Enabled, PLL Source From HXT .......................................................................................... 420
Figure 8.4-1 Typical Crystal Application Circuit ........................................................................... 431
Figure 8.4-2 Typical Crystal Application Circuit ........................................................................... 433
Figure 8.5-1 Power-up Ramp Condition ...................................................................................... 437
Figure 8.5-2 Typical Connection with Internal Voltage Reference ............................................... 438
2
Figure 8.7-1 I C Timing Diagram ................................................................................................. 446
Figure 8.8-2 SPI Slave Mode Timing Diagram ............................................................................ 449
2
Figure 8.9-1 I S Master Mode Timing Diagram............................................................................ 450
2
Figure 8.9-2 I S Slave Mode Timing Diagram.............................................................................. 451
2
Figure 8.10-1 I C Timing Diagram ............................................................................................... 452
Figure 8.11-1 SPI Master Mode Timing Diagram ........................................................................ 453
Figure 8.11-2 SPI Slave Mode Timing Diagram .......................................................................... 455
Figure 8.13-1 RMII Interface Timing Diagram .............................................................................. 457
Figure 8.13-2 Ethernet PHY Management Interface Timing Diagram ......................................... 458
Figure 8.14-1 SDIO Default Mode................................................................................................ 459
Figure 8.14-2 SDIO High-speed Mode ........................................................................................ 460
Figure 9.1-1 Soldering Profile From J-STD-020C ........................................................................ 467
Figure 9.4-1 Typical Crystal Application Circuit ........................................................................... 482
Figure 9.4-2 Typical 32.768 kHz Crystal Application Circuit ........................................................ 484
Figure 9.5-1 Power Ramp Up/Down Condition ............................................................................ 491
Figure 9.5-2 Typical Connection with Internal Voltage Reference ............................................... 501
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Figure 8.8-1 SPI Master Mode Timing Diagram .......................................................................... 447
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Figure 9.6-1 SPI Master Mode Timing Diagram .......................................................................... 502
Figure 9.6-2 SPI Slave Mode Timing Diagram ............................................................................ 504
2
Figure 9.6-3 I S Master Mode Timing Diagram............................................................................ 505
2
Figure 9.6-4 I S Slave Mode Timing Diagram.............................................................................. 506
2
Figure 9.6-5 I S Master Mode Timing Diagram............................................................................ 507
2
Figure 9.6-6 I S Slave Mode Timing Diagram.............................................................................. 508
2
Figure 9.6-7 I C Timing Diagram ................................................................................................. 509
Figure 9.6-8 SDIO Default Mode.................................................................................................. 511
Figure 9.6-9 SDIO High-speed Mode .......................................................................................... 512
Figure 9.6-10 Camera Capture Interface Timing Diagram........................................................... 513
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List of Tables
Table 6.2-1 Reset Value of Registers .......................................................................................... 324
Table 6.2-2 Power Mode Table .................................................................................................... 330
Table 6.2-3 Power Mode Difference Table .................................................................................. 331
Table 6.2-4 Power Mode Definition Table .................................................................................... 331
Table 6.2-5 Clocks in Power Modes ............................................................................................ 332
Table 6.2-6 Re-Entering Power-down Mode Condition ............................................................... 334
Table 6.2-7 Address Space Assignments for On-Chip Controllers .............................................. 338
Table 6.2-8 SRAM Organization .................................................................................................. 339
Table 6.5-1 FMC Features Comparison Table at Different Chip ................................................. 357
Table 6.13-1 BPWM Features Comparison Table ....................................................................... 367
Table 6.16-1 M480 Series UART Features .................................................................................. 371
Table 6.29-1 SDH Features Comparison Table ........................................................................... 385
Table 6.38-1 Crypto Features Comparison Table at Different Chip ............................................ 395
Table 6.40-1 EADC Features Comparison Table ........................................................................ 398
Table 6.44-1 Peripherals Interconnect Matrix table ..................................................................... 402
Table 8.1-1 Voltage Characteristics ............................................................................................. 412
Table 8.1-2 Current Characteristics ............................................................................................. 412
Table 8.1-3 Thermal Characteristics ............................................................................................ 413
Table 8.1-4 EMS Characteristics ................................................................................................. 413
Table 8.1-5 Electrical Characteristics........................................................................................... 413
Table 8.3-1 Current Consumption in Normal Run Mode.............................................................. 415
Table 8.3-3 Chip Current Consumption in Power-down Mode .................................................... 422
Table 8.3-4 Current Consumption in Normal Run Mode (Cache-on) .......................................... 422
Table 8.3-5 Current Consumption in Normal Run Mode (Cache-off) .......................................... 423
Table 8.3-6 Current Consumption in Idle Mode (Cache-on) ........................................................ 424
Table 8.3-7 Current Consumption in Idle Mode (Cache-off) ........................................................ 424
Table 8.3-8 Chip Current Consumption in Power-down Mode .................................................... 425
Table 8.3-9 Low-power Mode Wakeup Timings .......................................................................... 428
Table 8.3-10 PIN Input Characteristics ........................................................................................ 428
Table 8.3-11 PIN Output Characteristics ..................................................................................... 429
Table 8.3-12 nRESET PIN Characteristics .................................................................................. 429
Table 8.4-1 External 4~24 MHz High Speed Crystal (HXT) Oscillator ........................................ 431
Table 8.4-2 External 32.768 kHz Crystal ..................................................................................... 432
Table 8.4-3 I/O AC Characteristics .............................................................................................. 435
Table 9.1-1 Voltage Characteristics ............................................................................................. 462
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M480 SERIES DATASHEET
Table 8.3-2 Current Consumption in Idle Mode ........................................................................... 418
M480
Table 9.1-2 Current Characteristics ............................................................................................. 463
Table 9.1-3 Thermal Characteristics ............................................................................................ 464
Table 9.1-4 EMS Characteristics ................................................................................................. 465
Table 9.1-5 ESD Characteristics .................................................................................................. 465
Table 9.1-6 Electrical Characteristics........................................................................................... 465
Table 9.1-7 Package Moisture Sensitivity(MSL) .......................................................................... 466
Table 9.1-8 Soldering Profile ........................................................................................................ 467
Table 9.2-1 General Operating Conditions .................................................................................. 468
Table 9.3-1 Current Consumption in Normal Run Mode.............................................................. 469
Table 9.3-2 Current Consumption in Idle Mode ........................................................................... 470
Table 9.3-3 Chip Current Consumption in Power-down Mode .................................................... 472
Table 9.3-4 Peripheral Current Consumption .............................................................................. 474
Table 9.3-5 Low-power Mode Wake-up Timings ......................................................................... 475
Table 9.3-6 I/O Current Injection Characteristics ......................................................................... 476
Table 9.3-7 I/O Input Characteristics ........................................................................................... 476
Table 9.3-8 I/O Output Characteristics......................................................................................... 477
Table 9.3-9 nRESET Input Characteristics .................................................................................. 477
Table 9.4-148 MHz Internal High Speed RC Oscillator(HIRC) Characteristics ........................... 478
Table 9.4-2 12 MHz Internal High Speed RC Oscillator(HIRC) Characteristics .......................... 479
Table 9.4-3 10 kHz Internal Low Speed RC Oscillator(LIRC) Characteristics ............................. 480
Table 9.4-4 External 4~24 MHz High Speed Crystal (HXT) Oscillator ........................................ 481
Table 9.4-5 External 4~24 MHz High Speed Crystal Characteristics .......................................... 482
M480 SERIES DATASHEET
Table 9.4-6 External 4~24 MHz High Speed Clock Input Signal ................................................. 483
Table 9.4-7 External 32.768 kHz Low Speed Crystal (LXT) Oscillator ........................................ 484
Table 9.4-8 External 32.768 kHz Low Speed Crystal Characteristics ......................................... 484
Table 9.4-9 External 32.768 kHz Low Speed Clock Input Signal ................................................ 485
Table 9.4-10 PLL Characteristics ................................................................................................. 486
Table 9.4-11 I/O AC Characteristics ............................................................................................ 489
Table 9.5-1 Reset and Power Control Unit .................................................................................. 491
Table 9.5-2 ACMP Characteristics ............................................................................................... 498
Table 9.6-1 SPI Master Mode Characteristics ............................................................................. 502
Table 9.6-2 SPI Slave Mode Characteristics ............................................................................... 503
2
Table 9.6-3 I S Characteristics .................................................................................................... 505
2
Table 9.6-4 I S Characteristics .................................................................................................... 507
2
Table 9.6-5 I C Characteristics .................................................................................................... 509
Table 9.6-6 USB Full-Speed Characteristics ............................................................................... 510
Table 9.6-7 USB Full-Speed PHY Characteristics ....................................................................... 510
May 08, 2020
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M480
Table 9.6-8 SDIO Default Mode Timing ....................................................................................... 511
Table 9.6-9 SDIO Dynamic Characteristics ................................................................................. 512
Table 9.6-10 Camera Capture Interface Timing .......................................................................... 513
Table 10.1-1 List of Abbreviations................................................................................................ 516
M480 SERIES DATASHEET
May 08, 2020
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M480
1
GENERAL DESCRIPTION
®
®
®
The NuMicro M480 series microcontroller is embedded with Arm Cortex -M4F core with secure boot
and hardware cryptography which supports DSP instruction and integrated floating-point unit. The
M480 series consists of six sub-series according to characteristics and applications. The M480 series
supports Flash size up to 2560 KB and SRAM size up to 160 KB. The operating frequency is up to 192
MHz with 175/130 µA/ MHz dynamic power consumption and the standby current can be lower to 1
µA.
The M480 series supports secure boot functionality, which provides a constant digital signature of
system software for identification during boot up to protect the integrity of Flash content from attack.
The embedded hardware cryptography engine provides fast and easy encryption, decryption, ID
certification, private key and public key features. Additionally, the M480 series supports 10/100Mbps
Ethernet RMII, high-speed USB 2.0 OTG, dual 12-bit 5 MSPS SAR ADC, camera interface and
versatile peripherals, eligible for IoT, industrial automation, sensor network, automotive device, RC
aircraft, smart home, network gateway and consumer electronics.
®
The NuMicro M480 series consists of six sub-series:
®
M480 SERIES DATASHEET
NuMicro M481 Base series: high performance, low power consumption, versatile high speed
UART/SPI/I2C/PWM peripherals, eligible for data collector.
NuMicro M482 USB FS OTG series: Integrated USB 2.0 full speed interface with on-chip OTG
PHY, eligible for gaming or PC accessories.
NuMicro M483 CAN series: Integrated 2 or 3 sets of CAN 2.0B interfaces, 2 sets of USB 2.0
interfaces, dual ADC and up to 9 sets of UART interfaces, eligible for IoV and industrial control
NuMicro M484 USB HS OTG series: Integrated 2 sets of USB 2.0 interface with op-chip full
speed and high-speed OTG PHY, eligible for data concentrator of USB sensor.
NuMicro M485 Crypto series: Integrated hardware cryptography engine and random number
generator for randomly fabricating the key for data encryption/decryption and certification, eligible
for fingerprint module, smart payment and secure USB device.
NuMicro M487 Ethernet series: Integrated 10/100Mbps Ethernet MAC with industrial standard
RMII interface for quickly implementing the network connection, eligible for industrial IoT gateway,
UART-to-Ethernet converter, industrial automation, smart home, etc.
®
®
®
®
®
Series
USB Full Speed
USB High Speed
CAN 2.0B
√
Cryptography
Ethernet
M481
M482
√
M483
√
√
M484
√
√
M485
√
√
M487
√
√
May 08, 2020
√
√
Page 16 of 523
√
√
Rev 3.00
M480
2
FEATURES
Core and System
®
®
Arm Cortex -M4F core, running up to 192 MHz
– 192 MHz at1.8V-3.6V; 160 MHz at 1.62V
Built-in Memory Protection Unit (MPU)
Built-in Nested Vectored Interrupt Controller (NVIC)
®
®
Arm Cortex -M4F
Hardware IEEE 754 compliant Floating-point Unit (FPU)
DSP extension with hardware divider and single-cycle 32-bit
hardware multiplier
24-bit system tick timer
Programmble and maskable interrupt
Low Power Sleep mode by WFI and WFE instructions
Brown-out Detector
(BOD)
Low Voltage Reset (LVR)
Eight-level BOD with brown-out interrupt and reset option.
(3.0V/2.8V/2.6V/2.4V/2.2V/2.0V/1.8V/1.6V)
LVR with 1.5V threshold voltage level.
96-bit Unique ID (UID).
Security
128-bit Unique Customer ID (UCID).
One built-in temperature sensor with 1°C resolution.
Factory pre-loaded 32 KB mask ROM for secure boot procedure
Boot Loader
Uses SHA-256 and AES-256 to validate data in APROM,
LDROM and external SPI Flash
(M48xID/M487KMCAN)
Nuvoton ISP (In-System-Programming) tool for firmware
upgrade via UART and high speed USB device
ISP/IAP libraries
Boot Loader
(M48xGC/M48xE8)
Factory pre-loaded 8 KB mask ROM for secure boot procedure
Uses ECC to validate data in APROM, LDROM and external SPI
Flash
Dual bank 512/256 KB on-chip Application ROM (APROM) for
Over-The-Air (OTA) upgrade. (M48xID)
Flash
Dual bank 512 KB on-chip Application ROM (APROM) for OverThe-Air (OTA) upgrade. (M487KMCAN)
Single bank 256/128 KB on-chip Application ROM (APROM).
(M48xGC/M48xE8)
Four eXecute-Only-Memory regions for data protection.
May 08, 2020
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M480 SERIES DATASHEET
Memories
M480
(M48xGC/M48xE8)
192 MHz maximum frequency, with performance at zero wait
cycle in continuous address read access
4 KB on-chip Flash for user-defined loader (LDROM)
8 KB non-readble Key Protection ROM (KPROM) for firmware
programming protection
4 KB non-readble Security Protection ROM (SPROM) for
intelectual property protection
3 KB One Time Programable (OTP) ROM for data security.
(M48xID/M487KMCAN)
2 KB One Time Programable (OTP) ROM for data security.
(M48xGC/M48xE8)
All on-chip Flash support 4 KB page erase
Fast Flash programming verification with CRC
On-chip Flash programming with In-Chip Programming (ICP), InSystem Programming (ISP) and In-Application Programming
(IAP) capabilities
Configurable boot up sources including boot loader, userdefined loader (LDROM) or Application ROM (APROM)
Data Flash with configurable memory size
2-wired ICP Flash updating through SWD interface
32-bit/64-bit and multi-word Flash programming function
Up to 160 KB on-chip SRAM includes: (M48xID/ M487KMCAN)
M480 SERIES DATASHEET
– 32 KB SRAM located in bank 0 that supports hardware parity
check and retenion mode; Exception (NMI) generated upon a
parity check error
– 96/32 KB SRAM located in bank 1
– 32 KB SRAM located in bank 2 that can be used as cache for
external SPI Flash memory
SRAM
Up to 128/64 KB on-chip SRAM includes: (M48xGC/M48xE8)
– 32 KB SRAM located in bank 0 that supports hardware parity
check and retenion mode; Exception (NMI) generated upon a
parity check error
– 96/32 KB SRAM located in bank 1
Byte-, half-word- and word-access
PDMA operation
Supports CRC-CCITT, CRC-8, CRC-16 and CRC-32
polynomials
Programmable initial value and seed value
Cyclic Redundancy
Calculation (CRC)
Programmable order reverse setting and one’s complement
setting for input data and CRC checksum
8-bit, 16-bit, and 32-bit data width
8-bit write mode with 1-AHB clock cycle operation
16-bit write mode with 2-AHB clock cycle operation
May 08, 2020
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M480
32-bit write mode with 4-AHB clock cycle operation
Uses DMA to write data with performing CRC operation
16 independent and configurable channels for automatic data
transfer between memories and peripherals
Basic and Scatter-Gather transfer modes
Each channel supports circular buffer management using
Scatter-Gather Transfer mode
Peripheral DMA (PDMA)
Stride function for rectangle image data movement
Fixed-priority and Round-robin priorities modes
Single and burst transfer types
Byte-, half-word- and word tranfer unit with count up to 65536
Incremental or fixed source and destination address
Clocks
4~24 MHz High-speed eXternal crystal oscillator (HXT) for
precise timing operation
External Clock Source
32.7688 kHz Low-speed eXternal crystal oscillator (LXT) for
RTC function and low-power system operation
Supports clock failure detection for external crystal oscillators
and exception generatation (NMI)
48 MHz High-speed Internal RC oscillator (HIRC48M) dedicated
for crystal-less USB. (M48xGC/M48xE8)
12 MHz High-speed Internal RC oscillator (HIRC) trimmed to 2%
accuracy that can optionally be used as a system clock
10 kHz Low-speed Internal RC oscillator (LIRC) for watchdog
timer and wakeup operation
Up to 480 MHz on-chip PLL, sourced from HIRC or HXT, allows
CPU operation up to the maximum CPU frequency without the
need for a high-frequency crystal
Real-Time Clock with a separate power domain and
independent VBAT pin. (M48xGC/M48xE8)
The RTC clock source includes Low-speed external crystal
oscillator (LXT)
The RTC block includes 80 bytes of battery-powered backup
registers, which can be cleared by tamper pins.
(M48xID/M487KMCAN)
Real-Time Clock (RTC)
The RTC block includes 20 bytes of battery-powered backup
registers, which can be cleared by tamper pins.
(M48xGC/M48xE8)
Supports 6 static and dynamic tamper pins
Able to wake up CPU from any reduced power mode
Supports ±5ppm within 5 seconds software clock accuracy
compensation
Supports Alarm registers (second, minute, hour, day, month,
May 08, 2020
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M480 SERIES DATASHEET
Internal Clock Source
M480
year)
Supports RTC Time Tick and Alarm Match interrupt
Automatic leap year recognition
Supports 1 Hz clock output for calibration
Timers
TIMER
Four sets of 32-bit timers with 24-bit up counter and one 8-bit
pre-scale counter from independent clock source
One-shot, Periodic, Toggle and Continuous Counting operation
modes
Supports event counting function to count the event from
external pins
Supports external capture pin for interval measurement and
resetting 24-bit up counter
32-bit Timer
Supports chip wake-up function, if a timer interrupt signal is
generated
PWM
Eight 16-bit PWM counters with 12-bit clock prescale
Supports 12-bit deadband (dead time)
Up, down or up-down PWM counter type
Supports brake function
Supports mask function and tri-state output for each PWM
channel
M480 SERIES DATASHEET
Twelve 16-bit counters with 12-bit clock prescale for twelve 192
MHz PWM output channels
Up to 12 independent input capture channels with 16-bit
resolution counter
Supports dead time with maximum divided 12-bit prescale
Up, down or up-down PWM counter type
Supports complementary mode for 3 complementary paired
PWM output channels
Enhanced PWM (EPWM)
Synchronous function for phase control
Counter synchronous start function
Brake function with auto recovery mechanism
Mask function and tri-state output for each PWM channel
Trigger EADC or DAC to start conversion immediately.
Trigger EADC to start conversion after a short delay.
(M48xGC/M48xE8)
Hardware short-circuit output check. (M48xGC/M48xE8)
Basic PWM (BPWM)
May 08, 2020
Two 16-bit counters with 12-bit clock prescale for twelve 192
MHz PWM output channels.
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M480
Up to 6 independent input capture channels with 16-bit
resolution counter
Up, down or up-down PWM counter type
Counter synchronous start function
Mask function and tri-state output for each PWM channel
Able to trigger EADC to start conversion.
18-bit free running up counter for WDT time-out interval
Supports multiple clock sources from LIRC (default selection),
HCLK/2048 and LXT with 8 selectable time-out period
Watchdog
Able to wake up system from Power-down or Idle mode
Time-out event to trigger interrupt or reset system
Supports four WDT reset delay periods, including 1026, 130, 18
or 3 WDT_CLK reset delay period
Configured to force WDT enabled on chip power-on or reset.
Window Watchdog
Clock sourced from HCLK/2048 or LIRC; the window set by 6-bit
counter with 11-bit prescale
Suspended in Idle/Power-down mode
Analog Interfaces
One 12-bit, 19-ch 5 MSPS SAR EADC with up to 16 singleended input channels or 8 differential input pairs; 10-bit accuracy
is guaranteed.
Three internal channels for VBAT, band-gap VBG input and
Temperature sensor input
Enhanced Analog-toDigital Converter (EADC)
(M48xID/M487KMCAN)
Two power saving modes: Power-down mode and Standby
mode
Supports calibration capability.
Analog-to-Digital conversion can be triggered by software
enable, external pin, Timer 0~3 overflow pulse trigger or PWM
trigger.
Configurable EADC sampling time.
Double data buffers for sample module 0~3.
PDMA operation.
One 12-bit, 19-ch 5 MSPS SAR EADC with up to 16 singleended input channels or 8 differential input pairs; 10-bit accuracy
is guaranteed.
Enhanced Analog-toDigital Converter (EADC)
(M48xGC/M48xE8)
One 12-bit, 16-ch 5 MSPS SAR EADC with up to 16 singleended input channels or 8 differential input pairs; 10-bit accuracy
is guaranteed.
Three internal channels for VBAT, band-gap VBG input and
Temperature sensor input
Supports external VREF pin or internal reference voltage VREF:
May 08, 2020
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M480 SERIES DATASHEET
Supports external VREF pin or internal reference voltage VREF:
1.6V, 2.0V, 2.5V, and 3.0V.
M480
1.6V, 2.0V, 2.5V, and 3.0V.
Two power saving modes: Power-down mode and Standby
mode
Supports calibration capability.
Analog-to-Digital conversion can be triggered by software
enable, external pin, Timer 0~3 overflow pulse trigger or PWM
trigger.
Configurable EADC sampling time.
Double data buffers for sample module 0~3.
Supports simultaneously trigger mode.
PDMA operation.
12-bit, 1 MSPS voltage type DAC with 8-bit mode and 8μs railto-rail settle time.
Maximum output voltage AVDD -0.2V at buffer mode
Digital-to-Analog
Converter (DAC)
Digital-to-Analog conversion triggered by Timer0~3, EPWM0,
EPWM1, external trigger pin to start DAC conversion or
software.
Supports group mode for synchronized data update of two
DACs. (M48xID/M487KMCAN)
PDMA operation
Two rail-to-rail Analog Comparators.
Supports four multiplexed I/O pins at positive input.
Supports I/O pins, band-gap, DAC, and 16-level Voltage divider
from AVDD or VREF at negative input
M480 SERIES DATASHEET
Analog Comparator
(ACMP)
Supports four programmable propagation speeds for power
saving
Supports wake up from Power-down by interrput
Supports triggers for brake events and cycle-by-cycle control for
PWM
Supports window compare mode and window latch mode.
Supports programmable hysteresis window: 0mV, 10mV, 20mV
and 30mV
Operational Amplifier
(OPA)
(M48xID/M487KMCAN)
Three Operational Amplifiers with 0~AVDD input voltage range.
OPA schmitt trigger buffer output used as the interrupt source of
comparator.
Communication Interfaces
Low-power UARTs with up to 17.45 MHz baud rate.
Low-power UART
Auto-Baud Rate measurement and baud rate compensation
function.
Supports low power UART (LPUART): baud rate clock from
LXT(32.768 kHz) with 9600bps in Power-down mode even
system clock is stopped.
May 08, 2020
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M480
16-byte FIFOs with programmable level trigger
Auto flow control ( nCTS and nRTS)
Supports IrDA (SIR) function
Supports LIN function on UART0 and UART1
Supports RS-485 9-bit mode and direction control
Supports nCTS, incoming data, Received Data FIFO reached
threshold and RS-485 Address Match (AAD mode) wake-up
function in idle mode.
Supports hardware or software enables to program nRTS pin to
control RS-485 transmission direction
Supports wake-up function
8-bit receiver FIFO time-out detection function
Supports break error, frame error, parity error and
receive/transmit FIFO overflow detection function
PDMA operation.
ISO-7816-3 which are compliant with ISO-7816-3 T=0, T=1
Supports full duplex UART function.
4-byte FIFOs with programmable level trigger
Programmable guard time selection (11 ETU ~ 266 ETU)
One 24-bit and two 8 bit time-out counters for Answer to
Request (ATR) and waiting times processing
Smart Card Interface
Auto inverse convention function
Stop clock level and clock stop (clock keep) function
Transmitter and receiver error retry function
Supports hardware auto deactivation sequence after card
removal.
2
Three sets of I C devices with Master/Slave mode
Supports Standard mode (100 kbps), Fast mode (400 kbps),
Fast mode plus (1 Mbps) and High speed mode (3.4Mbps)
Supports 10 bits mode
2
IC
Programmable clocks allowing for versatile rate control
Supports multiple address recognition (four slave address with
mask option)
Supports SMBus and PMBus
Supports multi-address power-down wake-up function
PDMA operation
SPI Master (SPI Flash)
(M48xID)
May 08, 2020
Maximum 32 MB external SPI Flash memory with standard (1bit), dual (2-bit) and quad (4-bit) transfer mode.
32 KB cache memory for enhancing program execution
performance.
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M480 SERIES DATASHEET
Supports hardware activation, deactivation and warm reset
sequence process
M480
64-bit key length for code protection.
DMA mode for code transfer between SPI Flash memory and
SRAM.
SPI Master function with 8-, 16-, 24-, and 32-bit length of
transaction and burst mode operation, which can
transmit/receive data up to four successive transactions in one
transfer.
Supports eXcute-In-Place (XIP)
SPI Quad controller with Master/Slave mode, up to 96 MHz at
2.7V~3.6V stsyem voltage.
Supports Dual and Quad I/O Transfer mode
Supports one/two data channel half-duplex transfer.
(M48xID/M487KMCAN)
Supports one data channel half-duplex transfer.
(M48xGC/M48xE8)
Supports double data rate mode. (M48xGC/M48xE8)
Quad SPI
Supports receive-only mode
Configurable bit length of a transfer word from 8 to 32-bit
Provides separate 8-level depth transmit and receive FIFO
buffers
Supports MSB first or LSB first transfer sequence
Supports the byte reorder function
Supports Byte or Word Suspend mode
Supports 3-wired, no slave select signal, bi-direction interface
PDMA operation.
M480 SERIES DATASHEET
2
SPI/I S controllers with Master/Slave mode.
2
SPI/I S provides separate 4-level of 32-bit (or 8-level of 16-bit)
transmit and receive FIFO buffers.
SPI
Up to 96 MHz in both Master/Slave mode @ 2.7V-3.6V
Configurable bit length of a transfer word from 8 to 32-bit.
MSB first or LSB first transfer sequence.
2
SPI/I S
Byte reorder function.
Supports Byte or Word Suspend mode.
Supports one data channel half-duplex transfer.
Supports receive-only mode.
2
IS
Supports mono and stereo audio data with 8-, 16-, 24- and 32bit audio data sizes.
2
Supports PCM mode A, PCM mode B, I S and MSB justified
data format.
PDMA operation.
May 08, 2020
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M480
2
One set of I S interface with Master/Slave mode.
Supports mono and stereo audio data with 8-, 16-, 24- and 32bit word sizes.
Two 16-level FIFO data buffers, one for transmitting and the
other for receiving.
2
2
IS
Supports I S protocols: Philips standard, MSB-justified, and
LSB-justified data format.
Supports PCM protocols: PCM standard, MSB-justified, and
LSB-justified data format.
PCM protocol supports TDM multi-channel transmission in one
audio sample; the number of data channel can be set as 2, 4, 6
or 8.
PDMA operation.
2
Two sets of USCI,configured as UART, SPI or I C function.
Supports single byte TX and RX buffer mode
UART
Supports one transmit buffer and two receive buffers for data
payload.
Supports hardware auto flow control function and programmable
flow control trigger level.
9-bit Data Transfer.
Baud rate detection by built-in capture event of baud rate
generator.
Supports wake-up function.
PDMA operation.
SPI
Supports one transmit buffer and two receive buffer for data
payload.
(M48xID/M487KMCAN)
Supports additional receive/transmit 16 entries FIFO for data
payload.
Configurable bit length of a transfer word from 4 to 16-bit (SPI
Quad transmission only supports 8 to 16-bit of word length).
Supports MSB first or LSB first transfer sequence.
Supports Word Suspend function.
Supports 3-wire, no slave select signal, bi-direction interface.
Supports wake-up function: input slave select transition.
PDMA operation.
2
IC
Supports master and slave device capability.
Supports one transmit buffer and two receive buffer for data
payload.
Communication in standard mode (100 kbps), fast mode (up to
400 kbps), and Fast mode plus (1 Mbps).
May 08, 2020
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M480 SERIES DATASHEET
Supports Master or Slave mode operation.
Universal Serial Control
Interface (USCI)
M480
Supports 10-bit mode.
Supports 10-bit bus time out capability.
Supports bus monitor mode.
Supports power-down wake-up by data toggle or address
match.
Supports multiple address recognition.
Supports device address flag.
Programmable setup/hold time.
CAN 2.0B controllers.
Controller Area Network
(CAN)
Each supports 32 Message Objects; each Message Object has
its own identifier mask.
Programmable FIFO mode (concatenation of Message Object).
Disabled Automatic Re-transmission mode for Time Triggered
CAN applications.
Supports power-down wake-up function.
Secure Digital Host Controllers are compliant with SD Memory
Card Specification Version 2.0.
Secure Digital Host
Controller (SDHC)
Supports 50 MHz to achieve 200 Mbps at 3.3V operation.
Supports dedicated DMA master with Scatter-Gather function to
accelerate the data transfer between system memory and
SD/SDHC/SDIO card.
Supports up to three memory banks with individual adjustment
of timing parameter.
M480 SERIES DATASHEET
Each bank supports dedicated external chip select pin with
polarity control and up to 1 MB addressing space.
8-/16-bit data width.
External Bus Interface
(EBI)
Supports byte write in 16-bit data width mode.
Configurable idle cycle for different access condition: Idle of
Write command finish (W2X) and Idle of Read-to-Read (R2R).
Supports Address/Data multiplexed mode.
Supports address bus and data bus separate mode.
Supports LCD interface i80 mode.
PDMA operation.
Supports four I/O modes: Quasi bi-direction, Push-Pull output,
Open-Drain output and Input only with high impendence mode.
Selectable TTL/Schmitt trigger input.
Configured as interrupt source with edge/level trigger setting.
GPIO
Supports independent pull-up/pull-down control.
Supports high driver and high sink current I/O.
Supports software selectable slew rate control.
Supports 5V-tolerance function except analog I/O.
May 08, 2020
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Rev 3.00
M480
Control Interfaces
Quadrature Encoder
Interface (QEI)
Two QEI phase inputs (QEI_A, QEI_B) and one Index input
(QEI_INDEX).
Supports 2/4 times free-counting mode and 2/4 comparecounting mode.
Supports encoder pulse width measurement mode with ECAP.
Input Capture Timer/Counter
Supports three input channels with independent capture counter
hold register.
Enhanced Capture
(ECAP)
24-bit Input Capture up-counting timer/counter supports
captured events reset and/or reload capture counter.
Supports rising edge, falling edge and both edge detector
options with noise filter in front of input ports.
Supports compare-match function.
Advanced Connectivity
USB 2.0 Full Speed OTG (On-The-Go)
On-chip USB 2.0 full speed OTG transceiver.
Compliant with USB OTG Supplement 2.0
Configurable as host-only, device-only or ID-dependent
USB 2.0 Full Speed Host Controller
Compliant with USB Revision 1.1 Specification.
Supports full-speed (12Mbps) and low-speed (1.5Mbps) USB
devices.
USB 2.0 Full Speed with
on-chip transceiver
Supports Control, Bulk, Interrupt, Isochronous and Split
transfers.
Integrated a port routing logic to route full/low speed device to
OHCI controller.
Supports an integrated Root Hub.
Supports port power control and port over current detection.
Built-in DMA.
USB 2.0 Full Speed Device Controller
Compliant with USB Revision 2.0 Specification.
Supports suspend function when no bus activity existing for 3
ms.
12 configurable endpoints for configurable Isochronous, Bulk,
Interrupt and Control transfer types.
1024 bytes configurable RAM for endpoint buffer.
Remote wake-up capability.
May 08, 2020
Page 27 of 523
Rev 3.00
M480 SERIES DATASHEET
Compatible with OHCI (Open Host Controller Interface)
Revision 1.0.
M480
Supports crystall-less features. (M48xGC/M48xE8)
USB 2.0 link power management. (M48xID/M487KMCAN)
USB 2.0 High Speed OTG (On-The-Go)
On-chip USB 2.0 high speed OTG transceiver.
Compliant with USB OTG Supplement 2.0.
Configurable as host-only, device-only or ID-dependent.
USB 2.0 High Speed Host Controller
Compliant with USB Revision 2.0 Specification.
Compatible with EHCI (Enhanced Host Controller Interface)
Revision 1.0.
Compatible with OHCI (Open Host Controller Interface)
Revision 1.0.
Supports high-speed (480Mbps), full-speed (12Mbps) and lowspeed (1.5Mbps) USB devices.
USB 2.0 High Speed with
on-chip transceiver
(M48xID/M487KMCAN)
Integrated a port routing logic to route full/low speed device to
OHCI controller.
Supports an integrated Root Hub.
Built-in DMA.
USB 2.0 High Speed Device Controller
Compliant with USB Revision 2.0 Specification.
Supports one dedicate control endpoint and 12 configurable
endpoints; each can be Isochronous, Bulk or Interrupt and either
IN or OUT direction.
4096 bytes configurable RAM for endpoint buffer and up to 1024
bytes maximum packet size.
M480 SERIES DATASHEET
Three different operation modes of an in-endpoint: Auto
Validation mode, Manual Validation mode and Fly mode.
Suspend, resume and remote wake-up capability.
Built-in DMA.
IEEE Std. 802.3 CSMA/CD protocol.
Ethernet frame time stamping for IEEE Std. 1588 – 2002
protocol.
Supports both half and full duplex for 10 Mbps or 100 Mbps
operation.
Ethernet MAC
(M48xID/M487KMCAN)
RMII (Reduced Media Independent Interface) and serial
management interface (MDC/MDIO).
Pause and remote pause function for flow control.
Long frame (more than 1518 bytes) and short frame (less than
64 bytes) reception.
CAM function for Ethernet MAC address recognition.
Supports Magic Packet recognition to wake system up from
Power-down mode.
Built-in DMA.
May 08, 2020
Page 28 of 523
Rev 3.00
M480
Digital Camera Interface
Supports CCIR601, CCIR656 and 4-bit interfaces for CMOS
sensor.
Camera Capture
Interface (CCAP)
(M48xGC/M48xE8)
Color format for data input supports YUV4:2:2 and RGB565.
Color format for data output supports YUV4:2:2, RGB565,
RGB555 and Y-only.
Supports 1-bit Y(luminance) output with 8-bit threshold setting
for image thresholding.
Supports image cropping and downscaling.
Cryptography Accelerator
Hardware ECC accelerator.
Supports 192-bit and 256-bit key length.
m
Supports both prime field GF(p) and binary field GF(2 ).
Supports NIST P-192, P-224, P-256, P-384 and P-521 curve
sizes.
Elliptic Curve
Cryptography (ECC)
(M48xID/M487KMCAN)
Supports NIST B-163, B-233, B-283, B-409 and B-571 curve
sizes.
Supports NIST K-163, K-233, K-283, K-409 and K-571 curve
sizes.
Supports point multiplication, addition and doubling operations
m
in GF(p) and GF(2 ).
Hardware AES accelerator.
Advanced Encryption
Standard (AES)
Supports 128-bit, 192-bit and 256-bit key length and key
expander, and is compliant with FIPS 197.
Supports ECB, CBC, CFB, OFB, CTR, CBC-CS1, CBC-CS2 and
CBC-CS3 block cipher modes
Compliant with NIST SP800-38A and addendum.
Data Encryption
Standard (DES)
Hardware DES accelerator.
(M48xID/M487KMCAN)
Compliant with FIPS 46-3.
Supports ECB, CBC, CFB, OFB, and CTR block cipher mode.
Hardware Triple DES accelerator.
Triple Data Encryption
Standard (3DES)
Supports two or three different keys in each round.
(M48xID/M487KMCAN)
Implemented based on X9.52 standard and compliant with FIPS
SP 800-67.
May 08, 2020
Supports ECB, CBC, CFB, OFB, and CTR block cipher mode.
Page 29 of 523
Rev 3.00
M480 SERIES DATASHEET
Supports modulus division, multiplication, addition and
subtraction operations in GF(p).
M480
Hardware SHA accelerator.
Secure Hash Algorithm
(SHA)
Supports SHA-160, SHA-224, SHA-256, SHA-384 and SHA512. (M48xID/M487KMCAN)
Supports SHA-256. (M48xID/M487KMCAN)
Compliant with FIPS 180/180-2.
Hardware HMAC accelerator.
keyed-Hash Message
Authentication Code
(HMAC)
Supports HMAC-SHA-160, HMAC-SHA-224, HMAC-SHA-256,
HMAC-SHA-384, and HMAC-SHA-512. (M48xID/M487KMCAN)
Supports HMAC-SHA-256. (M48xID/M487KMCAN)
Compliant with FIPS 180/180-2.
True Random Number
Generator (TRNG)
800 random bits per second.
(M48xGC/M48xE8)
M480 SERIES DATASHEET
May 08, 2020
Page 30 of 523
Rev 3.00
M480
3
PARTS INFORMATION
3.1 Package Type
Part No.
M481
M482
QFN33
LQFP48
LQFP64
M481LGCAE
M481ZIDAE
M481LIDAE
M481ZE8AE
M481LE8AE
M482ZGCAE
M482LGCAE
M482SGCAE
M482ZIDAE
M482LIDAE
M482SIDAE
M482ZE8AE
M482LE8AE
M482SE8AE
M481SIDAE
M481SE8AE
M481SGCAE2A
M483SGCAE
M483SIDAE
M483SE8AE
M483SGCAE2A
M484SIDAE
M484
M485
M487
M484SIDAE2U
M485LIDAE
LQFP144
M481SGCAE
M481ZGCAE
M483
LQFP128
M485SIDAE
M487SIDAE
M482KGCAE
M482KIDAE
M483KGCAE
M483KIDAE
M483KGCAE2A
M484KIDAE
M485KIDAE
M487KIDAE
M487KMCAN
M487JIDAE
M480 SERIES DATASHEET
May 08, 2020
Page 31 of 523
Rev 3.00
M480
3.2 M480 Series Selection Guide
3.2.1
M481 Base Series (M481xIDAE)
M481
PART NUMBER
ZIDAE
Flash (KB)
LIDAE
512
160 (include 32 KB cache for XIP)
SRAM (KB)
4
ISP Loader ROM (KB)
I/O
32-bit Timer
26
41
4
Peripheral DMA
Tamper
16
-
-
LPUART
Connectivity
ISO-7816
1
3
1 (Support XIP)
1
3
3
I2S
4
1
3
I2C
USCI
2
2
CAN
LIN
SDHC
52
6
SPI Master
Quad SPI
SPI/I2S
SIDAE
1
2
16-bit PWM
2
24
QEI
1
2
2
ECAP
-
1
-
1
10
12
2
16
USB 2.0 FS OTG
USB 2.0 HS OTG
12-bit ADC
M480 SERIES DATASHEET
12-bit DAC
2
Analog Comparator
Operational Amplifier
1
2
-
2
Ethernet
Cryptography
External Bus
Interface
Package
-
√
√
QFN 32
LQFP 48
LQFP 64
May 08, 2020
Page 32 of 523
Rev 3.00
M480
3.2.2
M481 Base Series (M481xGCAE / M481xE8AE)
M481
PART NUMBER
Flash (KB)
(Support XOM)
SRAM (KB)
ZE8AE
ZGCAE
LE8AE
LGCAE
SE8AE
SGCAE
SGCAE2A
128
256
128
256
128
256
256
64
128
64
128
64
128
128
ISP Loader ROM (KB)
I/O
4
26
41
32-bit Timer
Peripheral DMA
Tamper
LPUART
-
1
1
3
3
8
ISO-7816
Connectivity
52
16
-
1
SPI Master
-
Quad SPI
2
SPI/I2S
52
4
2
3
I2S
I2C
1
3
USCI
-
CAN
-
LIN
2
SDHC
1
16-bit PWM
QEI
24
1
2
2
2
ECAP
-
1
1
1
16
8+8
USB 2.0 FS OTG
-
USB 2.0 HS OTG
12-bit ADC
10
12
12-bit DAC
1
Analog Comparator
Operational Amplifier
2
AES-256
√
TRNG
External Bus Interface
Camera Interface
Package
May 08, 2020
-
√
√
√
QFN33
LQFP 48
√
LQFP 64
√
LQFP 64
Page 33 of 523
Rev 3.00
M480 SERIES DATASHEET
Ethernet
Cryptography
M480
3.2.3
M482 USB FS OTG Series (M482xIDAE)
M482
PART NUMBER
ZIDAE
LIDAE
SIDAE
Flash (KB)
512
SRAM (KB)
160 (include 32 KB cache for XIP)
ISP Loader ROM (KB)
I/O
4
26
41
32-bit Timer
-
1
6
4
4
6
ISO-7816
SPI Master
Connectivity
100
16
-
LPUART
3
1 (Support XIP)
Quad SPI
SPI/I2S
52
4
Peripheral DMA
Tamper
KIDAE
1
3
3
I2S
1
I2C
3
USCI
CAN
2
-
LIN
2
SDHC
2
16-bit PWM
24
QEI
1
2
2
2
ECAP
USB 2.0 FS OTG
-
1
1
2
16
16
2
3
√
USB 2.0 HS OTG
12-bit ADC
10
12
12-bit DAC
2
Analog Comparator
Operational Amplifier
Ethernet
2
1
2
-
M480 SERIES DATASHEET
Cryptography
External Bus Interface
Package
May 08, 2020
-
√
√
√
QFN33
LQFP 48
LQFP 64
LQFP 128
Page 34 of 523
Rev 3.00
M480
3.2.4
M482 USB FS OTG Series (M482xGCAE / M482xE8AE)
M482
PART NUMBER
Flash (KB)
(Support XOM)
SRAM (KB)
ZE8AE
ZGCAE
LE8AE
LGCAE
SE8AE
SGCAE
KGCAE
128
256
128
256
128
256
256
64
128
64
128
64
128
128
ISP Loader ROM (KB)
I/O
4
26
41
32-bit Timer
Peripheral DMA
Tamper
LPUART
-
1
6
3
3
8
ISO-7816
Connectivity
100
16
-
1
SPI Master
-
Quad SPI
2
SPI/I2S
52
4
2
3
I2S
I2C
1
3
USCI
-
CAN
-
LIN
2
SDHC
1
16-bit PWM
QEI
24
1
2
2
2
ECAP
-
1
1
2
16
16
√ (Crystal-less)
USB 2.0 FS OTG
USB 2.0 HS OTG
12-bit ADC
10
12
12-bit DAC
1
Analog Comparator
Operational Amplifier
2
AES-256
√
TRNG
External Bus Interface
Camera Interface
Package
May 08, 2020
-
√
√
√
QFN33
LQFP 48
√
LQFP 64
√
LQFP 128
Page 35 of 523
Rev 3.00
M480 SERIES DATASHEET
Ethernet
Cryptography
M480
3.2.5
M483 CAN Series (M483xIDAE)
M483
PART NUMBER
SIDAE
KIDAE
Flash (KB)
512
SRAM (KB)
160 (include 32 KB cache for XIP)
ISP Loader ROM (KB)
I/O
4
44
100
32-bit Timer
4
Peripheral DMA
Connectivity
Tamper
16
1
6
LPUART
6
ISO-7816
SPI Master
3
1
Quad SPI
1
SPI/I2S
4
I2S
1
I2C
3
USCI
CAN
2
2
LIN
2
SDHC
2
16-bit PWM
24
QEI
ECAP
USB 2.0 FS OTG
2
1
-
2
√
USB 2.0 HS OTG
√
12-bit ADC
16
12-bit DAC
2
Analog Comparator
Operational Amplifier
Ethernet
M480 SERIES DATASHEET
Cryptography
External Bus
Interface
Package
May 08, 2020
2
2
3
√
LQFP 64
Page 36 of 523
LQFP 128
Rev 3.00
M480
3.2.6
M483 CAN Series (M483xGCAE / M483xE8AE)
M483
PART NUMBER
Flash (KB)
(Support XOM)
SRAM (KB)
SE8AE
SGCAE
SGCAE2A
128
256
256
256
64
128
128
128
ISP Loader ROM (KB)
I/O
52
4
16
1
Connectivity
ISO-7816
1
-
Quad SPI
2
SPI/I2S
3
I2S
I2C
1
3
USCI
-
CAN
3
LIN
2
SDHC
1
16-bit PWM
QEI
24
2
1
1
USB 2.0 HS OTG
8+8
16
12-bit DAC
Analog Comparator
1
2
Operational Amplifier
-
16+8
16
-
Cryptography
AES-256
√
TRNG
External Bus
Interface
Camera Interface
√
√
LQFP 64
LQFP 64
Page 37 of 523
LQFP 128
Rev 3.00
M480 SERIES DATASHEET
Ethernet
May 08, 2020
2
√ (Crystal-less)
USB 2.0 FS OTG
Package
6
1
8
SPI Master
12-bit ADC
100
52
Peripheral DMA
ECAP
KGCAE2A
4
32-bit Timer
Tamper
LPUART
KGCAE
M480
3.2.7
M484 USB HS OTG Series
M484
PART NUMBER
SIDAE
SIDAE2U
Flash (KB)
SRAM (KB)
ISP Loader ROM (KB)
I/O
Connectivity
160 (include 32 KB cache for XIP)
4
44
44
32-bit Timer
4
Peripheral DMA
16
Tamper
1
1
LPUART
6
ISO-7816
SPI Master
3
1
Quad SPI
1
SPI/I2S
4
I2S
1
I2C
3
USCI
CAN
2
-
LIN
2
SDHC
2
16-bit PWM
24
QEI
ECAP
USB 2.0 FS OTG
1
√
√
12-bit ADC
16
12-bit DAC
2
Analog Comparator
M480 SERIES DATASHEET
Cryptography
External Bus
Interface
Package
May 08, 2020
100
6
2
1
-
USB 2.0 HS OTG
Operational Amplifier
Ethernet
KIDAE
512
2
2
2
2
√
3
√
LQFP 64
LQFP 64
Page 38 of 523
LQFP 128
Rev 3.00
M480
3.2.8
M485 Crypto Series
M485
PART NUMBER
LIDAE
SIDAE
Flash (KB)
SRAM (KB)
ISP Loader ROM (KB)
I/O
Connectivity
160 (include 32 KB cache for XIP)
4
41
44
32-bit Timer
4
Peripheral DMA
16
Tamper
-
1
LPUART
6
ISO-7816
SPI Master
3
1
Quad SPI
SPI/I2S
4
1
I2C
3
USCI
CAN
2
-
LIN
2
SDHC
2
16-bit PWM
24
QEI
USB 2.0 HS OTG
12-bit ADC
1
-
2
√
-
√
√
16
16
2
2
2
2
-
3
√
√
LQFP 48
LQFP 64
Page 39 of 523
LQFP 128
Rev 3.00
M480 SERIES DATASHEET
May 08, 2020
4
12
12-bit DAC
Cryptography
External Bus
Interface
Package
6
2
1
√
Analog Comparator
Operational Amplifier
Ethernet
100
1
3
I2S
ECAP
USB 2.0 FS OTG
KIDAE
512
M480
3.2.9
M487 Ethernet Series
M487
PART NUMBER
SIDAE
Flash (KB)
KIDAE
SRAM (KB)
ISP Loader ROM (KB)
I/O
2560
44
100
32-bit Timer
4
Peripheral DMA
16
Tamper
1
6
6
-
SPI/I2S
4
I2S
1
I2C
3
USCI
CAN
2
2
LIN
2
SDHC
2
16-bit PWM
24
QEI
2
1
-
2
√
USB 2.0 HS OTG
√
12-bit ADC
16
12-bit DAC
2
Analog Comparator
M480 SERIES DATASHEET
May 08, 2020
6
3
1
Cryptography
External Bus
Interface
Package
94
1
Quad SPI
Operational Amplifier
Ethernet
114
6
ISO-7816
SPI Master
ECAP
USB 2.0 FS OTG
KMCAN
160
4
LPUART
Connectivity
JIDAE
512
2
√
2
√
3
3
LQFP 144
LQFP 128
2
2
3
√
√
√
LQFP 64
LQFP 128
Page 40 of 523
Rev 3.00
M480
3.3 M480 Selection Code
M4
81
Z
G
D
A
E
2A
Core
Series
Package
Flash Size
SRAM Size
Revision
Temperature
Peripheral
®
Cortex -M4F 81: Base
Z: QFN33
A: 8 Kbytes
1: 4 Kbytes
E:-40°C ~ 105°C 2A: 2 EADCs
82: USB FS
(5x5 mm)
B: 16 Kbytes
2: 8 Kbytes
N:-40°C ~ 85°C
83: CAN
L: LQFP48
C: 32 Kbytes
3: 16 Kbytes
84: USB HS
(7x7 mm)
D: 64 Kbytes
4: 20 Kbytes
85: Crypto
C: WLCSP
E: 128 Kbytes
5: 24 Kbytes
87: Ethernet
S: LQFP64
F: 192 Kbytes
6: 32 Kbytes
(7x7 mm)
G: 256 Kbytes
7: 48 Kbytes
O: QFN88
H: 384 Kbytes
8: 64 Kbytes
(10x10 mm)
I: 512 Kbytes
9: 80 Kbytes
2U: 2 USB ports
V: LQFP100 M: 2560 Kbytes A: 96 Kbytes
(14x14 mm)
B: 112 Kbytes
K: LQFP128
C: 128 Kbytes
(14x14 mm)
D: 160 Kbytes
J: LQFP144
(20x20 mm)
M480 SERIES DATASHEET
May 08, 2020
Page 41 of 523
Rev 3.00
M480
4
PIN CONFIGURATION
4.1 Pin Configuration
Users can find pin configuration information in chapter 4 or by using NuTool - PinConfig. The NuTool PinConfigure contains all NuMicro Family chip series with all part number, and helps users configure
GPIO multi-function correctly and handily.
4.1.1
QFN-33 Pin Diagram
VSS
25
LDO_CAP
PA.15
PA.14
PA.13
PA.12
PC.0
PC.1
PF.1
PF.0
24
23
22
21
20
19
18
17
Corresponding Part Number: M481ZE8AE, M481ZGCAE, M481ZIDAE, M482ZE8AE,
M482ZGCAE, M482ZIDAE
nRESET
26
15
VDDIO
VDD
27
14
PA.0
PB.15
28
13
PA.1
PB.14
29
12
PA.2
PB.13
30
11
PA.3
PB.12
31
10
PF.2
9
PF.3
33 VSS
2
3
4
5
6
7
8
PB.4
PB.3
PB.2
PB.1
PB.0
PF.5
PF.4
32
1
AVDD
QFN33
PB.5
M480 SERIES DATASHEET
16
Top transparent view
VDDIO power domain
Figure 4.1-1 QFN-33 Pin Diagram (0/1 USB FS)
May 08, 2020
Page 42 of 523
Rev 3.00
M480
4.1.2
LQFP-48 Pin Diagram (0/1 USB FS)
Corresponding Part Number: M481LE8AE, M481LGCAE, M481LIDAE, M482LE8AE,
PA.15
PA.14
PA.13
PA.12
PC.0
PC.1
PC.2
PC.3
PC.4
PC.5
PF.1
PF.0
36
35
34
33
32
31
30
29
28
27
26
25
M482LGCAE, M482LIDAE, M485LIDAE
37
24
nRESET
LDO_CAP
38
23
VDDIO
VDD
39
22
PA.0
PC.14
40
21
PA.1
PB.15
41
20
PA.2
PB.14
42
19
PA.3
PB.13
43
18
PA.4
PB.12
44
17
PA.5
AVDD
45
16
PA.6
AVSS
46
15
PA.7
PB.7
47
14
PF.2
PB.6
48
13
PF.3
6
7
8
9
10
11
12
PA.11
PA.10
PA.9
PA.8
PF.5
PF.4
4
PB.2
PB.0
3
PB.3
5
2
PB.4
PB.1
1
PB.5
LQFP48
M480 SERIES DATASHEET
VSS
VDDIO power domain
Figure 4.1-2 LQFP-48 Pin Diagram (0/1 USB FS)
May 08, 2020
Page 43 of 523
Rev 3.00
M480
4.1.3
LQFP-64 Pin Diagram (0/1 USB FS)
PA.15
PA.14
PA.13
PA.12
PD.0
PD.1
PD.2
PD.3
PC.0
PC.1
PC.2
PC.3
PC.4
PC.5
PF.1
PF.0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Corresponding Part Number: M481SIDAE, M482SIDAE
VSS
49
32
nRESET
LDO_CAP
50
31
VDDIO
51
30
PA.0
52
29
PA.1
PB.15
53
28
PA.2
PB.14
54
27
PA.3
PB.13
55
26
PA.4
PB.12
56
25
PA.5
AVDD
57
24
LDO_CAP
VREF
58
23
VDD
AVSS
59
22
VSS
PB.11
60
21
PA.6
PB.10
61
20
PA.7
PB.9
62
19
PC.6
PB.8
63
18
PC.7
PB.7
64
17
PF.2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PB.5
PB.4
PB.3
PB.2
PB.1
PB.0
PA.11
PA.10
PA.9
PA.8
PF.6
VDD
PF.5
PF.4
PF.3
LQFP64
PB.6
M480 SERIES DATASHEET
VDD
PC.14
VDDIO power domain
Figure 4.1-3 LQFP-64 Pin Diagram (0/1 USB FS)
May 08, 2020
Page 44 of 523
Rev 3.00
M480
4.1.4
LQFP-64 Pin Diagram (0/1 USB FS with VBAT)
Corresponding Part Number: M481SE8AE, M481SGCAE, M481SGCAE2A, M482SE8AE,
PA.15
PA.14
PA.13
PA.12
PD.0
PD.1
PD.2
PD.3
PC.0
PC.1
PC.2
PC.3
PC.4
PC.5
PF.1
PF.0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
M482SGCAE, M483SE8AE, M483SGCAE, M483SGCAE2A
49
32
nRESET
LDO_CAP
50
31
VDDIO
VDD
51
30
PA.0
PC.14
52
29
PA.1
PB.15
53
28
PA.2
PB.14
54
27
PA.3
PB.13
55
26
PA.4
PB.12
56
25
PA.5
AVDD
57
24
LDO_CAP
VREF
58
23
VDD
AVSS
59
22
VSS
PB.11
60
21
PA.6
PB.10
61
20
PA.7
PB.9
62
19
PC.6
PB.8
63
18
PC.7
PB.7
64
17
PF.2
16
PF.3
PA.9
PF.4
10
PA.10
15
9
PA.11
14
8
PB.0
PF.5
7
PB.1
13
6
PB.2
VBAT
5
PB.3
PF.6
4
PB.4
12
3
PB.5
11
2
VDDIO power domain
PA.8
1
PB.6
LQFP64
VBAT power domain
Figure 4.1-4 LQFP-64 Pin Diagram (0/1 USB FS with VBAT)
May 08, 2020
Page 45 of 523
Rev 3.00
M480 SERIES DATASHEET
VSS
M480
4.1.5
LQFP-64 Pin Diagram (1 USB HS)
HSUSB_ID
HSUSB_VDD12_CAP
HSUSB_D+
HSUSB_VSS
HSUSB_D-
HSUSB_VBUS
HSUSB_VDD33
HSUSB_VRES
PC.0
PC.1
PC.2
PC.3
PC.4
PC.5
PF.1
PF.0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Corresponding Part Number: M483SIDAE, M484SIDAE, M485SIDAE, M487SIDAE
VSS
49
32
nRESET
LDO_CAP
50
31
VDDIO
VDD
51
30
PA.0
PC.14
52
29
PA.1
PB.15
53
28
PA.2
PB.14
54
27
PA.3
PB.13
55
26
PA.4
PB.12
56
25
PA.5
AVDD
57
24
LDO_CAP
VREF
58
23
VDD
AVSS
59
22
VSS
PB.11
60
21
PA.6
PB.10
61
20
PA.7
PB.9
62
19
PC.6
PB.8
63
18
PC.7
PB.7
64
17
PF.2
8
9
10
11
12
13
14
15
16
PA.10
PA.9
PA.8
PF.6
VDD
PF.5
PF.4
PF.3
PB.2
PA.11
5
7
4
PB.3
PB.0
3
PB.4
6
2
PB.1
1
PB.5
M480 SERIES DATASHEET
PB.6
LQFP64
VDDIO power domain
Figure 4.1-5 LQFP-64 Pin Diagram (1 USB HS)
May 08, 2020
Page 46 of 523
Rev 3.00
M480
4.1.6
LQFP-64 Pin Diagram (USB FS + USB HS)
HSUSB_ID
HSUSB_VDD12_CAP
HSUSB_D+
HSUSB_VSS
HSUSB_D-
HSUSB_VBUS
HSUSB_VDD33
HSUSB_VRES
PA.15
PA.14
PA.13
PA.12
PC.0
PC.1
PF.1
PF.0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Corresponding Part Number: M484SIDAE2U
VSS
49
32
nRESET
LDO_CAP
50
31
VDDIO
VDD
51
30
PA.0
PC.14
52
29
PA.1
PB.15
53
28
PA.2
PB.14
54
27
PA.3
PB.13
55
26
PA.4
PB.12
56
25
PA.5
AVDD
57
24
LDO_CAP
VREF
58
23
VDD
AVSS
59
22
VSS
PB.11
60
21
PA.6
PB.10
61
20
PA.7
PB.9
62
19
PC.6
PB.8
63
18
PC.7
PB.7
64
17
PF.2
8
9
10
11
12
13
14
15
16
PA.10
PA.9
PA.8
PF.6
VDD
PF.5
PF.4
PF.3
PB.2
PA.11
5
7
4
PB.3
PB.0
3
PB.4
6
2
PB.1
1
PB.5
M480 SERIES DATASHEET
PB.6
LQFP64
VDDIO power domain
Figure 4.1-6 LQFP-64 Pin Diagram (USB FS + USB HS)
May 08, 2020
Page 47 of 523
Rev 3.00
M480
4.1.7
LQFP-128 Pin Diagram (1 USB FS)
NC
LDO_CAP
NC
VSS
NC
NC
VDD
NC
PA.15
PA.14
PA.13
PA.12
PD.13
PG.15
PG.14
PG.13
PG.12
PG.11
PG.10
PG.9
VDD
VSS
PC.0
PC.1
PC.2
PC.3
PC.4
PC.5
PD.8
PD.9
PF.1
PF.0
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
Corresponding Part Number: M482KIDAE
PE.7
97
64
nRESET
PE.6
98
63
PE.15
PE.5
99
62
PE.14
PE.4
100
61
VDDIO
PE.3
101
60
PA.0
PE.2
102
59
PA.1
VSS
103
58
PA.2
VDD
104
57
PA.3
PE.1
105
56
PA.4
PE.0
106
55
PA.5
PH.8
107
54
LDO_CAP
PH.9
108
53
VDD
PH.10
109
52
VSS
PH.11
110
51
PA.6
PD.14
111
50
PA.7
VSS
112
49
PC.6
LDO_CAP
113
48
PC.7
VDD
114
47
PC.8
PC.14
115
46
PE.13
PB.15
116
45
PE.12
PB.14
117
44
PE.11
PB.13
118
43
PE.10
PB.12
119
42
PE.9
AVDD
120
41
PE.8
VREF
121
40
VDD
AVSS
122
39
VSS
PB.11
123
38
PF.2
PB.10
124
37
PF.3
PB.9
125
36
PH.7
PB.8
126
35
PH.6
PB.7
127
34
PH.5
PB.6
128
33
PH.4
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PC.10
PC.9
PB.1
PB.0
VSS
VDD
PA.11
PA.10
PA.9
PA.8
PC.13
PD.12
PD.11
PD.10
PG.2
PG.3
PG.4
PF.11
PF.10
PF.9
PF.8
PF.7
PF.6
VDD
PF.5
PF.4
4
PB.2
PC.11
3
PB.3
5
2
PC.12
1
PB.4
M480 SERIES DATASHEET
PB.5
LQFP128
VDDIO power domain
Figure 4.1-7 LQFP-128 Pin Diagram (1 USB FS)
May 08, 2020
Page 48 of 523
Rev 3.00
M480
4.1.8
LQFP-128 Pin Diagram (1 USB FS with VBAT)
NC
NC
NC
NC
NC
NC
NC
NC
PA.15
PA.14
PA.13
PA.12
PD.13
PG.15
PG.14
PG.13
PG.12
PG.11
PG.10
PG.9
VDD
VSS
PC.0
PC.1
PC.2
PC.3
PC.4
PC.5
PD.8
PD.9
PF.1
PF.0
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
Corresponding Part Number: M483KGCAE, M483KGCAE2A
PE.7
97
64
nRESET
PE.6
98
63
PE.15
PE.5
99
62
PE.14
PE.4
100
61
VDDIO
PE.3
101
60
PA.0
PE.2
102
59
PA.1
VSS
103
58
PA.2
VDD
104
57
PA.3
PE.1
105
56
PA.4
PE.0
106
55
PA.5
PH.8
107
54
LDO_CAP
PH.9
108
53
VDD
PH.10
109
52
VSS
PH.11
110
51
PA.6
PD.14
111
50
PA.7
VSS
112
49
PC.6
LDO_CAP
113
48
PC.7
VDD
114
47
PC.8
PC.14
115
46
PE.13
PB.15
116
45
PE.12
PB.14
117
44
PE.11
PB.13
118
43
PE.10
PB.12
119
42
PE.9
AVDD
120
41
PE.8
VREF
121
40
VDD
AVSS
122
39
VSS
PB.11
123
38
PF.2
PB.10
124
37
PF.3
PB.9
125
36
PH.7
PB.8
126
35
PH.6
PB.7
127
34
PH.5
PB.6
128
33
PH.4
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PB.2
PC.12
PC.11
PC.10
PC.9
PB.1
PB.0
VSS
VDD
PA.11
PA.10
PA.9
PA.8
PC.13
PD.12
PD.11
PD.10
PG.2
PG.3
PG.4
PF.11
PF.10
PF.9
PF.8
PF.7
PF.6
VBAT
PF.5
PF.4
2
PB.3
1
PB.4
VDDIO power domain
M480 SERIES DATASHEET
PB.5
LQFP128
VBAT power domain
Figure 4.1-8 LQFP-128 Pin Diagram (1 USB FS)
May 08, 2020
Page 49 of 523
Rev 3.00
M480
4.1.9
LQFP-128 Pin Diagram (USB FS + USB HS)
HSUSB_ID
HSUSB_VDD12_CAP
HSUSB_D+
HSUSB_VSS
HSUSB_D-
HSUSB_VBUS
HSUSB_VDD33
HSUSB_VRES
PA.15
PA.14
PA.13
PA.12
PD.13
PG.15
PG.14
PG.13
PG.12
PG.11
PG.10
PG.9
VDD
VSS
PC.0
PC.1
PC.2
PC.3
PC.4
PC.5
PD.8
PD.9
PF.1
PF.0
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
Corresponding Part Number: M483KIDAE, M484KIDAE, M485KIDAE, M487KIDAE
97
64
nRESET
PE.6
98
63
PE.15
PE.5
99
62
PE.14
PE.4
100
61
VDDIO
PE.3
101
60
PA.0
PE.2
102
59
PA.1
VSS
103
58
PA.2
VDD
104
57
PA.3
PE.1
105
56
PA.4
PE.0
106
55
PA.5
PH.8
107
54
LDO_CAP
PH.9
108
53
VDD
PH.10
109
52
VSS
PH.11
110
51
PA.6
PD.14
111
50
PA.7
VSS
112
49
PC.6
LDO_CAP
113
48
PC.7
VDD
114
47
PC.8
PC.14
115
46
PE.13
PB.15
116
45
PE.12
PB.14
117
44
PE.11
PB.13
118
43
PE.10
PB.12
119
42
PE.9
AVDD
120
41
PE.8
VREF
121
40
VDD
AVSS
122
39
VSS
PB.11
123
38
PF.2
PB.10
124
37
PF.3
PB.9
125
36
PH.7
PB.8
126
35
PH.6
PB.7
127
34
PH.5
PB.6
128
33
PH.4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PB.4
PB.3
PB.2
PC.12
PC.11
PC.10
PC.9
PB.1
PB.0
VSS
VDD
PA.11
PA.10
PA.9
PA.8
PC.13
PD.12
PD.11
PD.10
PG.2
PG.3
PG.4
PF.11
PF.10
PF.9
PF.8
PF.7
PF.6
VDD
PF.5
PF.4
LQFP128
PB.5
M480 SERIES DATASHEET
PE.7
VDDIO power domain
Figure 4.1-9 LQFP-128 Pin Diagram (USB FS + USB HS)
May 08, 2020
Page 50 of 523
Rev 3.00
M480
4.1.10 LQFP-128 Pin Diagram (USB FS + USB HS)
HSUSB_ID
HSUSB_VDD12_CAP
HSUSB_D+
HSUSB_VSS
HSUSB_D-
HSUSB_VBUS
HSUSB_VDD33
HSUSB_VRES
PA.15
PA.14
PA.13
PA.12
PD.13
PG.15
PG.14
NC
PG.12
NC
PG.10
PG.9
VDD
VSS
PC.0
PC.1
PC.2
PC.3
PC.4
PC.5
PD.8
PD.9
PF.1
PF.0
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
Corresponding Part Number: M487KMCAN
97
64
nRESET
NC
98
63
PE.15
PE.5
99
62
PE.14
NC
100
61
VDDIO
PE.3
101
60
PA.0
NC
102
59
PA.1
VSS
103
58
PA.2
VDD
104
57
PA.3
PE.1
105
56
PA.4
PE.0
106
55
PA.5
PH.8
107
54
LDO_CAP
PH.9
108
53
VDD
PH.10
109
52
VSS
PH.11
110
51
PA.6
PD.14
111
50
PA.7
VSS
112
49
PC.6
LDO_CAP
113
48
PC.7
VDD
114
47
PC.8
PC.14
115
46
PE.13
PB.15
116
45
PE.12
PB.14
117
44
PE.11
PB.13
118
43
PE.10
PB.12
119
42
PE.9
AVDD
120
41
PE.8
VREF
121
40
VDD
AVSS
122
39
VSS
PB.11
123
38
PF.2
PB.10
124
37
PF.3
PB.9
125
36
PH.7
PB.8
126
35
PH.6
PB.7
127
34
PH.5
PB.6
128
33
PH.4
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PB.2
PC.12
PC.11
PC.10
PC.9
PB.1
PB.0
VSS
VDD
PA.11
PA.10
PA.9
PA.8
PC.13
PD.12
PD.11
PD.10
PG.2
PG.3
PG.4
PF.11
PF.10
PF.9
PF.8
PF.7
PF.6
VDD
PF.5
PF.4
2
PB.4
PB.3
1
PB.5
LQFP128
M480 SERIES DATASHEET
NC
VDDIO power domain
Figure 4.1-10 LQFP-128 Pin Diagram (USB FS + USB HS)
May 08, 2020
Page 51 of 523
Rev 3.00
M480
4.1.11 LQFP-144 Pin Diagram
HSUSB_ID
HSUSB_VDD12_CAP
HSUSB_D+
HSUSB_VSS
HSUSB_D-
HSUSB_VBUS
HSUSB_VDD33
HSUSB_VRES
PA.15
PA.14
PA.13
PA.12
PD.13
PD.0
PD.1
PD.2
PD.3
PG.15
PG.14
PG.13
PG.12
PG.11
PG.10
PG.9
VDD
VSS
PC.0
PC.1
PC.2
PC.3
PC.4
PC.5
PD.8
PD.9
PF.1
PF.0
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
Corresponding Part Number: M487JIDAE
109
72
nRESET
PE.6
110
71
PE.15
PE.5
111
70
PE.14
PE.4
112
69
VDDIO
PE.3
113
68
PA.0
PE.2
114
67
PA.1
VSS
115
66
PA.2
VDD
116
65
PA.3
PE.1
117
64
PA.4
PE.0
118
63
PA.5
PH.8
119
62
LDO_CAP
PH.9
120
61
VDD
PH.10
121
60
VSS
PH.11
122
59
PA.6
PD.14
123
58
PA.7
PG.5
124
57
PC.6
PG.6
125
56
PC.7
PG.7
126
55
PC.8
PG.8
127
54
PE.13
VSS
128
53
PE.12
LDO_CAP
129
52
PE.11
VDD
130
51
PE.10
PC.14
131
50
PE.9
PB.15
132
49
PE.8
PB.14
133
48
VDD
PB.13
134
47
VSS
PB.12
135
46
PF.2
AVDD
136
45
PF.3
VREF
137
44
PH.7
AVSS
138
43
PH.6
PB.11
139
42
PH.5
PB.10
140
41
PH.4
PB.9
141
40
PH.3
PB.8
142
39
PH.2
PB.7
143
38
PH.1
PB.6
144
37
PH.0
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PD.10
VSS
VDD
PG.0
PG.1
PG.2
PG.3
PG.4
PF.11
PF.10
PF.9
PF.8
PF.7
PF.6
VBAT
PF.5
PF.4
13
PA.11
19
12
VDD
PD.11
11
VSS
18
10
PB.0
PD.12
9
PB.1
17
8
PC.9
PC.13
7
PC.10
16
6
PC.11
PA.8
5
PC.12
15
4
PB.2
PA.9
3
PB.3
14
2
PA.10
1
PB.4
LQFP144
PB.5
M480 SERIES DATASHEET
PE.7
VDDIO power domain
Figure 4.1-11 LQFP-144 Pin Diagram
May 08, 2020
Page 52 of 523
Rev 3.00
M480
4.2 M48xxIDAE Pin Description
4.2.1
M481 Series Pin Description
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.0 MFP0 means SYS_GPA_MFPL[3:0] = 0x0.
PA.9 MFP5 means SYS_GPA_MFPH[7:4] = 0x5.
32 48 64 Pin Name
Pin Pin Pin
48
1
PB.6
2
EADC0_CH6
A
MFP1
EADC0 channel 6 analog input.
EBI_nWRH
O
MFP2
EBI high byte write enable output pin
USCI1_DAT1
I/O
MFP4
USCI1 data 1 pin.
UART1_RXD
I
MFP6
UART1 data receiver input pin.
SD1_CLK
O
MFP7
SD/SDIO1 clock output pin
EBI_nCS1
O
MFP8
EBI chip select 1 output pin.
BPWM1_CH5
I/O
MFP10
BPWM1 channel 5 output/capture input.
I
MFP11
EPWM1 Brake 1 input pin.
I/O
MFP12
EPWM1 channel 5 output/capture input.
INT4
I
MFP13
External interrupt 4 input pin.
ACMP1_O
O
MFP15
Analog comparator 1 output pin.
PB.5
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH5
A
MFP1
EADC0 channel 5 analog input.
ACMP1_N
A
MFP1
Analog comparator 1 negative input pin.
EBI_ADR0
O
MFP2
EBI address bus bit 0.
SD0_DAT3
I/O
MFP3
SD/SDIO0 data line bit 3.
SPI1_MISO
I/O
MFP5
SPI1 MISO (Master In, Slave Out) pin.
I C0_SCL
I/O
MFP6
I2C0 clock pin.
UART5_TXD
O
MFP7
UART5 data transmitter output pin.
USCI1_CTL0
I/O
MFP8
USCI1 control 0 pin.
SC0_CLK
O
MFP9
Smart Card 0 clock pin.
I S0_BCLK
O
MFP10
I2S0 bit clock output pin.
EPWM0_CH0
I/O
MFP11
EPWM0 channel 0 output/capture input.
TM0
I/O
MFP14
Timer0 event counter input/toggle output pin.
INT0
I
MFP15
External interrupt 0 input pin.
PB.4
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC0 channel 4 analog input.
2
2
3
EADC0_CH4
May 08, 2020
Page 53 of 523
M480 SERIES DATASHEET
General purpose digital I/O pin.
2
2
Description
MFP0
EPWM1_CH5
1
MFP
I/O
EPWM1_BRAKE1
1
Type
Rev 3.00
M480
32 48 64 Pin Name
Pin Pin Pin
4
MFP1
Analog comparator 1 positive input 1 pin.
EBI_ADR1
O
MFP2
EBI address bus bit 1.
SD0_DAT2
I/O
MFP3
SD/SDIO0 data line bit 2.
SPI1_MOSI
I/O
MFP5
SPI1 MOSI (Master Out, Slave In) pin.
I/O
MFP6
I2C0 data input/output pin.
UART5_RXD
I
MFP7
UART5 data receiver input pin.
USCI1_CTL1
I/O
MFP8
USCI1 control 1 pin.
SC0_DAT
I/O
MFP9
Smart Card 0 data pin.
I2S0_MCLK
O
MFP10
I2S0 master clock output pin.
EPWM0_CH1
I/O
MFP11
EPWM0 channel 1 output/capture input.
TM1
I/O
MFP14
Timer1 event counter input/toggle output pin.
INT1
I
MFP15
External interrupt 1 input pin.
PB.3
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH3
A
MFP1
EADC0 channel 3 analog input.
ACMP0_N
A
MFP1
Analog comparator 0 negative input pin.
EBI_ADR2
O
MFP2
EBI address bus bit 2.
SD0_DAT1
I/O
MFP3
SD/SDIO0 data line bit 1.
SPI1_CLK
I/O
MFP5
SPI1 serial clock pin.
UART1_TXD
O
MFP6
UART1 data transmitter output pin.
UART5_nRTS
O
MFP7
UART5 request to Send output pin.
USCI1_DAT1
I/O
MFP8
USCI1 data 1 pin.
SC0_RST
O
MFP9
Smart Card 0 reset pin.
I
MFP10
I2S0 data input pin.
EPWM0_CH2
I/O
MFP11
EPWM0 channel 2 output/capture input.
TM2
I/O
MFP14
Timer2 event counter input/toggle output pin.
INT2
I
MFP15
External interrupt 2 input pin.
PB.2
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH2
A
MFP1
EADC0 channel 2 analog input.
ACMP0_P1
A
MFP1
Analog comparator 0 positive input 1 pin.
OPA0_O
A
MFP1
Operational amplifier 0 output pin.
EBI_ADR3
O
MFP2
EBI address bus bit 3.
SD0_DAT0
I/O
MFP3
SD/SDIO0 data line bit 0.
SPI1_SS
I/O
MFP5
SPI1 slave select pin.
I
MFP6
UART1 data receiver input pin.
M480 SERIES DATASHEET
2
I S0_DI
4
4
5
Description
A
I C0_SDA
3
MFP
ACMP1_P1
2
3
Type
UART1_RXD
May 08, 2020
Page 54 of 523
Rev 3.00
M480
32 48 64 Pin Name
Pin Pin Pin
5
5
6
MFP7
UART5 clear to Send input pin.
USCI1_DAT0
I/O
MFP8
USCI1 data 0 pin.
SC0_PWR
O
MFP9
Smart Card 0 power pin.
I2S0_DO
O
MFP10
I2S0 data output pin.
EPWM0_CH3
I/O
MFP11
EPWM0 channel 3 output/capture input.
TM3
I/O
MFP14
Timer3 event counter input/toggle output pin.
INT3
I
MFP15
External interrupt 3 input pin.
PB.1
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH1
A
MFP1
EADC0 channel 1 analog input.
OPA0_N
A
MFP1
Operational amplifier 0 negative input pin.
EBI_ADR8
O
MFP2
EBI address bus bit 8.
SD0_CLK
O
MFP3
SD/SDIO0 clock output pin
SPI1_I2SMCLK
I/O
MFP5
SPI1 I2S master clock output pin
SPI3_I2SMCLK
I/O
MFP6
SPI3 I2S master clock output pin
UART2_TXD
O
MFP7
UART2 data transmitter output pin.
USCI1_CLK
I/O
MFP8
USCI1 clock pin.
I C1_SCL
I/O
MFP9
I2C1 clock pin.
I2S0_LRCK
O
MFP10
I2S0 left right channel clock output pin.
EPWM0_CH4
I/O
MFP11
EPWM0 channel 4 output/capture input.
EPWM1_CH4
I/O
MFP12
EPWM1 channel 4 output/capture input.
I
MFP13
EPWM0 Brake 0 input pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH0
A
MFP1
EADC0 channel 0 analog input.
OPA0_P
A
MFP1
Operational amplifier 0 positive input pin.
EBI_ADR9
O
MFP2
EBI address bus bit 9.
SD0_CMD
I/O
MFP3
SD/SDIO0 command/response pin
I
MFP7
UART2 data receiver input pin.
SPI0_I2SMCLK
I/O
MFP8
SPI0 I2S master clock output pin
I2C1_SDA
I/O
MFP9
I2C1 data input/output pin.
EPWM0_CH5
I/O
MFP11
EPWM0 channel 5 output/capture input.
EPWM1_CH5
I/O
MFP12
EPWM1 channel 5 output/capture input.
I
MFP13
EPWM0 Brake 1 input pin.
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
Analog comparator 0 positive input 0 pin.
PB.0
UART2_RXD
EPWM0_BRAKE1
7
8
PA.11
ACMP0_P0
May 08, 2020
Page 55 of 523
M480 SERIES DATASHEET
7
Description
I
EPWM0_BRAKE0
6
MFP
UART5_nCTS
2
6
Type
Rev 3.00
M480
32 48 64 Pin Name
Pin Pin Pin
8
9
MFP
Description
EBI_nRD
O
MFP2
EBI read enable output pin.
SC2_PWR
O
MFP3
Smart Card 2 power pin.
SPI2_SS
I/O
MFP4
SPI2 slave select pin.
SD1_DAT3
I/O
MFP5
SD/SDIO1 data line bit 3.
USCI0_CLK
I/O
MFP6
USCI0 clock pin.
I2C2_SCL
I/O
MFP7
I2C2 clock pin.
BPWM0_CH0
I/O
MFP9
BPWM0 channel 0 output/capture input.
EPWM0_SYNC_OUT
O
MFP10
EPWM0 counter synchronous trigger output pin.
TM0_EXT
I/O
MFP13
Timer0 event counter input/toggle output pin.
DAC1_ST
I
MFP14
DAC1 external trigger input.
I/O
MFP0
General purpose digital I/O pin.
ACMP1_P0
A
MFP1
Analog comparator 1 positive input 0 pin.
OPA1_O
A
MFP1
Operational amplifier 1 output pin.
EBI_nWR
O
MFP2
EBI write enable output pin.
SC2_RST
O
MFP3
Smart Card 2 reset pin.
SPI2_CLK
I/O
MFP4
SPI2 serial clock pin.
SD1_DAT2
I/O
MFP5
SD/SDIO1 data line bit 2.
USCI0_DAT0
I/O
MFP6
USCI0 data 0 pin.
I C2_SDA
I/O
MFP7
I2C2 data input/output pin.
BPWM0_CH1
I/O
MFP9
BPWM0 channel 1 output/capture input.
QEI1_INDEX
I
MFP10
Quadrature encoder 1 index input
ECAP0_IC0
I
MFP11
Enhanced capture unit 0 input 0 pin.
TM1_EXT
I/O
MFP13
Timer1 event counter input/toggle output pin.
DAC0_ST
I
MFP14
DAC0 external trigger input.
SWDH_CLK
O
MFP15
Serial Wire Debug Host Clock output
I/O
MFP0
General purpose digital I/O pin.
OPA1_N
A
MFP1
Operational amplifier 1 negative input pin.
EBI_MCLK
O
MFP2
EBI external clock output pin.
SC2_DAT
I/O
MFP3
Smart Card 2 data pin.
SPI2_MISO
I/O
MFP4
SPI2 MISO (Master In, Slave Out) pin.
SD1_DAT1
I/O
MFP5
SD/SDIO1 data line bit 1.
USCI0_DAT1
I/O
MFP6
USCI0 data 1 pin.
UART1_TXD
O
MFP7
UART1 data transmitter output pin.
BPWM0_CH2
I/O
MFP9
BPWM0 channel 2 output/capture input.
PA.10
2
M480 SERIES DATASHEET
9
Type
10 PA.9
May 08, 2020
Page 56 of 523
Rev 3.00
M480
32 48 64 Pin Name
Pin Pin Pin
10
Description
MFP10
Quadrature encoder 1 phase A input
ECAP0_IC1
I
MFP11
Enhanced capture unit 0 input 1 pin.
TM2_EXT
I/O
MFP13
Timer2 event counter input/toggle output pin.
SWDH_DAT
I/O
MFP15
Serial Wire Debug Host Data input/output pin
I/O
MFP0
General purpose digital I/O pin.
OPA1_P
A
MFP1
Operational amplifier 1 positive input pin.
EBI_ALE
O
MFP2
EBI address latch enable output pin.
SC2_CLK
O
MFP3
Smart Card 2 clock pin.
SPI2_MOSI
I/O
MFP4
SPI2 MOSI (Master Out, Slave In) pin.
SD1_DAT0
I/O
MFP5
SD/SDIO1 data line bit 0.
USCI0_CTL1
I/O
MFP6
USCI0 control 1 pin.
UART1_RXD
I
MFP7
UART1 data receiver input pin.
BPWM0_CH3
I/O
MFP9
BPWM0 channel 3 output/capture input.
QEI1_B
I
MFP10
Quadrature encoder 1 phase B input
ECAP0_IC2
I
MFP11
Enhanced capture unit 0 input 2 pin.
I/O
MFP13
Timer3 event counter input/toggle output pin.
I
MFP15
External interrupt 4 input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR19
O
MFP2
EBI address bus bit 19.
SC0_CLK
O
MFP3
Smart Card 0 clock pin.
I S0_LRCK
O
MFP4
I2S0 left right channel clock output pin.
SPI0_MOSI
I/O
MFP5
SPI0 MOSI (Master Out, Slave In) pin.
UART4_RXD
I
MFP6
UART4 data receiver input pin.
EBI_nCS0
O
MFP7
EBI chip select 0 output pin.
TAMPER0
I/O
MFP10
TAMPER detector loop pin 0.
13 VDD
P
MFP0
Power supply for I/O ports and LDO source for internal PLL
and digital circuit.
14 PF.5
I/O
MFP0
General purpose digital I/O pin.
UART2_RXD
I
MFP2
UART2 data receiver input pin.
UART2_nCTS
I
MFP4
UART2 clear to Send input pin.
BPWM0_CH4
I/O
MFP8
BPWM0 channel 4 output/capture input.
EPWM0_SYNC_OUT
O
MFP9
EPWM0 counter synchronous trigger output pin.
X32_IN
I
MFP10
External 32.768 kHz crystal input pin.
EADC0_ST
I
MFP11
EADC0 external trigger input.
11 PA.8
12 PF.6
2
May 08, 2020
Page 57 of 523
Rev 3.00
M480 SERIES DATASHEET
I
INT4
11
MFP
QEI1_A
TM3_EXT
7
Type
M480
32 48 64 Pin Name
Pin Pin Pin
8
9
12
13
15 PF.4
Description
MFP0
General purpose digital I/O pin.
UART2_TXD
O
MFP2
UART2 data transmitter output pin.
UART2_nRTS
O
MFP4
UART2 request to Send output pin.
BPWM0_CH5
I/O
MFP8
BPWM0 channel 5 output/capture input.
X32_OUT
O
MFP10
External 32.768 kHz crystal output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_nCS0
O
MFP2
EBI chip select 0 output pin.
UART0_TXD
O
MFP3
UART0 data transmitter output pin.
I2C0_SCL
I/O
MFP4
I2C0 clock pin.
I
MFP10
External 4~24 MHz (high speed) crystal input pin.
I/O
MFP11
BPWM1 channel 0 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_nCS1
O
MFP2
EBI chip select 1 output pin.
UART0_RXD
I
MFP3
UART0 data receiver input pin.
I2C0_SDA
I/O
MFP4
I2C0 data input/output pin.
QSPI0_CLK
I/O
MFP5
QSPI0 serial clock pin.
XT1_OUT
O
MFP10
External 4~24 MHz (high speed) crystal output pin.
BPWM1_CH1
I/O
MFP11
BPWM1 channel 1 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD9
I/O
MFP2
EBI address/data bus bit 9.
SPI1_MISO
I/O
MFP4
SPI1 MISO (Master In, Slave Out) pin.
UART4_TXD
O
MFP5
UART4 data transmitter output pin.
SC2_PWR
O
MFP6
Smart Card 2 power pin.
UART0_nCTS
I
MFP7
UART0 clear to Send input pin.
I C1_SMBAL
O
MFP8
I2C1 SMBus SMBALTER pin
EPWM1_CH2
I/O
MFP11
EPWM1 channel 2 output/capture input.
BPWM1_CH0
I/O
MFP12
BPWM1 channel 0 output/capture input.
TM0
I/O
MFP14
Timer0 event counter input/toggle output pin.
INT3
I
MFP15
External interrupt 3 input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD8
I/O
MFP2
EBI address/data bus bit 8.
SPI1_MOSI
I/O
MFP4
SPI1 MOSI (Master Out, Slave In) pin.
UART4_RXD
I
MFP5
UART4 data receiver input pin.
SC2_RST
O
MFP6
Smart Card 2 reset pin.
16 PF.3
BPWM1_CH0
14
MFP
I/O
XT1_IN
10
Type
17 PF.2
18 PC.7
M480 SERIES DATASHEET
2
19 PC.6
May 08, 2020
Page 58 of 523
Rev 3.00
M480
32 48 64 Pin Name
Pin Pin Pin
15
MFP
Description
O
MFP7
UART0 request to Send output pin.
I2C1_SMBSUS
O
MFP8
I2C1 SMBus SMBSUS pin (PMBus CONTROL pin)
EPWM1_CH3
I/O
MFP11
EPWM1 channel 3 output/capture input.
BPWM1_CH1
I/O
MFP12
BPWM1 channel 1 output/capture input.
TM1
I/O
MFP14
Timer1 event counter input/toggle output pin.
INT2
I
MFP15
External interrupt 2 input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD7
I/O
MFP2
EBI address/data bus bit 7.
SPI1_CLK
I/O
MFP4
SPI1 serial clock pin.
SC2_DAT
I/O
MFP6
Smart Card 2 data pin.
UART0_TXD
O
MFP7
UART0 data transmitter output pin.
I C1_SCL
I/O
MFP8
I2C1 clock pin.
EPWM1_CH4
I/O
MFP11
EPWM1 channel 4 output/capture input.
BPWM1_CH2
I/O
MFP12
BPWM1 channel 2 output/capture input.
ACMP0_WLAT
I
MFP13
Analog comparator 0 window latch input pin
TM2
I/O
MFP14
Timer2 event counter input/toggle output pin.
INT1
I
MFP15
External interrupt 1 input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD6
I/O
MFP2
EBI address/data bus bit 6.
SPI1_SS
I/O
MFP4
SPI1 slave select pin.
SD1_nCD
I
MFP5
SD/SDIO1 card detect input pin
SC2_CLK
O
MFP6
Smart Card 2 clock pin.
UART0_RXD
I
MFP7
UART0 data receiver input pin.
I2C1_SDA
I/O
MFP8
I2C1 data input/output pin.
EPWM1_CH5
I/O
MFP11
EPWM1 channel 5 output/capture input.
BPWM1_CH3
I/O
MFP12
BPWM1 channel 3 output/capture input.
ACMP1_WLAT
I
MFP13
Analog comparator 1 window latch input pin
TM3
I/O
MFP14
Timer3 event counter input/toggle output pin.
INT0
I
MFP15
External interrupt 0 input pin.
22 VSS
P
MFP0
Ground pin for digital circuit.
23 VDD
P
MFP0
Power supply for I/O ports and LDO source for internal PLL
and digital circuit.
24 LDO_CAP
A
MFP0
LDO output pin.
20 PA.7
21 PA.6
M480 SERIES DATASHEET
UART0_nRTS
2
16
Type
Note: This pin needs to be connected with an external
capacitor.
May 08, 2020
Page 59 of 523
Rev 3.00
M480
32 48 64 Pin Name
Pin Pin Pin
17
18
25 PA.5
Description
M480 SERIES DATASHEET
MFP0
General purpose digital I/O pin.
SPIM_D2
I/O
MFP2
SPIM data 2 pin for Quad Mode I/O.
QSPI0_MISO1
I/O
MFP3
QSPI0 MISO1 (Master In, Slave Out) pin.
SPI1_I2SMCLK
I/O
MFP4
SPI1 I2S master clock output pin
SD1_CMD
I/O
MFP5
SD/SDIO1 command/response pin
SC2_nCD
I
MFP6
Smart Card 2 card detect pin.
UART0_nCTS
I
MFP7
UART0 clear to Send input pin.
UART5_TXD
O
MFP8
UART5 data transmitter output pin.
I2C0_SCL
I/O
MFP9
I2C0 clock pin.
BPWM0_CH5
I/O
MFP12
BPWM0 channel 5 output/capture input.
EPWM0_CH0
I/O
MFP13
EPWM0 channel 0 output/capture input.
QEI0_INDEX
I
MFP14
Quadrature encoder 0 index input
I/O
MFP0
General purpose digital I/O pin.
SPIM_D3
I/O
MFP2
SPIM data 3 pin for Quad Mode I/O.
QSPI0_MOSI1
I/O
MFP3
QSPI0 MOSI1 (Master Out, Slave In) pin.
SPI0_I2SMCLK
I/O
MFP4
SPI0 I2S master clock output pin
SD1_CLK
O
MFP5
SD/SDIO1 clock output pin
SC0_nCD
I
MFP6
Smart Card 0 card detect pin.
UART0_nRTS
O
MFP7
UART0 request to Send output pin.
UART5_RXD
I
MFP8
UART5 data receiver input pin.
I C0_SDA
I/O
MFP9
I2C0 data input/output pin.
BPWM0_CH4
I/O
MFP12
BPWM0 channel 4 output/capture input.
EPWM0_CH1
I/O
MFP13
EPWM0 channel 1 output/capture input.
I
MFP14
Quadrature encoder 0 phase A input
I/O
MFP0
General purpose digital I/O pin.
SPIM_SS
I/O
MFP2
SPIM slave select pin.
QSPI0_SS
I/O
MFP3
QSPI0 slave select pin.
SPI0_SS
I/O
MFP4
SPI0 slave select pin.
SD1_DAT3
I/O
MFP5
SD/SDIO1 data line bit 3.
SC0_PWR
O
MFP6
Smart Card 0 power pin.
UART4_TXD
O
MFP7
UART4 data transmitter output pin.
UART1_TXD
O
MFP8
UART1 data transmitter output pin.
I2C1_SCL
I/O
MFP9
I2C1 clock pin.
BPWM0_CH3
I/O
MFP12
BPWM0 channel 3 output/capture input.
26 PA.4
QEI0_A
19
MFP
I/O
2
11
Type
27 PA.3
May 08, 2020
Page 60 of 523
Rev 3.00
M480
32 48 64 Pin Name
Pin Pin Pin
EPWM0_CH2
13
20
21
EPWM0 channel 2 output/capture input.
I
MFP14
Quadrature encoder 0 phase B input
I/O
MFP0
General purpose digital I/O pin.
SPIM_CLK
I/O
MFP2
SPIM serial clock pin.
QSPI0_CLK
I/O
MFP3
QSPI0 serial clock pin.
SPI0_CLK
I/O
MFP4
SPI0 serial clock pin.
SD1_DAT2
I/O
MFP5
SD/SDIO1 data line bit 2.
SC0_RST
O
MFP6
Smart Card 0 reset pin.
UART4_RXD
I
MFP7
UART4 data receiver input pin.
UART1_RXD
I
MFP8
UART1 data receiver input pin.
I2C1_SDA
I/O
MFP9
I2C1 data input/output pin.
BPWM0_CH2
I/O
MFP12
BPWM0 channel 2 output/capture input.
EPWM0_CH3
I/O
MFP13
EPWM0 channel 3 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
SPIM_MISO
I/O
MFP2
SPIM MISO (Master In, Slave Out) pin.
QSPI0_MISO0
I/O
MFP3
QSPI0 MISO0 (Master In, Slave Out) pin.
SPI0_MISO
I/O
MFP4
SPI0 MISO (Master In, Slave Out) pin.
SD1_DAT1
I/O
MFP5
SD/SDIO1 data line bit 1.
SC0_DAT
I/O
MFP6
Smart Card 0 data pin.
UART0_TXD
O
MFP7
UART0 data transmitter output pin.
UART1_nCTS
I
MFP8
UART1 clear to Send input pin.
I2C2_SCL
I/O
MFP9
I2C2 clock pin.
BPWM0_CH1
I/O
MFP12
BPWM0 channel 1 output/capture input.
EPWM0_CH4
I/O
MFP13
EPWM0 channel 4 output/capture input.
I
MFP15
DAC1 external trigger input.
I/O
MFP0
General purpose digital I/O pin.
SPIM_MOSI
I/O
MFP2
SPIM MOSI (Master Out, Slave In) pin.
QSPI0_MOSI0
I/O
MFP3
QSPI0 MOSI0 (Master Out, Slave In) pin.
SPI0_MOSI
I/O
MFP4
SPI0 MOSI (Master Out, Slave In) pin.
SD1_DAT0
I/O
MFP5
SD/SDIO1 data line bit 0.
SC0_CLK
O
MFP6
Smart Card 0 clock pin.
UART0_RXD
I
MFP7
UART0 data receiver input pin.
UART1_nRTS
O
MFP8
UART1 request to Send output pin.
I/O
MFP9
I2C2 data input/output pin.
28 PA.2
29 PA.1
30 PA.0
2
I C2_SDA
May 08, 2020
Page 61 of 523
M480 SERIES DATASHEET
22
Description
MFP13
DAC1_ST
14
MFP
I/O
QEI0_B
12
Type
Rev 3.00
M480
32 48 64 Pin Name
Pin Pin Pin
Type
MFP
Description
BPWM0_CH0
I/O
MFP12
BPWM0 channel 0 output/capture input.
EPWM0_CH5
I/O
MFP13
EPWM0 channel 5 output/capture input.
I
MFP15
DAC0 external trigger input.
DAC0_ST
15
23
31 VDDIO
P
MFP0
Power supply for PA.0~PA.5.
16
24
32 nRESET
I
MFP0
External reset input: active LOW, with an internal pull-up.
Set this pin low reset to initial state.
Note: It is recommended to use 10 kΩ pull-up resistor and
10 uF capacitor on nRESET pin.
17
25
33 PF.0
I/O
MFP0
General purpose digital I/O pin.
UART1_TXD
O
MFP2
UART1 data transmitter output pin.
I2C1_SCL
I/O
MFP3
I2C1 clock pin.
BPWM1_CH0
I/O
MFP12
BPWM1 channel 0 output/capture input.
ICE_DAT
O
MFP14
Serial wired debugger data pin.
Note: It is recommended to use 100 kΩ pull-up resistor on
ICE_DAT pin.
18
26
34 PF.1
I/O
MFP0
General purpose digital I/O pin.
I
MFP2
UART1 data receiver input pin.
I C1_SDA
I/O
MFP3
I2C1 data input/output pin.
BPWM1_CH1
I/O
MFP12
BPWM1 channel 1 output/capture input.
I
MFP14
Serial wired debugger clock pin.
UART1_RXD
2
ICE_CLK
Note: It is recommended to use 100 kΩ pull-up resistor on
ICE_CLK pin.
M480 SERIES DATASHEET
27
35 PC.5
I/O
MFP0
General purpose digital I/O pin.
EBI_AD5
I/O
MFP2
EBI address/data bus bit 5.
SPIM_D2
I/O
MFP3
SPIM data 2 pin for Quad Mode I/O.
QSPI0_MISO1
I/O
MFP4
QSPI0 MISO1 (Master In, Slave Out) pin.
UART2_TXD
O
MFP8
UART2 data transmitter output pin.
I C1_SCL
I/O
MFP9
I2C1 clock pin.
UART4_TXD
O
MFP11
UART4 data transmitter output pin.
EPWM1_CH0
I/O
MFP12
EPWM1 channel 0 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD4
I/O
MFP2
EBI address/data bus bit 4.
SPIM_D3
I/O
MFP3
SPIM data 3 pin for Quad Mode I/O.
QSPI0_MOSI1
I/O
MFP4
QSPI0 MOSI1 (Master Out, Slave In) pin.
SC1_nCD
I
MFP5
Smart Card 1 card detect pin.
I2S0_BCLK
O
MFP6
I2S0 bit clock output pin.
SPI1_I2SMCLK
I/O
MFP7
SPI1 I2S master clock output pin
2
28
36 PC.4
May 08, 2020
Page 62 of 523
Rev 3.00
M480
32 48 64 Pin Name
Pin Pin Pin
UART2_RXD
I/O
MFP9
I2C1 data input/output pin.
UART4_RXD
I
MFP11
UART4 data receiver input pin.
EPWM1_CH1
I/O
MFP12
EPWM1 channel 1 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD3
I/O
MFP2
EBI address/data bus bit 3.
SPIM_SS
I/O
MFP3
SPIM slave select pin.
QSPI0_SS
I/O
MFP4
QSPI0 slave select pin.
SC1_PWR
O
MFP5
Smart Card 1 power pin.
I S0_MCLK
O
MFP6
I2S0 master clock output pin.
SPI1_MISO
I/O
MFP7
SPI1 MISO (Master In, Slave Out) pin.
UART2_nRTS
O
MFP8
UART2 request to Send output pin.
I2C0_SMBAL
O
MFP9
I2C0 SMBus SMBALTER pin
UART3_TXD
O
MFP11
UART3 data transmitter output pin.
EPWM1_CH2
I/O
MFP12
EPWM1 channel 2 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD2
I/O
MFP2
EBI address/data bus bit 2.
SPIM_CLK
I/O
MFP3
SPIM serial clock pin.
QSPI0_CLK
I/O
MFP4
QSPI0 serial clock pin.
SC1_RST
O
MFP5
Smart Card 1 reset pin.
I
MFP6
I2S0 data input pin.
I/O
MFP7
SPI1 MOSI (Master Out, Slave In) pin.
UART2_nCTS
I
MFP8
UART2 clear to Send input pin.
I2C0_SMBSUS
O
MFP9
I2C0 SMBus SMBSUS pin (PMBus CONTROL pin)
UART3_RXD
I
MFP11
UART3 data receiver input pin.
EPWM1_CH3
I/O
MFP12
EPWM1 channel 3 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD1
I/O
MFP2
EBI address/data bus bit 1.
SPIM_MISO
I/O
MFP3
SPIM MISO (Master In, Slave Out) pin.
QSPI0_MISO0
I/O
MFP4
QSPI0 MISO0 (Master In, Slave Out) pin.
SC1_DAT
I/O
MFP5
Smart Card 1 data pin.
I S0_DO
O
MFP6
I2S0 data output pin.
SPI1_CLK
I/O
MFP7
SPI1 serial clock pin.
UART2_TXD
O
MFP8
UART2 data transmitter output pin.
37 PC.3
38 PC.2
I S0_DI
SPI1_MOSI
31
39 PC.1
2
May 08, 2020
Page 63 of 523
Rev 3.00
M480 SERIES DATASHEET
UART2 data receiver input pin.
2
19
Description
MFP8
2
30
MFP
I
I2C1_SDA
29
Type
M480
32 48 64 Pin Name
Pin Pin Pin
Type
I2C0_SCL
I/O
MFP9
I2C0 clock pin.
EPWM1_CH4
I/O
MFP12
EPWM1 channel 4 output/capture input.
ACMP0_O
O
MFP14
Analog comparator 0 output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD0
I/O
MFP2
EBI address/data bus bit 0.
SPIM_MOSI
I/O
MFP3
SPIM MOSI (Master Out, Slave In) pin.
QSPI0_MOSI0
I/O
MFP4
QSPI0 MOSI0 (Master Out, Slave In) pin.
SC1_CLK
O
MFP5
Smart Card 1 clock pin.
I2S0_LRCK
O
MFP6
I2S0 left right channel clock output pin.
SPI1_SS
I/O
MFP7
SPI1 slave select pin.
I
MFP8
UART2 data receiver input pin.
I C0_SDA
I/O
MFP9
I2C0 data input/output pin.
EPWM1_CH5
I/O
MFP12
EPWM1 channel 5 output/capture input.
ACMP1_O
O
MFP14
Analog comparator 1 output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD10
I/O
MFP2
EBI address/data bus bit 10.
USCI0_CTL1
I/O
MFP3
USCI0 control 1 pin.
SPI0_SS
I/O
MFP4
SPI0 slave select pin.
UART3_nRTS
O
MFP5
UART3 request to Send output pin.
USCI1_CTL0
I/O
MFP6
USCI1 control 0 pin.
SC2_PWR
O
MFP7
Smart Card 2 power pin.
SC1_nCD
I
MFP8
Smart Card 1 card detect pin.
UART0_TXD
O
MFP9
UART0 data transmitter output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD11
I/O
MFP2
EBI address/data bus bit 11.
USCI0_DAT1
I/O
MFP3
USCI0 data 1 pin.
SPI0_CLK
I/O
MFP4
SPI0 serial clock pin.
UART3_nCTS
I
MFP5
UART3 clear to Send input pin.
SC2_RST
O
MFP7
Smart Card 2 reset pin.
UART0_RXD
I
MFP9
UART0 data receiver input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD12
I/O
MFP2
EBI address/data bus bit 12.
USCI0_DAT0
I/O
MFP3
USCI0 data 0 pin.
SPI0_MISO
I/O
MFP4
SPI0 MISO (Master In, Slave Out) pin.
20
32
40 PC.0
UART2_RXD
2
41 PD.3
M480 SERIES DATASHEET
42 PD.2
43 PD.1
May 08, 2020
MFP
Description
Page 64 of 523
Rev 3.00
M480
32 48 64 Pin Name
Pin Pin Pin
MFP5
UART3 data transmitter output pin.
I2C2_SCL
I/O
MFP6
I2C2 clock pin.
SC2_DAT
I/O
MFP7
Smart Card 2 data pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD13
I/O
MFP2
EBI address/data bus bit 13.
USCI0_CLK
I/O
MFP3
USCI0 clock pin.
SPI0_MOSI
I/O
MFP4
SPI0 MOSI (Master Out, Slave In) pin.
I
MFP5
UART3 data receiver input pin.
I2C2_SDA
I/O
MFP6
I2C2 data input/output pin.
SC2_CLK
O
MFP7
Smart Card 2 clock pin.
TM2
I/O
MFP14
Timer2 event counter input/toggle output pin.
I/O
MFP0
General purpose digital I/O pin.
I2S0_BCLK
O
MFP2
I2S0 bit clock output pin.
UART4_TXD
O
MFP3
UART4 data transmitter output pin.
I2C1_SCL
I/O
MFP4
I2C1 clock pin.
SPI2_SS
I/O
MFP5
SPI2 slave select pin.
SC2_PWR
O
MFP7
Smart Card 2 power pin.
BPWM1_CH2
I/O
MFP11
BPWM1 channel 2 output/capture input.
QEI1_INDEX
I
MFP12
Quadrature encoder 1 index input
34
46 PA.13
I/O
MFP0
General purpose digital I/O pin.
2
I S0_MCLK
O
MFP2
I2S0 master clock output pin.
UART4_RXD
I
MFP3
UART4 data receiver input pin.
I C1_SDA
I/O
MFP4
I2C1 data input/output pin.
SPI2_CLK
I/O
MFP5
SPI2 serial clock pin.
SC2_RST
O
MFP7
Smart Card 2 reset pin.
BPWM1_CH3
I/O
MFP11
BPWM1 channel 3 output/capture input.
I
MFP12
Quadrature encoder 1 phase A input
I/O
MFP0
General purpose digital I/O pin.
I2S0_DI
I
MFP2
I2S0 data input pin.
UART0_TXD
O
MFP3
UART0 data transmitter output pin.
SPI2_MISO
I/O
MFP5
SPI2 MISO (Master In, Slave Out) pin.
I C2_SCL
I/O
MFP6
I2C2 clock pin.
SC2_DAT
I/O
MFP7
Smart Card 2 data pin.
BPWM1_CH4
I/O
MFP11
BPWM1 channel 4 output/capture input.
45 PA.12
2
QEI1_A
23
35
47 PA.14
2
May 08, 2020
Page 65 of 523
M480 SERIES DATASHEET
22
Description
O
UART3_RXD
33
MFP
UART3_TXD
44 PD.0
21
Type
Rev 3.00
M480
32 48 64 Pin Name
Pin Pin Pin
QEI1_B
24
36
Type
MFP
Description
I
MFP12
Quadrature encoder 1 phase B input
48 PA.15
I/O
MFP0
General purpose digital I/O pin.
2
I S0_DO
O
MFP2
I2S0 data output pin.
UART0_RXD
I
MFP3
UART0 data receiver input pin.
SPI2_MOSI
I/O
MFP5
SPI2 MOSI (Master Out, Slave In) pin.
I2C2_SDA
I/O
MFP6
I2C2 data input/output pin.
SC2_CLK
O
MFP7
Smart Card 2 clock pin.
BPWM1_CH5
I/O
MFP11
BPWM1 channel 5 output/capture input.
I
MFP12
EPWM0 counter synchronous trigger input pin.
EPWM0_SYNC_IN
25
37
49 VSS
P
MFP0
Ground pin for digital circuit.
26
38
50 LDO_CAP
A
MFP0
LDO output pin.
Note: This pin needs to be connected with an external
capacitor.
27
M480 SERIES DATASHEET
P
MFP0
Power supply for I/O ports and LDO source for internal PLL
and digital circuit.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD11
I/O
MFP2
EBI address/data bus bit 11.
SC1_nCD
I
MFP3
Smart Card 1 card detect pin.
SPI0_I2SMCLK
I/O
MFP4
SPI0 I2S master clock output pin
USCI0_CTL0
I/O
MFP5
USCI0 control 0 pin.
QSPI0_CLK
I/O
MFP6
QSPI0 serial clock pin.
I
MFP11
EPWM0 counter synchronous trigger input pin.
I/O
MFP13
Timer1 event counter input/toggle output pin.
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC0 channel 15 analog input.
EBI_AD12
I/O
MFP2
EBI address/data bus bit 12.
SC1_PWR
O
MFP3
Smart Card 1 power pin.
SPI0_SS
I/O
MFP4
SPI0 slave select pin.
USCI0_CTL1
I/O
MFP5
USCI0 control 1 pin.
UART0_nCTS
I
MFP6
UART0 clear to Send input pin.
UART3_TXD
O
MFP7
UART3 data transmitter output pin.
I2C2_SMBAL
O
MFP8
I2C2 SMBus SMBALTER pin
EPWM1_CH0
I/O
MFP11
EPWM1 channel 0 output/capture input.
TM0_EXT
I/O
MFP13
Timer0 event counter input/toggle output pin.
I/O
MFP0
General purpose digital I/O pin.
39
51 VDD
40
52 PC.14
EPWM0_SYNC_IN
TM1
28
41
53 PB.15
EADC0_CH15
29
42
54 PB.14
May 08, 2020
Page 66 of 523
Rev 3.00
M480
32 48 64 Pin Name
Pin Pin Pin
EADC0_CH14
43
EADC0 channel 14 analog input.
EBI_AD13
I/O
MFP2
EBI address/data bus bit 13.
SC1_RST
O
MFP3
Smart Card 1 reset pin.
SPI0_CLK
I/O
MFP4
SPI0 serial clock pin.
USCI0_DAT1
I/O
MFP5
USCI0 data 1 pin.
UART0_nRTS
O
MFP6
UART0 request to Send output pin.
UART3_RXD
I
MFP7
UART3 data receiver input pin.
I C2_SMBSUS
O
MFP8
I2C2 SMBus SMBSUS pin (PMBus CONTROL pin)
EPWM1_CH1
I/O
MFP11
EPWM1 channel 1 output/capture input.
TM1_EXT
I/O
MFP13
Timer1 event counter input/toggle output pin.
CLKO
O
MFP14
Clock Out
55 PB.13
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH13
A
MFP1
EADC0 channel 13 analog input.
DAC1_OUT
A
MFP1
DAC1 channel analog output.
ACMP0_P3
A
MFP1
Analog comparator 0 positive input 3 pin.
ACMP1_P3
A
MFP1
Analog comparator 1 positive input 3 pin.
EBI_AD14
I/O
MFP2
EBI address/data bus bit 14.
SC1_DAT
I/O
MFP3
Smart Card 1 data pin.
SPI0_MISO
I/O
MFP4
SPI0 MISO (Master In, Slave Out) pin.
USCI0_DAT0
I/O
MFP5
USCI0 data 0 pin.
UART0_TXD
O
MFP6
UART0 data transmitter output pin.
UART3_nRTS
O
MFP7
UART3 request to Send output pin.
I C2_SCL
I/O
MFP8
I2C2 clock pin.
EPWM1_CH2
I/O
MFP11
EPWM1 channel 2 output/capture input.
TM2_EXT
I/O
MFP13
Timer2 event counter input/toggle output pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH12
A
MFP1
EADC0 channel 12 analog input.
DAC0_OUT
A
MFP1
DAC0 channel analog output.
ACMP0_P2
A
MFP1
Analog comparator 0 positive input 2 pin.
ACMP1_P2
A
MFP1
Analog comparator 1 positive input 2 pin.
EBI_AD15
I/O
MFP2
EBI address/data bus bit 15.
SC1_CLK
O
MFP3
Smart Card 1 clock pin.
SPI0_MOSI
I/O
MFP4
SPI0 MOSI (Master Out, Slave In) pin.
USCI0_CLK
I/O
MFP5
USCI0 clock pin.
56 PB.12
May 08, 2020
Page 67 of 523
M480 SERIES DATASHEET
44
Description
MFP1
2
31
MFP
A
2
30
Type
Rev 3.00
M480
32 48 64 Pin Name
Pin Pin Pin
45
MFP
Description
UART0_RXD
I
MFP6
UART0 data receiver input pin.
UART3_nCTS
I
MFP7
UART3 clear to Send input pin.
I C2_SDA
I/O
MFP8
I2C2 data input/output pin.
SD0_nCD
I
MFP9
SD/SDIO0 card detect input pin
EPWM1_CH3
I/O
MFP11
EPWM1 channel 3 output/capture input.
TM3_EXT
I/O
MFP13
Timer3 event counter input/toggle output pin.
57 AVDD
P
MFP0
Power supply for internal analog circuit.
58 VREF
A
MFP0
ADC reference voltage input.
2
32
Type
Note: This pin needs to be connected with a 1uF capacitor.
46
59 AVSS
P
MFP0
Ground pin for analog circuit.
60 PB.11
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH11
A
MFP1
EADC0 channel 11 analog input.
EBI_ADR16
O
MFP2
EBI address bus bit 16.
UART0_nCTS
I
MFP5
UART0 clear to Send input pin.
UART4_TXD
O
MFP6
UART4 data transmitter output pin.
I C1_SCL
I/O
MFP7
I2C1 clock pin.
SPI0_I2SMCLK
I/O
MFP9
SPI0 I2S master clock output pin
BPWM1_CH0
I/O
MFP10
BPWM1 channel 0 output/capture input.
SPI3_CLK
I/O
MFP11
SPI3 serial clock pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH10
A
MFP1
EADC0 channel 10 analog input.
EBI_ADR17
O
MFP2
EBI address bus bit 17.
USCI1_CTL0
I/O
MFP4
USCI1 control 0 pin.
UART0_nRTS
O
MFP5
UART0 request to Send output pin.
UART4_RXD
I
MFP6
UART4 data receiver input pin.
I2C1_SDA
I/O
MFP7
I2C1 data input/output pin.
BPWM1_CH1
I/O
MFP10
BPWM1 channel 1 output/capture input.
SPI3_SS
I/O
MFP11
SPI3 slave select pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH9
A
MFP1
EADC0 channel 9 analog input.
EBI_ADR18
O
MFP2
EBI address bus bit 18.
USCI1_CTL1
I/O
MFP4
USCI1 control 1 pin.
UART0_TXD
O
MFP5
UART0 data transmitter output pin.
UART1_nCTS
I
MFP6
UART1 clear to Send input pin.
2
M480 SERIES DATASHEET
61 PB.10
62 PB.9
May 08, 2020
Page 68 of 523
Rev 3.00
M480
32 48 64 Pin Name
Pin Pin Pin
MFP
Description
O
MFP7
I2C1 SMBus SMBALTER pin
BPWM1_CH2
I/O
MFP10
BPWM1 channel 2 output/capture input.
SPI3_MISO
I/O
MFP11
SPI3 MISO (Master In, Slave Out) pin.
I
MFP13
External interrupt 7 input pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH8
A
MFP1
EADC0 channel 8 analog input.
EBI_ADR19
O
MFP2
EBI address bus bit 19.
USCI1_CLK
I/O
MFP4
USCI1 clock pin.
UART0_RXD
I
MFP5
UART0 data receiver input pin.
UART1_nRTS
O
MFP6
UART1 request to Send output pin.
I2C1_SMBSUS
O
MFP7
I2C1 SMBus SMBSUS pin (PMBus CONTROL pin)
BPWM1_CH3
I/O
MFP10
BPWM1 channel 3 output/capture input.
SPI3_MOSI
I/O
MFP11
SPI3 MOSI (Master Out, Slave In) pin.
I
MFP13
External interrupt 6 input pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH7
A
MFP1
EADC0 channel 7 analog input.
EBI_nWRL
O
MFP2
EBI low byte write enable output pin.
USCI1_DAT0
I/O
MFP4
USCI1 data 0 pin.
UART1_TXD
O
MFP6
UART1 data transmitter output pin.
SD1_CMD
I/O
MFP7
SD/SDIO1 command/response pin
EBI_nCS0
O
MFP8
EBI chip select 0 output pin.
BPWM1_CH4
I/O
MFP10
BPWM1 channel 4 output/capture input.
I
MFP11
EPWM1 Brake 0 input pin.
I/O
MFP12
EPWM1 channel 4 output/capture input.
INT5
I
MFP13
External interrupt 5 input pin.
ACMP0_O
O
MFP15
Analog comparator 0 output pin.
63 PB.8
INT6
64 PB.7
EPWM1_BRAKE0
EPWM1_CH4
May 08, 2020
Page 69 of 523
M480 SERIES DATASHEET
I2C1_SMBAL
INT7
47
Type
Rev 3.00
M480
4.2.2
M482 Series Pin Description
Note: PA.15 MFP can only be as USB_OTG_ID when enable full-Speed USB.
32 48 64 128 Pin Name
Pin Pin Pin Pin
1
2
1
2
2
3
1
2
M480 SERIES DATASHEET
3
3
4
3
May 08, 2020
PB.5
Type
MFP
Description
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH5
A
MFP1
EADC0 channel 5 analog input.
ACMP1_N
A
MFP1
Analog comparator 1 negative input pin.
EBI_ADR0
O
MFP2
EBI address bus bit 0.
SD0_DAT3
I/O
MFP3
SD/SDIO0 data line bit 3.
SPI1_MISO
I/O
MFP5
SPI1 MISO (Master In, Slave Out) pin.
I2C0_SCL
I/O
MFP6
I2C0 clock pin.
UART5_TXD
O
MFP7
UART5 data transmitter output pin.
USCI1_CTL0
I/O
MFP8
USCI1 control 0 pin.
SC0_CLK
O
MFP9
Smart Card 0 clock pin.
I2S0_BCLK
O
MFP10
I2S0 bit clock output pin.
EPWM0_CH0
I/O
MFP11
EPWM0 channel 0 output/capture input.
TM0
I/O
MFP14
Timer0 event counter input/toggle output pin.
INT0
I
MFP15
External interrupt 0 input pin.
PB.4
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH4
A
MFP1
EADC0 channel 4 analog input.
ACMP1_P1
A
MFP1
Analog comparator 1 positive input 1 pin.
EBI_ADR1
O
MFP2
EBI address bus bit 1.
SD0_DAT2
I/O
MFP3
SD/SDIO0 data line bit 2.
SPI1_MOSI
I/O
MFP5
SPI1 MOSI (Master Out, Slave In) pin.
I2C0_SDA
I/O
MFP6
I2C0 data input/output pin.
UART5_RXD
I
MFP7
UART5 data receiver input pin.
USCI1_CTL1
I/O
MFP8
USCI1 control 1 pin.
SC0_DAT
I/O
MFP9
Smart Card 0 data pin.
I2S0_MCLK
O
MFP10
I2S0 master clock output pin.
EPWM0_CH1
I/O
MFP11
EPWM0 channel 1 output/capture input.
TM1
I/O
MFP14
Timer1 event counter input/toggle output pin.
INT1
I
MFP15
External interrupt 1 input pin.
PB.3
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH3
A
MFP1
EADC0 channel 3 analog input.
ACMP0_N
A
MFP1
Analog comparator 0 negative input pin.
EBI_ADR2
O
MFP2
EBI address bus bit 2.
Page 70 of 523
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
4
4
5
4
May 08, 2020
MFP
Description
SD0_DAT1
I/O
MFP3
SD/SDIO0 data line bit 1.
SPI1_CLK
I/O
MFP5
SPI1 serial clock pin.
UART1_TXD
O
MFP6
UART1 data transmitter output pin.
UART5_nRTS
O
MFP7
UART5 request to Send output pin.
USCI1_DAT1
I/O
MFP8
USCI1 data 1 pin.
SC0_RST
O
MFP9
Smart Card 0 reset pin.
I2S0_DI
I
MFP10
I2S0 data input pin.
EPWM0_CH2
I/O
MFP11
EPWM0 channel 2 output/capture input.
TM2
I/O
MFP14
Timer2 event counter input/toggle output pin.
INT2
I
MFP15
External interrupt 2 input pin.
PB.2
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH2
A
MFP1
EADC0 channel 2 analog input.
ACMP0_P1
A
MFP1
Analog comparator 0 positive input 1 pin.
OPA0_O
A
MFP1
Operational amplifier 0 output pin.
EBI_ADR3
O
MFP2
EBI address bus bit 3.
SD0_DAT0
I/O
MFP3
SD/SDIO0 data line bit 0.
SPI1_SS
I/O
MFP5
SPI1 slave select pin.
UART1_RXD
I
MFP6
UART1 data receiver input pin.
UART5_nCTS
I
MFP7
UART5 clear to Send input pin.
USCI1_DAT0
I/O
MFP8
USCI1 data 0 pin.
SC0_PWR
O
MFP9
Smart Card 0 power pin.
I2S0_DO
O
MFP10
I2S0 data output pin.
EPWM0_CH3
I/O
MFP11
EPWM0 channel 3 output/capture input.
TM3
I/O
MFP14
Timer3 event counter input/toggle output pin.
INT3
I
MFP15
External interrupt 3 input pin.
PC.12
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR4
O
MFP2
EBI address bus bit 4.
UART0_TXD
O
MFP3
UART0 data transmitter output pin.
I2C0_SCL
I/O
MFP4
I2C0 clock pin.
SPI3_MISO
I/O
MFP6
SPI3 MISO (Master In, Slave Out) pin.
SC0_nCD
I
MFP9
Smart Card 0 card detect pin.
ECAP1_IC2
I
MFP11
Enhanced capture unit 1 input 2 pin.
EPWM1_CH0
I/O
MFP12
EPWM1 channel 0 output/capture input.
ACMP0_O
O
MFP14
Analog comparator 0 output pin.
Page 71 of 523
M480 SERIES DATASHEET
5
Type
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
6
7
8
M480 SERIES DATASHEET
5
5
6
9
May 08, 2020
Type
MFP
Description
PC.11
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR5
O
MFP2
EBI address bus bit 5.
UART0_RXD
I
MFP3
UART0 data receiver input pin.
I2C0_SDA
I/O
MFP4
I2C0 data input/output pin.
SPI3_MOSI
I/O
MFP6
SPI3 MOSI (Master Out, Slave In) pin.
ECAP1_IC1
I
MFP11
Enhanced capture unit 1 input 1 pin.
EPWM1_CH1
I/O
MFP12
EPWM1 channel 1 output/capture input.
ACMP1_O
O
MFP14
Analog comparator 1 output pin.
PC.10
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR6
O
MFP2
EBI address bus bit 6.
SPI3_CLK
I/O
MFP6
SPI3 serial clock pin.
UART3_TXD
O
MFP7
UART3 data transmitter output pin.
CAN1_TXD
O
MFP9
CAN1 bus transmitter output.
ECAP1_IC0
I
MFP11
Enhanced capture unit 1 input 0 pin.
EPWM1_CH2
I/O
MFP12
EPWM1 channel 2 output/capture input.
PC.9
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR7
O
MFP2
EBI address bus bit 7.
SPI3_SS
I/O
MFP6
SPI3 slave select pin.
UART3_RXD
I
MFP7
UART3 data receiver input pin.
CAN1_RXD
I
MFP9
CAN1 bus receiver input.
EPWM1_CH3
I/O
MFP12
EPWM1 channel 3 output/capture input.
PB.1
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH1
A
MFP1
EADC0 channel 1 analog input.
OPA0_N
A
MFP1
Operational amplifier 0 negative input pin.
EBI_ADR8
O
MFP2
EBI address bus bit 8.
SD0_CLK
O
MFP3
SD/SDIO0 clock output pin
SPI1_I2SMCLK
I/O
MFP5
SPI1 I2S master clock output pin
SPI3_I2SMCLK
I/O
MFP6
SPI3 I2S master clock output pin
UART2_TXD
O
MFP7
UART2 data transmitter output pin.
USCI1_CLK
I/O
MFP8
USCI1 clock pin.
I2C1_SCL
I/O
MFP9
I2C1 clock pin.
I2S0_LRCK
O
MFP10
I2S0 left right channel clock output pin.
EPWM0_CH4
I/O
MFP11
EPWM0 channel 4 output/capture input.
EPWM1_CH4
I/O
MFP12
EPWM1 channel 4 output/capture input.
Page 72 of 523
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
EPWM0_BRAKE0
6
6
7
9
Description
MFP13
EPWM0 Brake 0 input pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH0
A
MFP1
EADC0 channel 0 analog input.
OPA0_P
A
MFP1
Operational amplifier 0 positive input pin.
EBI_ADR9
O
MFP2
EBI address bus bit 9.
SD0_CMD
I/O
MFP3
SD/SDIO0 command/response pin
I
MFP7
UART2 data receiver input pin.
SPI0_I2SMCLK
I/O
MFP8
SPI0 I2S master clock output pin
I2C1_SDA
I/O
MFP9
I2C1 data input/output pin.
EPWM0_CH5
I/O
MFP11
EPWM0 channel 5 output/capture input.
EPWM1_CH5
I/O
MFP12
EPWM1 channel 5 output/capture input.
EPWM0_BRAKE1
I
MFP13
EPWM0 Brake 1 input pin.
11
VSS
P
MFP0
Ground pin for digital circuit.
12
VDD
P
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
13
PA.11
I/O
MFP0
General purpose digital I/O pin.
ACMP0_P0
A
MFP1
Analog comparator 0 positive input 0 pin.
EBI_nRD
O
MFP2
EBI read enable output pin.
SC2_PWR
O
MFP3
Smart Card 2 power pin.
SPI2_SS
I/O
MFP4
SPI2 slave select pin.
SD1_DAT3
I/O
MFP5
SD/SDIO1 data line bit 3.
USCI0_CLK
I/O
MFP6
USCI0 clock pin.
I2C2_SCL
I/O
MFP7
I2C2 clock pin.
BPWM0_CH0
I/O
MFP9
BPWM0 channel 0 output/capture input.
EPWM0_SYNC_OUT
O
MFP10
EPWM0 counter synchronous trigger output pin.
TM0_EXT
I/O
MFP13
Timer0 external capture input/toggle output pin.
DAC1_ST
I
MFP14
DAC1 external trigger input.
I/O
MFP0
General purpose digital I/O pin.
ACMP1_P0
A
MFP1
Analog comparator 1 positive input 0 pin.
OPA1_O
A
MFP1
Operational amplifier 1 output pin.
EBI_nWR
O
MFP2
EBI write enable output pin.
SC2_RST
O
MFP3
Smart Card 2 reset pin.
SPI2_CLK
I/O
MFP4
SPI2 serial clock pin.
SD1_DAT2
I/O
MFP5
SD/SDIO1 data line bit 2.
10
PB.0
14
May 08, 2020
PA.10
Page 73 of 523
Rev 3.00
M480 SERIES DATASHEET
8
8
MFP
I
UART2_RXD
7
Type
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
9
M480 SERIES DATASHEET
10
10
11
15
16
Description
I/O
MFP6
USCI0 data 0 pin.
I2C2_SDA
I/O
MFP7
I2C2 data input/output pin.
BPWM0_CH1
I/O
MFP9
BPWM0 channel 1 output/capture input.
QEI1_INDEX
I
MFP10
Quadrature encoder 1 index input
ECAP0_IC0
I
MFP11
Enhanced capture unit 0 input 0 pin.
TM1_EXT
I/O
MFP13
Timer1 external capture input/toggle output pin.
DAC0_ST
I
MFP14
DAC0 external trigger input.
I/O
MFP0
General purpose digital I/O pin.
OPA1_N
A
MFP1
Operational amplifier 1 negative input pin.
EBI_MCLK
O
MFP2
EBI external clock output pin.
SC2_DAT
I/O
MFP3
Smart Card 2 data pin.
SPI2_MISO
I/O
MFP4
SPI2 MISO (Master In, Slave Out) pin.
SD1_DAT1
I/O
MFP5
SD/SDIO1 data line bit 1.
USCI0_DAT1
I/O
MFP6
USCI0 data 1 pin.
UART1_TXD
O
MFP7
UART1 data transmitter output pin.
BPWM0_CH2
I/O
MFP9
BPWM0 channel 2 output/capture input.
QEI1_A
I
MFP10
Quadrature encoder 1 phase A input
ECAP0_IC1
I
MFP11
Enhanced capture unit 0 input 1 pin.
TM2_EXT
I/O
MFP13
Timer2 external capture input/toggle output pin.
PA.8
I/O
MFP0
General purpose digital I/O pin.
OPA1_P
A
MFP1
Operational amplifier 1 positive input pin.
EBI_ALE
O
MFP2
EBI address latch enable output pin.
SC2_CLK
O
MFP3
Smart Card 2 clock pin.
SPI2_MOSI
I/O
MFP4
SPI2 MOSI (Master Out, Slave In) pin.
SD1_DAT0
I/O
MFP5
SD/SDIO1 data line bit 0.
USCI0_CTL1
I/O
MFP6
USCI0 control 1 pin.
UART1_RXD
I
MFP7
UART1 data receiver input pin.
BPWM0_CH3
I/O
MFP9
BPWM0 channel 3 output/capture input.
QEI1_B
I
MFP10
Quadrature encoder 1 phase B input
ECAP0_IC2
I
MFP11
Enhanced capture unit 0 input 2 pin.
I/O
MFP13
Timer3 external capture input/toggle output pin.
I
MFP15
External interrupt 4 input pin.
PC.13
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR10
O
MFP2
EBI address bus bit 10.
PA.9
INT4
May 08, 2020
MFP
USCI0_DAT0
TM3_EXT
17
Type
Page 74 of 523
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
SC2_nCD
18
19
21
May 08, 2020
MFP
Description
I
MFP3
Smart Card 2 card detect pin.
SPI2_I2SMCLK
I/O
MFP4
SPI2 I2S master clock output pin
CAN1_TXD
O
MFP5
CAN1 bus transmitter output.
USCI0_CTL0
I/O
MFP6
USCI0 control 0 pin.
UART2_TXD
O
MFP7
UART2 data transmitter output pin.
BPWM0_CH4
I/O
MFP9
BPWM0 channel 4 output/capture input.
CLKO
O
MFP13
Clock Out
EADC0_ST
I
MFP14
EADC0 external trigger input.
I/O
MFP0
General purpose digital I/O pin.
OPA2_O
A
MFP1
Operational amplifier 2 output pin.
EBI_nCS0
O
MFP2
EBI chip select 0 output pin.
CAN1_RXD
I
MFP5
CAN1 bus receiver input.
UART2_RXD
I
MFP7
UART2 data receiver input pin.
BPWM0_CH5
I/O
MFP9
BPWM0 channel 5 output/capture input.
QEI0_INDEX
I
MFP10
Quadrature encoder 0 index input
CLKO
O
MFP13
Clock Out
EADC0_ST
I
MFP14
EADC0 external trigger input.
INT5
I
MFP15
External interrupt 5 input pin.
I/O
MFP0
General purpose digital I/O pin.
OPA2_N
A
MFP1
Operational amplifier 2 negative input pin.
EBI_nCS1
O
MFP2
EBI chip select 1 output pin.
UART1_TXD
O
MFP3
UART1 data transmitter output pin.
CAN0_TXD
O
MFP4
CAN0 bus transmitter output.
QEI0_A
I
MFP10
Quadrature encoder 0 phase A input
INT6
I
MFP15
External interrupt 6 input pin.
I/O
MFP0
General purpose digital I/O pin.
OPA2_P
A
MFP1
Operational amplifier 2 positive input pin.
EBI_nCS2
O
MFP2
EBI chip select 2 output pin.
UART1_RXD
I
MFP3
UART1 data receiver input pin.
CAN0_RXD
I
MFP4
CAN0 bus receiver input.
QEI0_B
I
MFP10
Quadrature encoder 0 phase B input
INT7
I
MFP15
External interrupt 7 input pin.
PG.2
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR11
O
MFP2
EBI address bus bit 11.
PD.12
PD.11
PD.10
Page 75 of 523
M480 SERIES DATASHEET
20
Type
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
22
23
24
M480 SERIES DATASHEET
25
26
27
May 08, 2020
Type
MFP
Description
SPI2_SS
I/O
MFP3
SPI2 slave select pin.
I2C0_SMBAL
O
MFP4
I2C0 SMBus SMBALTER pin
I2C1_SCL
I/O
MFP5
I2C1 clock pin.
TM0
I/O
MFP13
Timer0 event counter input/toggle output pin.
PG.3
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR12
O
MFP2
EBI address bus bit 12.
SPI2_CLK
I/O
MFP3
SPI2 serial clock pin.
I2C0_SMBSUS
O
MFP4
I2C0 SMBus SMBSUS pin (PMBus CONTROL pin)
I2C1_SDA
I/O
MFP5
I2C1 data input/output pin.
TM1
I/O
MFP13
Timer1 event counter input/toggle output pin.
PG.4
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR13
O
MFP2
EBI address bus bit 13.
SPI2_MISO
I/O
MFP3
SPI2 MISO (Master In, Slave Out) pin.
TM2
I/O
MFP13
Timer2 event counter input/toggle output pin.
PF.11
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR14
O
MFP2
EBI address bus bit 14.
SPI2_MOSI
I/O
MFP3
SPI2 MOSI (Master Out, Slave In) pin.
TAMPER5
I/O
MFP10
TAMPER detector loop pin 5.
TM3
I/O
MFP13
Timer3 event counter input/toggle output pin.
PF.10
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR15
O
MFP2
EBI address bus bit 15.
SC0_nCD
I
MFP3
Smart Card 0 card detect pin.
I2S0_BCLK
O
MFP4
I2S0 bit clock output pin.
SPI0_I2SMCLK
I/O
MFP5
SPI0 I2S master clock output pin
TAMPER4
I/O
MFP10
TAMPER detector loop pin 4.
PF.9
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR16
O
MFP2
EBI address bus bit 16.
SC0_PWR
O
MFP3
Smart Card 0 power pin.
I2S0_MCLK
O
MFP4
I2S0 master clock output pin.
SPI0_SS
I/O
MFP5
SPI0 slave select pin.
TAMPER3
I/O
MFP10
TAMPER detector loop pin 3.
PF.8
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR17
O
MFP2
EBI address bus bit 17.
SC0_RST
O
MFP3
Smart Card 0 reset pin.
Page 76 of 523
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
I2S0_DI
28
12
8
11
12
MFP
Description
I
MFP4
I2S0 data input pin.
SPI0_CLK
I/O
MFP5
SPI0 serial clock pin.
TAMPER2
I/O
MFP10
TAMPER detector loop pin 2.
PF.7
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR18
O
MFP2
EBI address bus bit 18.
SC0_DAT
I/O
MFP3
Smart Card 0 data pin.
I2S0_DO
O
MFP4
I2S0 data output pin.
SPI0_MISO
I/O
MFP5
SPI0 MISO (Master In, Slave Out) pin.
UART4_TXD
O
MFP6
UART4 data transmitter output pin.
TAMPER1
I/O
MFP10
TAMPER detector loop pin 1.
PF.6
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR19
O
MFP2
EBI address bus bit 19.
SC0_CLK
O
MFP3
Smart Card 0 clock pin.
I2S0_LRCK
O
MFP4
I2S0 left right channel clock output pin.
SPI0_MOSI
I/O
MFP5
SPI0 MOSI (Master Out, Slave In) pin.
UART4_RXD
I
MFP6
UART4 data receiver input pin.
EBI_nCS0
O
MFP7
EBI chip select 0 output pin.
TAMPER0
I/O
MFP10
TAMPER detector loop pin 0.
13
30
VDD
P
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
14
31
PF.5
I/O
MFP0
General purpose digital I/O pin.
UART2_RXD
I
MFP2
UART2 data receiver input pin.
UART2_nCTS
I
MFP4
UART2 clear to Send input pin.
BPWM0_CH4
I/O
MFP8
BPWM0 channel 4 output/capture input.
EPWM0_SYNC_OUT
O
MFP9
EPWM0 counter synchronous trigger output pin.
X32_IN
I
MFP10
External 32.768 kHz crystal input pin.
EADC0_ST
I
MFP11
EADC0 external trigger input.
PF.4
I/O
MFP0
General purpose digital I/O pin.
UART2_TXD
O
MFP2
UART2 data transmitter output pin.
UART2_nRTS
O
MFP4
UART2 request to Send output pin.
BPWM0_CH5
I/O
MFP8
BPWM0 channel 5 output/capture input.
X32_OUT
O
MFP10
External 32.768 kHz crystal output pin.
PH.4
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR3
O
MFP2
EBI address bus bit 3.
15
32
33
May 08, 2020
Page 77 of 523
Rev 3.00
M480 SERIES DATASHEET
7
29
Type
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
34
35
36
9
13
16
37
14
17
38
MFP
Description
SPI1_MISO
I/O
MFP3
SPI1 MISO (Master In, Slave Out) pin.
PH.5
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR2
O
MFP2
EBI address bus bit 2.
SPI1_MOSI
I/O
MFP3
SPI1 MOSI (Master Out, Slave In) pin.
PH.6
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR1
O
MFP2
EBI address bus bit 1.
SPI1_CLK
I/O
MFP3
SPI1 serial clock pin.
PH.7
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR0
O
MFP2
EBI address bus bit 0.
SPI1_SS
I/O
MFP3
SPI1 slave select pin.
PF.3
I/O
MFP0
General purpose digital I/O pin.
EBI_nCS0
O
MFP2
EBI chip select 0 output pin.
UART0_TXD
O
MFP3
UART0 data transmitter output pin.
I2C0_SCL
I/O
MFP4
I2C0 clock pin.
I
MFP10
External 4~24 MHz (high speed) crystal input pin.
BPWM1_CH0
I/O
MFP11
BPWM1 channel 0 output/capture input.
PF.2
I/O
MFP0
General purpose digital I/O pin.
EBI_nCS1
O
MFP2
EBI chip select 1 output pin.
UART0_RXD
I
MFP3
UART0 data receiver input pin.
I2C0_SDA
I/O
MFP4
I2C0 data input/output pin.
QSPI0_CLK
I/O
MFP5
Quad SPI0 serial clock pin.
XT1_OUT
O
MFP10
External 4~24 MHz (high speed) crystal output pin.
BPWM1_CH1
I/O
MFP11
BPWM1 channel 1 output/capture input.
XT1_IN
10
Type
M480 SERIES DATASHEET
39
VSS
P
MFP0
Ground pin for digital circuit.
40
VDD
P
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
41
PE.8
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR10
O
MFP2
EBI address bus bit 10.
I2S0_BCLK
O
MFP4
I2S0 bit clock output pin.
SPI2_CLK
I/O
MFP5
SPI2 serial clock pin.
USCI1_CTL1
I/O
MFP6
USCI1 control 1 pin.
UART2_TXD
O
MFP7
UART2 data transmitter output pin.
EPWM0_CH0
I/O
MFP10
EPWM0 channel 0 output/capture input.
I
MFP11
EPWM0 Brake 0 input pin.
EPWM0_BRAKE0
May 08, 2020
Page 78 of 523
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
42
43
45
May 08, 2020
MFP
Description
ECAP0_IC0
I
MFP12
Enhanced capture unit 0 input 0 pin.
TRACE_CLK
O
MFP14
ETM Trace Clock output pin
PE.9
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR11
O
MFP2
EBI address bus bit 11.
I2S0_MCLK
O
MFP4
I2S0 master clock output pin.
SPI2_MISO
I/O
MFP5
SPI2 MISO (Master In, Slave Out) pin.
USCI1_CTL0
I/O
MFP6
USCI1 control 0 pin.
UART2_RXD
I
MFP7
UART2 data receiver input pin.
EPWM0_CH1
I/O
MFP10
EPWM0 channel 1 output/capture input.
EPWM0_BRAKE1
I
MFP11
EPWM0 Brake 1 input pin.
ECAP0_IC1
I
MFP12
Enhanced capture unit 0 input 1 pin.
TRACE_DATA0
O
MFP14
ETM Trace Data 0 output pin
PE.10
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR12
O
MFP2
EBI address bus bit 12.
I2S0_DI
I
MFP4
I2S0 data input pin.
SPI2_MOSI
I/O
MFP5
SPI2 MOSI (Master Out, Slave In) pin.
USCI1_DAT0
I/O
MFP6
USCI1 data 0 pin.
UART3_TXD
O
MFP7
UART3 data transmitter output pin.
EPWM0_CH2
I/O
MFP10
EPWM0 channel 2 output/capture input.
EPWM1_BRAKE0
I
MFP11
EPWM1 Brake 0 input pin.
ECAP0_IC2
I
MFP12
Enhanced capture unit 0 input 2 pin.
TRACE_DATA1
O
MFP14
ETM Trace Data 1 output pin
PE.11
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR13
O
MFP2
EBI address bus bit 13.
I2S0_DO
O
MFP4
I2S0 data output pin.
SPI2_SS
I/O
MFP5
SPI2 slave select pin.
USCI1_DAT1
I/O
MFP6
USCI1 data 1 pin.
UART3_RXD
I
MFP7
UART3 data receiver input pin.
UART1_nCTS
I
MFP8
UART1 clear to Send input pin.
EPWM0_CH3
I/O
MFP10
EPWM0 channel 3 output/capture input.
EPWM1_BRAKE1
I
MFP11
EPWM1 Brake 1 input pin.
ECAP1_IC2
I
MFP13
Enhanced capture unit 1 input 2 pin.
TRACE_DATA2
O
MFP14
ETM Trace Data 2 output pin
PE.12
I/O
MFP0
General purpose digital I/O pin.
Page 79 of 523
M480 SERIES DATASHEET
44
Type
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
46
M480 SERIES DATASHEET
18
48
May 08, 2020
MFP
Description
EBI_ADR14
O
MFP2
EBI address bus bit 14.
I2S0_LRCK
O
MFP4
I2S0 left right channel clock output pin.
SPI2_I2SMCLK
I/O
MFP5
SPI2 I2S master clock output pin
USCI1_CLK
I/O
MFP6
USCI1 clock pin.
UART1_nRTS
O
MFP8
UART1 request to Send output pin.
EPWM0_CH4
I/O
MFP10
EPWM0 channel 4 output/capture input.
ECAP1_IC1
I
MFP13
Enhanced capture unit 1 input 1 pin.
TRACE_DATA3
O
MFP14
ETM Trace Data 3 output pin
PE.13
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR15
O
MFP2
EBI address bus bit 15.
I2C0_SCL
I/O
MFP4
I2C0 clock pin.
UART4_nRTS
O
MFP5
UART4 request to Send output pin.
UART1_TXD
O
MFP8
UART1 data transmitter output pin.
EPWM0_CH5
I/O
MFP10
EPWM0 channel 5 output/capture input.
EPWM1_CH0
I/O
MFP11
EPWM1 channel 0 output/capture input.
BPWM1_CH5
I/O
MFP12
BPWM1 channel 5 output/capture input.
I
MFP13
Enhanced capture unit 1 input 0 pin.
PC.8
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR16
O
MFP2
EBI address bus bit 16.
I2C0_SDA
I/O
MFP4
I2C0 data input/output pin.
UART4_nCTS
I
MFP5
UART4 clear to Send input pin.
UART1_RXD
I
MFP8
UART1 data receiver input pin.
EPWM1_CH1
I/O
MFP11
EPWM1 channel 1 output/capture input.
BPWM1_CH4
I/O
MFP12
BPWM1 channel 4 output/capture input.
PC.7
I/O
MFP0
General purpose digital I/O pin.
EBI_AD9
I/O
MFP2
EBI address/data bus bit 9.
SPI1_MISO
I/O
MFP4
SPI1 MISO (Master In, Slave Out) pin.
UART4_TXD
O
MFP5
UART4 data transmitter output pin.
SC2_PWR
O
MFP6
Smart Card 2 power pin.
UART0_nCTS
I
MFP7
UART0 clear to Send input pin.
I2C1_SMBAL
O
MFP8
I2C1 SMBus SMBALTER pin
EPWM1_CH2
I/O
MFP11
EPWM1 channel 2 output/capture input.
BPWM1_CH0
I/O
MFP12
BPWM1 channel 0 output/capture input.
TM0
I/O
MFP14
Timer0 event counter input/toggle output pin.
ECAP1_IC0
47
Type
Page 80 of 523
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
19
15
21
50
51
Description
INT3
I
MFP15
External interrupt 3 input pin.
PC.6
I/O
MFP0
General purpose digital I/O pin.
EBI_AD8
I/O
MFP2
EBI address/data bus bit 8.
SPI1_MOSI
I/O
MFP4
SPI1 MOSI (Master Out, Slave In) pin.
UART4_RXD
I
MFP5
UART4 data receiver input pin.
SC2_RST
O
MFP6
Smart Card 2 reset pin.
UART0_nRTS
O
MFP7
UART0 request to Send output pin.
I2C1_SMBSUS
O
MFP8
I2C1 SMBus SMBSUS pin (PMBus CONTROL pin)
EPWM1_CH3
I/O
MFP11
EPWM1 channel 3 output/capture input.
BPWM1_CH1
I/O
MFP12
BPWM1 channel 1 output/capture input.
TM1
I/O
MFP14
Timer1 event counter input/toggle output pin.
INT2
I
MFP15
External interrupt 2 input pin.
PA.7
I/O
MFP0
General purpose digital I/O pin.
EBI_AD7
I/O
MFP2
EBI address/data bus bit 7.
SPI1_CLK
I/O
MFP4
SPI1 serial clock pin.
SC2_DAT
I/O
MFP6
Smart Card 2 data pin.
UART0_TXD
O
MFP7
UART0 data transmitter output pin.
I2C1_SCL
I/O
MFP8
I2C1 clock pin.
EPWM1_CH4
I/O
MFP11
EPWM1 channel 4 output/capture input.
BPWM1_CH2
I/O
MFP12
BPWM1 channel 2 output/capture input.
ACMP0_WLAT
I
MFP13
Analog comparator 0 window latch input pin
TM2
I/O
MFP14
Timer2 event counter input/toggle output pin.
INT1
I
MFP15
External interrupt 1 input pin.
PA.6
I/O
MFP0
General purpose digital I/O pin.
EBI_AD6
I/O
MFP2
EBI address/data bus bit 6.
SPI1_SS
I/O
MFP4
SPI1 slave select pin.
SD1_nCD
I
MFP5
SD/SDIO1 card detect input pin
SC2_CLK
O
MFP6
Smart Card 2 clock pin.
UART0_RXD
I
MFP7
UART0 data receiver input pin.
I2C1_SDA
I/O
MFP8
I2C1 data input/output pin.
EPWM1_CH5
I/O
MFP11
EPWM1 channel 5 output/capture input.
BPWM1_CH3
I/O
MFP12
BPWM1 channel 3 output/capture input.
ACMP1_WLAT
I
MFP13
Analog comparator 1 window latch input pin
I/O
MFP14
Timer3 event counter input/toggle output pin.
TM3
May 08, 2020
MFP
Page 81 of 523
M480 SERIES DATASHEET
16
20
49
Type
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
Type
MFP
Description
INT0
I
MFP15
External interrupt 0 input pin.
22
52
VSS
P
MFP0
Ground pin for digital circuit.
23
53
VDD
P
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
24
54
LDO_CAP
A
MFP0
LDO output pin.
Note: This pin needs to be connected with an external
capacitor.
17
M480 SERIES DATASHEET
18
25
26
55
56
PA.5
I/O
MFP0
General purpose digital I/O pin.
SPIM_D2
I/O
MFP2
SPIM data 2 pin for Quad Mode I/O.
QSPI0_MISO1
I/O
MFP3
Quad SPI0 MISO1 (Master In, Slave Out) pin.
SPI1_I2SMCLK
I/O
MFP4
SPI1 I2S master clock output pin
SD1_CMD
I/O
MFP5
SD/SDIO1 command/response pin
SC2_nCD
I
MFP6
Smart Card 2 card detect pin.
UART0_nCTS
I
MFP7
UART0 clear to Send input pin.
UART5_TXD
O
MFP8
UART5 data transmitter output pin.
I2C0_SCL
I/O
MFP9
I2C0 clock pin.
CAN0_TXD
O
MFP10
CAN0 bus transmitter output.
BPWM0_CH5
I/O
MFP12
BPWM0 channel 5 output/capture input.
EPWM0_CH0
I/O
MFP13
EPWM0 channel 0 output/capture input.
QEI0_INDEX
I
MFP14
Quadrature encoder 0 index input
PA.4
I/O
MFP0
General purpose digital I/O pin.
SPIM_D3
I/O
MFP2
SPIM data 3 pin for Quad Mode I/O.
QSPI0_MOSI1
I/O
MFP3
Quad SPI0 MOSI1 (Master Out, Slave In) pin.
SPI0_I2SMCLK
I/O
MFP4
SPI0 I2S master clock output pin
SD1_CLK
O
MFP5
SD/SDIO1 clock output pin
SC0_nCD
I
MFP6
Smart Card 0 card detect pin.
UART0_nRTS
O
MFP7
UART0 request to Send output pin.
UART5_RXD
I
MFP8
UART5 data receiver input pin.
I2C0_SDA
I/O
MFP9
I2C0 data input/output pin.
CAN0_RXD
I
MFP10
CAN0 bus receiver input.
BPWM0_CH4
I/O
MFP12
BPWM0 channel 4 output/capture input.
EPWM0_CH1
I/O
MFP13
EPWM0 channel 1 output/capture input.
I
MFP14
Quadrature encoder 0 phase A input
PA.3
I/O
MFP0
General purpose digital I/O pin.
SPIM_SS
I/O
MFP2
SPIM slave select pin.
QEI0_A
11
19
27
57
May 08, 2020
Page 82 of 523
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
Type
QSPI0_SS
I/O
MFP3
Quad SPI0 slave select pin.
SPI0_SS
I/O
MFP4
SPI0 slave select pin.
SD1_DAT3
I/O
MFP5
SD/SDIO1 data line bit 3.
SC0_PWR
O
MFP6
Smart Card 0 power pin.
UART4_TXD
O
MFP7
UART4 data transmitter output pin.
UART1_TXD
O
MFP8
UART1 data transmitter output pin.
I2C1_SCL
I/O
MFP9
I2C1 clock pin.
BPWM0_CH3
I/O
MFP12
BPWM0 channel 3 output/capture input.
EPWM0_CH2
I/O
MFP13
EPWM0 channel 2 output/capture input.
I
MFP14
Quadrature encoder 0 phase B input
PA.2
I/O
MFP0
General purpose digital I/O pin.
SPIM_CLK
I/O
MFP2
SPIM serial clock pin.
QSPI0_CLK
I/O
MFP3
Quad SPI0 serial clock pin.
SPI0_CLK
I/O
MFP4
SPI0 serial clock pin.
SD1_DAT2
I/O
MFP5
SD/SDIO1 data line bit 2.
SC0_RST
O
MFP6
Smart Card 0 reset pin.
UART4_RXD
I
MFP7
UART4 data receiver input pin.
UART1_RXD
I
MFP8
UART1 data receiver input pin.
I2C1_SDA
I/O
MFP9
I2C1 data input/output pin.
BPWM0_CH2
I/O
MFP12
BPWM0 channel 2 output/capture input.
EPWM0_CH3
I/O
MFP13
EPWM0 channel 3 output/capture input.
PA.1
I/O
MFP0
General purpose digital I/O pin.
SPIM_MISO
I/O
MFP2
SPIM MISO (Master In, Slave Out) pin.
QSPI0_MISO0
I/O
MFP3
Quad SPI0 MISO0 (Master In, Slave Out) pin.
SPI0_MISO
I/O
MFP4
SPI0 MISO (Master In, Slave Out) pin.
SD1_DAT1
I/O
MFP5
SD/SDIO1 data line bit 1.
SC0_DAT
I/O
MFP6
Smart Card 0 data pin.
UART0_TXD
O
MFP7
UART0 data transmitter output pin.
UART1_nCTS
I
MFP8
UART1 clear to Send input pin.
I2C2_SCL
I/O
MFP9
I2C2 clock pin.
BPWM0_CH1
I/O
MFP12
BPWM0 channel 1 output/capture input.
EPWM0_CH4
I/O
MFP13
EPWM0 channel 4 output/capture input.
I
MFP15
DAC1 external trigger input.
I/O
MFP0
General purpose digital I/O pin.
QEI0_B
12
21
28
29
58
59
DAC1_ST
14
22
30
60
May 08, 2020
PA.0
Description
Page 83 of 523
M480 SERIES DATASHEET
13
20
MFP
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
15
23
31
M480 SERIES DATASHEET
24
32
MFP
Description
SPIM_MOSI
I/O
MFP2
SPIM MOSI (Master Out, Slave In) pin.
QSPI0_MOSI0
I/O
MFP3
Quad SPI0 MOSI0 (Master Out, Slave In) pin.
SPI0_MOSI
I/O
MFP4
SPI0 MOSI (Master Out, Slave In) pin.
SD1_DAT0
I/O
MFP5
SD/SDIO1 data line bit 0.
SC0_CLK
O
MFP6
Smart Card 0 clock pin.
UART0_RXD
I
MFP7
UART0 data receiver input pin.
UART1_nRTS
O
MFP8
UART1 request to Send output pin.
I2C2_SDA
I/O
MFP9
I2C2 data input/output pin.
BPWM0_CH0
I/O
MFP12
BPWM0 channel 0 output/capture input.
EPWM0_CH5
I/O
MFP13
EPWM0 channel 5 output/capture input.
DAC0_ST
I
MFP15
DAC0 external trigger input.
61
VDDIO
P
MFP0
Power supply for PA.0~PA.5.
62
PE.14
I/O
MFP0
General purpose digital I/O pin.
EBI_AD8
I/O
MFP2
EBI address/data bus bit 8.
UART2_TXD
O
MFP3
UART2 data transmitter output pin.
CAN0_TXD
O
MFP4
CAN0 bus transmitter output.
SD1_nCD
I
MFP5
SD/SDIO1 card detect input pin
PE.15
I/O
MFP0
General purpose digital I/O pin.
EBI_AD9
I/O
MFP2
EBI address/data bus bit 9.
UART2_RXD
I
MFP3
UART2 data receiver input pin.
CAN0_RXD
I
MFP4
CAN0 bus receiver input.
nRESET
I
MFP0
External reset input: active LOW, with an internal pull-up.
Set this pin low reset to initial state.
63
16
Type
64
Note: It is recommended to use 10 kΩ pull-up resistor
and 10 uF capacitor on nRESET pin.
17
25
33
65
PF.0
I/O
MFP0
General purpose digital I/O pin.
UART1_TXD
O
MFP2
UART1 data transmitter output pin.
I2C1_SCL
I/O
MFP3
I2C1 clock pin.
BPWM1_CH0
I/O
MFP12
BPWM1 channel 0 output/capture input.
ICE_DAT
O
MFP14
Serial wired debugger data pin.
Note: It is recommended to use 100 kΩ pull-up resistor
on ICE_DAT pin.
18
26
34
66
PF.1
I/O
MFP0
General purpose digital I/O pin.
I
MFP2
UART1 data receiver input pin.
I2C1_SDA
I/O
MFP3
I2C1 data input/output pin.
BPWM1_CH1
I/O
MFP12
BPWM1 channel 1 output/capture input.
UART1_RXD
May 08, 2020
Page 84 of 523
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
ICE_CLK
Type
I
MFP
MFP14
Description
Serial wired debugger clock pin.
Note: It is recommended to use 100 kΩ pull-up resistor
on ICE_CLK pin.
67
I/O
MFP0
General purpose digital I/O pin.
EBI_AD7
I/O
MFP2
EBI address/data bus bit 7.
I2C2_SCL
I/O
MFP3
I2C2 clock pin.
I
MFP4
UART2 clear to Send input pin.
PD.8
I/O
MFP0
General purpose digital I/O pin.
EBI_AD6
I/O
MFP2
EBI address/data bus bit 6.
I2C2_SDA
I/O
MFP3
I2C2 data input/output pin.
UART2_nRTS
O
MFP4
UART2 request to Send output pin.
PC.5
I/O
MFP0
General purpose digital I/O pin.
EBI_AD5
I/O
MFP2
EBI address/data bus bit 5.
SPIM_D2
I/O
MFP3
SPIM data 2 pin for Quad Mode I/O.
QSPI0_MISO1
I/O
MFP4
Quad SPI0 MISO1 (Master In, Slave Out) pin.
UART2_TXD
O
MFP8
UART2 data transmitter output pin.
I2C1_SCL
I/O
MFP9
I2C1 clock pin.
CAN0_TXD
O
MFP10
CAN0 bus transmitter output.
UART4_TXD
O
MFP11
UART4 data transmitter output pin.
EPWM1_CH0
I/O
MFP12
EPWM1 channel 0 output/capture input.
PC.4
I/O
MFP0
General purpose digital I/O pin.
EBI_AD4
I/O
MFP2
EBI address/data bus bit 4.
SPIM_D3
I/O
MFP3
SPIM data 3 pin for Quad Mode I/O.
QSPI0_MOSI1
I/O
MFP4
Quad SPI0 MOSI1 (Master Out, Slave In) pin.
SC1_nCD
I
MFP5
Smart Card 1 card detect pin.
I2S0_BCLK
O
MFP6
I2S0 bit clock output pin.
SPI1_I2SMCLK
I/O
MFP7
SPI1 I2S master clock output pin
I
MFP8
UART2 data receiver input pin.
I2C1_SDA
I/O
MFP9
I2C1 data input/output pin.
CAN0_RXD
I
MFP10
CAN0 bus receiver input.
UART4_RXD
I
MFP11
UART4 data receiver input pin.
EPWM1_CH1
I/O
MFP12
EPWM1 channel 1 output/capture input.
PC.3
I/O
MFP0
General purpose digital I/O pin.
EBI_AD3
I/O
MFP2
EBI address/data bus bit 3.
SPIM_SS
I/O
MFP3
SPIM slave select pin.
UART2_nCTS
68
27
28
35
36
69
70
UART2_RXD
29
37
71
May 08, 2020
Page 85 of 523
M480 SERIES DATASHEET
PD.9
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
Type
QSPI0_SS
I/O
MFP4
Quad SPI0 slave select pin.
SC1_PWR
O
MFP5
Smart Card 1 power pin.
I2S0_MCLK
O
MFP6
I2S0 master clock output pin.
SPI1_MISO
I/O
MFP7
SPI1 MISO (Master In, Slave Out) pin.
UART2_nRTS
O
MFP8
UART2 request to Send output pin.
I2C0_SMBAL
O
MFP9
I2C0 SMBus SMBALTER pin
CAN1_TXD
O
MFP10
CAN1 bus transmitter output.
UART3_TXD
O
MFP11
UART3 data transmitter output pin.
EPWM1_CH2
I/O
MFP12
EPWM1 channel 2 output/capture input.
PC.2
I/O
MFP0
General purpose digital I/O pin.
EBI_AD2
I/O
MFP2
EBI address/data bus bit 2.
SPIM_CLK
I/O
MFP3
SPIM serial clock pin.
QSPI0_CLK
I/O
MFP4
Quad SPI0 serial clock pin.
SC1_RST
O
MFP5
Smart Card 1 reset pin.
I2S0_DI
I
MFP6
I2S0 data input pin.
I/O
MFP7
SPI1 MOSI (Master Out, Slave In) pin.
UART2_nCTS
I
MFP8
UART2 clear to Send input pin.
I2C0_SMBSUS
O
MFP9
I2C0 SMBus SMBSUS pin (PMBus CONTROL pin)
CAN1_RXD
I
MFP10
CAN1 bus receiver input.
UART3_RXD
I
MFP11
UART3 data receiver input pin.
EPWM1_CH3
I/O
MFP12
EPWM1 channel 3 output/capture input.
PC.1
I/O
MFP0
General purpose digital I/O pin.
EBI_AD1
I/O
MFP2
EBI address/data bus bit 1.
SPIM_MISO
I/O
MFP3
SPIM MISO (Master In, Slave Out) pin.
QSPI0_MISO0
I/O
MFP4
Quad SPI0 MISO0 (Master In, Slave Out) pin.
SC1_DAT
I/O
MFP5
Smart Card 1 data pin.
I2S0_DO
O
MFP6
I2S0 data output pin.
SPI1_CLK
I/O
MFP7
SPI1 serial clock pin.
UART2_TXD
O
MFP8
UART2 data transmitter output pin.
I2C0_SCL
I/O
MFP9
I2C0 clock pin.
EPWM1_CH4
I/O
MFP12
EPWM1 channel 4 output/capture input.
ACMP0_O
O
MFP14
Analog comparator 0 output pin.
PC.0
I/O
MFP0
General purpose digital I/O pin.
EBI_AD0
I/O
MFP2
EBI address/data bus bit 0.
30
38
72
SPI1_MOSI
M480 SERIES DATASHEET
19
20
31
32
39
40
73
74
May 08, 2020
MFP
Description
Page 86 of 523
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
Type
MFP
Description
I/O
MFP3
SPIM MOSI (Master Out, Slave In) pin.
QSPI0_MOSI0
I/O
MFP4
Quad SPI0 MOSI0 (Master Out, Slave In) pin.
SC1_CLK
O
MFP5
Smart Card 1 clock pin.
I2S0_LRCK
O
MFP6
I2S0 left right channel clock output pin.
SPI1_SS
I/O
MFP7
SPI1 slave select pin.
I
MFP8
UART2 data receiver input pin.
I2C0_SDA
I/O
MFP9
I2C0 data input/output pin.
EPWM1_CH5
I/O
MFP12
EPWM1 channel 5 output/capture input.
ACMP1_O
O
MFP14
Analog comparator 1 output pin.
75
VSS
P
MFP0
Ground pin for digital circuit.
76
VDD
P
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
77
PG.9
I/O
MFP0
General purpose digital I/O pin.
EBI_AD0
I/O
MFP2
EBI address/data bus bit 0.
SD1_DAT3
I/O
MFP3
SD/SDIO1 data line bit 3.
SPIM_D2
I/O
MFP4
SPIM data 2 pin for Quad Mode I/O.
BPWM0_CH5
I/O
MFP12
BPWM0 channel 5 output/capture input.
PG.10
I/O
MFP0
General purpose digital I/O pin.
EBI_AD1
I/O
MFP2
EBI address/data bus bit 1.
SD1_DAT2
I/O
MFP3
SD/SDIO1 data line bit 2.
SPIM_D3
I/O
MFP4
SPIM data 3 pin for Quad Mode I/O.
BPWM0_CH4
I/O
MFP12
BPWM0 channel 4 output/capture input.
PG.11
I/O
MFP0
General purpose digital I/O pin.
EBI_AD2
I/O
MFP2
EBI address/data bus bit 2.
SD1_DAT1
I/O
MFP3
SD/SDIO1 data line bit 1.
SPIM_SS
I/O
MFP4
SPIM slave select pin.
BPWM0_CH3
I/O
MFP12
BPWM0 channel 3 output/capture input.
PG.12
I/O
MFP0
General purpose digital I/O pin.
EBI_AD3
I/O
MFP2
EBI address/data bus bit 3.
SD1_DAT0
I/O
MFP3
SD/SDIO1 data line bit 0.
SPIM_CLK
I/O
MFP4
SPIM serial clock pin.
BPWM0_CH2
I/O
MFP12
BPWM0 channel 2 output/capture input.
PG.13
I/O
MFP0
General purpose digital I/O pin.
EBI_AD4
I/O
MFP2
EBI address/data bus bit 4.
UART2_RXD
78
79
80
81
May 08, 2020
Page 87 of 523
M480 SERIES DATASHEET
SPIM_MOSI
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
Type
SD1_CMD
I/O
MFP3
SD/SDIO1 command/response pin
SPIM_MISO
I/O
MFP4
SPIM MISO (Master In, Slave Out) pin.
BPWM0_CH1
I/O
MFP12
BPWM0 channel 1 output/capture input.
PG.14
I/O
MFP0
General purpose digital I/O pin.
EBI_AD5
I/O
MFP2
EBI address/data bus bit 5.
SD1_CLK
O
MFP3
SD/SDIO1 clock output pin
SPIM_MOSI
I/O
MFP4
SPIM MOSI (Master Out, Slave In) pin.
BPWM0_CH0
I/O
MFP12
BPWM0 channel 0 output/capture input.
PG.15
I/O
MFP0
General purpose digital I/O pin.
SD1_nCD
I
MFP3
SD/SDIO1 card detect input pin
CLKO
O
MFP14
Clock Out
EADC0_ST
I
MFP15
EADC0 external trigger input.
PD.3
I/O
MFP0
General purpose digital I/O pin.
EBI_AD10
I/O
MFP2
EBI address/data bus bit 10.
USCI0_CTL1
I/O
MFP3
USCI0 control 1 pin.
SPI0_SS
I/O
MFP4
SPI0 slave select pin.
UART3_nRTS
O
MFP5
UART3 request to Send output pin.
USCI1_CTL0
I/O
MFP6
USCI1 control 0 pin.
SC2_PWR
O
MFP7
Smart Card 2 power pin.
SC1_nCD
I
MFP8
Smart Card 1 card detect pin.
UART0_TXD
O
MFP9
UART0 data transmitter output pin.
PD.2
I/O
MFP0
General purpose digital I/O pin.
EBI_AD11
I/O
MFP2
EBI address/data bus bit 11.
USCI0_DAT1
I/O
MFP3
USCI0 data 1 pin.
SPI0_CLK
I/O
MFP4
SPI0 serial clock pin.
UART3_nCTS
I
MFP5
UART3 clear to Send input pin.
SC2_RST
O
MFP7
Smart Card 2 reset pin.
UART0_RXD
I
MFP9
UART0 data receiver input pin.
PD.1
I/O
MFP0
General purpose digital I/O pin.
EBI_AD12
I/O
MFP2
EBI address/data bus bit 12.
USCI0_DAT0
I/O
MFP3
USCI0 data 0 pin.
SPI0_MISO
I/O
MFP4
SPI0 MISO (Master In, Slave Out) pin.
UART3_TXD
O
MFP5
UART3 data transmitter output pin.
I2C2_SCL
I/O
MFP6
I2C2 clock pin.
82
83
41
M480 SERIES DATASHEET
42
43
May 08, 2020
MFP
Description
Page 88 of 523
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
Type
SC2_DAT
I/O
MFP7
Smart Card 2 data pin.
PD.0
I/O
MFP0
General purpose digital I/O pin.
EBI_AD13
I/O
MFP2
EBI address/data bus bit 13.
USCI0_CLK
I/O
MFP3
USCI0 clock pin.
SPI0_MOSI
I/O
MFP4
SPI0 MOSI (Master Out, Slave In) pin.
I
MFP5
UART3 data receiver input pin.
I2C2_SDA
I/O
MFP6
I2C2 data input/output pin.
SC2_CLK
O
MFP7
Smart Card 2 clock pin.
TM2
I/O
MFP14
Timer2 event counter input/toggle output pin.
PD.13
I/O
MFP0
General purpose digital I/O pin.
EBI_AD10
I/O
MFP2
EBI address/data bus bit 10.
SD0_nCD
I
MFP3
SD/SDIO0 card detect input pin
SPI0_I2SMCLK
I/O
MFP4
SPI0 I2S master clock output pin
SPI1_I2SMCLK
I/O
MFP5
SPI1 I2S master clock output pin
I
MFP7
Smart Card 2 card detect pin.
PA.12
I/O
MFP0
General purpose digital I/O pin.
I2S0_BCLK
O
MFP2
I2S0 bit clock output pin.
UART4_TXD
O
MFP3
UART4 data transmitter output pin.
I2C1_SCL
I/O
MFP4
I2C1 clock pin.
SPI2_SS
I/O
MFP5
SPI2 slave select pin.
CAN0_TXD
O
MFP6
CAN0 bus transmitter output.
SC2_PWR
O
MFP7
Smart Card 2 power pin.
BPWM1_CH2
I/O
MFP11
BPWM1 channel 2 output/capture input.
QEI1_INDEX
I
MFP12
Quadrature encoder 1 index input
USB_VBUS
P
MFP14
Power supply from USB host or HUB.
PA.13
I/O
MFP0
General purpose digital I/O pin.
I2S0_MCLK
O
MFP2
I2S0 master clock output pin.
UART4_RXD
I
MFP3
UART4 data receiver input pin.
I2C1_SDA
I/O
MFP4
I2C1 data input/output pin.
SPI2_CLK
I/O
MFP5
SPI2 serial clock pin.
CAN0_RXD
I
MFP6
CAN0 bus receiver input.
SC2_RST
O
MFP7
Smart Card 2 reset pin.
BPWM1_CH3
I/O
MFP11
BPWM1 channel 3 output/capture input.
I
MFP12
Quadrature encoder 1 phase A input
44
UART3_RXD
84
SC2_nCD
21
34
45
46
85
86
QEI1_A
May 08, 2020
Description
Page 89 of 523
M480 SERIES DATASHEET
22
33
MFP
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
USB_D23
24
35
36
47
48
87
88
Type
MFP
Description
M480 SERIES DATASHEET
A
MFP14
USB differential signal D-.
I/O
MFP0
General purpose digital I/O pin.
I2S0_DI
I
MFP2
I2S0 data input pin.
UART0_TXD
O
MFP3
UART0 data transmitter output pin.
SPI2_MISO
I/O
MFP5
SPI2 MISO (Master In, Slave Out) pin.
I2C2_SCL
I/O
MFP6
I2C2 clock pin.
SC2_DAT
I/O
MFP7
Smart Card 2 data pin.
BPWM1_CH4
I/O
MFP11
BPWM1 channel 4 output/capture input.
QEI1_B
I
MFP12
Quadrature encoder 1 phase B input
USB_D+
A
MFP14
USB differential signal D+.
PA.15
I/O
MFP0
General purpose digital I/O pin.
I2S0_DO
O
MFP2
I2S0 data output pin.
UART0_RXD
I
MFP3
UART0 data receiver input pin.
SPI2_MOSI
I/O
MFP5
SPI2 MOSI (Master Out, Slave In) pin.
I2C2_SDA
I/O
MFP6
I2C2 data input/output pin.
SC2_CLK
O
MFP7
Smart Card 2 clock pin.
BPWM1_CH5
I/O
MFP11
BPWM1 channel 5 output/capture input.
EPWM0_SYNC_IN
I
MFP12
EPWM0 counter synchronous trigger input pin.
USB_OTG_ID
I
MFP14
USB_ identification.
P
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
P
MFP0
Ground pin for digital circuit.
A
MFP0
LDO output pin.
PA.14
89
NC
90
VDD
91
NC
92
NC
93
VSS
94
NC
95
LDO_CAP
Note: This pin needs to be connected with an external
capacitor.
96
NC
97
PE.7
I/O
MFP0
General purpose digital I/O pin.
SD0_CMD
I/O
MFP3
SD/SDIO0 command/response pin
SPIM_D2
I/O
MFP4
SPIM data 2 pin for Quad Mode I/O.
UART5_TXD
O
MFP8
UART5 data transmitter output pin.
CAN1_TXD
O
MFP9
CAN1 bus transmitter output.
May 08, 2020
Page 90 of 523
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
98
Description
MFP11
Quadrature encoder 1 index input
EPWM0_CH0
I/O
MFP12
EPWM0 channel 0 output/capture input.
BPWM0_CH5
I/O
MFP13
BPWM0 channel 5 output/capture input.
PE.6
I/O
MFP0
General purpose digital I/O pin.
SD0_CLK
O
MFP3
SD/SDIO0 clock output pin
SPIM_D3
I/O
MFP4
SPIM data 3 pin for Quad Mode I/O.
SPI3_I2SMCLK
I/O
MFP5
SPI3 I2S master clock output pin
I
MFP6
Smart Card 0 card detect pin.
USCI0_CTL0
I/O
MFP7
USCI0 control 0 pin.
UART5_RXD
I
MFP8
UART5 data receiver input pin.
CAN1_RXD
I
MFP9
CAN1 bus receiver input.
QEI1_A
I
MFP11
Quadrature encoder 1 phase A input
EPWM0_CH1
I/O
MFP12
EPWM0 channel 1 output/capture input.
BPWM0_CH4
I/O
MFP13
BPWM0 channel 4 output/capture input.
PE.5
I/O
MFP0
General purpose digital I/O pin.
EBI_nRD
O
MFP2
EBI read enable output pin.
SD0_DAT3
I/O
MFP3
SD/SDIO0 data line bit 3.
SPIM_SS
I/O
MFP4
SPIM slave select pin.
SPI3_SS
I/O
MFP5
SPI3 slave select pin.
SC0_PWR
O
MFP6
Smart Card 0 power pin.
USCI0_CTL1
I/O
MFP7
USCI0 control 1 pin.
I
MFP11
Quadrature encoder 1 phase B input
EPWM0_CH2
I/O
MFP12
EPWM0 channel 2 output/capture input.
BPWM0_CH3
I/O
MFP13
BPWM0 channel 3 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_nWR
O
MFP2
EBI write enable output pin.
SD0_DAT2
I/O
MFP3
SD/SDIO0 data line bit 2.
SPIM_CLK
I/O
MFP4
SPIM serial clock pin.
SPI3_CLK
I/O
MFP5
SPI3 serial clock pin.
SC0_RST
O
MFP6
Smart Card 0 reset pin.
USCI0_DAT1
I/O
MFP7
USCI0 data 1 pin.
QEI0_INDEX
I
MFP11
Quadrature encoder 0 index input
EPWM0_CH3
I/O
MFP12
EPWM0 channel 3 output/capture input.
BPWM0_CH2
I/O
MFP13
BPWM0 channel 2 output/capture input.
100 PE.4
Page 91 of 523
M480 SERIES DATASHEET
I
QEI1_B
May 08, 2020
MFP
QEI1_INDEX
SC0_nCD
99
Type
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
101 PE.3
Type
MFP
Description
I/O
MFP0
General purpose digital I/O pin.
EBI_MCLK
O
MFP2
EBI external clock output pin.
SD0_DAT1
I/O
MFP3
SD/SDIO0 data line bit 1.
SPIM_MISO
I/O
MFP4
SPIM MISO (Master In, Slave Out) pin.
SPI3_MISO
I/O
MFP5
SPI3 MISO (Master In, Slave Out) pin.
SC0_DAT
I/O
MFP6
Smart Card 0 data pin.
USCI0_DAT0
I/O
MFP7
USCI0 data 0 pin.
I
MFP11
Quadrature encoder 0 phase A input
EPWM0_CH4
I/O
MFP12
EPWM0 channel 4 output/capture input.
BPWM0_CH1
I/O
MFP13
BPWM0 channel 1 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_ALE
O
MFP2
EBI address latch enable output pin.
SD0_DAT0
I/O
MFP3
SD/SDIO0 data line bit 0.
SPIM_MOSI
I/O
MFP4
SPIM MOSI (Master Out, Slave In) pin.
SPI3_MOSI
I/O
MFP5
SPI3 MOSI (Master Out, Slave In) pin.
SC0_CLK
O
MFP6
Smart Card 0 clock pin.
USCI0_CLK
I/O
MFP7
USCI0 clock pin.
I
MFP11
Quadrature encoder 0 phase B input
EPWM0_CH5
I/O
MFP12
EPWM0 channel 5 output/capture input.
BPWM0_CH0
I/O
MFP13
BPWM0 channel 0 output/capture input.
103 VSS
P
MFP0
Ground pin for digital circuit.
104 VDD
P
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
105 PE.1
I/O
MFP0
General purpose digital I/O pin.
EBI_AD10
I/O
MFP2
EBI address/data bus bit 10.
QSPI0_MISO0
I/O
MFP3
Quad SPI0 MISO0 (Master In, Slave Out) pin.
SC2_DAT
I/O
MFP4
Smart Card 2 data pin.
I2S0_BCLK
O
MFP5
I2S0 bit clock output pin.
SPI1_MISO
I/O
MFP6
SPI1 MISO (Master In, Slave Out) pin.
UART3_TXD
O
MFP7
UART3 data transmitter output pin.
I2C1_SCL
I/O
MFP8
I2C1 clock pin.
I
MFP9
UART4 clear to Send input pin.
I/O
MFP0
General purpose digital I/O pin.
I/O
MFP2
EBI address/data bus bit 11.
QEI0_A
102 PE.2
QEI0_B
M480 SERIES DATASHEET
UART4_nCTS
106 PE.0
EBI_AD11
May 08, 2020
Page 92 of 523
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
MFP
Description
I/O
MFP3
Quad SPI0 MOSI0 (Master Out, Slave In) pin.
SC2_CLK
O
MFP4
Smart Card 2 clock pin.
I2S0_MCLK
O
MFP5
I2S0 master clock output pin.
SPI1_MOSI
I/O
MFP6
SPI1 MOSI (Master Out, Slave In) pin.
I
MFP7
UART3 data receiver input pin.
I2C1_SDA
I/O
MFP8
I2C1 data input/output pin.
UART4_nRTS
O
MFP9
UART4 request to Send output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD12
I/O
MFP2
EBI address/data bus bit 12.
QSPI0_CLK
I/O
MFP3
Quad SPI0 serial clock pin.
SC2_PWR
O
MFP4
Smart Card 2 power pin.
I2S0_DI
I
MFP5
I2S0 data input pin.
SPI1_CLK
I/O
MFP6
SPI1 serial clock pin.
UART3_nRTS
O
MFP7
UART3 request to Send output pin.
I2C1_SMBAL
O
MFP8
I2C1 SMBus SMBALTER pin
I2C2_SCL
I/O
MFP9
I2C2 clock pin.
UART1_TXD
O
MFP10
UART1 data transmitter output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD13
I/O
MFP2
EBI address/data bus bit 13.
QSPI0_SS
I/O
MFP3
Quad SPI0 slave select pin.
SC2_RST
O
MFP4
Smart Card 2 reset pin.
I2S0_DO
O
MFP5
I2S0 data output pin.
SPI1_SS
I/O
MFP6
SPI1 slave select pin.
UART3_nCTS
I
MFP7
UART3 clear to Send input pin.
I2C1_SMBSUS
O
MFP8
I2C1 SMBus SMBSUS pin (PMBus CONTROL pin)
I2C2_SDA
I/O
MFP9
I2C2 data input/output pin.
I
MFP10
UART1 data receiver input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD14
I/O
MFP2
EBI address/data bus bit 14.
QSPI0_MISO1
I/O
MFP3
Quad SPI0 MISO1 (Master In, Slave Out) pin.
SC2_nCD
I
MFP4
Smart Card 2 card detect pin.
I2S0_LRCK
O
MFP5
I2S0 left right channel clock output pin.
SPI1_I2SMCLK
I/O
MFP6
SPI1 I2S master clock output pin
UART4_TXD
O
MFP7
UART4 data transmitter output pin.
107 PH.8
108 PH.9
UART1_RXD
109 PH.10
Page 93 of 523
Rev 3.00
M480 SERIES DATASHEET
QSPI0_MOSI0
UART3_RXD
May 08, 2020
Type
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
UART0_TXD
Type
MFP
Description
O
MFP8
UART0 data transmitter output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD15
I/O
MFP2
EBI address/data bus bit 15.
QSPI0_MOSI1
I/O
MFP3
Quad SPI0 MOSI1 (Master Out, Slave In) pin.
UART4_RXD
I
MFP7
UART4 data receiver input pin.
UART0_RXD
I
MFP8
UART0 data receiver input pin.
EPWM0_CH5
I/O
MFP11
EPWM0 channel 5 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_nCS0
O
MFP2
EBI chip select 0 output pin.
SPI3_I2SMCLK
I/O
MFP3
SPI3 I2S master clock output pin
I
MFP4
Smart Card 1 card detect pin.
I/O
MFP11
EPWM0 channel 4 output/capture input.
110 PH.11
111 PD.14
SC1_nCD
EPWM0_CH4
25
37
49
112 VSS
P
MFP0
Ground pin for digital circuit.
26
38
50
113 LDO_CAP
A
MFP0
LDO output pin.
Note: This pin needs to be connected with an external
capacitor.
27
M480 SERIES DATASHEET
P
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD11
I/O
MFP2
EBI address/data bus bit 11.
SC1_nCD
I
MFP3
Smart Card 1 card detect pin.
SPI0_I2SMCLK
I/O
MFP4
SPI0 I2S master clock output pin
USCI0_CTL0
I/O
MFP5
USCI0 control 0 pin.
QSPI0_CLK
I/O
MFP6
Quad SPI0 serial clock pin.
I
MFP11
EPWM0 counter synchronous trigger input pin.
I/O
MFP13
Timer1 event counter input/toggle output pin.
I
MFP14
USB external VBUS regulator status pin.
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC0 channel 15 analog input.
EBI_AD12
I/O
MFP2
EBI address/data bus bit 12.
SC1_PWR
O
MFP3
Smart Card 1 power pin.
SPI0_SS
I/O
MFP4
SPI0 slave select pin.
USCI0_CTL1
I/O
MFP5
USCI0 control 1 pin.
UART0_nCTS
I
MFP6
UART0 clear to Send input pin.
UART3_TXD
O
MFP7
UART3 data transmitter output pin.
39
51
114 VDD
40
52
115 PC.14
EPWM0_SYNC_IN
TM1
USB_VBUS_ST
28
41
53
116 PB.15
EADC0_CH15
May 08, 2020
Page 94 of 523
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
29
42
54
44
55
56
Description
O
MFP8
I2C2 SMBus SMBALTER pin
EPWM1_CH0
I/O
MFP11
EPWM1 channel 0 output/capture input.
TM0_EXT
I/O
MFP13
Timer0 external capture input/toggle output pin.
USB_VBUS_EN
O
MFP14
USB external VBUS regulator enable pin.
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC0 channel 14 analog input.
EBI_AD13
I/O
MFP2
EBI address/data bus bit 13.
SC1_RST
O
MFP3
Smart Card 1 reset pin.
SPI0_CLK
I/O
MFP4
SPI0 serial clock pin.
USCI0_DAT1
I/O
MFP5
USCI0 data 1 pin.
UART0_nRTS
O
MFP6
UART0 request to Send output pin.
UART3_RXD
I
MFP7
UART3 data receiver input pin.
I2C2_SMBSUS
O
MFP8
I2C2 SMBus SMBSUS pin (PMBus CONTROL pin)
EPWM1_CH1
I/O
MFP11
EPWM1 channel 1 output/capture input.
TM1_EXT
I/O
MFP13
Timer1 external capture input/toggle output pin.
CLKO
O
MFP14
Clock Out
118 PB.13
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH13
A
MFP1
EADC0 channel 13 analog input.
DAC1_OUT
A
MFP1
DAC1 channel analog output.
ACMP0_P3
A
MFP1
Analog comparator 0 positive input 3 pin.
ACMP1_P3
A
MFP1
Analog comparator 1 positive input 3 pin.
EBI_AD14
I/O
MFP2
EBI address/data bus bit 14.
SC1_DAT
I/O
MFP3
Smart Card 1 data pin.
SPI0_MISO
I/O
MFP4
SPI0 MISO (Master In, Slave Out) pin.
USCI0_DAT0
I/O
MFP5
USCI0 data 0 pin.
UART0_TXD
O
MFP6
UART0 data transmitter output pin.
UART3_nRTS
O
MFP7
UART3 request to Send output pin.
I2C2_SCL
I/O
MFP8
I2C2 clock pin.
EPWM1_CH2
I/O
MFP11
EPWM1 channel 2 output/capture input.
TM2_EXT
I/O
MFP13
Timer2 external capture input/toggle output pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH12
A
MFP1
EADC0 channel 12 analog input.
DAC0_OUT
A
MFP1
DAC0 channel analog output.
ACMP0_P2
A
MFP1
Analog comparator 0 positive input 2 pin.
117 PB.14
119 PB.12
May 08, 2020
Page 95 of 523
M480 SERIES DATASHEET
31
43
MFP
I2C2_SMBAL
EADC0_CH14
30
Type
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
32
45
Type
MFP
Description
ACMP1_P2
A
MFP1
Analog comparator 1 positive input 2 pin.
EBI_AD15
I/O
MFP2
EBI address/data bus bit 15.
SC1_CLK
O
MFP3
Smart Card 1 clock pin.
SPI0_MOSI
I/O
MFP4
SPI0 MOSI (Master Out, Slave In) pin.
USCI0_CLK
I/O
MFP5
USCI0 clock pin.
UART0_RXD
I
MFP6
UART0 data receiver input pin.
UART3_nCTS
I
MFP7
UART3 clear to Send input pin.
I2C2_SDA
I/O
MFP8
I2C2 data input/output pin.
SD0_nCD
I
MFP9
SD/SDIO0 card detect input pin
EPWM1_CH3
I/O
MFP11
EPWM1 channel 3 output/capture input.
TM3_EXT
I/O
MFP13
Timer3 external capture input/toggle output pin.
57
120 AVDD
P
MFP0
Power supply for internal analog circuit.
58
121 VREF
A
MFP0
ADC reference voltage input.
Note: This pin needs to be connected with a 1uF
capacitor.
46
M480 SERIES DATASHEET
59
122 AVSS
P
MFP0
Ground pin for analog circuit.
60
123 PB.11
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH11
A
MFP1
EADC0 channel 11 analog input.
EBI_ADR16
O
MFP2
EBI address bus bit 16.
UART0_nCTS
I
MFP5
UART0 clear to Send input pin.
UART4_TXD
O
MFP6
UART4 data transmitter output pin.
I2C1_SCL
I/O
MFP7
I2C1 clock pin.
CAN0_TXD
O
MFP8
CAN0 bus transmitter output.
SPI0_I2SMCLK
I/O
MFP9
SPI0 I2S master clock output pin
BPWM1_CH0
I/O
MFP10
BPWM1 channel 0 output/capture input.
SPI3_CLK
I/O
MFP11
SPI3 serial clock pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH10
A
MFP1
EADC0 channel 10 analog input.
EBI_ADR17
O
MFP2
EBI address bus bit 17.
USCI1_CTL0
I/O
MFP4
USCI1 control 0 pin.
UART0_nRTS
O
MFP5
UART0 request to Send output pin.
UART4_RXD
I
MFP6
UART4 data receiver input pin.
I2C1_SDA
I/O
MFP7
I2C1 data input/output pin.
CAN0_RXD
I
MFP8
CAN0 bus receiver input.
I/O
MFP10
BPWM1 channel 1 output/capture input.
61
124 PB.10
BPWM1_CH1
May 08, 2020
Page 96 of 523
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
SPI3_SS
62
SPI3 slave select pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH9
A
MFP1
EADC0 channel 9 analog input.
EBI_ADR18
O
MFP2
EBI address bus bit 18.
USCI1_CTL1
I/O
MFP4
USCI1 control 1 pin.
UART0_TXD
O
MFP5
UART0 data transmitter output pin.
UART1_nCTS
I
MFP6
UART1 clear to Send input pin.
I2C1_SMBAL
O
MFP7
I2C1 SMBus SMBALTER pin
BPWM1_CH2
I/O
MFP10
BPWM1 channel 2 output/capture input.
SPI3_MISO
I/O
MFP11
SPI3 MISO (Master In, Slave Out) pin.
I
MFP13
External interrupt 7 input pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH8
A
MFP1
EADC0 channel 8 analog input.
EBI_ADR19
O
MFP2
EBI address bus bit 19.
USCI1_CLK
I/O
MFP4
USCI1 clock pin.
UART0_RXD
I
MFP5
UART0 data receiver input pin.
UART1_nRTS
O
MFP6
UART1 request to Send output pin.
I2C1_SMBSUS
O
MFP7
I2C1 SMBus SMBSUS pin (PMBus CONTROL pin)
BPWM1_CH3
I/O
MFP10
BPWM1 channel 3 output/capture input.
SPI3_MOSI
I/O
MFP11
SPI3 MOSI (Master Out, Slave In) pin.
I
MFP13
External interrupt 6 input pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH7
A
MFP1
EADC0 channel 7 analog input.
EBI_nWRL
O
MFP2
EBI low byte write enable output pin.
USCI1_DAT0
I/O
MFP4
USCI1 data 0 pin.
CAN1_TXD
O
MFP5
CAN1 bus transmitter output.
UART1_TXD
O
MFP6
UART1 data transmitter output pin.
SD1_CMD
I/O
MFP7
SD/SDIO1 command/response pin
EBI_nCS0
O
MFP8
EBI chip select 0 output pin.
BPWM1_CH4
I/O
MFP10
BPWM1 channel 4 output/capture input.
I
MFP11
EPWM1 Brake 0 input pin.
I/O
MFP12
EPWM1 channel 4 output/capture input.
INT5
I
MFP13
External interrupt 5 input pin.
USB_VBUS_ST
I
MFP14
USB external VBUS regulator status pin.
125 PB.9
126 PB.8
127 PB.7
EPWM1_BRAKE0
EPWM1_CH4
May 08, 2020
Page 97 of 523
M480 SERIES DATASHEET
64
Description
MFP11
INT6
47
MFP
I/O
INT7
63
Type
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
Type
ACMP0_O
O
MFP15
Analog comparator 0 output pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH6
A
MFP1
EADC0 channel 6 analog input.
EBI_nWRH
O
MFP2
EBI high byte write enable output pin
USCI1_DAT1
I/O
MFP4
USCI1 data 1 pin.
CAN1_RXD
I
MFP5
CAN1 bus receiver input.
UART1_RXD
I
MFP6
UART1 data receiver input pin.
SD1_CLK
O
MFP7
SD/SDIO1 clock output pin
EBI_nCS1
O
MFP8
EBI chip select 1 output pin.
BPWM1_CH5
I/O
MFP10
BPWM1 channel 5 output/capture input.
I
MFP11
EPWM1 Brake 1 input pin.
I/O
MFP12
EPWM1 channel 5 output/capture input.
INT4
I
MFP13
External interrupt 4 input pin.
USB_VBUS_EN
O
MFP14
USB external VBUS regulator enable pin.
ACMP1_O
O
MFP15
Analog comparator 1 output pin.
48
1
128 PB.6
EPWM1_BRAKE1
EPWM1_CH5
MFP
Description
M480 SERIES DATASHEET
May 08, 2020
Page 98 of 523
Rev 3.00
M480
4.2.3
M483 Series Pin Description
Note: PA.15 MFP can only be as USB_OTG_ID when enable full-Speed USB.
64 128 Pin Name
Pin Pin
2
1
MFP
Description
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH5
A
MFP1
EADC0 channel 5 analog input.
ACMP1_N
A
MFP1
Analog comparator 1 negative input pin.
EBI_ADR0
O
MFP2
EBI address bus bit 0.
SD0_DAT3
I/O
MFP3
SD/SDIO0 data line bit 3.
SPI1_MISO
I/O
MFP5
SPI1 MISO (Master In, Slave Out) pin.
I C0_SCL
I/O
MFP6
I2C0 clock pin.
UART5_TXD
O
MFP7
UART5 data transmitter output pin.
USCI1_CTL0
I/O
MFP8
USCI1 control 0 pin.
SC0_CLK
O
MFP9
Smart Card 0 clock pin.
I2S0_BCLK
O
MFP10
I2S0 bit clock output pin.
EPWM0_CH0
I/O
MFP11
EPWM0 channel 0 output/capture input.
TM0
I/O
MFP14
Timer0 event counter input/toggle output pin.
INT0
I
MFP15
External interrupt 0 input pin.
PB.4
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH4
A
MFP1
EADC0 channel 4 analog input.
ACMP1_P1
A
MFP1
Analog comparator 1 positive input 1 pin.
EBI_ADR1
O
MFP2
EBI address bus bit 1.
SD0_DAT2
I/O
MFP3
SD/SDIO0 data line bit 2.
SPI1_MOSI
I/O
MFP5
SPI1 MOSI (Master Out, Slave In) pin.
I/O
MFP6
I2C0 data input/output pin.
UART5_RXD
I
MFP7
UART5 data receiver input pin.
USCI1_CTL1
I/O
MFP8
USCI1 control 1 pin.
SC0_DAT
I/O
MFP9
Smart Card 0 data pin.
I S0_MCLK
O
MFP10
I2S0 master clock output pin.
EPWM0_CH1
I/O
MFP11
EPWM0 channel 1 output/capture input.
TM1
I/O
MFP14
Timer1 event counter input/toggle output pin.
INT1
I
MFP15
External interrupt 1 input pin.
PB.3
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH3
A
MFP1
EADC0 channel 3 analog input.
ACMP0_N
A
MFP1
Analog comparator 0 negative input pin.
EBI_ADR2
O
MFP2
EBI address bus bit 2.
PB.5
2
3
2
2
I C0_SDA
2
4
3
May 08, 2020
Page 99 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
64 128 Pin Name
Pin Pin
5
4
M480 SERIES DATASHEET
5
Type
MFP
Description
SD0_DAT1
I/O
MFP3
SD/SDIO0 data line bit 1.
SPI1_CLK
I/O
MFP5
SPI1 serial clock pin.
UART1_TXD
O
MFP6
UART1 data transmitter output pin.
UART5_nRTS
O
MFP7
UART5 request to Send output pin.
USCI1_DAT1
I/O
MFP8
USCI1 data 1 pin.
SC0_RST
O
MFP9
Smart Card 0 reset pin.
I2S0_DI
I
MFP10
I2S0 data input pin.
EPWM0_CH2
I/O
MFP11
EPWM0 channel 2 output/capture input.
TM2
I/O
MFP14
Timer2 event counter input/toggle output pin.
INT2
I
MFP15
External interrupt 2 input pin.
PB.2
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH2
A
MFP1
EADC0 channel 2 analog input.
ACMP0_P1
A
MFP1
Analog comparator 0 positive input 1 pin.
OPA0_O
A
MFP1
Operational amplifier 0 output pin.
EBI_ADR3
O
MFP2
EBI address bus bit 3.
SD0_DAT0
I/O
MFP3
SD/SDIO0 data line bit 0.
SPI1_SS
I/O
MFP5
SPI1 slave select pin.
UART1_RXD
I
MFP6
UART1 data receiver input pin.
UART5_nCTS
I
MFP7
UART5 clear to Send input pin.
USCI1_DAT0
I/O
MFP8
USCI1 data 0 pin.
SC0_PWR
O
MFP9
Smart Card 0 power pin.
I2S0_DO
O
MFP10
I2S0 data output pin.
EPWM0_CH3
I/O
MFP11
EPWM0 channel 3 output/capture input.
TM3
I/O
MFP14
Timer3 event counter input/toggle output pin.
INT3
I
MFP15
External interrupt 3 input pin.
PC.12
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR4
O
MFP2
EBI address bus bit 4.
UART0_TXD
O
MFP3
UART0 data transmitter output pin.
I2C0_SCL
I/O
MFP4
I2C0 clock pin.
SPI3_MISO
I/O
MFP6
SPI3 MISO (Master In, Slave Out) pin.
SC0_nCD
I
MFP9
Smart Card 0 card detect pin.
ECAP1_IC2
I
MFP11
Enhanced capture unit 1 input 2 pin.
EPWM1_CH0
I/O
MFP12
EPWM1 channel 0 output/capture input.
ACMP0_O
O
MFP14
Analog comparator 0 output pin.
May 08, 2020
Page 100 of 523
Rev 3.00
M480
64 128 Pin Name
Pin Pin
6
7
8
9
MFP
Description
PC.11
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR5
O
MFP2
EBI address bus bit 5.
UART0_RXD
I
MFP3
UART0 data receiver input pin.
I2C0_SDA
I/O
MFP4
I2C0 data input/output pin.
SPI3_MOSI
I/O
MFP6
SPI3 MOSI (Master Out, Slave In) pin.
ECAP1_IC1
I
MFP11
Enhanced capture unit 1 input 1 pin.
EPWM1_CH1
I/O
MFP12
EPWM1 channel 1 output/capture input.
ACMP1_O
O
MFP14
Analog comparator 1 output pin.
PC.10
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR6
O
MFP2
EBI address bus bit 6.
SPI3_CLK
I/O
MFP6
SPI3 serial clock pin.
UART3_TXD
O
MFP7
UART3 data transmitter output pin.
CAN1_TXD
O
MFP9
CAN1 bus transmitter output.
ECAP1_IC0
I
MFP11
Enhanced capture unit 1 input 0 pin.
EPWM1_CH2
I/O
MFP12
EPWM1 channel 2 output/capture input.
PC.9
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR7
O
MFP2
EBI address bus bit 7.
SPI3_SS
I/O
MFP6
SPI3 slave select pin.
UART3_RXD
I
MFP7
UART3 data receiver input pin.
CAN1_RXD
I
MFP9
CAN1 bus receiver input.
EPWM1_CH3
I/O
MFP12
EPWM1 channel 3 output/capture input.
PB.1
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH1
A
MFP1
EADC0 channel 1 analog input.
OPA0_N
A
MFP1
Operational amplifier 0 negative input pin.
EBI_ADR8
O
MFP2
EBI address bus bit 8.
SD0_CLK
O
MFP3
SD/SDIO0 clock output pin
SPI1_I2SMCLK
I/O
MFP5
SPI1 I2S master clock output pin
SPI3_I2SMCLK
I/O
MFP6
SPI3 I2S master clock output pin
UART2_TXD
O
MFP7
UART2 data transmitter output pin.
USCI1_CLK
I/O
MFP8
USCI1 clock pin.
I2C1_SCL
I/O
MFP9
I2C1 clock pin.
I2S0_LRCK
O
MFP10
I2S0 left right channel clock output pin.
EPWM0_CH4
I/O
MFP11
EPWM0 channel 4 output/capture input.
EPWM1_CH4
I/O
MFP12
EPWM1 channel 4 output/capture input.
May 08, 2020
Page 101 of 523
M480 SERIES DATASHEET
6
Type
Rev 3.00
M480
64 128 Pin Name
Pin Pin
Type
MFP
I
MFP13
EPWM0 Brake 0 input pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH0
A
MFP1
EADC0 channel 0 analog input.
OPA0_P
A
MFP1
Operational amplifier 0 positive input pin.
EBI_ADR9
O
MFP2
EBI address bus bit 9.
SD0_CMD
I/O
MFP3
SD/SDIO0 command/response pin
I
MFP7
UART2 data receiver input pin.
SPI0_I2SMCLK
I/O
MFP8
SPI0 I2S master clock output pin
I2C1_SDA
I/O
MFP9
I2C1 data input/output pin.
EPWM0_CH5
I/O
MFP11
EPWM0 channel 5 output/capture input.
EPWM1_CH5
I/O
MFP12
EPWM1 channel 5 output/capture input.
I
MFP13
EPWM0 Brake 1 input pin.
11 VSS
P
MFP0
Ground pin for digital circuit.
12 VDD
P
MFP0
Power supply for I/O ports and LDO source for internal PLL
and digital circuit.
I/O
MFP0
General purpose digital I/O pin.
ACMP0_P0
A
MFP1
Analog comparator 0 positive input 0 pin.
EBI_nRD
O
MFP2
EBI read enable output pin.
SC2_PWR
O
MFP3
Smart Card 2 power pin.
SPI2_SS
I/O
MFP4
SPI2 slave select pin.
SD1_DAT3
I/O
MFP5
SD/SDIO1 data line bit 3.
USCI0_CLK
I/O
MFP6
USCI0 clock pin.
I C2_SCL
I/O
MFP7
I2C2 clock pin.
BPWM0_CH0
I/O
MFP9
BPWM0 channel 0 output/capture input.
EPWM0_SYNC_OUT
O
MFP10
EPWM0 counter synchronous trigger output pin.
TM0_EXT
I/O
MFP13
Timer0 event counter input/toggle output pin.
DAC1_ST
I
MFP14
DAC1 external trigger input.
I/O
MFP0
General purpose digital I/O pin.
ACMP1_P0
A
MFP1
Analog comparator 1 positive input 0 pin.
OPA1_O
A
MFP1
Operational amplifier 1 output pin.
EBI_nWR
O
MFP2
EBI write enable output pin.
SC2_RST
O
MFP3
Smart Card 2 reset pin.
SPI2_CLK
I/O
MFP4
SPI2 serial clock pin.
SD1_DAT2
I/O
MFP5
SD/SDIO1 data line bit 2.
EPWM0_BRAKE0
7
10 PB.0
UART2_RXD
EPWM0_BRAKE1
8
13 PA.11
M480 SERIES DATASHEET
2
9
14 PA.10
May 08, 2020
Description
Page 102 of 523
Rev 3.00
M480
64 128 Pin Name
Pin Pin
10
MFP
Description
USCI0_DAT0
I/O
MFP6
USCI0 data 0 pin.
I2C2_SDA
I/O
MFP7
I2C2 data input/output pin.
BPWM0_CH1
I/O
MFP9
BPWM0 channel 1 output/capture input.
QEI1_INDEX
I
MFP10
Quadrature encoder 1 index input
ECAP0_IC0
I
MFP11
Enhanced capture unit 0 input 0 pin.
TM1_EXT
I/O
MFP13
Timer1 event counter input/toggle output pin.
DAC0_ST
I
MFP14
DAC0 external trigger input.
SWDH_CLK
O
MFP15
Serial Wire Debug Host Clock output
I/O
MFP0
General purpose digital I/O pin.
OPA1_N
A
MFP1
Operational amplifier 1 negative input pin.
EBI_MCLK
O
MFP2
EBI external clock output pin.
SC2_DAT
I/O
MFP3
Smart Card 2 data pin.
SPI2_MISO
I/O
MFP4
SPI2 MISO (Master In, Slave Out) pin.
SD1_DAT1
I/O
MFP5
SD/SDIO1 data line bit 1.
USCI0_DAT1
I/O
MFP6
USCI0 data 1 pin.
UART1_TXD
O
MFP7
UART1 data transmitter output pin.
BPWM0_CH2
I/O
MFP9
BPWM0 channel 2 output/capture input.
QEI1_A
I
MFP10
Quadrature encoder 1 phase A input
ECAP0_IC1
I
MFP11
Enhanced capture unit 0 input 1 pin.
TM2_EXT
I/O
MFP13
Timer2 event counter input/toggle output pin.
SWDH_DAT
I/O
MFP15
Serial Wire Debug Host Data input/output pin
I/O
MFP0
General purpose digital I/O pin.
OPA1_P
A
MFP1
Operational amplifier 1 positive input pin.
EBI_ALE
O
MFP2
EBI address latch enable output pin.
SC2_CLK
O
MFP3
Smart Card 2 clock pin.
SPI2_MOSI
I/O
MFP4
SPI2 MOSI (Master Out, Slave In) pin.
SD1_DAT0
I/O
MFP5
SD/SDIO1 data line bit 0.
USCI0_CTL1
I/O
MFP6
USCI0 control 1 pin.
UART1_RXD
I
MFP7
UART1 data receiver input pin.
BPWM0_CH3
I/O
MFP9
BPWM0 channel 3 output/capture input.
QEI1_B
I
MFP10
Quadrature encoder 1 phase B input
ECAP0_IC2
I
MFP11
Enhanced capture unit 0 input 2 pin.
I/O
MFP13
Timer3 event counter input/toggle output pin.
I
MFP15
External interrupt 4 input pin.
15 PA.9
16 PA.8
TM3_EXT
INT4
May 08, 2020
Page 103 of 523
M480 SERIES DATASHEET
11
Type
Rev 3.00
M480
64 128 Pin Name
Pin Pin
Type
MFP
Description
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR10
O
MFP2
EBI address bus bit 10.
SC2_nCD
I
MFP3
Smart Card 2 card detect pin.
SPI2_I2SMCLK
I/O
MFP4
SPI2 I2S master clock output pin
CAN1_TXD
O
MFP5
CAN1 bus transmitter output.
USCI0_CTL0
I/O
MFP6
USCI0 control 0 pin.
UART2_TXD
O
MFP7
UART2 data transmitter output pin.
BPWM0_CH4
I/O
MFP9
BPWM0 channel 4 output/capture input.
CLKO
O
MFP13
Clock Out
EADC0_ST
I
MFP14
EADC0 external trigger input.
I/O
MFP0
General purpose digital I/O pin.
OPA2_O
A
MFP1
Operational amplifier 2 output pin.
EBI_nCS0
O
MFP2
EBI chip select 0 output pin.
CAN1_RXD
I
MFP5
CAN1 bus receiver input.
UART2_RXD
I
MFP7
UART2 data receiver input pin.
BPWM0_CH5
I/O
MFP9
BPWM0 channel 5 output/capture input.
QEI0_INDEX
I
MFP10
Quadrature encoder 0 index input
CLKO
O
MFP13
Clock Out
EADC0_ST
I
MFP14
EADC0 external trigger input.
INT5
I
MFP15
External interrupt 5 input pin.
I/O
MFP0
General purpose digital I/O pin.
OPA2_N
A
MFP1
Operational amplifier 2 negative input pin.
EBI_nCS1
O
MFP2
EBI chip select 1 output pin.
UART1_TXD
O
MFP3
UART1 data transmitter output pin.
CAN0_TXD
O
MFP4
CAN0 bus transmitter output.
QEI0_A
I
MFP10
Quadrature encoder 0 phase A input
INT6
I
MFP15
External interrupt 6 input pin.
I/O
MFP0
General purpose digital I/O pin.
OPA2_P
A
MFP1
Operational amplifier 2 positive input pin.
EBI_nCS2
O
MFP2
EBI chip select 2 output pin.
UART1_RXD
I
MFP3
UART1 data receiver input pin.
CAN0_RXD
I
MFP4
CAN0 bus receiver input.
QEI0_B
I
MFP10
Quadrature encoder 0 phase B input
INT7
I
MFP15
External interrupt 7 input pin.
17 PC.13
18 PD.12
M480 SERIES DATASHEET
19 PD.11
20 PD.10
May 08, 2020
Page 104 of 523
Rev 3.00
M480
Type
MFP
Description
21 PG.2
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR11
O
MFP2
EBI address bus bit 11.
SPI2_SS
I/O
MFP3
SPI2 slave select pin.
I2C0_SMBAL
O
MFP4
I2C0 SMBus SMBALTER pin
I2C1_SCL
I/O
MFP5
I2C1 clock pin.
TM0
I/O
MFP13
Timer0 event counter input/toggle output pin.
22 PG.3
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR12
O
MFP2
EBI address bus bit 12.
SPI2_CLK
I/O
MFP3
SPI2 serial clock pin.
I C0_SMBSUS
O
MFP4
I2C0 SMBus SMBSUS pin (PMBus CONTROL pin)
I2C1_SDA
I/O
MFP5
I2C1 data input/output pin.
TM1
I/O
MFP13
Timer1 event counter input/toggle output pin.
23 PG.4
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR13
O
MFP2
EBI address bus bit 13.
SPI2_MISO
I/O
MFP3
SPI2 MISO (Master In, Slave Out) pin.
TM2
I/O
MFP13
Timer2 event counter input/toggle output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR14
O
MFP2
EBI address bus bit 14.
SPI2_MOSI
I/O
MFP3
SPI2 MOSI (Master Out, Slave In) pin.
TAMPER5
I/O
MFP10
TAMPER detector loop pin 5.
TM3
I/O
MFP13
Timer3 event counter input/toggle output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR15
O
MFP2
EBI address bus bit 15.
SC0_nCD
I
MFP3
Smart Card 0 card detect pin.
I S0_BCLK
O
MFP4
I2S0 bit clock output pin.
SPI0_I2SMCLK
I/O
MFP5
SPI0 I2S master clock output pin
TAMPER4
I/O
MFP10
TAMPER detector loop pin 4.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR16
O
MFP2
EBI address bus bit 16.
SC0_PWR
O
MFP3
Smart Card 0 power pin.
I2S0_MCLK
O
MFP4
I2S0 master clock output pin.
SPI0_SS
I/O
MFP5
SPI0 slave select pin.
TAMPER3
I/O
MFP10
TAMPER detector loop pin 3.
I/O
MFP0
General purpose digital I/O pin.
2
24 PF.11
25 PF.10
2
26 PF.9
27 PF.8
May 08, 2020
Page 105 of 523
M480 SERIES DATASHEET
64 128 Pin Name
Pin Pin
Rev 3.00
M480
64 128 Pin Name
Pin Pin
Type
MFP
Description
EBI_ADR17
O
MFP2
EBI address bus bit 17.
SC0_RST
O
MFP3
Smart Card 0 reset pin.
I
MFP4
I2S0 data input pin.
SPI0_CLK
I/O
MFP5
SPI0 serial clock pin.
TAMPER2
I/O
MFP10
TAMPER detector loop pin 2.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR18
O
MFP2
EBI address bus bit 18.
SC0_DAT
I/O
MFP3
Smart Card 0 data pin.
I2S0_DO
O
MFP4
I2S0 data output pin.
SPI0_MISO
I/O
MFP5
SPI0 MISO (Master In, Slave Out) pin.
UART4_TXD
O
MFP6
UART4 data transmitter output pin.
TAMPER1
I/O
MFP10
TAMPER detector loop pin 1.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR19
O
MFP2
EBI address bus bit 19.
SC0_CLK
O
MFP3
Smart Card 0 clock pin.
I2S0_LRCK
O
MFP4
I2S0 left right channel clock output pin.
SPI0_MOSI
I/O
MFP5
SPI0 MOSI (Master Out, Slave In) pin.
UART4_RXD
I
MFP6
UART4 data receiver input pin.
EBI_nCS0
O
MFP7
EBI chip select 0 output pin.
TAMPER0
I/O
MFP10
TAMPER detector loop pin 0.
2
I S0_DI
28 PF.7
12
29 PF.6
M480 SERIES DATASHEET
13
30 VDD
P
MFP0
Power supply for I/O ports and LDO source for internal PLL
and digital circuit.
14
31 PF.5
I/O
MFP0
General purpose digital I/O pin.
UART2_RXD
I
MFP2
UART2 data receiver input pin.
UART2_nCTS
I
MFP4
UART2 clear to Send input pin.
BPWM0_CH4
I/O
MFP8
BPWM0 channel 4 output/capture input.
EPWM0_SYNC_OUT
O
MFP9
EPWM0 counter synchronous trigger output pin.
X32_IN
I
MFP10
External 32.768 kHz crystal input pin.
EADC0_ST
I
MFP11
EADC0 external trigger input.
I/O
MFP0
General purpose digital I/O pin.
UART2_TXD
O
MFP2
UART2 data transmitter output pin.
UART2_nRTS
O
MFP4
UART2 request to Send output pin.
BPWM0_CH5
I/O
MFP8
BPWM0 channel 5 output/capture input.
X32_OUT
O
MFP10
External 32.768 kHz crystal output pin.
15
32 PF.4
May 08, 2020
Page 106 of 523
Rev 3.00
M480
Type
MFP
Description
33 PH.4
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR3
O
MFP2
EBI address bus bit 3.
SPI1_MISO
I/O
MFP3
SPI1 MISO (Master In, Slave Out) pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR2
O
MFP2
EBI address bus bit 2.
SPI1_MOSI
I/O
MFP3
SPI1 MOSI (Master Out, Slave In) pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR1
O
MFP2
EBI address bus bit 1.
SPI1_CLK
I/O
MFP3
SPI1 serial clock pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR0
O
MFP2
EBI address bus bit 0.
SPI1_SS
I/O
MFP3
SPI1 slave select pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_nCS0
O
MFP2
EBI chip select 0 output pin.
UART0_TXD
O
MFP3
UART0 data transmitter output pin.
I2C0_SCL
I/O
MFP4
I2C0 clock pin.
I
MFP10
External 4~24 MHz (high speed) crystal input pin.
I/O
MFP11
BPWM1 channel 0 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_nCS1
O
MFP2
EBI chip select 1 output pin.
UART0_RXD
I
MFP3
UART0 data receiver input pin.
I2C0_SDA
I/O
MFP4
I2C0 data input/output pin.
QSPI0_CLK
I/O
MFP5
QSPI0 serial clock pin.
XT1_OUT
O
MFP10
External 4~24 MHz (high speed) crystal output pin.
BPWM1_CH1
I/O
MFP11
BPWM1 channel 1 output/capture input.
39 VSS
P
MFP0
Ground pin for digital circuit.
40 VDD
P
MFP0
Power supply for I/O ports and LDO source for internal PLL
and digital circuit.
41 PE.8
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR10
O
MFP2
EBI address bus bit 10.
I2S0_BCLK
O
MFP4
I2S0 bit clock output pin.
SPI2_CLK
I/O
MFP5
SPI2 serial clock pin.
USCI1_CTL1
I/O
MFP6
USCI1 control 1 pin.
UART2_TXD
O
MFP7
UART2 data transmitter output pin.
34 PH.5
35 PH.6
36 PH.7
16
37 PF.3
XT1_IN
BPWM1_CH0
17
38 PF.2
May 08, 2020
Page 107 of 523
Rev 3.00
M480 SERIES DATASHEET
64 128 Pin Name
Pin Pin
M480
64 128 Pin Name
Pin Pin
Type
MFP
I/O
MFP10
EPWM0 channel 0 output/capture input.
EPWM0_BRAKE0
I
MFP11
EPWM0 Brake 0 input pin.
ECAP0_IC0
I
MFP12
Enhanced capture unit 0 input 0 pin.
TRACE_CLK
O
MFP14
ETM Trace Clock output pin
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR11
O
MFP2
EBI address bus bit 11.
I2S0_MCLK
O
MFP4
I2S0 master clock output pin.
SPI2_MISO
I/O
MFP5
SPI2 MISO (Master In, Slave Out) pin.
USCI1_CTL0
I/O
MFP6
USCI1 control 0 pin.
UART2_RXD
I
MFP7
UART2 data receiver input pin.
EPWM0_CH1
I/O
MFP10
EPWM0 channel 1 output/capture input.
EPWM0_BRAKE1
I
MFP11
EPWM0 Brake 1 input pin.
ECAP0_IC1
I
MFP12
Enhanced capture unit 0 input 1 pin.
TRACE_DATA0
O
MFP14
ETM Trace Data 0 output pin
I/O
MFP0
General purpose digital I/O pin.
O
MFP2
EBI address bus bit 12.
I
MFP4
I2S0 data input pin.
SPI2_MOSI
I/O
MFP5
SPI2 MOSI (Master Out, Slave In) pin.
USCI1_DAT0
I/O
MFP6
USCI1 data 0 pin.
UART3_TXD
O
MFP7
UART3 data transmitter output pin.
EPWM0_CH2
I/O
MFP10
EPWM0 channel 2 output/capture input.
EPWM1_BRAKE0
I
MFP11
EPWM1 Brake 0 input pin.
ECAP0_IC2
I
MFP12
Enhanced capture unit 0 input 2 pin.
TRACE_DATA1
O
MFP14
ETM Trace Data 1 output pin
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR13
O
MFP2
EBI address bus bit 13.
I2S0_DO
O
MFP4
I2S0 data output pin.
SPI2_SS
I/O
MFP5
SPI2 slave select pin.
USCI1_DAT1
I/O
MFP6
USCI1 data 1 pin.
UART3_RXD
I
MFP7
UART3 data receiver input pin.
UART1_nCTS
I
MFP8
UART1 clear to Send input pin.
EPWM0_CH3
I/O
MFP10
EPWM0 channel 3 output/capture input.
EPWM1_BRAKE1
I
MFP11
EPWM1 Brake 1 input pin.
ECAP1_IC2
I
MFP13
Enhanced capture unit 1 input 2 pin.
EPWM0_CH0
42 PE.9
43 PE.10
EBI_ADR12
2
I S0_DI
M480 SERIES DATASHEET
44 PE.11
May 08, 2020
Description
Page 108 of 523
Rev 3.00
M480
64 128 Pin Name
Pin Pin
MFP
O
MFP14
ETM Trace Data 2 output pin
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR14
O
MFP2
EBI address bus bit 14.
I2S0_LRCK
O
MFP4
I2S0 left right channel clock output pin.
SPI2_I2SMCLK
I/O
MFP5
SPI2 I2S master clock output pin
USCI1_CLK
I/O
MFP6
USCI1 clock pin.
UART1_nRTS
O
MFP8
UART1 request to Send output pin.
EPWM0_CH4
I/O
MFP10
EPWM0 channel 4 output/capture input.
ECAP1_IC1
I
MFP13
Enhanced capture unit 1 input 1 pin.
TRACE_DATA3
O
MFP14
ETM Trace Data 3 output pin
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR15
O
MFP2
EBI address bus bit 15.
I2C0_SCL
I/O
MFP4
I2C0 clock pin.
UART4_nRTS
O
MFP5
UART4 request to Send output pin.
UART1_TXD
O
MFP8
UART1 data transmitter output pin.
EPWM0_CH5
I/O
MFP10
EPWM0 channel 5 output/capture input.
EPWM1_CH0
I/O
MFP11
EPWM1 channel 0 output/capture input.
BPWM1_CH5
I/O
MFP12
BPWM1 channel 5 output/capture input.
I
MFP13
Enhanced capture unit 1 input 0 pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR16
O
MFP2
EBI address bus bit 16.
I2C0_SDA
I/O
MFP4
I2C0 data input/output pin.
UART4_nCTS
I
MFP5
UART4 clear to Send input pin.
UART1_RXD
I
MFP8
UART1 data receiver input pin.
EPWM1_CH1
I/O
MFP11
EPWM1 channel 1 output/capture input.
BPWM1_CH4
I/O
MFP12
BPWM1 channel 4 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD9
I/O
MFP2
EBI address/data bus bit 9.
SPI1_MISO
I/O
MFP4
SPI1 MISO (Master In, Slave Out) pin.
UART4_TXD
O
MFP5
UART4 data transmitter output pin.
SC2_PWR
O
MFP6
Smart Card 2 power pin.
UART0_nCTS
I
MFP7
UART0 clear to Send input pin.
I2C1_SMBAL
O
MFP8
I2C1 SMBus SMBALTER pin
EPWM1_CH2
I/O
MFP11
EPWM1 channel 2 output/capture input.
TRACE_DATA2
45 PE.12
46 PE.13
ECAP1_IC0
47 PC.8
18
48 PC.7
May 08, 2020
Description
Page 109 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
64 128 Pin Name
Pin Pin
19
Type
MFP
BPWM1_CH0
I/O
MFP12
BPWM1 channel 0 output/capture input.
TM0
I/O
MFP14
Timer0 event counter input/toggle output pin.
INT3
I
MFP15
External interrupt 3 input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD8
I/O
MFP2
EBI address/data bus bit 8.
SPI1_MOSI
I/O
MFP4
SPI1 MOSI (Master Out, Slave In) pin.
UART4_RXD
I
MFP5
UART4 data receiver input pin.
SC2_RST
O
MFP6
Smart Card 2 reset pin.
UART0_nRTS
O
MFP7
UART0 request to Send output pin.
I C1_SMBSUS
O
MFP8
I2C1 SMBus SMBSUS pin (PMBus CONTROL pin)
EPWM1_CH3
I/O
MFP11
EPWM1 channel 3 output/capture input.
BPWM1_CH1
I/O
MFP12
BPWM1 channel 1 output/capture input.
TM1
I/O
MFP14
Timer1 event counter input/toggle output pin.
INT2
I
MFP15
External interrupt 2 input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD7
I/O
MFP2
EBI address/data bus bit 7.
SPI1_CLK
I/O
MFP4
SPI1 serial clock pin.
SC2_DAT
I/O
MFP6
Smart Card 2 data pin.
UART0_TXD
O
MFP7
UART0 data transmitter output pin.
I2C1_SCL
I/O
MFP8
I2C1 clock pin.
EPWM1_CH4
I/O
MFP11
EPWM1 channel 4 output/capture input.
BPWM1_CH2
I/O
MFP12
BPWM1 channel 2 output/capture input.
ACMP0_WLAT
I
MFP13
Analog comparator 0 window latch input pin
TM2
I/O
MFP14
Timer2 event counter input/toggle output pin.
INT1
I
MFP15
External interrupt 1 input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD6
I/O
MFP2
EBI address/data bus bit 6.
SPI1_SS
I/O
MFP4
SPI1 slave select pin.
SD1_nCD
I
MFP5
SD/SDIO1 card detect input pin
SC2_CLK
O
MFP6
Smart Card 2 clock pin.
UART0_RXD
I
MFP7
UART0 data receiver input pin.
I C1_SDA
I/O
MFP8
I2C1 data input/output pin.
EPWM1_CH5
I/O
MFP11
EPWM1 channel 5 output/capture input.
BPWM1_CH3
I/O
MFP12
BPWM1 channel 3 output/capture input.
49 PC.6
2
20
M480 SERIES DATASHEET
21
50 PA.7
51 PA.6
2
May 08, 2020
Description
Page 110 of 523
Rev 3.00
M480
64 128 Pin Name
Pin Pin
Type
MFP
I
MFP13
Analog comparator 1 window latch input pin
TM3
I/O
MFP14
Timer3 event counter input/toggle output pin.
INT0
I
MFP15
External interrupt 0 input pin.
ACMP1_WLAT
Description
22
52 VSS
P
MFP0
Ground pin for digital circuit.
23
53 VDD
P
MFP0
Power supply for I/O ports and LDO source for internal PLL
and digital circuit.
24
54 LDO_CAP
A
MFP0
LDO output pin.
Note: This pin needs to be connected with an external
capacitor.
25
I/O
MFP0
General purpose digital I/O pin.
SPIM_D2
I/O
MFP2
SPIM data 2 pin for Quad Mode I/O.
QSPI0_MISO1
I/O
MFP3
QSPI0 MISO1 (Master In, Slave Out) pin.
SPI1_I2SMCLK
I/O
MFP4
SPI1 I2S master clock output pin
SD1_CMD
I/O
MFP5
SD/SDIO1 command/response pin
SC2_nCD
I
MFP6
Smart Card 2 card detect pin.
UART0_nCTS
I
MFP7
UART0 clear to Send input pin.
UART5_TXD
O
MFP8
UART5 data transmitter output pin.
I2C0_SCL
I/O
MFP9
I2C0 clock pin.
CAN0_TXD
O
MFP10
CAN0 bus transmitter output.
BPWM0_CH5
I/O
MFP12
BPWM0 channel 5 output/capture input.
EPWM0_CH0
I/O
MFP13
EPWM0 channel 0 output/capture input.
QEI0_INDEX
I
MFP14
Quadrature encoder 0 index input
I/O
MFP0
General purpose digital I/O pin.
SPIM_D3
I/O
MFP2
SPIM data 3 pin for Quad Mode I/O.
QSPI0_MOSI1
I/O
MFP3
QSPI0 MOSI1 (Master Out, Slave In) pin.
SPI0_I2SMCLK
I/O
MFP4
SPI0 I2S master clock output pin
SD1_CLK
O
MFP5
SD/SDIO1 clock output pin
SC0_nCD
I
MFP6
Smart Card 0 card detect pin.
UART0_nRTS
O
MFP7
UART0 request to Send output pin.
UART5_RXD
I
MFP8
UART5 data receiver input pin.
I/O
MFP9
I2C0 data input/output pin.
I
MFP10
CAN0 bus receiver input.
BPWM0_CH4
I/O
MFP12
BPWM0 channel 4 output/capture input.
EPWM0_CH1
I/O
MFP13
EPWM0 channel 1 output/capture input.
I
MFP14
Quadrature encoder 0 phase A input
56 PA.4
I2C0_SDA
CAN0_RXD
QEI0_A
May 08, 2020
Page 111 of 523
M480 SERIES DATASHEET
26
55 PA.5
Rev 3.00
M480
64 128 Pin Name
Pin Pin
27
Type
MFP
Description
I/O
MFP0
General purpose digital I/O pin.
SPIM_SS
I/O
MFP2
SPIM slave select pin.
QSPI0_SS
I/O
MFP3
QSPI0 slave select pin.
SPI0_SS
I/O
MFP4
SPI0 slave select pin.
SD1_DAT3
I/O
MFP5
SD/SDIO1 data line bit 3.
SC0_PWR
O
MFP6
Smart Card 0 power pin.
UART4_TXD
O
MFP7
UART4 data transmitter output pin.
UART1_TXD
O
MFP8
UART1 data transmitter output pin.
I2C1_SCL
I/O
MFP9
I2C1 clock pin.
BPWM0_CH3
I/O
MFP12
BPWM0 channel 3 output/capture input.
EPWM0_CH2
I/O
MFP13
EPWM0 channel 2 output/capture input.
I
MFP14
Quadrature encoder 0 phase B input
I/O
MFP0
General purpose digital I/O pin.
SPIM_CLK
I/O
MFP2
SPIM serial clock pin.
QSPI0_CLK
I/O
MFP3
QSPI0 serial clock pin.
SPI0_CLK
I/O
MFP4
SPI0 serial clock pin.
SD1_DAT2
I/O
MFP5
SD/SDIO1 data line bit 2.
SC0_RST
O
MFP6
Smart Card 0 reset pin.
UART4_RXD
I
MFP7
UART4 data receiver input pin.
UART1_RXD
I
MFP8
UART1 data receiver input pin.
I C1_SDA
I/O
MFP9
I2C1 data input/output pin.
BPWM0_CH2
I/O
MFP12
BPWM0 channel 2 output/capture input.
EPWM0_CH3
I/O
MFP13
EPWM0 channel 3 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
SPIM_MISO
I/O
MFP2
SPIM MISO (Master In, Slave Out) pin.
QSPI0_MISO0
I/O
MFP3
QSPI0 MISO0 (Master In, Slave Out) pin.
SPI0_MISO
I/O
MFP4
SPI0 MISO (Master In, Slave Out) pin.
SD1_DAT1
I/O
MFP5
SD/SDIO1 data line bit 1.
SC0_DAT
I/O
MFP6
Smart Card 0 data pin.
UART0_TXD
O
MFP7
UART0 data transmitter output pin.
UART1_nCTS
I
MFP8
UART1 clear to Send input pin.
I C2_SCL
I/O
MFP9
I2C2 clock pin.
BPWM0_CH1
I/O
MFP12
BPWM0 channel 1 output/capture input.
EPWM0_CH4
I/O
MFP13
EPWM0 channel 4 output/capture input.
57 PA.3
QEI0_B
28
58 PA.2
M480 SERIES DATASHEET
2
29
59 PA.1
2
May 08, 2020
Page 112 of 523
Rev 3.00
M480
64 128 Pin Name
Pin Pin
MFP
I
MFP15
DAC1 external trigger input.
I/O
MFP0
General purpose digital I/O pin.
SPIM_MOSI
I/O
MFP2
SPIM MOSI (Master Out, Slave In) pin.
QSPI0_MOSI0
I/O
MFP3
QSPI0 MOSI0 (Master Out, Slave In) pin.
SPI0_MOSI
I/O
MFP4
SPI0 MOSI (Master Out, Slave In) pin.
SD1_DAT0
I/O
MFP5
SD/SDIO1 data line bit 0.
SC0_CLK
O
MFP6
Smart Card 0 clock pin.
UART0_RXD
I
MFP7
UART0 data receiver input pin.
UART1_nRTS
O
MFP8
UART1 request to Send output pin.
I C2_SDA
I/O
MFP9
I2C2 data input/output pin.
BPWM0_CH0
I/O
MFP12
BPWM0 channel 0 output/capture input.
EPWM0_CH5
I/O
MFP13
EPWM0 channel 5 output/capture input.
I
MFP15
DAC0 external trigger input.
61 VDDIO
P
MFP0
Power supply for PA.0~PA.5.
62 PE.14
I/O
MFP0
General purpose digital I/O pin.
EBI_AD8
I/O
MFP2
EBI address/data bus bit 8.
UART2_TXD
O
MFP3
UART2 data transmitter output pin.
CAN0_TXD
O
MFP4
CAN0 bus transmitter output.
SD1_nCD
I
MFP5
SD/SDIO1 card detect input pin
I/O
MFP0
General purpose digital I/O pin.
I/O
MFP2
EBI address/data bus bit 9.
UART2_RXD
I
MFP3
UART2 data receiver input pin.
CAN0_RXD
I
MFP4
CAN0 bus receiver input.
I
MFP0
External reset input: active LOW, with an internal pull-up. Set
this pin low reset to initial state.
DAC1_ST
30
60 PA.0
2
DAC0_ST
31
63 PE.15
EBI_AD9
32
64 nRESET
Description
Note: It is recommended to use 10 kΩ pull-up resistor and 10
uF capacitor on nRESET pin.
33
65 PF.0
I/O
MFP0
General purpose digital I/O pin.
O
MFP2
UART1 data transmitter output pin.
I C1_SCL
I/O
MFP3
I2C1 clock pin.
BPWM1_CH0
I/O
MFP12
BPWM1 channel 0 output/capture input.
ICE_DAT
O
MFP14
Serial wired debugger data pin.
UART1_TXD
2
Note: It is recommended to use 100 kΩ pull-up resistor on
ICE_DAT pin.
34
66 PF.1
UART1_RXD
May 08, 2020
I/O
MFP0
General purpose digital I/O pin.
I
MFP2
UART1 data receiver input pin.
Page 113 of 523
Rev 3.00
M480 SERIES DATASHEET
Type
M480
64 128 Pin Name
Pin Pin
Type
MFP
Description
I2C1_SDA
I/O
MFP3
I2C1 data input/output pin.
BPWM1_CH1
I/O
MFP12
BPWM1 channel 1 output/capture input.
I
MFP14
Serial wired debugger clock pin.
ICE_CLK
Note: It is recommended to use 100 kΩ pull-up resistor on
ICE_CLK pin.
67 PD.9
I/O
MFP0
General purpose digital I/O pin.
EBI_AD7
I/O
MFP2
EBI address/data bus bit 7.
I2C2_SCL
I/O
MFP3
I2C2 clock pin.
I
MFP4
UART2 clear to Send input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD6
I/O
MFP2
EBI address/data bus bit 6.
I2C2_SDA
I/O
MFP3
I2C2 data input/output pin.
UART2_nRTS
O
MFP4
UART2 request to Send output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD5
I/O
MFP2
EBI address/data bus bit 5.
SPIM_D2
I/O
MFP3
SPIM data 2 pin for Quad Mode I/O.
QSPI0_MISO1
I/O
MFP4
QSPI0 MISO1 (Master In, Slave Out) pin.
UART2_TXD
O
MFP8
UART2 data transmitter output pin.
I2C1_SCL
I/O
MFP9
I2C1 clock pin.
CAN0_TXD
O
MFP10
CAN0 bus transmitter output.
UART4_TXD
O
MFP11
UART4 data transmitter output pin.
EPWM1_CH0
I/O
MFP12
EPWM1 channel 0 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD4
I/O
MFP2
EBI address/data bus bit 4.
SPIM_D3
I/O
MFP3
SPIM data 3 pin for Quad Mode I/O.
QSPI0_MOSI1
I/O
MFP4
QSPI0 MOSI1 (Master Out, Slave In) pin.
SC1_nCD
I
MFP5
Smart Card 1 card detect pin.
I2S0_BCLK
O
MFP6
I2S0 bit clock output pin.
SPI1_I2SMCLK
I/O
MFP7
SPI1 I2S master clock output pin
I
MFP8
UART2 data receiver input pin.
I/O
MFP9
I2C1 data input/output pin.
CAN0_RXD
I
MFP10
CAN0 bus receiver input.
UART4_RXD
I
MFP11
UART4 data receiver input pin.
EPWM1_CH1
I/O
MFP12
EPWM1 channel 1 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
UART2_nCTS
68 PD.8
35
M480 SERIES DATASHEET
36
69 PC.5
70 PC.4
UART2_RXD
2
I C1_SDA
37
71 PC.3
May 08, 2020
Page 114 of 523
Rev 3.00
M480
64 128 Pin Name
Pin Pin
MFP
Description
EBI_AD3
I/O
MFP2
EBI address/data bus bit 3.
SPIM_SS
I/O
MFP3
SPIM slave select pin.
QSPI0_SS
I/O
MFP4
QSPI0 slave select pin.
SC1_PWR
O
MFP5
Smart Card 1 power pin.
I S0_MCLK
O
MFP6
I2S0 master clock output pin.
SPI1_MISO
I/O
MFP7
SPI1 MISO (Master In, Slave Out) pin.
UART2_nRTS
O
MFP8
UART2 request to Send output pin.
I C0_SMBAL
O
MFP9
I2C0 SMBus SMBALTER pin
CAN1_TXD
O
MFP10
CAN1 bus transmitter output.
UART3_TXD
O
MFP11
UART3 data transmitter output pin.
EPWM1_CH2
I/O
MFP12
EPWM1 channel 2 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD2
I/O
MFP2
EBI address/data bus bit 2.
SPIM_CLK
I/O
MFP3
SPIM serial clock pin.
QSPI0_CLK
I/O
MFP4
QSPI0 serial clock pin.
SC1_RST
O
MFP5
Smart Card 1 reset pin.
I
MFP6
I2S0 data input pin.
I/O
MFP7
SPI1 MOSI (Master Out, Slave In) pin.
UART2_nCTS
I
MFP8
UART2 clear to Send input pin.
I2C0_SMBSUS
O
MFP9
I2C0 SMBus SMBSUS pin (PMBus CONTROL pin)
CAN1_RXD
I
MFP10
CAN1 bus receiver input.
UART3_RXD
I
MFP11
UART3 data receiver input pin.
EPWM1_CH3
I/O
MFP12
EPWM1 channel 3 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD1
I/O
MFP2
EBI address/data bus bit 1.
SPIM_MISO
I/O
MFP3
SPIM MISO (Master In, Slave Out) pin.
QSPI0_MISO0
I/O
MFP4
QSPI0 MISO0 (Master In, Slave Out) pin.
SC1_DAT
I/O
MFP5
Smart Card 1 data pin.
I2S0_DO
O
MFP6
I2S0 data output pin.
SPI1_CLK
I/O
MFP7
SPI1 serial clock pin.
UART2_TXD
O
MFP8
UART2 data transmitter output pin.
I C0_SCL
I/O
MFP9
I2C0 clock pin.
EPWM1_CH4
I/O
MFP12
EPWM1 channel 4 output/capture input.
ACMP0_O
O
MFP14
Analog comparator 0 output pin.
2
2
38
72 PC.2
2
I S0_DI
SPI1_MOSI
39
73 PC.1
2
May 08, 2020
Page 115 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
64 128 Pin Name
Pin Pin
40
Type
MFP
Description
I/O
MFP0
General purpose digital I/O pin.
EBI_AD0
I/O
MFP2
EBI address/data bus bit 0.
SPIM_MOSI
I/O
MFP3
SPIM MOSI (Master Out, Slave In) pin.
QSPI0_MOSI0
I/O
MFP4
QSPI0 MOSI0 (Master Out, Slave In) pin.
SC1_CLK
O
MFP5
Smart Card 1 clock pin.
I2S0_LRCK
O
MFP6
I2S0 left right channel clock output pin.
SPI1_SS
I/O
MFP7
SPI1 slave select pin.
I
MFP8
UART2 data receiver input pin.
I2C0_SDA
I/O
MFP9
I2C0 data input/output pin.
EPWM1_CH5
I/O
MFP12
EPWM1 channel 5 output/capture input.
ACMP1_O
O
MFP14
Analog comparator 1 output pin.
75 VSS
P
MFP0
Ground pin for digital circuit.
76 VDD
P
MFP0
Power supply for I/O ports and LDO source for internal PLL
and digital circuit.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD0
I/O
MFP2
EBI address/data bus bit 0.
SD1_DAT3
I/O
MFP3
SD/SDIO1 data line bit 3.
SPIM_D2
I/O
MFP4
SPIM data 2 pin for Quad Mode I/O.
BPWM0_CH5
I/O
MFP12
BPWM0 channel 5 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD1
I/O
MFP2
EBI address/data bus bit 1.
SD1_DAT2
I/O
MFP3
SD/SDIO1 data line bit 2.
SPIM_D3
I/O
MFP4
SPIM data 3 pin for Quad Mode I/O.
BPWM0_CH4
I/O
MFP12
BPWM0 channel 4 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD2
I/O
MFP2
EBI address/data bus bit 2.
SD1_DAT1
I/O
MFP3
SD/SDIO1 data line bit 1.
SPIM_SS
I/O
MFP4
SPIM slave select pin.
BPWM0_CH3
I/O
MFP12
BPWM0 channel 3 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD3
I/O
MFP2
EBI address/data bus bit 3.
SD1_DAT0
I/O
MFP3
SD/SDIO1 data line bit 0.
SPIM_CLK
I/O
MFP4
SPIM serial clock pin.
BPWM0_CH2
I/O
MFP12
BPWM0 channel 2 output/capture input.
74 PC.0
UART2_RXD
77 PG.9
78 PG.10
M480 SERIES DATASHEET
79 PG.11
80 PG.12
May 08, 2020
Page 116 of 523
Rev 3.00
M480
64 128 Pin Name
Pin Pin
MFP
Description
I/O
MFP0
General purpose digital I/O pin.
EBI_AD4
I/O
MFP2
EBI address/data bus bit 4.
SD1_CMD
I/O
MFP3
SD/SDIO1 command/response pin
SPIM_MISO
I/O
MFP4
SPIM MISO (Master In, Slave Out) pin.
BPWM0_CH1
I/O
MFP12
BPWM0 channel 1 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD5
I/O
MFP2
EBI address/data bus bit 5.
SD1_CLK
O
MFP3
SD/SDIO1 clock output pin
SPIM_MOSI
I/O
MFP4
SPIM MOSI (Master Out, Slave In) pin.
BPWM0_CH0
I/O
MFP12
BPWM0 channel 0 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
SD1_nCD
I
MFP3
SD/SDIO1 card detect input pin
CLKO
O
MFP14
Clock Out
EADC0_ST
I
MFP15
EADC0 external trigger input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD10
I/O
MFP2
EBI address/data bus bit 10.
SD0_nCD
I
MFP3
SD/SDIO0 card detect input pin
SPI0_I2SMCLK
I/O
MFP4
SPI0 I2S master clock output pin
SPI1_I2SMCLK
I/O
MFP5
SPI1 I2S master clock output pin
I
MFP7
Smart Card 2 card detect pin.
I/O
MFP0
General purpose digital I/O pin.
I2S0_BCLK
O
MFP2
I2S0 bit clock output pin.
UART4_TXD
O
MFP3
UART4 data transmitter output pin.
I2C1_SCL
I/O
MFP4
I2C1 clock pin.
SPI2_SS
I/O
MFP5
SPI2 slave select pin.
CAN0_TXD
O
MFP6
CAN0 bus transmitter output.
SC2_PWR
O
MFP7
Smart Card 2 power pin.
BPWM1_CH2
I/O
MFP11
BPWM1 channel 2 output/capture input.
QEI1_INDEX
I
MFP12
Quadrature encoder 1 index input
USB_VBUS
P
MFP14
Power supply from USB host or HUB.
86 PA.13
I/O
MFP0
General purpose digital I/O pin.
2
I S0_MCLK
O
MFP2
I2S0 master clock output pin.
UART4_RXD
I
MFP3
UART4 data receiver input pin.
I/O
MFP4
I2C1 data input/output pin.
81 PG.13
82 PG.14
83 PG.15
84 PD.13
SC2_nCD
85 PA.12
2
I C1_SDA
May 08, 2020
Page 117 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
64 128 Pin Name
Pin Pin
Type
MFP
Description
I/O
MFP5
SPI2 serial clock pin.
CAN0_RXD
I
MFP6
CAN0 bus receiver input.
SC2_RST
O
MFP7
Smart Card 2 reset pin.
BPWM1_CH3
I/O
MFP11
BPWM1 channel 3 output/capture input.
QEI1_A
I
MFP12
Quadrature encoder 1 phase A input
USB_D-
A
MFP14
USB differential signal D-.
87 PA.14
I/O
MFP0
General purpose digital I/O pin.
2
I S0_DI
I
MFP2
I2S0 data input pin.
UART0_TXD
O
MFP3
UART0 data transmitter output pin.
SPI2_MISO
I/O
MFP5
SPI2 MISO (Master In, Slave Out) pin.
I2C2_SCL
I/O
MFP6
I2C2 clock pin.
SC2_DAT
I/O
MFP7
Smart Card 2 data pin.
BPWM1_CH4
I/O
MFP11
BPWM1 channel 4 output/capture input.
QEI1_B
I
MFP12
Quadrature encoder 1 phase B input
USB_D+
A
MFP14
USB differential signal D+.
88 PA.15
I/O
MFP0
General purpose digital I/O pin.
2
I S0_DO
O
MFP2
I2S0 data output pin.
UART0_RXD
I
MFP3
UART0 data receiver input pin.
SPI2_MOSI
I/O
MFP5
SPI2 MOSI (Master Out, Slave In) pin.
I2C2_SDA
I/O
MFP6
I2C2 data input/output pin.
SC2_CLK
O
MFP7
Smart Card 2 clock pin.
BPWM1_CH5
I/O
MFP11
BPWM1 channel 5 output/capture input.
EPWM0_SYNC_IN
I
MFP12
EPWM0 counter synchronous trigger input pin.
USB_OTG_ID
I
MFP14
USB_ identification.
SPI2_CLK
M480 SERIES DATASHEET
41
89 HSUSB_VRES
A
MFP0
HSUSB module reference resister
42
90 HSUSB_VDD33
P
MFP0
Power supply for HSUSB VDD33
43
91 HSUSB_VBUS
P
MFP0
HSUSB Power supply from USB host or HUB.
44
92 HSUSB_D-
A
MFP0
HSUSB differential signal D-.
45
93 HSUSB_VSS
P
MFP0
Ground pin for HSUSB.
46
94 HSUSB_D+
A
MFP0
HSUSB differential signal D+.
47
95 HSUSB_VDD12_CAP
A
MFP0
HSUSB Internal power regulator output 1.2V decoupling pin.
Note: This pin needs to be connected with a 1uF capacitor.
48
96 HSUSB_ID
97 PE.7
May 08, 2020
I
MFP0
HSUSB identification.
I/O
MFP0
General purpose digital I/O pin.
Page 118 of 523
Rev 3.00
M480
64 128 Pin Name
Pin Pin
MFP
Description
SD0_CMD
I/O
MFP3
SD/SDIO0 command/response pin
SPIM_D2
I/O
MFP4
SPIM data 2 pin for Quad Mode I/O.
UART5_TXD
O
MFP8
UART5 data transmitter output pin.
CAN1_TXD
O
MFP9
CAN1 bus transmitter output.
QEI1_INDEX
I
MFP11
Quadrature encoder 1 index input
EPWM0_CH0
I/O
MFP12
EPWM0 channel 0 output/capture input.
BPWM0_CH5
I/O
MFP13
BPWM0 channel 5 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
SD0_CLK
O
MFP3
SD/SDIO0 clock output pin
SPIM_D3
I/O
MFP4
SPIM data 3 pin for Quad Mode I/O.
SPI3_I2SMCLK
I/O
MFP5
SPI3 I2S master clock output pin
I
MFP6
Smart Card 0 card detect pin.
USCI0_CTL0
I/O
MFP7
USCI0 control 0 pin.
UART5_RXD
I
MFP8
UART5 data receiver input pin.
CAN1_RXD
I
MFP9
CAN1 bus receiver input.
QEI1_A
I
MFP11
Quadrature encoder 1 phase A input
EPWM0_CH1
I/O
MFP12
EPWM0 channel 1 output/capture input.
BPWM0_CH4
I/O
MFP13
BPWM0 channel 4 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_nRD
O
MFP2
EBI read enable output pin.
SD0_DAT3
I/O
MFP3
SD/SDIO0 data line bit 3.
SPIM_SS
I/O
MFP4
SPIM slave select pin.
SPI3_SS
I/O
MFP5
SPI3 slave select pin.
SC0_PWR
O
MFP6
Smart Card 0 power pin.
USCI0_CTL1
I/O
MFP7
USCI0 control 1 pin.
I
MFP11
Quadrature encoder 1 phase B input
EPWM0_CH2
I/O
MFP12
EPWM0 channel 2 output/capture input.
BPWM0_CH3
I/O
MFP13
BPWM0 channel 3 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_nWR
O
MFP2
EBI write enable output pin.
SD0_DAT2
I/O
MFP3
SD/SDIO0 data line bit 2.
SPIM_CLK
I/O
MFP4
SPIM serial clock pin.
SPI3_CLK
I/O
MFP5
SPI3 serial clock pin.
SC0_RST
O
MFP6
Smart Card 0 reset pin.
98 PE.6
SC0_nCD
99 PE.5
QEI1_B
100 PE.4
May 08, 2020
Page 119 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
64 128 Pin Name
Pin Pin
Type
MFP
Description
USCI0_DAT1
I/O
MFP7
USCI0 data 1 pin.
QEI0_INDEX
I
MFP11
Quadrature encoder 0 index input
EPWM0_CH3
I/O
MFP12
EPWM0 channel 3 output/capture input.
BPWM0_CH2
I/O
MFP13
BPWM0 channel 2 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_MCLK
O
MFP2
EBI external clock output pin.
SD0_DAT1
I/O
MFP3
SD/SDIO0 data line bit 1.
SPIM_MISO
I/O
MFP4
SPIM MISO (Master In, Slave Out) pin.
SPI3_MISO
I/O
MFP5
SPI3 MISO (Master In, Slave Out) pin.
SC0_DAT
I/O
MFP6
Smart Card 0 data pin.
USCI0_DAT0
I/O
MFP7
USCI0 data 0 pin.
I
MFP11
Quadrature encoder 0 phase A input
EPWM0_CH4
I/O
MFP12
EPWM0 channel 4 output/capture input.
BPWM0_CH1
I/O
MFP13
BPWM0 channel 1 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_ALE
O
MFP2
EBI address latch enable output pin.
SD0_DAT0
I/O
MFP3
SD/SDIO0 data line bit 0.
SPIM_MOSI
I/O
MFP4
SPIM MOSI (Master Out, Slave In) pin.
SPI3_MOSI
I/O
MFP5
SPI3 MOSI (Master Out, Slave In) pin.
SC0_CLK
O
MFP6
Smart Card 0 clock pin.
USCI0_CLK
I/O
MFP7
USCI0 clock pin.
I
MFP11
Quadrature encoder 0 phase B input
EPWM0_CH5
I/O
MFP12
EPWM0 channel 5 output/capture input.
BPWM0_CH0
I/O
MFP13
BPWM0 channel 0 output/capture input.
103 VSS
P
MFP0
Ground pin for digital circuit.
104 VDD
P
MFP0
Power supply for I/O ports and LDO source for internal PLL
and digital circuit.
105 PE.1
I/O
MFP0
General purpose digital I/O pin.
EBI_AD10
I/O
MFP2
EBI address/data bus bit 10.
QSPI0_MISO0
I/O
MFP3
QSPI0 MISO0 (Master In, Slave Out) pin.
SC2_DAT
I/O
MFP4
Smart Card 2 data pin.
I S0_BCLK
O
MFP5
I2S0 bit clock output pin.
SPI1_MISO
I/O
MFP6
SPI1 MISO (Master In, Slave Out) pin.
UART3_TXD
O
MFP7
UART3 data transmitter output pin.
101 PE.3
QEI0_A
102 PE.2
M480 SERIES DATASHEET
QEI0_B
2
May 08, 2020
Page 120 of 523
Rev 3.00
M480
64 128 Pin Name
Pin Pin
MFP
Description
I/O
MFP8
I2C1 clock pin.
I
MFP9
UART4 clear to Send input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD11
I/O
MFP2
EBI address/data bus bit 11.
QSPI0_MOSI0
I/O
MFP3
QSPI0 MOSI0 (Master Out, Slave In) pin.
SC2_CLK
O
MFP4
Smart Card 2 clock pin.
I2S0_MCLK
O
MFP5
I2S0 master clock output pin.
SPI1_MOSI
I/O
MFP6
SPI1 MOSI (Master Out, Slave In) pin.
I
MFP7
UART3 data receiver input pin.
I C1_SDA
I/O
MFP8
I2C1 data input/output pin.
UART4_nRTS
O
MFP9
UART4 request to Send output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD12
I/O
MFP2
EBI address/data bus bit 12.
QSPI0_CLK
I/O
MFP3
QSPI0 serial clock pin.
SC2_PWR
O
MFP4
Smart Card 2 power pin.
I2S0_DI
I
MFP5
I2S0 data input pin.
SPI1_CLK
I/O
MFP6
SPI1 serial clock pin.
UART3_nRTS
O
MFP7
UART3 request to Send output pin.
I C1_SMBAL
O
MFP8
I2C1 SMBus SMBALTER pin
I2C2_SCL
I/O
MFP9
I2C2 clock pin.
UART1_TXD
O
MFP10
UART1 data transmitter output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD13
I/O
MFP2
EBI address/data bus bit 13.
QSPI0_SS
I/O
MFP3
QSPI0 slave select pin.
SC2_RST
O
MFP4
Smart Card 2 reset pin.
I2S0_DO
O
MFP5
I2S0 data output pin.
SPI1_SS
I/O
MFP6
SPI1 slave select pin.
UART3_nCTS
I
MFP7
UART3 clear to Send input pin.
I2C1_SMBSUS
O
MFP8
I2C1 SMBus SMBSUS pin (PMBus CONTROL pin)
I2C2_SDA
I/O
MFP9
I2C2 data input/output pin.
I
MFP10
UART1 data receiver input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD14
I/O
MFP2
EBI address/data bus bit 14.
QSPI0_MISO1
I/O
MFP3
QSPI0 MISO1 (Master In, Slave Out) pin.
I2C1_SCL
UART4_nCTS
106 PE.0
UART3_RXD
2
107 PH.8
2
108 PH.9
UART1_RXD
109 PH.10
May 08, 2020
Page 121 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
64 128 Pin Name
Pin Pin
Type
MFP
Description
SC2_nCD
I
MFP4
Smart Card 2 card detect pin.
I2S0_LRCK
O
MFP5
I2S0 left right channel clock output pin.
SPI1_I2SMCLK
I/O
MFP6
SPI1 I2S master clock output pin
UART4_TXD
O
MFP7
UART4 data transmitter output pin.
UART0_TXD
O
MFP8
UART0 data transmitter output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD15
I/O
MFP2
EBI address/data bus bit 15.
QSPI0_MOSI1
I/O
MFP3
QSPI0 MOSI1 (Master Out, Slave In) pin.
UART4_RXD
I
MFP7
UART4 data receiver input pin.
UART0_RXD
I
MFP8
UART0 data receiver input pin.
EPWM0_CH5
I/O
MFP11
EPWM0 channel 5 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_nCS0
O
MFP2
EBI chip select 0 output pin.
SPI3_I2SMCLK
I/O
MFP3
SPI3 I2S master clock output pin
I
MFP4
Smart Card 1 card detect pin.
I/O
MFP11
EPWM0 channel 4 output/capture input.
110 PH.11
111 PD.14
SC1_nCD
EPWM0_CH4
49
112 VSS
P
MFP0
Ground pin for digital circuit.
50
113 LDO_CAP
A
MFP0
LDO output pin.
Note: This pin needs to be connected with an external
capacitor.
M480 SERIES DATASHEET
P
MFP0
Power supply for I/O ports and LDO source for internal PLL
and digital circuit.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD11
I/O
MFP2
EBI address/data bus bit 11.
SC1_nCD
I
MFP3
Smart Card 1 card detect pin.
SPI0_I2SMCLK
I/O
MFP4
SPI0 I2S master clock output pin
USCI0_CTL0
I/O
MFP5
USCI0 control 0 pin.
QSPI0_CLK
I/O
MFP6
QSPI0 serial clock pin.
EPWM0_SYNC_IN
I
MFP11
EPWM0 counter synchronous trigger input pin.
ETM_TRACE_CLK
I
MFP12
ETM receiver Trace Clock input pin
I/O
MFP13
Timer1 event counter input/toggle output pin.
USB_VBUS_ST
I
MFP14
USB external VBUS regulator status pin.
HSUSB_VBUS_ST
I
MFP15
HSUSB external VBUS regulator status pin.
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC0 channel 15 analog input.
51
114 VDD
52
115 PC.14
TM1
53
116 PB.15
EADC0_CH15
May 08, 2020
Page 122 of 523
Rev 3.00
M480
64 128 Pin Name
Pin Pin
MFP
Description
EBI_AD12
I/O
MFP2
EBI address/data bus bit 12.
SC1_PWR
O
MFP3
Smart Card 1 power pin.
SPI0_SS
I/O
MFP4
SPI0 slave select pin.
USCI0_CTL1
I/O
MFP5
USCI0 control 1 pin.
UART0_nCTS
I
MFP6
UART0 clear to Send input pin.
UART3_TXD
O
MFP7
UART3 data transmitter output pin.
I2C2_SMBAL
O
MFP8
I2C2 SMBus SMBALTER pin
EPWM1_CH0
I/O
MFP11
EPWM1 channel 0 output/capture input.
I
MFP12
ETM receiver Trace Data 0 input pin
TM0_EXT
I/O
MFP13
Timer0 event counter input/toggle output pin.
USB_VBUS_EN
O
MFP14
USB external VBUS regulator enable pin.
HSUSB_VBUS_EN
O
MFP15
HSUSB external VBUS regulator enable pin.
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC0 channel 14 analog input.
EBI_AD13
I/O
MFP2
EBI address/data bus bit 13.
SC1_RST
O
MFP3
Smart Card 1 reset pin.
SPI0_CLK
I/O
MFP4
SPI0 serial clock pin.
USCI0_DAT1
I/O
MFP5
USCI0 data 1 pin.
UART0_nRTS
O
MFP6
UART0 request to Send output pin.
UART3_RXD
I
MFP7
UART3 data receiver input pin.
I C2_SMBSUS
O
MFP8
I2C2 SMBus SMBSUS pin (PMBus CONTROL pin)
EPWM1_CH1
I/O
MFP11
EPWM1 channel 1 output/capture input.
I
MFP12
ETM receiver Trace Data 1 input pin
TM1_EXT
I/O
MFP13
Timer1 event counter input/toggle output pin.
CLKO
O
MFP14
Clock Out
118 PB.13
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH13
A
MFP1
EADC0 channel 13 analog input.
DAC1_OUT
A
MFP1
DAC1 channel analog output.
ACMP0_P3
A
MFP1
Analog comparator 0 positive input 3 pin.
ACMP1_P3
A
MFP1
Analog comparator 1 positive input 3 pin.
EBI_AD14
I/O
MFP2
EBI address/data bus bit 14.
SC1_DAT
I/O
MFP3
Smart Card 1 data pin.
SPI0_MISO
I/O
MFP4
SPI0 MISO (Master In, Slave Out) pin.
USCI0_DAT0
I/O
MFP5
USCI0 data 0 pin.
ETM_TRACE_DATA0
54
117 PB.14
EADC0_CH14
2
ETM_TRACE_DATA1
55
May 08, 2020
Page 123 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
64 128 Pin Name
Pin Pin
Type
MFP
Description
UART0_TXD
O
MFP6
UART0 data transmitter output pin.
UART3_nRTS
O
MFP7
UART3 request to Send output pin.
I C2_SCL
I/O
MFP8
I2C2 clock pin.
EPWM1_CH2
I/O
MFP11
EPWM1 channel 2 output/capture input.
I
MFP12
ETM receiver Trace Data 2 input pin
I/O
MFP13
Timer2 event counter input/toggle output pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH12
A
MFP1
EADC0 channel 12 analog input.
DAC0_OUT
A
MFP1
DAC0 channel analog output.
ACMP0_P2
A
MFP1
Analog comparator 0 positive input 2 pin.
ACMP1_P2
A
MFP1
Analog comparator 1 positive input 2 pin.
EBI_AD15
I/O
MFP2
EBI address/data bus bit 15.
SC1_CLK
O
MFP3
Smart Card 1 clock pin.
SPI0_MOSI
I/O
MFP4
SPI0 MOSI (Master Out, Slave In) pin.
USCI0_CLK
I/O
MFP5
USCI0 clock pin.
UART0_RXD
I
MFP6
UART0 data receiver input pin.
UART3_nCTS
I
MFP7
UART3 clear to Send input pin.
I2C2_SDA
I/O
MFP8
I2C2 data input/output pin.
SD0_nCD
I
MFP9
SD/SDIO0 card detect input pin
I/O
MFP11
EPWM1 channel 3 output/capture input.
I
MFP12
ETM receiver Trace Data 3 input pin
I/O
MFP13
Timer3 event counter input/toggle output pin.
2
ETM_TRACE_DATA2
TM2_EXT
56
119 PB.12
M480 SERIES DATASHEET
EPWM1_CH3
ETM_TRACE_DATA3
TM3_EXT
57
120 AVDD
P
MFP0
Power supply for internal analog circuit.
58
121 VREF
A
MFP0
ADC reference voltage input.
Note: This pin needs to be connected with a 1uF capacitor.
59
122 AVSS
P
MFP0
Ground pin for analog circuit.
60
123 PB.11
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH11
A
MFP1
EADC0 channel 11 analog input.
EBI_ADR16
O
MFP2
EBI address bus bit 16.
UART0_nCTS
I
MFP5
UART0 clear to Send input pin.
UART4_TXD
O
MFP6
UART4 data transmitter output pin.
I C1_SCL
I/O
MFP7
I2C1 clock pin.
CAN0_TXD
O
MFP8
CAN0 bus transmitter output.
SPI0_I2SMCLK
I/O
MFP9
SPI0 I2S master clock output pin
2
May 08, 2020
Page 124 of 523
Rev 3.00
M480
64 128 Pin Name
Pin Pin
MFP
BPWM1_CH0
I/O
MFP10
BPWM1 channel 0 output/capture input.
SPI3_CLK
I/O
MFP11
SPI3 serial clock pin.
I
MFP14
HSUSB external VBUS regulator status pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH10
A
MFP1
EADC0 channel 10 analog input.
EBI_ADR17
O
MFP2
EBI address bus bit 17.
USCI1_CTL0
I/O
MFP4
USCI1 control 0 pin.
UART0_nRTS
O
MFP5
UART0 request to Send output pin.
UART4_RXD
I
MFP6
UART4 data receiver input pin.
I/O
MFP7
I2C1 data input/output pin.
I
MFP8
CAN0 bus receiver input.
BPWM1_CH1
I/O
MFP10
BPWM1 channel 1 output/capture input.
SPI3_SS
I/O
MFP11
SPI3 slave select pin.
HSUSB_VBUS_EN
O
MFP14
HSUSB external VBUS regulator enable pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH9
A
MFP1
EADC0 channel 9 analog input.
EBI_ADR18
O
MFP2
EBI address bus bit 18.
USCI1_CTL1
I/O
MFP4
USCI1 control 1 pin.
UART0_TXD
O
MFP5
UART0 data transmitter output pin.
UART1_nCTS
I
MFP6
UART1 clear to Send input pin.
I C1_SMBAL
O
MFP7
I2C1 SMBus SMBALTER pin
BPWM1_CH2
I/O
MFP10
BPWM1 channel 2 output/capture input.
SPI3_MISO
I/O
MFP11
SPI3 MISO (Master In, Slave Out) pin.
I
MFP13
External interrupt 7 input pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH8
A
MFP1
EADC0 channel 8 analog input.
EBI_ADR19
O
MFP2
EBI address bus bit 19.
USCI1_CLK
I/O
MFP4
USCI1 clock pin.
UART0_RXD
I
MFP5
UART0 data receiver input pin.
UART1_nRTS
O
MFP6
UART1 request to Send output pin.
I2C1_SMBSUS
O
MFP7
I2C1 SMBus SMBSUS pin (PMBus CONTROL pin)
BPWM1_CH3
I/O
MFP10
BPWM1 channel 3 output/capture input.
SPI3_MOSI
I/O
MFP11
SPI3 MOSI (Master Out, Slave In) pin.
I
MFP13
External interrupt 6 input pin.
HSUSB_VBUS_ST
61
124 PB.10
2
I C1_SDA
CAN0_RXD
62
125 PB.9
2
INT7
63
126 PB.8
INT6
May 08, 2020
Description
Page 125 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
64 128 Pin Name
Pin Pin
64
Type
MFP
Description
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH7
A
MFP1
EADC0 channel 7 analog input.
EBI_nWRL
O
MFP2
EBI low byte write enable output pin.
USCI1_DAT0
I/O
MFP4
USCI1 data 0 pin.
CAN1_TXD
O
MFP5
CAN1 bus transmitter output.
UART1_TXD
O
MFP6
UART1 data transmitter output pin.
SD1_CMD
I/O
MFP7
SD/SDIO1 command/response pin
EBI_nCS0
O
MFP8
EBI chip select 0 output pin.
BPWM1_CH4
I/O
MFP10
BPWM1 channel 4 output/capture input.
I
MFP11
EPWM1 Brake 0 input pin.
I/O
MFP12
EPWM1 channel 4 output/capture input.
INT5
I
MFP13
External interrupt 5 input pin.
USB_VBUS_ST
I
MFP14
USB external VBUS regulator status pin.
ACMP0_O
O
MFP15
Analog comparator 0 output pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH6
A
MFP1
EADC0 channel 6 analog input.
EBI_nWRH
O
MFP2
EBI high byte write enable output pin
USCI1_DAT1
I/O
MFP4
USCI1 data 1 pin.
CAN1_RXD
I
MFP5
CAN1 bus receiver input.
UART1_RXD
I
MFP6
UART1 data receiver input pin.
SD1_CLK
O
MFP7
SD/SDIO1 clock output pin
EBI_nCS1
O
MFP8
EBI chip select 1 output pin.
BPWM1_CH5
I/O
MFP10
BPWM1 channel 5 output/capture input.
I
MFP11
EPWM1 Brake 1 input pin.
I/O
MFP12
EPWM1 channel 5 output/capture input.
INT4
I
MFP13
External interrupt 4 input pin.
USB_VBUS_EN
O
MFP14
USB external VBUS regulator enable pin.
ACMP1_O
O
MFP15
Analog comparator 1 output pin.
127 PB.7
EPWM1_BRAKE0
EPWM1_CH4
1
128 PB.6
M480 SERIES DATASHEET
EPWM1_BRAKE1
EPWM1_CH5
May 08, 2020
Page 126 of 523
Rev 3.00
M480
4.2.4
M484 Series Pin Description
Note: PA.15 MFP can only be as USB_OTG_ID when enable full-Speed USB.
64 64 Pin 128 Pin Name
Pin 2 USB Pin
2
3
3
4
1
2
3
MFP
Description
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH5
A
MFP1
EADC0 channel 5 analog input.
ACMP1_N
A
MFP1
Analog comparator 1 negative input pin.
EBI_ADR0
O
MFP2
EBI address bus bit 0.
SD0_DAT3
I/O
MFP3
SD/SDIO0 data line bit 3.
SPI1_MISO
I/O
MFP5
SPI1 MISO (Master In, Slave Out) pin.
I2C0_SCL
I/O
MFP6
I2C0 clock pin.
UART5_TXD
O
MFP7
UART5 data transmitter output pin.
USCI1_CTL0
I/O
MFP8
USCI1 control 0 pin.
SC0_CLK
O
MFP9
Smart Card 0 clock pin.
I2S0_BCLK
O
MFP10
I2S0 bit clock output pin.
EPWM0_CH0
I/O
MFP11
EPWM0 channel 0 output/capture input.
TM0
I/O
MFP14
Timer0 event counter input/toggle output pin.
INT0
I
MFP15
External interrupt 0 input pin.
PB.4
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH4
A
MFP1
EADC0 channel 4 analog input.
ACMP1_P1
A
MFP1
Analog comparator 1 positive input 1 pin.
EBI_ADR1
O
MFP2
EBI address bus bit 1.
SD0_DAT2
I/O
MFP3
SD/SDIO0 data line bit 2.
SPI1_MOSI
I/O
MFP5
SPI1 MOSI (Master Out, Slave In) pin.
I2C0_SDA
I/O
MFP6
I2C0 data input/output pin.
UART5_RXD
I
MFP7
UART5 data receiver input pin.
USCI1_CTL1
I/O
MFP8
USCI1 control 1 pin.
SC0_DAT
I/O
MFP9
Smart Card 0 data pin.
I2S0_MCLK
O
MFP10
I2S0 master clock output pin.
EPWM0_CH1
I/O
MFP11
EPWM0 channel 1 output/capture input.
TM1
I/O
MFP14
Timer1 event counter input/toggle output pin.
INT1
I
MFP15
External interrupt 1 input pin.
PB.3
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH3
A
MFP1
EADC0 channel 3 analog input.
ACMP0_N
A
MFP1
Analog comparator 0 negative input pin.
EBI_ADR2
O
MFP2
EBI address bus bit 2.
PB.5
May 08, 2020
Page 127 of 523
M480 SERIES DATASHEET
4
2
Type
Rev 3.00
M480
64 64 Pin 128 Pin Name
Pin 2 USB Pin
5
5
4
M480 SERIES DATASHEET
5
Type
MFP
Description
SD0_DAT1
I/O
MFP3
SD/SDIO0 data line bit 1.
SPI1_CLK
I/O
MFP5
SPI1 serial clock pin.
UART1_TXD
O
MFP6
UART1 data transmitter output pin.
UART5_nRTS
O
MFP7
UART5 request to Send output pin.
USCI1_DAT1
I/O
MFP8
USCI1 data 1 pin.
SC0_RST
O
MFP9
Smart Card 0 reset pin.
I2S0_DI
I
MFP10
I2S0 data input pin.
EPWM0_CH2
I/O
MFP11
EPWM0 channel 2 output/capture input.
TM2
I/O
MFP14
Timer2 event counter input/toggle output pin.
INT2
I
MFP15
External interrupt 2 input pin.
PB.2
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH2
A
MFP1
EADC0 channel 2 analog input.
ACMP0_P1
A
MFP1
Analog comparator 0 positive input 1 pin.
OPA0_O
A
MFP1
Operational amplifier 0 output pin.
EBI_ADR3
O
MFP2
EBI address bus bit 3.
SD0_DAT0
I/O
MFP3
SD/SDIO0 data line bit 0.
SPI1_SS
I/O
MFP5
SPI1 slave select pin.
UART1_RXD
I
MFP6
UART1 data receiver input pin.
UART5_nCTS
I
MFP7
UART5 clear to Send input pin.
USCI1_DAT0
I/O
MFP8
USCI1 data 0 pin.
SC0_PWR
O
MFP9
Smart Card 0 power pin.
I2S0_DO
O
MFP10
I2S0 data output pin.
EPWM0_CH3
I/O
MFP11
EPWM0 channel 3 output/capture input.
TM3
I/O
MFP14
Timer3 event counter input/toggle output pin.
INT3
I
MFP15
External interrupt 3 input pin.
PC.12
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR4
O
MFP2
EBI address bus bit 4.
UART0_TXD
O
MFP3
UART0 data transmitter output pin.
I2C0_SCL
I/O
MFP4
I2C0 clock pin.
SPI3_MISO
I/O
MFP6
SPI3 MISO (Master In, Slave Out) pin.
SC0_nCD
I
MFP9
Smart Card 0 card detect pin.
ECAP1_IC2
I
MFP11
Enhanced capture unit 1 input 2 pin.
EPWM1_CH0
I/O
MFP12
EPWM1 channel 0 output/capture input.
ACMP0_O
O
MFP14
Analog comparator 0 output pin.
May 08, 2020
Page 128 of 523
Rev 3.00
M480
64 64 Pin 128 Pin Name
Pin 2 USB Pin
6
7
8
6
9
MFP
Description
PC.11
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR5
O
MFP2
EBI address bus bit 5.
UART0_RXD
I
MFP3
UART0 data receiver input pin.
I2C0_SDA
I/O
MFP4
I2C0 data input/output pin.
SPI3_MOSI
I/O
MFP6
SPI3 MOSI (Master Out, Slave In) pin.
ECAP1_IC1
I
MFP11
Enhanced capture unit 1 input 1 pin.
EPWM1_CH1
I/O
MFP12
EPWM1 channel 1 output/capture input.
ACMP1_O
O
MFP14
Analog comparator 1 output pin.
PC.10
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR6
O
MFP2
EBI address bus bit 6.
SPI3_CLK
I/O
MFP6
SPI3 serial clock pin.
UART3_TXD
O
MFP7
UART3 data transmitter output pin.
ECAP1_IC0
I
MFP11
Enhanced capture unit 1 input 0 pin.
EPWM1_CH2
I/O
MFP12
EPWM1 channel 2 output/capture input.
PC.9
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR7
O
MFP2
EBI address bus bit 7.
SPI3_SS
I/O
MFP6
SPI3 slave select pin.
UART3_RXD
I
MFP7
UART3 data receiver input pin.
EPWM1_CH3
I/O
MFP12
EPWM1 channel 3 output/capture input.
PB.1
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH1
A
MFP1
EADC0 channel 1 analog input.
OPA0_N
A
MFP1
Operational amplifier 0 negative input pin.
EBI_ADR8
O
MFP2
EBI address bus bit 8.
SD0_CLK
O
MFP3
SD/SDIO0 clock output pin
SPI1_I2SMCLK
I/O
MFP5
SPI1 I2S master clock output pin
SPI3_I2SMCLK
I/O
MFP6
SPI3 I2S master clock output pin
UART2_TXD
O
MFP7
UART2 data transmitter output pin.
USCI1_CLK
I/O
MFP8
USCI1 clock pin.
I2C1_SCL
I/O
MFP9
I2C1 clock pin.
I2S0_LRCK
O
MFP10
I2S0 left right channel clock output pin.
EPWM0_CH4
I/O
MFP11
EPWM0 channel 4 output/capture input.
EPWM1_CH4
I/O
MFP12
EPWM1 channel 4 output/capture input.
I
MFP13
EPWM0 Brake 0 input pin.
I/O
MFP0
General purpose digital I/O pin.
EPWM0_BRAKE0
7
7
10 PB.0
May 08, 2020
Page 129 of 523
M480 SERIES DATASHEET
6
Type
Rev 3.00
M480
64 64 Pin 128 Pin Name
Pin 2 USB Pin
Type
MFP
Description
EADC0_CH0
A
MFP1
EADC0 channel 0 analog input.
OPA0_P
A
MFP1
Operational amplifier 0 positive input pin.
EBI_ADR9
O
MFP2
EBI address bus bit 9.
SD0_CMD
I/O
MFP3
SD/SDIO0 command/response pin
I
MFP7
UART2 data receiver input pin.
SPI0_I2SMCLK
I/O
MFP8
SPI0 I2S master clock output pin
I2C1_SDA
I/O
MFP9
I2C1 data input/output pin.
EPWM0_CH5
I/O
MFP11
EPWM0 channel 5 output/capture input.
EPWM1_CH5
I/O
MFP12
EPWM1 channel 5 output/capture input.
I
MFP13
EPWM0 Brake 1 input pin.
11 VSS
P
MFP0
Ground pin for digital circuit.
12 VDD
P
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
I/O
MFP0
General purpose digital I/O pin.
ACMP0_P0
A
MFP1
Analog comparator 0 positive input 0 pin.
EBI_nRD
O
MFP2
EBI read enable output pin.
SC2_PWR
O
MFP3
Smart Card 2 power pin.
SPI2_SS
I/O
MFP4
SPI2 slave select pin.
SD1_DAT3
I/O
MFP5
SD/SDIO1 data line bit 3.
USCI0_CLK
I/O
MFP6
USCI0 clock pin.
I2C2_SCL
I/O
MFP7
I2C2 clock pin.
BPWM0_CH0
I/O
MFP9
BPWM0 channel 0 output/capture input.
EPWM0_SYNC_OUT
O
MFP10
EPWM0 counter synchronous trigger output pin.
TM0_EXT
I/O
MFP13
Timer0 external capture input/toggle output pin.
DAC1_ST
I
MFP14
DAC1 external trigger input.
I/O
MFP0
General purpose digital I/O pin.
ACMP1_P0
A
MFP1
Analog comparator 1 positive input 0 pin.
OPA1_O
A
MFP1
Operational amplifier 1 output pin.
EBI_nWR
O
MFP2
EBI write enable output pin.
SC2_RST
O
MFP3
Smart Card 2 reset pin.
SPI2_CLK
I/O
MFP4
SPI2 serial clock pin.
SD1_DAT2
I/O
MFP5
SD/SDIO1 data line bit 2.
USCI0_DAT0
I/O
MFP6
USCI0 data 0 pin.
I2C2_SDA
I/O
MFP7
I2C2 data input/output pin.
UART2_RXD
EPWM0_BRAKE1
8
M480 SERIES DATASHEET
9
8
9
13 PA.11
14 PA.10
May 08, 2020
Page 130 of 523
Rev 3.00
M480
64 64 Pin 128 Pin Name
Pin 2 USB Pin
10
10
MFP
Description
BPWM0_CH1
I/O
MFP9
BPWM0 channel 1 output/capture input.
QEI1_INDEX
I
MFP10
Quadrature encoder 1 index input
ECAP0_IC0
I
MFP11
Enhanced capture unit 0 input 0 pin.
TM1_EXT
I/O
MFP13
Timer1 external capture input/toggle output pin.
DAC0_ST
I
MFP14
DAC0 external trigger input.
I/O
MFP0
General purpose digital I/O pin.
OPA1_N
A
MFP1
Operational amplifier 1 negative input pin.
EBI_MCLK
O
MFP2
EBI external clock output pin.
SC2_DAT
I/O
MFP3
Smart Card 2 data pin.
SPI2_MISO
I/O
MFP4
SPI2 MISO (Master In, Slave Out) pin.
SD1_DAT1
I/O
MFP5
SD/SDIO1 data line bit 1.
USCI0_DAT1
I/O
MFP6
USCI0 data 1 pin.
UART1_TXD
O
MFP7
UART1 data transmitter output pin.
BPWM0_CH2
I/O
MFP9
BPWM0 channel 2 output/capture input.
QEI1_A
I
MFP10
Quadrature encoder 1 phase A input
ECAP0_IC1
I
MFP11
Enhanced capture unit 0 input 1 pin.
I/O
MFP13
Timer2 external capture input/toggle output pin.
I/O
MFP0
General purpose digital I/O pin.
OPA1_P
A
MFP1
Operational amplifier 1 positive input pin.
EBI_ALE
O
MFP2
EBI address latch enable output pin.
SC2_CLK
O
MFP3
Smart Card 2 clock pin.
SPI2_MOSI
I/O
MFP4
SPI2 MOSI (Master Out, Slave In) pin.
SD1_DAT0
I/O
MFP5
SD/SDIO1 data line bit 0.
USCI0_CTL1
I/O
MFP6
USCI0 control 1 pin.
UART1_RXD
I
MFP7
UART1 data receiver input pin.
BPWM0_CH3
I/O
MFP9
BPWM0 channel 3 output/capture input.
QEI1_B
I
MFP10
Quadrature encoder 1 phase B input
ECAP0_IC2
I
MFP11
Enhanced capture unit 0 input 2 pin.
I/O
MFP13
Timer3 external capture input/toggle output pin.
I
MFP15
External interrupt 4 input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR10
O
MFP2
EBI address bus bit 10.
SC2_nCD
I
MFP3
Smart Card 2 card detect pin.
I/O
MFP4
SPI2 I2S master clock output pin
15 PA.9
TM2_EXT
11
11
16 PA.8
TM3_EXT
INT4
17 PC.13
SPI2_I2SMCLK
May 08, 2020
Page 131 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
64 64 Pin 128 Pin Name
Pin 2 USB Pin
Type
MFP
Description
USCI0_CTL0
I/O
MFP6
USCI0 control 0 pin.
UART2_TXD
O
MFP7
UART2 data transmitter output pin.
BPWM0_CH4
I/O
MFP9
BPWM0 channel 4 output/capture input.
CLKO
O
MFP13
Clock Out
EADC0_ST
I
MFP14
EADC0 external trigger input.
I/O
MFP0
General purpose digital I/O pin.
OPA2_O
A
MFP1
Operational amplifier 2 output pin.
EBI_nCS0
O
MFP2
EBI chip select 0 output pin.
UART2_RXD
I
MFP7
UART2 data receiver input pin.
BPWM0_CH5
I/O
MFP9
BPWM0 channel 5 output/capture input.
QEI0_INDEX
I
MFP10
Quadrature encoder 0 index input
CLKO
O
MFP13
Clock Out
EADC0_ST
I
MFP14
EADC0 external trigger input.
INT5
I
MFP15
External interrupt 5 input pin.
I/O
MFP0
General purpose digital I/O pin.
OPA2_N
A
MFP1
Operational amplifier 2 negative input pin.
EBI_nCS1
O
MFP2
EBI chip select 1 output pin.
UART1_TXD
O
MFP3
UART1 data transmitter output pin.
QEI0_A
I
MFP10
Quadrature encoder 0 phase A input
INT6
I
MFP15
External interrupt 6 input pin.
I/O
MFP0
General purpose digital I/O pin.
OPA2_P
A
MFP1
Operational amplifier 2 positive input pin.
EBI_nCS2
O
MFP2
EBI chip select 2 output pin.
UART1_RXD
I
MFP3
UART1 data receiver input pin.
QEI0_B
I
MFP10
Quadrature encoder 0 phase B input
INT7
I
MFP15
External interrupt 7 input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR11
O
MFP2
EBI address bus bit 11.
SPI2_SS
I/O
MFP3
SPI2 slave select pin.
I2C0_SMBAL
O
MFP4
I2C0 SMBus SMBALTER pin
I2C1_SCL
I/O
MFP5
I2C1 clock pin.
TM0
I/O
MFP13
Timer0 event counter input/toggle output pin.
22 PG.3
I/O
MFP0
General purpose digital I/O pin.
O
MFP2
EBI address bus bit 12.
18 PD.12
19 PD.11
M480 SERIES DATASHEET
20 PD.10
21 PG.2
EBI_ADR12
May 08, 2020
Page 132 of 523
Rev 3.00
M480
64 64 Pin 128 Pin Name
Pin 2 USB Pin
MFP
Description
SPI2_CLK
I/O
MFP3
SPI2 serial clock pin.
I2C0_SMBSUS
O
MFP4
I2C0 SMBus SMBSUS pin (PMBus CONTROL pin)
I2C1_SDA
I/O
MFP5
I2C1 data input/output pin.
TM1
I/O
MFP13
Timer1 event counter input/toggle output pin.
23 PG.4
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR13
O
MFP2
EBI address bus bit 13.
SPI2_MISO
I/O
MFP3
SPI2 MISO (Master In, Slave Out) pin.
TM2
I/O
MFP13
Timer2 event counter input/toggle output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR14
O
MFP2
EBI address bus bit 14.
SPI2_MOSI
I/O
MFP3
SPI2 MOSI (Master Out, Slave In) pin.
TAMPER5
I/O
MFP10
TAMPER detector loop pin 5.
TM3
I/O
MFP13
Timer3 event counter input/toggle output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR15
O
MFP2
EBI address bus bit 15.
SC0_nCD
I
MFP3
Smart Card 0 card detect pin.
I2S0_BCLK
O
MFP4
I2S0 bit clock output pin.
SPI0_I2SMCLK
I/O
MFP5
SPI0 I2S master clock output pin
TAMPER4
I/O
MFP10
TAMPER detector loop pin 4.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR16
O
MFP2
EBI address bus bit 16.
SC0_PWR
O
MFP3
Smart Card 0 power pin.
I2S0_MCLK
O
MFP4
I2S0 master clock output pin.
SPI0_SS
I/O
MFP5
SPI0 slave select pin.
TAMPER3
I/O
MFP10
TAMPER detector loop pin 3.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR17
O
MFP2
EBI address bus bit 17.
SC0_RST
O
MFP3
Smart Card 0 reset pin.
I2S0_DI
I
MFP4
I2S0 data input pin.
SPI0_CLK
I/O
MFP5
SPI0 serial clock pin.
TAMPER2
I/O
MFP10
TAMPER detector loop pin 2.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR18
O
MFP2
EBI address bus bit 18.
SC0_DAT
I/O
MFP3
Smart Card 0 data pin.
24 PF.11
25 PF.10
26 PF.9
27 PF.8
28 PF.7
May 08, 2020
Page 133 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
64 64 Pin 128 Pin Name
Pin 2 USB Pin
12
12
Type
MFP
Description
I2S0_DO
O
MFP4
I2S0 data output pin.
SPI0_MISO
I/O
MFP5
SPI0 MISO (Master In, Slave Out) pin.
UART4_TXD
O
MFP6
UART4 data transmitter output pin.
TAMPER1
I/O
MFP10
TAMPER detector loop pin 1.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR19
O
MFP2
EBI address bus bit 19.
SC0_CLK
O
MFP3
Smart Card 0 clock pin.
I2S0_LRCK
O
MFP4
I2S0 left right channel clock output pin.
SPI0_MOSI
I/O
MFP5
SPI0 MOSI (Master Out, Slave In) pin.
UART4_RXD
I
MFP6
UART4 data receiver input pin.
EBI_nCS0
O
MFP7
EBI chip select 0 output pin.
TAMPER0
I/O
MFP10
TAMPER detector loop pin 0.
29 PF.6
M480 SERIES DATASHEET
13
13
30 VDD
P
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
14
14
31 PF.5
I/O
MFP0
General purpose digital I/O pin.
UART2_RXD
I
MFP2
UART2 data receiver input pin.
UART2_nCTS
I
MFP4
UART2 clear to Send input pin.
BPWM0_CH4
I/O
MFP8
BPWM0 channel 4 output/capture input.
EPWM0_SYNC_OUT
O
MFP9
EPWM0 counter synchronous trigger output pin.
X32_IN
I
MFP10
External 32.768 kHz crystal input pin.
EADC0_ST
I
MFP11
EADC0 external trigger input.
I/O
MFP0
General purpose digital I/O pin.
UART2_TXD
O
MFP2
UART2 data transmitter output pin.
UART2_nRTS
O
MFP4
UART2 request to Send output pin.
BPWM0_CH5
I/O
MFP8
BPWM0 channel 5 output/capture input.
X32_OUT
O
MFP10
External 32.768 kHz crystal output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR3
O
MFP2
EBI address bus bit 3.
SPI1_MISO
I/O
MFP3
SPI1 MISO (Master In, Slave Out) pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR2
O
MFP2
EBI address bus bit 2.
SPI1_MOSI
I/O
MFP3
SPI1 MOSI (Master Out, Slave In) pin.
I/O
MFP0
General purpose digital I/O pin.
O
MFP2
EBI address bus bit 1.
15
15
32 PF.4
33 PH.4
34 PH.5
35 PH.6
EBI_ADR1
May 08, 2020
Page 134 of 523
Rev 3.00
M480
64 64 Pin 128 Pin Name
Pin 2 USB Pin
MFP
Description
I/O
MFP3
SPI1 serial clock pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR0
O
MFP2
EBI address bus bit 0.
SPI1_SS
I/O
MFP3
SPI1 slave select pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_nCS0
O
MFP2
EBI chip select 0 output pin.
UART0_TXD
O
MFP3
UART0 data transmitter output pin.
I2C0_SCL
I/O
MFP4
I2C0 clock pin.
I
MFP10
External 4~24 MHz (high speed) crystal input pin.
I/O
MFP11
BPWM1 channel 0 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_nCS1
O
MFP2
EBI chip select 1 output pin.
UART0_RXD
I
MFP3
UART0 data receiver input pin.
I2C0_SDA
I/O
MFP4
I2C0 data input/output pin.
QSPI0_CLK
I/O
MFP5
Quad SPI0 serial clock pin.
XT1_OUT
O
MFP10
External 4~24 MHz (high speed) crystal output pin.
BPWM1_CH1
I/O
MFP11
BPWM1 channel 1 output/capture input.
39 VSS
P
MFP0
Ground pin for digital circuit.
40 VDD
P
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
41 PE.8
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR10
O
MFP2
EBI address bus bit 10.
I2S0_BCLK
O
MFP4
I2S0 bit clock output pin.
SPI2_CLK
I/O
MFP5
SPI2 serial clock pin.
USCI1_CTL1
I/O
MFP6
USCI1 control 1 pin.
UART2_TXD
O
MFP7
UART2 data transmitter output pin.
EPWM0_CH0
I/O
MFP10
EPWM0 channel 0 output/capture input.
EPWM0_BRAKE0
I
MFP11
EPWM0 Brake 0 input pin.
ECAP0_IC0
I
MFP12
Enhanced capture unit 0 input 0 pin.
TRACE_CLK
O
MFP14
ETM Trace Clock output pin
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR11
O
MFP2
EBI address bus bit 11.
I2S0_MCLK
O
MFP4
I2S0 master clock output pin.
SPI2_MISO
I/O
MFP5
SPI2 MISO (Master In, Slave Out) pin.
SPI1_CLK
36 PH.7
16
16
37 PF.3
XT1_IN
BPWM1_CH0
17
17
38 PF.2
42 PE.9
May 08, 2020
Page 135 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
64 64 Pin 128 Pin Name
Pin 2 USB Pin
Type
MFP
Description
USCI1_CTL0
I/O
MFP6
USCI1 control 0 pin.
UART2_RXD
I
MFP7
UART2 data receiver input pin.
EPWM0_CH1
I/O
MFP10
EPWM0 channel 1 output/capture input.
EPWM0_BRAKE1
I
MFP11
EPWM0 Brake 1 input pin.
ECAP0_IC1
I
MFP12
Enhanced capture unit 0 input 1 pin.
TRACE_DATA0
O
MFP14
ETM Trace Data 0 output pin
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR12
O
MFP2
EBI address bus bit 12.
I2S0_DI
I
MFP4
I2S0 data input pin.
SPI2_MOSI
I/O
MFP5
SPI2 MOSI (Master Out, Slave In) pin.
USCI1_DAT0
I/O
MFP6
USCI1 data 0 pin.
UART3_TXD
O
MFP7
UART3 data transmitter output pin.
EPWM0_CH2
I/O
MFP10
EPWM0 channel 2 output/capture input.
EPWM1_BRAKE0
I
MFP11
EPWM1 Brake 0 input pin.
ECAP0_IC2
I
MFP12
Enhanced capture unit 0 input 2 pin.
TRACE_DATA1
O
MFP14
ETM Trace Data 1 output pin
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR13
O
MFP2
EBI address bus bit 13.
I2S0_DO
O
MFP4
I2S0 data output pin.
SPI2_SS
I/O
MFP5
SPI2 slave select pin.
USCI1_DAT1
I/O
MFP6
USCI1 data 1 pin.
UART3_RXD
I
MFP7
UART3 data receiver input pin.
UART1_nCTS
I
MFP8
UART1 clear to Send input pin.
EPWM0_CH3
I/O
MFP10
EPWM0 channel 3 output/capture input.
EPWM1_BRAKE1
I
MFP11
EPWM1 Brake 1 input pin.
ECAP1_IC2
I
MFP13
Enhanced capture unit 1 input 2 pin.
TRACE_DATA2
O
MFP14
ETM Trace Data 2 output pin
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR14
O
MFP2
EBI address bus bit 14.
I2S0_LRCK
O
MFP4
I2S0 left right channel clock output pin.
SPI2_I2SMCLK
I/O
MFP5
SPI2 I2S master clock output pin
USCI1_CLK
I/O
MFP6
USCI1 clock pin.
UART1_nRTS
O
MFP8
UART1 request to Send output pin.
EPWM0_CH4
I/O
MFP10
EPWM0 channel 4 output/capture input.
43 PE.10
44 PE.11
M480 SERIES DATASHEET
45 PE.12
May 08, 2020
Page 136 of 523
Rev 3.00
M480
64 64 Pin 128 Pin Name
Pin 2 USB Pin
MFP
ECAP1_IC1
I
MFP13
Enhanced capture unit 1 input 1 pin.
TRACE_DATA3
O
MFP14
ETM Trace Data 3 output pin
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR15
O
MFP2
EBI address bus bit 15.
I2C0_SCL
I/O
MFP4
I2C0 clock pin.
UART4_nRTS
O
MFP5
UART4 request to Send output pin.
UART1_TXD
O
MFP8
UART1 data transmitter output pin.
EPWM0_CH5
I/O
MFP10
EPWM0 channel 5 output/capture input.
EPWM1_CH0
I/O
MFP11
EPWM1 channel 0 output/capture input.
BPWM1_CH5
I/O
MFP12
BPWM1 channel 5 output/capture input.
I
MFP13
Enhanced capture unit 1 input 0 pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR16
O
MFP2
EBI address bus bit 16.
I2C0_SDA
I/O
MFP4
I2C0 data input/output pin.
UART4_nCTS
I
MFP5
UART4 clear to Send input pin.
UART1_RXD
I
MFP8
UART1 data receiver input pin.
EPWM1_CH1
I/O
MFP11
EPWM1 channel 1 output/capture input.
BPWM1_CH4
I/O
MFP12
BPWM1 channel 4 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD9
I/O
MFP2
EBI address/data bus bit 9.
SPI1_MISO
I/O
MFP4
SPI1 MISO (Master In, Slave Out) pin.
UART4_TXD
O
MFP5
UART4 data transmitter output pin.
SC2_PWR
O
MFP6
Smart Card 2 power pin.
UART0_nCTS
I
MFP7
UART0 clear to Send input pin.
I2C1_SMBAL
O
MFP8
I2C1 SMBus SMBALTER pin
EPWM1_CH2
I/O
MFP11
EPWM1 channel 2 output/capture input.
BPWM1_CH0
I/O
MFP12
BPWM1 channel 0 output/capture input.
TM0
I/O
MFP14
Timer0 event counter input/toggle output pin.
INT3
I
MFP15
External interrupt 3 input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD8
I/O
MFP2
EBI address/data bus bit 8.
SPI1_MOSI
I/O
MFP4
SPI1 MOSI (Master Out, Slave In) pin.
UART4_RXD
I
MFP5
UART4 data receiver input pin.
SC2_RST
O
MFP6
Smart Card 2 reset pin.
46 PE.13
ECAP1_IC0
47 PC.8
18
19
18
19
48 PC.7
49 PC.6
May 08, 2020
Description
Page 137 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
64 64 Pin 128 Pin Name
Pin 2 USB Pin
20
21
20
21
M480 SERIES DATASHEET
Type
MFP
Description
UART0_nRTS
O
MFP7
UART0 request to Send output pin.
I2C1_SMBSUS
O
MFP8
I2C1 SMBus SMBSUS pin (PMBus CONTROL pin)
EPWM1_CH3
I/O
MFP11
EPWM1 channel 3 output/capture input.
BPWM1_CH1
I/O
MFP12
BPWM1 channel 1 output/capture input.
TM1
I/O
MFP14
Timer1 event counter input/toggle output pin.
INT2
I
MFP15
External interrupt 2 input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD7
I/O
MFP2
EBI address/data bus bit 7.
SPI1_CLK
I/O
MFP4
SPI1 serial clock pin.
SC2_DAT
I/O
MFP6
Smart Card 2 data pin.
UART0_TXD
O
MFP7
UART0 data transmitter output pin.
I2C1_SCL
I/O
MFP8
I2C1 clock pin.
EPWM1_CH4
I/O
MFP11
EPWM1 channel 4 output/capture input.
BPWM1_CH2
I/O
MFP12
BPWM1 channel 2 output/capture input.
ACMP0_WLAT
I
MFP13
Analog comparator 0 window latch input pin
TM2
I/O
MFP14
Timer2 event counter input/toggle output pin.
INT1
I
MFP15
External interrupt 1 input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD6
I/O
MFP2
EBI address/data bus bit 6.
SPI1_SS
I/O
MFP4
SPI1 slave select pin.
SD1_nCD
I
MFP5
SD/SDIO1 card detect input pin
SC2_CLK
O
MFP6
Smart Card 2 clock pin.
UART0_RXD
I
MFP7
UART0 data receiver input pin.
I2C1_SDA
I/O
MFP8
I2C1 data input/output pin.
EPWM1_CH5
I/O
MFP11
EPWM1 channel 5 output/capture input.
BPWM1_CH3
I/O
MFP12
BPWM1 channel 3 output/capture input.
ACMP1_WLAT
I
MFP13
Analog comparator 1 window latch input pin
TM3
I/O
MFP14
Timer3 event counter input/toggle output pin.
INT0
I
MFP15
External interrupt 0 input pin.
50 PA.7
51 PA.6
22
22
52 VSS
P
MFP0
Ground pin for digital circuit.
23
23
53 VDD
P
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
24
24
54 LDO_CAP
A
MFP0
LDO output pin.
Note: This pin needs to be connected with an external
capacitor.
May 08, 2020
Page 138 of 523
Rev 3.00
M480
64 64 Pin 128 Pin Name
Pin 2 USB Pin
25
26
25
26
MFP
Description
I/O
MFP0
General purpose digital I/O pin.
SPIM_D2
I/O
MFP2
SPIM data 2 pin for Quad Mode I/O.
QSPI0_MISO1
I/O
MFP3
Quad SPI0 MISO1 (Master In, Slave Out) pin.
SPI1_I2SMCLK
I/O
MFP4
SPI1 I2S master clock output pin
SD1_CMD
I/O
MFP5
SD/SDIO1 command/response pin
SC2_nCD
I
MFP6
Smart Card 2 card detect pin.
UART0_nCTS
I
MFP7
UART0 clear to Send input pin.
UART5_TXD
O
MFP8
UART5 data transmitter output pin.
I2C0_SCL
I/O
MFP9
I2C0 clock pin.
BPWM0_CH5
I/O
MFP12
BPWM0 channel 5 output/capture input.
EPWM0_CH0
I/O
MFP13
EPWM0 channel 0 output/capture input.
QEI0_INDEX
I
MFP14
Quadrature encoder 0 index input
I/O
MFP0
General purpose digital I/O pin.
SPIM_D3
I/O
MFP2
SPIM data 3 pin for Quad Mode I/O.
QSPI0_MOSI1
I/O
MFP3
Quad SPI0 MOSI1 (Master Out, Slave In) pin.
SPI0_I2SMCLK
I/O
MFP4
SPI0 I2S master clock output pin
SD1_CLK
O
MFP5
SD/SDIO1 clock output pin
SC0_nCD
I
MFP6
Smart Card 0 card detect pin.
UART0_nRTS
O
MFP7
UART0 request to Send output pin.
UART5_RXD
I
MFP8
UART5 data receiver input pin.
I2C0_SDA
I/O
MFP9
I2C0 data input/output pin.
BPWM0_CH4
I/O
MFP12
BPWM0 channel 4 output/capture input.
EPWM0_CH1
I/O
MFP13
EPWM0 channel 1 output/capture input.
I
MFP14
Quadrature encoder 0 phase A input
I/O
MFP0
General purpose digital I/O pin.
SPIM_SS
I/O
MFP2
SPIM slave select pin.
QSPI0_SS
I/O
MFP3
Quad SPI0 slave select pin.
SPI0_SS
I/O
MFP4
SPI0 slave select pin.
SD1_DAT3
I/O
MFP5
SD/SDIO1 data line bit 3.
SC0_PWR
O
MFP6
Smart Card 0 power pin.
UART4_TXD
O
MFP7
UART4 data transmitter output pin.
UART1_TXD
O
MFP8
UART1 data transmitter output pin.
I2C1_SCL
I/O
MFP9
I2C1 clock pin.
BPWM0_CH3
I/O
MFP12
BPWM0 channel 3 output/capture input.
55 PA.5
56 PA.4
QEI0_A
27
27
57 PA.3
May 08, 2020
Page 139 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
64 64 Pin 128 Pin Name
Pin 2 USB Pin
Type
MFP
I/O
MFP13
EPWM0 channel 2 output/capture input.
I
MFP14
Quadrature encoder 0 phase B input
I/O
MFP0
General purpose digital I/O pin.
SPIM_CLK
I/O
MFP2
SPIM serial clock pin.
QSPI0_CLK
I/O
MFP3
Quad SPI0 serial clock pin.
SPI0_CLK
I/O
MFP4
SPI0 serial clock pin.
SD1_DAT2
I/O
MFP5
SD/SDIO1 data line bit 2.
SC0_RST
O
MFP6
Smart Card 0 reset pin.
UART4_RXD
I
MFP7
UART4 data receiver input pin.
UART1_RXD
I
MFP8
UART1 data receiver input pin.
I2C1_SDA
I/O
MFP9
I2C1 data input/output pin.
BPWM0_CH2
I/O
MFP12
BPWM0 channel 2 output/capture input.
EPWM0_CH3
I/O
MFP13
EPWM0 channel 3 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
SPIM_MISO
I/O
MFP2
SPIM MISO (Master In, Slave Out) pin.
QSPI0_MISO0
I/O
MFP3
Quad SPI0 MISO0 (Master In, Slave Out) pin.
SPI0_MISO
I/O
MFP4
SPI0 MISO (Master In, Slave Out) pin.
SD1_DAT1
I/O
MFP5
SD/SDIO1 data line bit 1.
SC0_DAT
I/O
MFP6
Smart Card 0 data pin.
UART0_TXD
O
MFP7
UART0 data transmitter output pin.
UART1_nCTS
I
MFP8
UART1 clear to Send input pin.
I2C2_SCL
I/O
MFP9
I2C2 clock pin.
BPWM0_CH1
I/O
MFP12
BPWM0 channel 1 output/capture input.
EPWM0_CH4
I/O
MFP13
EPWM0 channel 4 output/capture input.
I
MFP15
DAC1 external trigger input.
I/O
MFP0
General purpose digital I/O pin.
SPIM_MOSI
I/O
MFP2
SPIM MOSI (Master Out, Slave In) pin.
QSPI0_MOSI0
I/O
MFP3
Quad SPI0 MOSI0 (Master Out, Slave In) pin.
SPI0_MOSI
I/O
MFP4
SPI0 MOSI (Master Out, Slave In) pin.
SD1_DAT0
I/O
MFP5
SD/SDIO1 data line bit 0.
SC0_CLK
O
MFP6
Smart Card 0 clock pin.
UART0_RXD
I
MFP7
UART0 data receiver input pin.
UART1_nRTS
O
MFP8
UART1 request to Send output pin.
I2C2_SDA
I/O
MFP9
I2C2 data input/output pin.
EPWM0_CH2
QEI0_B
28
29
28
29
58 PA.2
59 PA.1
M480 SERIES DATASHEET
DAC1_ST
30
30
60 PA.0
May 08, 2020
Description
Page 140 of 523
Rev 3.00
M480
64 64 Pin 128 Pin Name
Pin 2 USB Pin
Type
MFP
BPWM0_CH0
I/O
MFP12
BPWM0 channel 0 output/capture input.
EPWM0_CH5
I/O
MFP13
EPWM0 channel 5 output/capture input.
I
MFP15
DAC0 external trigger input.
61 VDDIO
P
MFP0
Power supply for PA.0~PA.5.
62 PE.14
I/O
MFP0
General purpose digital I/O pin.
EBI_AD8
I/O
MFP2
EBI address/data bus bit 8.
UART2_TXD
O
MFP3
UART2 data transmitter output pin.
SD1_nCD
I
MFP5
SD/SDIO1 card detect input pin
I/O
MFP0
General purpose digital I/O pin.
I/O
MFP2
EBI address/data bus bit 9.
I
MFP3
UART2 data receiver input pin.
I
MFP0
External reset input: active LOW, with an internal pull-up.
Set this pin low reset to initial state.
DAC0_ST
31
31
63 PE.15
EBI_AD9
UART2_RXD
32
32
64 nRESET
Description
Note: It is recommended to use 10 kΩ pull-up resistor and
10 uF capacitor on nRESET pin.
33
33
65 PF.0
I/O
MFP0
General purpose digital I/O pin.
UART1_TXD
O
MFP2
UART1 data transmitter output pin.
I2C1_SCL
I/O
MFP3
I2C1 clock pin.
BPWM1_CH0
I/O
MFP12
BPWM1 channel 0 output/capture input.
ICE_DAT
O
MFP14
Serial wired debugger data pin.
34
34
66 PF.1
I/O
MFP0
General purpose digital I/O pin.
I
MFP2
UART1 data receiver input pin.
I2C1_SDA
I/O
MFP3
I2C1 data input/output pin.
BPWM1_CH1
I/O
MFP12
BPWM1 channel 1 output/capture input.
I
MFP14
Serial wired debugger clock pin.
UART1_RXD
ICE_CLK
Note: It is recommended to use 100 kΩ pull-up resistor on
ICE_CLK pin.
67 PD.9
I/O
MFP0
General purpose digital I/O pin.
EBI_AD7
I/O
MFP2
EBI address/data bus bit 7.
I2C2_SCL
I/O
MFP3
I2C2 clock pin.
I
MFP4
UART2 clear to Send input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD6
I/O
MFP2
EBI address/data bus bit 6.
I2C2_SDA
I/O
MFP3
I2C2 data input/output pin.
UART2_nRTS
O
MFP4
UART2 request to Send output pin.
UART2_nCTS
68 PD.8
May 08, 2020
Page 141 of 523
Rev 3.00
M480 SERIES DATASHEET
Note: It is recommended to use 100 kΩ pull-up resistor on
ICE_DAT pin.
M480
64 64 Pin 128 Pin Name
Pin 2 USB Pin
35
36
Type
MFP
Description
I/O
MFP0
General purpose digital I/O pin.
EBI_AD5
I/O
MFP2
EBI address/data bus bit 5.
SPIM_D2
I/O
MFP3
SPIM data 2 pin for Quad Mode I/O.
QSPI0_MISO1
I/O
MFP4
Quad SPI0 MISO1 (Master In, Slave Out) pin.
UART2_TXD
O
MFP8
UART2 data transmitter output pin.
I2C1_SCL
I/O
MFP9
I2C1 clock pin.
UART4_TXD
O
MFP11
UART4 data transmitter output pin.
EPWM1_CH0
I/O
MFP12
EPWM1 channel 0 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD4
I/O
MFP2
EBI address/data bus bit 4.
SPIM_D3
I/O
MFP3
SPIM data 3 pin for Quad Mode I/O.
QSPI0_MOSI1
I/O
MFP4
Quad SPI0 MOSI1 (Master Out, Slave In) pin.
SC1_nCD
I
MFP5
Smart Card 1 card detect pin.
I2S0_BCLK
O
MFP6
I2S0 bit clock output pin.
SPI1_I2SMCLK
I/O
MFP7
SPI1 I2S master clock output pin
I
MFP8
UART2 data receiver input pin.
I/O
MFP9
I2C1 data input/output pin.
UART4_RXD
I
MFP11
UART4 data receiver input pin.
EPWM1_CH1
I/O
MFP12
EPWM1 channel 1 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD3
I/O
MFP2
EBI address/data bus bit 3.
SPIM_SS
I/O
MFP3
SPIM slave select pin.
QSPI0_SS
I/O
MFP4
Quad SPI0 slave select pin.
SC1_PWR
O
MFP5
Smart Card 1 power pin.
I2S0_MCLK
O
MFP6
I2S0 master clock output pin.
SPI1_MISO
I/O
MFP7
SPI1 MISO (Master In, Slave Out) pin.
UART2_nRTS
O
MFP8
UART2 request to Send output pin.
I2C0_SMBAL
O
MFP9
I2C0 SMBus SMBALTER pin
UART3_TXD
O
MFP11
UART3 data transmitter output pin.
EPWM1_CH2
I/O
MFP12
EPWM1 channel 2 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD2
I/O
MFP2
EBI address/data bus bit 2.
SPIM_CLK
I/O
MFP3
SPIM serial clock pin.
QSPI0_CLK
I/O
MFP4
Quad SPI0 serial clock pin.
69 PC.5
70 PC.4
UART2_RXD
I2C1_SDA
M480 SERIES DATASHEET
37
38
71 PC.3
72 PC.2
May 08, 2020
Page 142 of 523
Rev 3.00
M480
64 64 Pin 128 Pin Name
Pin 2 USB Pin
MFP
Description
SC1_RST
O
MFP5
Smart Card 1 reset pin.
I2S0_DI
I
MFP6
I2S0 data input pin.
I/O
MFP7
SPI1 MOSI (Master Out, Slave In) pin.
UART2_nCTS
I
MFP8
UART2 clear to Send input pin.
I2C0_SMBSUS
O
MFP9
I2C0 SMBus SMBSUS pin (PMBus CONTROL pin)
UART3_RXD
I
MFP11
UART3 data receiver input pin.
EPWM1_CH3
I/O
MFP12
EPWM1 channel 3 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD1
I/O
MFP2
EBI address/data bus bit 1.
SPIM_MISO
I/O
MFP3
SPIM MISO (Master In, Slave Out) pin.
QSPI0_MISO0
I/O
MFP4
Quad SPI0 MISO0 (Master In, Slave Out) pin.
SC1_DAT
I/O
MFP5
Smart Card 1 data pin.
I2S0_DO
O
MFP6
I2S0 data output pin.
SPI1_CLK
I/O
MFP7
SPI1 serial clock pin.
UART2_TXD
O
MFP8
UART2 data transmitter output pin.
I2C0_SCL
I/O
MFP9
I2C0 clock pin.
EPWM1_CH4
I/O
MFP12
EPWM1 channel 4 output/capture input.
ACMP0_O
O
MFP14
Analog comparator 0 output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD0
I/O
MFP2
EBI address/data bus bit 0.
SPIM_MOSI
I/O
MFP3
SPIM MOSI (Master Out, Slave In) pin.
QSPI0_MOSI0
I/O
MFP4
Quad SPI0 MOSI0 (Master Out, Slave In) pin.
SC1_CLK
O
MFP5
Smart Card 1 clock pin.
I2S0_LRCK
O
MFP6
I2S0 left right channel clock output pin.
SPI1_SS
I/O
MFP7
SPI1 slave select pin.
I
MFP8
UART2 data receiver input pin.
I2C0_SDA
I/O
MFP9
I2C0 data input/output pin.
EPWM1_CH5
I/O
MFP12
EPWM1 channel 5 output/capture input.
ACMP1_O
O
MFP14
Analog comparator 1 output pin.
75 VSS
P
MFP0
Ground pin for digital circuit.
76 VDD
P
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
I/O
MFP0
General purpose digital I/O pin.
I/O
MFP2
EBI address/data bus bit 0.
SPI1_MOSI
39
40
35
36
73 PC.1
74 PC.0
UART2_RXD
77 PG.9
EBI_AD0
May 08, 2020
Page 143 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
64 64 Pin 128 Pin Name
Pin 2 USB Pin
Type
MFP
Description
SD1_DAT3
I/O
MFP3
SD/SDIO1 data line bit 3.
SPIM_D2
I/O
MFP4
SPIM data 2 pin for Quad Mode I/O.
BPWM0_CH5
I/O
MFP12
BPWM0 channel 5 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD1
I/O
MFP2
EBI address/data bus bit 1.
SD1_DAT2
I/O
MFP3
SD/SDIO1 data line bit 2.
SPIM_D3
I/O
MFP4
SPIM data 3 pin for Quad Mode I/O.
BPWM0_CH4
I/O
MFP12
BPWM0 channel 4 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD2
I/O
MFP2
EBI address/data bus bit 2.
SD1_DAT1
I/O
MFP3
SD/SDIO1 data line bit 1.
SPIM_SS
I/O
MFP4
SPIM slave select pin.
BPWM0_CH3
I/O
MFP12
BPWM0 channel 3 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD3
I/O
MFP2
EBI address/data bus bit 3.
SD1_DAT0
I/O
MFP3
SD/SDIO1 data line bit 0.
SPIM_CLK
I/O
MFP4
SPIM serial clock pin.
BPWM0_CH2
I/O
MFP12
BPWM0 channel 2 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD4
I/O
MFP2
EBI address/data bus bit 4.
SD1_CMD
I/O
MFP3
SD/SDIO1 command/response pin
SPIM_MISO
I/O
MFP4
SPIM MISO (Master In, Slave Out) pin.
BPWM0_CH1
I/O
MFP12
BPWM0 channel 1 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD5
I/O
MFP2
EBI address/data bus bit 5.
SD1_CLK
O
MFP3
SD/SDIO1 clock output pin
SPIM_MOSI
I/O
MFP4
SPIM MOSI (Master Out, Slave In) pin.
BPWM0_CH0
I/O
MFP12
BPWM0 channel 0 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
SD1_nCD
I
MFP3
SD/SDIO1 card detect input pin
CLKO
O
MFP14
Clock Out
EADC0_ST
I
MFP15
EADC0 external trigger input.
I/O
MFP0
General purpose digital I/O pin.
I/O
MFP2
EBI address/data bus bit 10.
78 PG.10
79 PG.11
80 PG.12
81 PG.13
M480 SERIES DATASHEET
82 PG.14
83 PG.15
84 PD.13
EBI_AD10
May 08, 2020
Page 144 of 523
Rev 3.00
M480
64 64 Pin 128 Pin Name
Pin 2 USB Pin
MFP
Description
I
MFP3
SD/SDIO0 card detect input pin
SPI0_I2SMCLK
I/O
MFP4
SPI0 I2S master clock output pin
SPI1_I2SMCLK
I/O
MFP5
SPI1 I2S master clock output pin
I
MFP7
Smart Card 2 card detect pin.
I/O
MFP0
General purpose digital I/O pin.
I2S0_BCLK
O
MFP2
I2S0 bit clock output pin.
UART4_TXD
O
MFP3
UART4 data transmitter output pin.
I2C1_SCL
I/O
MFP4
I2C1 clock pin.
SPI2_SS
I/O
MFP5
SPI2 slave select pin.
SC2_PWR
O
MFP7
Smart Card 2 power pin.
BPWM1_CH2
I/O
MFP11
BPWM1 channel 2 output/capture input.
QEI1_INDEX
I
MFP12
Quadrature encoder 1 index input
USB_VBUS
P
MFP14
Power supply from USB host or HUB.
I/O
MFP0
General purpose digital I/O pin.
I2S0_MCLK
O
MFP2
I2S0 master clock output pin.
UART4_RXD
I
MFP3
UART4 data receiver input pin.
I2C1_SDA
I/O
MFP4
I2C1 data input/output pin.
SPI2_CLK
I/O
MFP5
SPI2 serial clock pin.
SC2_RST
O
MFP7
Smart Card 2 reset pin.
BPWM1_CH3
I/O
MFP11
BPWM1 channel 3 output/capture input.
QEI1_A
I
MFP12
Quadrature encoder 1 phase A input
USB_D-
A
MFP14
USB differential signal D-.
I/O
MFP0
General purpose digital I/O pin.
I2S0_DI
I
MFP2
I2S0 data input pin.
UART0_TXD
O
MFP3
UART0 data transmitter output pin.
SPI2_MISO
I/O
MFP5
SPI2 MISO (Master In, Slave Out) pin.
I2C2_SCL
I/O
MFP6
I2C2 clock pin.
SC2_DAT
I/O
MFP7
Smart Card 2 data pin.
BPWM1_CH4
I/O
MFP11
BPWM1 channel 4 output/capture input.
QEI1_B
I
MFP12
Quadrature encoder 1 phase B input
USB_D+
A
MFP14
USB differential signal D+.
I/O
MFP0
General purpose digital I/O pin.
I2S0_DO
O
MFP2
I2S0 data output pin.
UART0_RXD
I
MFP3
UART0 data receiver input pin.
SD0_nCD
SC2_nCD
37
38
39
40
85 PA.12
86 PA.13
87 PA.14
88 PA.15
May 08, 2020
Page 145 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
64 64 Pin 128 Pin Name
Pin 2 USB Pin
Type
MFP
Description
SPI2_MOSI
I/O
MFP5
SPI2 MOSI (Master Out, Slave In) pin.
I2C2_SDA
I/O
MFP6
I2C2 data input/output pin.
SC2_CLK
O
MFP7
Smart Card 2 clock pin.
BPWM1_CH5
I/O
MFP11
BPWM1 channel 5 output/capture input.
EPWM0_SYNC_IN
I
MFP12
EPWM0 counter synchronous trigger input pin.
USB_OTG_ID
I
MFP14
USB_ identification.
41
41
89 HSUSB_VRES
A
MFP0
HSUSB module reference resister
42
42
90 HSUSB_VDD33
P
MFP0
Power supply for HSUSB VDD33
43
43
91 HSUSB_VBUS
P
MFP0
HSUSB Power supply from USB host or HUB.
44
44
92 HSUSB_D-
A
MFP0
HSUSB differential signal D-.
45
45
93 HSUSB_VSS
P
MFP0
Ground pin for HSUSB.
46
46
94 HSUSB_D+
A
MFP0
HSUSB differential signal D+.
47
47
95 HSUSB_VDD12_CAP
A
MFP0
HSUSB Internal power regulator output 1.2V decoupling
pin.
Note: This pin needs to be connected with a 1uF capacitor.
48
48
96 HSUSB_ID
I
MFP0
HSUSB identification.
I/O
MFP0
General purpose digital I/O pin.
SD0_CMD
I/O
MFP3
SD/SDIO0 command/response pin
SPIM_D2
I/O
MFP4
SPIM data 2 pin for Quad Mode I/O.
UART5_TXD
O
MFP8
UART5 data transmitter output pin.
QEI1_INDEX
I
MFP11
Quadrature encoder 1 index input
EPWM0_CH0
I/O
MFP12
EPWM0 channel 0 output/capture input.
BPWM0_CH5
I/O
MFP13
BPWM0 channel 5 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
SD0_CLK
O
MFP3
SD/SDIO0 clock output pin
SPIM_D3
I/O
MFP4
SPIM data 3 pin for Quad Mode I/O.
SPI3_I2SMCLK
I/O
MFP5
SPI3 I2S master clock output pin
I
MFP6
Smart Card 0 card detect pin.
USCI0_CTL0
I/O
MFP7
USCI0 control 0 pin.
UART5_RXD
I
MFP8
UART5 data receiver input pin.
QEI1_A
I
MFP11
Quadrature encoder 1 phase A input
EPWM0_CH1
I/O
MFP12
EPWM0 channel 1 output/capture input.
BPWM0_CH4
I/O
MFP13
BPWM0 channel 4 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
O
MFP2
EBI read enable output pin.
97 PE.7
M480 SERIES DATASHEET
98 PE.6
SC0_nCD
99 PE.5
EBI_nRD
May 08, 2020
Page 146 of 523
Rev 3.00
M480
64 64 Pin 128 Pin Name
Pin 2 USB Pin
MFP
Description
SD0_DAT3
I/O
MFP3
SD/SDIO0 data line bit 3.
SPIM_SS
I/O
MFP4
SPIM slave select pin.
SPI3_SS
I/O
MFP5
SPI3 slave select pin.
SC0_PWR
O
MFP6
Smart Card 0 power pin.
USCI0_CTL1
I/O
MFP7
USCI0 control 1 pin.
I
MFP11
Quadrature encoder 1 phase B input
EPWM0_CH2
I/O
MFP12
EPWM0 channel 2 output/capture input.
BPWM0_CH3
I/O
MFP13
BPWM0 channel 3 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_nWR
O
MFP2
EBI write enable output pin.
SD0_DAT2
I/O
MFP3
SD/SDIO0 data line bit 2.
SPIM_CLK
I/O
MFP4
SPIM serial clock pin.
SPI3_CLK
I/O
MFP5
SPI3 serial clock pin.
SC0_RST
O
MFP6
Smart Card 0 reset pin.
USCI0_DAT1
I/O
MFP7
USCI0 data 1 pin.
QEI0_INDEX
I
MFP11
Quadrature encoder 0 index input
EPWM0_CH3
I/O
MFP12
EPWM0 channel 3 output/capture input.
BPWM0_CH2
I/O
MFP13
BPWM0 channel 2 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_MCLK
O
MFP2
EBI external clock output pin.
SD0_DAT1
I/O
MFP3
SD/SDIO0 data line bit 1.
SPIM_MISO
I/O
MFP4
SPIM MISO (Master In, Slave Out) pin.
SPI3_MISO
I/O
MFP5
SPI3 MISO (Master In, Slave Out) pin.
SC0_DAT
I/O
MFP6
Smart Card 0 data pin.
USCI0_DAT0
I/O
MFP7
USCI0 data 0 pin.
I
MFP11
Quadrature encoder 0 phase A input
EPWM0_CH4
I/O
MFP12
EPWM0 channel 4 output/capture input.
BPWM0_CH1
I/O
MFP13
BPWM0 channel 1 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_ALE
O
MFP2
EBI address latch enable output pin.
SD0_DAT0
I/O
MFP3
SD/SDIO0 data line bit 0.
SPIM_MOSI
I/O
MFP4
SPIM MOSI (Master Out, Slave In) pin.
SPI3_MOSI
I/O
MFP5
SPI3 MOSI (Master Out, Slave In) pin.
SC0_CLK
O
MFP6
Smart Card 0 clock pin.
QEI1_B
100 PE.4
101 PE.3
QEI0_A
102 PE.2
May 08, 2020
Page 147 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
64 64 Pin 128 Pin Name
Pin 2 USB Pin
Type
MFP
Description
I/O
MFP7
USCI0 clock pin.
I
MFP11
Quadrature encoder 0 phase B input
EPWM0_CH5
I/O
MFP12
EPWM0 channel 5 output/capture input.
BPWM0_CH0
I/O
MFP13
BPWM0 channel 0 output/capture input.
103 VSS
P
MFP0
Ground pin for digital circuit.
104 VDD
P
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
105 PE.1
I/O
MFP0
General purpose digital I/O pin.
EBI_AD10
I/O
MFP2
EBI address/data bus bit 10.
QSPI0_MISO0
I/O
MFP3
Quad SPI0 MISO0 (Master In, Slave Out) pin.
SC2_DAT
I/O
MFP4
Smart Card 2 data pin.
I2S0_BCLK
O
MFP5
I2S0 bit clock output pin.
SPI1_MISO
I/O
MFP6
SPI1 MISO (Master In, Slave Out) pin.
UART3_TXD
O
MFP7
UART3 data transmitter output pin.
I2C1_SCL
I/O
MFP8
I2C1 clock pin.
I
MFP9
UART4 clear to Send input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD11
I/O
MFP2
EBI address/data bus bit 11.
QSPI0_MOSI0
I/O
MFP3
Quad SPI0 MOSI0 (Master Out, Slave In) pin.
SC2_CLK
O
MFP4
Smart Card 2 clock pin.
I2S0_MCLK
O
MFP5
I2S0 master clock output pin.
SPI1_MOSI
I/O
MFP6
SPI1 MOSI (Master Out, Slave In) pin.
I
MFP7
UART3 data receiver input pin.
I2C1_SDA
I/O
MFP8
I2C1 data input/output pin.
UART4_nRTS
O
MFP9
UART4 request to Send output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD12
I/O
MFP2
EBI address/data bus bit 12.
QSPI0_CLK
I/O
MFP3
Quad SPI0 serial clock pin.
SC2_PWR
O
MFP4
Smart Card 2 power pin.
I2S0_DI
I
MFP5
I2S0 data input pin.
SPI1_CLK
I/O
MFP6
SPI1 serial clock pin.
UART3_nRTS
O
MFP7
UART3 request to Send output pin.
I2C1_SMBAL
O
MFP8
I2C1 SMBus SMBALTER pin
I2C2_SCL
I/O
MFP9
I2C2 clock pin.
USCI0_CLK
QEI0_B
UART4_nCTS
106 PE.0
M480 SERIES DATASHEET
UART3_RXD
107 PH.8
May 08, 2020
Page 148 of 523
Rev 3.00
M480
64 64 Pin 128 Pin Name
Pin 2 USB Pin
MFP
O
MFP10
UART1 data transmitter output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD13
I/O
MFP2
EBI address/data bus bit 13.
QSPI0_SS
I/O
MFP3
Quad SPI0 slave select pin.
SC2_RST
O
MFP4
Smart Card 2 reset pin.
I2S0_DO
O
MFP5
I2S0 data output pin.
SPI1_SS
I/O
MFP6
SPI1 slave select pin.
UART3_nCTS
I
MFP7
UART3 clear to Send input pin.
I2C1_SMBSUS
O
MFP8
I2C1 SMBus SMBSUS pin (PMBus CONTROL pin)
I2C2_SDA
I/O
MFP9
I2C2 data input/output pin.
I
MFP10
UART1 data receiver input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD14
I/O
MFP2
EBI address/data bus bit 14.
QSPI0_MISO1
I/O
MFP3
Quad SPI0 MISO1 (Master In, Slave Out) pin.
SC2_nCD
I
MFP4
Smart Card 2 card detect pin.
I2S0_LRCK
O
MFP5
I2S0 left right channel clock output pin.
SPI1_I2SMCLK
I/O
MFP6
SPI1 I2S master clock output pin
UART4_TXD
O
MFP7
UART4 data transmitter output pin.
UART0_TXD
O
MFP8
UART0 data transmitter output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD15
I/O
MFP2
EBI address/data bus bit 15.
QSPI0_MOSI1
I/O
MFP3
Quad SPI0 MOSI1 (Master Out, Slave In) pin.
UART4_RXD
I
MFP7
UART4 data receiver input pin.
UART0_RXD
I
MFP8
UART0 data receiver input pin.
EPWM0_CH5
I/O
MFP11
EPWM0 channel 5 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_nCS0
O
MFP2
EBI chip select 0 output pin.
SPI3_I2SMCLK
I/O
MFP3
SPI3 I2S master clock output pin
I
MFP4
Smart Card 1 card detect pin.
I/O
MFP11
EPWM0 channel 4 output/capture input.
UART1_TXD
108 PH.9
UART1_RXD
109 PH.10
110 PH.11
111 PD.14
SC1_nCD
EPWM0_CH4
Description
49
49
112 VSS
P
MFP0
Ground pin for digital circuit.
50
50
113 LDO_CAP
A
MFP0
LDO output pin.
M480 SERIES DATASHEET
Type
Note: This pin needs to be connected with an external
capacitor.
51
51
114 VDD
May 08, 2020
P
MFP0
Power supply for I/O ports and LDO source for internal
Page 149 of 523
Rev 3.00
M480
64 64 Pin 128 Pin Name
Pin 2 USB Pin
Type
MFP
Description
PLL and digital circuit.
52
52
115 PC.14
I/O
MFP0
General purpose digital I/O pin.
EBI_AD11
I/O
MFP2
EBI address/data bus bit 11.
SC1_nCD
I
MFP3
Smart Card 1 card detect pin.
SPI0_I2SMCLK
I/O
MFP4
SPI0 I2S master clock output pin
USCI0_CTL0
I/O
MFP5
USCI0 control 0 pin.
QSPI0_CLK
I/O
MFP6
Quad SPI0 serial clock pin.
I
MFP11
EPWM0 counter synchronous trigger input pin.
I/O
MFP13
Timer1 event counter input/toggle output pin.
USB_VBUS_ST
I
MFP14
USB external VBUS regulator status pin.
HSUSB_VBUS_ST
I
MFP15
HSUSB external VBUS regulator status pin.
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC0 channel 15 analog input.
EBI_AD12
I/O
MFP2
EBI address/data bus bit 12.
SC1_PWR
O
MFP3
Smart Card 1 power pin.
SPI0_SS
I/O
MFP4
SPI0 slave select pin.
USCI0_CTL1
I/O
MFP5
USCI0 control 1 pin.
UART0_nCTS
I
MFP6
UART0 clear to Send input pin.
UART3_TXD
O
MFP7
UART3 data transmitter output pin.
I2C2_SMBAL
O
MFP8
I2C2 SMBus SMBALTER pin
EPWM1_CH0
I/O
MFP11
EPWM1 channel 0 output/capture input.
TM0_EXT
I/O
MFP13
Timer0 external capture input/toggle output pin.
USB_VBUS_EN
O
MFP14
USB external VBUS regulator enable pin.
HSUSB_VBUS_EN
O
MFP15
HSUSB external VBUS regulator enable pin.
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC0 channel 14 analog input.
EBI_AD13
I/O
MFP2
EBI address/data bus bit 13.
SC1_RST
O
MFP3
Smart Card 1 reset pin.
SPI0_CLK
I/O
MFP4
SPI0 serial clock pin.
USCI0_DAT1
I/O
MFP5
USCI0 data 1 pin.
UART0_nRTS
O
MFP6
UART0 request to Send output pin.
UART3_RXD
I
MFP7
UART3 data receiver input pin.
I2C2_SMBSUS
O
MFP8
I2C2 SMBus SMBSUS pin (PMBus CONTROL pin)
EPWM1_CH1
I/O
MFP11
EPWM1 channel 1 output/capture input.
EPWM0_SYNC_IN
TM1
53
53
116 PB.15
EADC0_CH15
M480 SERIES DATASHEET
54
54
117 PB.14
EADC0_CH14
May 08, 2020
Page 150 of 523
Rev 3.00
M480
64 64 Pin 128 Pin Name
Pin 2 USB Pin
55
56
55
56
MFP
TM1_EXT
I/O
MFP13
Timer1 external capture input/toggle output pin.
CLKO
O
MFP14
Clock Out
118 PB.13
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH13
A
MFP1
EADC0 channel 13 analog input.
DAC1_OUT
A
MFP1
DAC1 channel analog output.
ACMP0_P3
A
MFP1
Analog comparator 0 positive input 3 pin.
ACMP1_P3
A
MFP1
Analog comparator 1 positive input 3 pin.
EBI_AD14
I/O
MFP2
EBI address/data bus bit 14.
SC1_DAT
I/O
MFP3
Smart Card 1 data pin.
SPI0_MISO
I/O
MFP4
SPI0 MISO (Master In, Slave Out) pin.
USCI0_DAT0
I/O
MFP5
USCI0 data 0 pin.
UART0_TXD
O
MFP6
UART0 data transmitter output pin.
UART3_nRTS
O
MFP7
UART3 request to Send output pin.
I2C2_SCL
I/O
MFP8
I2C2 clock pin.
EPWM1_CH2
I/O
MFP11
EPWM1 channel 2 output/capture input.
TM2_EXT
I/O
MFP13
Timer2 external capture input/toggle output pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH12
A
MFP1
EADC0 channel 12 analog input.
DAC0_OUT
A
MFP1
DAC0 channel analog output.
ACMP0_P2
A
MFP1
Analog comparator 0 positive input 2 pin.
ACMP1_P2
A
MFP1
Analog comparator 1 positive input 2 pin.
EBI_AD15
I/O
MFP2
EBI address/data bus bit 15.
SC1_CLK
O
MFP3
Smart Card 1 clock pin.
SPI0_MOSI
I/O
MFP4
SPI0 MOSI (Master Out, Slave In) pin.
USCI0_CLK
I/O
MFP5
USCI0 clock pin.
UART0_RXD
I
MFP6
UART0 data receiver input pin.
UART3_nCTS
I
MFP7
UART3 clear to Send input pin.
I2C2_SDA
I/O
MFP8
I2C2 data input/output pin.
SD0_nCD
I
MFP9
SD/SDIO0 card detect input pin
EPWM1_CH3
I/O
MFP11
EPWM1 channel 3 output/capture input.
TM3_EXT
I/O
MFP13
Timer3 external capture input/toggle output pin.
119 PB.12
Description
57
57
120 AVDD
P
MFP0
Power supply for internal analog circuit.
58
58
121 VREF
A
MFP0
ADC reference voltage input.
M480 SERIES DATASHEET
Type
Note: This pin needs to be connected with a 1uF capacitor.
May 08, 2020
Page 151 of 523
Rev 3.00
M480
64 64 Pin 128 Pin Name
Pin 2 USB Pin
Type
MFP
Description
59
59
122 AVSS
P
MFP0
Ground pin for analog circuit.
60
60
123 PB.11
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH11
A
MFP1
EADC0 channel 11 analog input.
EBI_ADR16
O
MFP2
EBI address bus bit 16.
UART0_nCTS
I
MFP5
UART0 clear to Send input pin.
UART4_TXD
O
MFP6
UART4 data transmitter output pin.
I2C1_SCL
I/O
MFP7
I2C1 clock pin.
SPI0_I2SMCLK
I/O
MFP9
SPI0 I2S master clock output pin
BPWM1_CH0
I/O
MFP10
BPWM1 channel 0 output/capture input.
SPI3_CLK
I/O
MFP11
SPI3 serial clock pin.
I
MFP14
HSUSB external VBUS regulator status pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH10
A
MFP1
EADC0 channel 10 analog input.
EBI_ADR17
O
MFP2
EBI address bus bit 17.
USCI1_CTL0
I/O
MFP4
USCI1 control 0 pin.
UART0_nRTS
O
MFP5
UART0 request to Send output pin.
UART4_RXD
I
MFP6
UART4 data receiver input pin.
I2C1_SDA
I/O
MFP7
I2C1 data input/output pin.
BPWM1_CH1
I/O
MFP10
BPWM1 channel 1 output/capture input.
SPI3_SS
I/O
MFP11
SPI3 slave select pin.
HSUSB_VBUS_EN
O
MFP14
HSUSB external VBUS regulator enable pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH9
A
MFP1
EADC0 channel 9 analog input.
EBI_ADR18
O
MFP2
EBI address bus bit 18.
USCI1_CTL1
I/O
MFP4
USCI1 control 1 pin.
UART0_TXD
O
MFP5
UART0 data transmitter output pin.
UART1_nCTS
I
MFP6
UART1 clear to Send input pin.
I2C1_SMBAL
O
MFP7
I2C1 SMBus SMBALTER pin
BPWM1_CH2
I/O
MFP10
BPWM1 channel 2 output/capture input.
SPI3_MISO
I/O
MFP11
SPI3 MISO (Master In, Slave Out) pin.
I
MFP13
External interrupt 7 input pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH8
A
MFP1
EADC0 channel 8 analog input.
EBI_ADR19
O
MFP2
EBI address bus bit 19.
HSUSB_VBUS_ST
61
M480 SERIES DATASHEET
62
61
62
124 PB.10
125 PB.9
INT7
63
63
126 PB.8
May 08, 2020
Page 152 of 523
Rev 3.00
M480
64 64 Pin 128 Pin Name
Pin 2 USB Pin
MFP
Description
USCI1_CLK
I/O
MFP4
USCI1 clock pin.
UART0_RXD
I
MFP5
UART0 data receiver input pin.
UART1_nRTS
O
MFP6
UART1 request to Send output pin.
I2C1_SMBSUS
O
MFP7
I2C1 SMBus SMBSUS pin (PMBus CONTROL pin)
BPWM1_CH3
I/O
MFP10
BPWM1 channel 3 output/capture input.
SPI3_MOSI
I/O
MFP11
SPI3 MOSI (Master Out, Slave In) pin.
I
MFP13
External interrupt 6 input pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH7
A
MFP1
EADC0 channel 7 analog input.
EBI_nWRL
O
MFP2
EBI low byte write enable output pin.
USCI1_DAT0
I/O
MFP4
USCI1 data 0 pin.
UART1_TXD
O
MFP6
UART1 data transmitter output pin.
SD1_CMD
I/O
MFP7
SD/SDIO1 command/response pin
EBI_nCS0
O
MFP8
EBI chip select 0 output pin.
BPWM1_CH4
I/O
MFP10
BPWM1 channel 4 output/capture input.
I
MFP11
EPWM1 Brake 0 input pin.
I/O
MFP12
EPWM1 channel 4 output/capture input.
INT5
I
MFP13
External interrupt 5 input pin.
USB_VBUS_ST
I
MFP14
USB external VBUS regulator status pin.
ACMP0_O
O
MFP15
Analog comparator 0 output pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH6
A
MFP1
EADC0 channel 6 analog input.
EBI_nWRH
O
MFP2
EBI high byte write enable output pin
USCI1_DAT1
I/O
MFP4
USCI1 data 1 pin.
UART1_RXD
I
MFP6
UART1 data receiver input pin.
SD1_CLK
O
MFP7
SD/SDIO1 clock output pin
EBI_nCS1
O
MFP8
EBI chip select 1 output pin.
BPWM1_CH5
I/O
MFP10
BPWM1 channel 5 output/capture input.
I
MFP11
EPWM1 Brake 1 input pin.
I/O
MFP12
EPWM1 channel 5 output/capture input.
INT4
I
MFP13
External interrupt 4 input pin.
USB_VBUS_EN
O
MFP14
USB external VBUS regulator enable pin.
ACMP1_O
O
MFP15
Analog comparator 1 output pin.
INT6
64
64
127 PB.7
EPWM1_BRAKE0
EPWM1_CH4
1
1
128 PB.6
EPWM1_BRAKE1
EPWM1_CH5
May 08, 2020
Page 153 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
M480 SERIES DATASHEET
May 08, 2020
Page 154 of 523
Rev 3.00
M480
4.2.5
M485 Series Pin Description
Note: PA.15 MFP can only be as USB_OTG_ID when enable full-Speed USB.
48 64 128 Pin Name
Pin Pin Pin
1
2
3
4
1
2
3
PB.5
MFP
Description
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH5
A
MFP1
EADC0 channel 5 analog input.
ACMP1_N
A
MFP1
Analog comparator 1 negative input pin.
EBI_ADR0
O
MFP2
EBI address bus bit 0.
SD0_DAT3
I/O
MFP3
SD/SDIO0 data line bit 3.
SPI1_MISO
I/O
MFP5
SPI1 MISO (Master In, Slave Out) pin.
I2C0_SCL
I/O
MFP6
I2C0 clock pin.
UART5_TXD
O
MFP7
UART5 data transmitter output pin.
USCI1_CTL0
I/O
MFP8
USCI1 control 0 pin.
SC0_CLK
O
MFP9
Smart Card 0 clock pin.
I2S0_BCLK
O
MFP10
I2S0 bit clock output pin.
EPWM0_CH0
I/O
MFP11
EPWM0 channel 0 output/capture input.
TM0
I/O
MFP14
Timer0 event counter input/toggle output pin.
INT0
I
MFP15
External interrupt 0 input pin.
PB.4
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH4
A
MFP1
EADC0 channel 4 analog input.
ACMP1_P1
A
MFP1
Analog comparator 1 positive input 1 pin.
EBI_ADR1
O
MFP2
EBI address bus bit 1.
SD0_DAT2
I/O
MFP3
SD/SDIO0 data line bit 2.
SPI1_MOSI
I/O
MFP5
SPI1 MOSI (Master Out, Slave In) pin.
I2C0_SDA
I/O
MFP6
I2C0 data input/output pin.
UART5_RXD
I
MFP7
UART5 data receiver input pin.
USCI1_CTL1
I/O
MFP8
USCI1 control 1 pin.
SC0_DAT
I/O
MFP9
Smart Card 0 data pin.
I2S0_MCLK
O
MFP10
I2S0 master clock output pin.
EPWM0_CH1
I/O
MFP11
EPWM0 channel 1 output/capture input.
TM1
I/O
MFP14
Timer1 event counter input/toggle output pin.
INT1
I
MFP15
External interrupt 1 input pin.
PB.3
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH3
A
MFP1
EADC0 channel 3 analog input.
ACMP0_N
A
MFP1
Analog comparator 0 negative input pin.
EBI_ADR2
O
MFP2
EBI address bus bit 2.
May 08, 2020
Page 155 of 523
M480 SERIES DATASHEET
3
2
Type
Rev 3.00
M480
48 64 128 Pin Name
Pin Pin Pin
4
5
4
M480 SERIES DATASHEET
5
Type
MFP
Description
SD0_DAT1
I/O
MFP3
SD/SDIO0 data line bit 1.
SPI1_CLK
I/O
MFP5
SPI1 serial clock pin.
UART1_TXD
O
MFP6
UART1 data transmitter output pin.
UART5_nRTS
O
MFP7
UART5 request to Send output pin.
USCI1_DAT1
I/O
MFP8
USCI1 data 1 pin.
SC0_RST
O
MFP9
Smart Card 0 reset pin.
I2S0_DI
I
MFP10
I2S0 data input pin.
EPWM0_CH2
I/O
MFP11
EPWM0 channel 2 output/capture input.
TM2
I/O
MFP14
Timer2 event counter input/toggle output pin.
INT2
I
MFP15
External interrupt 2 input pin.
PB.2
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH2
A
MFP1
EADC0 channel 2 analog input.
ACMP0_P1
A
MFP1
Analog comparator 0 positive input 1 pin.
OPA0_O
A
MFP1
Operational amplifier 0 output pin.
EBI_ADR3
O
MFP2
EBI address bus bit 3.
SD0_DAT0
I/O
MFP3
SD/SDIO0 data line bit 0.
SPI1_SS
I/O
MFP5
SPI1 slave select pin.
UART1_RXD
I
MFP6
UART1 data receiver input pin.
UART5_nCTS
I
MFP7
UART5 clear to Send input pin.
USCI1_DAT0
I/O
MFP8
USCI1 data 0 pin.
SC0_PWR
O
MFP9
Smart Card 0 power pin.
I2S0_DO
O
MFP10
I2S0 data output pin.
EPWM0_CH3
I/O
MFP11
EPWM0 channel 3 output/capture input.
TM3
I/O
MFP14
Timer3 event counter input/toggle output pin.
INT3
I
MFP15
External interrupt 3 input pin.
PC.12
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR4
O
MFP2
EBI address bus bit 4.
UART0_TXD
O
MFP3
UART0 data transmitter output pin.
I2C0_SCL
I/O
MFP4
I2C0 clock pin.
SPI3_MISO
I/O
MFP6
SPI3 MISO (Master In, Slave Out) pin.
SC0_nCD
I
MFP9
Smart Card 0 card detect pin.
ECAP1_IC2
I
MFP11
Enhanced capture unit 1 input 2 pin.
EPWM1_CH0
I/O
MFP12
EPWM1 channel 0 output/capture input.
ACMP0_O
O
MFP14
Analog comparator 0 output pin.
May 08, 2020
Page 156 of 523
Rev 3.00
M480
48 64 128 Pin Name
Pin Pin Pin
6
7
8
6
9
MFP
Description
PC.11
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR5
O
MFP2
EBI address bus bit 5.
UART0_RXD
I
MFP3
UART0 data receiver input pin.
I2C0_SDA
I/O
MFP4
I2C0 data input/output pin.
SPI3_MOSI
I/O
MFP6
SPI3 MOSI (Master Out, Slave In) pin.
ECAP1_IC1
I
MFP11
Enhanced capture unit 1 input 1 pin.
EPWM1_CH1
I/O
MFP12
EPWM1 channel 1 output/capture input.
ACMP1_O
O
MFP14
Analog comparator 1 output pin.
PC.10
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR6
O
MFP2
EBI address bus bit 6.
SPI3_CLK
I/O
MFP6
SPI3 serial clock pin.
UART3_TXD
O
MFP7
UART3 data transmitter output pin.
CAN1_TXD
O
MFP9
CAN1 bus transmitter output.
ECAP1_IC0
I
MFP11
Enhanced capture unit 1 input 0 pin.
EPWM1_CH2
I/O
MFP12
EPWM1 channel 2 output/capture input.
PC.9
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR7
O
MFP2
EBI address bus bit 7.
SPI3_SS
I/O
MFP6
SPI3 slave select pin.
UART3_RXD
I
MFP7
UART3 data receiver input pin.
CAN1_RXD
I
MFP9
CAN1 bus receiver input.
EPWM1_CH3
I/O
MFP12
EPWM1 channel 3 output/capture input.
PB.1
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH1
A
MFP1
EADC0 channel 1 analog input.
OPA0_N
A
MFP1
Operational amplifier 0 negative input pin.
EBI_ADR8
O
MFP2
EBI address bus bit 8.
SD0_CLK
O
MFP3
SD/SDIO0 clock output pin
SPI1_I2SMCLK
I/O
MFP5
SPI1 I2S master clock output pin
SPI3_I2SMCLK
I/O
MFP6
SPI3 I2S master clock output pin
UART2_TXD
O
MFP7
UART2 data transmitter output pin.
USCI1_CLK
I/O
MFP8
USCI1 clock pin.
I2C1_SCL
I/O
MFP9
I2C1 clock pin.
I2S0_LRCK
O
MFP10
I2S0 left right channel clock output pin.
EPWM0_CH4
I/O
MFP11
EPWM0 channel 4 output/capture input.
EPWM1_CH4
I/O
MFP12
EPWM1 channel 4 output/capture input.
May 08, 2020
Page 157 of 523
M480 SERIES DATASHEET
5
Type
Rev 3.00
M480
48 64 128 Pin Name
Pin Pin Pin
EPWM0_BRAKE0
6
7
8
9
Description
MFP13
EPWM0 Brake 0 input pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH0
A
MFP1
EADC0 channel 0 analog input.
OPA0_P
A
MFP1
Operational amplifier 0 positive input pin.
EBI_ADR9
O
MFP2
EBI address bus bit 9.
SD0_CMD
I/O
MFP3
SD/SDIO0 command/response pin
I
MFP7
UART2 data receiver input pin.
SPI0_I2SMCLK
I/O
MFP8
SPI0 I2S master clock output pin
I2C1_SDA
I/O
MFP9
I2C1 data input/output pin.
EPWM0_CH5
I/O
MFP11
EPWM0 channel 5 output/capture input.
EPWM1_CH5
I/O
MFP12
EPWM1 channel 5 output/capture input.
EPWM0_BRAKE1
I
MFP13
EPWM0 Brake 1 input pin.
11
VSS
P
MFP0
Ground pin for digital circuit.
12
VDD
P
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
13
PA.11
I/O
MFP0
General purpose digital I/O pin.
ACMP0_P0
A
MFP1
Analog comparator 0 positive input 0 pin.
EBI_nRD
O
MFP2
EBI read enable output pin.
SC2_PWR
O
MFP3
Smart Card 2 power pin.
SPI2_SS
I/O
MFP4
SPI2 slave select pin.
SD1_DAT3
I/O
MFP5
SD/SDIO1 data line bit 3.
USCI0_CLK
I/O
MFP6
USCI0 clock pin.
I2C2_SCL
I/O
MFP7
I2C2 clock pin.
BPWM0_CH0
I/O
MFP9
BPWM0 channel 0 output/capture input.
EPWM0_SYNC_OUT
O
MFP10
EPWM0 counter synchronous trigger output pin.
TM0_EXT
I/O
MFP13
Timer0 external capture input/toggle output pin.
DAC1_ST
I
MFP14
DAC1 external trigger input.
I/O
MFP0
General purpose digital I/O pin.
ACMP1_P0
A
MFP1
Analog comparator 1 positive input 0 pin.
OPA1_O
A
MFP1
Operational amplifier 1 output pin.
EBI_nWR
O
MFP2
EBI write enable output pin.
SC2_RST
O
MFP3
Smart Card 2 reset pin.
SPI2_CLK
I/O
MFP4
SPI2 serial clock pin.
SD1_DAT2
I/O
MFP5
SD/SDIO1 data line bit 2.
10
M480 SERIES DATASHEET
8
MFP
I
PB.0
UART2_RXD
7
Type
14
PA.10
May 08, 2020
Page 158 of 523
Rev 3.00
M480
48 64 128 Pin Name
Pin Pin Pin
9
11
15
16
Description
USCI0_DAT0
I/O
MFP6
USCI0 data 0 pin.
I2C2_SDA
I/O
MFP7
I2C2 data input/output pin.
BPWM0_CH1
I/O
MFP9
BPWM0 channel 1 output/capture input.
QEI1_INDEX
I
MFP10
Quadrature encoder 1 index input
ECAP0_IC0
I
MFP11
Enhanced capture unit 0 input 0 pin.
TM1_EXT
I/O
MFP13
Timer1 external capture input/toggle output pin.
DAC0_ST
I
MFP14
DAC0 external trigger input.
I/O
MFP0
General purpose digital I/O pin.
OPA1_N
A
MFP1
Operational amplifier 1 negative input pin.
EBI_MCLK
O
MFP2
EBI external clock output pin.
SC2_DAT
I/O
MFP3
Smart Card 2 data pin.
SPI2_MISO
I/O
MFP4
SPI2 MISO (Master In, Slave Out) pin.
SD1_DAT1
I/O
MFP5
SD/SDIO1 data line bit 1.
USCI0_DAT1
I/O
MFP6
USCI0 data 1 pin.
UART1_TXD
O
MFP7
UART1 data transmitter output pin.
BPWM0_CH2
I/O
MFP9
BPWM0 channel 2 output/capture input.
QEI1_A
I
MFP10
Quadrature encoder 1 phase A input
ECAP0_IC1
I
MFP11
Enhanced capture unit 0 input 1 pin.
TM2_EXT
I/O
MFP13
Timer2 external capture input/toggle output pin.
PA.8
I/O
MFP0
General purpose digital I/O pin.
OPA1_P
A
MFP1
Operational amplifier 1 positive input pin.
EBI_ALE
O
MFP2
EBI address latch enable output pin.
SC2_CLK
O
MFP3
Smart Card 2 clock pin.
SPI2_MOSI
I/O
MFP4
SPI2 MOSI (Master Out, Slave In) pin.
SD1_DAT0
I/O
MFP5
SD/SDIO1 data line bit 0.
USCI0_CTL1
I/O
MFP6
USCI0 control 1 pin.
UART1_RXD
I
MFP7
UART1 data receiver input pin.
BPWM0_CH3
I/O
MFP9
BPWM0 channel 3 output/capture input.
QEI1_B
I
MFP10
Quadrature encoder 1 phase B input
ECAP0_IC2
I
MFP11
Enhanced capture unit 0 input 2 pin.
I/O
MFP13
Timer3 external capture input/toggle output pin.
I
MFP15
External interrupt 4 input pin.
PC.13
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR10
O
MFP2
EBI address bus bit 10.
PA.9
TM3_EXT
INT4
17
MFP
May 08, 2020
Page 159 of 523
M480 SERIES DATASHEET
10
10
Type
Rev 3.00
M480
48 64 128 Pin Name
Pin Pin Pin
SC2_nCD
18
19
M480 SERIES DATASHEET
20
21
Type
MFP
Description
I
MFP3
Smart Card 2 card detect pin.
SPI2_I2SMCLK
I/O
MFP4
SPI2 I2S master clock output pin
CAN1_TXD
O
MFP5
CAN1 bus transmitter output.
USCI0_CTL0
I/O
MFP6
USCI0 control 0 pin.
UART2_TXD
O
MFP7
UART2 data transmitter output pin.
BPWM0_CH4
I/O
MFP9
BPWM0 channel 4 output/capture input.
CLKO
O
MFP13
Clock Out
EADC0_ST
I
MFP14
EADC0 external trigger input.
I/O
MFP0
General purpose digital I/O pin.
OPA2_O
A
MFP1
Operational amplifier 2 output pin.
EBI_nCS0
O
MFP2
EBI chip select 0 output pin.
CAN1_RXD
I
MFP5
CAN1 bus receiver input.
UART2_RXD
I
MFP7
UART2 data receiver input pin.
BPWM0_CH5
I/O
MFP9
BPWM0 channel 5 output/capture input.
QEI0_INDEX
I
MFP10
Quadrature encoder 0 index input
CLKO
O
MFP13
Clock Out
EADC0_ST
I
MFP14
EADC0 external trigger input.
INT5
I
MFP15
External interrupt 5 input pin.
I/O
MFP0
General purpose digital I/O pin.
OPA2_N
A
MFP1
Operational amplifier 2 negative input pin.
EBI_nCS1
O
MFP2
EBI chip select 1 output pin.
UART1_TXD
O
MFP3
UART1 data transmitter output pin.
CAN0_TXD
O
MFP4
CAN0 bus transmitter output.
QEI0_A
I
MFP10
Quadrature encoder 0 phase A input
INT6
I
MFP15
External interrupt 6 input pin.
I/O
MFP0
General purpose digital I/O pin.
OPA2_P
A
MFP1
Operational amplifier 2 positive input pin.
EBI_nCS2
O
MFP2
EBI chip select 2 output pin.
UART1_RXD
I
MFP3
UART1 data receiver input pin.
CAN0_RXD
I
MFP4
CAN0 bus receiver input.
QEI0_B
I
MFP10
Quadrature encoder 0 phase B input
INT7
I
MFP15
External interrupt 7 input pin.
PG.2
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR11
O
MFP2
EBI address bus bit 11.
PD.12
PD.11
PD.10
May 08, 2020
Page 160 of 523
Rev 3.00
M480
48 64 128 Pin Name
Pin Pin Pin
22
23
24
26
27
MFP
Description
SPI2_SS
I/O
MFP3
SPI2 slave select pin.
I2C0_SMBAL
O
MFP4
I2C0 SMBus SMBALTER pin
I2C1_SCL
I/O
MFP5
I2C1 clock pin.
TM0
I/O
MFP13
Timer0 event counter input/toggle output pin.
PG.3
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR12
O
MFP2
EBI address bus bit 12.
SPI2_CLK
I/O
MFP3
SPI2 serial clock pin.
I2C0_SMBSUS
O
MFP4
I2C0 SMBus SMBSUS pin (PMBus CONTROL pin)
I2C1_SDA
I/O
MFP5
I2C1 data input/output pin.
TM1
I/O
MFP13
Timer1 event counter input/toggle output pin.
PG.4
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR13
O
MFP2
EBI address bus bit 13.
SPI2_MISO
I/O
MFP3
SPI2 MISO (Master In, Slave Out) pin.
TM2
I/O
MFP13
Timer2 event counter input/toggle output pin.
PF.11
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR14
O
MFP2
EBI address bus bit 14.
SPI2_MOSI
I/O
MFP3
SPI2 MOSI (Master Out, Slave In) pin.
TAMPER5
I/O
MFP10
TAMPER detector loop pin 5.
TM3
I/O
MFP13
Timer3 event counter input/toggle output pin.
PF.10
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR15
O
MFP2
EBI address bus bit 15.
SC0_nCD
I
MFP3
Smart Card 0 card detect pin.
I2S0_BCLK
O
MFP4
I2S0 bit clock output pin.
SPI0_I2SMCLK
I/O
MFP5
SPI0 I2S master clock output pin
TAMPER4
I/O
MFP10
TAMPER detector loop pin 4.
PF.9
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR16
O
MFP2
EBI address bus bit 16.
SC0_PWR
O
MFP3
Smart Card 0 power pin.
I2S0_MCLK
O
MFP4
I2S0 master clock output pin.
SPI0_SS
I/O
MFP5
SPI0 slave select pin.
TAMPER3
I/O
MFP10
TAMPER detector loop pin 3.
PF.8
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR17
O
MFP2
EBI address bus bit 17.
SC0_RST
O
MFP3
Smart Card 0 reset pin.
May 08, 2020
Page 161 of 523
M480 SERIES DATASHEET
25
Type
Rev 3.00
M480
48 64 128 Pin Name
Pin Pin Pin
I2S0_DI
28
12
M480 SERIES DATASHEET
11
12
29
Type
MFP
Description
I
MFP4
I2S0 data input pin.
SPI0_CLK
I/O
MFP5
SPI0 serial clock pin.
TAMPER2
I/O
MFP10
TAMPER detector loop pin 2.
PF.7
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR18
O
MFP2
EBI address bus bit 18.
SC0_DAT
I/O
MFP3
Smart Card 0 data pin.
I2S0_DO
O
MFP4
I2S0 data output pin.
SPI0_MISO
I/O
MFP5
SPI0 MISO (Master In, Slave Out) pin.
UART4_TXD
O
MFP6
UART4 data transmitter output pin.
TAMPER1
I/O
MFP10
TAMPER detector loop pin 1.
PF.6
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR19
O
MFP2
EBI address bus bit 19.
SC0_CLK
O
MFP3
Smart Card 0 clock pin.
I2S0_LRCK
O
MFP4
I2S0 left right channel clock output pin.
SPI0_MOSI
I/O
MFP5
SPI0 MOSI (Master Out, Slave In) pin.
UART4_RXD
I
MFP6
UART4 data receiver input pin.
EBI_nCS0
O
MFP7
EBI chip select 0 output pin.
TAMPER0
I/O
MFP10
TAMPER detector loop pin 0.
13
30
VDD
P
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
14
31
PF.5
I/O
MFP0
General purpose digital I/O pin.
UART2_RXD
I
MFP2
UART2 data receiver input pin.
UART2_nCTS
I
MFP4
UART2 clear to Send input pin.
BPWM0_CH4
I/O
MFP8
BPWM0 channel 4 output/capture input.
EPWM0_SYNC_OUT
O
MFP9
EPWM0 counter synchronous trigger output pin.
X32_IN
I
MFP10
External 32.768 kHz crystal input pin.
EADC0_ST
I
MFP11
EADC0 external trigger input.
PF.4
I/O
MFP0
General purpose digital I/O pin.
UART2_TXD
O
MFP2
UART2 data transmitter output pin.
UART2_nRTS
O
MFP4
UART2 request to Send output pin.
BPWM0_CH5
I/O
MFP8
BPWM0 channel 5 output/capture input.
X32_OUT
O
MFP10
External 32.768 kHz crystal output pin.
PH.4
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR3
O
MFP2
EBI address bus bit 3.
15
32
33
May 08, 2020
Page 162 of 523
Rev 3.00
M480
48 64 128 Pin Name
Pin Pin Pin
34
35
36
13
16
37
17
38
MFP
Description
I/O
MFP3
SPI1 MISO (Master In, Slave Out) pin.
PH.5
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR2
O
MFP2
EBI address bus bit 2.
SPI1_MOSI
I/O
MFP3
SPI1 MOSI (Master Out, Slave In) pin.
PH.6
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR1
O
MFP2
EBI address bus bit 1.
SPI1_CLK
I/O
MFP3
SPI1 serial clock pin.
PH.7
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR0
O
MFP2
EBI address bus bit 0.
SPI1_SS
I/O
MFP3
SPI1 slave select pin.
PF.3
I/O
MFP0
General purpose digital I/O pin.
EBI_nCS0
O
MFP2
EBI chip select 0 output pin.
UART0_TXD
O
MFP3
UART0 data transmitter output pin.
I2C0_SCL
I/O
MFP4
I2C0 clock pin.
I
MFP10
External 4~24 MHz (high speed) crystal input pin.
BPWM1_CH0
I/O
MFP11
BPWM1 channel 0 output/capture input.
PF.2
I/O
MFP0
General purpose digital I/O pin.
EBI_nCS1
O
MFP2
EBI chip select 1 output pin.
UART0_RXD
I
MFP3
UART0 data receiver input pin.
I2C0_SDA
I/O
MFP4
I2C0 data input/output pin.
QSPI0_CLK
I/O
MFP5
Quad SPI0 serial clock pin.
XT1_OUT
O
MFP10
External 4~24 MHz (high speed) crystal output pin.
BPWM1_CH1
I/O
MFP11
BPWM1 channel 1 output/capture input.
39
VSS
P
MFP0
Ground pin for digital circuit.
40
VDD
P
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
41
PE.8
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR10
O
MFP2
EBI address bus bit 10.
I2S0_BCLK
O
MFP4
I2S0 bit clock output pin.
SPI2_CLK
I/O
MFP5
SPI2 serial clock pin.
USCI1_CTL1
I/O
MFP6
USCI1 control 1 pin.
UART2_TXD
O
MFP7
UART2 data transmitter output pin.
EPWM0_CH0
I/O
MFP10
EPWM0 channel 0 output/capture input.
I
MFP11
EPWM0 Brake 0 input pin.
EPWM0_BRAKE0
May 08, 2020
Page 163 of 523
Rev 3.00
M480 SERIES DATASHEET
SPI1_MISO
XT1_IN
14
Type
M480
48 64 128 Pin Name
Pin Pin Pin
42
43
M480 SERIES DATASHEET
44
45
Type
MFP
Description
ECAP0_IC0
I
MFP12
Enhanced capture unit 0 input 0 pin.
TRACE_CLK
O
MFP14
ETM Trace Clock output pin
PE.9
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR11
O
MFP2
EBI address bus bit 11.
I2S0_MCLK
O
MFP4
I2S0 master clock output pin.
SPI2_MISO
I/O
MFP5
SPI2 MISO (Master In, Slave Out) pin.
USCI1_CTL0
I/O
MFP6
USCI1 control 0 pin.
UART2_RXD
I
MFP7
UART2 data receiver input pin.
EPWM0_CH1
I/O
MFP10
EPWM0 channel 1 output/capture input.
EPWM0_BRAKE1
I
MFP11
EPWM0 Brake 1 input pin.
ECAP0_IC1
I
MFP12
Enhanced capture unit 0 input 1 pin.
TRACE_DATA0
O
MFP14
ETM Trace Data 0 output pin
PE.10
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR12
O
MFP2
EBI address bus bit 12.
I2S0_DI
I
MFP4
I2S0 data input pin.
SPI2_MOSI
I/O
MFP5
SPI2 MOSI (Master Out, Slave In) pin.
USCI1_DAT0
I/O
MFP6
USCI1 data 0 pin.
UART3_TXD
O
MFP7
UART3 data transmitter output pin.
EPWM0_CH2
I/O
MFP10
EPWM0 channel 2 output/capture input.
EPWM1_BRAKE0
I
MFP11
EPWM1 Brake 0 input pin.
ECAP0_IC2
I
MFP12
Enhanced capture unit 0 input 2 pin.
TRACE_DATA1
O
MFP14
ETM Trace Data 1 output pin
PE.11
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR13
O
MFP2
EBI address bus bit 13.
I2S0_DO
O
MFP4
I2S0 data output pin.
SPI2_SS
I/O
MFP5
SPI2 slave select pin.
USCI1_DAT1
I/O
MFP6
USCI1 data 1 pin.
UART3_RXD
I
MFP7
UART3 data receiver input pin.
UART1_nCTS
I
MFP8
UART1 clear to Send input pin.
EPWM0_CH3
I/O
MFP10
EPWM0 channel 3 output/capture input.
EPWM1_BRAKE1
I
MFP11
EPWM1 Brake 1 input pin.
ECAP1_IC2
I
MFP13
Enhanced capture unit 1 input 2 pin.
TRACE_DATA2
O
MFP14
ETM Trace Data 2 output pin
PE.12
I/O
MFP0
General purpose digital I/O pin.
May 08, 2020
Page 164 of 523
Rev 3.00
M480
48 64 128 Pin Name
Pin Pin Pin
46
48
Description
O
MFP2
EBI address bus bit 14.
I2S0_LRCK
O
MFP4
I2S0 left right channel clock output pin.
SPI2_I2SMCLK
I/O
MFP5
SPI2 I2S master clock output pin
USCI1_CLK
I/O
MFP6
USCI1 clock pin.
UART1_nRTS
O
MFP8
UART1 request to Send output pin.
EPWM0_CH4
I/O
MFP10
EPWM0 channel 4 output/capture input.
ECAP1_IC1
I
MFP13
Enhanced capture unit 1 input 1 pin.
TRACE_DATA3
O
MFP14
ETM Trace Data 3 output pin
PE.13
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR15
O
MFP2
EBI address bus bit 15.
I2C0_SCL
I/O
MFP4
I2C0 clock pin.
UART4_nRTS
O
MFP5
UART4 request to Send output pin.
UART1_TXD
O
MFP8
UART1 data transmitter output pin.
EPWM0_CH5
I/O
MFP10
EPWM0 channel 5 output/capture input.
EPWM1_CH0
I/O
MFP11
EPWM1 channel 0 output/capture input.
BPWM1_CH5
I/O
MFP12
BPWM1 channel 5 output/capture input.
I
MFP13
Enhanced capture unit 1 input 0 pin.
PC.8
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR16
O
MFP2
EBI address bus bit 16.
I2C0_SDA
I/O
MFP4
I2C0 data input/output pin.
UART4_nCTS
I
MFP5
UART4 clear to Send input pin.
UART1_RXD
I
MFP8
UART1 data receiver input pin.
EPWM1_CH1
I/O
MFP11
EPWM1 channel 1 output/capture input.
BPWM1_CH4
I/O
MFP12
BPWM1 channel 4 output/capture input.
PC.7
I/O
MFP0
General purpose digital I/O pin.
EBI_AD9
I/O
MFP2
EBI address/data bus bit 9.
SPI1_MISO
I/O
MFP4
SPI1 MISO (Master In, Slave Out) pin.
UART4_TXD
O
MFP5
UART4 data transmitter output pin.
SC2_PWR
O
MFP6
Smart Card 2 power pin.
UART0_nCTS
I
MFP7
UART0 clear to Send input pin.
I2C1_SMBAL
O
MFP8
I2C1 SMBus SMBALTER pin
EPWM1_CH2
I/O
MFP11
EPWM1 channel 2 output/capture input.
BPWM1_CH0
I/O
MFP12
BPWM1 channel 0 output/capture input.
TM0
I/O
MFP14
Timer0 event counter input/toggle output pin.
May 08, 2020
Page 165 of 523
M480 SERIES DATASHEET
18
MFP
EBI_ADR14
ECAP1_IC0
47
Type
Rev 3.00
M480
48 64 128 Pin Name
Pin Pin Pin
19
15
M480 SERIES DATASHEET
16
20
21
49
50
51
Type
MFP
Description
INT3
I
MFP15
External interrupt 3 input pin.
PC.6
I/O
MFP0
General purpose digital I/O pin.
EBI_AD8
I/O
MFP2
EBI address/data bus bit 8.
SPI1_MOSI
I/O
MFP4
SPI1 MOSI (Master Out, Slave In) pin.
UART4_RXD
I
MFP5
UART4 data receiver input pin.
SC2_RST
O
MFP6
Smart Card 2 reset pin.
UART0_nRTS
O
MFP7
UART0 request to Send output pin.
I2C1_SMBSUS
O
MFP8
I2C1 SMBus SMBSUS pin (PMBus CONTROL pin)
EPWM1_CH3
I/O
MFP11
EPWM1 channel 3 output/capture input.
BPWM1_CH1
I/O
MFP12
BPWM1 channel 1 output/capture input.
TM1
I/O
MFP14
Timer1 event counter input/toggle output pin.
INT2
I
MFP15
External interrupt 2 input pin.
PA.7
I/O
MFP0
General purpose digital I/O pin.
EBI_AD7
I/O
MFP2
EBI address/data bus bit 7.
SPI1_CLK
I/O
MFP4
SPI1 serial clock pin.
SC2_DAT
I/O
MFP6
Smart Card 2 data pin.
UART0_TXD
O
MFP7
UART0 data transmitter output pin.
I2C1_SCL
I/O
MFP8
I2C1 clock pin.
EPWM1_CH4
I/O
MFP11
EPWM1 channel 4 output/capture input.
BPWM1_CH2
I/O
MFP12
BPWM1 channel 2 output/capture input.
ACMP0_WLAT
I
MFP13
Analog comparator 0 window latch input pin
TM2
I/O
MFP14
Timer2 event counter input/toggle output pin.
INT1
I
MFP15
External interrupt 1 input pin.
PA.6
I/O
MFP0
General purpose digital I/O pin.
EBI_AD6
I/O
MFP2
EBI address/data bus bit 6.
SPI1_SS
I/O
MFP4
SPI1 slave select pin.
SD1_nCD
I
MFP5
SD/SDIO1 card detect input pin
SC2_CLK
O
MFP6
Smart Card 2 clock pin.
UART0_RXD
I
MFP7
UART0 data receiver input pin.
I2C1_SDA
I/O
MFP8
I2C1 data input/output pin.
EPWM1_CH5
I/O
MFP11
EPWM1 channel 5 output/capture input.
BPWM1_CH3
I/O
MFP12
BPWM1 channel 3 output/capture input.
ACMP1_WLAT
I
MFP13
Analog comparator 1 window latch input pin
I/O
MFP14
Timer3 event counter input/toggle output pin.
TM3
May 08, 2020
Page 166 of 523
Rev 3.00
M480
48 64 128 Pin Name
Pin Pin Pin
Type
MFP
Description
INT0
I
MFP15
External interrupt 0 input pin.
22
52
VSS
P
MFP0
Ground pin for digital circuit.
23
53
VDD
P
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
24
54
LDO_CAP
A
MFP0
LDO output pin.
Note: This pin needs to be connected with an external
capacitor.
17
26
55
56
PA.5
I/O
MFP0
General purpose digital I/O pin.
SPIM_D2
I/O
MFP2
SPIM data 2 pin for Quad Mode I/O.
QSPI0_MISO1
I/O
MFP3
Quad SPI0 MISO1 (Master In, Slave Out) pin.
SPI1_I2SMCLK
I/O
MFP4
SPI1 I2S master clock output pin
SD1_CMD
I/O
MFP5
SD/SDIO1 command/response pin
SC2_nCD
I
MFP6
Smart Card 2 card detect pin.
UART0_nCTS
I
MFP7
UART0 clear to Send input pin.
UART5_TXD
O
MFP8
UART5 data transmitter output pin.
I2C0_SCL
I/O
MFP9
I2C0 clock pin.
CAN0_TXD
O
MFP10
CAN0 bus transmitter output.
BPWM0_CH5
I/O
MFP12
BPWM0 channel 5 output/capture input.
EPWM0_CH0
I/O
MFP13
EPWM0 channel 0 output/capture input.
QEI0_INDEX
I
MFP14
Quadrature encoder 0 index input
PA.4
I/O
MFP0
General purpose digital I/O pin.
SPIM_D3
I/O
MFP2
SPIM data 3 pin for Quad Mode I/O.
QSPI0_MOSI1
I/O
MFP3
Quad SPI0 MOSI1 (Master Out, Slave In) pin.
SPI0_I2SMCLK
I/O
MFP4
SPI0 I2S master clock output pin
SD1_CLK
O
MFP5
SD/SDIO1 clock output pin
SC0_nCD
I
MFP6
Smart Card 0 card detect pin.
UART0_nRTS
O
MFP7
UART0 request to Send output pin.
UART5_RXD
I
MFP8
UART5 data receiver input pin.
I2C0_SDA
I/O
MFP9
I2C0 data input/output pin.
CAN0_RXD
I
MFP10
CAN0 bus receiver input.
BPWM0_CH4
I/O
MFP12
BPWM0 channel 4 output/capture input.
EPWM0_CH1
I/O
MFP13
EPWM0 channel 1 output/capture input.
I
MFP14
Quadrature encoder 0 phase A input
PA.3
I/O
MFP0
General purpose digital I/O pin.
SPIM_SS
I/O
MFP2
SPIM slave select pin.
QEI0_A
19
27
57
May 08, 2020
Page 167 of 523
M480 SERIES DATASHEET
18
25
Rev 3.00
M480
48 64 128 Pin Name
Pin Pin Pin
Type
QSPI0_SS
I/O
MFP3
Quad SPI0 slave select pin.
SPI0_SS
I/O
MFP4
SPI0 slave select pin.
SD1_DAT3
I/O
MFP5
SD/SDIO1 data line bit 3.
SC0_PWR
O
MFP6
Smart Card 0 power pin.
UART4_TXD
O
MFP7
UART4 data transmitter output pin.
UART1_TXD
O
MFP8
UART1 data transmitter output pin.
I2C1_SCL
I/O
MFP9
I2C1 clock pin.
BPWM0_CH3
I/O
MFP12
BPWM0 channel 3 output/capture input.
EPWM0_CH2
I/O
MFP13
EPWM0 channel 2 output/capture input.
I
MFP14
Quadrature encoder 0 phase B input
PA.2
I/O
MFP0
General purpose digital I/O pin.
SPIM_CLK
I/O
MFP2
SPIM serial clock pin.
QSPI0_CLK
I/O
MFP3
Quad SPI0 serial clock pin.
SPI0_CLK
I/O
MFP4
SPI0 serial clock pin.
SD1_DAT2
I/O
MFP5
SD/SDIO1 data line bit 2.
SC0_RST
O
MFP6
Smart Card 0 reset pin.
UART4_RXD
I
MFP7
UART4 data receiver input pin.
UART1_RXD
I
MFP8
UART1 data receiver input pin.
I2C1_SDA
I/O
MFP9
I2C1 data input/output pin.
BPWM0_CH2
I/O
MFP12
BPWM0 channel 2 output/capture input.
EPWM0_CH3
I/O
MFP13
EPWM0 channel 3 output/capture input.
PA.1
I/O
MFP0
General purpose digital I/O pin.
SPIM_MISO
I/O
MFP2
SPIM MISO (Master In, Slave Out) pin.
QSPI0_MISO0
I/O
MFP3
Quad SPI0 MISO0 (Master In, Slave Out) pin.
SPI0_MISO
I/O
MFP4
SPI0 MISO (Master In, Slave Out) pin.
SD1_DAT1
I/O
MFP5
SD/SDIO1 data line bit 1.
SC0_DAT
I/O
MFP6
Smart Card 0 data pin.
UART0_TXD
O
MFP7
UART0 data transmitter output pin.
UART1_nCTS
I
MFP8
UART1 clear to Send input pin.
I2C2_SCL
I/O
MFP9
I2C2 clock pin.
BPWM0_CH1
I/O
MFP12
BPWM0 channel 1 output/capture input.
EPWM0_CH4
I/O
MFP13
EPWM0 channel 4 output/capture input.
I
MFP15
DAC1 external trigger input.
I/O
MFP0
General purpose digital I/O pin.
QEI0_B
20
M480 SERIES DATASHEET
21
28
29
58
59
DAC1_ST
22
30
60
PA.0
May 08, 2020
MFP
Description
Page 168 of 523
Rev 3.00
M480
48 64 128 Pin Name
Pin Pin Pin
23
31
Description
I/O
MFP2
SPIM MOSI (Master Out, Slave In) pin.
QSPI0_MOSI0
I/O
MFP3
Quad SPI0 MOSI0 (Master Out, Slave In) pin.
SPI0_MOSI
I/O
MFP4
SPI0 MOSI (Master Out, Slave In) pin.
SD1_DAT0
I/O
MFP5
SD/SDIO1 data line bit 0.
SC0_CLK
O
MFP6
Smart Card 0 clock pin.
UART0_RXD
I
MFP7
UART0 data receiver input pin.
UART1_nRTS
O
MFP8
UART1 request to Send output pin.
I2C2_SDA
I/O
MFP9
I2C2 data input/output pin.
BPWM0_CH0
I/O
MFP12
BPWM0 channel 0 output/capture input.
EPWM0_CH5
I/O
MFP13
EPWM0 channel 5 output/capture input.
DAC0_ST
I
MFP15
DAC0 external trigger input.
61
VDDIO
P
MFP0
Power supply for PA.0~PA.5.
62
PE.14
I/O
MFP0
General purpose digital I/O pin.
EBI_AD8
I/O
MFP2
EBI address/data bus bit 8.
UART2_TXD
O
MFP3
UART2 data transmitter output pin.
CAN0_TXD
O
MFP4
CAN0 bus transmitter output.
SD1_nCD
I
MFP5
SD/SDIO1 card detect input pin
PE.15
I/O
MFP0
General purpose digital I/O pin.
EBI_AD9
I/O
MFP2
EBI address/data bus bit 9.
UART2_RXD
I
MFP3
UART2 data receiver input pin.
CAN0_RXD
I
MFP4
CAN0 bus receiver input.
nRESET
I
MFP0
External reset input: active LOW, with an internal pull-up.
Set this pin low reset to initial state.
64
Note: It is recommended to use 10 kΩ pull-up resistor
and 10 uF capacitor on nRESET pin.
25
33
65
PF.0
I/O
MFP0
General purpose digital I/O pin.
UART1_TXD
O
MFP2
UART1 data transmitter output pin.
I2C1_SCL
I/O
MFP3
I2C1 clock pin.
BPWM1_CH0
I/O
MFP12
BPWM1 channel 0 output/capture input.
ICE_DAT
O
MFP14
Serial wired debugger data pin.
Note: It is recommended to use 100 kΩ pull-up resistor
on ICE_DAT pin.
26
34
66
PF.1
I/O
MFP0
General purpose digital I/O pin.
I
MFP2
UART1 data receiver input pin.
I2C1_SDA
I/O
MFP3
I2C1 data input/output pin.
BPWM1_CH1
I/O
MFP12
BPWM1 channel 1 output/capture input.
UART1_RXD
May 08, 2020
Page 169 of 523
Rev 3.00
M480 SERIES DATASHEET
32
MFP
SPIM_MOSI
63
24
Type
M480
48 64 128 Pin Name
Pin Pin Pin
ICE_CLK
Type
I
MFP
MFP14
Description
Serial wired debugger clock pin.
Note: It is recommended to use 100 kΩ pull-up resistor
on ICE_CLK pin.
67
PD.9
I/O
MFP0
General purpose digital I/O pin.
EBI_AD7
I/O
MFP2
EBI address/data bus bit 7.
I2C2_SCL
I/O
MFP3
I2C2 clock pin.
I
MFP4
UART2 clear to Send input pin.
PD.8
I/O
MFP0
General purpose digital I/O pin.
EBI_AD6
I/O
MFP2
EBI address/data bus bit 6.
I2C2_SDA
I/O
MFP3
I2C2 data input/output pin.
UART2_nRTS
O
MFP4
UART2 request to Send output pin.
PC.5
I/O
MFP0
General purpose digital I/O pin.
EBI_AD5
I/O
MFP2
EBI address/data bus bit 5.
SPIM_D2
I/O
MFP3
SPIM data 2 pin for Quad Mode I/O.
QSPI0_MISO1
I/O
MFP4
Quad SPI0 MISO1 (Master In, Slave Out) pin.
UART2_TXD
O
MFP8
UART2 data transmitter output pin.
I2C1_SCL
I/O
MFP9
I2C1 clock pin.
CAN0_TXD
O
MFP10
CAN0 bus transmitter output.
UART4_TXD
O
MFP11
UART4 data transmitter output pin.
EPWM1_CH0
I/O
MFP12
EPWM1 channel 0 output/capture input.
PC.4
I/O
MFP0
General purpose digital I/O pin.
EBI_AD4
I/O
MFP2
EBI address/data bus bit 4.
SPIM_D3
I/O
MFP3
SPIM data 3 pin for Quad Mode I/O.
QSPI0_MOSI1
I/O
MFP4
Quad SPI0 MOSI1 (Master Out, Slave In) pin.
SC1_nCD
I
MFP5
Smart Card 1 card detect pin.
I2S0_BCLK
O
MFP6
I2S0 bit clock output pin.
SPI1_I2SMCLK
I/O
MFP7
SPI1 I2S master clock output pin
I
MFP8
UART2 data receiver input pin.
I2C1_SDA
I/O
MFP9
I2C1 data input/output pin.
CAN0_RXD
I
MFP10
CAN0 bus receiver input.
UART4_RXD
I
MFP11
UART4 data receiver input pin.
EPWM1_CH1
I/O
MFP12
EPWM1 channel 1 output/capture input.
PC.3
I/O
MFP0
General purpose digital I/O pin.
EBI_AD3
I/O
MFP2
EBI address/data bus bit 3.
SPIM_SS
I/O
MFP3
SPIM slave select pin.
UART2_nCTS
68
27
M480 SERIES DATASHEET
28
35
36
69
70
UART2_RXD
29
37
71
May 08, 2020
Page 170 of 523
Rev 3.00
M480
48 64 128 Pin Name
Pin Pin Pin
Type
QSPI0_SS
I/O
MFP4
Quad SPI0 slave select pin.
SC1_PWR
O
MFP5
Smart Card 1 power pin.
I2S0_MCLK
O
MFP6
I2S0 master clock output pin.
SPI1_MISO
I/O
MFP7
SPI1 MISO (Master In, Slave Out) pin.
UART2_nRTS
O
MFP8
UART2 request to Send output pin.
I2C0_SMBAL
O
MFP9
I2C0 SMBus SMBALTER pin
CAN1_TXD
O
MFP10
CAN1 bus transmitter output.
UART3_TXD
O
MFP11
UART3 data transmitter output pin.
EPWM1_CH2
I/O
MFP12
EPWM1 channel 2 output/capture input.
PC.2
I/O
MFP0
General purpose digital I/O pin.
EBI_AD2
I/O
MFP2
EBI address/data bus bit 2.
SPIM_CLK
I/O
MFP3
SPIM serial clock pin.
QSPI0_CLK
I/O
MFP4
Quad SPI0 serial clock pin.
SC1_RST
O
MFP5
Smart Card 1 reset pin.
I2S0_DI
I
MFP6
I2S0 data input pin.
I/O
MFP7
SPI1 MOSI (Master Out, Slave In) pin.
UART2_nCTS
I
MFP8
UART2 clear to Send input pin.
I2C0_SMBSUS
O
MFP9
I2C0 SMBus SMBSUS pin (PMBus CONTROL pin)
CAN1_RXD
I
MFP10
CAN1 bus receiver input.
UART3_RXD
I
MFP11
UART3 data receiver input pin.
EPWM1_CH3
I/O
MFP12
EPWM1 channel 3 output/capture input.
PC.1
I/O
MFP0
General purpose digital I/O pin.
EBI_AD1
I/O
MFP2
EBI address/data bus bit 1.
SPIM_MISO
I/O
MFP3
SPIM MISO (Master In, Slave Out) pin.
QSPI0_MISO0
I/O
MFP4
Quad SPI0 MISO0 (Master In, Slave Out) pin.
SC1_DAT
I/O
MFP5
Smart Card 1 data pin.
I2S0_DO
O
MFP6
I2S0 data output pin.
SPI1_CLK
I/O
MFP7
SPI1 serial clock pin.
UART2_TXD
O
MFP8
UART2 data transmitter output pin.
I2C0_SCL
I/O
MFP9
I2C0 clock pin.
EPWM1_CH4
I/O
MFP12
EPWM1 channel 4 output/capture input.
ACMP0_O
O
MFP14
Analog comparator 0 output pin.
PC.0
I/O
MFP0
General purpose digital I/O pin.
EBI_AD0
I/O
MFP2
EBI address/data bus bit 0.
30
38
72
SPI1_MOSI
32
39
40
73
74
May 08, 2020
Description
Page 171 of 523
M480 SERIES DATASHEET
31
MFP
Rev 3.00
M480
48 64 128 Pin Name
Pin Pin Pin
Type
MFP
Description
SPIM_MOSI
I/O
MFP3
SPIM MOSI (Master Out, Slave In) pin.
QSPI0_MOSI0
I/O
MFP4
Quad SPI0 MOSI0 (Master Out, Slave In) pin.
SC1_CLK
O
MFP5
Smart Card 1 clock pin.
I2S0_LRCK
O
MFP6
I2S0 left right channel clock output pin.
SPI1_SS
I/O
MFP7
SPI1 slave select pin.
I
MFP8
UART2 data receiver input pin.
I2C0_SDA
I/O
MFP9
I2C0 data input/output pin.
EPWM1_CH5
I/O
MFP12
EPWM1 channel 5 output/capture input.
ACMP1_O
O
MFP14
Analog comparator 1 output pin.
75
VSS
P
MFP0
Ground pin for digital circuit.
76
VDD
P
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
77
PG.9
I/O
MFP0
General purpose digital I/O pin.
EBI_AD0
I/O
MFP2
EBI address/data bus bit 0.
SD1_DAT3
I/O
MFP3
SD/SDIO1 data line bit 3.
SPIM_D2
I/O
MFP4
SPIM data 2 pin for Quad Mode I/O.
BPWM0_CH5
I/O
MFP12
BPWM0 channel 5 output/capture input.
PG.10
I/O
MFP0
General purpose digital I/O pin.
EBI_AD1
I/O
MFP2
EBI address/data bus bit 1.
SD1_DAT2
I/O
MFP3
SD/SDIO1 data line bit 2.
SPIM_D3
I/O
MFP4
SPIM data 3 pin for Quad Mode I/O.
BPWM0_CH4
I/O
MFP12
BPWM0 channel 4 output/capture input.
PG.11
I/O
MFP0
General purpose digital I/O pin.
EBI_AD2
I/O
MFP2
EBI address/data bus bit 2.
SD1_DAT1
I/O
MFP3
SD/SDIO1 data line bit 1.
SPIM_SS
I/O
MFP4
SPIM slave select pin.
BPWM0_CH3
I/O
MFP12
BPWM0 channel 3 output/capture input.
PG.12
I/O
MFP0
General purpose digital I/O pin.
EBI_AD3
I/O
MFP2
EBI address/data bus bit 3.
SD1_DAT0
I/O
MFP3
SD/SDIO1 data line bit 0.
SPIM_CLK
I/O
MFP4
SPIM serial clock pin.
BPWM0_CH2
I/O
MFP12
BPWM0 channel 2 output/capture input.
PG.13
I/O
MFP0
General purpose digital I/O pin.
EBI_AD4
I/O
MFP2
EBI address/data bus bit 4.
UART2_RXD
78
M480 SERIES DATASHEET
79
80
81
May 08, 2020
Page 172 of 523
Rev 3.00
M480
48 64 128 Pin Name
Pin Pin Pin
Type
SD1_CMD
I/O
MFP3
SD/SDIO1 command/response pin
SPIM_MISO
I/O
MFP4
SPIM MISO (Master In, Slave Out) pin.
BPWM0_CH1
I/O
MFP12
BPWM0 channel 1 output/capture input.
PG.14
I/O
MFP0
General purpose digital I/O pin.
EBI_AD5
I/O
MFP2
EBI address/data bus bit 5.
SD1_CLK
O
MFP3
SD/SDIO1 clock output pin
SPIM_MOSI
I/O
MFP4
SPIM MOSI (Master Out, Slave In) pin.
BPWM0_CH0
I/O
MFP12
BPWM0 channel 0 output/capture input.
PG.15
I/O
MFP0
General purpose digital I/O pin.
SD1_nCD
I
MFP3
SD/SDIO1 card detect input pin
CLKO
O
MFP14
Clock Out
EADC0_ST
I
MFP15
EADC0 external trigger input.
PD.13
I/O
MFP0
General purpose digital I/O pin.
EBI_AD10
I/O
MFP2
EBI address/data bus bit 10.
SD0_nCD
I
MFP3
SD/SDIO0 card detect input pin
SPI0_I2SMCLK
I/O
MFP4
SPI0 I2S master clock output pin
SPI1_I2SMCLK
I/O
MFP5
SPI1 I2S master clock output pin
I
MFP7
Smart Card 2 card detect pin.
PA.12
I/O
MFP0
General purpose digital I/O pin.
I2S0_BCLK
O
MFP2
I2S0 bit clock output pin.
UART4_TXD
O
MFP3
UART4 data transmitter output pin.
I2C1_SCL
I/O
MFP4
I2C1 clock pin.
SPI2_SS
I/O
MFP5
SPI2 slave select pin.
CAN0_TXD
O
MFP6
CAN0 bus transmitter output.
SC2_PWR
O
MFP7
Smart Card 2 power pin.
BPWM1_CH2
I/O
MFP11
BPWM1 channel 2 output/capture input.
QEI1_INDEX
I
MFP12
Quadrature encoder 1 index input
USB_VBUS
P
MFP14
Power supply from USB host or HUB.
PA.13
I/O
MFP0
General purpose digital I/O pin.
I2S0_MCLK
O
MFP2
I2S0 master clock output pin.
UART4_RXD
I
MFP3
UART4 data receiver input pin.
I2C1_SDA
I/O
MFP4
I2C1 data input/output pin.
SPI2_CLK
I/O
MFP5
SPI2 serial clock pin.
I
MFP6
CAN0 bus receiver input.
82
83
84
SC2_nCD
33
86
CAN0_RXD
May 08, 2020
Description
Page 173 of 523
M480 SERIES DATASHEET
34
85
MFP
Rev 3.00
M480
48 64 128 Pin Name
Pin Pin Pin
Type
SC2_RST
O
MFP7
Smart Card 2 reset pin.
BPWM1_CH3
I/O
MFP11
BPWM1 channel 3 output/capture input.
QEI1_A
I
MFP12
Quadrature encoder 1 phase A input
USB_D-
A
MFP14
USB differential signal D-.
I/O
MFP0
General purpose digital I/O pin.
I2S0_DI
I
MFP2
I2S0 data input pin.
UART0_TXD
O
MFP3
UART0 data transmitter output pin.
SPI2_MISO
I/O
MFP5
SPI2 MISO (Master In, Slave Out) pin.
I2C2_SCL
I/O
MFP6
I2C2 clock pin.
SC2_DAT
I/O
MFP7
Smart Card 2 data pin.
BPWM1_CH4
I/O
MFP11
BPWM1 channel 4 output/capture input.
QEI1_B
I
MFP12
Quadrature encoder 1 phase B input
USB_D+
A
MFP14
USB differential signal D+.
PA.15
I/O
MFP0
General purpose digital I/O pin.
I2S0_DO
O
MFP2
I2S0 data output pin.
UART0_RXD
I
MFP3
UART0 data receiver input pin.
SPI2_MOSI
I/O
MFP5
SPI2 MOSI (Master Out, Slave In) pin.
I2C2_SDA
I/O
MFP6
I2C2 data input/output pin.
SC2_CLK
O
MFP7
Smart Card 2 clock pin.
BPWM1_CH5
I/O
MFP11
BPWM1 channel 5 output/capture input.
EPWM0_SYNC_IN
I
MFP12
EPWM0 counter synchronous trigger input pin.
USB_OTG_ID
I
MFP14
USB_ identification.
35
87
36
88
PA.14
MFP
Description
M480 SERIES DATASHEET
41
89
HSUSB_VRES
A
MFP0
HSUSB module reference resister
42
90
HSUSB_VDD33
P
MFP0
Power supply for HSUSB VDD33
43
91
HSUSB_VBUS
P
MFP0
HSUSB Power supply from USB host or HUB.
44
92
HSUSB_D-
A
MFP0
HSUSB differential signal D-.
45
93
HSUSB_VSS
P
MFP0
Ground pin for HSUSB.
46
94
HSUSB_D+
A
MFP0
HSUSB differential signal D+.
47
95
HSUSB_VDD12_CAP
A
MFP0
HSUSB Internal power regulator output 1.2V decoupling
pin.
Note: This pin needs to be connected with a 1uF
capacitor.
48
96
HSUSB_ID
I
MFP0
HSUSB identification.
97
PE.7
I/O
MFP0
General purpose digital I/O pin.
SD0_CMD
I/O
MFP3
SD/SDIO0 command/response pin
May 08, 2020
Page 174 of 523
Rev 3.00
M480
48 64 128 Pin Name
Pin Pin Pin
Type
SPIM_D2
I/O
MFP4
SPIM data 2 pin for Quad Mode I/O.
UART5_TXD
O
MFP8
UART5 data transmitter output pin.
CAN1_TXD
O
MFP9
CAN1 bus transmitter output.
QEI1_INDEX
I
MFP11
Quadrature encoder 1 index input
EPWM0_CH0
I/O
MFP12
EPWM0 channel 0 output/capture input.
BPWM0_CH5
I/O
MFP13
BPWM0 channel 5 output/capture input.
PE.6
I/O
MFP0
General purpose digital I/O pin.
SD0_CLK
O
MFP3
SD/SDIO0 clock output pin
SPIM_D3
I/O
MFP4
SPIM data 3 pin for Quad Mode I/O.
SPI3_I2SMCLK
I/O
MFP5
SPI3 I2S master clock output pin
I
MFP6
Smart Card 0 card detect pin.
USCI0_CTL0
I/O
MFP7
USCI0 control 0 pin.
UART5_RXD
I
MFP8
UART5 data receiver input pin.
CAN1_RXD
I
MFP9
CAN1 bus receiver input.
QEI1_A
I
MFP11
Quadrature encoder 1 phase A input
EPWM0_CH1
I/O
MFP12
EPWM0 channel 1 output/capture input.
BPWM0_CH4
I/O
MFP13
BPWM0 channel 4 output/capture input.
PE.5
I/O
MFP0
General purpose digital I/O pin.
EBI_nRD
O
MFP2
EBI read enable output pin.
SD0_DAT3
I/O
MFP3
SD/SDIO0 data line bit 3.
SPIM_SS
I/O
MFP4
SPIM slave select pin.
SPI3_SS
I/O
MFP5
SPI3 slave select pin.
SC0_PWR
O
MFP6
Smart Card 0 power pin.
USCI0_CTL1
I/O
MFP7
USCI0 control 1 pin.
I
MFP11
Quadrature encoder 1 phase B input
EPWM0_CH2
I/O
MFP12
EPWM0 channel 2 output/capture input.
BPWM0_CH3
I/O
MFP13
BPWM0 channel 3 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_nWR
O
MFP2
EBI write enable output pin.
SD0_DAT2
I/O
MFP3
SD/SDIO0 data line bit 2.
SPIM_CLK
I/O
MFP4
SPIM serial clock pin.
SPI3_CLK
I/O
MFP5
SPI3 serial clock pin.
SC0_RST
O
MFP6
Smart Card 0 reset pin.
USCI0_DAT1
I/O
MFP7
USCI0 data 1 pin.
98
SC0_nCD
99
100 PE.4
May 08, 2020
Description
Page 175 of 523
M480 SERIES DATASHEET
QEI1_B
MFP
Rev 3.00
M480
48 64 128 Pin Name
Pin Pin Pin
Type
MFP
Description
QEI0_INDEX
I
MFP11
Quadrature encoder 0 index input
EPWM0_CH3
I/O
MFP12
EPWM0 channel 3 output/capture input.
BPWM0_CH2
I/O
MFP13
BPWM0 channel 2 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_MCLK
O
MFP2
EBI external clock output pin.
SD0_DAT1
I/O
MFP3
SD/SDIO0 data line bit 1.
SPIM_MISO
I/O
MFP4
SPIM MISO (Master In, Slave Out) pin.
SPI3_MISO
I/O
MFP5
SPI3 MISO (Master In, Slave Out) pin.
SC0_DAT
I/O
MFP6
Smart Card 0 data pin.
USCI0_DAT0
I/O
MFP7
USCI0 data 0 pin.
I
MFP11
Quadrature encoder 0 phase A input
EPWM0_CH4
I/O
MFP12
EPWM0 channel 4 output/capture input.
BPWM0_CH1
I/O
MFP13
BPWM0 channel 1 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_ALE
O
MFP2
EBI address latch enable output pin.
SD0_DAT0
I/O
MFP3
SD/SDIO0 data line bit 0.
SPIM_MOSI
I/O
MFP4
SPIM MOSI (Master Out, Slave In) pin.
SPI3_MOSI
I/O
MFP5
SPI3 MOSI (Master Out, Slave In) pin.
SC0_CLK
O
MFP6
Smart Card 0 clock pin.
USCI0_CLK
I/O
MFP7
USCI0 clock pin.
I
MFP11
Quadrature encoder 0 phase B input
EPWM0_CH5
I/O
MFP12
EPWM0 channel 5 output/capture input.
BPWM0_CH0
I/O
MFP13
BPWM0 channel 0 output/capture input.
103 VSS
P
MFP0
Ground pin for digital circuit.
104 VDD
P
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
105 PE.1
I/O
MFP0
General purpose digital I/O pin.
EBI_AD10
I/O
MFP2
EBI address/data bus bit 10.
QSPI0_MISO0
I/O
MFP3
Quad SPI0 MISO0 (Master In, Slave Out) pin.
SC2_DAT
I/O
MFP4
Smart Card 2 data pin.
I2S0_BCLK
O
MFP5
I2S0 bit clock output pin.
SPI1_MISO
I/O
MFP6
SPI1 MISO (Master In, Slave Out) pin.
UART3_TXD
O
MFP7
UART3 data transmitter output pin.
I2C1_SCL
I/O
MFP8
I2C1 clock pin.
101 PE.3
QEI0_A
102 PE.2
M480 SERIES DATASHEET
QEI0_B
May 08, 2020
Page 176 of 523
Rev 3.00
M480
48 64 128 Pin Name
Pin Pin Pin
UART4_nCTS
Type
MFP
Description
MFP9
UART4 clear to Send input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD11
I/O
MFP2
EBI address/data bus bit 11.
QSPI0_MOSI0
I/O
MFP3
Quad SPI0 MOSI0 (Master Out, Slave In) pin.
SC2_CLK
O
MFP4
Smart Card 2 clock pin.
I2S0_MCLK
O
MFP5
I2S0 master clock output pin.
SPI1_MOSI
I/O
MFP6
SPI1 MOSI (Master Out, Slave In) pin.
I
MFP7
UART3 data receiver input pin.
I2C1_SDA
I/O
MFP8
I2C1 data input/output pin.
UART4_nRTS
O
MFP9
UART4 request to Send output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD12
I/O
MFP2
EBI address/data bus bit 12.
QSPI0_CLK
I/O
MFP3
Quad SPI0 serial clock pin.
SC2_PWR
O
MFP4
Smart Card 2 power pin.
I2S0_DI
I
MFP5
I2S0 data input pin.
SPI1_CLK
I/O
MFP6
SPI1 serial clock pin.
UART3_nRTS
O
MFP7
UART3 request to Send output pin.
I2C1_SMBAL
O
MFP8
I2C1 SMBus SMBALTER pin
I2C2_SCL
I/O
MFP9
I2C2 clock pin.
UART1_TXD
O
MFP10
UART1 data transmitter output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD13
I/O
MFP2
EBI address/data bus bit 13.
QSPI0_SS
I/O
MFP3
Quad SPI0 slave select pin.
SC2_RST
O
MFP4
Smart Card 2 reset pin.
I2S0_DO
O
MFP5
I2S0 data output pin.
SPI1_SS
I/O
MFP6
SPI1 slave select pin.
UART3_nCTS
I
MFP7
UART3 clear to Send input pin.
I2C1_SMBSUS
O
MFP8
I2C1 SMBus SMBSUS pin (PMBus CONTROL pin)
I2C2_SDA
I/O
MFP9
I2C2 data input/output pin.
I
MFP10
UART1 data receiver input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD14
I/O
MFP2
EBI address/data bus bit 14.
QSPI0_MISO1
I/O
MFP3
Quad SPI0 MISO1 (Master In, Slave Out) pin.
I
MFP4
Smart Card 2 card detect pin.
106 PE.0
UART3_RXD
107 PH.8
108 PH.9
UART1_RXD
109 PH.10
SC2_nCD
May 08, 2020
Page 177 of 523
M480 SERIES DATASHEET
I
Rev 3.00
M480
48 64 128 Pin Name
Pin Pin Pin
Type
MFP
Description
I2S0_LRCK
O
MFP5
I2S0 left right channel clock output pin.
SPI1_I2SMCLK
I/O
MFP6
SPI1 I2S master clock output pin
UART4_TXD
O
MFP7
UART4 data transmitter output pin.
UART0_TXD
O
MFP8
UART0 data transmitter output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD15
I/O
MFP2
EBI address/data bus bit 15.
QSPI0_MOSI1
I/O
MFP3
Quad SPI0 MOSI1 (Master Out, Slave In) pin.
UART4_RXD
I
MFP7
UART4 data receiver input pin.
UART0_RXD
I
MFP8
UART0 data receiver input pin.
EPWM0_CH5
I/O
MFP11
EPWM0 channel 5 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_nCS0
O
MFP2
EBI chip select 0 output pin.
SPI3_I2SMCLK
I/O
MFP3
SPI3 I2S master clock output pin
I
MFP4
Smart Card 1 card detect pin.
I/O
MFP11
EPWM0 channel 4 output/capture input.
110 PH.11
111 PD.14
SC1_nCD
EPWM0_CH4
37
49
112 VSS
P
MFP0
Ground pin for digital circuit.
38
50
113 LDO_CAP
A
MFP0
LDO output pin.
Note: This pin needs to be connected with an external
capacitor.
M480 SERIES DATASHEET
P
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD11
I/O
MFP2
EBI address/data bus bit 11.
SC1_nCD
I
MFP3
Smart Card 1 card detect pin.
SPI0_I2SMCLK
I/O
MFP4
SPI0 I2S master clock output pin
USCI0_CTL0
I/O
MFP5
USCI0 control 0 pin.
QSPI0_CLK
I/O
MFP6
Quad SPI0 serial clock pin.
I
MFP11
EPWM0 counter synchronous trigger input pin.
I/O
MFP13
Timer1 event counter input/toggle output pin.
USB_VBUS_ST
I
MFP14
USB external VBUS regulator status pin.
HSUSB_VBUS_ST
I
MFP15
HSUSB external VBUS regulator status pin.
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC0 channel 15 analog input.
EBI_AD12
I/O
MFP2
EBI address/data bus bit 12.
SC1_PWR
O
MFP3
Smart Card 1 power pin.
39
51
114 VDD
40
52
115 PC.14
EPWM0_SYNC_IN
TM1
41
53
116 PB.15
EADC0_CH15
May 08, 2020
Page 178 of 523
Rev 3.00
M480
48 64 128 Pin Name
Pin Pin Pin
42
54
Description
I/O
MFP4
SPI0 slave select pin.
USCI0_CTL1
I/O
MFP5
USCI0 control 1 pin.
UART0_nCTS
I
MFP6
UART0 clear to Send input pin.
UART3_TXD
O
MFP7
UART3 data transmitter output pin.
I2C2_SMBAL
O
MFP8
I2C2 SMBus SMBALTER pin
EPWM1_CH0
I/O
MFP11
EPWM1 channel 0 output/capture input.
TM0_EXT
I/O
MFP13
Timer0 external capture input/toggle output pin.
USB_VBUS_EN
O
MFP14
USB external VBUS regulator enable pin.
HSUSB_VBUS_EN
O
MFP15
HSUSB external VBUS regulator enable pin.
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC0 channel 14 analog input.
EBI_AD13
I/O
MFP2
EBI address/data bus bit 13.
SC1_RST
O
MFP3
Smart Card 1 reset pin.
SPI0_CLK
I/O
MFP4
SPI0 serial clock pin.
USCI0_DAT1
I/O
MFP5
USCI0 data 1 pin.
UART0_nRTS
O
MFP6
UART0 request to Send output pin.
UART3_RXD
I
MFP7
UART3 data receiver input pin.
I2C2_SMBSUS
O
MFP8
I2C2 SMBus SMBSUS pin (PMBus CONTROL pin)
EPWM1_CH1
I/O
MFP11
EPWM1 channel 1 output/capture input.
TM1_EXT
I/O
MFP13
Timer1 external capture input/toggle output pin.
CLKO
O
MFP14
Clock Out
118 PB.13
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH13
A
MFP1
EADC0 channel 13 analog input.
DAC1_OUT
A
MFP1
DAC1 channel analog output.
ACMP0_P3
A
MFP1
Analog comparator 0 positive input 3 pin.
ACMP1_P3
A
MFP1
Analog comparator 1 positive input 3 pin.
EBI_AD14
I/O
MFP2
EBI address/data bus bit 14.
SC1_DAT
I/O
MFP3
Smart Card 1 data pin.
SPI0_MISO
I/O
MFP4
SPI0 MISO (Master In, Slave Out) pin.
USCI0_DAT0
I/O
MFP5
USCI0 data 0 pin.
UART0_TXD
O
MFP6
UART0 data transmitter output pin.
UART3_nRTS
O
MFP7
UART3 request to Send output pin.
I2C2_SCL
I/O
MFP8
I2C2 clock pin.
EPWM1_CH2
I/O
MFP11
EPWM1 channel 2 output/capture input.
117 PB.14
May 08, 2020
Page 179 of 523
M480 SERIES DATASHEET
55
MFP
SPI0_SS
EADC0_CH14
43
Type
Rev 3.00
M480
48 64 128 Pin Name
Pin Pin Pin
Type
TM2_EXT
I/O
MFP13
Timer2 external capture input/toggle output pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH12
A
MFP1
EADC0 channel 12 analog input.
DAC0_OUT
A
MFP1
DAC0 channel analog output.
ACMP0_P2
A
MFP1
Analog comparator 0 positive input 2 pin.
ACMP1_P2
A
MFP1
Analog comparator 1 positive input 2 pin.
EBI_AD15
I/O
MFP2
EBI address/data bus bit 15.
SC1_CLK
O
MFP3
Smart Card 1 clock pin.
SPI0_MOSI
I/O
MFP4
SPI0 MOSI (Master Out, Slave In) pin.
USCI0_CLK
I/O
MFP5
USCI0 clock pin.
UART0_RXD
I
MFP6
UART0 data receiver input pin.
UART3_nCTS
I
MFP7
UART3 clear to Send input pin.
I2C2_SDA
I/O
MFP8
I2C2 data input/output pin.
SD0_nCD
I
MFP9
SD/SDIO0 card detect input pin
EPWM1_CH3
I/O
MFP11
EPWM1 channel 3 output/capture input.
TM3_EXT
I/O
MFP13
Timer3 external capture input/toggle output pin.
44
45
56
119 PB.12
MFP
Description
57
120 AVDD
P
MFP0
Power supply for internal analog circuit.
58
121 VREF
A
MFP0
ADC reference voltage input.
Note: This pin needs to be connected with a 1uF
capacitor.
M480 SERIES DATASHEET
46
59
122 AVSS
P
MFP0
Ground pin for analog circuit.
60
123 PB.11
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH11
A
MFP1
EADC0 channel 11 analog input.
EBI_ADR16
O
MFP2
EBI address bus bit 16.
UART0_nCTS
I
MFP5
UART0 clear to Send input pin.
UART4_TXD
O
MFP6
UART4 data transmitter output pin.
I2C1_SCL
I/O
MFP7
I2C1 clock pin.
CAN0_TXD
O
MFP8
CAN0 bus transmitter output.
SPI0_I2SMCLK
I/O
MFP9
SPI0 I2S master clock output pin
BPWM1_CH0
I/O
MFP10
BPWM1 channel 0 output/capture input.
SPI3_CLK
I/O
MFP11
SPI3 serial clock pin.
I
MFP14
HSUSB external VBUS regulator status pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH10
A
MFP1
EADC0 channel 10 analog input.
EBI_ADR17
O
MFP2
EBI address bus bit 17.
HSUSB_VBUS_ST
61
124 PB.10
May 08, 2020
Page 180 of 523
Rev 3.00
M480
48 64 128 Pin Name
Pin Pin Pin
62
MFP4
USCI1 control 0 pin.
UART0_nRTS
O
MFP5
UART0 request to Send output pin.
UART4_RXD
I
MFP6
UART4 data receiver input pin.
I2C1_SDA
I/O
MFP7
I2C1 data input/output pin.
CAN0_RXD
I
MFP8
CAN0 bus receiver input.
BPWM1_CH1
I/O
MFP10
BPWM1 channel 1 output/capture input.
SPI3_SS
I/O
MFP11
SPI3 slave select pin.
HSUSB_VBUS_EN
O
MFP14
HSUSB external VBUS regulator enable pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH9
A
MFP1
EADC0 channel 9 analog input.
EBI_ADR18
O
MFP2
EBI address bus bit 18.
USCI1_CTL1
I/O
MFP4
USCI1 control 1 pin.
UART0_TXD
O
MFP5
UART0 data transmitter output pin.
UART1_nCTS
I
MFP6
UART1 clear to Send input pin.
I2C1_SMBAL
O
MFP7
I2C1 SMBus SMBALTER pin
BPWM1_CH2
I/O
MFP10
BPWM1 channel 2 output/capture input.
SPI3_MISO
I/O
MFP11
SPI3 MISO (Master In, Slave Out) pin.
I
MFP13
External interrupt 7 input pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH8
A
MFP1
EADC0 channel 8 analog input.
EBI_ADR19
O
MFP2
EBI address bus bit 19.
USCI1_CLK
I/O
MFP4
USCI1 clock pin.
UART0_RXD
I
MFP5
UART0 data receiver input pin.
UART1_nRTS
O
MFP6
UART1 request to Send output pin.
I2C1_SMBSUS
O
MFP7
I2C1 SMBus SMBSUS pin (PMBus CONTROL pin)
BPWM1_CH3
I/O
MFP10
BPWM1 channel 3 output/capture input.
SPI3_MOSI
I/O
MFP11
SPI3 MOSI (Master Out, Slave In) pin.
I
MFP13
External interrupt 6 input pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH7
A
MFP1
EADC0 channel 7 analog input.
EBI_nWRL
O
MFP2
EBI low byte write enable output pin.
USCI1_DAT0
I/O
MFP4
USCI1 data 0 pin.
CAN1_TXD
O
MFP5
CAN1 bus transmitter output.
UART1_TXD
O
MFP6
UART1 data transmitter output pin.
125 PB.9
126 PB.8
127 PB.7
May 08, 2020
Page 181 of 523
M480 SERIES DATASHEET
64
Description
I/O
INT6
47
MFP
USCI1_CTL0
INT7
63
Type
Rev 3.00
M480
48 64 128 Pin Name
Pin Pin Pin
Type
SD1_CMD
I/O
MFP7
SD/SDIO1 command/response pin
EBI_nCS0
O
MFP8
EBI chip select 0 output pin.
BPWM1_CH4
I/O
MFP10
BPWM1 channel 4 output/capture input.
I
MFP11
EPWM1 Brake 0 input pin.
I/O
MFP12
EPWM1 channel 4 output/capture input.
INT5
I
MFP13
External interrupt 5 input pin.
USB_VBUS_ST
I
MFP14
USB external VBUS regulator status pin.
ACMP0_O
O
MFP15
Analog comparator 0 output pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH6
A
MFP1
EADC0 channel 6 analog input.
EBI_nWRH
O
MFP2
EBI high byte write enable output pin
USCI1_DAT1
I/O
MFP4
USCI1 data 1 pin.
CAN1_RXD
I
MFP5
CAN1 bus receiver input.
UART1_RXD
I
MFP6
UART1 data receiver input pin.
SD1_CLK
O
MFP7
SD/SDIO1 clock output pin
EBI_nCS1
O
MFP8
EBI chip select 1 output pin.
BPWM1_CH5
I/O
MFP10
BPWM1 channel 5 output/capture input.
I
MFP11
EPWM1 Brake 1 input pin.
I/O
MFP12
EPWM1 channel 5 output/capture input.
INT4
I
MFP13
External interrupt 4 input pin.
USB_VBUS_EN
O
MFP14
USB external VBUS regulator enable pin.
ACMP1_O
O
MFP15
Analog comparator 1 output pin.
EPWM1_BRAKE0
EPWM1_CH4
48
1
128 PB.6
EPWM1_BRAKE1
EPWM1_CH5
M480 SERIES DATASHEET
May 08, 2020
MFP
Description
Page 182 of 523
Rev 3.00
M480
4.2.6
M487 Series Pin Description
Note: PA.15 MFP can only be as USB_OTG_ID when enable full-Speed USB.
Type
MFP
Description
2
PB.5
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH5
A
MFP1
EADC0 channel 5 analog input.
ACMP1_N
A
MFP1
Analog comparator 1 negative input pin.
EBI_ADR0
O
MFP2
EBI address bus bit 0.
SD0_DAT3
I/O
MFP3
SD/SDIO0 data line bit 3.
EMAC_RMII_REFCLK
I
MFP4
EMAC RMII reference clock input pin.
SPI1_MISO
I/O
MFP5
SPI1 MISO (Master In, Slave Out) pin.
I2C0_SCL
I/O
MFP6
I2C0 clock pin.
UART5_TXD
O
MFP7
UART5 data transmitter output pin.
USCI1_CTL0
I/O
MFP8
USCI1 control 0 pin.
SC0_CLK
O
MFP9
Smart Card 0 clock pin.
I S0_BCLK
O
MFP10
I2S0 bit clock output pin.
EPWM0_CH0
I/O
MFP11
EPWM0 channel 0 output/capture input.
TM0
I/O
MFP14
Timer0 event counter input/toggle output pin.
INT0
I
MFP15
External interrupt 0 input pin.
PB.4
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH4
A
MFP1
EADC0 channel 4 analog input.
ACMP1_P1
A
MFP1
Analog comparator 1 positive input 1 pin.
EBI_ADR1
O
MFP2
EBI address bus bit 1.
SD0_DAT2
I/O
MFP3
SD/SDIO0 data line bit 2.
EMAC_RMII_RXD0
I
MFP4
EMAC RMII Receive Data bus bit 0.
SPI1_MOSI
I/O
MFP5
SPI1 MOSI (Master Out, Slave In) pin.
I C0_SDA
I/O
MFP6
I2C0 data input/output pin.
UART5_RXD
I
MFP7
UART5 data receiver input pin.
USCI1_CTL1
I/O
MFP8
USCI1 control 1 pin.
SC0_DAT
I/O
MFP9
Smart Card 0 data pin.
I S0_MCLK
O
MFP10
I2S0 master clock output pin.
EPWM0_CH1
I/O
MFP11
EPWM0 channel 1 output/capture input.
TM1
I/O
MFP14
Timer1 event counter input/toggle output pin.
INT1
I
MFP15
External interrupt 1 input pin.
PB.3
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH3
A
MFP1
EADC0 channel 3 analog input.
1
1
2
3
2
2
2
2
4
3
3
May 08, 2020
Page 183 of 523
M480 SERIES DATASHEET
64 128 144 Pin Name
Pin Pin Pin
Rev 3.00
M480
64 128 144 Pin Name
Pin Pin Pin
Type
MFP
Description
ACMP0_N
A
MFP1
Analog comparator 0 negative input pin.
EBI_ADR2
O
MFP2
EBI address bus bit 2.
SD0_DAT1
I/O
MFP3
SD/SDIO0 data line bit 1.
EMAC_RMII_RXD1
I
MFP4
EMAC RMII Receive Data bus bit 1.
SPI1_CLK
I/O
MFP5
SPI1 serial clock pin.
UART1_TXD
O
MFP6
UART1 data transmitter output pin.
UART5_nRTS
O
MFP7
UART5 request to Send output pin.
USCI1_DAT1
I/O
MFP8
USCI1 data 1 pin.
SC0_RST
O
MFP9
Smart Card 0 reset pin.
I S0_DI
I
MFP10
I2S0 data input pin.
EPWM0_CH2
I/O
MFP11
EPWM0 channel 2 output/capture input.
TM2
I/O
MFP14
Timer2 event counter input/toggle output pin.
INT2
I
MFP15
External interrupt 2 input pin.
PB.2
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH2
A
MFP1
EADC0 channel 2 analog input.
ACMP0_P1
A
MFP1
Analog comparator 0 positive input 1 pin.
OPA0_O
A
MFP1
Operational amplifier 0 output pin.
EBI_ADR3
O
MFP2
EBI address bus bit 3.
SD0_DAT0
I/O
MFP3
SD/SDIO0 data line bit 0.
EMAC_RMII_CRSDV
I
MFP4
EMAC RMII Carrier Sense/Receive Data input pin.
SPI1_SS
I/O
MFP5
SPI1 slave select pin.
UART1_RXD
I
MFP6
UART1 data receiver input pin.
UART5_nCTS
I
MFP7
UART5 clear to Send input pin.
USCI1_DAT0
I/O
MFP8
USCI1 data 0 pin.
SC0_PWR
O
MFP9
Smart Card 0 power pin.
I2S0_DO
O
MFP10
I2S0 data output pin.
EPWM0_CH3
I/O
MFP11
EPWM0 channel 3 output/capture input.
TM3
I/O
MFP14
Timer3 event counter input/toggle output pin.
INT3
I
MFP15
External interrupt 3 input pin.
PC.12
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR4
O
MFP2
EBI address bus bit 4.
UART0_TXD
O
MFP3
UART0 data transmitter output pin.
I2C0_SCL
I/O
MFP4
I2C0 clock pin.
SPI3_MISO
I/O
MFP6
SPI3 MISO (Master In, Slave Out) pin.
2
5
4
4
M480 SERIES DATASHEET
5
5
May 08, 2020
Page 184 of 523
Rev 3.00
M480
64 128 144 Pin Name
Pin Pin Pin
6
6
MFP
Description
SC0_nCD
I
MFP9
Smart Card 0 card detect pin.
ECAP1_IC2
I
MFP11
Enhanced capture unit 1 input 2 pin.
EPWM1_CH0
I/O
MFP12
EPWM1 channel 0 output/capture input.
ACMP0_O
O
MFP14
Analog comparator 0 output pin.
PC.11
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR5
O
MFP2
EBI address bus bit 5.
UART0_RXD
I
MFP3
UART0 data receiver input pin.
I C0_SDA
I/O
MFP4
I2C0 data input/output pin.
SPI3_MOSI
I/O
MFP6
SPI3 MOSI (Master Out, Slave In) pin.
ECAP1_IC1
I
MFP11
Enhanced capture unit 1 input 1 pin.
EPWM1_CH1
I/O
MFP12
EPWM1 channel 1 output/capture input.
ACMP1_O
O
MFP14
Analog comparator 1 output pin.
PC.10
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR6
O
MFP2
EBI address bus bit 6.
SPI3_CLK
I/O
MFP6
SPI3 serial clock pin.
UART3_TXD
O
MFP7
UART3 data transmitter output pin.
CAN1_TXD
O
MFP9
CAN1 bus transmitter output.
ECAP1_IC0
I
MFP11
Enhanced capture unit 1 input 0 pin.
EPWM1_CH2
I/O
MFP12
EPWM1 channel 2 output/capture input.
PC.9
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR7
O
MFP2
EBI address bus bit 7.
SPI3_SS
I/O
MFP6
SPI3 slave select pin.
UART3_RXD
I
MFP7
UART3 data receiver input pin.
CAN1_RXD
I
MFP9
CAN1 bus receiver input.
EPWM1_CH3
I/O
MFP12
EPWM1 channel 3 output/capture input.
PB.1
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH1
A
MFP1
EADC0 channel 1 analog input.
OPA0_N
A
MFP1
Operational amplifier 0 negative input pin.
EBI_ADR8
O
MFP2
EBI address bus bit 8.
SD0_CLK
O
MFP3
SD/SDIO0 clock output pin
EMAC_RMII_RXERR
I
MFP4
EMAC RMII Receive Data Error input pin.
SPI1_I2SMCLK
I/O
MFP5
SPI1 I2S master clock output pin
SPI3_I2SMCLK
I/O
MFP6
SPI3 I2S master clock output pin
UART2_TXD
O
MFP7
UART2 data transmitter output pin.
2
7
8
6
9
7
8
9
May 08, 2020
Page 185 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
64 128 144 Pin Name
Pin Pin Pin
7
M480 SERIES DATASHEET
8
9
10
10
Type
MFP
Description
USCI1_CLK
I/O
MFP8
USCI1 clock pin.
I2C1_SCL
I/O
MFP9
I2C1 clock pin.
I2S0_LRCK
O
MFP10
I2S0 left right channel clock output pin.
EPWM0_CH4
I/O
MFP11
EPWM0 channel 4 output/capture input.
EPWM1_CH4
I/O
MFP12
EPWM1 channel 4 output/capture input.
EPWM0_BRAKE0
I
MFP13
EPWM0 Brake 0 input pin.
PB.0
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH0
A
MFP1
EADC0 channel 0 analog input.
OPA0_P
A
MFP1
Operational amplifier 0 positive input pin.
EBI_ADR9
O
MFP2
EBI address bus bit 9.
SD0_CMD
I/O
MFP3
SD/SDIO0 command/response pin
UART2_RXD
I
MFP7
UART2 data receiver input pin.
SPI0_I2SMCLK
I/O
MFP8
SPI0 I2S master clock output pin
I2C1_SDA
I/O
MFP9
I2C1 data input/output pin.
EPWM0_CH5
I/O
MFP11
EPWM0 channel 5 output/capture input.
EPWM1_CH5
I/O
MFP12
EPWM1 channel 5 output/capture input.
EPWM0_BRAKE1
I
MFP13
EPWM0 Brake 1 input pin.
11
11
VSS
P
MFP0
Ground pin for digital circuit.
12
12
VDD
P
MFP0
Power supply for I/O ports and LDO source for internal PLL
and digital circuit.
13
13
PA.11
I/O
MFP0
General purpose digital I/O pin.
ACMP0_P0
A
MFP1
Analog comparator 0 positive input 0 pin.
EBI_nRD
O
MFP2
EBI read enable output pin.
SC2_PWR
O
MFP3
Smart Card 2 power pin.
SPI2_SS
I/O
MFP4
SPI2 slave select pin.
SD1_DAT3
I/O
MFP5
SD/SDIO1 data line bit 3.
USCI0_CLK
I/O
MFP6
USCI0 clock pin.
I2C2_SCL
I/O
MFP7
I2C2 clock pin.
BPWM0_CH0
I/O
MFP9
BPWM0 channel 0 output/capture input.
EPWM0_SYNC_OUT
O
MFP10
EPWM0 counter synchronous trigger output pin.
TM0_EXT
I/O
MFP13
Timer0 event counter input/toggle output pin.
DAC1_ST
I
MFP14
DAC1 external trigger input.
PA.10
I/O
MFP0
General purpose digital I/O pin.
ACMP1_P0
A
MFP1
Analog comparator 1 positive input 0 pin.
14
14
May 08, 2020
Page 186 of 523
Rev 3.00
M480
64 128 144 Pin Name
Pin Pin Pin
10
16
15
16
MFP
Description
OPA1_O
A
MFP1
Operational amplifier 1 output pin.
EBI_nWR
O
MFP2
EBI write enable output pin.
SC2_RST
O
MFP3
Smart Card 2 reset pin.
SPI2_CLK
I/O
MFP4
SPI2 serial clock pin.
SD1_DAT2
I/O
MFP5
SD/SDIO1 data line bit 2.
USCI0_DAT0
I/O
MFP6
USCI0 data 0 pin.
I2C2_SDA
I/O
MFP7
I2C2 data input/output pin.
BPWM0_CH1
I/O
MFP9
BPWM0 channel 1 output/capture input.
QEI1_INDEX
I
MFP10
Quadrature encoder 1 index input
ECAP0_IC0
I
MFP11
Enhanced capture unit 0 input 0 pin.
TM1_EXT
I/O
MFP13
Timer1 event counter input/toggle output pin.
DAC0_ST
I
MFP14
DAC0 external trigger input.
SWDH_CLK
O
MFP15
Serial Wire Debug Host Clock output
PA.9
I/O
MFP0
General purpose digital I/O pin.
OPA1_N
A
MFP1
Operational amplifier 1 negative input pin.
EBI_MCLK
O
MFP2
EBI external clock output pin.
SC2_DAT
I/O
MFP3
Smart Card 2 data pin.
SPI2_MISO
I/O
MFP4
SPI2 MISO (Master In, Slave Out) pin.
SD1_DAT1
I/O
MFP5
SD/SDIO1 data line bit 1.
USCI0_DAT1
I/O
MFP6
USCI0 data 1 pin.
UART1_TXD
O
MFP7
UART1 data transmitter output pin.
BPWM0_CH2
I/O
MFP9
BPWM0 channel 2 output/capture input.
QEI1_A
I
MFP10
Quadrature encoder 1 phase A input
ECAP0_IC1
I
MFP11
Enhanced capture unit 0 input 1 pin.
TM2_EXT
I/O
MFP13
Timer2 event counter input/toggle output pin.
SWDH_DAT
I/O
MFP15
Serial Wire Debug Host Data input/output pin
PA.8
I/O
MFP0
General purpose digital I/O pin.
OPA1_P
A
MFP1
Operational amplifier 1 positive input pin.
EBI_ALE
O
MFP2
EBI address latch enable output pin.
SC2_CLK
O
MFP3
Smart Card 2 clock pin.
SPI2_MOSI
I/O
MFP4
SPI2 MOSI (Master Out, Slave In) pin.
SD1_DAT0
I/O
MFP5
SD/SDIO1 data line bit 0.
USCI0_CTL1
I/O
MFP6
USCI0 control 1 pin.
UART1_RXD
I
MFP7
UART1 data receiver input pin.
May 08, 2020
Page 187 of 523
M480 SERIES DATASHEET
11
15
Type
Rev 3.00
M480
64 128 144 Pin Name
Pin Pin Pin
17
18
M480 SERIES DATASHEET
19
20
17
18
19
20
Type
MFP
Description
BPWM0_CH3
I/O
MFP9
BPWM0 channel 3 output/capture input.
QEI1_B
I
MFP10
Quadrature encoder 1 phase B input
ECAP0_IC2
I
MFP11
Enhanced capture unit 0 input 2 pin.
TM3_EXT
I/O
MFP13
Timer3 event counter input/toggle output pin.
INT4
I
MFP15
External interrupt 4 input pin.
PC.13
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR10
O
MFP2
EBI address bus bit 10.
SC2_nCD
I
MFP3
Smart Card 2 card detect pin.
SPI2_I2SMCLK
I/O
MFP4
SPI2 I2S master clock output pin
CAN1_TXD
O
MFP5
CAN1 bus transmitter output.
USCI0_CTL0
I/O
MFP6
USCI0 control 0 pin.
UART2_TXD
O
MFP7
UART2 data transmitter output pin.
BPWM0_CH4
I/O
MFP9
BPWM0 channel 4 output/capture input.
CLKO
O
MFP13
Clock Out
EADC0_ST
I
MFP14
EADC0 external trigger input.
PD.12
I/O
MFP0
General purpose digital I/O pin.
OPA2_O
A
MFP1
Operational amplifier 2 output pin.
EBI_nCS0
O
MFP2
EBI chip select 0 output pin.
CAN1_RXD
I
MFP5
CAN1 bus receiver input.
UART2_RXD
I
MFP7
UART2 data receiver input pin.
BPWM0_CH5
I/O
MFP9
BPWM0 channel 5 output/capture input.
QEI0_INDEX
I
MFP10
Quadrature encoder 0 index input
CLKO
O
MFP13
Clock Out
EADC0_ST
I
MFP14
EADC0 external trigger input.
INT5
I
MFP15
External interrupt 5 input pin.
PD.11
I/O
MFP0
General purpose digital I/O pin.
OPA2_N
A
MFP1
Operational amplifier 2 negative input pin.
EBI_nCS1
O
MFP2
EBI chip select 1 output pin.
UART1_TXD
O
MFP3
UART1 data transmitter output pin.
CAN0_TXD
O
MFP4
CAN0 bus transmitter output.
QEI0_A
I
MFP10
Quadrature encoder 0 phase A input
INT6
I
MFP15
External interrupt 6 input pin.
PD.10
I/O
MFP0
General purpose digital I/O pin.
OPA2_P
A
MFP1
Operational amplifier 2 positive input pin.
May 08, 2020
Page 188 of 523
Rev 3.00
M480
64 128 144 Pin Name
Pin Pin Pin
MFP
Description
EBI_nCS2
O
MFP2
EBI chip select 2 output pin.
UART1_RXD
I
MFP3
UART1 data receiver input pin.
CAN0_RXD
I
MFP4
CAN0 bus receiver input.
QEI0_B
I
MFP10
Quadrature encoder 0 phase B input
INT7
I
MFP15
External interrupt 7 input pin.
21
VSS
P
MFP0
Ground pin for digital circuit.
22
VDD
P
MFP0
Power supply for I/O ports and LDO source for internal PLL
and digital circuit.
23
PG.0
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR8
O
MFP2
EBI address bus bit 8.
I2C0_SCL
I/O
MFP4
I2C0 clock pin.
I2C1_SMBAL
O
MFP5
I2C1 SMBus SMBALTER pin
UART2_RXD
I
MFP6
UART2 data receiver input pin.
CAN1_TXD
O
MFP7
CAN1 bus transmitter output.
UART1_TXD
O
MFP8
UART1 data transmitter output pin.
PG.1
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR9
O
MFP2
EBI address bus bit 9.
SPI2_I2SMCLK
I/O
MFP3
SPI2 I2S master clock output pin
I2C0_SDA
I/O
MFP4
I2C0 data input/output pin.
I2C1_SMBSUS
O
MFP5
I2C1 SMBus SMBSUS pin (PMBus CONTROL pin)
UART2_TXD
O
MFP6
UART2 data transmitter output pin.
CAN1_RXD
I
MFP7
CAN1 bus receiver input.
UART1_RXD
I
MFP8
UART1 data receiver input pin.
PG.2
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR11
O
MFP2
EBI address bus bit 11.
SPI2_SS
I/O
MFP3
SPI2 slave select pin.
I C0_SMBAL
O
MFP4
I2C0 SMBus SMBALTER pin
I2C1_SCL
I/O
MFP5
I2C1 clock pin.
TM0
I/O
MFP13
Timer0 event counter input/toggle output pin.
PG.3
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR12
O
MFP2
EBI address bus bit 12.
SPI2_CLK
I/O
MFP3
SPI2 serial clock pin.
I2C0_SMBSUS
O
MFP4
I2C0 SMBus SMBSUS pin (PMBus CONTROL pin)
I2C1_SDA
I/O
MFP5
I2C1 data input/output pin.
24
21
25
2
22
26
May 08, 2020
Page 189 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
64 128 144 Pin Name
Pin Pin Pin
23
24
25
27
28
29
Type
MFP
Description
TM1
I/O
MFP13
Timer1 event counter input/toggle output pin.
PG.4
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR13
O
MFP2
EBI address bus bit 13.
SPI2_MISO
I/O
MFP3
SPI2 MISO (Master In, Slave Out) pin.
TM2
I/O
MFP13
Timer2 event counter input/toggle output pin.
PF.11
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR14
O
MFP2
EBI address bus bit 14.
SPI2_MOSI
I/O
MFP3
SPI2 MOSI (Master Out, Slave In) pin.
TAMPER5
I/O
MFP10
TAMPER detector loop pin 5.
TM3
I/O
MFP13
Timer3 event counter input/toggle output pin.
PF.10
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR15
O
MFP2
EBI address bus bit 15.
SC0_nCD
I
MFP3
Smart Card 0 card detect pin.
I S0_BCLK
O
MFP4
I2S0 bit clock output pin.
SPI0_I2SMCLK
I/O
MFP5
SPI0 I2S master clock output pin
TAMPER4
I/O
MFP10
TAMPER detector loop pin 4.
PF.9
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR16
O
MFP2
EBI address bus bit 16.
SC0_PWR
O
MFP3
Smart Card 0 power pin.
I2S0_MCLK
O
MFP4
I2S0 master clock output pin.
SPI0_SS
I/O
MFP5
SPI0 slave select pin.
TAMPER3
I/O
MFP10
TAMPER detector loop pin 3.
PF.8
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR17
O
MFP2
EBI address bus bit 17.
SC0_RST
O
MFP3
Smart Card 0 reset pin.
I2S0_DI
I
MFP4
I2S0 data input pin.
SPI0_CLK
I/O
MFP5
SPI0 serial clock pin.
TAMPER2
I/O
MFP10
TAMPER detector loop pin 2.
PF.7
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR18
O
MFP2
EBI address bus bit 18.
SC0_DAT
I/O
MFP3
Smart Card 0 data pin.
I S0_DO
O
MFP4
I2S0 data output pin.
SPI0_MISO
I/O
MFP5
SPI0 MISO (Master In, Slave Out) pin.
UART4_TXD
O
MFP6
UART4 data transmitter output pin.
2
26
M480 SERIES DATASHEET
27
28
30
31
32
2
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Rev 3.00
M480
64 128 144 Pin Name
Pin Pin Pin
12
29
33
Type
MFP
Description
TAMPER1
I/O
MFP10
TAMPER detector loop pin 1.
PF.6
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR19
O
MFP2
EBI address bus bit 19.
SC0_CLK
O
MFP3
Smart Card 0 clock pin.
I S0_LRCK
O
MFP4
I2S0 left right channel clock output pin.
SPI0_MOSI
I/O
MFP5
SPI0 MOSI (Master Out, Slave In) pin.
UART4_RXD
I
MFP6
UART4 data receiver input pin.
EBI_nCS0
O
MFP7
EBI chip select 0 output pin.
TAMPER0
I/O
MFP10
TAMPER detector loop pin 0.
2
30
34
VDD
P
MFP0
Power supply for I/O ports and LDO source for internal PLL
and digital circuit.
14
31
35
PF.5
I/O
MFP0
General purpose digital I/O pin.
UART2_RXD
I
MFP2
UART2 data receiver input pin.
UART2_nCTS
I
MFP4
UART2 clear to Send input pin.
BPWM0_CH4
I/O
MFP8
BPWM0 channel 4 output/capture input.
EPWM0_SYNC_OUT
O
MFP9
EPWM0 counter synchronous trigger output pin.
X32_IN
I
MFP10
External 32.768 kHz crystal input pin.
EADC0_ST
I
MFP11
EADC0 external trigger input.
PF.4
I/O
MFP0
General purpose digital I/O pin.
UART2_TXD
O
MFP2
UART2 data transmitter output pin.
UART2_nRTS
O
MFP4
UART2 request to Send output pin.
BPWM0_CH5
I/O
MFP8
BPWM0 channel 5 output/capture input.
X32_OUT
O
MFP10
External 32.768 kHz crystal output pin.
PH.0
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR7
O
MFP2
EBI address bus bit 7.
UART5_TXD
O
MFP4
UART5 data transmitter output pin.
TM0_EXT
I/O
MFP13
Timer0 event counter input/toggle output pin.
PH.1
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR6
O
MFP2
EBI address bus bit 6.
UART5_RXD
I
MFP4
UART5 data receiver input pin.
TM1_EXT
I/O
MFP13
Timer1 event counter input/toggle output pin.
PH.2
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR5
O
MFP2
EBI address bus bit 5.
UART5_nRTS
O
MFP4
UART5 request to Send output pin.
15
32
36
37
38
39
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M480 SERIES DATASHEET
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Rev 3.00
M480
64 128 144 Pin Name
Pin Pin Pin
40
33
34
35
M480 SERIES DATASHEET
36
16
17
37
38
41
42
43
44
45
46
Type
MFP
Description
UART4_TXD
O
MFP5
UART4 data transmitter output pin.
I2C0_SCL
I/O
MFP6
I2C0 clock pin.
TM2_EXT
I/O
MFP13
Timer2 event counter input/toggle output pin.
PH.3
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR4
O
MFP2
EBI address bus bit 4.
SPI1_I2SMCLK
I/O
MFP3
SPI1 I2S master clock output pin
UART5_nCTS
I
MFP4
UART5 clear to Send input pin.
UART4_RXD
I
MFP5
UART4 data receiver input pin.
I2C0_SDA
I/O
MFP6
I2C0 data input/output pin.
TM3_EXT
I/O
MFP13
Timer3 event counter input/toggle output pin.
PH.4
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR3
O
MFP2
EBI address bus bit 3.
SPI1_MISO
I/O
MFP3
SPI1 MISO (Master In, Slave Out) pin.
PH.5
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR2
O
MFP2
EBI address bus bit 2.
SPI1_MOSI
I/O
MFP3
SPI1 MOSI (Master Out, Slave In) pin.
PH.6
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR1
O
MFP2
EBI address bus bit 1.
SPI1_CLK
I/O
MFP3
SPI1 serial clock pin.
PH.7
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR0
O
MFP2
EBI address bus bit 0.
SPI1_SS
I/O
MFP3
SPI1 slave select pin.
PF.3
I/O
MFP0
General purpose digital I/O pin.
EBI_nCS0
O
MFP2
EBI chip select 0 output pin.
UART0_TXD
O
MFP3
UART0 data transmitter output pin.
I2C0_SCL
I/O
MFP4
I2C0 clock pin.
XT1_IN
I
MFP10
External 4~24 MHz (high speed) crystal input pin.
BPWM1_CH0
I/O
MFP11
BPWM1 channel 0 output/capture input.
PF.2
I/O
MFP0
General purpose digital I/O pin.
EBI_nCS1
O
MFP2
EBI chip select 1 output pin.
UART0_RXD
I
MFP3
UART0 data receiver input pin.
I C0_SDA
I/O
MFP4
I2C0 data input/output pin.
QSPI0_CLK
I/O
MFP5
QSPI0 serial clock pin.
XT1_OUT
O
MFP10
External 4~24 MHz (high speed) crystal output pin.
2
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Rev 3.00
M480
64 128 144 Pin Name
Pin Pin Pin
Type
MFP
Description
BPWM1_CH1
I/O
MFP11
BPWM1 channel 1 output/capture input.
47
VSS
P
MFP0
Ground pin for digital circuit.
40
48
VDD
P
MFP0
Power supply for I/O ports and LDO source for internal PLL
and digital circuit.
41
49
PE.8
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR10
O
MFP2
EBI address bus bit 10.
EMAC_RMII_MDC
O
MFP3
EMAC RMII PHY Management Clock output pin.
I2S0_BCLK
O
MFP4
I2S0 bit clock output pin.
SPI2_CLK
I/O
MFP5
SPI2 serial clock pin.
USCI1_CTL1
I/O
MFP6
USCI1 control 1 pin.
UART2_TXD
O
MFP7
UART2 data transmitter output pin.
EPWM0_CH0
I/O
MFP10
EPWM0 channel 0 output/capture input.
EPWM0_BRAKE0
I
MFP11
EPWM0 Brake 0 input pin.
ECAP0_IC0
I
MFP12
Enhanced capture unit 0 input 0 pin.
TRACE_CLK
O
MFP14
ETM Trace Clock output pin
PE.9
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR11
O
MFP2
EBI address bus bit 11.
EMAC_RMII_MDIO
I/O
MFP3
EMAC RMII PHY Management Data pin.
I2S0_MCLK
O
MFP4
I2S0 master clock output pin.
SPI2_MISO
I/O
MFP5
SPI2 MISO (Master In, Slave Out) pin.
USCI1_CTL0
I/O
MFP6
USCI1 control 0 pin.
UART2_RXD
I
MFP7
UART2 data receiver input pin.
EPWM0_CH1
I/O
MFP10
EPWM0 channel 1 output/capture input.
EPWM0_BRAKE1
I
MFP11
EPWM0 Brake 1 input pin.
ECAP0_IC1
I
MFP12
Enhanced capture unit 0 input 1 pin.
TRACE_DATA0
O
MFP14
ETM Trace Data 0 output pin
PE.10
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR12
O
MFP2
EBI address bus bit 12.
EMAC_RMII_TXD0
O
MFP3
EMAC RMII Transmit Data bus bit 0.
I2S0_DI
I
MFP4
I2S0 data input pin.
SPI2_MOSI
I/O
MFP5
SPI2 MOSI (Master Out, Slave In) pin.
USCI1_DAT0
I/O
MFP6
USCI1 data 0 pin.
UART3_TXD
O
MFP7
UART3 data transmitter output pin.
EPWM0_CH2
I/O
MFP10
EPWM0 channel 2 output/capture input.
42
43
50
51
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M480 SERIES DATASHEET
39
Rev 3.00
M480
64 128 144 Pin Name
Pin Pin Pin
44
45
52
53
Type
MFP
Description
EPWM1_BRAKE0
I
MFP11
EPWM1 Brake 0 input pin.
ECAP0_IC2
I
MFP12
Enhanced capture unit 0 input 2 pin.
TRACE_DATA1
O
MFP14
ETM Trace Data 1 output pin
PE.11
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR13
O
MFP2
EBI address bus bit 13.
EMAC_RMII_TXD1
O
MFP3
EMAC RMII Transmit Data bus bit 1.
I2S0_DO
O
MFP4
I2S0 data output pin.
SPI2_SS
I/O
MFP5
SPI2 slave select pin.
USCI1_DAT1
I/O
MFP6
USCI1 data 1 pin.
UART3_RXD
I
MFP7
UART3 data receiver input pin.
UART1_nCTS
I
MFP8
UART1 clear to Send input pin.
EPWM0_CH3
I/O
MFP10
EPWM0 channel 3 output/capture input.
EPWM1_BRAKE1
I
MFP11
EPWM1 Brake 1 input pin.
ECAP1_IC2
I
MFP13
Enhanced capture unit 1 input 2 pin.
TRACE_DATA2
O
MFP14
ETM Trace Data 2 output pin
PE.12
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR14
O
MFP2
EBI address bus bit 14.
EMAC_RMII_TXEN
O
MFP3
EMAC RMII Transmit Enable output pin.
I S0_LRCK
O
MFP4
I2S0 left right channel clock output pin.
SPI2_I2SMCLK
I/O
MFP5
SPI2 I2S master clock output pin
USCI1_CLK
I/O
MFP6
USCI1 clock pin.
UART1_nRTS
O
MFP8
UART1 request to Send output pin.
EPWM0_CH4
I/O
MFP10
EPWM0 channel 4 output/capture input.
ECAP1_IC1
I
MFP13
Enhanced capture unit 1 input 1 pin.
TRACE_DATA3
O
MFP14
ETM Trace Data 3 output pin
PE.13
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR15
O
MFP2
EBI address bus bit 15.
EMAC_PPS
O
MFP3
EMAC Pulse Per Second output pin.
I2C0_SCL
I/O
MFP4
I2C0 clock pin.
UART4_nRTS
O
MFP5
UART4 request to Send output pin.
UART1_TXD
O
MFP8
UART1 data transmitter output pin.
EPWM0_CH5
I/O
MFP10
EPWM0 channel 5 output/capture input.
EPWM1_CH0
I/O
MFP11
EPWM1 channel 0 output/capture input.
BPWM1_CH5
I/O
MFP12
BPWM1 channel 5 output/capture input.
2
M480 SERIES DATASHEET
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54
May 08, 2020
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Rev 3.00
M480
64 128 144 Pin Name
Pin Pin Pin
47
55
MFP
Description
ECAP1_IC0
I
MFP13
Enhanced capture unit 1 input 0 pin.
PC.8
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR16
O
MFP2
EBI address bus bit 16.
EMAC_RMII_REFCLK
I
MFP3
EMAC RMII reference clock input pin.
I C0_SDA
I/O
MFP4
I2C0 data input/output pin.
UART4_nCTS
I
MFP5
UART4 clear to Send input pin.
UART1_RXD
I
MFP8
UART1 data receiver input pin.
EPWM1_CH1
I/O
MFP11
EPWM1 channel 1 output/capture input.
BPWM1_CH4
I/O
MFP12
BPWM1 channel 4 output/capture input.
PC.7
I/O
MFP0
General purpose digital I/O pin.
EBI_AD9
I/O
MFP2
EBI address/data bus bit 9.
EMAC_RMII_RXD0
I
MFP3
EMAC RMII Receive Data bus bit 0.
SPI1_MISO
I/O
MFP4
SPI1 MISO (Master In, Slave Out) pin.
UART4_TXD
O
MFP5
UART4 data transmitter output pin.
SC2_PWR
O
MFP6
Smart Card 2 power pin.
UART0_nCTS
I
MFP7
UART0 clear to Send input pin.
I C1_SMBAL
O
MFP8
I2C1 SMBus SMBALTER pin
EPWM1_CH2
I/O
MFP11
EPWM1 channel 2 output/capture input.
BPWM1_CH0
I/O
MFP12
BPWM1 channel 0 output/capture input.
TM0
I/O
MFP14
Timer0 event counter input/toggle output pin.
INT3
I
MFP15
External interrupt 3 input pin.
PC.6
I/O
MFP0
General purpose digital I/O pin.
EBI_AD8
I/O
MFP2
EBI address/data bus bit 8.
EMAC_RMII_RXD1
I
MFP3
EMAC RMII Receive Data bus bit 1.
SPI1_MOSI
I/O
MFP4
SPI1 MOSI (Master Out, Slave In) pin.
UART4_RXD
I
MFP5
UART4 data receiver input pin.
SC2_RST
O
MFP6
Smart Card 2 reset pin.
UART0_nRTS
O
MFP7
UART0 request to Send output pin.
I2C1_SMBSUS
O
MFP8
I2C1 SMBus SMBSUS pin (PMBus CONTROL pin)
EPWM1_CH3
I/O
MFP11
EPWM1 channel 3 output/capture input.
BPWM1_CH1
I/O
MFP12
BPWM1 channel 1 output/capture input.
TM1
I/O
MFP14
Timer1 event counter input/toggle output pin.
INT2
I
MFP15
External interrupt 2 input pin.
PA.7
I/O
MFP0
General purpose digital I/O pin.
2
18
48
56
2
19
20
49
50
57
58
May 08, 2020
Page 195 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
64 128 144 Pin Name
Pin Pin Pin
21
51
59
Type
MFP
Description
EBI_AD7
I/O
MFP2
EBI address/data bus bit 7.
EMAC_RMII_CRSDV
I
MFP3
EMAC RMII Carrier Sense/Receive Data input pin.
SPI1_CLK
I/O
MFP4
SPI1 serial clock pin.
SC2_DAT
I/O
MFP6
Smart Card 2 data pin.
UART0_TXD
O
MFP7
UART0 data transmitter output pin.
I2C1_SCL
I/O
MFP8
I2C1 clock pin.
EPWM1_CH4
I/O
MFP11
EPWM1 channel 4 output/capture input.
BPWM1_CH2
I/O
MFP12
BPWM1 channel 2 output/capture input.
ACMP0_WLAT
I
MFP13
Analog comparator 0 window latch input pin
TM2
I/O
MFP14
Timer2 event counter input/toggle output pin.
INT1
I
MFP15
External interrupt 1 input pin.
PA.6
I/O
MFP0
General purpose digital I/O pin.
EBI_AD6
I/O
MFP2
EBI address/data bus bit 6.
EMAC_RMII_RXERR
I
MFP3
EMAC RMII Receive Data Error input pin.
SPI1_SS
I/O
MFP4
SPI1 slave select pin.
SD1_nCD
I
MFP5
SD/SDIO1 card detect input pin
SC2_CLK
O
MFP6
Smart Card 2 clock pin.
UART0_RXD
I
MFP7
UART0 data receiver input pin.
I C1_SDA
I/O
MFP8
I2C1 data input/output pin.
EPWM1_CH5
I/O
MFP11
EPWM1 channel 5 output/capture input.
BPWM1_CH3
I/O
MFP12
BPWM1 channel 3 output/capture input.
ACMP1_WLAT
I
MFP13
Analog comparator 1 window latch input pin
TM3
I/O
MFP14
Timer3 event counter input/toggle output pin.
INT0
I
MFP15
External interrupt 0 input pin.
2
M480 SERIES DATASHEET
22
52
60
VSS
P
MFP0
Ground pin for digital circuit.
23
53
61
VDD
P
MFP0
Power supply for I/O ports and LDO source for internal PLL
and digital circuit.
24
54
62
LDO_CAP
A
MFP0
LDO output pin.
Note: This pin needs to be connected with an external
capacitor.
25
55
63
PA.5
I/O
MFP0
General purpose digital I/O pin.
SPIM_D2
I/O
MFP2
SPIM data 2 pin for Quad Mode I/O.
QSPI0_MISO1
I/O
MFP3
QSPI0 MISO1 (Master In, Slave Out) pin.
SPI1_I2SMCLK
I/O
MFP4
SPI1 I2S master clock output pin
SD1_CMD
I/O
MFP5
SD/SDIO1 command/response pin
May 08, 2020
Page 196 of 523
Rev 3.00
M480
64 128 144 Pin Name
Pin Pin Pin
26
56
64
MFP
Description
SC2_nCD
I
MFP6
Smart Card 2 card detect pin.
UART0_nCTS
I
MFP7
UART0 clear to Send input pin.
UART5_TXD
O
MFP8
UART5 data transmitter output pin.
I2C0_SCL
I/O
MFP9
I2C0 clock pin.
CAN0_TXD
O
MFP10
CAN0 bus transmitter output.
BPWM0_CH5
I/O
MFP12
BPWM0 channel 5 output/capture input.
EPWM0_CH0
I/O
MFP13
EPWM0 channel 0 output/capture input.
QEI0_INDEX
I
MFP14
Quadrature encoder 0 index input
PA.4
I/O
MFP0
General purpose digital I/O pin.
SPIM_D3
I/O
MFP2
SPIM data 3 pin for Quad Mode I/O.
QSPI0_MOSI1
I/O
MFP3
QSPI0 MOSI1 (Master Out, Slave In) pin.
SPI0_I2SMCLK
I/O
MFP4
SPI0 I2S master clock output pin
SD1_CLK
O
MFP5
SD/SDIO1 clock output pin
SC0_nCD
I
MFP6
Smart Card 0 card detect pin.
UART0_nRTS
O
MFP7
UART0 request to Send output pin.
UART5_RXD
I
MFP8
UART5 data receiver input pin.
I C0_SDA
I/O
MFP9
I2C0 data input/output pin.
CAN0_RXD
I
MFP10
CAN0 bus receiver input.
BPWM0_CH4
I/O
MFP12
BPWM0 channel 4 output/capture input.
EPWM0_CH1
I/O
MFP13
EPWM0 channel 1 output/capture input.
QEI0_A
I
MFP14
Quadrature encoder 0 phase A input
PA.3
I/O
MFP0
General purpose digital I/O pin.
SPIM_SS
I/O
MFP2
SPIM slave select pin.
QSPI0_SS
I/O
MFP3
QSPI0 slave select pin.
SPI0_SS
I/O
MFP4
SPI0 slave select pin.
SD1_DAT3
I/O
MFP5
SD/SDIO1 data line bit 3.
SC0_PWR
O
MFP6
Smart Card 0 power pin.
UART4_TXD
O
MFP7
UART4 data transmitter output pin.
UART1_TXD
O
MFP8
UART1 data transmitter output pin.
I C1_SCL
I/O
MFP9
I2C1 clock pin.
BPWM0_CH3
I/O
MFP12
BPWM0 channel 3 output/capture input.
EPWM0_CH2
I/O
MFP13
EPWM0 channel 2 output/capture input.
QEI0_B
I
MFP14
Quadrature encoder 0 phase B input
PA.2
I/O
MFP0
General purpose digital I/O pin.
2
27
57
65
2
28
58
66
May 08, 2020
Page 197 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
64 128 144 Pin Name
Pin Pin Pin
Type
MFP
Description
SPIM_CLK
I/O
MFP2
SPIM serial clock pin.
QSPI0_CLK
I/O
MFP3
QSPI0 serial clock pin.
SPI0_CLK
I/O
MFP4
SPI0 serial clock pin.
SD1_DAT2
I/O
MFP5
SD/SDIO1 data line bit 2.
SC0_RST
O
MFP6
Smart Card 0 reset pin.
UART4_RXD
I
MFP7
UART4 data receiver input pin.
UART1_RXD
I
MFP8
UART1 data receiver input pin.
I C1_SDA
I/O
MFP9
I2C1 data input/output pin.
BPWM0_CH2
I/O
MFP12
BPWM0 channel 2 output/capture input.
EPWM0_CH3
I/O
MFP13
EPWM0 channel 3 output/capture input.
PA.1
I/O
MFP0
General purpose digital I/O pin.
SPIM_MISO
I/O
MFP2
SPIM MISO (Master In, Slave Out) pin.
QSPI0_MISO0
I/O
MFP3
QSPI0 MISO0 (Master In, Slave Out) pin.
SPI0_MISO
I/O
MFP4
SPI0 MISO (Master In, Slave Out) pin.
SD1_DAT1
I/O
MFP5
SD/SDIO1 data line bit 1.
SC0_DAT
I/O
MFP6
Smart Card 0 data pin.
UART0_TXD
O
MFP7
UART0 data transmitter output pin.
UART1_nCTS
I
MFP8
UART1 clear to Send input pin.
I C2_SCL
I/O
MFP9
I2C2 clock pin.
BPWM0_CH1
I/O
MFP12
BPWM0 channel 1 output/capture input.
EPWM0_CH4
I/O
MFP13
EPWM0 channel 4 output/capture input.
DAC1_ST
I
MFP15
DAC1 external trigger input.
PA.0
I/O
MFP0
General purpose digital I/O pin.
SPIM_MOSI
I/O
MFP2
SPIM MOSI (Master Out, Slave In) pin.
QSPI0_MOSI0
I/O
MFP3
QSPI0 MOSI0 (Master Out, Slave In) pin.
SPI0_MOSI
I/O
MFP4
SPI0 MOSI (Master Out, Slave In) pin.
SD1_DAT0
I/O
MFP5
SD/SDIO1 data line bit 0.
SC0_CLK
O
MFP6
Smart Card 0 clock pin.
UART0_RXD
I
MFP7
UART0 data receiver input pin.
UART1_nRTS
O
MFP8
UART1 request to Send output pin.
I2C2_SDA
I/O
MFP9
I2C2 data input/output pin.
BPWM0_CH0
I/O
MFP12
BPWM0 channel 0 output/capture input.
EPWM0_CH5
I/O
MFP13
EPWM0 channel 5 output/capture input.
DAC0_ST
I
MFP15
DAC0 external trigger input.
2
29
59
67
2
M480 SERIES DATASHEET
30
60
68
May 08, 2020
Page 198 of 523
Rev 3.00
M480
64 128 144 Pin Name
Pin Pin Pin
Type
MFP
Description
31
61
69
VDDIO
P
MFP0
Power supply for PA.0~PA.5.
62
70
PE.14
I/O
MFP0
General purpose digital I/O pin.
EBI_AD8
I/O
MFP2
EBI address/data bus bit 8.
UART2_TXD
O
MFP3
UART2 data transmitter output pin.
CAN0_TXD
O
MFP4
CAN0 bus transmitter output.
SD1_nCD
I
MFP5
SD/SDIO1 card detect input pin
PE.15
I/O
MFP0
General purpose digital I/O pin.
EBI_AD9
I/O
MFP2
EBI address/data bus bit 9.
UART2_RXD
I
MFP3
UART2 data receiver input pin.
CAN0_RXD
I
MFP4
CAN0 bus receiver input.
nRESET
I
MFP0
External reset input: active LOW, with an internal pull-up.
Set this pin low reset to initial state.
63
32
64
71
72
Note: It is recommended to use 10 kΩ pull-up resistor and
10 uF capacitor on nRESET pin.
33
65
73
PF.0
I/O
MFP0
General purpose digital I/O pin.
UART1_TXD
O
MFP2
UART1 data transmitter output pin.
I C1_SCL
I/O
MFP3
I2C1 clock pin.
BPWM1_CH0
I/O
MFP12
BPWM1 channel 0 output/capture input.
ICE_DAT
O
MFP14
Serial wired debugger data pin.
2
Note: It is recommended to use 100 kΩ pull-up resistor on
ICE_DAT pin.
66
74
PF.1
I/O
MFP0
General purpose digital I/O pin.
UART1_RXD
I
MFP2
UART1 data receiver input pin.
I2C1_SDA
I/O
MFP3
I2C1 data input/output pin.
BPWM1_CH1
I/O
MFP12
BPWM1 channel 1 output/capture input.
ICE_CLK
I
MFP14
Serial wired debugger clock pin.
Note: It is recommended to use 100 kΩ pull-up resistor on
ICE_CLK pin.
67
68
75
76
PD.9
I/O
MFP0
General purpose digital I/O pin.
EBI_AD7
I/O
MFP2
EBI address/data bus bit 7.
I2C2_SCL
I/O
MFP3
I2C2 clock pin.
UART2_nCTS
I
MFP4
UART2 clear to Send input pin.
PD.8
I/O
MFP0
General purpose digital I/O pin.
EBI_AD6
I/O
MFP2
EBI address/data bus bit 6.
I C2_SDA
I/O
MFP3
I2C2 data input/output pin.
UART2_nRTS
O
MFP4
UART2 request to Send output pin.
PC.5
I/O
MFP0
General purpose digital I/O pin.
2
35
69
77
May 08, 2020
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Rev 3.00
M480 SERIES DATASHEET
34
M480
64 128 144 Pin Name
Pin Pin Pin
Type
MFP
Description
EBI_AD5
I/O
MFP2
EBI address/data bus bit 5.
SPIM_D2
I/O
MFP3
SPIM data 2 pin for Quad Mode I/O.
QSPI0_MISO1
I/O
MFP4
QSPI0 MISO1 (Master In, Slave Out) pin.
UART2_TXD
O
MFP8
UART2 data transmitter output pin.
I C1_SCL
I/O
MFP9
I2C1 clock pin.
CAN0_TXD
O
MFP10
CAN0 bus transmitter output.
UART4_TXD
O
MFP11
UART4 data transmitter output pin.
EPWM1_CH0
I/O
MFP12
EPWM1 channel 0 output/capture input.
PC.4
I/O
MFP0
General purpose digital I/O pin.
EBI_AD4
I/O
MFP2
EBI address/data bus bit 4.
SPIM_D3
I/O
MFP3
SPIM data 3 pin for Quad Mode I/O.
QSPI0_MOSI1
I/O
MFP4
QSPI0 MOSI1 (Master Out, Slave In) pin.
SC1_nCD
I
MFP5
Smart Card 1 card detect pin.
I S0_BCLK
O
MFP6
I2S0 bit clock output pin.
SPI1_I2SMCLK
I/O
MFP7
SPI1 I2S master clock output pin
UART2_RXD
I
MFP8
UART2 data receiver input pin.
I C1_SDA
I/O
MFP9
I2C1 data input/output pin.
CAN0_RXD
I
MFP10
CAN0 bus receiver input.
UART4_RXD
I
MFP11
UART4 data receiver input pin.
EPWM1_CH1
I/O
MFP12
EPWM1 channel 1 output/capture input.
PC.3
I/O
MFP0
General purpose digital I/O pin.
EBI_AD3
I/O
MFP2
EBI address/data bus bit 3.
SPIM_SS
I/O
MFP3
SPIM slave select pin.
QSPI0_SS
I/O
MFP4
QSPI0 slave select pin.
SC1_PWR
O
MFP5
Smart Card 1 power pin.
I2S0_MCLK
O
MFP6
I2S0 master clock output pin.
SPI1_MISO
I/O
MFP7
SPI1 MISO (Master In, Slave Out) pin.
UART2_nRTS
O
MFP8
UART2 request to Send output pin.
I2C0_SMBAL
O
MFP9
I2C0 SMBus SMBALTER pin
CAN1_TXD
O
MFP10
CAN1 bus transmitter output.
UART3_TXD
O
MFP11
UART3 data transmitter output pin.
EPWM1_CH2
I/O
MFP12
EPWM1 channel 2 output/capture input.
PC.2
I/O
MFP0
General purpose digital I/O pin.
EBI_AD2
I/O
MFP2
EBI address/data bus bit 2.
2
36
70
78
2
2
M480 SERIES DATASHEET
37
38
71
72
79
80
May 08, 2020
Page 200 of 523
Rev 3.00
M480
64 128 144 Pin Name
Pin Pin Pin
39
73
81
MFP
Description
SPIM_CLK
I/O
MFP3
SPIM serial clock pin.
QSPI0_CLK
I/O
MFP4
QSPI0 serial clock pin.
SC1_RST
O
MFP5
Smart Card 1 reset pin.
I2S0_DI
I
MFP6
I2S0 data input pin.
SPI1_MOSI
I/O
MFP7
SPI1 MOSI (Master Out, Slave In) pin.
UART2_nCTS
I
MFP8
UART2 clear to Send input pin.
I2C0_SMBSUS
O
MFP9
I2C0 SMBus SMBSUS pin (PMBus CONTROL pin)
CAN1_RXD
I
MFP10
CAN1 bus receiver input.
UART3_RXD
I
MFP11
UART3 data receiver input pin.
EPWM1_CH3
I/O
MFP12
EPWM1 channel 3 output/capture input.
PC.1
I/O
MFP0
General purpose digital I/O pin.
EBI_AD1
I/O
MFP2
EBI address/data bus bit 1.
SPIM_MISO
I/O
MFP3
SPIM MISO (Master In, Slave Out) pin.
QSPI0_MISO0
I/O
MFP4
QSPI0 MISO0 (Master In, Slave Out) pin.
SC1_DAT
I/O
MFP5
Smart Card 1 data pin.
I2S0_DO
O
MFP6
I2S0 data output pin.
SPI1_CLK
I/O
MFP7
SPI1 serial clock pin.
UART2_TXD
O
MFP8
UART2 data transmitter output pin.
I C0_SCL
I/O
MFP9
I2C0 clock pin.
EPWM1_CH4
I/O
MFP12
EPWM1 channel 4 output/capture input.
ACMP0_O
O
MFP14
Analog comparator 0 output pin.
PC.0
I/O
MFP0
General purpose digital I/O pin.
EBI_AD0
I/O
MFP2
EBI address/data bus bit 0.
SPIM_MOSI
I/O
MFP3
SPIM MOSI (Master Out, Slave In) pin.
QSPI0_MOSI0
I/O
MFP4
QSPI0 MOSI0 (Master Out, Slave In) pin.
SC1_CLK
O
MFP5
Smart Card 1 clock pin.
I2S0_LRCK
O
MFP6
I2S0 left right channel clock output pin.
SPI1_SS
I/O
MFP7
SPI1 slave select pin.
UART2_RXD
I
MFP8
UART2 data receiver input pin.
I C0_SDA
I/O
MFP9
I2C0 data input/output pin.
EPWM1_CH5
I/O
MFP12
EPWM1 channel 5 output/capture input.
ACMP1_O
O
MFP14
Analog comparator 1 output pin.
2
40
74
82
2
M480 SERIES DATASHEET
Type
75
83
VSS
P
MFP0
Ground pin for digital circuit.
76
84
VDD
P
MFP0
Power supply for I/O ports and LDO source for internal PLL
May 08, 2020
Page 201 of 523
Rev 3.00
M480
64 128 144 Pin Name
Pin Pin Pin
Type
MFP
Description
and digital circuit.
77
78
79
80
M480 SERIES DATASHEET
81
82
83
85
86
87
88
89
90
91
PG.9
I/O
MFP0
General purpose digital I/O pin.
EBI_AD0
I/O
MFP2
EBI address/data bus bit 0.
SD1_DAT3
I/O
MFP3
SD/SDIO1 data line bit 3.
SPIM_D2
I/O
MFP4
SPIM data 2 pin for Quad Mode I/O.
BPWM0_CH5
I/O
MFP12
BPWM0 channel 5 output/capture input.
PG.10
I/O
MFP0
General purpose digital I/O pin.
EBI_AD1
I/O
MFP2
EBI address/data bus bit 1.
SD1_DAT2
I/O
MFP3
SD/SDIO1 data line bit 2.
SPIM_D3
I/O
MFP4
SPIM data 3 pin for Quad Mode I/O.
BPWM0_CH4
I/O
MFP12
BPWM0 channel 4 output/capture input.
PG.11
I/O
MFP0
General purpose digital I/O pin.
EBI_AD2
I/O
MFP2
EBI address/data bus bit 2.
SD1_DAT1
I/O
MFP3
SD/SDIO1 data line bit 1.
SPIM_SS
I/O
MFP4
SPIM slave select pin.
BPWM0_CH3
I/O
MFP12
BPWM0 channel 3 output/capture input.
PG.12
I/O
MFP0
General purpose digital I/O pin.
EBI_AD3
I/O
MFP2
EBI address/data bus bit 3.
SD1_DAT0
I/O
MFP3
SD/SDIO1 data line bit 0.
SPIM_CLK
I/O
MFP4
SPIM serial clock pin.
BPWM0_CH2
I/O
MFP12
BPWM0 channel 2 output/capture input.
PG.13
I/O
MFP0
General purpose digital I/O pin.
EBI_AD4
I/O
MFP2
EBI address/data bus bit 4.
SD1_CMD
I/O
MFP3
SD/SDIO1 command/response pin
SPIM_MISO
I/O
MFP4
SPIM MISO (Master In, Slave Out) pin.
BPWM0_CH1
I/O
MFP12
BPWM0 channel 1 output/capture input.
PG.14
I/O
MFP0
General purpose digital I/O pin.
EBI_AD5
I/O
MFP2
EBI address/data bus bit 5.
SD1_CLK
O
MFP3
SD/SDIO1 clock output pin
SPIM_MOSI
I/O
MFP4
SPIM MOSI (Master Out, Slave In) pin.
BPWM0_CH0
I/O
MFP12
BPWM0 channel 0 output/capture input.
PG.15
I/O
MFP0
General purpose digital I/O pin.
SD1_nCD
I
MFP3
SD/SDIO1 card detect input pin
CLKO
O
MFP14
Clock Out
May 08, 2020
Page 202 of 523
Rev 3.00
M480
64 128 144 Pin Name
Pin Pin Pin
92
93
94
MFP
Description
EADC0_ST
I
MFP15
EADC0 external trigger input.
PD.3
I/O
MFP0
General purpose digital I/O pin.
EBI_AD10
I/O
MFP2
EBI address/data bus bit 10.
USCI0_CTL1
I/O
MFP3
USCI0 control 1 pin.
SPI0_SS
I/O
MFP4
SPI0 slave select pin.
UART3_nRTS
O
MFP5
UART3 request to Send output pin.
USCI1_CTL0
I/O
MFP6
USCI1 control 0 pin.
SC2_PWR
O
MFP7
Smart Card 2 power pin.
SC1_nCD
I
MFP8
Smart Card 1 card detect pin.
UART0_TXD
O
MFP9
UART0 data transmitter output pin.
PD.2
I/O
MFP0
General purpose digital I/O pin.
EBI_AD11
I/O
MFP2
EBI address/data bus bit 11.
USCI0_DAT1
I/O
MFP3
USCI0 data 1 pin.
SPI0_CLK
I/O
MFP4
SPI0 serial clock pin.
UART3_nCTS
I
MFP5
UART3 clear to Send input pin.
SC2_RST
O
MFP7
Smart Card 2 reset pin.
UART0_RXD
I
MFP9
UART0 data receiver input pin.
PD.1
I/O
MFP0
General purpose digital I/O pin.
EBI_AD12
I/O
MFP2
EBI address/data bus bit 12.
USCI0_DAT0
I/O
MFP3
USCI0 data 0 pin.
SPI0_MISO
I/O
MFP4
SPI0 MISO (Master In, Slave Out) pin.
UART3_TXD
O
MFP5
UART3 data transmitter output pin.
I C2_SCL
I/O
MFP6
I2C2 clock pin.
SC2_DAT
I/O
MFP7
Smart Card 2 data pin.
PD.0
I/O
MFP0
General purpose digital I/O pin.
EBI_AD13
I/O
MFP2
EBI address/data bus bit 13.
USCI0_CLK
I/O
MFP3
USCI0 clock pin.
SPI0_MOSI
I/O
MFP4
SPI0 MOSI (Master Out, Slave In) pin.
UART3_RXD
I
MFP5
UART3 data receiver input pin.
I C2_SDA
I/O
MFP6
I2C2 data input/output pin.
SC2_CLK
O
MFP7
Smart Card 2 clock pin.
TM2
I/O
MFP14
Timer2 event counter input/toggle output pin.
PD.13
I/O
MFP0
General purpose digital I/O pin.
EBI_AD10
I/O
MFP2
EBI address/data bus bit 10.
2
95
2
84
96
May 08, 2020
Page 203 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
64 128 144 Pin Name
Pin Pin Pin
85
97
Type
MFP
Description
SD0_nCD
I
MFP3
SD/SDIO0 card detect input pin
SPI0_I2SMCLK
I/O
MFP4
SPI0 I2S master clock output pin
SPI1_I2SMCLK
I/O
MFP5
SPI1 I2S master clock output pin
SC2_nCD
I
MFP7
Smart Card 2 card detect pin.
PA.12
I/O
MFP0
General purpose digital I/O pin.
I2S0_BCLK
O
MFP2
I2S0 bit clock output pin.
UART4_TXD
O
MFP3
UART4 data transmitter output pin.
I C1_SCL
I/O
MFP4
I2C1 clock pin.
SPI2_SS
I/O
MFP5
SPI2 slave select pin.
CAN0_TXD
O
MFP6
CAN0 bus transmitter output.
SC2_PWR
O
MFP7
Smart Card 2 power pin.
BPWM1_CH2
I/O
MFP11
BPWM1 channel 2 output/capture input.
QEI1_INDEX
I
MFP12
Quadrature encoder 1 index input
USB_VBUS
P
MFP14
Power supply from USB host or HUB.
PA.13
I/O
MFP0
General purpose digital I/O pin.
I2S0_MCLK
O
MFP2
I2S0 master clock output pin.
UART4_RXD
I
MFP3
UART4 data receiver input pin.
I2C1_SDA
I/O
MFP4
I2C1 data input/output pin.
SPI2_CLK
I/O
MFP5
SPI2 serial clock pin.
CAN0_RXD
I
MFP6
CAN0 bus receiver input.
SC2_RST
O
MFP7
Smart Card 2 reset pin.
BPWM1_CH3
I/O
MFP11
BPWM1 channel 3 output/capture input.
QEI1_A
I
MFP12
Quadrature encoder 1 phase A input
USB_D-
A
MFP14
USB differential signal D-.
PA.14
I/O
MFP0
General purpose digital I/O pin.
I2S0_DI
I
MFP2
I2S0 data input pin.
UART0_TXD
O
MFP3
UART0 data transmitter output pin.
SPI2_MISO
I/O
MFP5
SPI2 MISO (Master In, Slave Out) pin.
I2C2_SCL
I/O
MFP6
I2C2 clock pin.
SC2_DAT
I/O
MFP7
Smart Card 2 data pin.
BPWM1_CH4
I/O
MFP11
BPWM1 channel 4 output/capture input.
QEI1_B
I
MFP12
Quadrature encoder 1 phase B input
USB_D+
A
MFP14
USB differential signal D+.
I/O
MFP0
General purpose digital I/O pin.
2
86
M480 SERIES DATASHEET
87
88
98
99
100 PA.15
May 08, 2020
Page 204 of 523
Rev 3.00
M480
64 128 144 Pin Name
Pin Pin Pin
Type
MFP
Description
I2S0_DO
O
MFP2
I2S0 data output pin.
UART0_RXD
I
MFP3
UART0 data receiver input pin.
SPI2_MOSI
I/O
MFP5
SPI2 MOSI (Master Out, Slave In) pin.
I2C2_SDA
I/O
MFP6
I2C2 data input/output pin.
SC2_CLK
O
MFP7
Smart Card 2 clock pin.
BPWM1_CH5
I/O
MFP11
BPWM1 channel 5 output/capture input.
EPWM0_SYNC_IN
I
MFP12
EPWM0 counter synchronous trigger input pin.
USB_OTG_ID
I
MFP14
USB_ identification.
41
89
101 HSUSB_VRES
A
MFP0
HSUSB module reference resister
42
90
102 HSUSB_VDD33
P
MFP0
Power supply for HSUSB VDD33
43
91
103 HSUSB_VBUS
P
MFP0
HSUSB Power supply from USB host or HUB.
44
92
104 HSUSB_D-
A
MFP0
HSUSB differential signal D-.
45
93
105 HSUSB_VSS
P
MFP0
Ground pin for HSUSB.
46
94
106 HSUSB_D+
A
MFP0
HSUSB differential signal D+.
47
95
107 HSUSB_VDD12_CAP
A
MFP0
HSUSB Internal power regulator output 1.2V decoupling pin.
Note: This pin needs to be connected with a 1uF capacitor.
48
108 HSUSB_ID
I
MFP0
HSUSB identification.
97
109 PE.7
I/O
MFP0
General purpose digital I/O pin.
SD0_CMD
I/O
MFP3
SD/SDIO0 command/response pin
SPIM_D2
I/O
MFP4
SPIM data 2 pin for Quad Mode I/O.
UART5_TXD
O
MFP8
UART5 data transmitter output pin.
CAN1_TXD
O
MFP9
CAN1 bus transmitter output.
QEI1_INDEX
I
MFP11
Quadrature encoder 1 index input
EPWM0_CH0
I/O
MFP12
EPWM0 channel 0 output/capture input.
BPWM0_CH5
I/O
MFP13
BPWM0 channel 5 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
SD0_CLK
O
MFP3
SD/SDIO0 clock output pin
SPIM_D3
I/O
MFP4
SPIM data 3 pin for Quad Mode I/O.
SPI3_I2SMCLK
I/O
MFP5
SPI3 I2S master clock output pin
SC0_nCD
I
MFP6
Smart Card 0 card detect pin.
USCI0_CTL0
I/O
MFP7
USCI0 control 0 pin.
UART5_RXD
I
MFP8
UART5 data receiver input pin.
CAN1_RXD
I
MFP9
CAN1 bus receiver input.
QEI1_A
I
MFP11
Quadrature encoder 1 phase A input
98
110 PE.6
May 08, 2020
Page 205 of 523
M480 SERIES DATASHEET
96
Rev 3.00
M480
64 128 144 Pin Name
Pin Pin Pin
99
Type
MFP
Description
EPWM0_CH1
I/O
MFP12
EPWM0 channel 1 output/capture input.
BPWM0_CH4
I/O
MFP13
BPWM0 channel 4 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_nRD
O
MFP2
EBI read enable output pin.
SD0_DAT3
I/O
MFP3
SD/SDIO0 data line bit 3.
SPIM_SS
I/O
MFP4
SPIM slave select pin.
SPI3_SS
I/O
MFP5
SPI3 slave select pin.
SC0_PWR
O
MFP6
Smart Card 0 power pin.
USCI0_CTL1
I/O
MFP7
USCI0 control 1 pin.
QEI1_B
I
MFP11
Quadrature encoder 1 phase B input
EPWM0_CH2
I/O
MFP12
EPWM0 channel 2 output/capture input.
BPWM0_CH3
I/O
MFP13
BPWM0 channel 3 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_nWR
O
MFP2
EBI write enable output pin.
SD0_DAT2
I/O
MFP3
SD/SDIO0 data line bit 2.
SPIM_CLK
I/O
MFP4
SPIM serial clock pin.
SPI3_CLK
I/O
MFP5
SPI3 serial clock pin.
SC0_RST
O
MFP6
Smart Card 0 reset pin.
USCI0_DAT1
I/O
MFP7
USCI0 data 1 pin.
QEI0_INDEX
I
MFP11
Quadrature encoder 0 index input
EPWM0_CH3
I/O
MFP12
EPWM0 channel 3 output/capture input.
BPWM0_CH2
I/O
MFP13
BPWM0 channel 2 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_MCLK
O
MFP2
EBI external clock output pin.
SD0_DAT1
I/O
MFP3
SD/SDIO0 data line bit 1.
SPIM_MISO
I/O
MFP4
SPIM MISO (Master In, Slave Out) pin.
SPI3_MISO
I/O
MFP5
SPI3 MISO (Master In, Slave Out) pin.
SC0_DAT
I/O
MFP6
Smart Card 0 data pin.
USCI0_DAT0
I/O
MFP7
USCI0 data 0 pin.
QEI0_A
I
MFP11
Quadrature encoder 0 phase A input
EPWM0_CH4
I/O
MFP12
EPWM0 channel 4 output/capture input.
BPWM0_CH1
I/O
MFP13
BPWM0 channel 1 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
O
MFP2
EBI address latch enable output pin.
111 PE.5
100 112 PE.4
M480 SERIES DATASHEET
101 113 PE.3
102 114 PE.2
EBI_ALE
May 08, 2020
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Rev 3.00
M480
64 128 144 Pin Name
Pin Pin Pin
MFP
Description
SD0_DAT0
I/O
MFP3
SD/SDIO0 data line bit 0.
SPIM_MOSI
I/O
MFP4
SPIM MOSI (Master Out, Slave In) pin.
SPI3_MOSI
I/O
MFP5
SPI3 MOSI (Master Out, Slave In) pin.
SC0_CLK
O
MFP6
Smart Card 0 clock pin.
USCI0_CLK
I/O
MFP7
USCI0 clock pin.
QEI0_B
I
MFP11
Quadrature encoder 0 phase B input
EPWM0_CH5
I/O
MFP12
EPWM0 channel 5 output/capture input.
BPWM0_CH0
I/O
MFP13
BPWM0 channel 0 output/capture input.
103 115 VSS
P
MFP0
Ground pin for digital circuit.
104 116 VDD
P
MFP0
Power supply for I/O ports and LDO source for internal PLL
and digital circuit.
105 117 PE.1
I/O
MFP0
General purpose digital I/O pin.
EBI_AD10
I/O
MFP2
EBI address/data bus bit 10.
QSPI0_MISO0
I/O
MFP3
QSPI0 MISO0 (Master In, Slave Out) pin.
SC2_DAT
I/O
MFP4
Smart Card 2 data pin.
I S0_BCLK
O
MFP5
I2S0 bit clock output pin.
SPI1_MISO
I/O
MFP6
SPI1 MISO (Master In, Slave Out) pin.
UART3_TXD
O
MFP7
UART3 data transmitter output pin.
I2C1_SCL
I/O
MFP8
I2C1 clock pin.
UART4_nCTS
I
MFP9
UART4 clear to Send input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD11
I/O
MFP2
EBI address/data bus bit 11.
QSPI0_MOSI0
I/O
MFP3
QSPI0 MOSI0 (Master Out, Slave In) pin.
SC2_CLK
O
MFP4
Smart Card 2 clock pin.
I S0_MCLK
O
MFP5
I2S0 master clock output pin.
SPI1_MOSI
I/O
MFP6
SPI1 MOSI (Master Out, Slave In) pin.
UART3_RXD
I
MFP7
UART3 data receiver input pin.
I2C1_SDA
I/O
MFP8
I2C1 data input/output pin.
UART4_nRTS
O
MFP9
UART4 request to Send output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD12
I/O
MFP2
EBI address/data bus bit 12.
QSPI0_CLK
I/O
MFP3
QSPI0 serial clock pin.
SC2_PWR
O
MFP4
Smart Card 2 power pin.
I
MFP5
I2S0 data input pin.
2
106 118 PE.0
2
107 119 PH.8
2
I S0_DI
May 08, 2020
Page 207 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
64 128 144 Pin Name
Pin Pin Pin
Type
MFP
Description
SPI1_CLK
I/O
MFP6
SPI1 serial clock pin.
UART3_nRTS
O
MFP7
UART3 request to Send output pin.
I C1_SMBAL
O
MFP8
I2C1 SMBus SMBALTER pin
I2C2_SCL
I/O
MFP9
I2C2 clock pin.
UART1_TXD
O
MFP10
UART1 data transmitter output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD13
I/O
MFP2
EBI address/data bus bit 13.
QSPI0_SS
I/O
MFP3
QSPI0 slave select pin.
SC2_RST
O
MFP4
Smart Card 2 reset pin.
I S0_DO
O
MFP5
I2S0 data output pin.
SPI1_SS
I/O
MFP6
SPI1 slave select pin.
UART3_nCTS
I
MFP7
UART3 clear to Send input pin.
I2C1_SMBSUS
O
MFP8
I2C1 SMBus SMBSUS pin (PMBus CONTROL pin)
I2C2_SDA
I/O
MFP9
I2C2 data input/output pin.
UART1_RXD
I
MFP10
UART1 data receiver input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD14
I/O
MFP2
EBI address/data bus bit 14.
QSPI0_MISO1
I/O
MFP3
QSPI0 MISO1 (Master In, Slave Out) pin.
SC2_nCD
I
MFP4
Smart Card 2 card detect pin.
I2S0_LRCK
O
MFP5
I2S0 left right channel clock output pin.
SPI1_I2SMCLK
I/O
MFP6
SPI1 I2S master clock output pin
UART4_TXD
O
MFP7
UART4 data transmitter output pin.
UART0_TXD
O
MFP8
UART0 data transmitter output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD15
I/O
MFP2
EBI address/data bus bit 15.
QSPI0_MOSI1
I/O
MFP3
QSPI0 MOSI1 (Master Out, Slave In) pin.
UART4_RXD
I
MFP7
UART4 data receiver input pin.
UART0_RXD
I
MFP8
UART0 data receiver input pin.
EPWM0_CH5
I/O
MFP11
EPWM0 channel 5 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_nCS0
O
MFP2
EBI chip select 0 output pin.
SPI3_I2SMCLK
I/O
MFP3
SPI3 I2S master clock output pin
SC1_nCD
I
MFP4
Smart Card 1 card detect pin.
EPWM0_CH4
I/O
MFP11
EPWM0 channel 4 output/capture input.
2
108 120 PH.9
2
109 121 PH.10
M480 SERIES DATASHEET
110 122 PH.11
111 123 PD.14
May 08, 2020
Page 208 of 523
Rev 3.00
M480
64 128 144 Pin Name
Pin Pin Pin
MFP
Description
I/O
MFP0
General purpose digital I/O pin.
EBI_nCS1
O
MFP2
EBI chip select 1 output pin.
SPI3_SS
I/O
MFP3
SPI3 slave select pin.
SC1_PWR
O
MFP4
Smart Card 1 power pin.
EPWM0_CH3
I/O
MFP11
EPWM0 channel 3 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_nCS2
O
MFP2
EBI chip select 2 output pin.
SPI3_CLK
I/O
MFP3
SPI3 serial clock pin.
SC1_RST
O
MFP4
Smart Card 1 reset pin.
EPWM0_CH2
I/O
MFP11
EPWM0 channel 2 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_nWRL
O
MFP2
EBI low byte write enable output pin.
SPI3_MISO
I/O
MFP3
SPI3 MISO (Master In, Slave Out) pin.
SC1_DAT
I/O
MFP4
Smart Card 1 data pin.
EPWM0_CH1
I/O
MFP11
EPWM0 channel 1 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_nWRH
O
MFP2
EBI high byte write enable output pin
SPI3_MOSI
I/O
MFP3
SPI3 MOSI (Master Out, Slave In) pin.
SC1_CLK
O
MFP4
Smart Card 1 clock pin.
EPWM0_CH0
I/O
MFP11
EPWM0 channel 0 output/capture input.
124 PG.5
125 PG.6
126 PG.7
127 PG.8
49
112 128 VSS
P
MFP0
Ground pin for digital circuit.
50
113 129 LDO_CAP
A
MFP0
LDO output pin.
Note: This pin needs to be connected with an external
capacitor.
51
114 130 VDD
P
MFP0
Power supply for I/O ports and LDO source for internal PLL
and digital circuit.
52
115 131 PC.14
I/O
MFP0
General purpose digital I/O pin.
EBI_AD11
I/O
MFP2
EBI address/data bus bit 11.
SC1_nCD
I
MFP3
Smart Card 1 card detect pin.
SPI0_I2SMCLK
I/O
MFP4
SPI0 I2S master clock output pin
USCI0_CTL0
I/O
MFP5
USCI0 control 0 pin.
QSPI0_CLK
I/O
MFP6
QSPI0 serial clock pin.
EPWM0_SYNC_IN
I
MFP11
EPWM0 counter synchronous trigger input pin.
ETM_TRACE_CLK
I
MFP12
ETM receiver Trace Clock input pin
TM1
I/O
MFP13
Timer1 event counter input/toggle output pin.
May 08, 2020
Page 209 of 523
Rev 3.00
M480 SERIES DATASHEET
Type
M480
64 128 144 Pin Name
Pin Pin Pin
53
54
M480 SERIES DATASHEET
Type
MFP
Description
USB_VBUS_ST
I
MFP14
USB external VBUS regulator status pin.
HSUSB_VBUS_ST
I
MFP15
HSUSB external VBUS regulator status pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH15
A
MFP1
EADC0 channel 15 analog input.
EBI_AD12
I/O
MFP2
EBI address/data bus bit 12.
SC1_PWR
O
MFP3
Smart Card 1 power pin.
SPI0_SS
I/O
MFP4
SPI0 slave select pin.
USCI0_CTL1
I/O
MFP5
USCI0 control 1 pin.
UART0_nCTS
I
MFP6
UART0 clear to Send input pin.
UART3_TXD
O
MFP7
UART3 data transmitter output pin.
I2C2_SMBAL
O
MFP8
I2C2 SMBus SMBALTER pin
EPWM1_CH0
I/O
MFP11
EPWM1 channel 0 output/capture input.
ETM_TRACE_DATA0
I
MFP12
ETM receiver Trace Data 0 input pin
TM0_EXT
I/O
MFP13
Timer0 event counter input/toggle output pin.
USB_VBUS_EN
O
MFP14
USB external VBUS regulator enable pin.
HSUSB_VBUS_EN
O
MFP15
HSUSB external VBUS regulator enable pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH14
A
MFP1
EADC0 channel 14 analog input.
EBI_AD13
I/O
MFP2
EBI address/data bus bit 13.
SC1_RST
O
MFP3
Smart Card 1 reset pin.
SPI0_CLK
I/O
MFP4
SPI0 serial clock pin.
USCI0_DAT1
I/O
MFP5
USCI0 data 1 pin.
UART0_nRTS
O
MFP6
UART0 request to Send output pin.
UART3_RXD
I
MFP7
UART3 data receiver input pin.
I C2_SMBSUS
O
MFP8
I2C2 SMBus SMBSUS pin (PMBus CONTROL pin)
EPWM1_CH1
I/O
MFP11
EPWM1 channel 1 output/capture input.
ETM_TRACE_DATA1
I
MFP12
ETM receiver Trace Data 1 input pin
TM1_EXT
I/O
MFP13
Timer1 event counter input/toggle output pin.
CLKO
O
MFP14
Clock Out
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH13
A
MFP1
EADC0 channel 13 analog input.
DAC1_OUT
A
MFP1
DAC1 channel analog output.
ACMP0_P3
A
MFP1
Analog comparator 0 positive input 3 pin.
ACMP1_P3
A
MFP1
Analog comparator 1 positive input 3 pin.
116 132 PB.15
117 133 PB.14
2
55
118 134 PB.13
May 08, 2020
Page 210 of 523
Rev 3.00
M480
64 128 144 Pin Name
Pin Pin Pin
56
MFP
Description
EBI_AD14
I/O
MFP2
EBI address/data bus bit 14.
SC1_DAT
I/O
MFP3
Smart Card 1 data pin.
SPI0_MISO
I/O
MFP4
SPI0 MISO (Master In, Slave Out) pin.
USCI0_DAT0
I/O
MFP5
USCI0 data 0 pin.
UART0_TXD
O
MFP6
UART0 data transmitter output pin.
UART3_nRTS
O
MFP7
UART3 request to Send output pin.
I2C2_SCL
I/O
MFP8
I2C2 clock pin.
EPWM1_CH2
I/O
MFP11
EPWM1 channel 2 output/capture input.
ETM_TRACE_DATA2
I
MFP12
ETM receiver Trace Data 2 input pin
TM2_EXT
I/O
MFP13
Timer2 event counter input/toggle output pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH12
A
MFP1
EADC0 channel 12 analog input.
DAC0_OUT
A
MFP1
DAC0 channel analog output.
ACMP0_P2
A
MFP1
Analog comparator 0 positive input 2 pin.
ACMP1_P2
A
MFP1
Analog comparator 1 positive input 2 pin.
EBI_AD15
I/O
MFP2
EBI address/data bus bit 15.
SC1_CLK
O
MFP3
Smart Card 1 clock pin.
SPI0_MOSI
I/O
MFP4
SPI0 MOSI (Master Out, Slave In) pin.
USCI0_CLK
I/O
MFP5
USCI0 clock pin.
UART0_RXD
I
MFP6
UART0 data receiver input pin.
UART3_nCTS
I
MFP7
UART3 clear to Send input pin.
I2C2_SDA
I/O
MFP8
I2C2 data input/output pin.
SD0_nCD
I
MFP9
SD/SDIO0 card detect input pin
EPWM1_CH3
I/O
MFP11
EPWM1 channel 3 output/capture input.
ETM_TRACE_DATA3
I
MFP12
ETM receiver Trace Data 3 input pin
TM3_EXT
I/O
MFP13
Timer3 event counter input/toggle output pin.
119 135 PB.12
57
120 136 AVDD
P
MFP0
Power supply for internal analog circuit.
58
121 137 VREF
A
MFP0
ADC reference voltage input.
M480 SERIES DATASHEET
Type
Note: This pin needs to be connected with a 1uF capacitor.
59
122 138 AVSS
P
MFP0
Ground pin for analog circuit.
60
123 139 PB.11
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH11
A
MFP1
EADC0 channel 11 analog input.
EBI_ADR16
O
MFP2
EBI address bus bit 16.
EMAC_RMII_MDC
O
MFP3
EMAC RMII PHY Management Clock output pin.
May 08, 2020
Page 211 of 523
Rev 3.00
M480
64 128 144 Pin Name
Pin Pin Pin
Type
MFP
Description
UART0_nCTS
I
MFP5
UART0 clear to Send input pin.
UART4_TXD
O
MFP6
UART4 data transmitter output pin.
I C1_SCL
I/O
MFP7
I2C1 clock pin.
CAN0_TXD
O
MFP8
CAN0 bus transmitter output.
SPI0_I2SMCLK
I/O
MFP9
SPI0 I2S master clock output pin
BPWM1_CH0
I/O
MFP10
BPWM1 channel 0 output/capture input.
SPI3_CLK
I/O
MFP11
SPI3 serial clock pin.
HSUSB_VBUS_ST
I
MFP14
HSUSB external VBUS regulator status pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH10
A
MFP1
EADC0 channel 10 analog input.
EBI_ADR17
O
MFP2
EBI address bus bit 17.
EMAC_RMII_MDIO
I/O
MFP3
EMAC RMII PHY Management Data pin.
USCI1_CTL0
I/O
MFP4
USCI1 control 0 pin.
UART0_nRTS
O
MFP5
UART0 request to Send output pin.
UART4_RXD
I
MFP6
UART4 data receiver input pin.
I2C1_SDA
I/O
MFP7
I2C1 data input/output pin.
CAN0_RXD
I
MFP8
CAN0 bus receiver input.
BPWM1_CH1
I/O
MFP10
BPWM1 channel 1 output/capture input.
SPI3_SS
I/O
MFP11
SPI3 slave select pin.
HSUSB_VBUS_EN
O
MFP14
HSUSB external VBUS regulator enable pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH9
A
MFP1
EADC0 channel 9 analog input.
EBI_ADR18
O
MFP2
EBI address bus bit 18.
EMAC_RMII_TXD0
O
MFP3
EMAC RMII Transmit Data bus bit 0.
USCI1_CTL1
I/O
MFP4
USCI1 control 1 pin.
UART0_TXD
O
MFP5
UART0 data transmitter output pin.
UART1_nCTS
I
MFP6
UART1 clear to Send input pin.
I C1_SMBAL
O
MFP7
I2C1 SMBus SMBALTER pin
BPWM1_CH2
I/O
MFP10
BPWM1 channel 2 output/capture input.
SPI3_MISO
I/O
MFP11
SPI3 MISO (Master In, Slave Out) pin.
INT7
I
MFP13
External interrupt 7 input pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH8
A
MFP1
EADC0 channel 8 analog input.
EBI_ADR19
O
MFP2
EBI address bus bit 19.
2
61
M480 SERIES DATASHEET
62
124 140 PB.10
125 141 PB.9
2
63
126 142 PB.8
May 08, 2020
Page 212 of 523
Rev 3.00
M480
64 128 144 Pin Name
Pin Pin Pin
MFP
Description
EMAC_RMII_TXD1
O
MFP3
EMAC RMII Transmit Data bus bit 1.
USCI1_CLK
I/O
MFP4
USCI1 clock pin.
UART0_RXD
I
MFP5
UART0 data receiver input pin.
UART1_nRTS
O
MFP6
UART1 request to Send output pin.
I C1_SMBSUS
O
MFP7
I2C1 SMBus SMBSUS pin (PMBus CONTROL pin)
BPWM1_CH3
I/O
MFP10
BPWM1 channel 3 output/capture input.
SPI3_MOSI
I/O
MFP11
SPI3 MOSI (Master Out, Slave In) pin.
INT6
I
MFP13
External interrupt 6 input pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH7
A
MFP1
EADC0 channel 7 analog input.
EBI_nWRL
O
MFP2
EBI low byte write enable output pin.
EMAC_RMII_TXEN
O
MFP3
EMAC RMII Transmit Enable output pin.
USCI1_DAT0
I/O
MFP4
USCI1 data 0 pin.
CAN1_TXD
O
MFP5
CAN1 bus transmitter output.
UART1_TXD
O
MFP6
UART1 data transmitter output pin.
SD1_CMD
I/O
MFP7
SD/SDIO1 command/response pin
EBI_nCS0
O
MFP8
EBI chip select 0 output pin.
BPWM1_CH4
I/O
MFP10
BPWM1 channel 4 output/capture input.
EPWM1_BRAKE0
I
MFP11
EPWM1 Brake 0 input pin.
EPWM1_CH4
I/O
MFP12
EPWM1 channel 4 output/capture input.
INT5
I
MFP13
External interrupt 5 input pin.
USB_VBUS_ST
I
MFP14
USB external VBUS regulator status pin.
ACMP0_O
O
MFP15
Analog comparator 0 output pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH6
A
MFP1
EADC0 channel 6 analog input.
EBI_nWRH
O
MFP2
EBI high byte write enable output pin
EMAC_PPS
O
MFP3
EMAC Pulse Per Second output pin.
USCI1_DAT1
I/O
MFP4
USCI1 data 1 pin.
CAN1_RXD
I
MFP5
CAN1 bus receiver input.
UART1_RXD
I
MFP6
UART1 data receiver input pin.
SD1_CLK
O
MFP7
SD/SDIO1 clock output pin
EBI_nCS1
O
MFP8
EBI chip select 1 output pin.
BPWM1_CH5
I/O
MFP10
BPWM1 channel 5 output/capture input.
EPWM1_BRAKE1
I
MFP11
EPWM1 Brake 1 input pin.
2
64
1
127 143 PB.7
128 144 PB.6
May 08, 2020
Page 213 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
64 128 144 Pin Name
Pin Pin Pin
Type
MFP
Description
EPWM1_CH5
I/O
MFP12
EPWM1 channel 5 output/capture input.
INT4
I
MFP13
External interrupt 4 input pin.
USB_VBUS_EN
O
MFP14
USB external VBUS regulator enable pin.
ACMP1_O
O
MFP15
Analog comparator 1 output pin.
M480 SERIES DATASHEET
May 08, 2020
Page 214 of 523
Rev 3.00
M480
4.3 M48xxE8AE/M48xxGCAE Pin Description
4.3.1
M481 Series Pin Description
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.0 MFP0 means SYS_GPA_MFPL[3:0] = 0x0.
PA.9 MFP5 means SYS_GPA_MFPH[7:4] = 0x5.
32 48 64 Pin Name
Pin Pin Pin
48
1
MFP
Description
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH6
A
MFP1
EADC0 channel 6 analog input.
EBI_nWRHPA.1
O
MFP2
EBI high byte write enable output pin
CAN1_RXD
I
MFP5
CAN1 bus receiver input.
UART1_RXD
I
MFP6
UART1 data receiver input pin.
EBI_nCS1
O
MFP8
EBI chip select 1 output pin.
BPWM1_CH5
I/O
MFP10
BPWM1 channel 5 output/capture input.
I
MFP11
EPWM1 Brake 1 input pin.
I/O
MFP12
EPWM1 channel 5 output/capture input.
INT4
I
MFP13
External interrupt 4 input pin.
USB_VBUS_EN
O
MFP14
USB external VBUS regulator enable pin.
ACMP1_O
O
MFP15
Analog comparator 1 output pin.
PB.5
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH5
A
MFP1
EADC0 channel 5 analog input.
ACMP1_N
A
MFP1
Analog comparator 1 negative input pin.
EBI_ADR0
O
MFP2
EBI address bus bit 0.
SD0_DAT3
I/O
MFP3
SD/SDIO0 data line bit 3.
SPI1_MISO
I/O
MFP5
SPI1 MISO (Master In, Slave Out) pin.
I C0_SCL
I/O
MFP6
I2C0 clock pin.
UART5_TXD
O
MFP7
UART5 data transmitter output pin.
SC0_CLK
O
MFP9
Smart Card 0 clock pin.
I2S0_BCLK
O
MFP10
I2S0 bit clock output pin.
EPWM0_CH0
I/O
MFP11
EPWM0 channel 0 output/capture input.
UART2_TXD
O
MFP12
UART2 data transmitter output pin.
TM0
I/O
MFP14
Timer0 event counter input/toggle output pin.
INT0
I
MFP15
External interrupt 0 input pin.
PB.4
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC0 channel 4 analog input.
PB.6
EPWM1_BRAKE1
EPWM1_CH5
1
1
2
2
2
2
3
EADC0_CH4
May 08, 2020
Page 215 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
32 48 64 Pin Name
Pin Pin Pin
Type
MFP
Description
ACMP1_P1
A
MFP1
Analog comparator 1 positive input 1 pin.
EBI_ADR1
O
MFP2
EBI address bus bit 1.
SD0_DAT2
I/O
MFP3
SD/SDIO0 data line bit 2.
SPI1_MOSI
I/O
MFP5
SPI1 MOSI (Master Out, Slave In) pin.
I/O
MFP6
I2C0 data input/output pin.
I
MFP7
UART5 data receiver input pin.
I/O
MFP9
Smart Card 0 data pin.
I S0_MCLK
O
MFP10
I2S0 master clock output pin.
EPWM0_CH1
I/O
MFP11
EPWM0 channel 1 output/capture input.
UART2_RXD
I
MFP12
UART2 data receiver input pin.
TM1
I/O
MFP14
Timer1 event counter input/toggle output pin.
INT1
I
MFP15
External interrupt 1 input pin.
PB.3
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH3
A
MFP1
EADC0 channel 3 analog input.
EADC1_CH11
A
MFP1
EADC1 channel 11 analog input.
ACMP0_N
A
MFP1
Analog comparator 0 negative input pin.
EBI_ADR2
O
MFP2
EBI address bus bit 2.
SD0_DAT1
I/O
MFP3
SD/SDIO0 data line bit 1.
SPI1_CLK
I/O
MFP5
SPI1 serial clock pin.
UART1_TXD
O
MFP6
UART1 data transmitter output pin.
UART5_nRTS
O
MFP7
UART5 request to Send output pin.
SC0_RST
O
MFP9
Smart Card 0 reset pin.
I
MFP10
I2S0 data input pin.
I/O
MFP11
EPWM0 channel 2 output/capture input.
I C1_SCL
I/O
MFP12
I2C1 clock pin.
TM2
I/O
MFP14
Timer2 event counter input/toggle output pin.
INT2
I
MFP15
External interrupt 2 input pin.
PB.2
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH2
A
MFP1
EADC0 channel 2 analog input.
EADC1_CH10
A
MFP1
EADC1 channel 10 analog input.
ACMP0_P1
A
MFP1
Analog comparator 0 positive input 1 pin.
EBI_ADR3
O
MFP2
EBI address bus bit 3.
SD0_DAT0
I/O
MFP3
SD/SDIO0 data line bit 0.
SPI1_SS
I/O
MFP5
SPI1 slave select pin.
2
I C0_SDA
UART5_RXD
SC0_DAT
2
3
3
4
M480 SERIES DATASHEET
2
I S0_DI
EPWM0_CH2
2
4
4
5
May 08, 2020
Page 216 of 523
Rev 3.00
M480
32 48 64 Pin Name
Pin Pin Pin
5
5
6
MFP
Description
UART1_RXD
I
MFP6
UART1 data receiver input pin.
UART5_nCTS
I
MFP7
UART5 clear to Send input pin.
SC0_PWR
O
MFP9
Smart Card 0 power pin.
I2S0_DO
O
MFP10
I2S0 data output pin.
EPWM0_CH3
I/O
MFP11
EPWM0 channel 3 output/capture input.
I2C1_SDA
I/O
MFP12
I2C1 data input/output pin.
TM3
I/O
MFP14
Timer3 event counter input/toggle output pin.
INT3
I
MFP15
External interrupt 3 input pin.
PB.1
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH1
A
MFP1
EADC0 channel 1 analog input.
EADC1_CH9
A
MFP1
EADC1 channel 9 analog input.
EBI_ADR8
O
MFP2
EBI address bus bit 8.
SD0_CLK
O
MFP3
SD/SDIO0 clock output pin
SPI1_I2SMCLK
I/O
MFP5
SPI1 I2S master clock output pin
UART2_TXD
O
MFP7
UART2 data transmitter output pin.
I2C1_SCL
I/O
MFP9
I2C1 clock pin.
I2S0_LRCK
O
MFP10
I2S0 left right channel clock output pin.
EPWM0_CH4
I/O
MFP11
EPWM0 channel 4 output/capture input.
EPWM1_CH4
I/O
MFP12
EPWM1 channel 4 output/capture input.
I
MFP13
EPWM0 Brake 0 input pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH0
A
MFP1
EADC0 channel 0 analog input.
EADC1_CH8
A
MFP1
EADC1 channel 8 analog input.
EBI_ADR9
O
MFP2
EBI address bus bit 9.
SD0_CMD
I/O
MFP3
SD/SDIO0 command/response pin
SPI2_I2SMCLK
I/O
MFP4
SPI2 I2S master clock output pin
I
MFP7
UART2 data receiver input pin.
SPI0_I2SMCLK
I/O
MFP8
SPI0 I2S master clock output pin
I2C1_SDA
I/O
MFP9
I2C1 data input/output pin.
EPWM0_CH5
I/O
MFP11
EPWM0 channel 5 output/capture input.
EPWM1_CH5
I/O
MFP12
EPWM1 channel 5 output/capture input.
I
MFP13
EPWM0 Brake 1 input pin.
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC1 channel 7 analog input.
EPWM0_BRAKE0
6
6
7
PB.0
UART2_RXD
EPWM0_BRAKE1
7
8
PA.11
EADC1_CH7
May 08, 2020
Page 217 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
32 48 64 Pin Name
Pin Pin Pin
8
9
Type
MFP
Description
ACMP0_P0
A
MFP1
Analog comparator 0 positive input 0 pin.
EBI_nRD
O
MFP2
EBI read enable output pin.
SPI2_SS
I/O
MFP4
SPI2 slave select pin.
I2C2_SCL
I/O
MFP7
I2C2 clock pin.
UART6_TXD
O
MFP8
UART6 data transmitter output pin.
BPWM0_CH0
I/O
MFP9
BPWM0 channel 0 output/capture input.
EPWM0_SYNC_OUT
O
MFP10
EPWM0 counter synchronous trigger output pin.
TM0_EXT
I/O
MFP13
Timer0 external capture input/toggle output pin.
PA.10
I/O
MFP0
General purpose digital I/O pin.
EADC1_CH6
A
MFP1
EADC1 channel 6 analog input.
ACMP1_P0
A
MFP1
Analog comparator 1 positive input 0 pin.
EBI_nWR
O
MFP2
EBI write enable output pin.
SPI2_CLK
I/O
MFP4
SPI2 serial clock pin.
I/O
MFP7
I2C2 data input/output pin.
UART6_RXD
I
MFP8
UART6 data receiver input pin.
BPWM0_CH1
I/O
MFP9
BPWM0 channel 1 output/capture input.
QEI1_INDEX
I
MFP10
Quadrature encoder 1 index input
ECAP0_IC0
I
MFP11
Enhanced capture unit 0 input 0 pin.
TM1_EXT
I/O
MFP13
Timer1 external capture input/toggle output pin.
DAC0_ST
I
MFP14
DAC0 external trigger input.
SWDH_CLK
O
MFP15
Serial Wire Debug Host Clock output
I/O
MFP0
General purpose digital I/O pin.
EADC1_CH5
A
MFP1
EADC1 channel 5 analog input.
EBI_MCLK
O
MFP2
EBI external clock output pin.
SPI2_MISO
I/O
MFP4
SPI2 MISO (Master In, Slave Out) pin.
UART1_TXD
O
MFP7
UART1 data transmitter output pin.
UART7_TXD
O
MFP8
UART7 data transmitter output pin.
BPWM0_CH2
I/O
MFP9
BPWM0 channel 2 output/capture input.
QEI1_A
I
MFP10
Quadrature encoder 1 phase A input
ECAP0_IC1
I
MFP11
Enhanced capture unit 0 input 1 pin.
TM2_EXT
I/O
MFP13
Timer2 external capture input/toggle output pin.
SWDH_DAT
I/O
MFP15
Serial Wire Debug Host Data input/output pin
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC1 channel 4 analog input.
2
I C2_SDA
M480 SERIES DATASHEET
9
10
10 PA.9
11 PA.8
EADC1_CH4
May 08, 2020
Page 218 of 523
Rev 3.00
M480
32 48 64 Pin Name
Pin Pin Pin
MFP
Description
EBI_ALE
O
MFP2
EBI address latch enable output pin.
SPI2_MOSI
I/O
MFP4
SPI2 MOSI (Master Out, Slave In) pin.
UART1_RXD
I
MFP7
UART1 data receiver input pin.
UART7_RXD
I
MFP8
UART7 data receiver input pin.
BPWM0_CH3
I/O
MFP9
BPWM0 channel 3 output/capture input.
QEI1_B
I
MFP10
Quadrature encoder 1 phase B input
ECAP0_IC2
I
MFP11
Enhanced capture unit 0 input 2 pin.
I/O
MFP13
Timer3 external capture input/toggle output pin.
I
MFP15
External interrupt 4 input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR19
O
MFP2
EBI address bus bit 19.
SC0_CLK
O
MFP3
Smart Card 0 clock pin.
I2S0_LRCK
O
MFP4
I2S0 left right channel clock output pin.
SPI0_MOSI
I/O
MFP5
SPI0 MOSI (Master Out, Slave In) pin.
UART4_RXD
I
MFP6
UART4 data receiver input pin.
EBI_nCS0
O
MFP7
EBI chip select 0 output pin.
CAN2_RXD
I
MFP8
CAN2 bus receiver input.
TAMPER0
I/O
MFP10
TAMPER detector loop pin 0.
13 VBAT
P
MFP0
Power supply by batteries for RTC.
14 PF.5
I/O
MFP0
General purpose digital I/O pin.
UART2_RXD
I
MFP2
UART2 data receiver input pin.
UART2_nCTS
I
MFP4
UART2 clear to Send input pin.
EPWM0_CH0
I/O
MFP7
EPWM0 channel 0 output/capture input.
BPWM0_CH4
I/O
MFP8
BPWM0 channel 4 output/capture input.
EPWM0_SYNC_OUT
O
MFP9
EPWM0 counter synchronous trigger output pin.
X32_IN
I
MFP10
External 32.768 kHz crystal input pin.
EADC0_ST
I
MFP11
EADC0 external trigger input.
I/O
MFP0
General purpose digital I/O pin.
UART2_TXD
O
MFP2
UART2 data transmitter output pin.
UART2_nRTS
O
MFP4
UART2 request to Send output pin.
EPWM0_CH1
I/O
MFP7
EPWM0 channel 1 output/capture input.
BPWM0_CH5
I/O
MFP8
BPWM0 channel 5 output/capture input.
X32_OUT
O
MFP10
External 32.768 kHz crystal output pin.
EADC1_ST
I
MFP11
EADC1 external trigger input.
TM3_EXT
INT4
12 PF.6
7
8
11
12
15 PF.4
May 08, 2020
Page 219 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
32 48 64 Pin Name
Pin Pin Pin
9
13
Type
MFP
Description
I/O
MFP0
General purpose digital I/O pin.
EBI_nCS0
O
MFP2
EBI chip select 0 output pin.
UART0_TXD
O
MFP3
UART0 data transmitter output pin.
I2C0_SCL
I/O
MFP4
I2C0 clock pin.
I
MFP10
External 4~24 MHz (high speed) crystal input pin.
I/O
MFP11
BPWM1 channel 0 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_nCS1
O
MFP2
EBI chip select 1 output pin.
UART0_RXD
I
MFP3
UART0 data receiver input pin.
I C0_SDA
I/O
MFP4
I2C0 data input/output pin.
QSPI0_CLK
I/O
MFP5
Quad SPI0 serial clock pin.
XT1_OUT
O
MFP10
External 4~24 MHz (high speed) crystal output pin.
BPWM1_CH1
I/O
MFP11
BPWM1 channel 1 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD9
I/O
MFP2
EBI address/data bus bit 9.
SPI1_MISO
I/O
MFP4
SPI1 MISO (Master In, Slave Out) pin.
UART4_TXD
O
MFP5
UART4 data transmitter output pin.
UART0_nCTS
I
MFP7
UART0 clear to Send input pin.
I C1_SMBAL
O
MFP8
I2C1 SMBus SMBALTER pin
UART6_TXD
O
MFP9
UART6 data transmitter output pin.
EPWM1_CH2
I/O
MFP11
EPWM1 channel 2 output/capture input.
BPWM1_CH0
I/O
MFP12
BPWM1 channel 0 output/capture input.
TM0
I/O
MFP14
Timer0 event counter input/toggle output pin.
INT3
I
MFP15
External interrupt 3 input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD8
I/O
MFP2
EBI address/data bus bit 8.
SPI1_MOSI
I/O
MFP4
SPI1 MOSI (Master Out, Slave In) pin.
UART4_RXD
I
MFP5
UART4 data receiver input pin.
UART0_nRTS
O
MFP7
UART0 request to Send output pin.
I C1_SMBSUS
O
MFP8
I2C1 SMBus SMBSUS pin (PMBus CONTROL pin)
UART6_RXD
I
MFP9
UART6 data receiver input pin.
EPWM1_CH3
I/O
MFP11
EPWM1 channel 3 output/capture input.
BPWM1_CH1
I/O
MFP12
BPWM1 channel 1 output/capture input.
TM1
I/O
MFP14
Timer1 event counter input/toggle output pin.
16 PF.3
XT1_IN
BPWM1_CH0
10
14
17 PF.2
2
18 PC.7
2
M480 SERIES DATASHEET
19 PC.6
2
May 08, 2020
Page 220 of 523
Rev 3.00
M480
32 48 64 Pin Name
Pin Pin Pin
MFP
I
MFP15
External interrupt 2 input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD7
I/O
MFP2
EBI address/data bus bit 7.
SPI1_CLK
I/O
MFP4
SPI1 serial clock pin.
UART0_TXD
O
MFP7
UART0 data transmitter output pin.
I2C1_SCL
I/O
MFP8
I2C1 clock pin.
QSPI1_MISO1
I/O
MFP9
Quad SPI1 MISO1 (Master In, Slave Out) pin.
EPWM1_CH4
I/O
MFP11
EPWM1 channel 4 output/capture input.
BPWM1_CH2
I/O
MFP12
BPWM1 channel 2 output/capture input.
ACMP0_WLAT
I
MFP13
Analog comparator 0 window latch input pin
TM2
I/O
MFP14
Timer2 event counter input/toggle output pin.
INT1
I
MFP15
External interrupt 1 input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD6
I/O
MFP2
EBI address/data bus bit 6.
SPI1_SS
I/O
MFP4
SPI1 slave select pin.
I
MFP7
UART0 data receiver input pin.
I C1_SDA
I/O
MFP8
I2C1 data input/output pin.
QSPI1_MOSI1
I/O
MFP9
Quad SPI1 MOSI1 (Master Out, Slave In) pin.
EPWM1_CH5
I/O
MFP11
EPWM1 channel 5 output/capture input.
BPWM1_CH3
I/O
MFP12
BPWM1 channel 3 output/capture input.
ACMP1_WLAT
I
MFP13
Analog comparator 1 window latch input pin
TM3
I/O
MFP14
Timer3 event counter input/toggle output pin.
INT0
I
MFP15
External interrupt 0 input pin.
22 VSS
P
MFP0
Ground pin for digital circuit.
23 VDD
P
MFP0
Power supply for I/O ports and LDO source for internal PLL
and digital circuit.
24 LDO_CAP
A
MFP0
LDO output pin.
INT2
15
16
20 PA.7
21 PA.6
UART0_RXD
2
Description
Note: This pin needs to be connected with an external
capacitor.
17
25 PA.5
I/O
MFP0
General purpose digital I/O pin.
QSPI0_MISO1
I/O
MFP3
Quad SPI0 MISO1 (Master In, Slave Out) pin.
SPI1_I2SMCLK
I/O
MFP4
SPI1 I2S master clock output pin
UART0_nCTS
I
MFP7
UART0 clear to Send input pin.
UART5_TXD
O
MFP8
UART5 data transmitter output pin.
I/O
MFP9
I2C0 clock pin.
2
I C0_SCL
May 08, 2020
Page 221 of 523
Rev 3.00
M480 SERIES DATASHEET
Type
M480
32 48 64 Pin Name
Pin Pin Pin
18
Type
MFP
CAN0_TXD
O
MFP10
CAN0 bus transmitter output.
UART0_TXD
O
MFP11
UART0 data transmitter output pin.
BPWM0_CH5
I/O
MFP12
BPWM0 channel 5 output/capture input.
EPWM0_CH0
I/O
MFP13
EPWM0 channel 0 output/capture input.
QEI0_INDEX
I
MFP14
Quadrature encoder 0 index input
I/O
MFP0
General purpose digital I/O pin.
QSPI0_MOSI1
I/O
MFP3
Quad SPI0 MOSI1 (Master Out, Slave In) pin.
SPI0_I2SMCLK
I/O
MFP4
SPI0 I2S master clock output pin
SC0_nCD
I
MFP6
Smart Card 0 card detect pin.
UART0_nRTS
O
MFP7
UART0 request to Send output pin.
UART5_RXD
I
MFP8
UART5 data receiver input pin.
I/O
MFP9
I2C0 data input/output pin.
CAN0_RXD
I
MFP10
CAN0 bus receiver input.
UART0_RXD
I
MFP11
UART0 data receiver input pin.
BPWM0_CH4
I/O
MFP12
BPWM0 channel 4 output/capture input.
EPWM0_CH1
I/O
MFP13
EPWM0 channel 1 output/capture input.
I
MFP14
Quadrature encoder 0 phase A input
I/O
MFP0
General purpose digital I/O pin.
QSPI0_SS
I/O
MFP3
Quad SPI0 slave select pin.
SPI0_SS
I/O
MFP4
SPI0 slave select pin.
SC0_PWR
O
MFP6
Smart Card 0 power pin.
UART4_TXD
O
MFP7
UART4 data transmitter output pin.
UART1_TXD
O
MFP8
UART1 data transmitter output pin.
I2C1_SCL
I/O
MFP9
I2C1 clock pin.
I2C0_SMBAL
O
MFP10
I2C0 SMBus SMBALTER pin
BPWM0_CH3
I/O
MFP12
BPWM0 channel 3 output/capture input.
EPWM0_CH2
I/O
MFP13
EPWM0 channel 2 output/capture input.
QEI0_B
I
MFP14
Quadrature encoder 0 phase B input
EPWM1_BRAKE1
I
MFP15
EPWM1 Brake 1 input pin.
I/O
MFP0
General purpose digital I/O pin.
QSPI0_CLK
I/O
MFP3
Quad SPI0 serial clock pin.
SPI0_CLK
I/O
MFP4
SPI0 serial clock pin.
SC0_RST
O
MFP6
Smart Card 0 reset pin.
UART4_RXD
I
MFP7
UART4 data receiver input pin.
26 PA.4
2
I C0_SDA
QEI0_A
11
19
M480 SERIES DATASHEET
12
20
27 PA.3
28 PA.2
May 08, 2020
Description
Page 222 of 523
Rev 3.00
M480
32 48 64 Pin Name
Pin Pin Pin
MFP
Description
I
MFP8
UART1 data receiver input pin.
I2C1_SDA
I/O
MFP9
I2C1 data input/output pin.
I2C0_SMBSUS
O
MFP10
I2C0 SMBus SMBSUS pin (PMBus CONTROL pin)
BPWM0_CH2
I/O
MFP12
BPWM0 channel 2 output/capture input.
EPWM0_CH3
I/O
MFP13
EPWM0 channel 3 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
QSPI0_MISO0
I/O
MFP3
Quad SPI0 MISO0 (Master In, Slave Out) pin.
SPI0_MISO
I/O
MFP4
SPI0 MISO (Master In, Slave Out) pin.
SC0_DAT
I/O
MFP6
Smart Card 0 data pin.
UART0_TXD
O
MFP7
UART0 data transmitter output pin.
UART1_nCTS
I
MFP8
UART1 clear to Send input pin.
I/O
MFP9
I2C2 clock pin.
CCAP_DATA7
I
MFP10
Camera capture data input bus bit 7.
BPWM0_CH1
I/O
MFP12
BPWM0 channel 1 output/capture input.
EPWM0_CH4
I/O
MFP13
EPWM0 channel 4 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
QSPI0_MOSI0
I/O
MFP3
Quad SPI0 MOSI0 (Master Out, Slave In) pin.
SPI0_MOSI
I/O
MFP4
SPI0 MOSI (Master Out, Slave In) pin.
SC0_CLK
O
MFP6
Smart Card 0 clock pin.
UART0_RXD
I
MFP7
UART0 data receiver input pin.
UART1_nRTS
O
MFP8
UART1 request to Send output pin.
I2C2_SDA
I/O
MFP9
I2C2 data input/output pin.
CCAP_DATA6
I
MFP10
Camera capture data input bus bit 6.
BPWM0_CH0
I/O
MFP12
BPWM0 channel 0 output/capture input.
EPWM0_CH5
I/O
MFP13
EPWM0 channel 5 output/capture input.
I
MFP15
DAC0 external trigger input.
UART1_RXD
13
21
29 PA.1
2
I C2_SCL
14
22
30 PA.0
DAC0_ST
M480 SERIES DATASHEET
Type
15
23
31 VDDIO
P
MFP0
Power supply for PA.0~PA.5.
16
24
32 nRESET
I
MFP0
External reset input: active LOW, with an internal pull-up.
Set this pin low reset to initial state.
Note: It is recommended to use 10 kΩ pull-up resistor and
10 uF capacitor on nRESET pin.
17
25
33 PF.0
I/O
MFP0
General purpose digital I/O pin.
UART1_TXD
O
MFP2
UART1 data transmitter output pin.
I2C1_SCL
I/O
MFP3
I2C1 clock pin.
UART0_TXD
O
MFP4
UART0 data transmitter output pin.
May 08, 2020
Page 223 of 523
Rev 3.00
M480
32 48 64 Pin Name
Pin Pin Pin
Type
MFP
Description
BPWM1_CH0
I/O
MFP12
BPWM1 channel 0 output/capture input.
ICE_DAT
I/O
MFP14
Serial wired debugger data pin.
Note: It is recommended to use 100 kΩ pull-up resistor on
ICE_DAT pin.
18
26
34 PF.1
I/O
MFP0
General purpose digital I/O pin.
I
MFP2
UART1 data receiver input pin.
I/O
MFP3
I2C1 data input/output pin.
UART0_RXD
I
MFP4
UART0 data receiver input pin.
BPWM1_CH1
I/O
MFP12
BPWM1 channel 1 output/capture input.
ICE_CLK
I/O
MFP14
Serial wired debugger clock pin.
UART1_RXD
I2C1_SDA
Note: It is recommended to use 100 kΩ pull-up resistor on
ICE_CLK pin.
27
35 PC.5
I/O
MFP0
General purpose digital I/O pin.
EBI_AD5
I/O
MFP2
EBI address/data bus bit 5.
QSPI0_MISO1
I/O
MFP4
Quad SPI0 MISO1 (Master In, Slave Out) pin.
UART2_TXD
O
MFP8
UART2 data transmitter output pin.
I C1_SCL
I/O
MFP9
I2C1 clock pin.
CAN0_TXD
O
MFP10
CAN0 bus transmitter output.
UART4_TXD
O
MFP11
UART4 data transmitter output pin.
EPWM1_CH0
I/O
MFP12
EPWM1 channel 0 output/capture input.
CCAP_DATA5
I
MFP13
Camera capture data input bus bit 5.
I/O
MFP14
Quad SPI1 slave select pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD4
I/O
MFP2
EBI address/data bus bit 4.
QSPI0_MOSI1
I/O
MFP4
Quad SPI0 MOSI1 (Master Out, Slave In) pin.
I2S0_BCLK
O
MFP6
I2S0 bit clock output pin.
SPI1_I2SMCLK
I/O
MFP7
SPI1 I2S master clock output pin
I
MFP8
UART2 data receiver input pin.
I/O
MFP9
I2C1 data input/output pin.
CAN0_RXD
I
MFP10
CAN0 bus receiver input.
UART4_RXD
I
MFP11
UART4 data receiver input pin.
EPWM1_CH1
I/O
MFP12
EPWM1 channel 1 output/capture input.
CCAP_DATA4
I
MFP13
Camera capture data input bus bit 4.
I/O
MFP14
Quad SPI1 serial clock pin.
I/O
MFP0
General purpose digital I/O pin.
2
M480 SERIES DATASHEET
QSPI1_SS
28
36 PC.4
UART2_RXD
I2C1_SDA
QSPI1_CLK
29
37 PC.3
May 08, 2020
Page 224 of 523
Rev 3.00
M480
32 48 64 Pin Name
Pin Pin Pin
MFP
Description
EBI_AD3
I/O
MFP2
EBI address/data bus bit 3.
QSPI0_SS
I/O
MFP4
Quad SPI0 slave select pin.
I S0_MCLK
O
MFP6
I2S0 master clock output pin.
SPI1_MISO
I/O
MFP7
SPI1 MISO (Master In, Slave Out) pin.
UART2_nRTS
O
MFP8
UART2 request to Send output pin.
I2C0_SMBAL
O
MFP9
I2C0 SMBus SMBALTER pin
CAN1_TXD
O
MFP10
CAN1 bus transmitter output.
UART3_TXD
O
MFP11
UART3 data transmitter output pin.
EPWM1_CH2
I/O
MFP12
EPWM1 channel 2 output/capture input.
CCAP_DATA3
I
MFP13
Camera capture data input bus bit 3.
QSPI1_MISO0
I/O
MFP14
Quad SPI1 MISO0 (Master In, Slave Out) pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD2
I/O
MFP2
EBI address/data bus bit 2.
QSPI0_CLK
I/O
MFP4
Quad SPI0 serial clock pin.
I
MFP6
I2S0 data input pin.
I/O
MFP7
SPI1 MOSI (Master Out, Slave In) pin.
UART2_nCTS
I
MFP8
UART2 clear to Send input pin.
I2C0_SMBSUS
O
MFP9
I2C0 SMBus SMBSUS pin (PMBus CONTROL pin)
CAN1_RXD
I
MFP10
CAN1 bus receiver input.
UART3_RXD
I
MFP11
UART3 data receiver input pin.
EPWM1_CH3
I/O
MFP12
EPWM1 channel 3 output/capture input.
CCAP_DATA2
I
MFP13
Camera capture data input bus bit 2.
QSPI1_MOSI0
I/O
MFP14
Quad SPI1 MOSI0 (Master Out, Slave In) pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD1
I/O
MFP2
EBI address/data bus bit 1.
QSPI0_MISO0
I/O
MFP4
Quad SPI0 MISO0 (Master In, Slave Out) pin.
I2S0_DO
O
MFP6
I2S0 data output pin.
SPI1_CLK
I/O
MFP7
SPI1 serial clock pin.
UART2_TXD
O
MFP8
UART2 data transmitter output pin.
I C0_SCL
I/O
MFP9
I2C0 clock pin.
CAN2_TXD
O
MFP10
CAN2 bus transmitter output.
EPWM1_CH4
I/O
MFP12
EPWM1 channel 4 output/capture input.
CCAP_DATA1
I
MFP13
Camera capture data input bus bit 1.
ACMP0_O
O
MFP14
Analog comparator 0 output pin.
2
30
38 PC.2
I2S0_DI
SPI1_MOSI
19
31
39 PC.1
2
May 08, 2020
Page 225 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
32 48 64 Pin Name
Pin Pin Pin
Type
MFP
I
MFP15
EADC0 external trigger input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD0
I/O
MFP2
EBI address/data bus bit 0.
QSPI0_MOSI0
I/O
MFP4
Quad SPI0 MOSI0 (Master Out, Slave In) pin.
I S0_LRCK
O
MFP6
I2S0 left right channel clock output pin.
SPI1_SS
I/O
MFP7
SPI1 slave select pin.
I
MFP8
UART2 data receiver input pin.
I/O
MFP9
I2C0 data input/output pin.
I
MFP10
CAN2 bus receiver input.
EPWM1_CH5
I/O
MFP12
EPWM1 channel 5 output/capture input.
CCAP_DATA0
I
MFP13
Camera capture data input bus bit 0.
ACMP1_O
O
MFP14
Analog comparator 1 output pin.
EADC1_ST
I
MFP15
EADC1 external trigger input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD10
I/O
MFP2
EBI address/data bus bit 10.
SPI0_SS
I/O
MFP4
SPI0 slave select pin.
UART3_nRTS
O
MFP5
UART3 request to Send output pin.
UART0_TXD
O
MFP9
UART0 data transmitter output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD11
I/O
MFP2
EBI address/data bus bit 11.
SPI0_CLK
I/O
MFP4
SPI0 serial clock pin.
UART3_nCTS
I
MFP5
UART3 clear to Send input pin.
UART0_RXD
I
MFP9
UART0 data receiver input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD12
I/O
MFP2
EBI address/data bus bit 12.
SPI0_MISO
I/O
MFP4
SPI0 MISO (Master In, Slave Out) pin.
UART3_TXD
O
MFP5
UART3 data transmitter output pin.
I/O
MFP6
I2C2 clock pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD13
I/O
MFP2
EBI address/data bus bit 13.
SPI0_MOSI
I/O
MFP4
SPI0 MOSI (Master Out, Slave In) pin.
I
MFP5
UART3 data receiver input pin.
I2C2_SDA
I/O
MFP6
I2C2 data input/output pin.
TM2
I/O
MFP14
Timer2 event counter input/toggle output pin.
EADC0_ST
20
32
40 PC.0
2
UART2_RXD
2
I C0_SDA
CAN2_RXD
41 PD.3
42 PD.2
M480 SERIES DATASHEET
43 PD.1
2
I C2_SCL
44 PD.0
UART3_RXD
May 08, 2020
Description
Page 226 of 523
Rev 3.00
M480
32 48 64 Pin Name
Pin Pin Pin
21
22
33
34
MFP
Description
I/O
MFP0
General purpose digital I/O pin.
I2S0_BCLK
O
MFP2
I2S0 bit clock output pin.
UART4_TXD
O
MFP3
UART4 data transmitter output pin.
I2C1_SCL
I/O
MFP4
I2C1 clock pin.
SPI2_SS
I/O
MFP5
SPI2 slave select pin.
CAN0_TXD
O
MFP6
CAN0 bus transmitter output.
BPWM1_CH2
I/O
MFP11
BPWM1 channel 2 output/capture input.
QEI1_INDEX
I
MFP12
Quadrature encoder 1 index input
USB_VBUS
P
MFP14
Power supply from USB host or HUB.
I/O
MFP0
General purpose digital I/O pin.
I2S0_MCLK
O
MFP2
I2S0 master clock output pin.
UART4_RXD
I
MFP3
UART4 data receiver input pin.
I2C1_SDA
I/O
MFP4
I2C1 data input/output pin.
SPI2_CLK
I/O
MFP5
SPI2 serial clock pin.
I
MFP6
CAN0 bus receiver input.
I/O
MFP11
BPWM1 channel 3 output/capture input.
QEI1_A
I
MFP12
Quadrature encoder 1 phase A input
USB_D-
A
MFP14
USB differential signal D-.
I/O
MFP0
General purpose digital I/O pin.
I2S0_DI
I
MFP2
I2S0 data input pin.
UART0_TXD
O
MFP3
UART0 data transmitter output pin.
SPI2_MISO
I/O
MFP5
SPI2 MISO (Master In, Slave Out) pin.
I C2_SCL
I/O
MFP6
I2C2 clock pin.
BPWM1_CH4
I/O
MFP11
BPWM1 channel 4 output/capture input.
QEI1_B
I
MFP12
Quadrature encoder 1 phase B input
USB_D+
A
MFP14
USB differential signal D+.
48 PA.15
I/O
MFP0
General purpose digital I/O pin.
2
I S0_DO
O
MFP2
I2S0 data output pin.
UART0_RXD
I
MFP3
UART0 data receiver input pin.
SPI2_MOSI
I/O
MFP5
SPI2 MOSI (Master Out, Slave In) pin.
I2C2_SDA
I/O
MFP6
I2C2 data input/output pin.
BPWM1_CH5
I/O
MFP11
BPWM1 channel 5 output/capture input.
EPWM0_SYNC_IN
I
MFP12
EPWM0 counter synchronous trigger input pin.
USB_OTG_ID
I
MFP14
USB_ identification.
45 PA.12
46 PA.13
CAN0_RXD
BPWM1_CH3
23
35
47 PA.14
2
24
36
May 08, 2020
Page 227 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
32 48 64 Pin Name
Pin Pin Pin
Type
MFP
Description
25
37
49 VSS
P
MFP0
Ground pin for digital circuit.
26
38
50 LDO_CAP
A
MFP0
LDO output pin.
Note: This pin needs to be connected with an external
capacitor.
27
P
MFP0
Power supply for I/O ports and LDO source for internal PLL
and digital circuit.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD11
I/O
MFP2
EBI address/data bus bit 11.
SPI0_I2SMCLK
I/O
MFP4
SPI0 I2S master clock output pin
QSPI0_CLK
I/O
MFP6
Quad SPI0 serial clock pin.
EPWM0_SYNC_IN
I
MFP11
EPWM0 counter synchronous trigger input pin.
ETM_TRACE_CLK
I
MFP12
ETM receiver Trace Clock input pin
I/O
MFP13
Timer1 event counter input/toggle output pin.
I
MFP14
USB external VBUS regulator status pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH15
A
MFP1
EADC0 channel 15 analog input.
EADC1_CH15
A
MFP1
EADC1 channel 15 analog input.
EBI_AD12
I/O
MFP2
EBI address/data bus bit 12.
SPI0_SS
I/O
MFP4
SPI0 slave select pin.
UART0_nCTS
I
MFP6
UART0 clear to Send input pin.
UART3_TXD
O
MFP7
UART3 data transmitter output pin.
I C2_SMBAL
O
MFP8
I2C2 SMBus SMBALTER pin
EPWM0_BRAKE1
I
MFP10
EPWM0 Brake 1 input pin.
I/O
MFP11
EPWM1 channel 0 output/capture input.
I
MFP12
ETM receiver Trace Data 0 input pin
TM0_EXT
I/O
MFP13
Timer0 external capture input/toggle output pin.
USB_VBUS_EN
O
MFP14
USB external VBUS regulator enable pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH14
A
MFP1
EADC0 channel 14 analog input.
EADC1_CH14
A
MFP1
EADC1 channel 14 analog input.
EBI_AD13
I/O
MFP2
EBI address/data bus bit 13.
SPI0_CLK
I/O
MFP4
SPI0 serial clock pin.
UART0_nRTS
O
MFP6
UART0 request to Send output pin.
UART3_RXD
I
MFP7
UART3 data receiver input pin.
O
MFP8
I2C2 SMBus SMBSUS pin (PMBus CONTROL pin)
39
51 VDD
40
52 PC.14
TM1
USB_VBUS_ST
28
41
53 PB.15
M480 SERIES DATASHEET
2
EPWM1_CH0
ETM_TRACE_DATA0
29
42
54 PB.14
2
I C2_SMBSUS
May 08, 2020
Page 228 of 523
Rev 3.00
M480
32 48 64 Pin Name
Pin Pin Pin
MFP
I/O
MFP11
EPWM1 channel 1 output/capture input.
I
MFP12
ETM receiver Trace Data 1 input pin
TM1_EXT
I/O
MFP13
Timer1 external capture input/toggle output pin.
CLKO
O
MFP14
Clock Out
USB_VBUS_ST
I
MFP15
USB external VBUS regulator status pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH13
A
MFP1
EADC0 channel 13 analog input.
EADC1_CH13
A
MFP1
EADC1 channel 13 analog input.
ACMP0_P3
A
MFP1
Analog comparator 0 positive input 3 pin.
ACMP1_P3
A
MFP1
Analog comparator 1 positive input 3 pin.
EBI_AD14
I/O
MFP2
EBI address/data bus bit 14.
SPI0_MISO
I/O
MFP4
SPI0 MISO (Master In, Slave Out) pin.
UART0_TXD
O
MFP6
UART0 data transmitter output pin.
UART3_nRTS
O
MFP7
UART3 request to Send output pin.
I2C2_SCL
I/O
MFP8
I2C2 clock pin.
I
MFP10
Camera capture interface pix clock input pin.
I/O
MFP11
EPWM1 channel 2 output/capture input.
I
MFP12
ETM receiver Trace Data 2 input pin
I/O
MFP13
Timer2 external capture input/toggle output pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH12
A
MFP1
EADC0 channel 12 analog input.
EADC1_CH12
A
MFP1
EADC1 channel 12 analog input.
DAC0_OUT
A
MFP1
DAC0 channel analog output.
ACMP0_P2
A
MFP1
Analog comparator 0 positive input 2 pin.
ACMP1_P2
A
MFP1
Analog comparator 1 positive input 2 pin.
EBI_AD15
I/O
MFP2
EBI address/data bus bit 15.
SPI0_MOSI
I/O
MFP4
SPI0 MOSI (Master Out, Slave In) pin.
UART0_RXD
I
MFP6
UART0 data receiver input pin.
UART3_nCTS
I
MFP7
UART3 clear to Send input pin.
I C2_SDA
I/O
MFP8
I2C2 data input/output pin.
SD0_nCD
I
MFP9
SD/SDIO0 card detect input pin
CCAP_SCLK
O
MFP10
Camera capture interface sensor clock pin.
EPWM1_CH3
I/O
MFP11
EPWM1 channel 3 output/capture input.
I
MFP12
ETM receiver Trace Data 3 input pin
EPWM1_CH1
ETM_TRACE_DATA1
30
43
55 PB.13
CCAP_PIXCLK
EPWM1_CH2
ETM_TRACE_DATA2
TM2_EXT
31
44
56 PB.12
2
ETM_TRACE_DATA3
May 08, 2020
Description
Page 229 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
32 48 64 Pin Name
Pin Pin Pin
Type
MFP
I/O
MFP13
Timer3 external capture input/toggle output pin.
57 AVDD
P
MFP0
Power supply for internal analog circuit.
58 VREF
A
MFP0
ADC reference voltage input.
TM3_EXT
32
45
Description
Note: This pin needs to be connected with a 1uF capacitor.
46
59 AVSS
P
MFP0
Ground pin for analog circuit.
60 PB.11
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH11
A
MFP1
EADC0 channel 11 analog input.
EBI_ADR16
O
MFP2
EBI address bus bit 16.
UART0_nCTS
I
MFP5
UART0 clear to Send input pin.
UART4_TXD
O
MFP6
UART4 data transmitter output pin.
I2C1_SCL
I/O
MFP7
I2C1 clock pin.
CAN0_TXD
O
MFP8
CAN0 bus transmitter output.
SPI0_I2SMCLK
I/O
MFP9
SPI0 I2S master clock output pin
BPWM1_CH0
I/O
MFP10
BPWM1 channel 0 output/capture input.
I
MFP12
Camera capture interface SFIELD input pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH10
A
MFP1
EADC0 channel 10 analog input.
EBI_ADR17
O
MFP2
EBI address bus bit 17.
UART0_nRTS
O
MFP5
UART0 request to Send output pin.
UART4_RXD
I
MFP6
UART4 data receiver input pin.
I/O
MFP7
I2C1 data input/output pin.
I
MFP8
CAN0 bus receiver input.
BPWM1_CH1
I/O
MFP10
BPWM1 channel 1 output/capture input.
CCAP_VSYNC
I
MFP12
Camera capture interface vsync input pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH9
A
MFP1
EADC0 channel 9 analog input.
EBI_ADR18
O
MFP2
EBI address bus bit 18.
UART0_TXD
O
MFP5
UART0 data transmitter output pin.
UART1_nCTS
I
MFP6
UART1 clear to Send input pin.
I2C1_SMBAL
O
MFP7
I2C1 SMBus SMBALTER pin
UART7_TXD
O
MFP8
UART7 data transmitter output pin.
I C0_SCL
I/O
MFP9
I2C0 clock pin.
BPWM1_CH2
I/O
MFP10
BPWM1 channel 2 output/capture input.
CAN2_TXD
O
MFP12
CAN2 bus transmitter output.
CCAP_SFIELD
61 PB.10
M480 SERIES DATASHEET
I2C1_SDA
CAN0_RXD
62 PB.9
2
May 08, 2020
Page 230 of 523
Rev 3.00
M480
32 48 64 Pin Name
Pin Pin Pin
MFP
INT7
I
MFP13
External interrupt 7 input pin.
CCAP_HSYNC
I
MFP14
Camera capture interface hsync input pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH8
A
MFP1
EADC0 channel 8 analog input.
EBI_ADR19
O
MFP2
EBI address bus bit 19.
UART0_RXD
I
MFP5
UART0 data receiver input pin.
UART1_nRTS
O
MFP6
UART1 request to Send output pin.
I C1_SMBSUS
O
MFP7
I2C1 SMBus SMBSUS pin (PMBus CONTROL pin)
UART7_RXD
I
MFP8
UART7 data receiver input pin.
I C0_SDA
I/O
MFP9
I2C0 data input/output pin.
BPWM1_CH3
I/O
MFP10
BPWM1 channel 3 output/capture input.
CAN2_RXD
I
MFP12
CAN2 bus receiver input.
INT6
I
MFP13
External interrupt 6 input pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH7
A
MFP1
EADC0 channel 7 analog input.
EBI_nWRL
O
MFP2
EBI low byte write enable output pin.
CAN1_TXD
O
MFP5
CAN1 bus transmitter output.
UART1_TXD
O
MFP6
UART1 data transmitter output pin.
EBI_nCS0
O
MFP8
EBI chip select 0 output pin.
BPWM1_CH4
I/O
MFP10
BPWM1 channel 4 output/capture input.
I
MFP11
EPWM1 Brake 0 input pin.
I/O
MFP12
EPWM1 channel 4 output/capture input.
INT5
I
MFP13
External interrupt 5 input pin.
USB_VBUS_ST
I
MFP14
USB external VBUS regulator status pin.
ACMP0_O
O
MFP15
Analog comparator 0 output pin.
63 PB.8
2
2
47
64 PB.7
EPWM1_BRAKE0
EPWM1_CH4
May 08, 2020
Description
Page 231 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
4.3.2
M482 Series Pin Description
Note: PA.15 MFP can only be as USB_OTG_ID when enable full-Speed USB.
32 48 64 128 Pin Name
Pin Pin Pin Pin
1
1
2
1
Type
MFP
Description
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH5
A
MFP1
EADC0 channel 5 analog input.
ACMP1_N
A
MFP1
Analog comparator 1 negative input pin.
EBI_ADR0
O
MFP2
EBI address bus bit 0.
SD0_DAT3
I/O
MFP3
SD/SDIO0 data line bit 3.
SPI1_MISO
I/O
MFP5
SPI1 MISO (Master In, Slave Out) pin.
I C0_SCL
I/O
MFP6
I2C0 clock pin.
UART5_TXD
O
MFP7
UART5 data transmitter output pin.
SC0_CLK
O
MFP9
Smart Card 0 clock pin.
I S0_BCLK
O
MFP10
I2S0 bit clock output pin.
EPWM0_CH0
I/O
MFP11
EPWM0 channel 0 output/capture input.
UART2_TXD
O
MFP12
UART2 data transmitter output pin.
TM0
I/O
MFP14
Timer0 event counter input/toggle output pin.
INT0
I
MFP15
External interrupt 0 input pin.
PB.4
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH4
A
MFP1
EADC0 channel 4 analog input.
ACMP1_P1
A
MFP1
Analog comparator 1 positive input 1 pin.
EBI_ADR1
O
MFP2
EBI address bus bit 1.
SD0_DAT2
I/O
MFP3
SD/SDIO0 data line bit 2.
SPI1_MOSI
I/O
MFP5
SPI1 MOSI (Master Out, Slave In) pin.
I/O
MFP6
I2C0 data input/output pin.
I
MFP7
UART5 data receiver input pin.
SC0_DAT
I/O
MFP9
Smart Card 0 data pin.
I2S0_MCLK
O
MFP10
I2S0 master clock output pin.
EPWM0_CH1
I/O
MFP11
EPWM0 channel 1 output/capture input.
UART2_RXD
I
MFP12
UART2 data receiver input pin.
TM1
I/O
MFP14
Timer1 event counter input/toggle output pin.
INT1
I
MFP15
External interrupt 1 input pin.
PB.3
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH3
A
MFP1
EADC0 channel 3 analog input.
EADC1_CH11
A
MFP1
EADC1 channel 11 analog input.
ACMP0_N
A
MFP1
Analog comparator 0 negative input pin.
PB.5
2
2
2
2
3
2
M480 SERIES DATASHEET
2
I C0_SDA
UART5_RXD
3
3
4
3
May 08, 2020
Page 232 of 523
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
4
4
5
4
MFP
Description
EBI_ADR2
O
MFP2
EBI address bus bit 2.
SD0_DAT1
I/O
MFP3
SD/SDIO0 data line bit 1.
SPI1_CLK
I/O
MFP5
SPI1 serial clock pin.
UART1_TXD
O
MFP6
UART1 data transmitter output pin.
UART5_nRTS
O
MFP7
UART5 request to Send output pin.
SC0_RST
O
MFP9
Smart Card 0 reset pin.
I2S0_DI
I
MFP10
I2S0 data input pin.
EPWM0_CH2
I/O
MFP11
EPWM0 channel 2 output/capture input.
I2C1_SCL
I/O
MFP12
I2C1 clock pin.
TM2
I/O
MFP14
Timer2 event counter input/toggle output pin.
INT2
I
MFP15
External interrupt 2 input pin.
PB.2
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH2
A
MFP1
EADC0 channel 2 analog input.
EADC1_CH10
A
MFP1
EADC1 channel 10 analog input.
ACMP0_P1
A
MFP1
Analog comparator 0 positive input 1 pin.
EBI_ADR3
O
MFP2
EBI address bus bit 3.
SD0_DAT0
I/O
MFP3
SD/SDIO0 data line bit 0.
SPI1_SS
I/O
MFP5
SPI1 slave select pin.
UART1_RXD
I
MFP6
UART1 data receiver input pin.
UART5_nCTS
I
MFP7
UART5 clear to Send input pin.
SC0_PWR
O
MFP9
Smart Card 0 power pin.
I2S0_DO
O
MFP10
I2S0 data output pin.
EPWM0_CH3
I/O
MFP11
EPWM0 channel 3 output/capture input.
I2C1_SDA
I/O
MFP12
I2C1 data input/output pin.
TM3
I/O
MFP14
Timer3 event counter input/toggle output pin.
INT3
I
MFP15
External interrupt 3 input pin.
PC.12
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR4
O
MFP2
EBI address bus bit 4.
UART0_TXD
O
MFP3
UART0 data transmitter output pin.
I C0_SCL
I/O
MFP4
I2C0 clock pin.
UART6_TXD
O
MFP5
UART6 data transmitter output pin.
SC0_nCD
I
MFP9
Smart Card 0 card detect pin.
ECAP1_IC2
I
MFP11
Enhanced capture unit 1 input 2 pin.
I/O
MFP12
EPWM1 channel 0 output/capture input.
2
EPWM1_CH0
May 08, 2020
Page 233 of 523
M480 SERIES DATASHEET
5
Type
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
6
Type
MFP
ACMP0_O
O
MFP14
Analog comparator 0 output pin.
PC.11
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR5
O
MFP2
EBI address bus bit 5.
UART0_RXD
I
MFP3
UART0 data receiver input pin.
I/O
MFP4
I2C0 data input/output pin.
UART6_RXD
I
MFP5
UART6 data receiver input pin.
ECAP1_IC1
I
MFP11
Enhanced capture unit 1 input 1 pin.
EPWM1_CH1
I/O
MFP12
EPWM1 channel 1 output/capture input.
ACMP1_O
O
MFP14
Analog comparator 1 output pin.
PC.10
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR6
O
MFP2
EBI address bus bit 6.
UART6_nRTS
O
MFP5
UART6 request to Send output pin.
UART3_TXD
O
MFP7
UART3 data transmitter output pin.
CAN1_TXD
O
MFP9
CAN1 bus transmitter output.
ECAP1_IC0
I
MFP11
Enhanced capture unit 1 input 0 pin.
I/O
MFP12
EPWM1 channel 2 output/capture input.
I
MFP14
EADC1 external trigger input.
PC.9
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR7
O
MFP2
EBI address bus bit 7.
UART6_nCTS
I
MFP5
UART6 clear to Send input pin.
UART3_RXD
I
MFP7
UART3 data receiver input pin.
CAN1_RXD
I
MFP9
CAN1 bus receiver input.
I/O
MFP12
EPWM1 channel 3 output/capture input.
I
MFP14
EADC1 external trigger input.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH1
A
MFP1
EADC0 channel 1 analog input.
EADC1_CH9
A
MFP1
EADC1 channel 9 analog input.
EBI_ADR8
O
MFP2
EBI address bus bit 8.
SD0_CLK
O
MFP3
SD/SDIO0 clock output pin
SPI1_I2SMCLK
I/O
MFP5
SPI1 I2S master clock output pin
UART2_TXD
O
MFP7
UART2 data transmitter output pin.
I C1_SCL
I/O
MFP9
I2C1 clock pin.
I2S0_LRCK
O
MFP10
I2S0 left right channel clock output pin.
EPWM0_CH4
I/O
MFP11
EPWM0 channel 4 output/capture input.
2
I C0_SDA
7
EPWM1_CH2
EADC1_ST
8
M480 SERIES DATASHEET
EPWM1_CH3
EADC1_ST
5
5
6
9
PB.1
2
May 08, 2020
Description
Page 234 of 523
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
MFP
I/O
MFP12
EPWM1 channel 4 output/capture input.
I
MFP13
EPWM0 Brake 0 input pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH0
A
MFP1
EADC0 channel 0 analog input.
EADC1_CH8
A
MFP1
EADC1 channel 8 analog input.
EBI_ADR9
O
MFP2
EBI address bus bit 9.
SD0_CMD
I/O
MFP3
SD/SDIO0 command/response pin
SPI2_I2SMCLK
I/O
MFP4
SPI2 I2S master clock output pin
I
MFP7
UART2 data receiver input pin.
SPI0_I2SMCLK
I/O
MFP8
SPI0 I2S master clock output pin
I2C1_SDA
I/O
MFP9
I2C1 data input/output pin.
EPWM0_CH5
I/O
MFP11
EPWM0 channel 5 output/capture input.
EPWM1_CH5
I/O
MFP12
EPWM1 channel 5 output/capture input.
I
MFP13
EPWM0 Brake 1 input pin.
11 VSS
P
MFP0
Ground pin for digital circuit.
12 VDD
P
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
I/O
MFP0
General purpose digital I/O pin.
EADC1_CH7
A
MFP1
EADC1 channel 7 analog input.
ACMP0_P0
A
MFP1
Analog comparator 0 positive input 0 pin.
EBI_nRD
O
MFP2
EBI read enable output pin.
SPI2_SS
I/O
MFP4
SPI2 slave select pin.
I C2_SCL
I/O
MFP7
I2C2 clock pin.
UART6_TXD
O
MFP8
UART6 data transmitter output pin.
BPWM0_CH0
I/O
MFP9
BPWM0 channel 0 output/capture input.
EPWM0_SYNC_OUT
O
MFP10
EPWM0 counter synchronous trigger output pin.
TM0_EXT
I/O
MFP13
Timer0 external capture input/toggle output pin.
I/O
MFP0
General purpose digital I/O pin.
EADC1_CH6
A
MFP1
EADC1 channel 6 analog input.
ACMP1_P0
A
MFP1
Analog comparator 1 positive input 0 pin.
EBI_nWR
O
MFP2
EBI write enable output pin.
SPI2_CLK
I/O
MFP4
SPI2 serial clock pin.
I2C2_SDA
I/O
MFP7
I2C2 data input/output pin.
I
MFP8
UART6 data receiver input pin.
EPWM1_CH4
EPWM0_BRAKE0
6
6
7
10 PB.0
UART2_RXD
EPWM0_BRAKE1
7
8
13 PA.11
2
8
9
14 PA.10
UART6_RXD
May 08, 2020
Description
Page 235 of 523
Rev 3.00
M480 SERIES DATASHEET
Type
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
9
10
10
11
Type
MFP
Description
BPWM0_CH1
I/O
MFP9
BPWM0 channel 1 output/capture input.
QEI1_INDEX
I
MFP10
Quadrature encoder 1 index input
ECAP0_IC0
I
MFP11
Enhanced capture unit 0 input 0 pin.
TM1_EXT
I/O
MFP13
Timer1 external capture input/toggle output pin.
DAC0_ST
I
MFP14
DAC0 external trigger input.
SWDH_CLK
O
MFP15
Serial Wire Debug Host Clock output
I/O
MFP0
General purpose digital I/O pin.
EADC1_CH5
A
MFP1
EADC1 channel 5 analog input.
EBI_MCLK
O
MFP2
EBI external clock output pin.
SPI2_MISO
I/O
MFP4
SPI2 MISO (Master In, Slave Out) pin.
UART1_TXD
O
MFP7
UART1 data transmitter output pin.
UART7_TXD
O
MFP8
UART7 data transmitter output pin.
BPWM0_CH2
I/O
MFP9
BPWM0 channel 2 output/capture input.
QEI1_A
I
MFP10
Quadrature encoder 1 phase A input
ECAP0_IC1
I
MFP11
Enhanced capture unit 0 input 1 pin.
TM2_EXT
I/O
MFP13
Timer2 external capture input/toggle output pin.
SWDH_DAT
I/O
MFP15
Serial Wire Debug Host Data input/output pin
I/O
MFP0
General purpose digital I/O pin.
EADC1_CH4
A
MFP1
EADC1 channel 4 analog input.
EBI_ALE
O
MFP2
EBI address latch enable output pin.
SPI2_MOSI
I/O
MFP4
SPI2 MOSI (Master Out, Slave In) pin.
UART1_RXD
I
MFP7
UART1 data receiver input pin.
UART7_RXD
I
MFP8
UART7 data receiver input pin.
BPWM0_CH3
I/O
MFP9
BPWM0 channel 3 output/capture input.
QEI1_B
I
MFP10
Quadrature encoder 1 phase B input
ECAP0_IC2
I
MFP11
Enhanced capture unit 0 input 2 pin.
I/O
MFP13
Timer3 external capture input/toggle output pin.
I
MFP15
External interrupt 4 input pin.
I/O
MFP0
General purpose digital I/O pin.
EADC1_CH3
A
MFP1
EADC1 channel 3 analog input.
EBI_ADR10
O
MFP2
EBI address bus bit 10.
SPI2_I2SMCLK
I/O
MFP4
SPI2 I2S master clock output pin
CAN1_TXD
O
MFP5
CAN1 bus transmitter output.
UART2_TXD
O
MFP7
UART2 data transmitter output pin.
15 PA.9
16 PA.8
M480 SERIES DATASHEET
TM3_EXT
INT4
17 PC.13
May 08, 2020
Page 236 of 523
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
MFP
Description
BPWM0_CH4
I/O
MFP9
BPWM0 channel 4 output/capture input.
CLKO
O
MFP13
Clock Out
EADC0_ST
I
MFP14
EADC0 external trigger input.
I/O
MFP0
General purpose digital I/O pin.
EADC1_CH2
A
MFP1
EADC1 channel 2 analog input.
EBI_nCS0
O
MFP2
EBI chip select 0 output pin.
CAN1_RXD
I
MFP5
CAN1 bus receiver input.
UART2_RXD
I
MFP7
UART2 data receiver input pin.
BPWM0_CH5
I/O
MFP9
BPWM0 channel 5 output/capture input.
QEI0_INDEX
I
MFP10
Quadrature encoder 0 index input
CLKO
O
MFP13
Clock Out
EADC0_ST
I
MFP14
EADC0 external trigger input.
INT5
I
MFP15
External interrupt 5 input pin.
I/O
MFP0
General purpose digital I/O pin.
EADC1_CH1
A
MFP1
EADC1 channel 1 analog input.
EBI_nCS1
O
MFP2
EBI chip select 1 output pin.
UART1_TXD
O
MFP3
UART1 data transmitter output pin.
CAN0_TXD
O
MFP4
CAN0 bus transmitter output.
QEI0_A
I
MFP10
Quadrature encoder 0 phase A input
INT6
I
MFP15
External interrupt 6 input pin.
I/O
MFP0
General purpose digital I/O pin.
EADC1_CH0
A
MFP1
EADC1 channel 0 analog input.
EBI_nCS2
O
MFP2
EBI chip select 2 output pin.
UART1_RXD
I
MFP3
UART1 data receiver input pin.
CAN0_RXD
I
MFP4
CAN0 bus receiver input.
QEI0_B
I
MFP10
Quadrature encoder 0 phase B input
INT7
I
MFP15
External interrupt 7 input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR11
O
MFP2
EBI address bus bit 11.
SPI2_SS
I/O
MFP3
SPI2 slave select pin.
I2C0_SMBAL
O
MFP4
I2C0 SMBus SMBALTER pin
I2C1_SCL
I/O
MFP5
I2C1 clock pin.
I
MFP7
Camera capture data input bus bit 7.
I/O
MFP13
Timer0 event counter input/toggle output pin.
18 PD.12
19 PD.11
20 PD.10
21 PG.2
CCAP_DATA7
TM0
May 08, 2020
Page 237 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
Type
MFP
Description
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR12
O
MFP2
EBI address bus bit 12.
SPI2_CLK
I/O
MFP3
SPI2 serial clock pin.
I2C0_SMBSUS
O
MFP4
I2C0 SMBus SMBSUS pin (PMBus CONTROL pin)
I2C1_SDA
I/O
MFP5
I2C1 data input/output pin.
I
MFP7
Camera capture data input bus bit 6.
TM1
I/O
MFP13
Timer1 event counter input/toggle output pin.
23 PG.4
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR13
O
MFP2
EBI address bus bit 13.
SPI2_MISO
I/O
MFP3
SPI2 MISO (Master In, Slave Out) pin.
I
MFP7
Camera capture data input bus bit 5.
I/O
MFP13
Timer2 event counter input/toggle output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR14
O
MFP2
EBI address bus bit 14.
SPI2_MOSI
I/O
MFP3
SPI2 MOSI (Master Out, Slave In) pin.
UART5_TXD
O
MFP6
UART5 data transmitter output pin.
CCAP_DATA4
I
MFP7
Camera capture data input bus bit 4.
I/O
MFP13
Timer3 event counter input/toggle output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR15
O
MFP2
EBI address bus bit 15.
SC0_nCD
I
MFP3
Smart Card 0 card detect pin.
I2S0_BCLK
O
MFP4
I2S0 bit clock output pin.
SPI0_I2SMCLK
I/O
MFP5
SPI0 I2S master clock output pin
UART5_RXD
I
MFP6
UART5 data receiver input pin.
CCAP_DATA3
I
MFP7
Camera capture data input bus bit 3.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR16
O
MFP2
EBI address bus bit 16.
SC0_PWR
O
MFP3
Smart Card 0 power pin.
I2S0_MCLK
O
MFP4
I2S0 master clock output pin.
SPI0_SS
I/O
MFP5
SPI0 slave select pin.
UART5_nRTS
O
MFP6
UART5 request to Send output pin.
CCAP_DATA2
I
MFP7
Camera capture data input bus bit 2.
CAN1_TXD
O
MFP8
CAN1 bus transmitter output.
I/O
MFP0
General purpose digital I/O pin.
22 PG.3
CCAP_DATA6
CCAP_DATA5
TM2
24 PF.11
TM3
25 PF.10
M480 SERIES DATASHEET
26 PF.9
27 PF.8
May 08, 2020
Page 238 of 523
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
MFP
Description
EBI_ADR17
O
MFP2
EBI address bus bit 17.
SC0_RST
O
MFP3
Smart Card 0 reset pin.
I
MFP4
I2S0 data input pin.
I/O
MFP5
SPI0 serial clock pin.
UART5_nCTS
I
MFP6
UART5 clear to Send input pin.
CCAP_DATA1
I
MFP7
Camera capture data input bus bit 1.
CAN1_RXD
I
MFP8
CAN1 bus receiver input.
TAMPER2
I/O
MFP10
TAMPER detector loop pin 2.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR18
O
MFP2
EBI address bus bit 18.
SC0_DAT
I/O
MFP3
Smart Card 0 data pin.
I S0_DO
O
MFP4
I2S0 data output pin.
SPI0_MISO
I/O
MFP5
SPI0 MISO (Master In, Slave Out) pin.
UART4_TXD
O
MFP6
UART4 data transmitter output pin.
CCAP_DATA0
I
MFP7
Camera capture data input bus bit 0.
CAN2_TXD
O
MFP8
CAN2 bus transmitter output.
TAMPER1
I/O
MFP10
TAMPER detector loop pin 1.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR19
O
MFP2
EBI address bus bit 19.
SC0_CLK
O
MFP3
Smart Card 0 clock pin.
I S0_LRCK
O
MFP4
I2S0 left right channel clock output pin.
SPI0_MOSI
I/O
MFP5
SPI0 MOSI (Master Out, Slave In) pin.
UART4_RXD
I
MFP6
UART4 data receiver input pin.
EBI_nCS0
O
MFP7
EBI chip select 0 output pin.
CAN2_RXD
I
MFP8
CAN2 bus receiver input.
TAMPER0
I/O
MFP10
TAMPER detector loop pin 0.
2
I S0_DI
SPI0_CLK
28 PF.7
2
12
29 PF.6
2
7
11
M480 SERIES DATASHEET
Type
13
30 VBAT
P
MFP0
Power supply by batteries for RTC.
14
31 PF.5
I/O
MFP0
General purpose digital I/O pin.
UART2_RXD
I
MFP2
UART2 data receiver input pin.
UART2_nCTS
I
MFP4
UART2 clear to Send input pin.
EPWM0_CH0
I/O
MFP7
EPWM0 channel 0 output/capture input.
BPWM0_CH4
I/O
MFP8
BPWM0 channel 4 output/capture input.
EPWM0_SYNC_OUT
O
MFP9
EPWM0 counter synchronous trigger output pin.
X32_IN
I
MFP10
External 32.768 kHz crystal input pin.
May 08, 2020
Page 239 of 523
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
Type
MFP
I
MFP11
EADC0 external trigger input.
I/O
MFP0
General purpose digital I/O pin.
UART2_TXD
O
MFP2
UART2 data transmitter output pin.
UART2_nRTS
O
MFP4
UART2 request to Send output pin.
EPWM0_CH1
I/O
MFP7
EPWM0 channel 1 output/capture input.
BPWM0_CH5
I/O
MFP8
BPWM0 channel 5 output/capture input.
X32_OUT
O
MFP10
External 32.768 kHz crystal output pin.
EADC1_ST
I
MFP11
EADC1 external trigger input.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR3
O
MFP2
EBI address bus bit 3.
SPI1_MISO
I/O
MFP3
SPI1 MISO (Master In, Slave Out) pin.
UART7_nRTS
O
MFP4
UART7 request to Send output pin.
UART6_TXD
O
MFP5
UART6 data transmitter output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR2
O
MFP2
EBI address bus bit 2.
SPI1_MOSI
I/O
MFP3
SPI1 MOSI (Master Out, Slave In) pin.
UART7_nCTS
I
MFP4
UART7 clear to Send input pin.
UART6_RXD
I
MFP5
UART6 data receiver input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR1
O
MFP2
EBI address bus bit 1.
SPI1_CLK
I/O
MFP3
SPI1 serial clock pin.
UART7_TXD
O
MFP4
UART7 data transmitter output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR0
O
MFP2
EBI address bus bit 0.
SPI1_SS
I/O
MFP3
SPI1 slave select pin.
I
MFP4
UART7 data receiver input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_nCS0
O
MFP2
EBI chip select 0 output pin.
UART0_TXD
O
MFP3
UART0 data transmitter output pin.
I/O
MFP4
I2C0 clock pin.
I
MFP10
External 4~24 MHz (high speed) crystal input pin.
I/O
MFP11
BPWM1 channel 0 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
O
MFP2
EBI chip select 1 output pin.
EADC0_ST
8
12
15
32 PF.4
33 PH.4
34 PH.5
35 PH.6
M480 SERIES DATASHEET
36 PH.7
UART7_RXD
9
13
16
37 PF.3
2
I C0_SCL
XT1_IN
BPWM1_CH0
10
14
17
38 PF.2
EBI_nCS1
May 08, 2020
Description
Page 240 of 523
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
MFP
Description
I
MFP3
UART0 data receiver input pin.
I2C0_SDA
I/O
MFP4
I2C0 data input/output pin.
QSPI0_CLK
I/O
MFP5
Quad SPI0 serial clock pin.
XT1_OUT
O
MFP10
External 4~24 MHz (high speed) crystal output pin.
BPWM1_CH1
I/O
MFP11
BPWM1 channel 1 output/capture input.
39 VSS
P
MFP0
Ground pin for digital circuit.
40 VDD
P
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
41 PE.8
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR10
O
MFP2
EBI address bus bit 10.
I2S0_BCLK
O
MFP4
I2S0 bit clock output pin.
SPI2_CLK
I/O
MFP5
SPI2 serial clock pin.
UART2_TXD
O
MFP7
UART2 data transmitter output pin.
EPWM0_CH0
I/O
MFP10
EPWM0 channel 0 output/capture input.
EPWM0_BRAKE0
I
MFP11
EPWM0 Brake 0 input pin.
ECAP0_IC0
I
MFP12
Enhanced capture unit 0 input 0 pin.
TRACE_DATA3
O
MFP14
ETM Trace Data 3 output pin
I/O
MFP0
General purpose digital I/O pin.
O
MFP2
EBI address bus bit 11.
I S0_MCLK
O
MFP4
I2S0 master clock output pin.
SPI2_MISO
I/O
MFP5
SPI2 MISO (Master In, Slave Out) pin.
UART2_RXD
I
MFP7
UART2 data receiver input pin.
EPWM0_CH1
I/O
MFP10
EPWM0 channel 1 output/capture input.
EPWM0_BRAKE1
I
MFP11
EPWM0 Brake 1 input pin.
ECAP0_IC1
I
MFP12
Enhanced capture unit 0 input 1 pin.
TRACE_DATA2
O
MFP14
ETM Trace Data 2 output pin
I/O
MFP0
General purpose digital I/O pin.
O
MFP2
EBI address bus bit 12.
I
MFP4
I2S0 data input pin.
SPI2_MOSI
I/O
MFP5
SPI2 MOSI (Master Out, Slave In) pin.
UART3_TXD
O
MFP7
UART3 data transmitter output pin.
EPWM0_CH2
I/O
MFP10
EPWM0 channel 2 output/capture input.
EPWM1_BRAKE0
I
MFP11
EPWM1 Brake 0 input pin.
ECAP0_IC2
I
MFP12
Enhanced capture unit 0 input 2 pin.
UART0_RXD
42 PE.9
EBI_ADR11
2
43 PE.10
EBI_ADR12
2
I S0_DI
May 08, 2020
Page 241 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
Type
MFP
O
MFP14
ETM Trace Data 1 output pin
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR13
O
MFP2
EBI address bus bit 13.
I2S0_DO
O
MFP4
I2S0 data output pin.
SPI2_SS
I/O
MFP5
SPI2 slave select pin.
UART3_RXD
I
MFP7
UART3 data receiver input pin.
UART1_nCTS
I
MFP8
UART1 clear to Send input pin.
EPWM0_CH3
I/O
MFP10
EPWM0 channel 3 output/capture input.
EPWM1_BRAKE1
I
MFP11
EPWM1 Brake 1 input pin.
ECAP1_IC2
I
MFP13
Enhanced capture unit 1 input 2 pin.
TRACE_DATA0
O
MFP14
ETM Trace Data 0 output pin
I/O
MFP0
General purpose digital I/O pin.
O
MFP2
EBI address bus bit 14.
I S0_LRCK
O
MFP4
I2S0 left right channel clock output pin.
SPI2_I2SMCLK
I/O
MFP5
SPI2 I2S master clock output pin
UART1_nRTS
O
MFP8
UART1 request to Send output pin.
EPWM0_CH4
I/O
MFP10
EPWM0 channel 4 output/capture input.
ECAP1_IC1
I
MFP13
Enhanced capture unit 1 input 1 pin.
TRACE_CLK
O
MFP14
ETM Trace Clock output pin
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR15
O
MFP2
EBI address bus bit 15.
I2C0_SCL
I/O
MFP4
I2C0 clock pin.
UART4_nRTS
O
MFP5
UART4 request to Send output pin.
UART1_TXD
O
MFP8
UART1 data transmitter output pin.
EPWM0_CH5
I/O
MFP10
EPWM0 channel 5 output/capture input.
EPWM1_CH0
I/O
MFP11
EPWM1 channel 0 output/capture input.
BPWM1_CH5
I/O
MFP12
BPWM1 channel 5 output/capture input.
I
MFP13
Enhanced capture unit 1 input 0 pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR16
O
MFP2
EBI address bus bit 16.
I2C0_SDA
I/O
MFP4
I2C0 data input/output pin.
UART4_nCTS
I
MFP5
UART4 clear to Send input pin.
UART1_RXD
I
MFP8
UART1 data receiver input pin.
EPWM1_CH1
I/O
MFP11
EPWM1 channel 1 output/capture input.
TRACE_DATA1
44 PE.11
45 PE.12
EBI_ADR14
2
M480 SERIES DATASHEET
46 PE.13
ECAP1_IC0
47 PC.8
May 08, 2020
Description
Page 242 of 523
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
MFP
I/O
MFP12
BPWM1 channel 4 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD9
I/O
MFP2
EBI address/data bus bit 9.
SPI1_MISO
I/O
MFP4
SPI1 MISO (Master In, Slave Out) pin.
UART4_TXD
O
MFP5
UART4 data transmitter output pin.
UART0_nCTS
I
MFP7
UART0 clear to Send input pin.
I2C1_SMBAL
O
MFP8
I2C1 SMBus SMBALTER pin
UART6_TXD
O
MFP9
UART6 data transmitter output pin.
EPWM1_CH2
I/O
MFP11
EPWM1 channel 2 output/capture input.
BPWM1_CH0
I/O
MFP12
BPWM1 channel 0 output/capture input.
TM0
I/O
MFP14
Timer0 event counter input/toggle output pin.
INT3
I
MFP15
External interrupt 3 input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD8
I/O
MFP2
EBI address/data bus bit 8.
SPI1_MOSI
I/O
MFP4
SPI1 MOSI (Master Out, Slave In) pin.
UART4_RXD
I
MFP5
UART4 data receiver input pin.
UART0_nRTS
O
MFP7
UART0 request to Send output pin.
I2C1_SMBSUS
O
MFP8
I2C1 SMBus SMBSUS pin (PMBus CONTROL pin)
UART6_RXD
I
MFP9
UART6 data receiver input pin.
EPWM1_CH3
I/O
MFP11
EPWM1 channel 3 output/capture input.
BPWM1_CH1
I/O
MFP12
BPWM1 channel 1 output/capture input.
TM1
I/O
MFP14
Timer1 event counter input/toggle output pin.
INT2
I
MFP15
External interrupt 2 input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD7
I/O
MFP2
EBI address/data bus bit 7.
SPI1_CLK
I/O
MFP4
SPI1 serial clock pin.
UART0_TXD
O
MFP7
UART0 data transmitter output pin.
I C1_SCL
I/O
MFP8
I2C1 clock pin.
QSPI1_MISO1
I/O
MFP9
Quad SPI1 MISO1 (Master In, Slave Out) pin.
EPWM1_CH4
I/O
MFP11
EPWM1 channel 4 output/capture input.
BPWM1_CH2
I/O
MFP12
BPWM1 channel 2 output/capture input.
ACMP0_WLAT
I
MFP13
Analog comparator 0 window latch input pin
TM2
I/O
MFP14
Timer2 event counter input/toggle output pin.
INT1
I
MFP15
External interrupt 1 input pin.
BPWM1_CH4
18
19
15
20
48 PC.7
49 PC.6
50 PA.7
2
May 08, 2020
Description
Page 243 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
16
21
Type
MFP
Description
I/O
MFP0
General purpose digital I/O pin.
EBI_AD6
I/O
MFP2
EBI address/data bus bit 6.
SPI1_SS
I/O
MFP4
SPI1 slave select pin.
I
MFP7
UART0 data receiver input pin.
I C1_SDA
I/O
MFP8
I2C1 data input/output pin.
QSPI1_MOSI1
I/O
MFP9
Quad SPI1 MOSI1 (Master Out, Slave In) pin.
EPWM1_CH5
I/O
MFP11
EPWM1 channel 5 output/capture input.
BPWM1_CH3
I/O
MFP12
BPWM1 channel 3 output/capture input.
ACMP1_WLAT
I
MFP13
Analog comparator 1 window latch input pin
TM3
I/O
MFP14
Timer3 event counter input/toggle output pin.
INT0
I
MFP15
External interrupt 0 input pin.
51 PA.6
UART0_RXD
2
22
52 VSS
P
MFP0
Ground pin for digital circuit.
23
53 VDD
P
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
24
54 LDO_CAP
A
MFP0
LDO output pin.
Note: This pin needs to be connected with an external
capacitor.
17
25
55 PA.5
M480 SERIES DATASHEET
18
26
I/O
MFP0
General purpose digital I/O pin.
QSPI0_MISO1
I/O
MFP3
Quad SPI0 MISO1 (Master In, Slave Out) pin.
SPI1_I2SMCLK
I/O
MFP4
SPI1 I2S master clock output pin
UART0_nCTS
I
MFP7
UART0 clear to Send input pin.
UART5_TXD
O
MFP8
UART5 data transmitter output pin.
I2C0_SCL
I/O
MFP9
I2C0 clock pin.
CAN0_TXD
O
MFP10
CAN0 bus transmitter output.
UART0_TXD
O
MFP11
UART0 data transmitter output pin.
BPWM0_CH5
I/O
MFP12
BPWM0 channel 5 output/capture input.
EPWM0_CH0
I/O
MFP13
EPWM0 channel 0 output/capture input.
QEI0_INDEX
I
MFP14
Quadrature encoder 0 index input
I/O
MFP0
General purpose digital I/O pin.
QSPI0_MOSI1
I/O
MFP3
Quad SPI0 MOSI1 (Master Out, Slave In) pin.
SPI0_I2SMCLK
I/O
MFP4
SPI0 I2S master clock output pin
SC0_nCD
I
MFP6
Smart Card 0 card detect pin.
UART0_nRTS
O
MFP7
UART0 request to Send output pin.
UART5_RXD
I
MFP8
UART5 data receiver input pin.
I/O
MFP9
I2C0 data input/output pin.
56 PA.4
2
I C0_SDA
May 08, 2020
Page 244 of 523
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
MFP
CAN0_RXD
I
MFP10
CAN0 bus receiver input.
UART0_RXD
I
MFP11
UART0 data receiver input pin.
BPWM0_CH4
I/O
MFP12
BPWM0 channel 4 output/capture input.
EPWM0_CH1
I/O
MFP13
EPWM0 channel 1 output/capture input.
I
MFP14
Quadrature encoder 0 phase A input
I/O
MFP0
General purpose digital I/O pin.
QSPI0_SS
I/O
MFP3
Quad SPI0 slave select pin.
SPI0_SS
I/O
MFP4
SPI0 slave select pin.
SC0_PWR
O
MFP6
Smart Card 0 power pin.
UART4_TXD
O
MFP7
UART4 data transmitter output pin.
UART1_TXD
O
MFP8
UART1 data transmitter output pin.
I C1_SCL
I/O
MFP9
I2C1 clock pin.
I2C0_SMBAL
O
MFP10
I2C0 SMBus SMBALTER pin
BPWM0_CH3
I/O
MFP12
BPWM0 channel 3 output/capture input.
EPWM0_CH2
I/O
MFP13
EPWM0 channel 2 output/capture input.
QEI0_B
I
MFP14
Quadrature encoder 0 phase B input
EPWM1_BRAKE1
I
MFP15
EPWM1 Brake 1 input pin.
I/O
MFP0
General purpose digital I/O pin.
QSPI0_CLK
I/O
MFP3
Quad SPI0 serial clock pin.
SPI0_CLK
I/O
MFP4
SPI0 serial clock pin.
SC0_RST
O
MFP6
Smart Card 0 reset pin.
UART4_RXD
I
MFP7
UART4 data receiver input pin.
UART1_RXD
I
MFP8
UART1 data receiver input pin.
I2C1_SDA
I/O
MFP9
I2C1 data input/output pin.
I2C0_SMBSUS
O
MFP10
I2C0 SMBus SMBSUS pin (PMBus CONTROL pin)
BPWM0_CH2
I/O
MFP12
BPWM0 channel 2 output/capture input.
EPWM0_CH3
I/O
MFP13
EPWM0 channel 3 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
QSPI0_MISO0
I/O
MFP3
Quad SPI0 MISO0 (Master In, Slave Out) pin.
SPI0_MISO
I/O
MFP4
SPI0 MISO (Master In, Slave Out) pin.
SC0_DAT
I/O
MFP6
Smart Card 0 data pin.
UART0_TXD
O
MFP7
UART0 data transmitter output pin.
UART1_nCTS
I
MFP8
UART1 clear to Send input pin.
I/O
MFP9
I2C2 clock pin.
QEI0_A
11
19
27
57 PA.3
2
12
13
20
21
28
29
58 PA.2
59 PA.1
2
I C2_SCL
May 08, 2020
Description
Page 245 of 523
Rev 3.00
M480 SERIES DATASHEET
Type
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
14
22
30
Type
MFP
CCAP_DATA7
I
MFP10
Camera capture data input bus bit 7.
BPWM0_CH1
I/O
MFP12
BPWM0 channel 1 output/capture input.
EPWM0_CH4
I/O
MFP13
EPWM0 channel 4 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
QSPI0_MOSI0
I/O
MFP3
Quad SPI0 MOSI0 (Master Out, Slave In) pin.
SPI0_MOSI
I/O
MFP4
SPI0 MOSI (Master Out, Slave In) pin.
SC0_CLK
O
MFP6
Smart Card 0 clock pin.
UART0_RXD
I
MFP7
UART0 data receiver input pin.
UART1_nRTS
O
MFP8
UART1 request to Send output pin.
I/O
MFP9
I2C2 data input/output pin.
CCAP_DATA6
I
MFP10
Camera capture data input bus bit 6.
BPWM0_CH0
I/O
MFP12
BPWM0 channel 0 output/capture input.
EPWM0_CH5
I/O
MFP13
EPWM0 channel 5 output/capture input.
I
MFP15
DAC0 external trigger input.
61 VDDIO
P
MFP0
Power supply for PA.0~PA.5.
62 PE.14
I/O
MFP0
General purpose digital I/O pin.
EBI_AD8
I/O
MFP2
EBI address/data bus bit 8.
UART2_TXD
O
MFP3
UART2 data transmitter output pin.
CAN0_TXD
O
MFP4
CAN0 bus transmitter output.
UART6_TXD
O
MFP6
UART6 data transmitter output pin.
I/O
MFP0
General purpose digital I/O pin.
I/O
MFP2
EBI address/data bus bit 9.
UART2_RXD
I
MFP3
UART2 data receiver input pin.
CAN0_RXD
I
MFP4
CAN0 bus receiver input.
UART6_RXD
I
MFP6
UART6 data receiver input pin.
I
MFP0
External reset input: active LOW, with an internal pull-up.
Set this pin low reset to initial state.
60 PA.0
2
I C2_SDA
DAC0_ST
15
23
31
M480 SERIES DATASHEET
63 PE.15
EBI_AD9
16
24
32
64 nRESET
Description
Note: It is recommended to use 10 kΩ pull-up resistor and
10 uF capacitor on nRESET pin.
17
25
33
65 PF.0
I/O
MFP0
General purpose digital I/O pin.
UART1_TXD
O
MFP2
UART1 data transmitter output pin.
I2C1_SCL
I/O
MFP3
I2C1 clock pin.
UART0_TXD
O
MFP4
UART0 data transmitter output pin.
BPWM1_CH0
I/O
MFP12
BPWM1 channel 0 output/capture input.
ICE_DAT
I/O
MFP14
Serial wired debugger data pin.
Note: It is recommended to use 100 kΩ pull-up resistor on
May 08, 2020
Page 246 of 523
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
Type
MFP
Description
ICE_DAT pin.
18
26
34
66 PF.1
I/O
MFP0
General purpose digital I/O pin.
I
MFP2
UART1 data receiver input pin.
I/O
MFP3
I2C1 data input/output pin.
UART0_RXD
I
MFP4
UART0 data receiver input pin.
BPWM1_CH1
I/O
MFP12
BPWM1 channel 1 output/capture input.
ICE_CLK
I/O
MFP14
Serial wired debugger clock pin.
UART1_RXD
I2C1_SDA
Note: It is recommended to use 100 kΩ pull-up resistor on
ICE_CLK pin.
67 PD.9
MFP0
General purpose digital I/O pin.
EBI_AD7
I/O
MFP2
EBI address/data bus bit 7.
I2C2_SCL
I/O
MFP3
I2C2 clock pin.
UART2_nCTS
I
MFP4
UART2 clear to Send input pin.
UART7_TXD
O
MFP5
UART7 data transmitter output pin.
CAN2_TXD
O
MFP6
CAN2 bus transmitter output.
I/O
MFP0
General purpose digital I/O pin.
I/O
MFP2
EBI address/data bus bit 6.
I C2_SDA
I/O
MFP3
I2C2 data input/output pin.
UART2_nRTS
O
MFP4
UART2 request to Send output pin.
UART7_RXD
I
MFP5
UART7 data receiver input pin.
CAN2_RXD
I
MFP6
CAN2 bus receiver input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD5
I/O
MFP2
EBI address/data bus bit 5.
QSPI0_MISO1
I/O
MFP4
Quad SPI0 MISO1 (Master In, Slave Out) pin.
UART2_TXD
O
MFP8
UART2 data transmitter output pin.
I2C1_SCL
I/O
MFP9
I2C1 clock pin.
CAN0_TXD
O
MFP10
CAN0 bus transmitter output.
UART4_TXD
O
MFP11
UART4 data transmitter output pin.
EPWM1_CH0
I/O
MFP12
EPWM1 channel 0 output/capture input.
CCAP_DATA5
I
MFP13
Camera capture data input bus bit 5.
I/O
MFP14
Quad SPI1 slave select pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD4
I/O
MFP2
EBI address/data bus bit 4.
QSPI0_MOSI1
I/O
MFP4
Quad SPI0 MOSI1 (Master Out, Slave In) pin.
O
MFP6
I2S0 bit clock output pin.
68 PD.8
EBI_AD6
2
27
35
69 PC.5
QSPI1_SS
28
36
70 PC.4
2
I S0_BCLK
May 08, 2020
Page 247 of 523
M480 SERIES DATASHEET
I/O
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
Type
MFP
Description
I/O
MFP7
SPI1 I2S master clock output pin
I
MFP8
UART2 data receiver input pin.
I/O
MFP9
I2C1 data input/output pin.
CAN0_RXD
I
MFP10
CAN0 bus receiver input.
UART4_RXD
I
MFP11
UART4 data receiver input pin.
EPWM1_CH1
I/O
MFP12
EPWM1 channel 1 output/capture input.
CCAP_DATA4
I
MFP13
Camera capture data input bus bit 4.
I/O
MFP14
Quad SPI1 serial clock pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD3
I/O
MFP2
EBI address/data bus bit 3.
QSPI0_SS
I/O
MFP4
Quad SPI0 slave select pin.
I S0_MCLK
O
MFP6
I2S0 master clock output pin.
SPI1_MISO
I/O
MFP7
SPI1 MISO (Master In, Slave Out) pin.
UART2_nRTS
O
MFP8
UART2 request to Send output pin.
I2C0_SMBAL
O
MFP9
I2C0 SMBus SMBALTER pin
CAN1_TXD
O
MFP10
CAN1 bus transmitter output.
UART3_TXD
O
MFP11
UART3 data transmitter output pin.
EPWM1_CH2
I/O
MFP12
EPWM1 channel 2 output/capture input.
CCAP_DATA3
I
MFP13
Camera capture data input bus bit 3.
QSPI1_MISO0
I/O
MFP14
Quad SPI1 MISO0 (Master In, Slave Out) pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD2
I/O
MFP2
EBI address/data bus bit 2.
QSPI0_CLK
I/O
MFP4
Quad SPI0 serial clock pin.
I
MFP6
I2S0 data input pin.
I/O
MFP7
SPI1 MOSI (Master Out, Slave In) pin.
UART2_nCTS
I
MFP8
UART2 clear to Send input pin.
I2C0_SMBSUS
O
MFP9
I2C0 SMBus SMBSUS pin (PMBus CONTROL pin)
CAN1_RXD
I
MFP10
CAN1 bus receiver input.
UART3_RXD
I
MFP11
UART3 data receiver input pin.
EPWM1_CH3
I/O
MFP12
EPWM1 channel 3 output/capture input.
CCAP_DATA2
I
MFP13
Camera capture data input bus bit 2.
QSPI1_MOSI0
I/O
MFP14
Quad SPI1 MOSI0 (Master Out, Slave In) pin.
I/O
MFP0
General purpose digital I/O pin.
I/O
MFP2
EBI address/data bus bit 1.
SPI1_I2SMCLK
UART2_RXD
2
I C1_SDA
QSPI1_CLK
29
37
71 PC.3
2
M480 SERIES DATASHEET
30
38
72 PC.2
I2S0_DI
SPI1_MOSI
19
31
39
73 PC.1
EBI_AD1
May 08, 2020
Page 248 of 523
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
MFP
Description
QSPI0_MISO0
I/O
MFP4
Quad SPI0 MISO0 (Master In, Slave Out) pin.
I2S0_DO
O
MFP6
I2S0 data output pin.
SPI1_CLK
I/O
MFP7
SPI1 serial clock pin.
UART2_TXD
O
MFP8
UART2 data transmitter output pin.
I C0_SCL
I/O
MFP9
I2C0 clock pin.
CAN2_TXD
O
MFP10
CAN2 bus transmitter output.
EPWM1_CH4
I/O
MFP12
EPWM1 channel 4 output/capture input.
CCAP_DATA1
I
MFP13
Camera capture data input bus bit 1.
ACMP0_O
O
MFP14
Analog comparator 0 output pin.
EADC0_ST
I
MFP15
EADC0 external trigger input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD0
I/O
MFP2
EBI address/data bus bit 0.
QSPI0_MOSI0
I/O
MFP4
Quad SPI0 MOSI0 (Master Out, Slave In) pin.
I S0_LRCK
O
MFP6
I2S0 left right channel clock output pin.
SPI1_SS
I/O
MFP7
SPI1 slave select pin.
I
MFP8
UART2 data receiver input pin.
I/O
MFP9
I2C0 data input/output pin.
I
MFP10
CAN2 bus receiver input.
EPWM1_CH5
I/O
MFP12
EPWM1 channel 5 output/capture input.
CCAP_DATA0
I
MFP13
Camera capture data input bus bit 0.
ACMP1_O
O
MFP14
Analog comparator 1 output pin.
EADC1_ST
I
MFP15
EADC1 external trigger input.
75 VSS
P
MFP0
Ground pin for digital circuit.
76 VDD
P
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD0
I/O
MFP2
EBI address/data bus bit 0.
QSPI1_MISO1
I/O
MFP5
Quad SPI1 MISO1 (Master In, Slave Out) pin.
CCAP_PIXCLK
I
MFP7
Camera capture interface pix clock input pin.
I/O
MFP12
BPWM0 channel 5 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD1
I/O
MFP2
EBI address/data bus bit 1.
QSPI1_MOSI1
I/O
MFP5
Quad SPI1 MOSI1 (Master Out, Slave In) pin.
CCAP_SCLK
O
MFP7
Camera capture interface sensor clock pin.
2
20
32
40
74 PC.0
2
UART2_RXD
2
I C0_SDA
CAN2_RXD
77 PG.9
BPWM0_CH5
78 PG.10
May 08, 2020
Page 249 of 523
Rev 3.00
M480 SERIES DATASHEET
Type
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
Type
MFP
I/O
MFP12
BPWM0 channel 4 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD2
I/O
MFP2
EBI address/data bus bit 2.
QSPI1_SS
I/O
MFP5
Quad SPI1 slave select pin.
UART7_TXD
O
MFP6
UART7 data transmitter output pin.
CCAP_SFIELD
I
MFP7
Camera capture interface SFIELD input pin.
I/O
MFP12
BPWM0 channel 3 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD3
I/O
MFP2
EBI address/data bus bit 3.
QSPI1_CLK
I/O
MFP5
Quad SPI1 serial clock pin.
UART7_RXD
I
MFP6
UART7 data receiver input pin.
CCAP_VSYNC
I
MFP7
Camera capture interface vsync input pin.
BPWM0_CH2
I/O
MFP12
BPWM0 channel 2 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD4
I/O
MFP2
EBI address/data bus bit 4.
QSPI1_MISO0
I/O
MFP5
Quad SPI1 MISO0 (Master In, Slave Out) pin.
UART6_TXD
O
MFP6
UART6 data transmitter output pin.
CCAP_HSYNC
I
MFP7
Camera capture interface hsync input pin.
I/O
MFP12
BPWM0 channel 1 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD5
I/O
MFP2
EBI address/data bus bit 5.
QSPI1_MOSI0
I/O
MFP5
Quad SPI1 MOSI0 (Master Out, Slave In) pin.
UART6_RXD
I
MFP6
UART6 data receiver input pin.
BPWM0_CH0
I/O
MFP12
BPWM0 channel 0 output/capture input.
83 PG.15
I/O
MFP0
General purpose digital I/O pin.
CLKO
O
MFP14
Clock Out
EADC0_ST
I
MFP15
EADC0 external trigger input.
PD.3
I/O
MFP0
General purpose digital I/O pin.
EBI_AD10
I/O
MFP2
EBI address/data bus bit 10.
SPI0_SS
I/O
MFP4
SPI0 slave select pin.
UART3_nRTS
O
MFP5
UART3 request to Send output pin.
UART0_TXD
O
MFP9
UART0 data transmitter output pin.
PD.2
I/O
MFP0
General purpose digital I/O pin.
EBI_AD11
I/O
MFP2
EBI address/data bus bit 11.
BPWM0_CH4
79 PG.11
BPWM0_CH3
80 PG.12
81 PG.13
BPWM0_CH1
M480 SERIES DATASHEET
82 PG.14
41
42
May 08, 2020
Description
Page 250 of 523
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
MFP
Description
I/O
MFP4
SPI0 serial clock pin.
UART3_nCTS
I
MFP5
UART3 clear to Send input pin.
UART0_RXD
I
MFP9
UART0 data receiver input pin.
PD.1
I/O
MFP0
General purpose digital I/O pin.
EBI_AD12
I/O
MFP2
EBI address/data bus bit 12.
SPI0_MISO
I/O
MFP4
SPI0 MISO (Master In, Slave Out) pin.
UART3_TXD
O
MFP5
UART3 data transmitter output pin.
I2C2_SCL
I/O
MFP6
I2C2 clock pin.
PD.0
I/O
MFP0
General purpose digital I/O pin.
EBI_AD13
I/O
MFP2
EBI address/data bus bit 13.
SPI0_MOSI
I/O
MFP4
SPI0 MOSI (Master Out, Slave In) pin.
I
MFP5
UART3 data receiver input pin.
I2C2_SDA
I/O
MFP6
I2C2 data input/output pin.
TM2
I/O
MFP14
Timer2 event counter input/toggle output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD10
I/O
MFP2
EBI address/data bus bit 10.
SD0_nCD
I
MFP3
SD/SDIO0 card detect input pin
SPI0_I2SMCLK
I/O
MFP4
SPI0 I2S master clock output pin
SPI1_I2SMCLK
I/O
MFP5
SPI1 I2S master clock output pin
I/O
MFP0
General purpose digital I/O pin.
I2S0_BCLK
O
MFP2
I2S0 bit clock output pin.
UART4_TXD
O
MFP3
UART4 data transmitter output pin.
I C1_SCL
I/O
MFP4
I2C1 clock pin.
SPI2_SS
I/O
MFP5
SPI2 slave select pin.
CAN0_TXD
O
MFP6
CAN0 bus transmitter output.
BPWM1_CH2
I/O
MFP11
BPWM1 channel 2 output/capture input.
QEI1_INDEX
I
MFP12
Quadrature encoder 1 index input
USB_VBUS
P
MFP14
Power supply from USB host or HUB.
I/O
MFP0
General purpose digital I/O pin.
I2S0_MCLK
O
MFP2
I2S0 master clock output pin.
UART4_RXD
I
MFP3
UART4 data receiver input pin.
I C1_SDA
I/O
MFP4
I2C1 data input/output pin.
SPI2_CLK
I/O
MFP5
SPI2 serial clock pin.
I
MFP6
CAN0 bus receiver input.
SPI0_CLK
43
44
UART3_RXD
84 PD.13
21
33
45
85 PA.12
2
22
34
46
86 PA.13
2
CAN0_RXD
May 08, 2020
Page 251 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
Type
MFP
I/O
MFP11
BPWM1 channel 3 output/capture input.
QEI1_A
I
MFP12
Quadrature encoder 1 phase A input
USB_D-
A
MFP14
USB differential signal D-.
87 PA.14
I/O
MFP0
General purpose digital I/O pin.
2
I S0_DI
I
MFP2
I2S0 data input pin.
UART0_TXD
O
MFP3
UART0 data transmitter output pin.
SPI2_MISO
I/O
MFP5
SPI2 MISO (Master In, Slave Out) pin.
I C2_SCL
I/O
MFP6
I2C2 clock pin.
BPWM1_CH4
I/O
MFP11
BPWM1 channel 4 output/capture input.
QEI1_B
I
MFP12
Quadrature encoder 1 phase B input
USB_D+
A
MFP14
USB differential signal D+.
I/O
MFP0
General purpose digital I/O pin.
I2S0_DO
O
MFP2
I2S0 data output pin.
UART0_RXD
I
MFP3
UART0 data receiver input pin.
SPI2_MOSI
I/O
MFP5
SPI2 MOSI (Master Out, Slave In) pin.
I2C2_SDA
I/O
MFP6
I2C2 data input/output pin.
BPWM1_CH5
I/O
MFP11
BPWM1 channel 5 output/capture input.
EPWM0_SYNC_IN
I
MFP12
EPWM0 counter synchronous trigger input pin.
USB_OTG_ID
I
MFP14
USB_ identification.
89 NC
-
MFP0
No connect pin, leave floating.
90 NC
-
MFP0
No connect pin, leave floating.
91 NC
-
MFP0
No connect pin, leave floating.
92 NC
-
MFP0
No connect pin, leave floating.
93 NC
-
MFP0
No connect pin, leave floating.
94 NC
-
MFP0
No connect pin, leave floating.
95 NC
-
MFP0
No connect pin, leave floating.
96 NC
-
MFP0
No connect pin, leave floating.
I/O
MFP0
General purpose digital I/O pin.
SD0_CMD
I/O
MFP3
SD/SDIO0 command/response pin
UART5_TXD
O
MFP8
UART5 data transmitter output pin.
CAN1_TXD
O
MFP9
CAN1 bus transmitter output.
QEI1_INDEX
I
MFP11
Quadrature encoder 1 index input
EPWM0_CH0
I/O
MFP12
EPWM0 channel 0 output/capture input.
BPWM0_CH5
I/O
MFP13
BPWM0 channel 5 output/capture input.
BPWM1_CH3
23
35
47
2
24
36
48
88 PA.15
M480 SERIES DATASHEET
97 PE.7
May 08, 2020
Description
Page 252 of 523
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
MFP
Description
I/O
MFP0
General purpose digital I/O pin.
SD0_CLK
O
MFP3
SD/SDIO0 clock output pin
SC0_nCD
I
MFP6
Smart Card 0 card detect pin.
UART5_RXD
I
MFP8
UART5 data receiver input pin.
CAN1_RXD
I
MFP9
CAN1 bus receiver input.
QEI1_A
I
MFP11
Quadrature encoder 1 phase A input
EPWM0_CH1
I/O
MFP12
EPWM0 channel 1 output/capture input.
BPWM0_CH4
I/O
MFP13
BPWM0 channel 4 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_nRD
O
MFP2
EBI read enable output pin.
SD0_DAT3
I/O
MFP3
SD/SDIO0 data line bit 3.
SC0_PWR
O
MFP6
Smart Card 0 power pin.
UART6_TXD
O
MFP8
UART6 data transmitter output pin.
UART7_nRTS
O
MFP9
UART7 request to Send output pin.
QEI1_B
I
MFP11
Quadrature encoder 1 phase B input
EPWM0_CH2
I/O
MFP12
EPWM0 channel 2 output/capture input.
BPWM0_CH3
I/O
MFP13
BPWM0 channel 3 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_nWR
O
MFP2
EBI write enable output pin.
SD0_DAT2
I/O
MFP3
SD/SDIO0 data line bit 2.
SC0_RST
O
MFP6
Smart Card 0 reset pin.
UART6_RXD
I
MFP8
UART6 data receiver input pin.
UART7_nCTS
I
MFP9
UART7 clear to Send input pin.
QEI0_INDEX
I
MFP11
Quadrature encoder 0 index input
EPWM0_CH3
I/O
MFP12
EPWM0 channel 3 output/capture input.
BPWM0_CH2
I/O
MFP13
BPWM0 channel 2 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_MCLK
O
MFP2
EBI external clock output pin.
SD0_DAT1
I/O
MFP3
SD/SDIO0 data line bit 1.
SC0_DAT
I/O
MFP6
Smart Card 0 data pin.
UART6_nRTS
O
MFP8
UART6 request to Send output pin.
UART7_TXD
O
MFP9
UART7 data transmitter output pin.
QEI0_A
I
MFP11
Quadrature encoder 0 phase A input
I/O
MFP12
EPWM0 channel 4 output/capture input.
98 PE.6
99 PE.5
100 PE.4
101 PE.3
EPWM0_CH4
May 08, 2020
Page 253 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
Type
MFP
I/O
MFP13
BPWM0 channel 1 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_ALE
O
MFP2
EBI address latch enable output pin.
SD0_DAT0
I/O
MFP3
SD/SDIO0 data line bit 0.
SC0_CLK
O
MFP6
Smart Card 0 clock pin.
UART6_nCTS
I
MFP8
UART6 clear to Send input pin.
UART7_RXD
I
MFP9
UART7 data receiver input pin.
QEI0_B
I
MFP11
Quadrature encoder 0 phase B input
EPWM0_CH5
I/O
MFP12
EPWM0 channel 5 output/capture input.
BPWM0_CH0
I/O
MFP13
BPWM0 channel 0 output/capture input.
103 VSS
P
MFP0
Ground pin for digital circuit.
104 VDD
P
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
105 PE.1
I/O
MFP0
General purpose digital I/O pin.
EBI_AD10
I/O
MFP2
EBI address/data bus bit 10.
QSPI0_MISO0
I/O
MFP3
Quad SPI0 MISO0 (Master In, Slave Out) pin.
I2S0_BCLK
O
MFP5
I2S0 bit clock output pin.
SPI1_MISO
I/O
MFP6
SPI1 MISO (Master In, Slave Out) pin.
UART3_TXD
O
MFP7
UART3 data transmitter output pin.
I/O
MFP8
I2C1 clock pin.
I
MFP9
UART4 clear to Send input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD11
I/O
MFP2
EBI address/data bus bit 11.
QSPI0_MOSI0
I/O
MFP3
Quad SPI0 MOSI0 (Master Out, Slave In) pin.
I S0_MCLK
O
MFP5
I2S0 master clock output pin.
SPI1_MOSI
I/O
MFP6
SPI1 MOSI (Master Out, Slave In) pin.
I
MFP7
UART3 data receiver input pin.
I2C1_SDA
I/O
MFP8
I2C1 data input/output pin.
UART4_nRTS
O
MFP9
UART4 request to Send output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD12
I/O
MFP2
EBI address/data bus bit 12.
QSPI0_CLK
I/O
MFP3
Quad SPI0 serial clock pin.
I
MFP5
I2S0 data input pin.
I/O
MFP6
SPI1 serial clock pin.
BPWM0_CH1
102 PE.2
2
I C1_SCL
M480 SERIES DATASHEET
UART4_nCTS
106 PE.0
2
UART3_RXD
107 PH.8
I2S0_DI
SPI1_CLK
May 08, 2020
Description
Page 254 of 523
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
MFP
Description
UART3_nRTS
O
MFP7
UART3 request to Send output pin.
I2C1_SMBAL
O
MFP8
I2C1 SMBus SMBALTER pin
I2C2_SCL
I/O
MFP9
I2C2 clock pin.
UART1_TXD
O
MFP10
UART1 data transmitter output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD13
I/O
MFP2
EBI address/data bus bit 13.
QSPI0_SS
I/O
MFP3
Quad SPI0 slave select pin.
I S0_DO
O
MFP5
I2S0 data output pin.
SPI1_SS
I/O
MFP6
SPI1 slave select pin.
UART3_nCTS
I
MFP7
UART3 clear to Send input pin.
I2C1_SMBSUS
O
MFP8
I2C1 SMBus SMBSUS pin (PMBus CONTROL pin)
I2C2_SDA
I/O
MFP9
I2C2 data input/output pin.
I
MFP10
UART1 data receiver input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD14
I/O
MFP2
EBI address/data bus bit 14.
QSPI0_MISO1
I/O
MFP3
Quad SPI0 MISO1 (Master In, Slave Out) pin.
I S0_LRCK
O
MFP5
I2S0 left right channel clock output pin.
SPI1_I2SMCLK
I/O
MFP6
SPI1 I2S master clock output pin
UART4_TXD
O
MFP7
UART4 data transmitter output pin.
UART0_TXD
O
MFP8
UART0 data transmitter output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD15
I/O
MFP2
EBI address/data bus bit 15.
QSPI0_MOSI1
I/O
MFP3
Quad SPI0 MOSI1 (Master Out, Slave In) pin.
UART4_RXD
I
MFP7
UART4 data receiver input pin.
UART0_RXD
I
MFP8
UART0 data receiver input pin.
EPWM0_CH5
I/O
MFP11
EPWM0 channel 5 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_nCS0
O
MFP2
EBI chip select 0 output pin.
SPI0_I2SMCLK
I/O
MFP5
SPI0 I2S master clock output pin
EPWM0_CH4
I/O
MFP11
EPWM0 channel 4 output/capture input.
108 PH.9
2
UART1_RXD
109 PH.10
2
110 PH.11
111 PD.14
25
37
49 112 VSS
P
MFP0
Ground pin for digital circuit.
26
38
50 113 LDO_CAP
A
MFP0
LDO output pin.
M480 SERIES DATASHEET
Type
Note: This pin needs to be connected with an external
capacitor.
27
39
51 114 VDD
May 08, 2020
P
MFP0
Power supply for I/O ports and LDO source for internal
Page 255 of 523
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
Type
MFP
Description
PLL and digital circuit.
40
52 115 PC.14
I/O
MFP0
General purpose digital I/O pin.
EBI_AD11
I/O
MFP2
EBI address/data bus bit 11.
SPI0_I2SMCLK
I/O
MFP4
SPI0 I2S master clock output pin
QSPI0_CLK
I/O
MFP6
Quad SPI0 serial clock pin.
EPWM0_SYNC_IN
I
MFP11
EPWM0 counter synchronous trigger input pin.
ETM_TRACE_CLK
I
MFP12
ETM receiver Trace Clock input pin
I/O
MFP13
Timer1 event counter input/toggle output pin.
I
MFP14
USB external VBUS regulator status pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH15
A
MFP1
EADC0 channel 15 analog input.
EADC1_CH15
A
MFP1
EADC1 channel 15 analog input.
EBI_AD12
I/O
MFP2
EBI address/data bus bit 12.
SPI0_SS
I/O
MFP4
SPI0 slave select pin.
UART0_nCTS
I
MFP6
UART0 clear to Send input pin.
UART3_TXD
O
MFP7
UART3 data transmitter output pin.
I C2_SMBAL
O
MFP8
I2C2 SMBus SMBALTER pin
EPWM0_BRAKE1
I
MFP10
EPWM0 Brake 1 input pin.
I/O
MFP11
EPWM1 channel 0 output/capture input.
I
MFP12
ETM receiver Trace Data 0 input pin
TM0_EXT
I/O
MFP13
Timer0 external capture input/toggle output pin.
USB_VBUS_EN
O
MFP14
USB external VBUS regulator enable pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH14
A
MFP1
EADC0 channel 14 analog input.
EADC1_CH14
A
MFP1
EADC1 channel 14 analog input.
EBI_AD13
I/O
MFP2
EBI address/data bus bit 13.
SPI0_CLK
I/O
MFP4
SPI0 serial clock pin.
UART0_nRTS
O
MFP6
UART0 request to Send output pin.
UART3_RXD
I
MFP7
UART3 data receiver input pin.
I C2_SMBSUS
O
MFP8
I2C2 SMBus SMBSUS pin (PMBus CONTROL pin)
EPWM1_CH1
I/O
MFP11
EPWM1 channel 1 output/capture input.
I
MFP12
ETM receiver Trace Data 1 input pin
TM1_EXT
I/O
MFP13
Timer1 external capture input/toggle output pin.
CLKO
O
MFP14
Clock Out
TM1
USB_VBUS_ST
28
41
53 116 PB.15
2
EPWM1_CH0
M480 SERIES DATASHEET
ETM_TRACE_DATA0
29
42
54 117 PB.14
2
ETM_TRACE_DATA1
May 08, 2020
Page 256 of 523
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
MFP
I
MFP15
USB external VBUS regulator status pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH13
A
MFP1
EADC0 channel 13 analog input.
EADC1_CH13
A
MFP1
EADC1 channel 13 analog input.
ACMP0_P3
A
MFP1
Analog comparator 0 positive input 3 pin.
ACMP1_P3
A
MFP1
Analog comparator 1 positive input 3 pin.
EBI_AD14
I/O
MFP2
EBI address/data bus bit 14.
SPI0_MISO
I/O
MFP4
SPI0 MISO (Master In, Slave Out) pin.
UART0_TXD
O
MFP6
UART0 data transmitter output pin.
UART3_nRTS
O
MFP7
UART3 request to Send output pin.
I2C2_SCL
I/O
MFP8
I2C2 clock pin.
I
MFP10
Camera capture interface pix clock input pin.
I/O
MFP11
EPWM1 channel 2 output/capture input.
I
MFP12
ETM receiver Trace Data 2 input pin
I/O
MFP13
Timer2 external capture input/toggle output pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH12
A
MFP1
EADC0 channel 12 analog input.
EADC1_CH12
A
MFP1
EADC1 channel 12 analog input.
DAC0_OUT
A
MFP1
DAC0 channel analog output.
ACMP0_P2
A
MFP1
Analog comparator 0 positive input 2 pin.
ACMP1_P2
A
MFP1
Analog comparator 1 positive input 2 pin.
EBI_AD15
I/O
MFP2
EBI address/data bus bit 15.
SPI0_MOSI
I/O
MFP4
SPI0 MOSI (Master Out, Slave In) pin.
UART0_RXD
I
MFP6
UART0 data receiver input pin.
UART3_nCTS
I
MFP7
UART3 clear to Send input pin.
I2C2_SDA
I/O
MFP8
I2C2 data input/output pin.
SD0_nCD
I
MFP9
SD/SDIO0 card detect input pin
CCAP_SCLK
O
MFP10
Camera capture interface sensor clock pin.
EPWM1_CH3
I/O
MFP11
EPWM1 channel 3 output/capture input.
I
MFP12
ETM receiver Trace Data 3 input pin
I/O
MFP13
Timer3 external capture input/toggle output pin.
57 120 AVDD
P
MFP0
Power supply for internal analog circuit.
58 121 VREF
A
MFP0
ADC reference voltage input.
USB_VBUS_ST
30
43
55 118 PB.13
CCAP_PIXCLK
EPWM1_CH2
ETM_TRACE_DATA2
TM2_EXT
31
44
56 119 PB.12
ETM_TRACE_DATA3
TM3_EXT
32
45
Description
M480 SERIES DATASHEET
Type
Note: This pin needs to be connected with a 1uF
capacitor.
May 08, 2020
Page 257 of 523
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
46
Type
MFP
Description
59 122 AVSS
P
MFP0
Ground pin for analog circuit.
60 123 PB.11
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH11
A
MFP1
EADC0 channel 11 analog input.
EBI_ADR16
O
MFP2
EBI address bus bit 16.
UART0_nCTS
I
MFP5
UART0 clear to Send input pin.
UART4_TXD
O
MFP6
UART4 data transmitter output pin.
I2C1_SCL
I/O
MFP7
I2C1 clock pin.
CAN0_TXD
O
MFP8
CAN0 bus transmitter output.
SPI0_I2SMCLK
I/O
MFP9
SPI0 I2S master clock output pin
BPWM1_CH0
I/O
MFP10
BPWM1 channel 0 output/capture input.
I
MFP12
Camera capture interface SFIELD input pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH10
A
MFP1
EADC0 channel 10 analog input.
EBI_ADR17
O
MFP2
EBI address bus bit 17.
UART0_nRTS
O
MFP5
UART0 request to Send output pin.
UART4_RXD
I
MFP6
UART4 data receiver input pin.
I/O
MFP7
I2C1 data input/output pin.
I
MFP8
CAN0 bus receiver input.
BPWM1_CH1
I/O
MFP10
BPWM1 channel 1 output/capture input.
CCAP_VSYNC
I
MFP12
Camera capture interface vsync input pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH9
A
MFP1
EADC0 channel 9 analog input.
EBI_ADR18
O
MFP2
EBI address bus bit 18.
UART0_TXD
O
MFP5
UART0 data transmitter output pin.
UART1_nCTS
I
MFP6
UART1 clear to Send input pin.
I2C1_SMBAL
O
MFP7
I2C1 SMBus SMBALTER pin
UART7_TXD
O
MFP8
UART7 data transmitter output pin.
I C0_SCL
I/O
MFP9
I2C0 clock pin.
BPWM1_CH2
I/O
MFP10
BPWM1 channel 2 output/capture input.
CAN2_TXD
O
MFP12
CAN2 bus transmitter output.
INT7
I
MFP13
External interrupt 7 input pin.
CCAP_HSYNC
I
MFP14
Camera capture interface hsync input pin.
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC0 channel 8 analog input.
CCAP_SFIELD
61 124 PB.10
2
I C1_SDA
CAN0_RXD
M480 SERIES DATASHEET
62 125 PB.9
2
63 126 PB.8
EADC0_CH8
May 08, 2020
Page 258 of 523
Rev 3.00
M480
32 48 64 128 Pin Name
Pin Pin Pin Pin
47
MFP
Description
EBI_ADR19
O
MFP2
EBI address bus bit 19.
UART0_RXD
I
MFP5
UART0 data receiver input pin.
UART1_nRTS
O
MFP6
UART1 request to Send output pin.
I2C1_SMBSUS
O
MFP7
I2C1 SMBus SMBSUS pin (PMBus CONTROL pin)
UART7_RXD
I
MFP8
UART7 data receiver input pin.
I2C0_SDA
I/O
MFP9
I2C0 data input/output pin.
BPWM1_CH3
I/O
MFP10
BPWM1 channel 3 output/capture input.
CAN2_RXD
I
MFP12
CAN2 bus receiver input.
INT6
I
MFP13
External interrupt 6 input pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH7
A
MFP1
EADC0 channel 7 analog input.
EBI_nWRL
O
MFP2
EBI low byte write enable output pin.
CAN1_TXD
O
MFP5
CAN1 bus transmitter output.
UART1_TXD
O
MFP6
UART1 data transmitter output pin.
EBI_nCS0
O
MFP8
EBI chip select 0 output pin.
BPWM1_CH4
I/O
MFP10
BPWM1 channel 4 output/capture input.
I
MFP11
EPWM1 Brake 0 input pin.
I/O
MFP12
EPWM1 channel 4 output/capture input.
INT5
I
MFP13
External interrupt 5 input pin.
USB_VBUS_ST
I
MFP14
USB external VBUS regulator status pin.
ACMP0_O
O
MFP15
Analog comparator 0 output pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH6
A
MFP1
EADC0 channel 6 analog input.
EBI_nWRH
O
MFP2
EBI high byte write enable output pin
CAN1_RXD
I
MFP5
CAN1 bus receiver input.
UART1_RXD
I
MFP6
UART1 data receiver input pin.
EBI_nCS1
O
MFP8
EBI chip select 1 output pin.
BPWM1_CH5
I/O
MFP10
BPWM1 channel 5 output/capture input.
I
MFP11
EPWM1 Brake 1 input pin.
I/O
MFP12
EPWM1 channel 5 output/capture input.
INT4
I
MFP13
External interrupt 4 input pin.
USB_VBUS_EN
O
MFP14
USB external VBUS regulator enable pin.
ACMP1_O
O
MFP15
Analog comparator 1 output pin.
64 127 PB.7
EPWM1_BRAKE0
EPWM1_CH4
48
1
128 PB.6
EPWM1_BRAKE1
EPWM1_CH5
May 08, 2020
Page 259 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
M480 SERIES DATASHEET
May 08, 2020
Page 260 of 523
Rev 3.00
M480
4.3.3
M483 Series Pin Description
Note: PA.15 MFP can only be as USB_OTG_ID when enable full-Speed USB.
64 128 Pin Name
Pin Pin
2
1
MFP
Description
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH5
A
MFP1
EADC0 channel 5 analog input.
ACMP1_N
A
MFP1
Analog comparator 1 negative input pin.
EBI_ADR0
O
MFP2
EBI address bus bit 0.
SD0_DAT3
I/O
MFP3
SD/SDIO0 data line bit 3.
SPI1_MISO
I/O
MFP5
SPI1 MISO (Master In, Slave Out) pin.
I C0_SCL
I/O
MFP6
I2C0 clock pin.
UART5_TXD
O
MFP7
UART5 data transmitter output pin.
SC0_CLK
O
MFP9
Smart Card 0 clock pin.
I S0_BCLK
O
MFP10
I2S0 bit clock output pin.
EPWM0_CH0
I/O
MFP11
EPWM0 channel 0 output/capture input.
UART2_TXD
O
MFP12
UART2 data transmitter output pin.
TM0
I/O
MFP14
Timer0 event counter input/toggle output pin.
INT0
I
MFP15
External interrupt 0 input pin.
PB.4
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH4
A
MFP1
EADC0 channel 4 analog input.
ACMP1_P1
A
MFP1
Analog comparator 1 positive input 1 pin.
EBI_ADR1
O
MFP2
EBI address bus bit 1.
SD0_DAT2
I/O
MFP3
SD/SDIO0 data line bit 2.
SPI1_MOSI
I/O
MFP5
SPI1 MOSI (Master Out, Slave In) pin.
I/O
MFP6
I2C0 data input/output pin.
I
MFP7
UART5 data receiver input pin.
SC0_DAT
I/O
MFP9
Smart Card 0 data pin.
I2S0_MCLK
O
MFP10
I2S0 master clock output pin.
EPWM0_CH1
I/O
MFP11
EPWM0 channel 1 output/capture input.
UART2_RXD
I
MFP12
UART2 data receiver input pin.
TM1
I/O
MFP14
Timer1 event counter input/toggle output pin.
INT1
I
MFP15
External interrupt 1 input pin.
PB.3
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH3
A
MFP1
EADC0 channel 3 analog input.
EADC1_CH11
A
MFP1
EADC1 channel 11 analog input.
ACMP0_N
A
MFP1
Analog comparator 0 negative input pin.
PB.5
2
2
3
2
2
I C0_SDA
UART5_RXD
4
3
May 08, 2020
Page 261 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
64 128 Pin Name
Pin Pin
5
4
M480 SERIES DATASHEET
5
Type
MFP
Description
EBI_ADR2
O
MFP2
EBI address bus bit 2.
SD0_DAT1
I/O
MFP3
SD/SDIO0 data line bit 1.
SPI1_CLK
I/O
MFP5
SPI1 serial clock pin.
UART1_TXD
O
MFP6
UART1 data transmitter output pin.
UART5_nRTS
O
MFP7
UART5 request to Send output pin.
SC0_RST
O
MFP9
Smart Card 0 reset pin.
I2S0_DI
I
MFP10
I2S0 data input pin.
EPWM0_CH2
I/O
MFP11
EPWM0 channel 2 output/capture input.
I2C1_SCL
I/O
MFP12
I2C1 clock pin.
TM2
I/O
MFP14
Timer2 event counter input/toggle output pin.
INT2
I
MFP15
External interrupt 2 input pin.
PB.2
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH2
A
MFP1
EADC0 channel 2 analog input.
EADC1_CH10
A
MFP1
EADC1 channel 10 analog input.
ACMP0_P1
A
MFP1
Analog comparator 0 positive input 1 pin.
EBI_ADR3
O
MFP2
EBI address bus bit 3.
SD0_DAT0
I/O
MFP3
SD/SDIO0 data line bit 0.
SPI1_SS
I/O
MFP5
SPI1 slave select pin.
UART1_RXD
I
MFP6
UART1 data receiver input pin.
UART5_nCTS
I
MFP7
UART5 clear to Send input pin.
SC0_PWR
O
MFP9
Smart Card 0 power pin.
I2S0_DO
O
MFP10
I2S0 data output pin.
EPWM0_CH3
I/O
MFP11
EPWM0 channel 3 output/capture input.
I2C1_SDA
I/O
MFP12
I2C1 data input/output pin.
TM3
I/O
MFP14
Timer3 event counter input/toggle output pin.
INT3
I
MFP15
External interrupt 3 input pin.
PC.12
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR4
O
MFP2
EBI address bus bit 4.
UART0_TXD
O
MFP3
UART0 data transmitter output pin.
I C0_SCL
I/O
MFP4
I2C0 clock pin.
UART6_TXD
O
MFP5
UART6 data transmitter output pin.
SC0_nCD
I
MFP9
Smart Card 0 card detect pin.
ECAP1_IC2
I
MFP11
Enhanced capture unit 1 input 2 pin.
I/O
MFP12
EPWM1 channel 0 output/capture input.
2
EPWM1_CH0
May 08, 2020
Page 262 of 523
Rev 3.00
M480
64 128 Pin Name
Pin Pin
6
MFP
ACMP0_O
O
MFP14
Analog comparator 0 output pin.
PC.11
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR5
O
MFP2
EBI address bus bit 5.
UART0_RXD
I
MFP3
UART0 data receiver input pin.
I/O
MFP4
I2C0 data input/output pin.
UART6_RXD
I
MFP5
UART6 data receiver input pin.
ECAP1_IC1
I
MFP11
Enhanced capture unit 1 input 1 pin.
EPWM1_CH1
I/O
MFP12
EPWM1 channel 1 output/capture input.
ACMP1_O
O
MFP14
Analog comparator 1 output pin.
PC.10
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR6
O
MFP2
EBI address bus bit 6.
UART6_nRTS
O
MFP5
UART6 request to Send output pin.
UART3_TXD
O
MFP7
UART3 data transmitter output pin.
CAN1_TXD
O
MFP9
CAN1 bus transmitter output.
ECAP1_IC0
I
MFP11
Enhanced capture unit 1 input 0 pin.
I/O
MFP12
EPWM1 channel 2 output/capture input.
I
MFP14
EADC1 external trigger input.
PC.9
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR7
O
MFP2
EBI address bus bit 7.
UART6_nCTS
I
MFP5
UART6 clear to Send input pin.
UART3_RXD
I
MFP7
UART3 data receiver input pin.
CAN1_RXD
I
MFP9
CAN1 bus receiver input.
I/O
MFP12
EPWM1 channel 3 output/capture input.
I
MFP14
EADC1 external trigger input.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH1
A
MFP1
EADC0 channel 1 analog input.
EADC1_CH9
A
MFP1
EADC1 channel 9 analog input.
EBI_ADR8
O
MFP2
EBI address bus bit 8.
SD0_CLK
O
MFP3
SD/SDIO0 clock output pin
SPI1_I2SMCLK
I/O
MFP5
SPI1 I2S master clock output pin
UART2_TXD
O
MFP7
UART2 data transmitter output pin.
I C1_SCL
I/O
MFP9
I2C1 clock pin.
I2S0_LRCK
O
MFP10
I2S0 left right channel clock output pin.
EPWM0_CH4
I/O
MFP11
EPWM0 channel 4 output/capture input.
2
I C0_SDA
7
EPWM1_CH2
EADC1_ST
8
EPWM1_CH3
EADC1_ST
6
9
PB.1
2
May 08, 2020
Description
Page 263 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
64 128 Pin Name
Pin Pin
Type
MFP
I/O
MFP12
EPWM1 channel 4 output/capture input.
I
MFP13
EPWM0 Brake 0 input pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH0
A
MFP1
EADC0 channel 0 analog input.
EADC1_CH8
A
MFP1
EADC1 channel 8 analog input.
EBI_ADR9
O
MFP2
EBI address bus bit 9.
SD0_CMD
I/O
MFP3
SD/SDIO0 command/response pin
SPI2_I2SMCLK
I/O
MFP4
SPI2 I2S master clock output pin
I
MFP7
UART2 data receiver input pin.
SPI0_I2SMCLK
I/O
MFP8
SPI0 I2S master clock output pin
I2C1_SDA
I/O
MFP9
I2C1 data input/output pin.
EPWM0_CH5
I/O
MFP11
EPWM0 channel 5 output/capture input.
EPWM1_CH5
I/O
MFP12
EPWM1 channel 5 output/capture input.
I
MFP13
EPWM0 Brake 1 input pin.
11 VSS
P
MFP0
Ground pin for digital circuit.
12 VDD
P
MFP0
Power supply for I/O ports and LDO source for internal PLL
and digital circuit.
I/O
MFP0
General purpose digital I/O pin.
EADC1_CH7
A
MFP1
EADC1 channel 7 analog input.
ACMP0_P0
A
MFP1
Analog comparator 0 positive input 0 pin.
EBI_nRD
O
MFP2
EBI read enable output pin.
SPI2_SS
I/O
MFP4
SPI2 slave select pin.
I C2_SCL
I/O
MFP7
I2C2 clock pin.
UART6_TXD
O
MFP8
UART6 data transmitter output pin.
BPWM0_CH0
I/O
MFP9
BPWM0 channel 0 output/capture input.
EPWM0_SYNC_OUT
O
MFP10
EPWM0 counter synchronous trigger output pin.
TM0_EXT
I/O
MFP13
Timer0 external capture input/toggle output pin.
I/O
MFP0
General purpose digital I/O pin.
EADC1_CH6
A
MFP1
EADC1 channel 6 analog input.
ACMP1_P0
A
MFP1
Analog comparator 1 positive input 0 pin.
EBI_nWR
O
MFP2
EBI write enable output pin.
SPI2_CLK
I/O
MFP4
SPI2 serial clock pin.
I2C2_SDA
I/O
MFP7
I2C2 data input/output pin.
I
MFP8
UART6 data receiver input pin.
EPWM1_CH4
EPWM0_BRAKE0
7
10 PB.0
UART2_RXD
EPWM0_BRAKE1
8
13 PA.11
M480 SERIES DATASHEET
2
9
14 PA.10
UART6_RXD
May 08, 2020
Description
Page 264 of 523
Rev 3.00
M480
64 128 Pin Name
Pin Pin
10
11
MFP
Description
BPWM0_CH1
I/O
MFP9
BPWM0 channel 1 output/capture input.
QEI1_INDEX
I
MFP10
Quadrature encoder 1 index input
ECAP0_IC0
I
MFP11
Enhanced capture unit 0 input 0 pin.
TM1_EXT
I/O
MFP13
Timer1 external capture input/toggle output pin.
DAC0_ST
I
MFP14
DAC0 external trigger input.
SWDH_CLK
O
MFP15
Serial Wire Debug Host Clock output
I/O
MFP0
General purpose digital I/O pin.
EADC1_CH5
A
MFP1
EADC1 channel 5 analog input.
EBI_MCLK
O
MFP2
EBI external clock output pin.
SPI2_MISO
I/O
MFP4
SPI2 MISO (Master In, Slave Out) pin.
UART1_TXD
O
MFP7
UART1 data transmitter output pin.
UART7_TXD
O
MFP8
UART7 data transmitter output pin.
BPWM0_CH2
I/O
MFP9
BPWM0 channel 2 output/capture input.
QEI1_A
I
MFP10
Quadrature encoder 1 phase A input
ECAP0_IC1
I
MFP11
Enhanced capture unit 0 input 1 pin.
TM2_EXT
I/O
MFP13
Timer2 external capture input/toggle output pin.
SWDH_DAT
I/O
MFP15
Serial Wire Debug Host Data input/output pin
I/O
MFP0
General purpose digital I/O pin.
EADC1_CH4
A
MFP1
EADC1 channel 4 analog input.
EBI_ALE
O
MFP2
EBI address latch enable output pin.
SPI2_MOSI
I/O
MFP4
SPI2 MOSI (Master Out, Slave In) pin.
UART1_RXD
I
MFP7
UART1 data receiver input pin.
UART7_RXD
I
MFP8
UART7 data receiver input pin.
BPWM0_CH3
I/O
MFP9
BPWM0 channel 3 output/capture input.
QEI1_B
I
MFP10
Quadrature encoder 1 phase B input
ECAP0_IC2
I
MFP11
Enhanced capture unit 0 input 2 pin.
I/O
MFP13
Timer3 external capture input/toggle output pin.
I
MFP15
External interrupt 4 input pin.
I/O
MFP0
General purpose digital I/O pin.
EADC1_CH3
A
MFP1
EADC1 channel 3 analog input.
EBI_ADR10
O
MFP2
EBI address bus bit 10.
SPI2_I2SMCLK
I/O
MFP4
SPI2 I2S master clock output pin
CAN1_TXD
O
MFP5
CAN1 bus transmitter output.
UART2_TXD
O
MFP7
UART2 data transmitter output pin.
15 PA.9
16 PA.8
TM3_EXT
INT4
17 PC.13
May 08, 2020
Page 265 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
64 128 Pin Name
Pin Pin
Type
MFP
Description
BPWM0_CH4
I/O
MFP9
BPWM0 channel 4 output/capture input.
CLKO
O
MFP13
Clock Out
EADC0_ST
I
MFP14
EADC0 external trigger input.
I/O
MFP0
General purpose digital I/O pin.
EADC1_CH2
A
MFP1
EADC1 channel 2 analog input.
EBI_nCS0
O
MFP2
EBI chip select 0 output pin.
CAN1_RXD
I
MFP5
CAN1 bus receiver input.
UART2_RXD
I
MFP7
UART2 data receiver input pin.
BPWM0_CH5
I/O
MFP9
BPWM0 channel 5 output/capture input.
QEI0_INDEX
I
MFP10
Quadrature encoder 0 index input
CLKO
O
MFP13
Clock Out
EADC0_ST
I
MFP14
EADC0 external trigger input.
INT5
I
MFP15
External interrupt 5 input pin.
I/O
MFP0
General purpose digital I/O pin.
EADC1_CH1
A
MFP1
EADC1 channel 1 analog input.
EBI_nCS1
O
MFP2
EBI chip select 1 output pin.
UART1_TXD
O
MFP3
UART1 data transmitter output pin.
CAN0_TXD
O
MFP4
CAN0 bus transmitter output.
QEI0_A
I
MFP10
Quadrature encoder 0 phase A input
INT6
I
MFP15
External interrupt 6 input pin.
I/O
MFP0
General purpose digital I/O pin.
EADC1_CH0
A
MFP1
EADC1 channel 0 analog input.
EBI_nCS2
O
MFP2
EBI chip select 2 output pin.
UART1_RXD
I
MFP3
UART1 data receiver input pin.
CAN0_RXD
I
MFP4
CAN0 bus receiver input.
QEI0_B
I
MFP10
Quadrature encoder 0 phase B input
INT7
I
MFP15
External interrupt 7 input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR11
O
MFP2
EBI address bus bit 11.
SPI2_SS
I/O
MFP3
SPI2 slave select pin.
I2C0_SMBAL
O
MFP4
I2C0 SMBus SMBALTER pin
I2C1_SCL
I/O
MFP5
I2C1 clock pin.
I
MFP7
Camera capture data input bus bit 7.
I/O
MFP13
Timer0 event counter input/toggle output pin.
18 PD.12
19 PD.11
M480 SERIES DATASHEET
20 PD.10
21 PG.2
CCAP_DATA7
TM0
May 08, 2020
Page 266 of 523
Rev 3.00
M480
Type
MFP
Description
22 PG.3
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR12
O
MFP2
EBI address bus bit 12.
SPI2_CLK
I/O
MFP3
SPI2 serial clock pin.
I2C0_SMBSUS
O
MFP4
I2C0 SMBus SMBSUS pin (PMBus CONTROL pin)
I2C1_SDA
I/O
MFP5
I2C1 data input/output pin.
I
MFP7
Camera capture data input bus bit 6.
TM1
I/O
MFP13
Timer1 event counter input/toggle output pin.
23 PG.4
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR13
O
MFP2
EBI address bus bit 13.
SPI2_MISO
I/O
MFP3
SPI2 MISO (Master In, Slave Out) pin.
I
MFP7
Camera capture data input bus bit 5.
I/O
MFP13
Timer2 event counter input/toggle output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR14
O
MFP2
EBI address bus bit 14.
SPI2_MOSI
I/O
MFP3
SPI2 MOSI (Master Out, Slave In) pin.
UART5_TXD
O
MFP6
UART5 data transmitter output pin.
CCAP_DATA4
I
MFP7
Camera capture data input bus bit 4.
I/O
MFP13
Timer3 event counter input/toggle output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR15
O
MFP2
EBI address bus bit 15.
SC0_nCD
I
MFP3
Smart Card 0 card detect pin.
I2S0_BCLK
O
MFP4
I2S0 bit clock output pin.
SPI0_I2SMCLK
I/O
MFP5
SPI0 I2S master clock output pin
UART5_RXD
I
MFP6
UART5 data receiver input pin.
CCAP_DATA3
I
MFP7
Camera capture data input bus bit 3.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR16
O
MFP2
EBI address bus bit 16.
SC0_PWR
O
MFP3
Smart Card 0 power pin.
I2S0_MCLK
O
MFP4
I2S0 master clock output pin.
SPI0_SS
I/O
MFP5
SPI0 slave select pin.
UART5_nRTS
O
MFP6
UART5 request to Send output pin.
CCAP_DATA2
I
MFP7
Camera capture data input bus bit 2.
CAN1_TXD
O
MFP8
CAN1 bus transmitter output.
I/O
MFP0
General purpose digital I/O pin.
CCAP_DATA6
CCAP_DATA5
TM2
24 PF.11
TM3
25 PF.10
26 PF.9
27 PF.8
May 08, 2020
Page 267 of 523
M480 SERIES DATASHEET
64 128 Pin Name
Pin Pin
Rev 3.00
M480
64 128 Pin Name
Pin Pin
Type
MFP
Description
EBI_ADR17
O
MFP2
EBI address bus bit 17.
SC0_RST
O
MFP3
Smart Card 0 reset pin.
I
MFP4
I2S0 data input pin.
I/O
MFP5
SPI0 serial clock pin.
UART5_nCTS
I
MFP6
UART5 clear to Send input pin.
CCAP_DATA1
I
MFP7
Camera capture data input bus bit 1.
CAN1_RXD
I
MFP8
CAN1 bus receiver input.
TAMPER2
I/O
MFP10
TAMPER detector loop pin 2.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR18
O
MFP2
EBI address bus bit 18.
SC0_DAT
I/O
MFP3
Smart Card 0 data pin.
I S0_DO
O
MFP4
I2S0 data output pin.
SPI0_MISO
I/O
MFP5
SPI0 MISO (Master In, Slave Out) pin.
UART4_TXD
O
MFP6
UART4 data transmitter output pin.
CCAP_DATA0
I
MFP7
Camera capture data input bus bit 0.
CAN2_TXD
O
MFP8
CAN2 bus transmitter output.
TAMPER1
I/O
MFP10
TAMPER detector loop pin 1.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR19
O
MFP2
EBI address bus bit 19.
SC0_CLK
O
MFP3
Smart Card 0 clock pin.
I S0_LRCK
O
MFP4
I2S0 left right channel clock output pin.
SPI0_MOSI
I/O
MFP5
SPI0 MOSI (Master Out, Slave In) pin.
UART4_RXD
I
MFP6
UART4 data receiver input pin.
EBI_nCS0
O
MFP7
EBI chip select 0 output pin.
CAN2_RXD
I
MFP8
CAN2 bus receiver input.
TAMPER0
I/O
MFP10
TAMPER detector loop pin 0.
2
I S0_DI
SPI0_CLK
28 PF.7
2
12
29 PF.6
M480 SERIES DATASHEET
2
13
30 VBAT
P
MFP0
Power supply by batteries for RTC.
14
31 PF.5
I/O
MFP0
General purpose digital I/O pin.
UART2_RXD
I
MFP2
UART2 data receiver input pin.
UART2_nCTS
I
MFP4
UART2 clear to Send input pin.
EPWM0_CH0
I/O
MFP7
EPWM0 channel 0 output/capture input.
BPWM0_CH4
I/O
MFP8
BPWM0 channel 4 output/capture input.
EPWM0_SYNC_OUT
O
MFP9
EPWM0 counter synchronous trigger output pin.
X32_IN
I
MFP10
External 32.768 kHz crystal input pin.
May 08, 2020
Page 268 of 523
Rev 3.00
M480
64 128 Pin Name
Pin Pin
MFP
I
MFP11
EADC0 external trigger input.
I/O
MFP0
General purpose digital I/O pin.
UART2_TXD
O
MFP2
UART2 data transmitter output pin.
UART2_nRTS
O
MFP4
UART2 request to Send output pin.
EPWM0_CH1
I/O
MFP7
EPWM0 channel 1 output/capture input.
BPWM0_CH5
I/O
MFP8
BPWM0 channel 5 output/capture input.
X32_OUT
O
MFP10
External 32.768 kHz crystal output pin.
EADC1_ST
I
MFP11
EADC1 external trigger input.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR3
O
MFP2
EBI address bus bit 3.
SPI1_MISO
I/O
MFP3
SPI1 MISO (Master In, Slave Out) pin.
UART7_nRTS
O
MFP4
UART7 request to Send output pin.
UART6_TXD
O
MFP5
UART6 data transmitter output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR2
O
MFP2
EBI address bus bit 2.
SPI1_MOSI
I/O
MFP3
SPI1 MOSI (Master Out, Slave In) pin.
UART7_nCTS
I
MFP4
UART7 clear to Send input pin.
UART6_RXD
I
MFP5
UART6 data receiver input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR1
O
MFP2
EBI address bus bit 1.
SPI1_CLK
I/O
MFP3
SPI1 serial clock pin.
UART7_TXD
O
MFP4
UART7 data transmitter output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR0
O
MFP2
EBI address bus bit 0.
SPI1_SS
I/O
MFP3
SPI1 slave select pin.
I
MFP4
UART7 data receiver input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_nCS0
O
MFP2
EBI chip select 0 output pin.
UART0_TXD
O
MFP3
UART0 data transmitter output pin.
I/O
MFP4
I2C0 clock pin.
I
MFP10
External 4~24 MHz (high speed) crystal input pin.
I/O
MFP11
BPWM1 channel 0 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
O
MFP2
EBI chip select 1 output pin.
EADC0_ST
15
32 PF.4
33 PH.4
34 PH.5
35 PH.6
36 PH.7
UART7_RXD
16
37 PF.3
2
I C0_SCL
XT1_IN
BPWM1_CH0
17
38 PF.2
EBI_nCS1
May 08, 2020
Description
Page 269 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
64 128 Pin Name
Pin Pin
Type
MFP
Description
I
MFP3
UART0 data receiver input pin.
I2C0_SDA
I/O
MFP4
I2C0 data input/output pin.
QSPI0_CLK
I/O
MFP5
Quad SPI0 serial clock pin.
XT1_OUT
O
MFP10
External 4~24 MHz (high speed) crystal output pin.
BPWM1_CH1
I/O
MFP11
BPWM1 channel 1 output/capture input.
39 VSS
P
MFP0
Ground pin for digital circuit.
40 VDD
P
MFP0
Power supply for I/O ports and LDO source for internal PLL
and digital circuit.
41 PE.8
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR10
O
MFP2
EBI address bus bit 10.
I2S0_BCLK
O
MFP4
I2S0 bit clock output pin.
SPI2_CLK
I/O
MFP5
SPI2 serial clock pin.
UART2_TXD
O
MFP7
UART2 data transmitter output pin.
EPWM0_CH0
I/O
MFP10
EPWM0 channel 0 output/capture input.
EPWM0_BRAKE0
I
MFP11
EPWM0 Brake 0 input pin.
ECAP0_IC0
I
MFP12
Enhanced capture unit 0 input 0 pin.
TRACE_DATA3
O
MFP14
ETM Trace Data 3 output pin
I/O
MFP0
General purpose digital I/O pin.
O
MFP2
EBI address bus bit 11.
I S0_MCLK
O
MFP4
I2S0 master clock output pin.
SPI2_MISO
I/O
MFP5
SPI2 MISO (Master In, Slave Out) pin.
UART2_RXD
I
MFP7
UART2 data receiver input pin.
EPWM0_CH1
I/O
MFP10
EPWM0 channel 1 output/capture input.
EPWM0_BRAKE1
I
MFP11
EPWM0 Brake 1 input pin.
ECAP0_IC1
I
MFP12
Enhanced capture unit 0 input 1 pin.
TRACE_DATA2
O
MFP14
ETM Trace Data 2 output pin
I/O
MFP0
General purpose digital I/O pin.
O
MFP2
EBI address bus bit 12.
I
MFP4
I2S0 data input pin.
SPI2_MOSI
I/O
MFP5
SPI2 MOSI (Master Out, Slave In) pin.
UART3_TXD
O
MFP7
UART3 data transmitter output pin.
EPWM0_CH2
I/O
MFP10
EPWM0 channel 2 output/capture input.
EPWM1_BRAKE0
I
MFP11
EPWM1 Brake 0 input pin.
ECAP0_IC2
I
MFP12
Enhanced capture unit 0 input 2 pin.
UART0_RXD
42 PE.9
EBI_ADR11
2
M480 SERIES DATASHEET
43 PE.10
EBI_ADR12
2
I S0_DI
May 08, 2020
Page 270 of 523
Rev 3.00
M480
64 128 Pin Name
Pin Pin
MFP
O
MFP14
ETM Trace Data 1 output pin
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR13
O
MFP2
EBI address bus bit 13.
I2S0_DO
O
MFP4
I2S0 data output pin.
SPI2_SS
I/O
MFP5
SPI2 slave select pin.
UART3_RXD
I
MFP7
UART3 data receiver input pin.
UART1_nCTS
I
MFP8
UART1 clear to Send input pin.
EPWM0_CH3
I/O
MFP10
EPWM0 channel 3 output/capture input.
EPWM1_BRAKE1
I
MFP11
EPWM1 Brake 1 input pin.
ECAP1_IC2
I
MFP13
Enhanced capture unit 1 input 2 pin.
TRACE_DATA0
O
MFP14
ETM Trace Data 0 output pin
I/O
MFP0
General purpose digital I/O pin.
O
MFP2
EBI address bus bit 14.
I S0_LRCK
O
MFP4
I2S0 left right channel clock output pin.
SPI2_I2SMCLK
I/O
MFP5
SPI2 I2S master clock output pin
UART1_nRTS
O
MFP8
UART1 request to Send output pin.
EPWM0_CH4
I/O
MFP10
EPWM0 channel 4 output/capture input.
ECAP1_IC1
I
MFP13
Enhanced capture unit 1 input 1 pin.
TRACE_CLK
O
MFP14
ETM Trace Clock output pin
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR15
O
MFP2
EBI address bus bit 15.
I2C0_SCL
I/O
MFP4
I2C0 clock pin.
UART4_nRTS
O
MFP5
UART4 request to Send output pin.
UART1_TXD
O
MFP8
UART1 data transmitter output pin.
EPWM0_CH5
I/O
MFP10
EPWM0 channel 5 output/capture input.
EPWM1_CH0
I/O
MFP11
EPWM1 channel 0 output/capture input.
BPWM1_CH5
I/O
MFP12
BPWM1 channel 5 output/capture input.
I
MFP13
Enhanced capture unit 1 input 0 pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR16
O
MFP2
EBI address bus bit 16.
I2C0_SDA
I/O
MFP4
I2C0 data input/output pin.
UART4_nCTS
I
MFP5
UART4 clear to Send input pin.
UART1_RXD
I
MFP8
UART1 data receiver input pin.
EPWM1_CH1
I/O
MFP11
EPWM1 channel 1 output/capture input.
TRACE_DATA1
44 PE.11
45 PE.12
EBI_ADR14
2
46 PE.13
ECAP1_IC0
47 PC.8
May 08, 2020
Description
Page 271 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
64 128 Pin Name
Pin Pin
Type
MFP
I/O
MFP12
BPWM1 channel 4 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD9
I/O
MFP2
EBI address/data bus bit 9.
SPI1_MISO
I/O
MFP4
SPI1 MISO (Master In, Slave Out) pin.
UART4_TXD
O
MFP5
UART4 data transmitter output pin.
UART0_nCTS
I
MFP7
UART0 clear to Send input pin.
I2C1_SMBAL
O
MFP8
I2C1 SMBus SMBALTER pin
UART6_TXD
O
MFP9
UART6 data transmitter output pin.
EPWM1_CH2
I/O
MFP11
EPWM1 channel 2 output/capture input.
BPWM1_CH0
I/O
MFP12
BPWM1 channel 0 output/capture input.
TM0
I/O
MFP14
Timer0 event counter input/toggle output pin.
INT3
I
MFP15
External interrupt 3 input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD8
I/O
MFP2
EBI address/data bus bit 8.
SPI1_MOSI
I/O
MFP4
SPI1 MOSI (Master Out, Slave In) pin.
UART4_RXD
I
MFP5
UART4 data receiver input pin.
UART0_nRTS
O
MFP7
UART0 request to Send output pin.
I2C1_SMBSUS
O
MFP8
I2C1 SMBus SMBSUS pin (PMBus CONTROL pin)
UART6_RXD
I
MFP9
UART6 data receiver input pin.
EPWM1_CH3
I/O
MFP11
EPWM1 channel 3 output/capture input.
BPWM1_CH1
I/O
MFP12
BPWM1 channel 1 output/capture input.
TM1
I/O
MFP14
Timer1 event counter input/toggle output pin.
INT2
I
MFP15
External interrupt 2 input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD7
I/O
MFP2
EBI address/data bus bit 7.
SPI1_CLK
I/O
MFP4
SPI1 serial clock pin.
UART0_TXD
O
MFP7
UART0 data transmitter output pin.
I C1_SCL
I/O
MFP8
I2C1 clock pin.
QSPI1_MISO1
I/O
MFP9
Quad SPI1 MISO1 (Master In, Slave Out) pin.
EPWM1_CH4
I/O
MFP11
EPWM1 channel 4 output/capture input.
BPWM1_CH2
I/O
MFP12
BPWM1 channel 2 output/capture input.
ACMP0_WLAT
I
MFP13
Analog comparator 0 window latch input pin
TM2
I/O
MFP14
Timer2 event counter input/toggle output pin.
INT1
I
MFP15
External interrupt 1 input pin.
BPWM1_CH4
18
19
M480 SERIES DATASHEET
20
48 PC.7
49 PC.6
50 PA.7
2
May 08, 2020
Description
Page 272 of 523
Rev 3.00
M480
64 128 Pin Name
Pin Pin
21
Type
MFP
Description
I/O
MFP0
General purpose digital I/O pin.
EBI_AD6
I/O
MFP2
EBI address/data bus bit 6.
SPI1_SS
I/O
MFP4
SPI1 slave select pin.
I
MFP7
UART0 data receiver input pin.
I C1_SDA
I/O
MFP8
I2C1 data input/output pin.
QSPI1_MOSI1
I/O
MFP9
Quad SPI1 MOSI1 (Master Out, Slave In) pin.
EPWM1_CH5
I/O
MFP11
EPWM1 channel 5 output/capture input.
BPWM1_CH3
I/O
MFP12
BPWM1 channel 3 output/capture input.
ACMP1_WLAT
I
MFP13
Analog comparator 1 window latch input pin
TM3
I/O
MFP14
Timer3 event counter input/toggle output pin.
INT0
I
MFP15
External interrupt 0 input pin.
51 PA.6
UART0_RXD
2
22
52 VSS
P
MFP0
Ground pin for digital circuit.
23
53 VDD
P
MFP0
Power supply for I/O ports and LDO source for internal PLL
and digital circuit.
24
54 LDO_CAP
A
MFP0
LDO output pin.
Note: This pin needs to be connected with an external
capacitor.
25
I/O
MFP0
General purpose digital I/O pin.
QSPI0_MISO1
I/O
MFP3
Quad SPI0 MISO1 (Master In, Slave Out) pin.
SPI1_I2SMCLK
I/O
MFP4
SPI1 I2S master clock output pin
UART0_nCTS
I
MFP7
UART0 clear to Send input pin.
UART5_TXD
O
MFP8
UART5 data transmitter output pin.
I2C0_SCL
I/O
MFP9
I2C0 clock pin.
CAN0_TXD
O
MFP10
CAN0 bus transmitter output.
UART0_TXD
O
MFP11
UART0 data transmitter output pin.
BPWM0_CH5
I/O
MFP12
BPWM0 channel 5 output/capture input.
EPWM0_CH0
I/O
MFP13
EPWM0 channel 0 output/capture input.
QEI0_INDEX
I
MFP14
Quadrature encoder 0 index input
I/O
MFP0
General purpose digital I/O pin.
QSPI0_MOSI1
I/O
MFP3
Quad SPI0 MOSI1 (Master Out, Slave In) pin.
SPI0_I2SMCLK
I/O
MFP4
SPI0 I2S master clock output pin
SC0_nCD
I
MFP6
Smart Card 0 card detect pin.
UART0_nRTS
O
MFP7
UART0 request to Send output pin.
UART5_RXD
I
MFP8
UART5 data receiver input pin.
I/O
MFP9
I2C0 data input/output pin.
56 PA.4
2
I C0_SDA
May 08, 2020
Page 273 of 523
M480 SERIES DATASHEET
26
55 PA.5
Rev 3.00
M480
64 128 Pin Name
Pin Pin
Type
MFP
CAN0_RXD
I
MFP10
CAN0 bus receiver input.
UART0_RXD
I
MFP11
UART0 data receiver input pin.
BPWM0_CH4
I/O
MFP12
BPWM0 channel 4 output/capture input.
EPWM0_CH1
I/O
MFP13
EPWM0 channel 1 output/capture input.
I
MFP14
Quadrature encoder 0 phase A input
I/O
MFP0
General purpose digital I/O pin.
QSPI0_SS
I/O
MFP3
Quad SPI0 slave select pin.
SPI0_SS
I/O
MFP4
SPI0 slave select pin.
SC0_PWR
O
MFP6
Smart Card 0 power pin.
UART4_TXD
O
MFP7
UART4 data transmitter output pin.
UART1_TXD
O
MFP8
UART1 data transmitter output pin.
I C1_SCL
I/O
MFP9
I2C1 clock pin.
I2C0_SMBAL
O
MFP10
I2C0 SMBus SMBALTER pin
BPWM0_CH3
I/O
MFP12
BPWM0 channel 3 output/capture input.
EPWM0_CH2
I/O
MFP13
EPWM0 channel 2 output/capture input.
QEI0_B
I
MFP14
Quadrature encoder 0 phase B input
EPWM1_BRAKE1
I
MFP15
EPWM1 Brake 1 input pin.
I/O
MFP0
General purpose digital I/O pin.
QSPI0_CLK
I/O
MFP3
Quad SPI0 serial clock pin.
SPI0_CLK
I/O
MFP4
SPI0 serial clock pin.
SC0_RST
O
MFP6
Smart Card 0 reset pin.
UART4_RXD
I
MFP7
UART4 data receiver input pin.
UART1_RXD
I
MFP8
UART1 data receiver input pin.
I2C1_SDA
I/O
MFP9
I2C1 data input/output pin.
I2C0_SMBSUS
O
MFP10
I2C0 SMBus SMBSUS pin (PMBus CONTROL pin)
BPWM0_CH2
I/O
MFP12
BPWM0 channel 2 output/capture input.
EPWM0_CH3
I/O
MFP13
EPWM0 channel 3 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
QSPI0_MISO0
I/O
MFP3
Quad SPI0 MISO0 (Master In, Slave Out) pin.
SPI0_MISO
I/O
MFP4
SPI0 MISO (Master In, Slave Out) pin.
SC0_DAT
I/O
MFP6
Smart Card 0 data pin.
UART0_TXD
O
MFP7
UART0 data transmitter output pin.
UART1_nCTS
I
MFP8
UART1 clear to Send input pin.
I/O
MFP9
I2C2 clock pin.
QEI0_A
27
57 PA.3
2
28
M480 SERIES DATASHEET
29
58 PA.2
59 PA.1
2
I C2_SCL
May 08, 2020
Description
Page 274 of 523
Rev 3.00
M480
64 128 Pin Name
Pin Pin
30
MFP
CCAP_DATA7
I
MFP10
Camera capture data input bus bit 7.
BPWM0_CH1
I/O
MFP12
BPWM0 channel 1 output/capture input.
EPWM0_CH4
I/O
MFP13
EPWM0 channel 4 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
QSPI0_MOSI0
I/O
MFP3
Quad SPI0 MOSI0 (Master Out, Slave In) pin.
SPI0_MOSI
I/O
MFP4
SPI0 MOSI (Master Out, Slave In) pin.
SC0_CLK
O
MFP6
Smart Card 0 clock pin.
UART0_RXD
I
MFP7
UART0 data receiver input pin.
UART1_nRTS
O
MFP8
UART1 request to Send output pin.
I/O
MFP9
I2C2 data input/output pin.
CCAP_DATA6
I
MFP10
Camera capture data input bus bit 6.
BPWM0_CH0
I/O
MFP12
BPWM0 channel 0 output/capture input.
EPWM0_CH5
I/O
MFP13
EPWM0 channel 5 output/capture input.
I
MFP15
DAC0 external trigger input.
61 VDDIO
P
MFP0
Power supply for PA.0~PA.5.
62 PE.14
I/O
MFP0
General purpose digital I/O pin.
EBI_AD8
I/O
MFP2
EBI address/data bus bit 8.
UART2_TXD
O
MFP3
UART2 data transmitter output pin.
CAN0_TXD
O
MFP4
CAN0 bus transmitter output.
UART6_TXD
O
MFP6
UART6 data transmitter output pin.
I/O
MFP0
General purpose digital I/O pin.
I/O
MFP2
EBI address/data bus bit 9.
UART2_RXD
I
MFP3
UART2 data receiver input pin.
CAN0_RXD
I
MFP4
CAN0 bus receiver input.
UART6_RXD
I
MFP6
UART6 data receiver input pin.
I
MFP0
External reset input: active LOW, with an internal pull-up. Set
this pin low reset to initial state.
60 PA.0
2
I C2_SDA
DAC0_ST
31
63 PE.15
EBI_AD9
32
64 nRESET
Description
Note: It is recommended to use 10 kΩ pull-up resistor and 10
uF capacitor on nRESET pin.
33
65 PF.0
I/O
MFP0
General purpose digital I/O pin.
UART1_TXD
O
MFP2
UART1 data transmitter output pin.
I2C1_SCL
I/O
MFP3
I2C1 clock pin.
UART0_TXD
O
MFP4
UART0 data transmitter output pin.
BPWM1_CH0
I/O
MFP12
BPWM1 channel 0 output/capture input.
ICE_DAT
I/O
MFP14
Serial wired debugger data pin.
Note: It is recommended to use 100 kΩ pull-up resistor on
May 08, 2020
Page 275 of 523
Rev 3.00
M480 SERIES DATASHEET
Type
M480
64 128 Pin Name
Pin Pin
Type
MFP
Description
ICE_DAT pin.
34
66 PF.1
I/O
MFP0
General purpose digital I/O pin.
I
MFP2
UART1 data receiver input pin.
I/O
MFP3
I2C1 data input/output pin.
UART0_RXD
I
MFP4
UART0 data receiver input pin.
BPWM1_CH1
I/O
MFP12
BPWM1 channel 1 output/capture input.
ICE_CLK
I/O
MFP14
Serial wired debugger clock pin.
UART1_RXD
I2C1_SDA
Note: It is recommended to use 100 kΩ pull-up resistor on
ICE_CLK pin.
67 PD.9
I/O
MFP0
General purpose digital I/O pin.
EBI_AD7
I/O
MFP2
EBI address/data bus bit 7.
I2C2_SCL
I/O
MFP3
I2C2 clock pin.
UART2_nCTS
I
MFP4
UART2 clear to Send input pin.
UART7_TXD
O
MFP5
UART7 data transmitter output pin.
CAN2_TXD
O
MFP6
CAN2 bus transmitter output.
I/O
MFP0
General purpose digital I/O pin.
I/O
MFP2
EBI address/data bus bit 6.
I C2_SDA
I/O
MFP3
I2C2 data input/output pin.
UART2_nRTS
O
MFP4
UART2 request to Send output pin.
UART7_RXD
I
MFP5
UART7 data receiver input pin.
CAN2_RXD
I
MFP6
CAN2 bus receiver input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD5
I/O
MFP2
EBI address/data bus bit 5.
QSPI0_MISO1
I/O
MFP4
Quad SPI0 MISO1 (Master In, Slave Out) pin.
UART2_TXD
O
MFP8
UART2 data transmitter output pin.
I2C1_SCL
I/O
MFP9
I2C1 clock pin.
CAN0_TXD
O
MFP10
CAN0 bus transmitter output.
UART4_TXD
O
MFP11
UART4 data transmitter output pin.
EPWM1_CH0
I/O
MFP12
EPWM1 channel 0 output/capture input.
CCAP_DATA5
I
MFP13
Camera capture data input bus bit 5.
I/O
MFP14
Quad SPI1 slave select pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD4
I/O
MFP2
EBI address/data bus bit 4.
QSPI0_MOSI1
I/O
MFP4
Quad SPI0 MOSI1 (Master Out, Slave In) pin.
O
MFP6
I2S0 bit clock output pin.
68 PD.8
EBI_AD6
2
M480 SERIES DATASHEET
35
69 PC.5
QSPI1_SS
36
70 PC.4
2
I S0_BCLK
May 08, 2020
Page 276 of 523
Rev 3.00
M480
64 128 Pin Name
Pin Pin
MFP
Description
I/O
MFP7
SPI1 I2S master clock output pin
I
MFP8
UART2 data receiver input pin.
I/O
MFP9
I2C1 data input/output pin.
CAN0_RXD
I
MFP10
CAN0 bus receiver input.
UART4_RXD
I
MFP11
UART4 data receiver input pin.
EPWM1_CH1
I/O
MFP12
EPWM1 channel 1 output/capture input.
CCAP_DATA4
I
MFP13
Camera capture data input bus bit 4.
I/O
MFP14
Quad SPI1 serial clock pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD3
I/O
MFP2
EBI address/data bus bit 3.
QSPI0_SS
I/O
MFP4
Quad SPI0 slave select pin.
I S0_MCLK
O
MFP6
I2S0 master clock output pin.
SPI1_MISO
I/O
MFP7
SPI1 MISO (Master In, Slave Out) pin.
UART2_nRTS
O
MFP8
UART2 request to Send output pin.
I2C0_SMBAL
O
MFP9
I2C0 SMBus SMBALTER pin
CAN1_TXD
O
MFP10
CAN1 bus transmitter output.
UART3_TXD
O
MFP11
UART3 data transmitter output pin.
EPWM1_CH2
I/O
MFP12
EPWM1 channel 2 output/capture input.
CCAP_DATA3
I
MFP13
Camera capture data input bus bit 3.
QSPI1_MISO0
I/O
MFP14
Quad SPI1 MISO0 (Master In, Slave Out) pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD2
I/O
MFP2
EBI address/data bus bit 2.
QSPI0_CLK
I/O
MFP4
Quad SPI0 serial clock pin.
I
MFP6
I2S0 data input pin.
I/O
MFP7
SPI1 MOSI (Master Out, Slave In) pin.
UART2_nCTS
I
MFP8
UART2 clear to Send input pin.
I2C0_SMBSUS
O
MFP9
I2C0 SMBus SMBSUS pin (PMBus CONTROL pin)
CAN1_RXD
I
MFP10
CAN1 bus receiver input.
UART3_RXD
I
MFP11
UART3 data receiver input pin.
EPWM1_CH3
I/O
MFP12
EPWM1 channel 3 output/capture input.
CCAP_DATA2
I
MFP13
Camera capture data input bus bit 2.
QSPI1_MOSI0
I/O
MFP14
Quad SPI1 MOSI0 (Master Out, Slave In) pin.
I/O
MFP0
General purpose digital I/O pin.
I/O
MFP2
EBI address/data bus bit 1.
SPI1_I2SMCLK
UART2_RXD
2
I C1_SDA
QSPI1_CLK
37
71 PC.3
2
38
72 PC.2
I2S0_DI
SPI1_MOSI
39
73 PC.1
EBI_AD1
May 08, 2020
Page 277 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
64 128 Pin Name
Pin Pin
Type
MFP
Description
QSPI0_MISO0
I/O
MFP4
Quad SPI0 MISO0 (Master In, Slave Out) pin.
I2S0_DO
O
MFP6
I2S0 data output pin.
SPI1_CLK
I/O
MFP7
SPI1 serial clock pin.
UART2_TXD
O
MFP8
UART2 data transmitter output pin.
I C0_SCL
I/O
MFP9
I2C0 clock pin.
CAN2_TXD
O
MFP10
CAN2 bus transmitter output.
EPWM1_CH4
I/O
MFP12
EPWM1 channel 4 output/capture input.
CCAP_DATA1
I
MFP13
Camera capture data input bus bit 1.
ACMP0_O
O
MFP14
Analog comparator 0 output pin.
EADC0_ST
I
MFP15
EADC0 external trigger input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD0
I/O
MFP2
EBI address/data bus bit 0.
QSPI0_MOSI0
I/O
MFP4
Quad SPI0 MOSI0 (Master Out, Slave In) pin.
I S0_LRCK
O
MFP6
I2S0 left right channel clock output pin.
SPI1_SS
I/O
MFP7
SPI1 slave select pin.
I
MFP8
UART2 data receiver input pin.
I/O
MFP9
I2C0 data input/output pin.
I
MFP10
CAN2 bus receiver input.
EPWM1_CH5
I/O
MFP12
EPWM1 channel 5 output/capture input.
CCAP_DATA0
I
MFP13
Camera capture data input bus bit 0.
ACMP1_O
O
MFP14
Analog comparator 1 output pin.
EADC1_ST
I
MFP15
EADC1 external trigger input.
75 VSS
P
MFP0
Ground pin for digital circuit.
76 VDD
P
MFP0
Power supply for I/O ports and LDO source for internal PLL
and digital circuit.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD0
I/O
MFP2
EBI address/data bus bit 0.
QSPI1_MISO1
I/O
MFP5
Quad SPI1 MISO1 (Master In, Slave Out) pin.
CCAP_PIXCLK
I
MFP7
Camera capture interface pix clock input pin.
I/O
MFP12
BPWM0 channel 5 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD1
I/O
MFP2
EBI address/data bus bit 1.
QSPI1_MOSI1
I/O
MFP5
Quad SPI1 MOSI1 (Master Out, Slave In) pin.
CCAP_SCLK
O
MFP7
Camera capture interface sensor clock pin.
2
40
74 PC.0
2
UART2_RXD
2
I C0_SDA
CAN2_RXD
M480 SERIES DATASHEET
77 PG.9
BPWM0_CH5
78 PG.10
May 08, 2020
Page 278 of 523
Rev 3.00
M480
64 128 Pin Name
Pin Pin
MFP
I/O
MFP12
BPWM0 channel 4 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD2
I/O
MFP2
EBI address/data bus bit 2.
QSPI1_SS
I/O
MFP5
Quad SPI1 slave select pin.
UART7_TXD
O
MFP6
UART7 data transmitter output pin.
CCAP_SFIELD
I
MFP7
Camera capture interface SFIELD input pin.
I/O
MFP12
BPWM0 channel 3 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD3
I/O
MFP2
EBI address/data bus bit 3.
QSPI1_CLK
I/O
MFP5
Quad SPI1 serial clock pin.
UART7_RXD
I
MFP6
UART7 data receiver input pin.
CCAP_VSYNC
I
MFP7
Camera capture interface vsync input pin.
BPWM0_CH2
I/O
MFP12
BPWM0 channel 2 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD4
I/O
MFP2
EBI address/data bus bit 4.
QSPI1_MISO0
I/O
MFP5
Quad SPI1 MISO0 (Master In, Slave Out) pin.
UART6_TXD
O
MFP6
UART6 data transmitter output pin.
CCAP_HSYNC
I
MFP7
Camera capture interface hsync input pin.
I/O
MFP12
BPWM0 channel 1 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD5
I/O
MFP2
EBI address/data bus bit 5.
QSPI1_MOSI0
I/O
MFP5
Quad SPI1 MOSI0 (Master Out, Slave In) pin.
UART6_RXD
I
MFP6
UART6 data receiver input pin.
BPWM0_CH0
I/O
MFP12
BPWM0 channel 0 output/capture input.
83 PG.15
I/O
MFP0
General purpose digital I/O pin.
CLKO
O
MFP14
Clock Out
EADC0_ST
I
MFP15
EADC0 external trigger input.
PD.3
I/O
MFP0
General purpose digital I/O pin.
EBI_AD10
I/O
MFP2
EBI address/data bus bit 10.
SPI0_SS
I/O
MFP4
SPI0 slave select pin.
UART3_nRTS
O
MFP5
UART3 request to Send output pin.
UART0_TXD
O
MFP9
UART0 data transmitter output pin.
PD.2
I/O
MFP0
General purpose digital I/O pin.
EBI_AD11
I/O
MFP2
EBI address/data bus bit 11.
BPWM0_CH4
79 PG.11
BPWM0_CH3
80 PG.12
81 PG.13
BPWM0_CH1
82 PG.14
41
42
May 08, 2020
Description
Page 279 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
64 128 Pin Name
Pin Pin
Type
MFP
Description
I/O
MFP4
SPI0 serial clock pin.
UART3_nCTS
I
MFP5
UART3 clear to Send input pin.
UART0_RXD
I
MFP9
UART0 data receiver input pin.
PD.1
I/O
MFP0
General purpose digital I/O pin.
EBI_AD12
I/O
MFP2
EBI address/data bus bit 12.
SPI0_MISO
I/O
MFP4
SPI0 MISO (Master In, Slave Out) pin.
UART3_TXD
O
MFP5
UART3 data transmitter output pin.
I2C2_SCL
I/O
MFP6
I2C2 clock pin.
PD.0
I/O
MFP0
General purpose digital I/O pin.
EBI_AD13
I/O
MFP2
EBI address/data bus bit 13.
SPI0_MOSI
I/O
MFP4
SPI0 MOSI (Master Out, Slave In) pin.
I
MFP5
UART3 data receiver input pin.
I2C2_SDA
I/O
MFP6
I2C2 data input/output pin.
TM2
I/O
MFP14
Timer2 event counter input/toggle output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD10
I/O
MFP2
EBI address/data bus bit 10.
SD0_nCD
I
MFP3
SD/SDIO0 card detect input pin
SPI0_I2SMCLK
I/O
MFP4
SPI0 I2S master clock output pin
SPI1_I2SMCLK
I/O
MFP5
SPI1 I2S master clock output pin
I/O
MFP0
General purpose digital I/O pin.
I2S0_BCLK
O
MFP2
I2S0 bit clock output pin.
UART4_TXD
O
MFP3
UART4 data transmitter output pin.
I C1_SCL
I/O
MFP4
I2C1 clock pin.
SPI2_SS
I/O
MFP5
SPI2 slave select pin.
CAN0_TXD
O
MFP6
CAN0 bus transmitter output.
BPWM1_CH2
I/O
MFP11
BPWM1 channel 2 output/capture input.
QEI1_INDEX
I
MFP12
Quadrature encoder 1 index input
USB_VBUS
P
MFP14
Power supply from USB host or HUB.
I/O
MFP0
General purpose digital I/O pin.
I2S0_MCLK
O
MFP2
I2S0 master clock output pin.
UART4_RXD
I
MFP3
UART4 data receiver input pin.
I C1_SDA
I/O
MFP4
I2C1 data input/output pin.
SPI2_CLK
I/O
MFP5
SPI2 serial clock pin.
I
MFP6
CAN0 bus receiver input.
SPI0_CLK
43
44
UART3_RXD
84 PD.13
M480 SERIES DATASHEET
45
85 PA.12
2
46
86 PA.13
2
CAN0_RXD
May 08, 2020
Page 280 of 523
Rev 3.00
M480
64 128 Pin Name
Pin Pin
MFP
I/O
MFP11
BPWM1 channel 3 output/capture input.
QEI1_A
I
MFP12
Quadrature encoder 1 phase A input
USB_D-
A
MFP14
USB differential signal D-.
87 PA.14
I/O
MFP0
General purpose digital I/O pin.
2
I S0_DI
I
MFP2
I2S0 data input pin.
UART0_TXD
O
MFP3
UART0 data transmitter output pin.
SPI2_MISO
I/O
MFP5
SPI2 MISO (Master In, Slave Out) pin.
I C2_SCL
I/O
MFP6
I2C2 clock pin.
BPWM1_CH4
I/O
MFP11
BPWM1 channel 4 output/capture input.
QEI1_B
I
MFP12
Quadrature encoder 1 phase B input
USB_D+
A
MFP14
USB differential signal D+.
I/O
MFP0
General purpose digital I/O pin.
I2S0_DO
O
MFP2
I2S0 data output pin.
UART0_RXD
I
MFP3
UART0 data receiver input pin.
SPI2_MOSI
I/O
MFP5
SPI2 MOSI (Master Out, Slave In) pin.
I2C2_SDA
I/O
MFP6
I2C2 data input/output pin.
BPWM1_CH5
I/O
MFP11
BPWM1 channel 5 output/capture input.
EPWM0_SYNC_IN
I
MFP12
EPWM0 counter synchronous trigger input pin.
USB_OTG_ID
I
MFP14
USB_ identification.
89 NC
-
MFP0
No connect pin, leave floating.
90 NC
-
MFP0
No connect pin, leave floating.
91 NC
-
MFP0
No connect pin, leave floating.
92 NC
-
MFP0
No connect pin, leave floating.
93 NC
-
MFP0
No connect pin, leave floating.
94 NC
-
MFP0
No connect pin, leave floating.
95 NC
-
MFP0
No connect pin, leave floating.
96 NC
-
MFP0
No connect pin, leave floating.
I/O
MFP0
General purpose digital I/O pin.
SD0_CMD
I/O
MFP3
SD/SDIO0 command/response pin
UART5_TXD
O
MFP8
UART5 data transmitter output pin.
CAN1_TXD
O
MFP9
CAN1 bus transmitter output.
QEI1_INDEX
I
MFP11
Quadrature encoder 1 index input
EPWM0_CH0
I/O
MFP12
EPWM0 channel 0 output/capture input.
BPWM0_CH5
I/O
MFP13
BPWM0 channel 5 output/capture input.
BPWM1_CH3
47
2
48
88 PA.15
97 PE.7
May 08, 2020
Description
Page 281 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
64 128 Pin Name
Pin Pin
Type
MFP
Description
98 PE.6
I/O
MFP0
General purpose digital I/O pin.
SD0_CLK
O
MFP3
SD/SDIO0 clock output pin
SC0_nCD
I
MFP6
Smart Card 0 card detect pin.
UART5_RXD
I
MFP8
UART5 data receiver input pin.
CAN1_RXD
I
MFP9
CAN1 bus receiver input.
QEI1_A
I
MFP11
Quadrature encoder 1 phase A input
EPWM0_CH1
I/O
MFP12
EPWM0 channel 1 output/capture input.
BPWM0_CH4
I/O
MFP13
BPWM0 channel 4 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_nRD
O
MFP2
EBI read enable output pin.
SD0_DAT3
I/O
MFP3
SD/SDIO0 data line bit 3.
SC0_PWR
O
MFP6
Smart Card 0 power pin.
UART6_TXD
O
MFP8
UART6 data transmitter output pin.
UART7_nRTS
O
MFP9
UART7 request to Send output pin.
QEI1_B
I
MFP11
Quadrature encoder 1 phase B input
EPWM0_CH2
I/O
MFP12
EPWM0 channel 2 output/capture input.
BPWM0_CH3
I/O
MFP13
BPWM0 channel 3 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_nWR
O
MFP2
EBI write enable output pin.
SD0_DAT2
I/O
MFP3
SD/SDIO0 data line bit 2.
SC0_RST
O
MFP6
Smart Card 0 reset pin.
UART6_RXD
I
MFP8
UART6 data receiver input pin.
UART7_nCTS
I
MFP9
UART7 clear to Send input pin.
QEI0_INDEX
I
MFP11
Quadrature encoder 0 index input
EPWM0_CH3
I/O
MFP12
EPWM0 channel 3 output/capture input.
BPWM0_CH2
I/O
MFP13
BPWM0 channel 2 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_MCLK
O
MFP2
EBI external clock output pin.
SD0_DAT1
I/O
MFP3
SD/SDIO0 data line bit 1.
SC0_DAT
I/O
MFP6
Smart Card 0 data pin.
UART6_nRTS
O
MFP8
UART6 request to Send output pin.
UART7_TXD
O
MFP9
UART7 data transmitter output pin.
QEI0_A
I
MFP11
Quadrature encoder 0 phase A input
I/O
MFP12
EPWM0 channel 4 output/capture input.
99 PE.5
100 PE.4
M480 SERIES DATASHEET
101 PE.3
EPWM0_CH4
May 08, 2020
Page 282 of 523
Rev 3.00
M480
64 128 Pin Name
Pin Pin
MFP
I/O
MFP13
BPWM0 channel 1 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_ALE
O
MFP2
EBI address latch enable output pin.
SD0_DAT0
I/O
MFP3
SD/SDIO0 data line bit 0.
SC0_CLK
O
MFP6
Smart Card 0 clock pin.
UART6_nCTS
I
MFP8
UART6 clear to Send input pin.
UART7_RXD
I
MFP9
UART7 data receiver input pin.
QEI0_B
I
MFP11
Quadrature encoder 0 phase B input
EPWM0_CH5
I/O
MFP12
EPWM0 channel 5 output/capture input.
BPWM0_CH0
I/O
MFP13
BPWM0 channel 0 output/capture input.
103 VSS
P
MFP0
Ground pin for digital circuit.
104 VDD
P
MFP0
Power supply for I/O ports and LDO source for internal PLL
and digital circuit.
105 PE.1
I/O
MFP0
General purpose digital I/O pin.
EBI_AD10
I/O
MFP2
EBI address/data bus bit 10.
QSPI0_MISO0
I/O
MFP3
Quad SPI0 MISO0 (Master In, Slave Out) pin.
I2S0_BCLK
O
MFP5
I2S0 bit clock output pin.
SPI1_MISO
I/O
MFP6
SPI1 MISO (Master In, Slave Out) pin.
UART3_TXD
O
MFP7
UART3 data transmitter output pin.
I/O
MFP8
I2C1 clock pin.
I
MFP9
UART4 clear to Send input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD11
I/O
MFP2
EBI address/data bus bit 11.
QSPI0_MOSI0
I/O
MFP3
Quad SPI0 MOSI0 (Master Out, Slave In) pin.
I S0_MCLK
O
MFP5
I2S0 master clock output pin.
SPI1_MOSI
I/O
MFP6
SPI1 MOSI (Master Out, Slave In) pin.
I
MFP7
UART3 data receiver input pin.
I2C1_SDA
I/O
MFP8
I2C1 data input/output pin.
UART4_nRTS
O
MFP9
UART4 request to Send output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD12
I/O
MFP2
EBI address/data bus bit 12.
QSPI0_CLK
I/O
MFP3
Quad SPI0 serial clock pin.
I
MFP5
I2S0 data input pin.
I/O
MFP6
SPI1 serial clock pin.
BPWM0_CH1
102 PE.2
2
I C1_SCL
UART4_nCTS
106 PE.0
2
UART3_RXD
107 PH.8
I2S0_DI
SPI1_CLK
May 08, 2020
Description
Page 283 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
64 128 Pin Name
Pin Pin
Type
MFP
Description
UART3_nRTS
O
MFP7
UART3 request to Send output pin.
I2C1_SMBAL
O
MFP8
I2C1 SMBus SMBALTER pin
I2C2_SCL
I/O
MFP9
I2C2 clock pin.
UART1_TXD
O
MFP10
UART1 data transmitter output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD13
I/O
MFP2
EBI address/data bus bit 13.
QSPI0_SS
I/O
MFP3
Quad SPI0 slave select pin.
I S0_DO
O
MFP5
I2S0 data output pin.
SPI1_SS
I/O
MFP6
SPI1 slave select pin.
UART3_nCTS
I
MFP7
UART3 clear to Send input pin.
I2C1_SMBSUS
O
MFP8
I2C1 SMBus SMBSUS pin (PMBus CONTROL pin)
I2C2_SDA
I/O
MFP9
I2C2 data input/output pin.
I
MFP10
UART1 data receiver input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD14
I/O
MFP2
EBI address/data bus bit 14.
QSPI0_MISO1
I/O
MFP3
Quad SPI0 MISO1 (Master In, Slave Out) pin.
I S0_LRCK
O
MFP5
I2S0 left right channel clock output pin.
SPI1_I2SMCLK
I/O
MFP6
SPI1 I2S master clock output pin
UART4_TXD
O
MFP7
UART4 data transmitter output pin.
UART0_TXD
O
MFP8
UART0 data transmitter output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD15
I/O
MFP2
EBI address/data bus bit 15.
QSPI0_MOSI1
I/O
MFP3
Quad SPI0 MOSI1 (Master Out, Slave In) pin.
UART4_RXD
I
MFP7
UART4 data receiver input pin.
UART0_RXD
I
MFP8
UART0 data receiver input pin.
EPWM0_CH5
I/O
MFP11
EPWM0 channel 5 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_nCS0
O
MFP2
EBI chip select 0 output pin.
SPI0_I2SMCLK
I/O
MFP5
SPI0 I2S master clock output pin
EPWM0_CH4
I/O
MFP11
EPWM0 channel 4 output/capture input.
108 PH.9
2
UART1_RXD
109 PH.10
2
M480 SERIES DATASHEET
110 PH.11
111 PD.14
49
112 VSS
P
MFP0
Ground pin for digital circuit.
50
113 LDO_CAP
A
MFP0
LDO output pin.
Note: This pin needs to be connected with an external
capacitor.
51
114 VDD
May 08, 2020
P
MFP0
Power supply for I/O ports and LDO source for internal PLL
Page 284 of 523
Rev 3.00
M480
64 128 Pin Name
Pin Pin
Type
MFP
Description
and digital circuit.
52
115 PC.14
MFP0
General purpose digital I/O pin.
EBI_AD11
I/O
MFP2
EBI address/data bus bit 11.
SPI0_I2SMCLK
I/O
MFP4
SPI0 I2S master clock output pin
QSPI0_CLK
I/O
MFP6
Quad SPI0 serial clock pin.
EPWM0_SYNC_IN
I
MFP11
EPWM0 counter synchronous trigger input pin.
ETM_TRACE_CLK
I
MFP12
ETM receiver Trace Clock input pin
I/O
MFP13
Timer1 event counter input/toggle output pin.
I
MFP14
USB external VBUS regulator status pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH15
A
MFP1
EADC0 channel 15 analog input.
EADC1_CH15
A
MFP1
EADC1 channel 15 analog input.
EBI_AD12
I/O
MFP2
EBI address/data bus bit 12.
SPI0_SS
I/O
MFP4
SPI0 slave select pin.
UART0_nCTS
I
MFP6
UART0 clear to Send input pin.
UART3_TXD
O
MFP7
UART3 data transmitter output pin.
I C2_SMBAL
O
MFP8
I2C2 SMBus SMBALTER pin
EPWM0_BRAKE1
I
MFP10
EPWM0 Brake 1 input pin.
I/O
MFP11
EPWM1 channel 0 output/capture input.
I
MFP12
ETM receiver Trace Data 0 input pin
TM0_EXT
I/O
MFP13
Timer0 external capture input/toggle output pin.
USB_VBUS_EN
O
MFP14
USB external VBUS regulator enable pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH14
A
MFP1
EADC0 channel 14 analog input.
EADC1_CH14
A
MFP1
EADC1 channel 14 analog input.
EBI_AD13
I/O
MFP2
EBI address/data bus bit 13.
SPI0_CLK
I/O
MFP4
SPI0 serial clock pin.
UART0_nRTS
O
MFP6
UART0 request to Send output pin.
UART3_RXD
I
MFP7
UART3 data receiver input pin.
I C2_SMBSUS
O
MFP8
I2C2 SMBus SMBSUS pin (PMBus CONTROL pin)
EPWM1_CH1
I/O
MFP11
EPWM1 channel 1 output/capture input.
I
MFP12
ETM receiver Trace Data 1 input pin
TM1_EXT
I/O
MFP13
Timer1 external capture input/toggle output pin.
CLKO
O
MFP14
Clock Out
TM1
USB_VBUS_ST
53
116 PB.15
2
EPWM1_CH0
ETM_TRACE_DATA0
54
117 PB.14
2
ETM_TRACE_DATA1
May 08, 2020
Page 285 of 523
M480 SERIES DATASHEET
I/O
Rev 3.00
M480
64 128 Pin Name
Pin Pin
Type
MFP
I
MFP15
USB external VBUS regulator status pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH13
A
MFP1
EADC0 channel 13 analog input.
EADC1_CH13
A
MFP1
EADC1 channel 13 analog input.
ACMP0_P3
A
MFP1
Analog comparator 0 positive input 3 pin.
ACMP1_P3
A
MFP1
Analog comparator 1 positive input 3 pin.
EBI_AD14
I/O
MFP2
EBI address/data bus bit 14.
SPI0_MISO
I/O
MFP4
SPI0 MISO (Master In, Slave Out) pin.
UART0_TXD
O
MFP6
UART0 data transmitter output pin.
UART3_nRTS
O
MFP7
UART3 request to Send output pin.
I2C2_SCL
I/O
MFP8
I2C2 clock pin.
I
MFP10
Camera capture interface pix clock input pin.
I/O
MFP11
EPWM1 channel 2 output/capture input.
I
MFP12
ETM receiver Trace Data 2 input pin
I/O
MFP13
Timer2 external capture input/toggle output pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH12
A
MFP1
EADC0 channel 12 analog input.
EADC1_CH12
A
MFP1
EADC1 channel 12 analog input.
DAC0_OUT
A
MFP1
DAC0 channel analog output.
ACMP0_P2
A
MFP1
Analog comparator 0 positive input 2 pin.
ACMP1_P2
A
MFP1
Analog comparator 1 positive input 2 pin.
EBI_AD15
I/O
MFP2
EBI address/data bus bit 15.
SPI0_MOSI
I/O
MFP4
SPI0 MOSI (Master Out, Slave In) pin.
UART0_RXD
I
MFP6
UART0 data receiver input pin.
UART3_nCTS
I
MFP7
UART3 clear to Send input pin.
I2C2_SDA
I/O
MFP8
I2C2 data input/output pin.
SD0_nCD
I
MFP9
SD/SDIO0 card detect input pin
CCAP_SCLK
O
MFP10
Camera capture interface sensor clock pin.
EPWM1_CH3
I/O
MFP11
EPWM1 channel 3 output/capture input.
I
MFP12
ETM receiver Trace Data 3 input pin
I/O
MFP13
Timer3 external capture input/toggle output pin.
USB_VBUS_ST
55
118 PB.13
CCAP_PIXCLK
EPWM1_CH2
ETM_TRACE_DATA2
TM2_EXT
56
119 PB.12
M480 SERIES DATASHEET
ETM_TRACE_DATA3
TM3_EXT
Description
57
120 AVDD
P
MFP0
Power supply for internal analog circuit.
58
121 VREF
A
MFP0
ADC reference voltage input.
Note: This pin needs to be connected with a 1uF capacitor.
May 08, 2020
Page 286 of 523
Rev 3.00
M480
64 128 Pin Name
Pin Pin
Type
MFP
Description
122 AVSS
P
MFP0
Ground pin for analog circuit.
60
123 PB.11
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH11
A
MFP1
EADC0 channel 11 analog input.
EBI_ADR16
O
MFP2
EBI address bus bit 16.
UART0_nCTS
I
MFP5
UART0 clear to Send input pin.
UART4_TXD
O
MFP6
UART4 data transmitter output pin.
I2C1_SCL
I/O
MFP7
I2C1 clock pin.
CAN0_TXD
O
MFP8
CAN0 bus transmitter output.
SPI0_I2SMCLK
I/O
MFP9
SPI0 I2S master clock output pin
BPWM1_CH0
I/O
MFP10
BPWM1 channel 0 output/capture input.
I
MFP12
Camera capture interface SFIELD input pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH10
A
MFP1
EADC0 channel 10 analog input.
EBI_ADR17
O
MFP2
EBI address bus bit 17.
UART0_nRTS
O
MFP5
UART0 request to Send output pin.
UART4_RXD
I
MFP6
UART4 data receiver input pin.
I/O
MFP7
I2C1 data input/output pin.
I
MFP8
CAN0 bus receiver input.
BPWM1_CH1
I/O
MFP10
BPWM1 channel 1 output/capture input.
CCAP_VSYNC
I
MFP12
Camera capture interface vsync input pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH9
A
MFP1
EADC0 channel 9 analog input.
EBI_ADR18
O
MFP2
EBI address bus bit 18.
UART0_TXD
O
MFP5
UART0 data transmitter output pin.
UART1_nCTS
I
MFP6
UART1 clear to Send input pin.
I2C1_SMBAL
O
MFP7
I2C1 SMBus SMBALTER pin
UART7_TXD
O
MFP8
UART7 data transmitter output pin.
I C0_SCL
I/O
MFP9
I2C0 clock pin.
BPWM1_CH2
I/O
MFP10
BPWM1 channel 2 output/capture input.
CAN2_TXD
O
MFP12
CAN2 bus transmitter output.
INT7
I
MFP13
External interrupt 7 input pin.
CCAP_HSYNC
I
MFP14
Camera capture interface hsync input pin.
I/O
MFP0
General purpose digital I/O pin.
A
MFP1
EADC0 channel 8 analog input.
CCAP_SFIELD
61
124 PB.10
2
I C1_SDA
CAN0_RXD
62
125 PB.9
2
63
126 PB.8
EADC0_CH8
May 08, 2020
Page 287 of 523
M480 SERIES DATASHEET
59
Rev 3.00
M480
64 128 Pin Name
Pin Pin
64
Type
MFP
Description
EBI_ADR19
O
MFP2
EBI address bus bit 19.
UART0_RXD
I
MFP5
UART0 data receiver input pin.
UART1_nRTS
O
MFP6
UART1 request to Send output pin.
I2C1_SMBSUS
O
MFP7
I2C1 SMBus SMBSUS pin (PMBus CONTROL pin)
UART7_RXD
I
MFP8
UART7 data receiver input pin.
I2C0_SDA
I/O
MFP9
I2C0 data input/output pin.
BPWM1_CH3
I/O
MFP10
BPWM1 channel 3 output/capture input.
CAN2_RXD
I
MFP12
CAN2 bus receiver input.
INT6
I
MFP13
External interrupt 6 input pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH7
A
MFP1
EADC0 channel 7 analog input.
EBI_nWRL
O
MFP2
EBI low byte write enable output pin.
CAN1_TXD
O
MFP5
CAN1 bus transmitter output.
UART1_TXD
O
MFP6
UART1 data transmitter output pin.
EBI_nCS0
O
MFP8
EBI chip select 0 output pin.
BPWM1_CH4
I/O
MFP10
BPWM1 channel 4 output/capture input.
I
MFP11
EPWM1 Brake 0 input pin.
I/O
MFP12
EPWM1 channel 4 output/capture input.
INT5
I
MFP13
External interrupt 5 input pin.
USB_VBUS_ST
I
MFP14
USB external VBUS regulator status pin.
ACMP0_O
O
MFP15
Analog comparator 0 output pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH6
A
MFP1
EADC0 channel 6 analog input.
EBI_nWRH
O
MFP2
EBI high byte write enable output pin
CAN1_RXD
I
MFP5
CAN1 bus receiver input.
UART1_RXD
I
MFP6
UART1 data receiver input pin.
EBI_nCS1
O
MFP8
EBI chip select 1 output pin.
BPWM1_CH5
I/O
MFP10
BPWM1 channel 5 output/capture input.
I
MFP11
EPWM1 Brake 1 input pin.
I/O
MFP12
EPWM1 channel 5 output/capture input.
INT4
I
MFP13
External interrupt 4 input pin.
USB_VBUS_EN
O
MFP14
USB external VBUS regulator enable pin.
ACMP1_O
O
MFP15
Analog comparator 1 output pin.
127 PB.7
EPWM1_BRAKE0
EPWM1_CH4
M480 SERIES DATASHEET
1
128 PB.6
EPWM1_BRAKE1
EPWM1_CH5
May 08, 2020
Page 288 of 523
Rev 3.00
M480
4.4 M487KMCAN Pin Description
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.0 MFP0 means SYS_GPA_MFPL[3:0] = 0x0.
PA.9 MFP5 means SYS_GPA_MFPH[7:4] = 0x5.
Note: PA.15 MFP can only be as USB_OTG_ID when enable full-Speed USB.
Type
MFP
Description
1
PB.5
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH5
A
MFP1
EADC0 channel 5 analog input.
ACMP1_N
A
MFP1
Analog comparator 1 negative input pin.
EBI_ADR0
O
MFP2
EBI address bus bit 0.
SD0_DAT3
I/O
MFP3
SD/SDIO0 data line bit 3.
EMAC_RMII_REFCLK
I
MFP4
EMAC RMII reference clock input pin.
SPI1_MISO
I/O
MFP5
SPI1 MISO (Master In, Slave Out) pin.
I C0_SCL
I/O
MFP6
I2C0 clock pin.
UART5_TXD
O
MFP7
UART5 data transmitter output pin.
USCI1_CTL0
I/O
MFP8
USCI1 control 0 pin.
SC0_CLK
O
MFP9
Smart Card 0 clock pin.
I S0_BCLK
O
MFP10
I2S0 bit clock output pin.
EPWM0_CH0
I/O
MFP11
EPWM0 channel 0 output/capture input.
TM0
I/O
MFP14
Timer0 event counter input/toggle output pin.
INT0
I
MFP15
External interrupt 0 input pin.
PB.4
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH4
A
MFP1
EADC0 channel 4 analog input.
ACMP1_P1
A
MFP1
Analog comparator 1 positive input 1 pin.
EBI_ADR1
O
MFP2
EBI address bus bit 1.
SD0_DAT2
I/O
MFP3
SD/SDIO0 data line bit 2.
EMAC_RMII_RXD0
I
MFP4
EMAC RMII Receive Data bus bit 0.
SPI1_MOSI
I/O
MFP5
SPI1 MOSI (Master Out, Slave In) pin.
I2C0_SDA
I/O
MFP6
I2C0 data input/output pin.
UART5_RXD
I
MFP7
UART5 data receiver input pin.
USCI1_CTL1
I/O
MFP8
USCI1 control 1 pin.
SC0_DAT
I/O
MFP9
Smart Card 0 data pin.
I2S0_MCLK
O
MFP10
I2S0 master clock output pin.
EPWM0_CH1
I/O
MFP11
EPWM0 channel 1 output/capture input.
2
2
2
May 08, 2020
Page 289 of 523
M480 SERIES DATASHEET
128 Pin Name
Pin
Rev 3.00
M480
128 Pin Name
Pin
3
Type
MFP
Description
TM1
I/O
MFP14
Timer1 event counter input/toggle output pin.
INT1
I
MFP15
External interrupt 1 input pin.
PB.3
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH3
A
MFP1
EADC0 channel 3 analog input.
ACMP0_N
A
MFP1
Analog comparator 0 negative input pin.
EBI_ADR2
O
MFP2
EBI address bus bit 2.
SD0_DAT1
I/O
MFP3
SD/SDIO0 data line bit 1.
EMAC_RMII_RXD1
I
MFP4
EMAC RMII Receive Data bus bit 1.
SPI1_CLK
I/O
MFP5
SPI1 serial clock pin.
UART1_TXD
O
MFP6
UART1 data transmitter output pin.
UART5_nRTS
O
MFP7
UART5 request to Send output pin.
USCI1_DAT1
I/O
MFP8
USCI1 data 1 pin.
SC0_RST
O
MFP9
Smart Card 0 reset pin.
I S0_DI
I
MFP10
I2S0 data input pin.
EPWM0_CH2
I/O
MFP11
EPWM0 channel 2 output/capture input.
TM2
I/O
MFP14
Timer2 event counter input/toggle output pin.
INT2
I
MFP15
External interrupt 2 input pin.
PB.2
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH2
A
MFP1
EADC0 channel 2 analog input.
ACMP0_P1
A
MFP1
Analog comparator 0 positive input 1 pin.
OPA0_O
A
MFP1
Operational amplifier 0 output pin.
EBI_ADR3
O
MFP2
EBI address bus bit 3.
SD0_DAT0
I/O
MFP3
SD/SDIO0 data line bit 0.
EMAC_RMII_CRSDV
I
MFP4
EMAC RMII Carrier Sense/Receive Data input pin.
SPI1_SS
I/O
MFP5
SPI1 slave select pin.
UART1_RXD
I
MFP6
UART1 data receiver input pin.
UART5_nCTS
I
MFP7
UART5 clear to Send input pin.
USCI1_DAT0
I/O
MFP8
USCI1 data 0 pin.
SC0_PWR
O
MFP9
Smart Card 0 power pin.
I S0_DO
O
MFP10
I2S0 data output pin.
EPWM0_CH3
I/O
MFP11
EPWM0 channel 3 output/capture input.
TM3
I/O
MFP14
Timer3 event counter input/toggle output pin.
INT3
I
MFP15
External interrupt 3 input pin.
PC.12
I/O
MFP0
General purpose digital I/O pin.
2
4
M480 SERIES DATASHEET
2
5
May 08, 2020
Page 290 of 523
Rev 3.00
M480
128 Pin Name
Pin
MFP
Description
EBI_ADR4
O
MFP2
EBI address bus bit 4.
UART0_TXD
O
MFP3
UART0 data transmitter output pin.
I C0_SCL
I/O
MFP4
I2C0 clock pin.
SPI3_MISO
I/O
MFP6
SPI3 MISO (Master In, Slave Out) pin.
SC0_nCD
I
MFP9
Smart Card 0 card detect pin.
ECAP1_IC2
I
MFP11
Enhanced capture unit 1 input 2 pin.
EPWM1_CH0
I/O
MFP12
EPWM1 channel 0 output/capture input.
ACMP0_O
O
MFP14
Analog comparator 0 output pin.
PC.11
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR5
O
MFP2
EBI address bus bit 5.
UART0_RXD
I
MFP3
UART0 data receiver input pin.
I C0_SDA
I/O
MFP4
I2C0 data input/output pin.
SPI3_MOSI
I/O
MFP6
SPI3 MOSI (Master Out, Slave In) pin.
ECAP1_IC1
I
MFP11
Enhanced capture unit 1 input 1 pin.
EPWM1_CH1
I/O
MFP12
EPWM1 channel 1 output/capture input.
ACMP1_O
O
MFP14
Analog comparator 1 output pin.
PC.10
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR6
O
MFP2
EBI address bus bit 6.
SPI3_CLK
I/O
MFP6
SPI3 serial clock pin.
UART3_TXD
O
MFP7
UART3 data transmitter output pin.
CAN1_TXD
O
MFP9
CAN1 bus transmitter output.
ECAP1_IC0
I
MFP11
Enhanced capture unit 1 input 0 pin.
EPWM1_CH2
I/O
MFP12
EPWM1 channel 2 output/capture input.
PC.9
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR7
O
MFP2
EBI address bus bit 7.
SPI3_SS
I/O
MFP6
SPI3 slave select pin.
UART3_RXD
I
MFP7
UART3 data receiver input pin.
CAN1_RXD
I
MFP9
CAN1 bus receiver input.
EPWM1_CH3
I/O
MFP12
EPWM1 channel 3 output/capture input.
PB.1
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH1
A
MFP1
EADC0 channel 1 analog input.
OPA0_N
A
MFP1
Operational amplifier 0 negative input pin.
EBI_ADR8
O
MFP2
EBI address bus bit 8.
SD0_CLK
O
MFP3
SD/SDIO0 clock output pin
2
6
2
7
8
9
May 08, 2020
Page 291 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
128 Pin Name
Pin
Type
MFP
Description
EMAC_RMII_RXERR
I
MFP4
EMAC RMII Receive Data Error input pin.
SPI1_I2SMCLK
I/O
MFP5
SPI1 I2S master clock output pin
SPI3_I2SMCLK
I/O
MFP6
SPI3 I2S master clock output pin
UART2_TXD
O
MFP7
UART2 data transmitter output pin.
USCI1_CLK
I/O
MFP8
USCI1 clock pin.
I2C1_SCL
I/O
MFP9
I2C1 clock pin.
I2S0_LRCK
O
MFP10
I2S0 left right channel clock output pin.
EPWM0_CH4
I/O
MFP11
EPWM0 channel 4 output/capture input.
EPWM1_CH4
I/O
MFP12
EPWM1 channel 4 output/capture input.
EPWM0_BRAKE0
I
MFP13
EPWM0 Brake 0 input pin.
PB.0
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH0
A
MFP1
EADC0 channel 0 analog input.
OPA0_P
A
MFP1
Operational amplifier 0 positive input pin.
EBI_ADR9
O
MFP2
EBI address bus bit 9.
SD0_CMD
I/O
MFP3
SD/SDIO0 command/response pin
UART2_RXD
I
MFP7
UART2 data receiver input pin.
SPI0_I2SMCLK
I/O
MFP8
SPI0 I2S master clock output pin
I2C1_SDA
I/O
MFP9
I2C1 data input/output pin.
EPWM0_CH5
I/O
MFP11
EPWM0 channel 5 output/capture input.
EPWM1_CH5
I/O
MFP12
EPWM1 channel 5 output/capture input.
EPWM0_BRAKE1
I
MFP13
EPWM0 Brake 1 input pin.
11
VSS
P
MFP0
Ground pin for digital circuit.
12
VDD
P
MFP0
Power supply for I/O ports and LDO source for internal PLL
and digital circuit.
13
PA.11
I/O
MFP0
General purpose digital I/O pin.
ACMP0_P0
A
MFP1
Analog comparator 0 positive input 0 pin.
EBI_nRD
O
MFP2
EBI read enable output pin.
SC2_PWR
O
MFP3
Smart Card 2 power pin.
SPI2_SS
I/O
MFP4
SPI2 slave select pin.
SD1_DAT3
I/O
MFP5
SD/SDIO1 data line bit 3.
USCI0_CLK
I/O
MFP6
USCI0 clock pin.
I C2_SCL
I/O
MFP7
I2C2 clock pin.
BPWM0_CH0
I/O
MFP9
BPWM0 channel 0 output/capture input.
EPWM0_SYNC_OUT
O
MFP10
EPWM0 counter synchronous trigger output pin.
10
M480 SERIES DATASHEET
2
May 08, 2020
Page 292 of 523
Rev 3.00
M480
128 Pin Name
Pin
14
15
MFP
Description
TM0_EXT
I/O
MFP13
Timer0 event counter input/toggle output pin.
DAC1_ST
I
MFP14
DAC1 external trigger input.
PA.10
I/O
MFP0
General purpose digital I/O pin.
ACMP1_P0
A
MFP1
Analog comparator 1 positive input 0 pin.
OPA1_O
A
MFP1
Operational amplifier 1 output pin.
EBI_nWR
O
MFP2
EBI write enable output pin.
SC2_RST
O
MFP3
Smart Card 2 reset pin.
SPI2_CLK
I/O
MFP4
SPI2 serial clock pin.
SD1_DAT2
I/O
MFP5
SD/SDIO1 data line bit 2.
USCI0_DAT0
I/O
MFP6
USCI0 data 0 pin.
I2C2_SDA
I/O
MFP7
I2C2 data input/output pin.
BPWM0_CH1
I/O
MFP9
BPWM0 channel 1 output/capture input.
QEI1_INDEX
I
MFP10
Quadrature encoder 1 index input
ECAP0_IC0
I
MFP11
Enhanced capture unit 0 input 0 pin.
TM1_EXT
I/O
MFP13
Timer1 event counter input/toggle output pin.
DAC0_ST
I
MFP14
DAC0 external trigger input.
SWDH_CLK
O
MFP15
Serial Wire Debug Host Clock output
PA.9
I/O
MFP0
General purpose digital I/O pin.
OPA1_N
A
MFP1
Operational amplifier 1 negative input pin.
EBI_MCLK
O
MFP2
EBI external clock output pin.
SC2_DAT
I/O
MFP3
Smart Card 2 data pin.
SPI2_MISO
I/O
MFP4
SPI2 MISO (Master In, Slave Out) pin.
SD1_DAT1
I/O
MFP5
SD/SDIO1 data line bit 1.
USCI0_DAT1
I/O
MFP6
USCI0 data 1 pin.
UART1_TXD
O
MFP7
UART1 data transmitter output pin.
BPWM0_CH2
I/O
MFP9
BPWM0 channel 2 output/capture input.
QEI1_A
I
MFP10
Quadrature encoder 1 phase A input
ECAP0_IC1
I
MFP11
Enhanced capture unit 0 input 1 pin.
TM2_EXT
I/O
MFP13
Timer2 event counter input/toggle output pin.
SWDH_DAT
I/O
MFP15
Serial Wire Debug Host Data input/output pin
PA.8
I/O
MFP0
General purpose digital I/O pin.
OPA1_P
A
MFP1
Operational amplifier 1 positive input pin.
EBI_ALE
O
MFP2
EBI address latch enable output pin.
SC2_CLK
O
MFP3
Smart Card 2 clock pin.
May 08, 2020
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M480 SERIES DATASHEET
16
Type
Rev 3.00
M480
128 Pin Name
Pin
17
M480 SERIES DATASHEET
18
19
Type
MFP
Description
SPI2_MOSI
I/O
MFP4
SPI2 MOSI (Master Out, Slave In) pin.
SD1_DAT0
I/O
MFP5
SD/SDIO1 data line bit 0.
USCI0_CTL1
I/O
MFP6
USCI0 control 1 pin.
UART1_RXD
I
MFP7
UART1 data receiver input pin.
BPWM0_CH3
I/O
MFP9
BPWM0 channel 3 output/capture input.
QEI1_B
I
MFP10
Quadrature encoder 1 phase B input
ECAP0_IC2
I
MFP11
Enhanced capture unit 0 input 2 pin.
TM3_EXT
I/O
MFP13
Timer3 event counter input/toggle output pin.
INT4
I
MFP15
External interrupt 4 input pin.
PC.13
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR10
O
MFP2
EBI address bus bit 10.
SC2_nCD
I
MFP3
Smart Card 2 card detect pin.
SPI2_I2SMCLK
I/O
MFP4
SPI2 I2S master clock output pin
CAN1_TXD
O
MFP5
CAN1 bus transmitter output.
USCI0_CTL0
I/O
MFP6
USCI0 control 0 pin.
UART2_TXD
O
MFP7
UART2 data transmitter output pin.
BPWM0_CH4
I/O
MFP9
BPWM0 channel 4 output/capture input.
CLKO
O
MFP13
Clock Out
EADC0_ST
I
MFP14
EADC0 external trigger input.
PD.12
I/O
MFP0
General purpose digital I/O pin.
OPA2_O
A
MFP1
Operational amplifier 2 output pin.
EBI_nCS0
O
MFP2
EBI chip select 0 output pin.
CAN1_RXD
I
MFP5
CAN1 bus receiver input.
UART2_RXD
I
MFP7
UART2 data receiver input pin.
BPWM0_CH5
I/O
MFP9
BPWM0 channel 5 output/capture input.
QEI0_INDEX
I
MFP10
Quadrature encoder 0 index input
CLKO
O
MFP13
Clock Out
EADC0_ST
I
MFP14
EADC0 external trigger input.
INT5
I
MFP15
External interrupt 5 input pin.
PD.11
I/O
MFP0
General purpose digital I/O pin.
OPA2_N
A
MFP1
Operational amplifier 2 negative input pin.
EBI_nCS1
O
MFP2
EBI chip select 1 output pin.
UART1_TXD
O
MFP3
UART1 data transmitter output pin.
CAN0_TXD
O
MFP4
CAN0 bus transmitter output.
May 08, 2020
Page 294 of 523
Rev 3.00
M480
128 Pin Name
Pin
20
21
22
MFP
Description
QEI0_A
I
MFP10
Quadrature encoder 0 phase A input
INT6
I
MFP15
External interrupt 6 input pin.
PD.10
I/O
MFP0
General purpose digital I/O pin.
OPA2_P
A
MFP1
Operational amplifier 2 positive input pin.
EBI_nCS2
O
MFP2
EBI chip select 2 output pin.
UART1_RXD
I
MFP3
UART1 data receiver input pin.
CAN0_RXD
I
MFP4
CAN0 bus receiver input.
QEI0_B
I
MFP10
Quadrature encoder 0 phase B input
INT7
I
MFP15
External interrupt 7 input pin.
PG.2
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR11
O
MFP2
EBI address bus bit 11.
SPI2_SS
I/O
MFP3
SPI2 slave select pin.
I2C0_SMBAL
O
MFP4
I2C0 SMBus SMBALTER pin
I2C1_SCL
I/O
MFP5
I2C1 clock pin.
TM0
I/O
MFP13
Timer0 event counter input/toggle output pin.
PG.3
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR12
O
MFP2
EBI address bus bit 12.
SPI2_CLK
I/O
MFP3
SPI2 serial clock pin.
I C0_SMBSUS
O
MFP4
I2C0 SMBus SMBSUS pin (PMBus CONTROL pin)
I2C1_SDA
I/O
MFP5
I2C1 data input/output pin.
TM1
I/O
MFP13
Timer1 event counter input/toggle output pin.
PG.4
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR13
O
MFP2
EBI address bus bit 13.
SPI2_MISO
I/O
MFP3
SPI2 MISO (Master In, Slave Out) pin.
TM2
I/O
MFP13
Timer2 event counter input/toggle output pin.
PF.11
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR14
O
MFP2
EBI address bus bit 14.
SPI2_MOSI
I/O
MFP3
SPI2 MOSI (Master Out, Slave In) pin.
TAMPER5
I/O
MFP10
TAMPER detector loop pin 5.
TM3
I/O
MFP13
Timer3 event counter input/toggle output pin.
PF.10
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR15
O
MFP2
EBI address bus bit 15.
SC0_nCD
I
MFP3
Smart Card 0 card detect pin.
O
MFP4
I2S0 bit clock output pin.
2
23
24
25
2
I S0_BCLK
May 08, 2020
Page 295 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
128 Pin Name
Pin
Type
MFP
Description
SPI0_I2SMCLK
I/O
MFP5
SPI0 I2S master clock output pin
TAMPER4
I/O
MFP10
TAMPER detector loop pin 4.
PF.9
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR16
O
MFP2
EBI address bus bit 16.
SC0_PWR
O
MFP3
Smart Card 0 power pin.
I2S0_MCLK
O
MFP4
I2S0 master clock output pin.
SPI0_SS
I/O
MFP5
SPI0 slave select pin.
TAMPER3
I/O
MFP10
TAMPER detector loop pin 3.
PF.8
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR17
O
MFP2
EBI address bus bit 17.
SC0_RST
O
MFP3
Smart Card 0 reset pin.
I S0_DI
I
MFP4
I2S0 data input pin.
SPI0_CLK
I/O
MFP5
SPI0 serial clock pin.
TAMPER2
I/O
MFP10
TAMPER detector loop pin 2.
PF.7
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR18
O
MFP2
EBI address bus bit 18.
SC0_DAT
I/O
MFP3
Smart Card 0 data pin.
I2S0_DO
O
MFP4
I2S0 data output pin.
SPI0_MISO
I/O
MFP5
SPI0 MISO (Master In, Slave Out) pin.
UART4_TXD
O
MFP6
UART4 data transmitter output pin.
TAMPER1
I/O
MFP10
TAMPER detector loop pin 1.
PF.6
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR19
O
MFP2
EBI address bus bit 19.
SC0_CLK
O
MFP3
Smart Card 0 clock pin.
I S0_LRCK
O
MFP4
I2S0 left right channel clock output pin.
SPI0_MOSI
I/O
MFP5
SPI0 MOSI (Master Out, Slave In) pin.
UART4_RXD
I
MFP6
UART4 data receiver input pin.
EBI_nCS0
O
MFP7
EBI chip select 0 output pin.
TAMPER0
I/O
MFP10
TAMPER detector loop pin 0.
30
VDD
P
MFP0
Power supply for I/O ports and LDO source for internal PLL
and digital circuit.
31
PF.5
I/O
MFP0
General purpose digital I/O pin.
UART2_RXD
I
MFP2
UART2 data receiver input pin.
UART2_nCTS
I
MFP4
UART2 clear to Send input pin.
26
27
2
28
M480 SERIES DATASHEET
29
2
May 08, 2020
Page 296 of 523
Rev 3.00
M480
128 Pin Name
Pin
32
33
34
35
36
MFP
Description
BPWM0_CH4
I/O
MFP8
BPWM0 channel 4 output/capture input.
EPWM0_SYNC_OUT
O
MFP9
EPWM0 counter synchronous trigger output pin.
X32_IN
I
MFP10
External 32.768 kHz crystal input pin.
EADC0_ST
I
MFP11
EADC0 external trigger input.
PF.4
I/O
MFP0
General purpose digital I/O pin.
UART2_TXD
O
MFP2
UART2 data transmitter output pin.
UART2_nRTS
O
MFP4
UART2 request to Send output pin.
BPWM0_CH5
I/O
MFP8
BPWM0 channel 5 output/capture input.
X32_OUT
O
MFP10
External 32.768 kHz crystal output pin.
PH.4
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR3
O
MFP2
EBI address bus bit 3.
SPI1_MISO
I/O
MFP3
SPI1 MISO (Master In, Slave Out) pin.
PH.5
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR2
O
MFP2
EBI address bus bit 2.
SPI1_MOSI
I/O
MFP3
SPI1 MOSI (Master Out, Slave In) pin.
PH.6
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR1
O
MFP2
EBI address bus bit 1.
SPI1_CLK
I/O
MFP3
SPI1 serial clock pin.
PH.7
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR0
O
MFP2
EBI address bus bit 0.
SPI1_SS
I/O
MFP3
SPI1 slave select pin.
PF.3
I/O
MFP0
General purpose digital I/O pin.
EBI_nCS0
O
MFP2
EBI chip select 0 output pin.
UART0_TXD
O
MFP3
UART0 data transmitter output pin.
I C0_SCL
I/O
MFP4
I2C0 clock pin.
XT1_IN
I
MFP10
External 4~24 MHz (high speed) crystal input pin.
BPWM1_CH0
I/O
MFP11
BPWM1 channel 0 output/capture input.
PF.2
I/O
MFP0
General purpose digital I/O pin.
EBI_nCS1
O
MFP2
EBI chip select 1 output pin.
UART0_RXD
I
MFP3
UART0 data receiver input pin.
I2C0_SDA
I/O
MFP4
I2C0 data input/output pin.
QSPI0_CLK
I/O
MFP5
QSPI0 serial clock pin.
XT1_OUT
O
MFP10
External 4~24 MHz (high speed) crystal output pin.
BPWM1_CH1
I/O
MFP11
BPWM1 channel 1 output/capture input.
2
38
May 08, 2020
Page 297 of 523
M480 SERIES DATASHEET
37
Type
Rev 3.00
M480
128 Pin Name
Pin
Type
MFP
Description
39
VSS
P
MFP0
Ground pin for digital circuit.
40
VDD
P
MFP0
Power supply for I/O ports and LDO source for internal PLL
and digital circuit.
41
PE.8
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR10
O
MFP2
EBI address bus bit 10.
EMAC_RMII_MDC
O
MFP3
EMAC RMII PHY Management Clock output pin.
I S0_BCLK
O
MFP4
I2S0 bit clock output pin.
SPI2_CLK
I/O
MFP5
SPI2 serial clock pin.
USCI1_CTL1
I/O
MFP6
USCI1 control 1 pin.
UART2_TXD
O
MFP7
UART2 data transmitter output pin.
EPWM0_CH0
I/O
MFP10
EPWM0 channel 0 output/capture input.
EPWM0_BRAKE0
I
MFP11
EPWM0 Brake 0 input pin.
ECAP0_IC0
I
MFP12
Enhanced capture unit 0 input 0 pin.
TRACE_CLK
O
MFP14
ETM Trace Clock output pin
PE.9
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR11
O
MFP2
EBI address bus bit 11.
EMAC_RMII_MDIO
I/O
MFP3
EMAC RMII PHY Management Data pin.
I S0_MCLK
O
MFP4
I2S0 master clock output pin.
SPI2_MISO
I/O
MFP5
SPI2 MISO (Master In, Slave Out) pin.
USCI1_CTL0
I/O
MFP6
USCI1 control 0 pin.
UART2_RXD
I
MFP7
UART2 data receiver input pin.
EPWM0_CH1
I/O
MFP10
EPWM0 channel 1 output/capture input.
EPWM0_BRAKE1
I
MFP11
EPWM0 Brake 1 input pin.
ECAP0_IC1
I
MFP12
Enhanced capture unit 0 input 1 pin.
TRACE_DATA0
O
MFP14
ETM Trace Data 0 output pin
PE.10
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR12
O
MFP2
EBI address bus bit 12.
EMAC_RMII_TXD0
O
MFP3
EMAC RMII Transmit Data bus bit 0.
I S0_DI
I
MFP4
I2S0 data input pin.
SPI2_MOSI
I/O
MFP5
SPI2 MOSI (Master Out, Slave In) pin.
USCI1_DAT0
I/O
MFP6
USCI1 data 0 pin.
UART3_TXD
O
MFP7
UART3 data transmitter output pin.
EPWM0_CH2
I/O
MFP10
EPWM0 channel 2 output/capture input.
EPWM1_BRAKE0
I
MFP11
EPWM1 Brake 0 input pin.
2
42
2
M480 SERIES DATASHEET
43
2
May 08, 2020
Page 298 of 523
Rev 3.00
M480
128 Pin Name
Pin
44
45
MFP
Description
ECAP0_IC2
I
MFP12
Enhanced capture unit 0 input 2 pin.
TRACE_DATA1
O
MFP14
ETM Trace Data 1 output pin
PE.11
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR13
O
MFP2
EBI address bus bit 13.
EMAC_RMII_TXD1
O
MFP3
EMAC RMII Transmit Data bus bit 1.
I2S0_DO
O
MFP4
I2S0 data output pin.
SPI2_SS
I/O
MFP5
SPI2 slave select pin.
USCI1_DAT1
I/O
MFP6
USCI1 data 1 pin.
UART3_RXD
I
MFP7
UART3 data receiver input pin.
UART1_nCTS
I
MFP8
UART1 clear to Send input pin.
EPWM0_CH3
I/O
MFP10
EPWM0 channel 3 output/capture input.
EPWM1_BRAKE1
I
MFP11
EPWM1 Brake 1 input pin.
ECAP1_IC2
I
MFP13
Enhanced capture unit 1 input 2 pin.
TRACE_DATA2
O
MFP14
ETM Trace Data 2 output pin
PE.12
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR14
O
MFP2
EBI address bus bit 14.
EMAC_RMII_TXEN
O
MFP3
EMAC RMII Transmit Enable output pin.
I2S0_LRCK
O
MFP4
I2S0 left right channel clock output pin.
SPI2_I2SMCLK
I/O
MFP5
SPI2 I2S master clock output pin
USCI1_CLK
I/O
MFP6
USCI1 clock pin.
UART1_nRTS
O
MFP8
UART1 request to Send output pin.
EPWM0_CH4
I/O
MFP10
EPWM0 channel 4 output/capture input.
ECAP1_IC1
I
MFP13
Enhanced capture unit 1 input 1 pin.
TRACE_DATA3
O
MFP14
ETM Trace Data 3 output pin
PE.13
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR15
O
MFP2
EBI address bus bit 15.
EMAC_PPS
O
MFP3
EMAC Pulse Per Second output pin.
I C0_SCL
I/O
MFP4
I2C0 clock pin.
UART4_nRTS
O
MFP5
UART4 request to Send output pin.
UART1_TXD
O
MFP8
UART1 data transmitter output pin.
EPWM0_CH5
I/O
MFP10
EPWM0 channel 5 output/capture input.
EPWM1_CH0
I/O
MFP11
EPWM1 channel 0 output/capture input.
BPWM1_CH5
I/O
MFP12
BPWM1 channel 5 output/capture input.
ECAP1_IC0
I
MFP13
Enhanced capture unit 1 input 0 pin.
2
May 08, 2020
Page 299 of 523
M480 SERIES DATASHEET
46
Type
Rev 3.00
M480
128 Pin Name
Pin
Type
MFP
Description
47
PC.8
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR16
O
MFP2
EBI address bus bit 16.
EMAC_RMII_REFCLK
I
MFP3
EMAC RMII reference clock input pin.
I2C0_SDA
I/O
MFP4
I2C0 data input/output pin.
UART4_nCTS
I
MFP5
UART4 clear to Send input pin.
UART1_RXD
I
MFP8
UART1 data receiver input pin.
EPWM1_CH1
I/O
MFP11
EPWM1 channel 1 output/capture input.
BPWM1_CH4
I/O
MFP12
BPWM1 channel 4 output/capture input.
PC.7
I/O
MFP0
General purpose digital I/O pin.
EBI_AD9
I/O
MFP2
EBI address/data bus bit 9.
EMAC_RMII_RXD0
I
MFP3
EMAC RMII Receive Data bus bit 0.
SPI1_MISO
I/O
MFP4
SPI1 MISO (Master In, Slave Out) pin.
UART4_TXD
O
MFP5
UART4 data transmitter output pin.
SC2_PWR
O
MFP6
Smart Card 2 power pin.
UART0_nCTS
I
MFP7
UART0 clear to Send input pin.
I2C1_SMBAL
O
MFP8
I2C1 SMBus SMBALTER pin
EPWM1_CH2
I/O
MFP11
EPWM1 channel 2 output/capture input.
BPWM1_CH0
I/O
MFP12
BPWM1 channel 0 output/capture input.
TM0
I/O
MFP14
Timer0 event counter input/toggle output pin.
INT3
I
MFP15
External interrupt 3 input pin.
PC.6
I/O
MFP0
General purpose digital I/O pin.
EBI_AD8
I/O
MFP2
EBI address/data bus bit 8.
EMAC_RMII_RXD1
I
MFP3
EMAC RMII Receive Data bus bit 1.
SPI1_MOSI
I/O
MFP4
SPI1 MOSI (Master Out, Slave In) pin.
UART4_RXD
I
MFP5
UART4 data receiver input pin.
SC2_RST
O
MFP6
Smart Card 2 reset pin.
UART0_nRTS
O
MFP7
UART0 request to Send output pin.
I C1_SMBSUS
O
MFP8
I2C1 SMBus SMBSUS pin (PMBus CONTROL pin)
EPWM1_CH3
I/O
MFP11
EPWM1 channel 3 output/capture input.
BPWM1_CH1
I/O
MFP12
BPWM1 channel 1 output/capture input.
TM1
I/O
MFP14
Timer1 event counter input/toggle output pin.
INT2
I
MFP15
External interrupt 2 input pin.
PA.7
I/O
MFP0
General purpose digital I/O pin.
EBI_AD7
I/O
MFP2
EBI address/data bus bit 7.
48
M480 SERIES DATASHEET
49
2
50
May 08, 2020
Page 300 of 523
Rev 3.00
M480
128 Pin Name
Pin
MFP
Description
EMAC_RMII_CRSDV
I
MFP3
EMAC RMII Carrier Sense/Receive Data input pin.
SPI1_CLK
I/O
MFP4
SPI1 serial clock pin.
SC2_DAT
I/O
MFP6
Smart Card 2 data pin.
UART0_TXD
O
MFP7
UART0 data transmitter output pin.
I C1_SCL
I/O
MFP8
I2C1 clock pin.
EPWM1_CH4
I/O
MFP11
EPWM1 channel 4 output/capture input.
BPWM1_CH2
I/O
MFP12
BPWM1 channel 2 output/capture input.
ACMP0_WLAT
I
MFP13
Analog comparator 0 window latch input pin
TM2
I/O
MFP14
Timer2 event counter input/toggle output pin.
INT1
I
MFP15
External interrupt 1 input pin.
PA.6
I/O
MFP0
General purpose digital I/O pin.
EBI_AD6
I/O
MFP2
EBI address/data bus bit 6.
EMAC_RMII_RXERR
I
MFP3
EMAC RMII Receive Data Error input pin.
SPI1_SS
I/O
MFP4
SPI1 slave select pin.
SD1_nCD
I
MFP5
SD/SDIO1 card detect input pin
SC2_CLK
O
MFP6
Smart Card 2 clock pin.
UART0_RXD
I
MFP7
UART0 data receiver input pin.
I2C1_SDA
I/O
MFP8
I2C1 data input/output pin.
EPWM1_CH5
I/O
MFP11
EPWM1 channel 5 output/capture input.
BPWM1_CH3
I/O
MFP12
BPWM1 channel 3 output/capture input.
ACMP1_WLAT
I
MFP13
Analog comparator 1 window latch input pin
TM3
I/O
MFP14
Timer3 event counter input/toggle output pin.
INT0
I
MFP15
External interrupt 0 input pin.
52
VSS
P
MFP0
Ground pin for digital circuit.
53
VDD
P
MFP0
Power supply for I/O ports and LDO source for internal PLL
and digital circuit.
54
LDO_CAP
A
MFP0
LDO output pin.
2
51
Note: This pin needs to be connected with an external
capacitor.
55
PA.5
I/O
MFP0
General purpose digital I/O pin.
SPIM_D2
I/O
MFP2
SPIM data 2 pin for Quad Mode I/O.
QSPI0_MISO1
I/O
MFP3
QSPI0 MISO1 (Master In, Slave Out) pin.
SPI1_I2SMCLK
I/O
MFP4
SPI1 I2S master clock output pin
SD1_CMD
I/O
MFP5
SD/SDIO1 command/response pin
SC2_nCD
I
MFP6
Smart Card 2 card detect pin.
May 08, 2020
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Rev 3.00
M480 SERIES DATASHEET
Type
M480
128 Pin Name
Pin
Type
MFP
Description
UART0_nCTS
I
MFP7
UART0 clear to Send input pin.
UART5_TXD
O
MFP8
UART5 data transmitter output pin.
I C0_SCL
I/O
MFP9
I2C0 clock pin.
CAN0_TXD
O
MFP10
CAN0 bus transmitter output.
BPWM0_CH5
I/O
MFP12
BPWM0 channel 5 output/capture input.
EPWM0_CH0
I/O
MFP13
EPWM0 channel 0 output/capture input.
QEI0_INDEX
I
MFP14
Quadrature encoder 0 index input
PA.4
I/O
MFP0
General purpose digital I/O pin.
SPIM_D3
I/O
MFP2
SPIM data 3 pin for Quad Mode I/O.
QSPI0_MOSI1
I/O
MFP3
QSPI0 MOSI1 (Master Out, Slave In) pin.
SPI0_I2SMCLK
I/O
MFP4
SPI0 I2S master clock output pin
SD1_CLK
O
MFP5
SD/SDIO1 clock output pin
SC0_nCD
I
MFP6
Smart Card 0 card detect pin.
UART0_nRTS
O
MFP7
UART0 request to Send output pin.
UART5_RXD
I
MFP8
UART5 data receiver input pin.
I2C0_SDA
I/O
MFP9
I2C0 data input/output pin.
CAN0_RXD
I
MFP10
CAN0 bus receiver input.
BPWM0_CH4
I/O
MFP12
BPWM0 channel 4 output/capture input.
EPWM0_CH1
I/O
MFP13
EPWM0 channel 1 output/capture input.
QEI0_A
I
MFP14
Quadrature encoder 0 phase A input
PA.3
I/O
MFP0
General purpose digital I/O pin.
SPIM_SS
I/O
MFP2
SPIM slave select pin.
QSPI0_SS
I/O
MFP3
QSPI0 slave select pin.
SPI0_SS
I/O
MFP4
SPI0 slave select pin.
SD1_DAT3
I/O
MFP5
SD/SDIO1 data line bit 3.
SC0_PWR
O
MFP6
Smart Card 0 power pin.
UART4_TXD
O
MFP7
UART4 data transmitter output pin.
UART1_TXD
O
MFP8
UART1 data transmitter output pin.
I2C1_SCL
I/O
MFP9
I2C1 clock pin.
BPWM0_CH3
I/O
MFP12
BPWM0 channel 3 output/capture input.
EPWM0_CH2
I/O
MFP13
EPWM0 channel 2 output/capture input.
QEI0_B
I
MFP14
Quadrature encoder 0 phase B input
PA.2
I/O
MFP0
General purpose digital I/O pin.
SPIM_CLK
I/O
MFP2
SPIM serial clock pin.
2
56
M480 SERIES DATASHEET
57
58
May 08, 2020
Page 302 of 523
Rev 3.00
M480
128 Pin Name
Pin
59
MFP
Description
QSPI0_CLK
I/O
MFP3
QSPI0 serial clock pin.
SPI0_CLK
I/O
MFP4
SPI0 serial clock pin.
SD1_DAT2
I/O
MFP5
SD/SDIO1 data line bit 2.
SC0_RST
O
MFP6
Smart Card 0 reset pin.
UART4_RXD
I
MFP7
UART4 data receiver input pin.
UART1_RXD
I
MFP8
UART1 data receiver input pin.
I2C1_SDA
I/O
MFP9
I2C1 data input/output pin.
BPWM0_CH2
I/O
MFP12
BPWM0 channel 2 output/capture input.
EPWM0_CH3
I/O
MFP13
EPWM0 channel 3 output/capture input.
PA.1
I/O
MFP0
General purpose digital I/O pin.
SPIM_MISO
I/O
MFP2
SPIM MISO (Master In, Slave Out) pin.
QSPI0_MISO0
I/O
MFP3
QSPI0 MISO0 (Master In, Slave Out) pin.
SPI0_MISO
I/O
MFP4
SPI0 MISO (Master In, Slave Out) pin.
SD1_DAT1
I/O
MFP5
SD/SDIO1 data line bit 1.
SC0_DAT
I/O
MFP6
Smart Card 0 data pin.
UART0_TXD
O
MFP7
UART0 data transmitter output pin.
UART1_nCTS
I
MFP8
UART1 clear to Send input pin.
I2C2_SCL
I/O
MFP9
I2C2 clock pin.
BPWM0_CH1
I/O
MFP12
BPWM0 channel 1 output/capture input.
EPWM0_CH4
I/O
MFP13
EPWM0 channel 4 output/capture input.
DAC1_ST
I
MFP15
DAC1 external trigger input.
PA.0
I/O
MFP0
General purpose digital I/O pin.
SPIM_MOSI
I/O
MFP2
SPIM MOSI (Master Out, Slave In) pin.
QSPI0_MOSI0
I/O
MFP3
QSPI0 MOSI0 (Master Out, Slave In) pin.
SPI0_MOSI
I/O
MFP4
SPI0 MOSI (Master Out, Slave In) pin.
SD1_DAT0
I/O
MFP5
SD/SDIO1 data line bit 0.
SC0_CLK
O
MFP6
Smart Card 0 clock pin.
UART0_RXD
I
MFP7
UART0 data receiver input pin.
UART1_nRTS
O
MFP8
UART1 request to Send output pin.
I C2_SDA
I/O
MFP9
I2C2 data input/output pin.
BPWM0_CH0
I/O
MFP12
BPWM0 channel 0 output/capture input.
EPWM0_CH5
I/O
MFP13
EPWM0 channel 5 output/capture input.
DAC0_ST
I
MFP15
DAC0 external trigger input.
VDDIO
P
MFP0
Power supply for PA.0~PA.5.
2
61
May 08, 2020
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M480 SERIES DATASHEET
60
Type
Rev 3.00
M480
128 Pin Name
Pin
Type
MFP
Description
62
PE.14
I/O
MFP0
General purpose digital I/O pin.
EBI_AD8
I/O
MFP2
EBI address/data bus bit 8.
UART2_TXD
O
MFP3
UART2 data transmitter output pin.
CAN0_TXD
O
MFP4
CAN0 bus transmitter output.
SD1_nCD
I
MFP5
SD/SDIO1 card detect input pin
PE.15
I/O
MFP0
General purpose digital I/O pin.
EBI_AD9
I/O
MFP2
EBI address/data bus bit 9.
UART2_RXD
I
MFP3
UART2 data receiver input pin.
CAN0_RXD
I
MFP4
CAN0 bus receiver input.
nRESET
I
MFP0
External reset input: active LOW, with an internal pull-up.
Set this pin low reset to initial state.
63
64
Note: It is recommended to use 10 kΩ pull-up resistor and
10 uF capacitor on nRESET pin.
65
PF.0
I/O
MFP0
General purpose digital I/O pin.
UART1_TXD
O
MFP2
UART1 data transmitter output pin.
I2C1_SCL
I/O
MFP3
I2C1 clock pin.
BPWM1_CH0
I/O
MFP12
BPWM1 channel 0 output/capture input.
ICE_DAT
O
MFP14
Serial wired debugger data pin.
Note: It is recommended to use 100 kΩ pull-up resistor on
ICE_DAT pin.
66
M480 SERIES DATASHEET
PF.1
I/O
MFP0
General purpose digital I/O pin.
UART1_RXD
I
MFP2
UART1 data receiver input pin.
I C1_SDA
I/O
MFP3
I2C1 data input/output pin.
BPWM1_CH1
I/O
MFP12
BPWM1 channel 1 output/capture input.
ICE_CLK
I
MFP14
Serial wired debugger clock pin.
2
Note: It is recommended to use 100 kΩ pull-up resistor on
ICE_CLK pin.
67
PD.9
I/O
MFP0
General purpose digital I/O pin.
EBI_AD7
I/O
MFP2
EBI address/data bus bit 7.
I C2_SCL
I/O
MFP3
I2C2 clock pin.
UART2_nCTS
I
MFP4
UART2 clear to Send input pin.
PD.8
I/O
MFP0
General purpose digital I/O pin.
EBI_AD6
I/O
MFP2
EBI address/data bus bit 6.
I2C2_SDA
I/O
MFP3
I2C2 data input/output pin.
UART2_nRTS
O
MFP4
UART2 request to Send output pin.
PC.5
I/O
MFP0
General purpose digital I/O pin.
EBI_AD5
I/O
MFP2
EBI address/data bus bit 5.
2
68
69
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Rev 3.00
M480
128 Pin Name
Pin
70
MFP
Description
SPIM_D2
I/O
MFP3
SPIM data 2 pin for Quad Mode I/O.
QSPI0_MISO1
I/O
MFP4
QSPI0 MISO1 (Master In, Slave Out) pin.
UART2_TXD
O
MFP8
UART2 data transmitter output pin.
I2C1_SCL
I/O
MFP9
I2C1 clock pin.
CAN0_TXD
O
MFP10
CAN0 bus transmitter output.
UART4_TXD
O
MFP11
UART4 data transmitter output pin.
EPWM1_CH0
I/O
MFP12
EPWM1 channel 0 output/capture input.
PC.4
I/O
MFP0
General purpose digital I/O pin.
EBI_AD4
I/O
MFP2
EBI address/data bus bit 4.
SPIM_D3
I/O
MFP3
SPIM data 3 pin for Quad Mode I/O.
QSPI0_MOSI1
I/O
MFP4
QSPI0 MOSI1 (Master Out, Slave In) pin.
SC1_nCD
I
MFP5
Smart Card 1 card detect pin.
I2S0_BCLK
O
MFP6
I2S0 bit clock output pin.
SPI1_I2SMCLK
I/O
MFP7
SPI1 I2S master clock output pin
UART2_RXD
I
MFP8
UART2 data receiver input pin.
I2C1_SDA
I/O
MFP9
I2C1 data input/output pin.
CAN0_RXD
I
MFP10
CAN0 bus receiver input.
UART4_RXD
I
MFP11
UART4 data receiver input pin.
EPWM1_CH1
I/O
MFP12
EPWM1 channel 1 output/capture input.
PC.3
I/O
MFP0
General purpose digital I/O pin.
EBI_AD3
I/O
MFP2
EBI address/data bus bit 3.
SPIM_SS
I/O
MFP3
SPIM slave select pin.
QSPI0_SS
I/O
MFP4
QSPI0 slave select pin.
SC1_PWR
O
MFP5
Smart Card 1 power pin.
I S0_MCLK
O
MFP6
I2S0 master clock output pin.
SPI1_MISO
I/O
MFP7
SPI1 MISO (Master In, Slave Out) pin.
UART2_nRTS
O
MFP8
UART2 request to Send output pin.
I C0_SMBAL
O
MFP9
I2C0 SMBus SMBALTER pin
CAN1_TXD
O
MFP10
CAN1 bus transmitter output.
UART3_TXD
O
MFP11
UART3 data transmitter output pin.
EPWM1_CH2
I/O
MFP12
EPWM1 channel 2 output/capture input.
PC.2
I/O
MFP0
General purpose digital I/O pin.
EBI_AD2
I/O
MFP2
EBI address/data bus bit 2.
SPIM_CLK
I/O
MFP3
SPIM serial clock pin.
2
2
72
May 08, 2020
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M480 SERIES DATASHEET
71
Type
Rev 3.00
M480
128 Pin Name
Pin
Type
MFP
Description
QSPI0_CLK
I/O
MFP4
QSPI0 serial clock pin.
SC1_RST
O
MFP5
Smart Card 1 reset pin.
I S0_DI
I
MFP6
I2S0 data input pin.
SPI1_MOSI
I/O
MFP7
SPI1 MOSI (Master Out, Slave In) pin.
UART2_nCTS
I
MFP8
UART2 clear to Send input pin.
I2C0_SMBSUS
O
MFP9
I2C0 SMBus SMBSUS pin (PMBus CONTROL pin)
CAN1_RXD
I
MFP10
CAN1 bus receiver input.
UART3_RXD
I
MFP11
UART3 data receiver input pin.
EPWM1_CH3
I/O
MFP12
EPWM1 channel 3 output/capture input.
PC.1
I/O
MFP0
General purpose digital I/O pin.
EBI_AD1
I/O
MFP2
EBI address/data bus bit 1.
SPIM_MISO
I/O
MFP3
SPIM MISO (Master In, Slave Out) pin.
QSPI0_MISO0
I/O
MFP4
QSPI0 MISO0 (Master In, Slave Out) pin.
SC1_DAT
I/O
MFP5
Smart Card 1 data pin.
I2S0_DO
O
MFP6
I2S0 data output pin.
SPI1_CLK
I/O
MFP7
SPI1 serial clock pin.
UART2_TXD
O
MFP8
UART2 data transmitter output pin.
I2C0_SCL
I/O
MFP9
I2C0 clock pin.
EPWM1_CH4
I/O
MFP12
EPWM1 channel 4 output/capture input.
ACMP0_O
O
MFP14
Analog comparator 0 output pin.
PC.0
I/O
MFP0
General purpose digital I/O pin.
EBI_AD0
I/O
MFP2
EBI address/data bus bit 0.
SPIM_MOSI
I/O
MFP3
SPIM MOSI (Master Out, Slave In) pin.
QSPI0_MOSI0
I/O
MFP4
QSPI0 MOSI0 (Master Out, Slave In) pin.
SC1_CLK
O
MFP5
Smart Card 1 clock pin.
I2S0_LRCK
O
MFP6
I2S0 left right channel clock output pin.
SPI1_SS
I/O
MFP7
SPI1 slave select pin.
UART2_RXD
I
MFP8
UART2 data receiver input pin.
I2C0_SDA
I/O
MFP9
I2C0 data input/output pin.
EPWM1_CH5
I/O
MFP12
EPWM1 channel 5 output/capture input.
ACMP1_O
O
MFP14
Analog comparator 1 output pin.
75
VSS
P
MFP0
Ground pin for digital circuit.
76
VDD
P
MFP0
Power supply for I/O ports and LDO source for internal PLL
and digital circuit.
2
73
M480 SERIES DATASHEET
74
May 08, 2020
Page 306 of 523
Rev 3.00
M480
Type
MFP
Description
77
PG.9
I/O
MFP0
General purpose digital I/O pin.
EBI_AD0
I/O
MFP2
EBI address/data bus bit 0.
SD1_DAT3
I/O
MFP3
SD/SDIO1 data line bit 3.
SPIM_D2
I/O
MFP4
SPIM data 2 pin for Quad Mode I/O.
BPWM0_CH5
I/O
MFP12
BPWM0 channel 5 output/capture input.
PG.10
I/O
MFP0
General purpose digital I/O pin.
EBI_AD1
I/O
MFP2
EBI address/data bus bit 1.
SD1_DAT2
I/O
MFP3
SD/SDIO1 data line bit 2.
SPIM_D3
I/O
MFP4
SPIM data 3 pin for Quad Mode I/O.
BPWM0_CH4
I/O
MFP12
BPWM0 channel 4 output/capture input.
79
NC
-
-
No connection.
80
PG.12
I/O
MFP0
General purpose digital I/O pin.
EBI_AD3
I/O
MFP2
EBI address/data bus bit 3.
SD1_DAT0
I/O
MFP3
SD/SDIO1 data line bit 0.
SPIM_CLK
I/O
MFP4
SPIM serial clock pin.
BPWM0_CH2
I/O
MFP12
BPWM0 channel 2 output/capture input.
81
NC
-
-
No connection.
82
PG.14
I/O
MFP0
General purpose digital I/O pin.
EBI_AD5
I/O
MFP2
EBI address/data bus bit 5.
SD1_CLK
O
MFP3
SD/SDIO1 clock output pin
SPIM_MOSI
I/O
MFP4
SPIM MOSI (Master Out, Slave In) pin.
BPWM0_CH0
I/O
MFP12
BPWM0 channel 0 output/capture input.
PG.15
I/O
MFP0
General purpose digital I/O pin.
SD1_nCD
I
MFP3
SD/SDIO1 card detect input pin
CLKO
O
MFP14
Clock Out
EADC0_ST
I
MFP15
EADC0 external trigger input.
PD.13
I/O
MFP0
General purpose digital I/O pin.
EBI_AD10
I/O
MFP2
EBI address/data bus bit 10.
SD0_nCD
I
MFP3
SD/SDIO0 card detect input pin
SPI0_I2SMCLK
I/O
MFP4
SPI0 I2S master clock output pin
SPI1_I2SMCLK
I/O
MFP5
SPI1 I2S master clock output pin
SC2_nCD
I
MFP7
Smart Card 2 card detect pin.
PA.12
I/O
MFP0
General purpose digital I/O pin.
O
MFP2
I2S0 bit clock output pin.
78
83
84
85
2
I S0_BCLK
May 08, 2020
Page 307 of 523
M480 SERIES DATASHEET
128 Pin Name
Pin
Rev 3.00
M480
128 Pin Name
Pin
86
Type
MFP
Description
UART4_TXD
O
MFP3
UART4 data transmitter output pin.
I2C1_SCL
I/O
MFP4
I2C1 clock pin.
SPI2_SS
I/O
MFP5
SPI2 slave select pin.
CAN0_TXD
O
MFP6
CAN0 bus transmitter output.
SC2_PWR
O
MFP7
Smart Card 2 power pin.
BPWM1_CH2
I/O
MFP11
BPWM1 channel 2 output/capture input.
QEI1_INDEX
I
MFP12
Quadrature encoder 1 index input
USB_VBUS
P
MFP14
Power supply from USB host or HUB.
PA.13
I/O
MFP0
General purpose digital I/O pin.
I S0_MCLK
O
MFP2
I2S0 master clock output pin.
UART4_RXD
I
MFP3
UART4 data receiver input pin.
I C1_SDA
I/O
MFP4
I2C1 data input/output pin.
SPI2_CLK
I/O
MFP5
SPI2 serial clock pin.
CAN0_RXD
I
MFP6
CAN0 bus receiver input.
SC2_RST
O
MFP7
Smart Card 2 reset pin.
BPWM1_CH3
I/O
MFP11
BPWM1 channel 3 output/capture input.
QEI1_A
I
MFP12
Quadrature encoder 1 phase A input
USB_D-
A
MFP14
USB differential signal D-.
PA.14
I/O
MFP0
General purpose digital I/O pin.
I2S0_DI
I
MFP2
I2S0 data input pin.
UART0_TXD
O
MFP3
UART0 data transmitter output pin.
SPI2_MISO
I/O
MFP5
SPI2 MISO (Master In, Slave Out) pin.
I C2_SCL
I/O
MFP6
I2C2 clock pin.
SC2_DAT
I/O
MFP7
Smart Card 2 data pin.
BPWM1_CH4
I/O
MFP11
BPWM1 channel 4 output/capture input.
QEI1_B
I
MFP12
Quadrature encoder 1 phase B input
USB_D+
A
MFP14
USB differential signal D+.
PA.15
I/O
MFP0
General purpose digital I/O pin.
I2S0_DO
O
MFP2
I2S0 data output pin.
UART0_RXD
I
MFP3
UART0 data receiver input pin.
SPI2_MOSI
I/O
MFP5
SPI2 MOSI (Master Out, Slave In) pin.
I C2_SDA
I/O
MFP6
I2C2 data input/output pin.
SC2_CLK
O
MFP7
Smart Card 2 clock pin.
BPWM1_CH5
I/O
MFP11
BPWM1 channel 5 output/capture input.
2
2
87
M480 SERIES DATASHEET
2
88
2
May 08, 2020
Page 308 of 523
Rev 3.00
M480
128 Pin Name
Pin
Type
MFP
Description
EPWM0_SYNC_IN
I
MFP12
EPWM0 counter synchronous trigger input pin.
USB_OTG_ID
I
MFP14
USB_ identification.
89
HSUSB_VRES
A
MFP0
HSUSB module reference resister
90
HSUSB_VDD33
P
MFP0
Power supply for HSUSB VDD33
91
HSUSB_VBUS
P
MFP0
HSUSB Power supply from USB host or HUB.
92
HSUSB_D-
A
MFP0
HSUSB differential signal D-.
93
HSUSB_VSS
P
MFP0
Ground pin for HSUSB.
94
HSUSB_D+
A
MFP0
HSUSB differential signal D+.
95
HSUSB_VDD12_CAP
A
MFP0
HSUSB Internal power regulator output 1.2V decoupling pin.
Note: This pin needs to be connected with a 1uF capacitor.
HSUSB_ID
I
MFP0
HSUSB identification.
97
NC
-
-
No connection.
98
NC
-
-
No connection.
99
PE.5
I/O
MFP0
General purpose digital I/O pin.
EBI_nRD
O
MFP2
EBI read enable output pin.
SD0_DAT3
I/O
MFP3
SD/SDIO0 data line bit 3.
SPIM_SS
I/O
MFP4
SPIM slave select pin.
SPI3_SS
I/O
MFP5
SPI3 slave select pin.
SC0_PWR
O
MFP6
Smart Card 0 power pin.
USCI0_CTL1
I/O
MFP7
USCI0 control 1 pin.
QEI1_B
I
MFP11
Quadrature encoder 1 phase B input
EPWM0_CH2
I/O
MFP12
EPWM0 channel 2 output/capture input.
BPWM0_CH3
I/O
MFP13
BPWM0 channel 3 output/capture input.
100 NC
-
-
No connection.
101 PE.3
I/O
MFP0
General purpose digital I/O pin.
EBI_MCLK
O
MFP2
EBI external clock output pin.
SD0_DAT1
I/O
MFP3
SD/SDIO0 data line bit 1.
SPIM_MISO
I/O
MFP4
SPIM MISO (Master In, Slave Out) pin.
SPI3_MISO
I/O
MFP5
SPI3 MISO (Master In, Slave Out) pin.
SC0_DAT
I/O
MFP6
Smart Card 0 data pin.
USCI0_DAT0
I/O
MFP7
USCI0 data 0 pin.
QEI0_A
I
MFP11
Quadrature encoder 0 phase A input
EPWM0_CH4
I/O
MFP12
EPWM0 channel 4 output/capture input.
BPWM0_CH1
I/O
MFP13
BPWM0 channel 1 output/capture input.
May 08, 2020
Page 309 of 523
M480 SERIES DATASHEET
96
Rev 3.00
M480
128 Pin Name
Pin
Type
MFP
Description
102 NC
-
-
No connection.
103 VSS
P
MFP0
Ground pin for digital circuit.
104 VDD
P
MFP0
Power supply for I/O ports and LDO source for internal PLL
and digital circuit.
105 PE.1
I/O
MFP0
General purpose digital I/O pin.
EBI_AD10
I/O
MFP2
EBI address/data bus bit 10.
QSPI0_MISO0
I/O
MFP3
QSPI0 MISO0 (Master In, Slave Out) pin.
SC2_DAT
I/O
MFP4
Smart Card 2 data pin.
I S0_BCLK
O
MFP5
I2S0 bit clock output pin.
SPI1_MISO
I/O
MFP6
SPI1 MISO (Master In, Slave Out) pin.
UART3_TXD
O
MFP7
UART3 data transmitter output pin.
I C1_SCL
I/O
MFP8
I2C1 clock pin.
UART4_nCTS
I
MFP9
UART4 clear to Send input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD11
I/O
MFP2
EBI address/data bus bit 11.
QSPI0_MOSI0
I/O
MFP3
QSPI0 MOSI0 (Master Out, Slave In) pin.
SC2_CLK
O
MFP4
Smart Card 2 clock pin.
I S0_MCLK
O
MFP5
I2S0 master clock output pin.
SPI1_MOSI
I/O
MFP6
SPI1 MOSI (Master Out, Slave In) pin.
UART3_RXD
I
MFP7
UART3 data receiver input pin.
I2C1_SDA
I/O
MFP8
I2C1 data input/output pin.
UART4_nRTS
O
MFP9
UART4 request to Send output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD12
I/O
MFP2
EBI address/data bus bit 12.
QSPI0_CLK
I/O
MFP3
QSPI0 serial clock pin.
SC2_PWR
O
MFP4
Smart Card 2 power pin.
I S0_DI
I
MFP5
I2S0 data input pin.
SPI1_CLK
I/O
MFP6
SPI1 serial clock pin.
UART3_nRTS
O
MFP7
UART3 request to Send output pin.
I2C1_SMBAL
O
MFP8
I2C1 SMBus SMBALTER pin
I2C2_SCL
I/O
MFP9
I2C2 clock pin.
UART1_TXD
O
MFP10
UART1 data transmitter output pin.
I/O
MFP0
General purpose digital I/O pin.
I/O
MFP2
EBI address/data bus bit 13.
2
2
106 PE.0
2
M480 SERIES DATASHEET
107 PH.8
2
108 PH.9
EBI_AD13
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M480
128 Pin Name
Pin
MFP
Description
QSPI0_SS
I/O
MFP3
QSPI0 slave select pin.
SC2_RST
O
MFP4
Smart Card 2 reset pin.
I S0_DO
O
MFP5
I2S0 data output pin.
SPI1_SS
I/O
MFP6
SPI1 slave select pin.
UART3_nCTS
I
MFP7
UART3 clear to Send input pin.
I2C1_SMBSUS
O
MFP8
I2C1 SMBus SMBSUS pin (PMBus CONTROL pin)
I2C2_SDA
I/O
MFP9
I2C2 data input/output pin.
UART1_RXD
I
MFP10
UART1 data receiver input pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD14
I/O
MFP2
EBI address/data bus bit 14.
QSPI0_MISO1
I/O
MFP3
QSPI0 MISO1 (Master In, Slave Out) pin.
SC2_nCD
I
MFP4
Smart Card 2 card detect pin.
I2S0_LRCK
O
MFP5
I2S0 left right channel clock output pin.
SPI1_I2SMCLK
I/O
MFP6
SPI1 I2S master clock output pin
UART4_TXD
O
MFP7
UART4 data transmitter output pin.
UART0_TXD
O
MFP8
UART0 data transmitter output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD15
I/O
MFP2
EBI address/data bus bit 15.
QSPI0_MOSI1
I/O
MFP3
QSPI0 MOSI1 (Master Out, Slave In) pin.
UART4_RXD
I
MFP7
UART4 data receiver input pin.
UART0_RXD
I
MFP8
UART0 data receiver input pin.
EPWM0_CH5
I/O
MFP11
EPWM0 channel 5 output/capture input.
I/O
MFP0
General purpose digital I/O pin.
EBI_nCS0
O
MFP2
EBI chip select 0 output pin.
SPI3_I2SMCLK
I/O
MFP3
SPI3 I2S master clock output pin
SC1_nCD
I
MFP4
Smart Card 1 card detect pin.
EPWM0_CH4
I/O
MFP11
EPWM0 channel 4 output/capture input.
112 VSS
P
MFP0
Ground pin for digital circuit.
113 LDO_CAP
A
MFP0
LDO output pin.
2
109 PH.10
110 PH.11
111 PD.14
M480 SERIES DATASHEET
Type
Note: This pin needs to be connected with an external
capacitor.
114 VDD
P
MFP0
Power supply for I/O ports and LDO source for internal PLL
and digital circuit.
115 PC.14
I/O
MFP0
General purpose digital I/O pin.
I/O
MFP2
EBI address/data bus bit 11.
EBI_AD11
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M480
128 Pin Name
Pin
Type
MFP
Description
SC1_nCD
I
MFP3
Smart Card 1 card detect pin.
SPI0_I2SMCLK
I/O
MFP4
SPI0 I2S master clock output pin
USCI0_CTL0
I/O
MFP5
USCI0 control 0 pin.
QSPI0_CLK
I/O
MFP6
QSPI0 serial clock pin.
EPWM0_SYNC_IN
I
MFP11
EPWM0 counter synchronous trigger input pin.
ETM_TRACE_CLK
I
MFP12
ETM receiver Trace Clock input pin
TM1
I/O
MFP13
Timer1 event counter input/toggle output pin.
USB_VBUS_ST
I
MFP14
USB external VBUS regulator status pin.
HSUSB_VBUS_ST
I
MFP15
HSUSB external VBUS regulator status pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH15
A
MFP1
EADC0 channel 15 analog input.
EBI_AD12
I/O
MFP2
EBI address/data bus bit 12.
SC1_PWR
O
MFP3
Smart Card 1 power pin.
SPI0_SS
I/O
MFP4
SPI0 slave select pin.
USCI0_CTL1
I/O
MFP5
USCI0 control 1 pin.
UART0_nCTS
I
MFP6
UART0 clear to Send input pin.
UART3_TXD
O
MFP7
UART3 data transmitter output pin.
I2C2_SMBAL
O
MFP8
I2C2 SMBus SMBALTER pin
EPWM1_CH0
I/O
MFP11
EPWM1 channel 0 output/capture input.
ETM_TRACE_DATA0
I
MFP12
ETM receiver Trace Data 0 input pin
TM0_EXT
I/O
MFP13
Timer0 event counter input/toggle output pin.
USB_VBUS_EN
O
MFP14
USB external VBUS regulator enable pin.
HSUSB_VBUS_EN
O
MFP15
HSUSB external VBUS regulator enable pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH14
A
MFP1
EADC0 channel 14 analog input.
EBI_AD13
I/O
MFP2
EBI address/data bus bit 13.
SC1_RST
O
MFP3
Smart Card 1 reset pin.
SPI0_CLK
I/O
MFP4
SPI0 serial clock pin.
USCI0_DAT1
I/O
MFP5
USCI0 data 1 pin.
UART0_nRTS
O
MFP6
UART0 request to Send output pin.
UART3_RXD
I
MFP7
UART3 data receiver input pin.
I C2_SMBSUS
O
MFP8
I2C2 SMBus SMBSUS pin (PMBus CONTROL pin)
EPWM1_CH1
I/O
MFP11
EPWM1 channel 1 output/capture input.
ETM_TRACE_DATA1
I
MFP12
ETM receiver Trace Data 1 input pin
116 PB.15
M480 SERIES DATASHEET
117 PB.14
2
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M480
128 Pin Name
Pin
MFP
Description
TM1_EXT
I/O
MFP13
Timer1 event counter input/toggle output pin.
CLKO
O
MFP14
Clock Out
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH13
A
MFP1
EADC0 channel 13 analog input.
DAC1_OUT
A
MFP1
DAC1 channel analog output.
ACMP0_P3
A
MFP1
Analog comparator 0 positive input 3 pin.
ACMP1_P3
A
MFP1
Analog comparator 1 positive input 3 pin.
EBI_AD14
I/O
MFP2
EBI address/data bus bit 14.
SC1_DAT
I/O
MFP3
Smart Card 1 data pin.
SPI0_MISO
I/O
MFP4
SPI0 MISO (Master In, Slave Out) pin.
USCI0_DAT0
I/O
MFP5
USCI0 data 0 pin.
UART0_TXD
O
MFP6
UART0 data transmitter output pin.
UART3_nRTS
O
MFP7
UART3 request to Send output pin.
I C2_SCL
I/O
MFP8
I2C2 clock pin.
EPWM1_CH2
I/O
MFP11
EPWM1 channel 2 output/capture input.
ETM_TRACE_DATA2
I
MFP12
ETM receiver Trace Data 2 input pin
TM2_EXT
I/O
MFP13
Timer2 event counter input/toggle output pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH12
A
MFP1
EADC0 channel 12 analog input.
DAC0_OUT
A
MFP1
DAC0 channel analog output.
ACMP0_P2
A
MFP1
Analog comparator 0 positive input 2 pin.
ACMP1_P2
A
MFP1
Analog comparator 1 positive input 2 pin.
EBI_AD15
I/O
MFP2
EBI address/data bus bit 15.
SC1_CLK
O
MFP3
Smart Card 1 clock pin.
SPI0_MOSI
I/O
MFP4
SPI0 MOSI (Master Out, Slave In) pin.
USCI0_CLK
I/O
MFP5
USCI0 clock pin.
UART0_RXD
I
MFP6
UART0 data receiver input pin.
UART3_nCTS
I
MFP7
UART3 clear to Send input pin.
I2C2_SDA
I/O
MFP8
I2C2 data input/output pin.
SD0_nCD
I
MFP9
SD/SDIO0 card detect input pin
EPWM1_CH3
I/O
MFP11
EPWM1 channel 3 output/capture input.
ETM_TRACE_DATA3
I
MFP12
ETM receiver Trace Data 3 input pin
TM3_EXT
I/O
MFP13
Timer3 event counter input/toggle output pin.
P
MFP0
Power supply for internal analog circuit.
118 PB.13
2
119 PB.12
120 AVDD
May 08, 2020
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M480 SERIES DATASHEET
Type
Rev 3.00
M480
128 Pin Name
Pin
Type
MFP
Description
121 VREF
A
MFP0
ADC reference voltage input.
Note: This pin needs to be connected with a 1uF capacitor.
122 AVSS
P
MFP0
Ground pin for analog circuit.
123 PB.11
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH11
A
MFP1
EADC0 channel 11 analog input.
EBI_ADR16
O
MFP2
EBI address bus bit 16.
EMAC_RMII_MDC
O
MFP3
EMAC RMII PHY Management Clock output pin.
UART0_nCTS
I
MFP5
UART0 clear to Send input pin.
UART4_TXD
O
MFP6
UART4 data transmitter output pin.
I2C1_SCL
I/O
MFP7
I2C1 clock pin.
CAN0_TXD
O
MFP8
CAN0 bus transmitter output.
SPI0_I2SMCLK
I/O
MFP9
SPI0 I2S master clock output pin
BPWM1_CH0
I/O
MFP10
BPWM1 channel 0 output/capture input.
SPI3_CLK
I/O
MFP11
SPI3 serial clock pin.
HSUSB_VBUS_ST
I
MFP14
HSUSB external VBUS regulator status pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH10
A
MFP1
EADC0 channel 10 analog input.
EBI_ADR17
O
MFP2
EBI address bus bit 17.
EMAC_RMII_MDIO
I/O
MFP3
EMAC RMII PHY Management Data pin.
USCI1_CTL0
I/O
MFP4
USCI1 control 0 pin.
UART0_nRTS
O
MFP5
UART0 request to Send output pin.
UART4_RXD
I
MFP6
UART4 data receiver input pin.
I C1_SDA
I/O
MFP7
I2C1 data input/output pin.
CAN0_RXD
I
MFP8
CAN0 bus receiver input.
BPWM1_CH1
I/O
MFP10
BPWM1 channel 1 output/capture input.
SPI3_SS
I/O
MFP11
SPI3 slave select pin.
HSUSB_VBUS_EN
O
MFP14
HSUSB external VBUS regulator enable pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH9
A
MFP1
EADC0 channel 9 analog input.
EBI_ADR18
O
MFP2
EBI address bus bit 18.
EMAC_RMII_TXD0
O
MFP3
EMAC RMII Transmit Data bus bit 0.
USCI1_CTL1
I/O
MFP4
USCI1 control 1 pin.
UART0_TXD
O
MFP5
UART0 data transmitter output pin.
UART1_nCTS
I
MFP6
UART1 clear to Send input pin.
124 PB.10
M480 SERIES DATASHEET
2
125 PB.9
May 08, 2020
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M480
128 Pin Name
Pin
MFP
Description
I2C1_SMBAL
O
MFP7
I2C1 SMBus SMBALTER pin
BPWM1_CH2
I/O
MFP10
BPWM1 channel 2 output/capture input.
SPI3_MISO
I/O
MFP11
SPI3 MISO (Master In, Slave Out) pin.
INT7
I
MFP13
External interrupt 7 input pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH8
A
MFP1
EADC0 channel 8 analog input.
EBI_ADR19
O
MFP2
EBI address bus bit 19.
EMAC_RMII_TXD1
O
MFP3
EMAC RMII Transmit Data bus bit 1.
USCI1_CLK
I/O
MFP4
USCI1 clock pin.
UART0_RXD
I
MFP5
UART0 data receiver input pin.
UART1_nRTS
O
MFP6
UART1 request to Send output pin.
I C1_SMBSUS
O
MFP7
I2C1 SMBus SMBSUS pin (PMBus CONTROL pin)
BPWM1_CH3
I/O
MFP10
BPWM1 channel 3 output/capture input.
SPI3_MOSI
I/O
MFP11
SPI3 MOSI (Master Out, Slave In) pin.
INT6
I
MFP13
External interrupt 6 input pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH7
A
MFP1
EADC0 channel 7 analog input.
EBI_nWRL
O
MFP2
EBI low byte write enable output pin.
EMAC_RMII_TXEN
O
MFP3
EMAC RMII Transmit Enable output pin.
USCI1_DAT0
I/O
MFP4
USCI1 data 0 pin.
CAN1_TXD
O
MFP5
CAN1 bus transmitter output.
UART1_TXD
O
MFP6
UART1 data transmitter output pin.
SD1_CMD
I/O
MFP7
SD/SDIO1 command/response pin
EBI_nCS0
O
MFP8
EBI chip select 0 output pin.
BPWM1_CH4
I/O
MFP10
BPWM1 channel 4 output/capture input.
EPWM1_BRAKE0
I
MFP11
EPWM1 Brake 0 input pin.
EPWM1_CH4
I/O
MFP12
EPWM1 channel 4 output/capture input.
INT5
I
MFP13
External interrupt 5 input pin.
USB_VBUS_ST
I
MFP14
USB external VBUS regulator status pin.
ACMP0_O
O
MFP15
Analog comparator 0 output pin.
I/O
MFP0
General purpose digital I/O pin.
EADC0_CH6
A
MFP1
EADC0 channel 6 analog input.
EBI_nWRH
O
MFP2
EBI high byte write enable output pin
EMAC_PPS
O
MFP3
EMAC Pulse Per Second output pin.
126 PB.8
2
127 PB.7
128 PB.6
May 08, 2020
Page 315 of 523
M480 SERIES DATASHEET
Type
Rev 3.00
M480
128 Pin Name
Pin
Type
MFP
Description
USCI1_DAT1
I/O
MFP4
USCI1 data 1 pin.
CAN1_RXD
I
MFP5
CAN1 bus receiver input.
UART1_RXD
I
MFP6
UART1 data receiver input pin.
SD1_CLK
O
MFP7
SD/SDIO1 clock output pin
EBI_nCS1
O
MFP8
EBI chip select 1 output pin.
BPWM1_CH5
I/O
MFP10
BPWM1 channel 5 output/capture input.
EPWM1_BRAKE1
I
MFP11
EPWM1 Brake 1 input pin.
EPWM1_CH5
I/O
MFP12
EPWM1 channel 5 output/capture input.
INT4
I
MFP13
External interrupt 4 input pin.
USB_VBUS_EN
O
MFP14
USB external VBUS regulator enable pin.
ACMP1_O
O
MFP15
Analog comparator 1 output pin.
M480 SERIES DATASHEET
May 08, 2020
Page 316 of 523
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M480
5
BLOCK DIAGRAM
5.1 M480 Block Diagram
®
Figure 5.1-1 NuMicro M480 Block Diagram (M48xID)
M480 SERIES DATASHEET
®
Figure 5.1-2 NuMicro M480 Block Diagram (M487KMCAN)
May 08, 2020
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M480
®
Figure 5.1-3 NuMicro M480 Block Diagram (M48xGC)
M480 SERIES DATASHEET
®
Figure 5.1-4 NuMicro M480 Block Diagram (M48xE8)
May 08, 2020
Page 318 of 523
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M480
6
FUNCTIONAL DESCRIPTION
6.1 Arm® Cortex® -M4F Core
®
The Cortex -M4 processor, a configurable, multistage, 32-bit RISC processor, has three AMBA AHBLite interfaces for best parallel performance and includes an NVIC component. The processor with
®
optional hardware debug functionality can execute Thumb code and is compatible with other Cortex M profile processors. The profile supports two modes -Thread mode and Handler mode. Handler
mode is entered as a result of an exception. An exception return can only be issued in Handler mode.
®
Thread mode is entered on Reset, and can be entered as a result of an exception return. The Cortex ®
M4F is a processor with the same capability as the Cortex -M4 processor and includes floating point
®
®
arithmetic functionality. The NuMicro M480 series is embedded with Cortex -M4F processor.
®
®
®
Throughout this document, the name Cortex -M4 refers to both Cortex -M4 and Cortex -M4F
processors. Figure 6.1-1 shows the functional controller of the processor.
M480 SERIES DATASHEET
®
Figure 6.1-1 Cortex -M4F Block Diagram
®
Cortex -M4F processor features:
A low gate count processor core, with low latency interrupt processing that has:
–
A subset of the Thumb instruction set, defined in the Armv7-M Architecture Reference
Manual
–
Banked Stack Pointer (SP)
–
Hardware integer divide instructions, SDIV and UDIV
–
Handler and Thread modes
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M480
M480 SERIES DATASHEET
–
Thumb and Debug states
–
Support for interruptible-continued instructions LDM, STM, PUSH, and POP for low
interrupt latency
–
Automatic processor state saving and restoration for low latency Interrupt Service
Routine (ISR) entry and exit
–
Support for Armv6 big-endian byte-invariant or little-endian accesses
–
Support for Armv6 unaligned accesses
®
Floating Point Unit (FPU) in the Cortex -M4F processor providing:
–
32-bit instructions for single-precision (C float) data-processing operations
–
Combined Multiply and Accumulate instructions for increased precision (Fused MAC)
–
Hardware support for conversion, addition, subtraction, multiplication with optional
accumulate, division, and square-root
–
Hardware support for denormals and all IEEE rounding modes
–
32 dedicated 32-bit single precision registers, also addressable as 16 double-word
registers
–
Decoupled three stage pipeline
Nested Vectored Interrupt Controller (NVIC) closely integrated with the processor core to
achieve low latency interrupt processing. Features include:
®
–
External interrupts. Configurable from 1 to 240 (the NuMicro M480 series configured
with 64 interrupts)
–
Bits of priority, configurable from 3 to 8
–
Dynamic reprioritization of interrupts
–
Priority grouping which enables selection of preempting interrupt levels and
nonpreempting interrupt levels
–
Support for tril-chaining and late arrival of interrupts, which enables back-to-back
interrupt processing without the overhead of state saving and restoration between
interrupts.
–
Processor state automatically saved on interrupt entry, and restored on interrupt exit
with on instruction overhead
–
Support for Wake-up Interrupt Controller (WIC) with Ultra-low Power Sleep mode
Memory Protection Unit (MPU). An optional MPU for memory protection, including:
–
Eight memory regions
–
Sub Region Disable (SRD), enabling efficient use of memory regions
–
The ability to enable a background region that implements the default memory map
attributes
Low-cost debug solution that features:
–
Debug access to all memory and registers in the system, including access to memory
mapped devices, access to internal core registers when the core is halted, and access
to debug control registers even while SYSRESETn is asserted.
–
Serial Wire Debug Port(SW-DP) or Serial Wire JTAG Debug Port (SWJ-DP) debug
access
–
Optional Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and
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M480
code patches
–
Optional Data Watchpoint and Trace (DWT) unit for implementing watchpoints, data
tracing, and system profiling
–
Optional Instrumentation Trace Macrocell (ITM) for support of printf() style debugging
–
Optional Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer (TPA),
including Single Wire Output (SWO) mode
–
Optional Embedded Trace Macrocell (ETM) for instruction trace.
Bus interfaces:
–
Three Advanced High-performance Bus-Lite (AHB-Lite) interfaces: ICode, Dcode, and
System bus interfaces
–
Private Peripheral Bus (PPB) based on Advanced Peripheral Bus (APB) interface
–
Bit-band support that includes atomic bit-band write and read operations.
–
Memory access alignment
–
Write buffer for buffering of write data
–
Exclusive access transfers for multiprocessor systems
M480 SERIES DATASHEET
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M480
6.2 System Manager
6.2.1
Overview
System management includes the following sections:
6.2.2
System Reset
System Power Distribution
SRAM Memory Orginization
System Timer (SysTick)
Nested Vectored Interrupt Controller (NVIC)
System Control register
System Reset
The system reset can be issued by one of the events listed below. These reset event flags can be
read from SYS_RSTSTS register to determine the reset source. Hardware reset sourcces are from
peripheral signals. Software reset can trigger reset through setting control registers.
Hardware Reset Sources
–
Power-on Reset
–
Low level on the nRESET pin
–
Watchdog Time-out Reset and Window Watchdog Reset (WDT/WWDT Reset)
–
Low Voltage Reset (LVR)
–
Brown-out Detector Reset (BOD Reset)
–
CPU Lockup Reset
Software Reset Sources
M480 SERIES DATASHEET
–
CHIP Reset will reset whole chip by writing 1 to CHIPRST (SYS_IPRST0[0])
–
MCU Reset to reboot but keeping the booting setting from APROM or LDROM by
writing 1 to SYSRESETREQ (AIRCR[2])
–
CPU Reset for Cortex -M4 core only by writing 1 to CPURST (SYS_IPRST0[1])
May 08, 2020
®
Page 322 of 523
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M480
Glitch Filter
32 us
nRESET
~50k ohm
@3.3v
VDD
POROFF(SYS_PORCTL[15:0])
Power-on
Reset
LVREN(SYS_BODCTL[7])
AVDD
Reset Pulse Width
~3.2ms
Low Voltage
Reset
BODRSTEN(SYS_BODCTL[3])
Brown-out
Reset
WDT/WWDT
Reset
Reset Pulse Width
64 WDT clocks
CPU Lockup
Reset
Reset Pulse Width
2 system clocks
System Reset
CHIP Reset
CHIPRST(SYS_IPRST0[0])
MCU Reset
SYSRSTREQ(AIRCR[2])
Software Reset
Reset Pulse Width
2 system clocks
CPU Reset
CPURST(SYS_IPRST0[1])
Figure 6.2-1 System Reset Sources
®
There are a total of 9 reset sources in the NuMicro family. In general, CPU reset is used to reset
®
®
Cortex -M4 only; the other reset sources will reset Cortex -M4 and all peripherals. However, there are
small differences between each reset source and they are listed in Table 6.2-1.
Reset Sources
Register
CHIPRST
(SYS_IPRST0[0])
nRESET
WDT
LVR
BOD
Lockup
CHIP
MCU
CPU
Bit 0 = 1
Bit 1 = 1
Bit 2 = 1
Bit 3 = 1
Bit 4 = 1
Bit 8 = 1
Bit 0 = 1
Bit 5 = 1
Bit 7 = 1
0x0
-
-
-
-
-
-
-
-
BODEN
(SYS_BODCTL[0])
BODVL
(SYS_BODCTL[2:1])
Reload
Reload
Reload
Reload
from
from
from
from
CONFIG0 CONFIG0 CONFIG0 CONFIG0
-
Reload
Reload
Reload
from
from
from
CONFIG0 CONFIG0 CONFIG0
-
BODRSTEN
(SYS_BODCTL[3])
HXTEN
(CLK_PWRCTL[0])
LXTEN
(CLK_PWRCTL[1])
WDTCKEN
(CLK_APBCLK0[0])
HCLKSEL
May 08, 2020
Reload
Reload
Reload
Reload
Reload
Reload
Reload
Reload
from
from
from
from
from
from
from
from
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
0x0
-
-
-
-
-
-
-
-
0x1
-
0x1
-
-
-
0x1
-
-
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
-
Page 323 of 523
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M480 SERIES DATASHEET
SYS_RSTSTS
POR
M480
(CLK_CLKSEL0[2:0])
WDTSEL
(CLK_CLKSEL1[1:0])
HXTSTB
(CLK_STATUS[0])
LXTSTB
(CLK_STATUS[1])
PLLSTB
(CLK_STATUS[2])
HIRCSTB
(CLK_STATUS[4])
CLKSFAIL
(CLK_STATUS[7])
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
0x3
0x3
-
-
-
-
-
-
-
0x0
-
-
-
-
-
-
-
-
0x0
-
-
-
-
-
-
-
-
0x0
-
-
-
-
-
-
-
-
0x0
-
-
-
-
-
-
-
-
0x0
0x0
-
-
-
-
-
-
-
-
Reload
from
CONFIG0
-
-
RSTEN
(WDT_CTL[1])
WDTEN
Reload
Reload
Reload
Reload
Reload
from
from
from
from
from
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
(WDT_CTL[7])
WDT_CTL
0x0700
0x0700
0x0700
0x0700
0x0700
-
0x0700
-
-
WDT_ALTCTL
0x0000
0x0000
0x0000
0x0000
0x0000
-
0x0000
-
-
WWDT_RLDCNT
0x0000
0x0000
0x0000
0x0000
0x0000
-
0x0000
-
-
-
0x3F0800
-
-
except bit 1 and bit 7.
WWDT_CTL
WWDT_STATUS
M480 SERIES DATASHEET
WWDT_CNT
0x3F0800 0x3F0800 0x3F0800 0x3F0800 0x3F0800
0x0000
0x0000
0x0000
0x0000
0x0000
-
0x0000
-
-
0x3F
0x3F
0x3F
0x3F
0x3F
-
0x3F
-
-
Reload
Reload
Reload
Reload
Reload
from
from
from
from
from
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
-
Reload
from
CONFIG0
-
-
Reload
Reload
Reload
Reload
Reload
from
from
from
from
from
CONFIG1 CONFIG1 CONFIG1 CONFIG1 CONFIG1
-
Reload
from
CONFIG1
-
-
Reload
Reload
Reload
Reload
Reload
from
from
from
from
from
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
-
Reload
from
CONFIG0
-
-
Reload
Reload
Reload
Reload
Reload
base on base on base on base on base on
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
-
Reload
base on
CONFIG0
-
-
BS
(FMC_ISPCTL[1])
BL
(FMC_ISPCTL[16])
FMC_DFBA
CBS
(FMC_ISPSTS[2:1))
VECMAP
(FMC_ISPSTS[23:9])
Other Peripheral
Registers
Reset Value
FMC Registers
Reset Value
-
Note: ‘-‘ means that the value of register keeps original setting.
Table 6.2-1 Reset Value of Registers
May 08, 2020
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M480
6.2.2.1
nRESET Reset
The nRESET reset means to generate a reset signal by pulling low nRESET pin, which is an
asynchronous reset input pin and can be used to reset system at any time. When the nRESET voltage
is lower than 0.2 VDD and the state keeps longer than 32 us (glitch filter), chip will be reset. The
nRESET reset will control the chip in reset state until the nRESET voltage rises above 0.7 V DD and the
state keeps longer than 32 us (glitch filter). The PINRF(SYS_RSTSTS[1]) will be set to 1 if the
previous reset source is nRESET reset Figure 6.2-2 shows the nRESET reset waveform.
nRESET
0.7 VDD
32 us
0.2 VDD
32 us
nRESET Reset
Figure 6.2-2 nRESET Reset Waveform
6.2.2.2
Power-on Reset (POR)
The Power-on reset (POR) is used to generate a stable system reset signal and forces the system to
be reset when power-on to avoid unexpected behavior of MCU. When applying the power to MCU, the
POR module will detect the rising voltage and generate reset signal to system until the voltage is
ready for MCU operation. At POR reset, the PORF(SYS_RSTSTS[0]) will be set to 1 to indicate there
is a POR reset event. The PORF(SYS_RSTSTS[0]) bit can be cleared by writing 1 to it.Figure 6.2-3
shows the power-on reset waveform.
M480 SERIES DATASHEET
VPOR
0.1V
VDD
Power-on
Reset
Figure 6.2-3 Power-on Reset (POR) Waveform
6.2.2.3
Low Voltage Reset (LVR)
If the Low Voltage Reset function is enabled by setting the Low Voltage Reset Enable Bit LVREN
(SYS_BODCTL[7]) to 1, after 200us delay, LVR detection circuit will be stable and the LVR function
will be active. Then LVR function will detect AVDD during system operation. When the AVDD voltage is
lower than VLVR and the state keeps longer than De-glitch time set by LVRDGSEL
(SYS_BODCTL[14:12]), chip will be reset. The LVR reset will control the chip in reset state until the
May 08, 2020
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AVDD voltage rises above VLVR and the state keeps longer than De-glitch time set by LVRDGSEL
(SYS_BODCTL[14:12]). The default setting of Low Voltage Reset is enabled without De-glitch
function.Figure 6.2-4 shows the Low Voltage Reset waveform.
AVDD
VLVR
T1
( < LVRDGSEL)
T2
( =LVRDGSEL)
T3
( =LVRDGSEL)
Low Voltage Reset
200 us
Delay for LVR stable
LVREN
Figure 6.2-4 Low Voltage Reset (LVR) Waveform
6.2.2.4
Brown-out Detector Reset (BOD Reset)
M480 SERIES DATASHEET
If the Brown-out Detector (BOD) function is enabled by setting the Brown-out Detector Enable Bit
BODEN (SYS_BODCTL[0]), Brown-out Detector function will detect AVDD during system operation.
When the AVDD voltage is lower than VBOD which is decided by BODEN and BODVL
(SYS_BODCTL[18:16]) and the state keeps longer than De-glitch time set by BODDGSEL
(SYS_BODCTL[10:8]), chip will be reset. The BOD reset will control the chip in reset state until the
AVDD voltage rises above VBOD and the state keeps longer than De-glitch time set by BODDGSEL. The
default value of BODEN, BODVL and BODRSTEN (SYS_BODCTL[3]) is set by Flash controller user
configuration
register
CBODEN
(CONFIG0
[19]),
CBOV
(CONFIG0
[23:21])
and
CBORST(CONFIG0[20]) respectively. User can determine the initial BOD setting by setting the
CONFIG0 register. Figure 6.2-5 shows the Brown-out Detector waveform.
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M480
AVDD
VBODH
VBODL
Hysteresis
T1
(< BODDGSEL)
T2
(= BODDGSEL)
BODOUT
T3
(= BODDGSEL)
BODRSTEN
Brown-out
Reset
Figure 6.2-5 Brown-out Detector (BOD) Waveform
6.2.2.5
Watchdog Timer Reset (WDT)
Software can check if the reset is caused by watchdog time-out to indicate the previous reset is a
watchdog reset and handle the failure of MCU after watchdog time-out reset by checking
WDTRF(SYS_RSTSTS[2]).
6.2.2.6
CPU Lockup Reset
CPU enters lockup status after CPU produces hardfault at hardfault handler and chip gives immediate
indication of seriously errant kernel software. This is the result of the CPU being locked because of an
unrecoverable exception following the activation of the processor’s built in system state protection
hardware. When chip enters debug mode, the CPU lockup reset will be ignored.
6.2.2.7
CPU Reset, CHIP Reset and MCU Reset
®
The CPU Reset means only Cortex -M4 core is reset and all other peripherals remain the same status
after CPU reset. User can set the CPURST(SYS_IPRST0[1]) to 1 to assert the CPU Reset signal.
The CHIP Reset is same with Power-on Reset. The CPU and all peripherals are reset and
BS(FMC_ISPCTL[1]) bit is automatically reloaded from CONFIG0 setting. User can set the
CHIPRST(SYS_IPRST0[1]) to 1 to assert the CHIP Reset signal.
The MCU Reset is similar with CHIP Reset. The difference is that BS(FMC_ISPCTL[1]) will not be
reloaded from CONFIG0 setting and keep its original software setting for booting from APROM or
LDROM. User can set the SYSRESETREQ(AIRCR[2]) to 1 to assert the MCU Reset.
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M480 SERIES DATASHEET
In most industrial applications, system reliability is very important. To automatically recover the MCU
from failure status is one way to improve system reliability. The watchdog timer(WDT) is widely used
to check if the system works fine. If the MCU is crashed or out of control, it may cause the watchdog
time-out. User may decide to enable system reset during watchdog time-out to recover the system and
take action for the system crash/out-of-control after reset.
M480
6.2.3
System Power Distribution
In this chip, power distribution is divided into four segments:
Analog power from AVDD and AVSS provides the power for analog components operation.
Digital power from VDD and VSS supplies the power to the internal regulator which
provides a fixed 1.8 V power for digital operation and I/O pins.
USB transceiver power from VBUS offers the power for operating the USB transceiver.
RTC power from VBAT provides the power for RTC and 80 bytes backup registers.
AVDD
12-bit ADC
Internal
Reference
Voltage
12-bit DAC
Analog
Comparator
AVSS
OPA0/1/2
PF.5
PF.4
PF.6~PF.11
VREF
VBAT
The outputs of internal voltage regulators, LDO and V DD33, require an external capacitor which should
be located close to the corresponding pin. Analog power (AVDD) should be the same voltage level of
®
the digital power (VDD). Figure 6.2-6 shows the NuMicro M480 power distribution.
32.768 kHz
crystal
oscillator
IO Cell
HSUSB_D+
HSUSB_DHSUSB_VDD12_CAP
0.9V
USB 2.0
OTG OHY
Temp. Sensor
SRAM
HSUSB_VBUS
HSUSB_VRES
HSUSB_VDD33
Flash
IO Cell
PA.0~PA.5
1.2V/1.26V
2uF
PLL
PF.2
PF.3
4~24 MHz
crystal
oscillator
POR12
POR33
12 MHz HIRC
Oscillator
10 kHz
LIRC
Oscillator
3.3V à
1.2V/1.26V
LDO
Power
On
Control
USB 1.1
OTG
PHY
VDDIO
IO Cell
GPIO except
PF.4 ~PF.11 and
PA.0~PA.5
VSS
M480 Power Distribution
VDD
M480 SERIES DATASHEET
Digital Logic
RTC &
80 bytes
backup
register
RTCLDO
3.3V à 0.9V
LVDR
(Low Voltage Reset, Brown-out
Detector)
LDO_CAP
1uF
®
Figure 6.2-6 NuMicro M480 Power Distribution Diagram
May 08, 2020
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M480
Note:
1. When VBAT power source first power-on, the power-on reset will happened and reset all VBAT
domain circuit. The I/O in VBAT domain (PF.4 ~ PF.11) will become floating state and make
additional leakage in VBAT domain. User should power on VDD first to reset chip and set I/O control
to make these I/Os becomes a static state to prevent additional leakage .
2. The VBAT domain I/O (PF.4 ~ PF.11) will have unpredictable 1.5V glitch during power-on if VBAT
and VDD connect together. To prevent this unpredictable glitch to make , user should avoid use
these pins to be other IC’s active or inactive control pins.
M480 SERIES DATASHEET
May 08, 2020
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M480
6.2.4
Power Modes and Wake-up Sources
®
The NuMicro M480 series has power manager unit to support several operating modes for saving
®
power. Table 6.2-2 lists all power mode at NuMicro M480 series.
CPU Operating Maximum
Speed
Mode
LDO_CAP Clock Disable
(V)
( MHz)
Normal mode
160
1.20
All clocks are disabled by control register.
Turbo mode
192
1.26
All clocks are disabled by control register.
Idle mode
Fast Wakeup
mode (FWPD)
CPU enter Sleep mode
1.20/1.26 Only CPU clock is disabled.
Power-down CPU enters Deep Sleep mode
Normal Power-down mode
CPU enters Deep Sleep mode
(NPD)
Low leakage Power-down
mode
CPU enters Deep Sleep mode
1.20/1.26 Most clocks are disabled except LIRC/LXT, and
only RTC/WDT/Timer/UART peripheral clocks
still enable if their clock sources are selected as
LIRC/LXT.
1.20/1.26 Most clocks are disabled except LIRC/LXT, and
only RTC/WDT/Timer/UART peripheral clocks
still enable if their clock sources are selected as
LIRC/LXT.
Most clocks are disabled except LIRC/LXT, and
only RTC/WDT/Timer/UART peripheral clocks
still enable if their clock sources are selected as
LIRC/LXT.
0.9
(LLPD)
Standby Power-down mode
Power off
Floating Only LIRC/LXT still enable for RTC function and
wake-up timer usage
Power off
Floating Only LIRC/LXT still enable for RTC function and
wake-up timer usage
Power off
Floating Only LIRC/LXT still enable for RTC function and
wake-up timer usage
(SPD0)
Standby Power-down mode
(SPD1) (M48xID/M487KMCAN)
Deep Power-down mode
(DPD)*
M480 SERIES DATASHEET
*M487KMCAN doesn’t support Deep Power-down mode (DPD)
Table 6.2-2 Power Mode Table
Note:
1. User must turn on LIRC before entering SPD0/1 mode.
2. SPD0 mode has 32KB data retention in SRAM bank0. (M48xID/M487KMCAN)
3. SPD0 mode data retension size is configurable. (M48xGC/M48xE8)
There are different power mode entry setting For each power mode, they have different entry setting
and leaving condition. Table 6.2-3 shows the entry setting for each power mode. When chip power-on,
chip is running ar normal mode. User can enter each mode by setting SLEEPDEEP (SCR[2]), PDEN
(CLK_PWRCT:[7]) and PDMSEL (CLK_PMUCTL[2:0]) and execute WFI instruction. And
Register/Instruction
SLEEPDEEP
PDEN
Mode
(SCR[2])
(CLK_PWRCTL[7]) (CLK_PMUCTL[2:0])
PDMSEL
CPU Run WFI Instruction
Normal mode
0
0
0
NO
Idle mode
0
0
0
YES
Fast Wakeup Power-down mode
1
1
2
YES
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M480
Normal Power-down mode
1
1
0
YES
Low leakage Power-down mode
1
1
1
YES
Standby Power-down mode 0
1
1
4
YES
Standby Power-down mode 1
1
1
5
YES
Deep Power-down mode*
1
1
6
YES
*M487KMCAN doesn’t support Deep Power-down mode (DPD)
Table 6.2-3 Power Mode Difference Table
There are several wake-up sources in Idle mode and Power-down mode. Table 6.2-4 lists the
available clocks for each power mode.
Power Mode
Normal Mode
Idle Mode
Power-Down Mode
Definition
CPU is in active state
CPU is in sleep state
CPU is in sleep state and all
clocks stop except LXT and
LIRC. SRAM content retended.
Entry Condition
Chip is in normal mode after
system reset released
CPU executes WFI instruction. CPU sets sleep mode enable
and power down enable and
executes WFI instruction.
Wake-up Sources
N/A
All interrupts
RTC, WDT, I²C, Timer, UART,
BOD, GPIO, EINT, USCI,
USBD, ACMP and BOD.
Available Clocks
All
All except CPU clock
LXT and LIRC
After Wake-up
N/A
CPU back to normal mode
CPU back to normal mode
Table 6.2-4 Power Mode Definition Table
Normal Mode
CPU Clock ON
HXT, HIRC, LXT, LIRC, HCLK, PCLK ON
Flash ON
CPU executes WFI
Interrupts occur
1. SLEEPDEEP(SCR[2]) = 1
2. PDEN(CLK_PWRCTL[7]) = 1
3. CPU executes WFI
Wake-up events occur
Power-down Mode
CPU Clock OFF
HXT, HIRC, PCLK OFF
LXT, LIRC ON
Flash Halt
Idle Mode
CPU Clock OFF
HXT, HIRC, PCLK ON
LXT, LIRC ON
Flash Halt
Figure 6.2-7 Power Mode State Machine
HXT
May 08, 2020
Idle Mode
NPD, LLPD, FWPD
SPD
DPD
ON
Halt
Halt
Halt
Page 331 of 523
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M480 SERIES DATASHEET
System reset released
M480
HIRC
ON
Halt
Halt
Halt
LXT
ON
ON/OFF1
ON/OFF1
ON/OFF1
LIRC
ON
ON/OFF2
ON/OFF2
ON/OFF2,8
PLL
ON
Halt
Halt
Halt
HCLK/PCLK
ON
Halt
Halt
Halt
CPU
Halt
Halt
Halt
Halt
SRAM retention
ON
ON
ON/OFF7
Halt
FLASH
ON
Halt
Halt
Halt
TIMER
ON
ON/OFF3
ON/OFF3
Halt
WDT
ON
ON/OFF
4
4
Halt
RTC
ON
ON/OFF5
ON/OFF5
ON/OFF5
UART
ON
ON/OFF6
ON/OFF6
Halt
Others
ON
Halt
Halt
Halt
ON/OFF
Table 6.2-5 Clocks in Power Modes
Note:
1. LXT ON or OFF depends on SW setting in normal mode.
2. LIRC ON or OFF depends on S/W setting in normal mode.
3. If TIMER clock source is selected as LIRC/LXT and LIRC/LXT is on.
4. If WDT clock source is selected as LIRC and LIRC is on.
5. If RTC clock source is selected as LXT and LXT is on.
M480 SERIES DATASHEET
6. If UART clock source is selected as LXT and LXT is on.
7. SRAM retention size depends on SW setting in normal mode.
8. If timer wake up function is disabled, LIRC will be disabled automatically when chip enter DPD
mode for power saving.
Wake-up sources in Normal Power-down mode (NPD):
RTC, WDT, I²C, Timer, UART, USCI, BOD, EBOD, GPIO, USBD, and ACMP.
After chip enters power down, the following wake-up sources can wake chip up to normal mode. Table
6.2-6 lists the condition about how to enter Power-down mode again for each peripheral.
User needs to wait this condition before setting PDEN(CLK_PWRCTL[7]) and execute WFI to enter
Power-down mode.
Power-Down Mode
Wake-Up
Source
Wake-Up Condition
NPD/
SPD
DPD
Re-Entering Power-Down Mode Condition
FWPD/
LLPD
BOD
Brown-Out Detector
Reset / Interrupt
V
-
-
After software writes 1 to clear BODIF
(SYS_BODCTL[4]).
Brown-Out Detector
-
V
-
After software writes 1 (CLK_PMUSTS[31]) to clear
BODWK (CLK_PMUSTS[13]) when SPD mode is
May 08, 2020
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M480
Reset
LVR
entered.
V
-
-
After software writes 1 to clear LVRF
(SYS_RSTSTS[3])
-
V
-
After software writes 1 (CLK_PMUSTS[31]) to clear
LVRWK (CLK_PMUSTS[12]) when SPD mode is
entered.
LVR Reset
POR
POR Reset
V
V
-
After software writes 1 to clear PORF
(SYS_RSTSTS[0])
INT
External Interrupt
V
-
-
After software write 1 to clear the Px_INTSRC[n] bit.
GPIO
GPIO Interrupt
V
-
-
After software write 1 to clear the Px_INTSRC[n] bit.
rising or falling edge
event, 64-pin
-
V
-
After software writes 1 (CLK_PMUSTS[31]) to clear
GPxWK (CLK_PMUSTS[11:8]) when SPD mode is
entered.
rising or falling edge
event , 1-pin
-
-
V
After software writes 1 (CLK_PMUSTS[31]) to clear
PINWK0 (CLK_PMUSTS[0]) when DPD mode is
entered. (M48xID Only)
GPIO(PA~PD)
Wake-up pin
GPIO(PC.0)
Wake-up pin
GPIO(PC.0/P
B.0/PB.2/PB.1
2/PF.6) Wakeup pin
-
-
V
After software writes 1 (CLK_PMUSTS[31]) to clear
PINWKx (CLK_PMUSTS[6:3] and CLK_PMUSTS[0])
when DPD mode is entered. (M48xGC/M48xE8
Only)
Timer Interrupt
V
-
-
After software writes 1 to clear TWKF
(TIMERx_INTSTS[1]) and TIF (TIMERx_INTSTS[0]).
Wakeup by wake-up
timer time-out
-
V
V
After software writes 1 (CLK_PMUSTS[31]) to clear
TMRWK (CLK_PMUSTS[1]) when SPD or DPD
mode is entered.
WDT Interrupt
V
-
-
After software writes 1 to clear WKF (WDT_CTL[5])
(Write Protect).
Alarm Interrupt
V
-
-
After software writes 1 to clear ALMIF
(RTC_INTSTS[0]).
Time Tick Interrupt
V
-
-
After software writes 1 to clear TICKIF
(RTC_INTSTS[1]).
TIMER
Wakeup timer
WDT
RTC
V
Wakeup by RTC alarm
-
V
After software writes 1 (CLK_PMUSTS[31]) to clear
(M48xGC/ RTCWK (CLK_PMUSTS[2]) when DPD or SPD
M48xE8) mode is entered.
V
Wakeup by RTC tick
time
-
V
After software writes 1 (CLK_PMUSTS[31]) to clear
(M48xGC/ RTCWK (CLK_PMUSTS[2]) when DPD or SPD
M48xE8) mode is entered.
Wakeup by tamper
event
-
V
V
After software writes 1 (CLK_PMUSTS[31]) to clear
(M48xGC/ RTCWK (CLK_PMUSTS[2]) when DPD or SPD
mode is entered.
M48xE8)
nCTS wake-up
V
-
-
After software writes 1 to clear CTSWKF
(UARTx_WKSTS[0]).
RX Data wake-up
V
-
-
After software writes 1 to clear DATWKF
(UARTx_WKSTS[1]).
Received FIFO
Threshold Wake-up
V
-
-
After software writes 1 to clear RFRTWKF
(UARTx_WKSTS[2]).
RS-485 AAD Mode
V
-
-
After software writes 1 to clear RS485WKF
UART
May 08, 2020
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M480 SERIES DATASHEET
rising or falling edge
event, 5-pin
M480
Wake-up
(UARTx_WKSTS[3]).
Received FIFO
Threshold Time-out
Wake-up
V
-
-
After software writes 1 to clear TOUTWKF
(UARTx_WKSTS[4]).
CTS Toggle
V
-
-
After software writes 1 to clear WKF
(UUART_WKSTS[0]).
Data Toggle
V
-
-
After software writes 1 to clear WKF
(UUART_WKSTS[0]).
Data toggle
V
-
-
After software writes 1 to clear WKF
(UI2C_WKSTS[0]).
Address match
V
-
-
After software writes 1 to clear WKAKDONE
(UI2C_PROTSTS[16], then writes 1 to clear WKF
(UI2C_WKSTS[0]).
SS Toggle
V
-
-
After software writes 1 to clear WKF
(USPI_WKSTS[0]).
Address match wake-up
V
-
-
After software writes 1 to clear WKAKDONE
(I2C_WKSTS[1]). Then software writes 1 to clear
WKIF(I2C_WKSTS[0]).
Remote Wake-up
V
-
-
After software writes 1 to clear BUSIF
(USBD_INTSTS[0]).
Comparator PowerDown Wake-Up Interrupt
V
-
-
After software writes 1 to clear WKIF0
(ACMP_STATUS[8]) and WKIF1
(ACMP_STATUS[9]).
ACMPO status change
-
V
-
After software writes 1 (CLK_PMUSTS[31]) to clear
ACMPWK (CLK_PMUSTS[14]) when SPD mode is
entered.
USCI UART
USCI I2C
USCI SPI
I2C
USBD
ACMP
ACMP
Table 6.2-6 Re-Entering Power-down Mode Condition
6.2.5
Power Modes and Power Level Transition
M480 SERIES DATASHEET
May 08, 2020
Page 334 of 523
Rev 3.00
M480
FWPD
LLPD
NPD
SPD
DPD
Wake-up reset
Wake-up reset
POR Reset
nReset pin
WDT reset
CHIP reset
LVR
BOD reset
Lockup reset
System reset
Power Level PL0
Power Level changing
Run mode
Power Level PL1
Power Level PL1
Idle mode
Power Level PL0
6.2.6
System Memory Map
®
The NuMicro M480 series provides 4G-byte addressing space. The memory locations assigned to
each on-chip controllers are shown in Table 6.2-7. The detailed register definition, memory space, and
®
programming will be described in the following sections for each on-chip peripheral. The NuMicro
M480 series only supports little-endian data format.
Address Space
Token
Controllers
Flash and SRAM Memory Space
0x0000_0000 – 0x0003_FFFF
FLASH_BA
FLASH Memory Space (256 Kbytes)
0x0000_0000 – 0x0007_FFFF
FLASH_BA
FLASH Memory Space (512 Kbytes)
0x0800_0000 – 0x09FF_FFFF
SPIM_BA
SPIM Memory Space (32 Mbytes) (M48xID)
0x0800_0000 – 0x081F_FFFF
SPIM_BA
Embedded SPI Flash Space(2 Mbytes) (M487KMCAN)
0x2000_0000 – 0x2000_7FFF
SRAM0_BA
SRAM Memory Space (32 Kbytes)
0x2000_8000 – 0x2001_FFFF
SRAM1_BA
SRAM Memory Space (96 Kbytes)
May 08, 2020
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Rev 3.00
M480 SERIES DATASHEET
®
Figure 6.2-8 NuMicro M480 Power Distribution Diagram
M480
0x2002_0000 – 0x2002_7FFF
SRAM2_BA
SRAM Memory Space (32 Kbytes) for CPU only and share with SPIM
cache
0x6000_0000 – 0x6FFF_FFFF
EXTMEM_BA
External Memory Space (256 Mbytes)
Peripheral Controllers Space (0x4000_0000 – 0x400F_FFFF)
M480 SERIES DATASHEET
0x4000_0000 – 0x4000_01FF
SYS_BA
System Control Registers
0x4000_0200 – 0x4000_02FF
CLK_BA
Clock Control Registers
0x4000_0300 – 0x4000_03FF
NMI_BA
NMI Control Registers
0x4000_4000 – 0x4000_4FFF
GPIO_BA
GPIO Control Registers
0x4000_7000 – 0x4000_7FFF
SPIM_BA
SPIM Control Registers
0x4000_8000 – 0x4000_8FFF
PDMA_BA
Peripheral DMA Control Registers
0x4000_9000 – 0x4000_9FFF
USBH_BA
USB Host Control Registers
0x4000_B000 – 0x4000_BFFF
EMAC_BA
Ethernet MAC Control Registers
0x4000_C000 – 0x4000_CFFF
FMC_BA
Flash Memory Control Registers
0x4000_D000 – 0x4000_DFFF
SDH0_BA
SDHOST0 Control Registers
0x4000_E000 – 0x4000_EFFF
SDH1_BA
SDHOST1 Control Registers
0x4001_0000 – 0x4001_0FFF
EBI_BA
External Bus Interface Control Registers
0x4001_9000 – 0x4001_9FFF
HSUSBD_BA
HSUSBD Control Registers
0x4001_A000 – 0x4001_AFFF
HSUSBH _BA
HSUSBH Host Control Registers
0x4003_0000 – 0x4003_0FFF
CCAP_BA
CCAP Control Registers
0x4003_1000 – 0x4003_1FFF
CRC_BA
CRC Generator Registers
0x4003_E000 – 0x4003_EFFF
SWDC_BA
SWD Control Registers
0x4003_F000 – 0x4003_FFFF
ETMC_BA
ETM Control Registers
0x5008_0000 – 0x5008_0FFF
CRYP_BA
Cryptographic Accelerator Registers
APB Controllers Space (0x4000_0000 ~ 0x400F_FFFF)
0x4004_0000 – 0x4004_0FFF
WDT_BA
Watchdog Timer Control Registers
0x4004_1000 – 0x4004_1FFF
RTC_BA
Real Time Clock (RTC) Control Register
0x4004_3000 – 0x4004_3FFF
EADC0_BA
Enhanced Analog-Digital-Converter 0 (EADC0) Control Registers
0x4004_5000 – 0x4004_5FFF
ACMP01_BA
Analog Comparator 0/ 1 Control Registers
0x4004_6000 – 0x4004_6FFF
OPA_BA
OP Amplifier Control Registers
0x4004_7000 – 0x4004_7FFF
DAC_BA
DAC Control Registers
0x4004_8000 – 0x4004_8FFF
I2S0_BA
I2S0 Interface Control Registers
0x4004_B000 – 0x4004_BFFF
EADC1_BA
Enhanced Analog-Digital-Converter 1 (EADC1) Control Registers
0x4004_D000 – 0x4004_DFFF
OTG_BA
OTG Control Registers
0x4004_F000 – 0x4004_FFFF
HSOTG_BA
HSOTG Control Registers
0x4005_0000 – 0x4005_0FFF
TMR01_BA
Timer0/Timer1 Control Registers
0x4005_1000 – 0x4005_1FFF
TMR23_BA
Timer2/Timer3 Control Registers
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M480
0x4005_8000 – 0x4005_8FFF
EPWM0_BA
EPWM0 Control Registers
0x4005_9000 – 0x4005_9FFF
EPWM1_BA
EPWM1 Control Registers
0x4005_A000 – 0x4005_AFFF
BPWM0_BA
BPWM0 Control Registers
0x4005_B000 – 0x4005_BFFF
BPWM1_BA
BPWM1 Control Registers
0x4006_0000 – 0x4006_0FFF
QSPI0_BA
QSPI0 Control Registers
0x4006_1000 – 0x4006_1FFF
SPI0_BA
SPI0 Control Registers
0x4006_2000 – 0x4006_2FFF
SPI1_BA
SPI1 Control Registers
0x4006_3000 – 0x4006_3FFF
SPI2_BA
SPI2 Control Registers
0x4006_4000 – 0x4006_4FFF
SPI3_BA
SPI3 Control Registers
0x4006_9000 – 0x4006_9FFF
QSPI1_BA
QSPI1 Control Registers
0x4007_0000 – 0x4007_0FFF
UART0_BA
UART0 Control Registers
0x4007_1000 – 0x4007_1FFF
UART1_BA
UART1 Control Registers
0x4007_2000 – 0x4007_2FFF
UART2_BA
UART2 Control Registers
0x4007_3000 – 0x4007_3FFF
UART3_BA
UART3 Control Registers
0x4007_4000 – 0x4007_4FFF
UART4_BA
UART4 Control Registers
0x4007_5000 – 0x4007_5FFF
UART5_BA
UART5 Control Registers
0x4007_6000 – 0x4007_6FFF
UART6_BA
UART6 Control Registers
0x4007_7000 – 0x4007_7FFF
UART7_BA
UART7 Control Registers
I C0_BA
I2C0 Control Registers
0x4008_1000 – 0x4008_1FFF
I2C1_BA
I2C1 Control Registers
0x4008_2000 – 0x4008_2FFF
I2C2_BA
I2C2 Control Registers
0x4009_0000 – 0x4009_0FFF
SC0_BA
Smartcard Host 0 Control Registers
0x4009_1000 – 0x4009_1FFF
SC1_BA
Smartcard Host 1 Control Registers
0x4009_2000 – 0x4009_2FFF
SC2_BA
Smartcard Host 2 Control Registers
0x4009_3000 – 0x4009_3FFF
SC3_BA
Smartcard Host 3 Control Registers
0x400A_0000 – 0x400A_0FFF
CAN0_BA
CAN0 Bus Control Registers
0x400A_1000 – 0x400A_1FFF
CAN1_BA
CAN1 Bus Control Registers
0x400A_2000 – 0x400A_2FFF
CAN2_BA
CAN2 Bus Control Registers
0x400B_0000 – 0x400B_0FFF
QEI0_BA
QEI0 Control Registers
0x400B_1000 – 0x400B_1FFF
QEI1_BA
QEI1 Control Registers
0x400B_4000 – 0x400B_4FFF
ECAP0_BA
ECAP0 Control Registers
0x400B_5000 – 0x400B_5FFF
ECAP1_BA
ECAP1 Control Registers
0x400B_9000 – 0x400B_9FFF
TRNG_BA
TRNG Control Registers
0x400C_0000 – 0x400C_0FFF
USBD_BA
USB Device Control Register
0x400D_0000 – 0x400D_0FFF
USCI0_BA
USCI0 Control Registers
Page 337 of 523
M480 SERIES DATASHEET
0x4008_0000 – 0x4008_0FFF
May 08, 2020
2
Rev 3.00
M480
0x400D_1000 – 0x400D_1FFF
USCI1_BA
USCI1 Control Registers
System Controllers Space (0xE000_E000 ~ 0xE000_EFFF)
0xE000_E010 – 0xE000_E0FF
SCS_BA
System Timer Control Registers
0xE000_E100 – 0xE000_ECFF
SCS_BA
External Interrupt Controller Control Registers
0xE000_ED00 – 0xE000_ED8F
SCS_BA
System Control Registers
Table 6.2-7 Address Space Assignments for On-Chip Controllers
6.2.7
SRAM Memory Orginization
The M480 series supports embedded SRAM with total 160 Kbytes size and the SRAM organization is
separated to three banks: SRAM bank0 and SRAM bank1 and SRAM bank2. The first bank has 32
Kbytes address space, the second bank has 96 Kbyte address space and the third bank has 32Kbyte.
These three banks address space can be accessed simultaneously. The SRAM bank0 supports parity
error check to make sure chip operating more stable. The SRAM bank2 is shared with SPIM cache, it
can switch to external SPI Flash cache memory. Note that SRAM bank2 has additional two wait cycles
when reading data.
Supports total 160 Kbytes SRAM
Supports byte / half word / word write
Supports fixed 32 Kbytes SRAM bank0 for independent access
Supports parity error check function for SRAM bank0
Supports oversize response error
Supports remap address to 0x1000_0000
M480 SERIES DATASHEET
AHB Bus
AHB interface
controller
SRAM decoder
SRAM bank0
AHB interface
controller
SRAM decoder
SRAM bank1
AHB interface
controller
SRAM decoder
SRAM bank2
Figure 6.2-9 SRAM Block Diagram
Figure 6.2-9 shows the SRAM organization of M480. There are three SRAM banks in M480. The
bank0 is addressed to 32 Kbytes, the bank1 is addressed to 96 Kbytes and the bank2 is addressed to
32 Kbyte. The bank0 address space is from 0x2000_0000 to 0x2000_7FFF. The bank1 address space
is from 0x2000_8000 to 0x2001_FFFF. The bank2 address space is from 0x2002_0000 to
0x2002_7FFF. The address between 0x2002_8000 to 0x3FFF_FFFF is illegal memory space and chip
will enter hardfault if CPU accesses these illegal memory addresses.
160 Kbytes Device
May 08, 2020
128 Kbytes Device
Page 338 of 523
64KB Device
Read Access
Rev 3.00
M480
SRAM bank0
0x2000_0000
0x2000_7FFF
0x1000_0000
0x1000_7FFF
~ 0x2000_0000
or 0x2000_7FFF
~ 0x1000_0000
0x1000_7FFF
~ 0x2000_0000
or 0x2000_7FFF
~ 0x1000_0000
0x1000_7FFF
~ Zero wait cycle
or continuous access
~
for
SRAM bank1
0x2000_8000
0x2001_FFFF
0x1000_8000
0x1001_FFFF
~ 0x2000_8000
or 0x2001_FFFF
~ 0x1000_8000
0x1001_FFFF
~ 0x2000_8000
or 0x2000_FFFF
~ 0x1000_8000
0x1000_FFFF
~ Zero wait cycle
or continuous access
~
for
SRAM bank2
0x2002_0000
0x2002_7FFF
0x1002_0000
0x1002_7FFF
~
or
~
Two wait cycles
Table 6.2-8 SRAM Organization
The address of each bank is remapping from 0x2000_0000 to 0x1000_0000. CPU can access SRAM
bank0 through 0x2000_0000 to 0x2000_7FFF or 0x1000_0000 to 0x1000_7FFF, and access SRAM
bank1 through 0x2000_8000 to 0x2001_FFFF or 0x1000_8000 to 0x1001_FFFF, and access SRAM
bank2 through 0x2002_0000 to 0x2002_7FFF or 0x1002_0000 to 0x1002_7FFF.
When setting the control register CCMEN(SPIM_CTL1[2]) to 0, SRAM bank2 is switched to external
SPI Flash cache memory. In this case, the SRAM bank2 can’t be accessed as gernal SRAM. If user
access SRAM bank2 by AHB bus master, the SPI Flash controller will send error response via HRESP
AHB bus signal to bus master.
M480 SERIES DATASHEET
May 08, 2020
Page 339 of 523
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M480
0x3FFF_FFFF
Reserved
0x2002_8000
0x2002_7FFF
0x1002_7FFF
512MB
32K byte
SRAM bank2
32K byte
SRAM bank2
remapping
0x2002_0000
0x1002_0000
0x2001_FFFF
0x1001_FFFF
96K byte
SRAM bank1
remapping
96K byte
SRAM bank1
0x2000_8000
0x1000_8000
0x2000_7FFF
0x1000_7FFF
32K byte
SRAM bank0
M480 SERIES DATASHEET
0x2000_0000
remapping
32K byte
SRAM bank0
0x1000_0000
160K byte device
160K byte device
Figure 6.2-10 SRAM Memory Organization
SRAM bank0 has byte parity error check function. When CPU is accessing SRAM bank0, the parity
error checking mechanism is dynamic operating. As parity error occured, the PERRIF
(SYS_SRAM_STATUS[0]) will be asserted to 1 and the SYS_SRAM_ERRADDR register will recode
the address with parity error. Chip will enter interrupt when SRAM parity error occurred if PERRIEN
(SYS_SRAM_INTCTL[0]) is set to 1. When SRAM parity error occured, chip will stop detecting SRAM
parity error until user writes 1 to clear the PERRIF(SYS_SRAM_STATUS[0]) bit.
May 08, 2020
Page 340 of 523
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M480
6.2.8
Bus Matrix
The M480 supports Bus Matrix to manage the access arbitration between masters. The access
arbitration can be selected by INTACTEN (SYS_AHBMCTL[0]) to use round-robin algorithm or set
®
Cortex -M4 CPU as the highest bus priority.
USBH
Crypto
M5
M4
SDIO0
PDMA
M4-SBUS
M4-DBUS
M4-IBUS
M3
M2
M1
M0
S0
S1
S2
FLASH
SRAM1
(32K)
SRAM2
(96K)
S3
APB1
S4
APB2
S5
EBI
S6
AHB
(ctrl)
®
Figure 6.2-11 NuMicro M480 Bus Matrix Diagram
6.2.9
HIRC Auto Trim
For instance, the system needs an accurate 12 MHz clock. In such case, if neither using use PLL as
the system clock source nor soldering 32.768 kHz crystal in system, user has to set REFCKSEL
(SYS_IRCTCTL[10] reference clock selection) to “1”, set FREQSEL (SYS_IRCTCTL[1:0] trim
frequency selection) to “01”, and the auto-trim function will be enabled. Interrupt status bit FREQLOCK
(SYS_IRCTISTS[8] HIRC frequency lock status) “1” indicates the HIRC output frequency is accurate
within 0.25% deviation.
In HIRC case, the system needs an accurate 48 MHz clock. In such case, if neither using use PLL as
the system clock source nor soldering 32.768 kHz crystal in system, user has to set REFCKSEL
(SYS_HIRCTCTL[10] reference clock selection) to “1”, set FREQSEL (SYS_HIRCTCTL[1:0] trim
frequency selection) to “10”, and the auto-trim function will be enabled. Interrupt status bit FREQLOCK
(SYS_HIRCTSTS[8] HIRC frequency lock status) “1” indicates the HIRC output frequency is accurate
within 0.25% deviation.
May 08, 2020
Page 341 of 523
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M480 SERIES DATASHEET
This chip supports auto-trim function: the HIRC trim (12 MHz RC oscillator) and HIRC trim (48 MHz
RC oscillator,), according to the accurate LXT (32.768 kHz crystal oscillator) or internal USB
synchronous mode, automatically gets accurate HIRC output frequency, 0.25 % deviation within all
temperature ranges.
M480
6.2.10 Register Lock Control
Some of the system control registers need to be protected to avoid inadvertent write and disturb the
chip operation. These system control registers are protected after the power-on reset till user to
disable register protection. For user to program these protected registers, a register protection disable
sequence needs to be followed by a special programming. The register protection disable sequence is
writing the data “59h”, “16h” “88h” to the register SYS_REGLCTL address at 0x4000_0100
continuously. Any different data value, different sequence or any other write to other address during
these three data writing will abort the whole sequence.
M480 SERIES DATASHEET
SYS_IPRST0
Address 0x4000_0008
SYS_BODCTL
address 0x4000_0018
SYS_VREFCTL
address 0x4000_0028
SYS_USBPHY
address 0x4000_002C
SYS_SRAM_BISTCTL
address 0x4000_00D0
SYS_PORDISAN
address 0x4000_01EC
SYS_PLCTL
address 0x4000_01F8
CLK_PWRCTL
address 0x4000_0200
CLK_APBCLK0
address 0x4000_0208
CLK_CLKSEL0
address 0x4000_0210
CLK_CLKSEL1
address 0x4000_0214
CLK_PLLCTL
address 0x4000_0240
CLK_PMUCTL
address 0x4000_0290
NMIEN
address 0x4000_0300
AHBMCTL
address 0x4000_0400
FMC_FTCTL
address 0x4000_5018
FMC_ICPCMD
address 0x4000_501C
FMC_ISPCTL
address 0x4000_C000
FMC_ISPTRG
address 0x4000_C010
FMC_ISPSTS
address 0x4000_C040
FMC_CYCCTL
address 0x4000_C04C
FMC_KPKEYTRG
address 0x4000_C05C
FMC_KPKEYSTS
address 0x4000_C060
WDT_CTL
address 0x4004_0000
WDT_ALTCTL
address 0x4004_0004
TIMER0_CTL
address 0x4005_0000
TIMER1_CTL
address 0x4005_0100
TIMER2_CTL
address 0x4005_1000
TIMER3_CTL
address 0x4005_1100
May 08, 2020
Page 342 of 523
Rev 3.00
M480
address 0x4005_0040
TIMER1_PWMCTL
address 0x4005_0140
TIMER2_PWMCTL
address 0x4005_1040
TIMER3_PWMCTL
address 0x4005_1140
TIMER0_PWMDTCTL
address 0x4005_0058
TIMER1_PWMDTCTL
address 0x4005_0158
TIMER2_PWMDTCTL
address 0x4005_1058
TIMER3_PWMDTCTL
address 0x4005_1158
TIMER0_PWMBRKCTL
address 0x4005_0070
TIMER1_PWMBRKCTL
address 0x4005_0170
TIMER2_PWMBRKCTL
address 0x4005_1070
TIMER3_PWMBRKCTL
address 0x4005_1170
TIMER0_PWMSWBRK
address 0x4005_007C
TIMER1_PWMSWBRK
address 0x4005_017C
TIMER2_PWMSWBRK
address 0x4005_107C
TIMER3_PWMSWBRK
address 0x4005_117C
TIMER0_PWMINTEN1
address 0x4005_0084
TIMER1_PWMINTEN1
address 0x4005_0184
TIMER2_PWMINTEN1
address 0x4005_1084
TIMER3_PWMINTEN1
address 0x4005_1184
TIMER0_PWMINTSTS1
address 0x4005_008C
TIMER1_PWMINTSTS1
address 0x4005_018C
TIMER2_PWMINTSTS1
address 0x4005_108C
TIMER3_PWMINTSTS1
address 0x4005_118C
EPWM_CTL0
address 0x4005_8000/0x4005_9000
EPWM_CTL1
address 0x4005_8000/0x4005_9000
EPWM_DTCTL0_1
address 0x4005_8070/0x4005_9070
EPWM_DTCTL2_3
address 0x4005_8074/0x4005_9074
EPWM_DTCTL4_5
address 0x4005_8078/0x4005_9078
EPWM_BRKCTL0_1
address 0x4005_80C8/0x4005_90C8
EPWM_BRKCTL2_3
address 0x4005_80CC/0x4005_90CC
EPWM_BRKCTL4_5
address 0x4005_80D0/0x4005_90D0
EPWM_SWBRK
address 0x4005_80DC/0x4005_90DC
EPWM_INTEN1
address 0x4005_80E4/0x4005_90E4
EPWM_INTSTS1
address 0x4005_80EC/0x4005_90EC
May 08, 2020
Page 343 of 523
M480 SERIES DATASHEET
TIMER0_PWMCTL
Rev 3.00
M480
address 0x4005_A000/0x4005_B000
SYST_VAL
address 0xE000_E018
May 08, 2020
Page 344 of 523
M480 SERIES DATASHEET
BPWM_CTL0
Rev 3.00
M480
6.2.11 System Timer (SysTick)
®
The Cortex -M4 includes an integrated system timer, SysTick, which provides a simple, 24-bit clearon-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be
used as a Real Time Operating System (RTOS) tick timer or as a simple counter.
When system timer is enabled, it will count down from the value in the SysTick Current Value Register
(SYST_VAL) to zero, and reload (wrap) to the value in the SysTick Reload Value Register
(SYST_LOAD) on the next clock cycle, and then decrement on subsequent clocks. When the counter
transitions to zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads.
The SYST_VAL value is UNKNOWN on reset. Software should write to the register to clear it to zero
before enabling the feature. This ensures the timer will count from the SYST_LOAD value rather than
an arbitrary value when it is enabled.
If the SYST_LOAD is zero, the timer will be maintained with a current value of zero after it is reloaded
with this value. This mechanism can be used to disable the feature independently from the timer
enable bit.
®
®
For more detailed information, please refer to the “Arm Cortex -M4 Technical Reference Manual” and
®
“Arm v6-M Architecture Reference Manual”.
M480 SERIES DATASHEET
May 08, 2020
Page 345 of 523
Rev 3.00
M480
6.2.12 Nested Vectored Interrupt Controller (NVIC)
The NVIC and the processor core interface are closely coupled to enable low latency interrupt
processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge of the
stacked, or nested, interrupts to enable tail-chaining of interrupts. You can only fully access the NVIC
from privileged mode, but you can cause interrupts to enter a pending state in user mode if you enable
the Configuration and Control Register. Any other user mode access causes a bus fault. You can
access all NVIC registers using byte, halfword, and word accesses unless otherwise stated. NVIC
registers are located within the SCS (System Control Space). All NVIC registers and system debug
registers are little-endian regardless of the endianness state of the processor.
The NVIC supports:
An implementation-defined number of interrupts, in the range 1-240 interrupts.
A programmable priority level of 0-16 for each interrupt; a higher level corresponds to a
lower priority, so level 0 is the highest interrupt priority.
Level and pulse detection of interrupt signals.
Dynamic reprioritization of interrupts.
Grouping of priority values into group priority and subpriority fields.
Interrupt tail-chaining.
An external Non Maskable Interrupt (NMI)
WIC with Ultra-low Power Sleep mode support
The processor automatically stacks its state on exception entry and unstacks this state on exception
exit, with no instruction overhead. This provides low latency exception handling.
M480 SERIES DATASHEET
May 08, 2020
Page 346 of 523
Rev 3.00
M480
6.3 Clock Controller
6.3.1
Overview
The clock controller generates clocks for the whole chip, including system clocks and all peripheral
clocks. The clock controller also implements the power control function with the individually clock
ON/OFF control, clock source selection and a clock divider. The chip will not enter Power-down mode
®
until CPU sets the Power-down enable bit PDEN(CLK_PWRCTL[7]) and Cortex -M4F core executes
the WFI instruction. After that, chip enters Power-down mode and wait for wake-up interrupt source
triggered to leave Power-down mode. In Power-down mode, the clock controller turns off the 4~24
MHz external high speed crystal (HXT) and 12 MHz internal high speed RC oscillator (HIRC) to
reduce the overall system power consumption.Figure 6.3-1 shows the clock generator and the
overview of the clock source control.
M480 SERIES DATASHEET
May 08, 2020
Page 347 of 523
Rev 3.00
M480
ACMP
BPWM0
HIRC
12MHz
HXT
4~24MHz
LXT
32.768 kHz
LIRC
10 kHz
EADC
ECAP0
BPWM1
CRC
I2C0
EBI
HIRC
1
PLLFOUT
PLL FOUT
HXT
EMC
0
CLK_PLLCTL[19]
HIRC
111
LIRC
HXT
PCLK0
CAN1
I2C2
DAC
PCLK1
I2S
ECAP1
I2C1
FMC
OPA
PDMA
EPWM0
OTG
SD0
QEI0
HSOTG
SD1
SC0
EPWM1
CRYP
SC2
QEI1
RTC
SPIM
QSPI0
SPI1
SC1
001
HSUSBD
SPI3
SPI0
000
HSUSBH
TMR0
SPI2
USBH
TMR1
TMR2
UR0
TMR3
UR2
UR1
010
LXT
/1,/2,/4,/8,/16
SRAM
011
PLLFOUT
HCLK
1/(HCLKDIV+1)
CLK_CLKSEL0[2:0]
MDCCLK
HCLK
CAN0
CPU
1/(EMACDIV+1)
REFCLK
1/2
1/20
Ethernet
RX_CLK
TX_CLK
UR3
UR4
EMC
USBD
UR5
USCI0
USCI1
WDG
LIRC
HCLK
11
1/2048
10
LXT
01
/1,/2,/4,/8,/16
WDT
CLK_CLKSEL1[1:0]
HIRC
11
LXT
LIRC
11
WWDT
HCLK
1/2048
HIRC
HCLK
1/2
111
1/2
011
1/2
010
01
HXT
10
00
CLK_CLKSEL1[25:24]
CLK_CLKSEL1[27:26]
CLK_CLKSEL3[25:24]
CLK_CLKSEL3[27:26]
CLK_CLKSEL3[29:28]
CLK_CLKSEL3[31:30]
CLK_CLKSEL1[31:30]
CPUCLK
UART0
UART1
UART2
UART3
UART4
UART5
1/(UART0DIV+1)
1/(UART1DIV+1)
1/(UART2DIV+1)
1/(UART3DIV+1)
1/(UART4DIV+1)
1/(UART5DIV+1)
10
PLLFOUT
1
SysTick
HXT
LXT
001
HXT
0
USB2.0 OTG
Controller
SYST_CTRL[2]
HXT
USB2.0 OTG
PHY
000
USB2.0 Device
Controller
30MHz
USB2.0 Host
Controller
CLK_CLKSEL0[5:3]
HIRC
USB1.1 Host
Controller
11
PLLFOUT
HCLK
10
PLLFOUT
HXT
1/(SDH0DIV+1)
1/(SDH1DIV+1)
01
/(USBDIV + 1)
SD0
SD1
USB1.1 OTG
Controller
00
CLK_CLKSEL0[21:20]
CLK_CLKSEL0[23:22]
DIV1EN
(CLK_CLKOCTL[5])
HIRC
PCLK1
USB1.1 Device
Controller
48MHz
1/(EADCDIV+1)
EADC
11
HCLK
10
LXT
LIRC
LXT
M480 SERIES DATASHEET
PCLK0
PLLFOUT
HXT
0
PCLK0
PLLFOUT
HXT
0
1
LIRC
10
0
1 Hz clock from RTC
/32768
LXT
11
1
RTCSEL(CLK_CLKSEL3[8])
I2S0
01
00
HIRC
PCLK1
11
10
01
PLLFOUT
QSPI0
SPI1
SPI3
HXT
PCLK1
PCLK0
1
0
PLLFOUT
EPWM 0
BPWM 0
PCLK0
PLLFOUT
HXT
HIRC
11
10
01
1/(SC0DIV+1)
1/(SC2DIV+1)
PCLK0
SC0
SC2
PLLFOUT
HXT
00
HIRC
LIRC
LXT
HXT
HIRC
111
LIRC
101
011
PCLK0
01
SPI0
SPI2
00
1
0
EPWM 1
BPWM 1
11
10
1/(SC1DIV+1)
SC1
01
00
CLK_CLKSEL3[3:2]
CLK_CLKSEL3[1:0]
CLK_CLKSEL3[5:4]
TM0/TM1
10
CLK_CLKSEL2[1]
CLK_CLKSEL2[9]
CLK_CLKSEL2[0]
CLK_CLKSEL2[8]
HIRC
11
CLK_CLKSEL2[5:4]
CLK_CLKSEL2[11:10]
00
CLK_CLKSEL2[3:2]
CLK_CLKSEL2[7:6]
CLK_CLKSEL2[13:12]
PLLFOUT
CLKO
1
CLK_CLKSEL1[29:28]
CLK_CLKSEL3[17:16]
HIRC
0
00
RTC
CLK_CLKSEL3[8]
HIRC
CLK1HZEN
(CLK_CLKOCTL[6])
01
HXT
1
/2(CLK_CLKOCTL[3:0]+1)
010
PCLK1
LXT
001
HXT
000
101
011
TM2/TM3
TMR0
TMR1
111
010
TMR2
TMR3
001
000
CLK_CLKSEL1 [18:16]
CLK_CLKSEL1[22:20]
CLK_CLKSEL1 [10:8]
CLK_CLKSEL1[14:12]
Note: For USB High-speed application, HXT should be 12 MHz.
Figure 6.3-1 Clock Generator Global View Diagram (M48xID/M487KMCAN)
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M480
BPWM0
HIRC
12MHz
HXT
4~24MHz
LXT
32.768 kHz
LIRC
10 kHz
HIRC48M
48MHz
EADC
CAN2
EADC1
CRC
I2C0
EBI
HIRC
1
PLLFOUT
PLL FOUT
HXT
/1,/2,/4,/8,/16
FMC
0
CLK_PLLCTL[19]
111
LIRC
LXT
HXT
1/(HCLKDIV+1)
010
HCLK
ECAP0
SD0
EPWM0
CRYP
QEI0
OTG
SC0
EPWM1
ECAP1
I2C1
QSPI0
CCAP
QEI1
SPI1
RTC
TMR0
QSPI1
001
TMR1
000
UR0
SPI2
UR2
TMR2
LIRC
11
1/2048
10
LXT
01
WDT
SPI0
UR4
TMR3
UR6
TRNG
USBD
UR1
WDG
UR3
UR5
UR7
CLK_CLKSEL1[1:0]
LIRC
DAC
PDMA
CLK_CLKSEL0[2:0]
HCLK
CAN1
PCLK1
I2S
USBH
011
PLLFOUT
BPWM1
I2C2
PCLK0
SRAM
HIRC
ACMP
CAN0
CPU
/1,/2,/4,/8,/16
11
WWDT
HCLK
1/2048
10
HIRC
CLK_CLKSEL1[31:30]
11
LXT
10
PLLFOUT
HIRC
HCLK
1/2
111
1/2
011
HXT
CPUCLK
1/2
010
LXT
001
HXT
0
SYST_CTRL[2]
000
CLK_CLKSEL0[5:3]
HIRC
00
CLK_CLKSEL1[25:24]
CLK_CLKSEL1[27:26]
CLK_CLKSEL3[21:20]
CLK_CLKSEL3[23:22]
CLK_CLKSEL3[25:24]
CLK_CLKSEL3[27:26]
CLK_CLKSEL3[29:28]
CLK_CLKSEL3[31:30]
1
SysTick
HXT
UART0
UART1
UART2
UART3
UART4
UART5
1/(UART0DIV+1)
1/(UART1DIV+1)
1/(UART2DIV+1)
1/(UART3DIV+1)
1/(UART4DIV+1)
1/(UART5DIV+1)
1/(UART6DIV+1)
1/(UART7DIV+1)
01
UART6
UART7
11
HCLK
10
PLLFOUT
HXT
1/(SDH0DIV+1)
SD0
USB1.1 Host
Controller
01
00
HIRC48M
48MHz
HIRC48M
0
/(USBDIV + 1)
PLLFOUT
CLK_CLKSEL0[21:20]
48MHz
USB1.1 Device
Controller
1
USBSEL(CLK_CLKSEL0[8])
PCLK1
PCLK1
1/(EADCDIV+1)
EADC
1/(EADC1DIV+1)
EADC1
DIV1EN
(CLK_CLKOCTL[5])
HIRC
11
HCLK
10
LXT
LIRC
LXT
PLLFOUT
HXT
0
PCLK0
PLLFOUT
HXT
0
1
LIRC
LXT
11
10
0
1 Hz clock from RTC
/32768
1
RTCSEL(CLK_CLKSEL3[8])
1/(I2S0DIV+1)
I2S0
01
00
HIRC
PCLK1
11
10
01
PLLFOUT
QSPI0
SPI1
HXT
00
PCLK1
PCLK0
1
0
PLLFOUT
EPWM 0
BPWM 0
PCLK0
PLLFOUT
HXT
HIRC
11
LIRC
10
10
QSPI1
01
SPI0
SPI2
00
1/(SC0DIV+1)
01
SC0
0
EPWM 1
BPWM 1
111
101
011
TM2/TM3
PCLK1
00
1
CLK_CLKSEL2[1]
CLK_CLKSEL2[9]
CLK_CLKSEL2[0]
CLK_CLKSEL2[8]
HIRC
11
CLK_CLKSEL2[5:4]
CLK_CLKSEL2[11:10]
CLK_CLKSEL3[13:12]
CLK_CLKSEL2[3:2]
CLK_CLKSEL2[7:6]
PLLFOUT
CLKO
1
CLK_CLKSEL1[29:28]
CLK_CLKSEL3[17:16]
HIRC
0
00
M480 SERIES DATASHEET
PCLK0
CLK1HZEN
(CLK_CLKOCTL[6])
RTC
CLK_CLKSEL3[8]
HIRC
/2(CLK_CLKOCTL[3:0]+1)
01
HXT
1
USB1.1 OTG
Controller
LXT
HXT
CLK_CLKSEL3[1:0]
010
TMR2
TMR3
001
000
CLK_CLKSEL1 [18:16]
CLK_CLKSEL1[22:20]
HIRC
LIRC
TM0/TM1
111
LXT
HXT
CLK_CLKSEL1 [10:8]
CLK_CLKSEL1[14:12]
HIRC
101
011
PCLK0
010
001
TMR0
TMR1
HCLK
PLLFOUT
HXT
000
11
10
1/(CCAPDIV+1)
CCAP
1/(VSENSEDIV+1)
CCAP_SCLK
01
00
CLK_CLKSEL0[17:16]
Figure 6.3-2 Clock Generator Global View Diagram (M48xGC/M48xE8)
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M480
6.3.2
Clock Generator
The clock generator consists of 5 clock sources, which are listed below:
32.768 kHz external low speed crystal oscillator (LXT)
4~24 MHz external high speed crystal oscillator (HXT)
Programmable PLL output clock frequency (PLLFOUT), PLL source can be selected from
external 4~24 MHz external high speed crystal (HXT) or 12 MHz internal high speed
oscillator (HIRC)
12 MHz internal high speed RC oscillator (HIRC)
10 kHz internal low speed RC oscillator (LIRC)
LXTEN (CLK_PWRCTL[1])
X32_IN
External 32.768
kHz Crystal
(LXT)
LXT
X32_OUT
HXTEN (CLK_PWRCTL[0])
HXT
XT1_IN
External 4~24
MHz Crystal
(HXT)
XT1_OUT
PLLSRC (CLK_PLLCTL[19])
0
HIRCEN (CLK_PWRCTL[2])
PLL
PLL FOUT
1
M480 SERIES DATASHEET
Internal 12 MHz
Oscillator
(HIRC)
HIRC
LIRCEN (CLK_PWRCTL[3])
Internal 10 kHz
Oscillator
(LIRC)
LIRC
Figure 6.3-3 Clock Generator Block Diagram
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6.3.3
System Clock and SysTick Clock
The system clock has 5 clock sources, which were generated from clock generator block. The clock
source switch depends on the register HCLKSEL (CLK_CLKSEL0[2:0]). The block diagram is shown
in Figure 6.3-4.
HCLKSEL
(CLK_CLKSEL0[2:0])
HIRC
LIRC
PLLFOUT
LXT
HXT
111
CPUCLK
011
1/(HCLK_N+1)
1/(HCLKDIV+1)
HCLKDIV
(CLK_CLKDIV0[3:0])
010
001
000
CPU in Power Down Mode
HCLK
PCLK0
PCLK1
CPU
AHB
APB0
APB1
Figure 6.3-4 System Clock Block Diagrams
There are two clock fail detectors to observe HXT and LXT clock source and they have individual
enable and interrupt control. When HXT detector is enabled, the HIRC clock is enabled automatically.
When LXT detector is enabled, the LIRC clock is enabled automatically.
Figure 6.3-5 shows The HXT clock stops detection and system clock switches to HIRC procedure
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M480 SERIES DATASHEET
When HXT clock detector is enabled, the system clock will auto switch to HIRC if HXT clock stop
being detected on the following condition: system clock source comes from HXT or system clock
source comes from PLL with HXT as the input of PLL. If HXT clock stop condition is detected, the
HXTFIF (CLK_CLKDSTS[0]) is set to 1 and chip will enter interrupt if HXTFIE (CLK_CLKDCTL[5]) is
set to 1. User can trying to recover HXT by disable HXT and enable HXT again to check if the clock
stable bit is set to 1 or not. If HXT clock stable bit is set to 1, it means HXT is recover to oscillate after
re-enable action and user can switch system clock to HXT again.
M480
Set HXTFDEN To enable
HXT clock detector
NO
HXTFIF = 1?
YES
System clock source =
“HXT” or “PLL with
HXT” ?
System clock keep
original clock
NO
YES
Switch system clock to
HIRC
Figure 6.3-5 HXT Stop Protect Procedure
®
M480 SERIES DATASHEET
The clock source of SysTick in Cortex -M4F core can use CPU clock or external clock
(SYST_CTRL[2]). If using external clock, the SysTick clock (STCLK) has 5 clock sources. The clock
source switch depends on the setting of the register STCLKSEL (CLK_CLKSEL0[5:3]). The block
diagram is shown in Figure 6.3-6.
STCLKSEL
(CLK_CLKSEL0[5:3])
HIRC
HCLK
HXT
LXT
HXT
1/2
111
1/2
011
1/2
010
STCLK
001
000
Figure 6.3-6 SysTick Clock Control Block Diagram
6.3.4
Peripherals Clock
Each peripheral clock has its own clock source selection. Refer to the CLK_CLKSEL1, CLK_CLKSEL2
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M480
and CLK_CLKSEL3 register.
6.3.5
Power-down Mode Clock
When entering Power-down mode, system clocks, some clock sources and some peripheral clocks
are disabled. Some clock sources and peripherals clock are still active in Power-down mode.
For theses clocks, which still keep active, are listed below:
6.3.6
Clock Generator
–
10 kHz internal low speed RC oscillator (LIRC) clock
–
32.768 kHz external low speed crystal oscillator (LXT) clock
Peripherals Clock (When the modules adopt LXT or LIRC as clock source)
Clock Output
This device is equipped with a power-of-2 frequency divider which is composed of 16 chained divideby-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one multiplexer is
reflected to CLKO function pin. Therefore there are 16 options of power-of-2 divided clocks with the
1
16
frequency from Fin/2 to Fin/2 where Fin is input clock frequency to the clock divider.
(N+1)
The output formula is Fout = Fin/2
, where Fin is the input clock frequency, Fout is the clock divider
output frequency and N is the 4-bit value in FREQSEL (CLK_CLKOCTL[3:0]).
When writing 1 to CLKOEN (CLK_CLKOCTL[4]), the chained counter starts to count. When writing 0
to CLKOEN (CLK_CLKOCTL[4]), the chained counter continuously runs till divided clock reaches low
state and stays in low state.
CLKOEN
(CLK_CLKOCTL[4])
Enable
divide-by-2 counter
1/2
HCLK
LXT
HXT
1/23
…...
1/215
DIV1EN
(CLK_CLKOCTL[5])
1/216
0000
0001
:
:
1110
1111
11
10
CLK1HZEN
(CLK_CLKOCTL[6])
16 to 1
MUX
0
0
1
CLKO
1
01
00
RTCSEL(CLK_CLKSEL3[8])
CLKOSEL (CLK_CLKSEL1[29:28])
LIRC
0
/32768
LXT
1 Hz clock from RTC
1
Figure 6.3-7 Clock Output Block Diagram
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M480 SERIES DATASHEET
HIRC
1/22
FREQSEL
(CLK_CLKOCTL[3:0])
16 chained
divide-by-2 counter
M480
6.3.7
USB Clock Source
The clock sources of USB 1.0 and 2.0 systems are generated from external crystal clock
12MHz or programmable PLL output. M48xGC/M48xE8 has a HIRC48M for USB 1.0 system.
The generated clocks are shown in Figure 6.3-8 and Figure 6.3-9.
USB2.0 OTG
Controller
HXT
USB2.0 OTG
PHY
30MHz
USB2.0 Device
Controller
USB2.0 Host
Controller
USB1.1 Host
Controller
PLLFOUT
/(USBDIV + 1)
48MHz
USB1.1 Device
Controller
USB1.1 OTG
Controller
Figure 6.3-8 USB Clock Source (M48xID/M487KMCAN)
M480 SERIES DATASHEET
USB1.1 Host
Controller
HIRC48M
0
PLLFOUT
/(USBDIV + 1)
48MHz
1
USBSEL
USB1.1 Device
Controller
USB1.1 OTG
Controller
Figure 6.3-9 USB Clock Source (M48xGC/M48xE8)
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M480
6.4 True Random Number Generator (TRNG)
6.4.1
Overview
The True Random Number Generator (TRNG) is used to generate the randomness by extracting from
physical phenomena.
6.4.2
Features
Generates 800 random bits per second
M480 SERIES DATASHEET
May 08, 2020
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M480
6.5 Flash Memeory Controller (FMC)
6.5.1
Overview
The FMC is equipped with 128/256/512 Kbytes on-chip embedded Flash for application and
configurable Data Flash to store some application dependent data. Thus, the total size of application
rom (APROM) is 128/256/512 Kbytes. A User Configuration block provides for system initiation. A 4
Kbytes loader ROM (LDROM) is used for In-System-Programming (ISP) function. A 4 Kbytes security
protection ROM (SPROM) can conceal user program. A 3 Kbytes one-time-program ROM (OTP) is
used for recording one-time-program data. A 32 Kbytes Boot Loader consists of native ISP functions
and secure boot function. A 8 Kbytes Boot Loader consists of secure boot function. A 4 Kbytes cache
with zero wait cycle is used to improve Flash access performance. This chip also supports InApplication-Programming (IAP) function. User switches the code executing without chip reset after the
embedded Flash is updated.
6.5.2
Features
M480 SERIES DATASHEET
Supports dual-bank Flash macro for safe firmware upgrade
Supports 128/256 Kbytes application ROM (APROM)
Supports 512 Kbytes application ROM (APROM)
Supports 4 Kbytes loader ROM (LDROM)
Supports 4 Kbytes security protection ROM (SPROM) to conceal user program
Supports mirror SPROM in dual-bank Flash macro to read SPROM code while writing
other ROM
Supports 4 XOM (eXecution Only Memory) regions to conceal user program in APROM.
Supports Data Flash with configurable memory size
Supports 16 bytes User Configuration block to control system initiation
Supports 3 Kbytes one-time-program ROM (OTP)
Supports 4 Kbytes page erase for all embedded Flash
Supports block and bank erase for APROM, except for XOM regions
Supports Boot Loader with native In-System-Programming (ISP) functions
Supports Secure Boot function for code integrity and authenticity
Supports Security Key protection function for APROM, LDROM, SPROM, User
Configuration block and KPROM protection
Supports 32-bit/64-bit and multi-word Flash programming function
Supports fast Flash programming verification function
Supports CRC32 checksum calculation function
Supports Flash all one verification function
Supports In-System-Programming (ISP) / In-Application-Programming (IAP) to update
embedded Flash memory
Supports cache memory to improve Flash access performance and reduce power
consumption
Supports auto-tuning Flash access cycle function to optimize the Flash access
performance
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M480
FMC Features
M48xID/M487KMCAN
Dual-bank Flash macro
●
128/256 Kbytes APROM
●
512 Kbytes APROM
●
4 Kbytes LDROM
●
4 Kbytes SPROM
●
M48xGC/M48xE8
●
●
●
4 XOM region
Data Flash with configurable memory size
●
●
16 bytes User Configuration block (UCFG)
●
●
3 Kbytes OTP
●
●
8 Kbytes KPROM
●
●
4 Kbytes page erase
●
●
Block and bank erase for APROM, except for XOM
●
●
32 Kbytes Boot Loader with native ISP functions
●
●
8 Kbytes Boot Loader with native ISP functions
●
AES secure boot function
●
ECC secure boot function
●
●
Security Key protection function for UCFG and KPROM
●
●
Security Key protection function for SPROM
●
32-bit/64-bit and multi-word Flash programming function
●
●
Fast Flash programming verification function
●
●
CRC32 checksum calculation function
●
●
4 Kbytes cache memory
●
●
M480 SERIES DATASHEET
Security Key protection function for APROM and LDROM
●
Auto-tuning Flash access cycle function
In-Application-Programming function (IAP)
●
Boot from boot loader via PF.0 at reset rising
●
●
Table 6.5-1 FMC Features Comparison Table at Different Chip
May 08, 2020
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M480
6.6 General Purpose I/O (GPIO)
6.6.1
Overview
This chip has up to 118 General Purpose I/O pins to be shared with other function pins depending on
the chip configuration. These 118 pins are arranged in 8 ports named as PA, PB, PC, PD, PE, PF, PG
and PH. PA, PB, PE and PG has 16 pins on port. PC, PD has 15 pins on port. PF, PH has 12 pins on
port. Each of the 118 pins is independent and has the corresponding register bits to control the pin
mode function and data.
The I/O type of each of I/O pins can be configured by software individually as Input, Push-pull output,
Open-drain output or Quasi-bidirectional mode. After the chip is reset, the I/O mode of all pins are
depending on CIOINI (CONFIG0[10]).
6.6.2
Features
Four I/O modes:
–
Quasi-bidirectional mode
–
Push-Pull Output mode
–
Open-Drain Output mode
–
Input only with high impendence mode
TTL/Schmitt trigger input selectable
I/O pin can be configured as interrupt source with edge/level setting
Supports High Drive and High Slew Rate I/O mode
Configurable default I/O mode of all pins after reset by CIOINI (CONFIG0[10]) setting
–
CIOINI = 0, all GPIO pins in Quasi-bidirectional mode after chip reset
–
CIOINI = 1, all GPIO pins in input mode after chip reset
M480 SERIES DATASHEET
Supports independent pull-up and pull-down control
Enabling the pin interrupt function will also enable the wake-up function
May 08, 2020
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M480
6.7 PDMA Controller (PDMA)
6.7.1
Overview
The peripheral direct memory access (PDMA) controller is used to provide high-speed data transfer.
The PDMA controller can transfer data from one address to another without CPU intervention. This
has the benefit of reducing the workload of CPU and keeps CPU resources free for other applications.
The PDMA controller has a total of 16 channels and each channel can perform transfer between
memory and peripherals or between memory and memory.
6.7.2
Features
Supports 16 independently configurable channels
Selectable 2 level of priority (fixed priority or round-robin priority)
Supports transfer data width of 8, 16, and 32 bits
Supports source and destination address increment size can be byte, half-word, word or
no increment
Supports software and SPI, UART, DAC, ADC and PWM request
Supports Scatter-Gather mode to perform sophisticated transfer through the use of the
descriptor link list table
Supports single and burst transfer type
Supports time-out function on channel 0 and channel1
Supports stride function from channel 0 to channel 5
Enhanced Stride Function for image processing (M48xGC/M48xE8)
M480 SERIES DATASHEET
May 08, 2020
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M480
6.8 Timer Controller (TMR)
6.8.1
Overview
The timer controller includes four 32-bit timers, Timer0 ~ Timer3, allowing user to easily implement a
timer control for applications. The timer can perform functions, such as frequency measurement, delay
timing, clock generation, and event counting by external input pins, and interval measurement by
external capture pins.
The timer controller also provides four PWM generators. Each PWM generator supports two PWM
output channels in independent mode and complementary mode. The output state of PWM output pin
can be control by pin mask, polarity and break control, and dead-time generator.
6.8.2
Features
6.8.2.1
Timer Function Features
M480 SERIES DATASHEET
Four sets of 32-bit timers, each timer having one 24-bit up counter and one 8-bit prescale
counter
Independent clock source for each timer
Provides one-shot, periodic, toggle-output and continuous counting operation modes
24-bit up counter value is readable through CNT (TIMERx_CNT[23:0])
Supports event counting function
24-bit capture value is readable through CAPDAT (TIMERx_CAP[23:0])
Supports external capture pin event for interval measurement
Supports external capture pin event to reset 24-bit up counter
Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is
generated
Support Timer0 ~ Timer3 time-out interrupt signal or capture interrupt signal to trigger
EPWM, BPWM, EADC, DAC and PDMA function
Supports internal capture triggered while internal ACMP output signal transition
Supports internal clock (HIRC, LIRC) and external clock (HXT, LXT) for capture event
Supports Inter-Timer trigger mode
Supports event counting source from internal USB SOF signal
6.8.2.2
PWM Function Features
Supports maximum clock frequency up to maximum PCLK
Supports independent mode for PWM generator with two output channels
Supports complementary mode for PWM generator with paired PWM output channel
–
12-bit dead-time insertion with 12-bit prescale
Supports 12-bit prescale from 1 to 4096
Supports 16-bit PWM counter
–
Up, down and up-down count operation type
–
One-shot or auto-reload counter operation mode
Supports mask function and tri-state enable for each PWM output pin
Supports brake function
May 08, 2020
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M480
–
Brake source from pin, analog comparator and system safety events (clock failed,
Brown-out detection, SRAM parity error and CPU lockup)
–
Brake pin noise filter control for brake source
–
Edge detect brake source to control brake state until brake status cleared
–
Level detect brake source to auto recover function after brake condition removed
Supports interrupt on the following events:
–
PWM zero point, period point, up-count compared or down-count compared point
events
–
Brake condition happened
Supports trigger EADC on the following events:
–
PWM zero point, period, zero or period point, up-count compared or down-count
compared point events
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6.9 Watchdog Timer (WDT)
6.9.1
Overview
The Watchdog Timer (WDT) is used to perform a system reset when system runs into an unknown
state. This prevents system from hanging for an infinite period of time. Besides, this Watchdog Timer
supports the function to wake up system from Idle/Power-down mode.
6.9.2
Features
18-bit free running up counter for WDT time-out interval
Selectable time-out interval (2 ~ 2 ) and the time-out interval is 1.6 ms ~ 26.214 s if
WDT_CLK = 10 kHz.
System kept in reset state for a period of (1 / WDT_CLK) * 63
Supports selectable WDT reset delay period, including 1026、130、18 or 3 WDT_CLK
reset delay period
Supports to force WDT enabled after chip powered on or reset by setting CWDTEN[2:0]
in Config0 register
Supports WDT time-out wake-up function only if WDT clock source is selected as 10 kHz
or LXT.
4
18
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6.10 Window Watchdog Timer (WWDT)
6.10.1 Overview
The Window Watchdog Timer (WWDT) is used to perform a system reset within a specified window
period to prevent software running to uncontrollable status by any unpredictable condition.
6.10.2 Features
6-bit down counter value (CNTDAT, WWDT_CNT[5:0]) and 6-bit compare value
(CMPDAT, WWDT_CTL[21:16]) to make the WWDT time-out window period flexible
Supports 4-bit value (PSCSEL, WWDT_CTL[11:8]) to programmable maximum 11-bit
prescale counter period of WWDT counter
WWDT counter suspends in Idle/Power-down mode
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6.11 Real Time Clock (RTC)
6.11.1 Overview
The Real Time Clock (RTC) controller provides the real time and calendar message. The RTC offers
programmable time tick and alarm match interrupts. The data format of time and calendar messages
are expressed in BCD format. A digital frequency compensation feature is available to compensate
external crystal oscillator frequency accuracy.
6.11.2 Features
M480 SERIES DATASHEET
Supports independent RTC power domain with external power pin V BAT.
(M48xGC/M48xE8)
Supports real time counter in RTC_TIME (hour, minute, second) and calendar counter in
RTC_CAL (year, month, day) for RTC time and calendar check.
Supports alarm time (hour, minute, second) and calendar (year, month, day) settings in
RTC_TALM and RTC_CALM.
Supports alarm time (hour, minute, second) and calendar (year, month, day) mask enable
in RTC_TAMSK and RTC_CAMSK.
Selectable 12-hour or 24-hour time scale in RTC_CLKFMT register.
Optional support 1/128 second HZCNT in RTC_TIME and RTC_TALM.
Supports Leap Year indication in RTC_LEAPYEAR register.
Supports Day of the Week counter in RTC_WEEKDAY register.
Frequency of RTC clock source compensate by RTC_FREQADJ register.
All time and calendar message expressed in BCD format.
Supports periodic RTC Time Tick interrupt with 8 period interval options 1/128, 1/64,
1/32, 1/16, 1/8, 1/4, 1/2 and 1 second.
Supports RTC Time Tick and Alarm Match interrupt.
Supports chip wake-up from Idle or Power-down mode while a RTC interrupt signal is
generated.
Supports Daylight Saving Time software control in RTC_DSTCTL.
Supports up to 6 individual tamper pins.
Supports 20/80 bytes spare registers and tamper pins detection to clear the content of
these spare registers.
Supports Flash mass erase operate will also clear the 20 bytes spare registers content.
(M48xGC/M48xE8)
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6.12 EPWM Generator and Capture Timer (EPWM)
6.12.1 Overview
The chip provides two EPWM generators － EPWM0 and EPWM1. Each EPWM supports 6 channels
of EPWM output or input capture. There is a 12-bit prescaler to support flexible clock to the 16-bit
EPWM counter with 16-bit comparator. The EPWM counter supports up, down and up-down counter
types. EPWM uses comparator compared with counter to generate events. These events use to
generate EPWM pulse, interrupt and trigger signal for EADC/DAC to start conversion.
The EPWM generator supports two standard EPWM output modes: Independent mode and
Complementary mode, they have difference architecture. There are two output functions based on
standard output modes: Group function and Synchronous function. Group function can be enabled
under Independent mode or complementary mode. Synchronous function only enabled under
complementary mode. Complementary mode has two comparators to generate various EPWM pulse
with 12-bit dead-time generator and another free trigger comparator to generate trigger signal for
EADC. For EPWM output control unit, it supports polarity output, independent pin mask and brake
functions.
The EPWM generator also supports input capture function. It supports latch EPWM counter value to
corresponding register when input channel has a rising transition, falling transition or both transition is
happened. Capture function also support PDMA to transfer captured data to memory.
6.12.2 Features
6.12.2.1 EPWM Function Features
Supports maximum clock frequency up to maximum PLL frequency
Supports up to two EPWM modules, each module provides 6 output channels
Supports independent mode for EPWM output/Capture input channel
Supports complementary mode for 3 complementary paired EPWM output channel
Dead-time insertion with 12-bit resolution
–
Synchronous function for phase control
–
Two compared values during one period
Supports 12-bit prescaler from 1 to 4096
Supports 16-bit resolution EPWM counter
–
M480 SERIES DATASHEET
–
Up, down and up/down counter operation type
Supports one-shot or auto-reload counter operation mode
Supports group function
Supports synchronous function
Supports mask function and tri-state enable for each EPWM pin
Supports brake function
–
Brake source from pin, analog comparator and system safety events (clock failed,
SRAM parity error, Brown-out detection and CPU lockup).
–
Noise filter for brake source from pin
–
Leading edge blanking (LEB) function for brake source from analog comparator
–
Edge detect brake source to control brake state until brake interrupt cleared
–
Level detect brake source to auto recover function after brake condition removed
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Supports interrupt on the following events:
–
EPWM counter matches 0, period value or compared value
–
Brake condition happened
Supports trigger EADC/DAC on the following events:
–
EPWM counter matches 0, period value or compared value
–
EPWM counter matches free trigger comparator compared value (only for EADC)
–
Supports EPWM trigger EADC event prescaler feature
Supports EPWM output accumulator stop counter mode (M48xGC/M48xE8)
Supports Fault Detect function (M48xGC/M48xE8)
6.12.2.2 Capture Function Features
Supports up to 12 capture input channels with 16-bit resolution
Supports rising or falling capture condition
Supports input rising/falling capture interrupt
Supports rising/falling capture with counter reload option
Supports PDMA transfer function for EPWM all channels
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6.13 Basic PWM Generator and Capture Timer (BPWM)
6.13.1 Overview
The chip provides two BPWM generators － BPWM0 and BPWM1. Each BPWM supports 6 channels
of BPWM output or input capture. There is a 12-bit prescaler to support flexible clock to the 16-bit
BPWM counter with 16-bit comparator. The BPWM counter supports up, down and up-down counter
types, all 6 channels share one counter. BPWM uses the comparator compared with counter to
generate events. These events are used to generate BPWM pulse, interrupt and trigger signal for
EADC0/1 to start conversion. For BPWM output control unit, it supports polarity output, independent
pin mask and tri-state output enable.
The BPWM generator also supports input capture function to latch BPWM counter value to
corresponding register when input channel has a rising transition, falling transition or both transition is
happened.
6.13.2 Features
6.13.2.1 BPWM Function Features
Supports maximum clock frequency up to maximum PLL frequency.
Supports up to two BPWM modules; each module provides 6 output channels
Supports independent mode for BPWM output/Capture input channel
Supports 12-bit prescalar from 1 to 4096
Supports 16-bit resolution BPWM counter; each module provides 1 BPWM counter
–
Up, down and up/down counter operation type
Supports mask function and tri-state enable for each BPWM pin
Supports interrupt in the following events:
–
Supports trigger EADC0/1 in the following events:
–
M480 SERIES DATASHEET
BPWM counter matches 0, period value or compared value
BPWM counter matches 0, period value or compared value
6.13.2.2 Capture Function Features
Supports up to 12 capture input channels with 16-bit resolution
Supports rising or falling capture condition
Supports input rising/falling capture interrupt
Supports rising/falling capture with counter reload option
M48xID/M487KMCAN
Trigger numbers for EADC
M48xGC/M48xE8
1
2
Table 6.13-1 BPWM Features Comparison Table
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6.14 Quadrature Encoder Interface (QEI)
6.14.1 Overview
There are two QEI controllers in this device. The Quadrature Encoder Interface (QEI) decodes speed
of rotation and motion sensor information. It can be used in any application that uses a quadrature
encoder for feedback.
6.14.2 Features
6.14.2.1 Quadrature Encoder Interface (QEI) Features
Up to two QEI controllers, QEI0 and QEI1.
Two QEI phase inputs, QEA and QEB; One Index input.
A 32-bit up/down Quadrature Encoder Pulse Counter (QEI_CNT)
A 32-bit software-latch Quadrature Encoder Pulse Counter Hold Register
(QEI_CNTHOLD)
A 32-bit Quadrature Encoder Pulse Counter Index Latch Register (QEI_CNTLATCH)
A 32-bit Quadrature Encoder Pulse Counter Compare Register (QEI_CNTCMP) with a
Pre-set Maximum Count Register (QEI_CNTMAX)
One QEI control register (QEI_CTL) and one QEI Status Register (QEI_STATUS)
Four Quadrature encoder pulse counter operation modes
–
Support x4 free-counting mode
–
Support x2 free-counting mode
–
Support x4 compare-counting mode
–
Support x2 compare-counting mode
M480 SERIES DATASHEET
Encoder Pulse Width measurement mode
Input frequency of QEA/QEB/IDX without noise filter must lower than PCLK/4
Input frequency of QEA/QEB/IDX with noise filter must lower than Noise Filter Clk/8
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6.15 Enhanced Input Capture Timer (ECAP)
6.15.1 Overview
The chip provides up to two units of Input Capture Timer/Counter whose capture function can detect
the digital edge-changed signal at channel inputs. Each unit has three input capture channels. The
timer/counter is equipped with up counting, reload and compare-match capabilities.
6.15.2 Features
Up to two Input Capture Timer/Counter units, CAP0 and CAP1.
Each unit has 3 input channels.
Each unit has its own interrupt vector.
Each input channel has its own capture counter hold register.
24-bit Input Capture up-counting timer/counter.
With noise filter in front end of input ports.
Edge detector with three options:
–
Rising edge detection
–
Falling edge detection
–
Both edge detection
Captured events reset and/or reload capture counter.
Supports compare-match function.
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6.16 UART Interface Controller (UART)
6.16.1 Overview
The chip provides three channels of Universal Asynchronous Receiver/Transmitters (UART). The
UART controller performs Normal Speed UART and supports flow control function. The UART
controller performs a serial-to-parallel conversion on data received from the peripheral and a parallelto-serial conversion on data transmitted from the CPU. Each UART controller channel supports ten
types of interrupts. The UART controller also supports IrDA SIR, LIN, RS-485 and Single-wire function
modes and auto-baud rate measuring function.
6.16.2 Features
Full-duplex asynchronous communications
Separates receive and transmit 16/16 bytes entry FIFO for data payloads
Supports hardware auto-flow control
Programmable receiver buffer trigger level
Supports programmable baud rate generator for each channel individually
Supports nCTS, incoming data, Received Data FIFO reached threshold and RS-485
Address Match (AAD mode) wake-up function
Supports 8-bit receiver buffer time-out detection function
Programmable transmitting data delay time between the last stop and the next START bit
by setting DLY (UART_TOUT [15:8])
Supports Auto-Baud Rate measurement and baud rate compensation function
–
9600 bps for UART_CLK is selected LXT.
M480 SERIES DATASHEET
Supports break error, frame error, parity error and receive/transmit buffer overflow
detection function
Fully programmable serial-interface characteristics
–
Programmable number of data bit, 5-, 6-, 7-, 8- bit character
–
Programmable PARITY bit, even, odd, no parity or stick PARITY bit generation and
detection
–
Programmable STOP bit, 1, 1.5, or 2 STOP bit generation
Supports IrDA SIR function mode
–
3/16 bit duration for normal mode
Supports LIN function mode (Only UART0/UART1 with LIN function)
–
LIN master/slave mode
–
Programmable break generation function for transmitter
–
Break detection function for receiver
Supports RS-485 function mode
–
RS-485 9-bit mode
–
Hardware or software enables to program nRTS pin to control RS-485 transmission
direction
Supports PDMA transfer function
Supports Single-wire function mode.
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UART Feature
UART0/UART1
UART2 ~ UART7
SC_UART
FIFO
16 Bytes
16 Bytes
4 Bytes
Auto Flow Control (CTS/RTS)
√
√
-
√
IrDA
√
√
-
-
LIN
√
-
-
-
RS-485 Function Mode
√
√
-
√
nCTS Wake-up
√
√
-
√
Imcoming Data Wake-up
√
√
-
√
√
√
-
RS-485 Address Match (AAD mode)
√
Wake-up
√
-
Auto-Baud Rate Measurement
√
√
-
√
STOP bit Length
1, 1.5, 2 bit
1, 1.5, 2 bit
1, 2 bit
1, 2 bit
Word Length
5, 6, 7, 8 bits
5, 6, 7, 8 bits
5, 6, 7, 8 bits
6~13 bits
Even / Odd Parity
√
√
√
√
Stick Bit
√
√
-
-
Received
Data
threshold Wake-up
FIFO
reached
USCI-UART
TX: 1byte
RX: 2byte
-
Note: √= Supported
Table 6.16-1 M480 Series UART Features
M480 SERIES DATASHEET
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6.17 Ethernet MAC Controller (EMAC)
6.17.1 Overview
This chip provides an Ethernet MAC Controller (EMAC) for Network application. The Ethernet MAC
controller consists of IEEE 802.3/Ethernet protocol engine with internal CAM function for recognizing
Ethernet MAC addresses, Transmit-FIFO, Receive-FIFO, TX/RX state machine controller, time
stamping engine for IEEE 1588, Magic Packet parsing engine and status controller. The EMAC
supports both the MII and RMII (Reduced MII) interface to connect with external Ethernet PHY.
6.17.2 Features
Supports IEEE Std. 802.3 CSMA/CD protocol
Supports Ethernet frame time stamping for IEEE Std. 1588 – 2002 protocol
Supports both half and full duplex for 10 Mbps or 100 Mbps operation
Supports RMII interface
Supports MII Management function to control external Ethernet PHY
Supports pause and remote pause function for flow control
Supports long frame (more than 1518 bytes) and short frame (less than 64 bytes)
reception
Supports 16 entries CAM function for Ethernet MAC address recognition
Supports Magic Packet recognition to wake system up from Power-down mode
Supports 256 bytes transmit FIFO and 256 bytes receive FIFO
Supports DMA function
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6.18 Smart Card Host Interface (SC)
6.18.1 Overview
The Smart Card Interface controller (SC controller) is based on ISO/IEC 7816-3 standard and fully
compliant with PC/SC Specifications. It also provides status of card insertion/removal. It can also be
set as UART mode to communicate with other device.
6.18.2 Features
ISO 7816-3 T = 0, T = 1 compliant
EMV2000 compliant
Three ISO 7816-3 ports
Separates receive/transmit 4 byte entry FIFO for data payloads
Programmable transmission clock frequency
Programmable receiver buffer trigger level
Programmable guard time selection (11 ETU ~ 267 ETU)
One 24-bit timer and two 8-bit timers for Answer to Request (ATR) and waiting times
processing
Supports auto direct / inverse convention function
Supports transmitter and receiver error retry and error number limiting function
Supports hardware activation sequence process, and the time between PWR on and CLK
start is configurable
Supports hardware warm reset sequence process
Supports hardware deactivation sequence process
Supports hardware auto deactivation sequence when detected the card removal
Supports UART mode
–
Full duplex, asynchronous communications
–
Separates receiving / transmitting 4 bytes entry FIFO for data payloads
–
Supports programmable baud rate generator
–
Supports programmable receiver buffer trigger level
–
Programmable transmitting data delay time between the last stop bit leaving the TXFIFO and the de-assertion by setting EGT (SCn_EGT[7:0])
–
Programmable even, odd or no parity bit generation and detection
–
Programmable stop bit, 1- or 2- stop bit generation
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6.19 I2S Controller (I2S)
6.19.1 Overview
2
2
The I S controller consists of I S protocol to interface with external audio CODEC. Two 16-level depth
FIFO for reading path and writing path respectively are capable of handling 8/16/24/32 bits audio data
sizes. A PDMA controller handles the data movement between FIFO and memory.
6.19.2 Features
Supports Master mode and Slave mode
Capable of handling 8, 16, 24 and 32 bits data sizes in each audio channel
Supports monaural and stereo audio data
Supports I S protocols: Philips standard, MSB-justified, and LSB-justified data format
Supports PCM protocols: PCM standard, MSB-justified, and LSB-justified data format
PCM protocol supports TDM multi-channel transmission in one audio sample, and the
number of data channel can be set as 2, 4, 6, or 8
Provides two 16-level FIFO data buffers, one for transmitting and the other for receiving
Generates interrupt requests when buffer levels cross a programmable boundary
Supports two PDMA requests, one for transmitting and the other for receiving
2
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6.20 Serial Peripheral Interface (SPI)
6.20.1 Overview
The Serial Peripheral Interface (SPI) applies to synchronous serial data communication and allows full
duplex transfer. Devices communicate in Master/Slave mode with the 4-wire bi-direction interface. The
chip contains up to four sets of SPI controllers performing a serial-to-parallel conversion on data
received from a peripheral device, and a parallel-to-serial conversion on data transmitted to a
peripheral device. Each SPI controller can be configured as a master or a slave device and supports
2
the PDMA function to access the data buffer. Each SPI controller also supports I S mode to connect
external audio CODEC.
6.20.2 Features
–
Up to four sets of SPI controllers
–
Supports Master or Slave mode operation
–
Master mode up to 96 MHz (when chip works at VDD = 2.7~3.6V)
–
Slave mode up to 96 MHz when SPI master device supports adjustment function of
RX data sampling clock (when chip works at VDD = 2.7~3.6V)
–
Slave mode up to 48 MHz when SPI master device does not support adjustment
function of RX data sampling clock (when chip works at VDD = 2.7~3.6V)
–
Configurable bit length of a transaction word from 8 to 32-bit
–
Provides separate 4-level depth transmit and receive FIFO buffers
–
Supports MSB first or LSB first transfer sequence
–
Supports Byte Reorder function
–
Supports Byte or Word Suspend mode
–
Supports PDMA transfer
–
Supports one data channel half-duplex transfer
–
Supports receive-only mode
2
I S Mode
–
Supports Master or Slave
–
Capable of handling 8-, 16-, 24- and 32-bit word sizes
–
Each provides two 4-level FIFO data buffers, one for transmitting and the other for
receiving
–
Supports monaural and stereo audio data
–
Supports PCM mode A, PCM mode B, I S and MSB justified data format
–
Supports two PDMA requests, one for transmitting and the other for receiving
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SPI Mode
M480
6.21 Quad Serial Peripheral Interface (QSPI)
6.21.1 Overview
The Quad Serial Peripheral Interface (QSPI) applies to synchronous serial data communication and
allows full duplex transfer. Devices communicate in Master/Slave mode with the 4-wire bi-direction
interface. The chip contains one QSPI controller performing a serial-to-parallel conversion on data
received from a peripheral device, and a parallel-to-serial conversion on data transmitted to a
peripheral device.
The QSPI controller supports 2-bit Transfer mode to perform full-duplex 2-bit data transfer and also
supports Dual and Quad I/O Transfer mode and the controller supports the PDMA function to access
the data buffer.
6.21.2 Features
M480 SERIES DATASHEET
Supports Master or Slave mode operation
Master mode up to 96 MHz (when chip works at VDD = 2.7V~3.6V)
Slave mode up to 96 MHz when SPI master device supports adjustment function of RX
data sampling clock (when chip works at VDD = 2.7V~3.6V)
Slave mode up to 48 MHz when SPI master device does not support adjustment function
of RX data sampling clock (when chip works at VDD = 2.7V~3.6V)
Supports 2-bit Transfer mode
Supports Dual and Quad I/O Transfer mode
Configurable bit length of a transaction word from 8 to 32-bit
Provides separate 8-level depth transmit and receive FIFO buffers
Supports MSB first or LSB first transfer sequence
Supports Byte Reorder function
Supports Byte or Word Suspend mode
Supports PDMA transfer
Supports 3-Wire, no slave selection signal, bi-direction interface
Supports one data channel half-duplex transfer
Supports Transmit Double Transfer Rate Mode (TX DTR mode)
Supports receive-only mode
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6.22 SPI Synchronous Serial Interface Controller (SPI Master mode)
6.22.1 Overview
The SPI Synchronous serial Interface Controller for SPI master mode performs a serial-to-parallel
conversion on data received from the peripheral, and a parallel-to-serial conversion on data received
from MCU. This SPI controller can drive one external peripheral (External SPI Flash) and it is seen as
the SPI master mode. It can generate an interrupt signal when data transfer is finished and can be
cleared by writing 1 to the interrupt flag. The active level of device/slave select signal can be chosen to
low active or high active, which depends on the peripheral. Writing a divisor into the SPIM_CTL1
register can program the frequency of serial clock output to the peripheral.
In SPI Flash controller, normal I/O mode contains four 32-bit transmit/receive buffers, and can provide
1 to 4 burst mode operation. The number of bits in each transaction can be 8, 16, 24, or 32; data can
be transmitted/received up to four successive transactions in one transfer.
By DMA write mode, user can move data from SRAM to external SPI Flash component. In DMA read
mode, user can move data from external SPI Flash component to SRAM. In direct memory mapping
mode (DMM mode), this SPI Flash controller will translate the AHB bus commands into SPI Flash
operations without MCU setting related SPI Flash command. Therefore users can access external SPI
Flash as a ROM module.
In direct memory mapping mode with cache off mode, it will pre-fetch 4-word Flash data after a direct
memory mapping access. when using direct memory mapping mode with cache on mode, it will use
32 Kbytes cache memory to reduce the number of accessing external SPI Flash component and the
performance of SPI Flash access can be improved. To improve the read operation of SPI Flash
without increasing the serial clock frequency, this SPI Flash controller supports DTR/DDR (Double
Transfer Rate/Double Data Rate) read command codes that support Standard/Dual/Quad SPI modes.
The one byte command code is still latched into the device on the rising edge of the serial clock similar
to all other SPI commands. Once a DTR/DDR instruction code is accepted by the device, the address
input and data output will be latched on both rising and falling edges of the serial clock.
6.22.2 Features
Supports maximum 32 Mbytes SPI Flash size
Supports SPI master mode
Supports Direct Memory Mapping Mode and Normal I/O Mode
Supports 8/16/24/32 bits transaction for Normal I/O mode
Provides burst mode operation in Normal I/O mode, which can transmit/receive data up to
four successive transactions in one transfer
Supports DMA mode read/write
Supports standard (1-bit), dual (2-bit), and quad (4-bit) I/O transfer mode
Supports Double Transfer Rate (DTR) / Double Data Rate (DDR) transfer mode
Supports 32 Kbytes cache memory
Supports 32 Kbytes Core Coupled Memory (CCM) when cache function disable
Supports Cipher encryption/decryption
One slave/device select line for external SPI Flash component
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In core coupled memory mode (CCM mode), the cache function is disabled by hardware
automatically, and MCU can access this 32 Kbytes cache memory as general SRAM. For data
protection, this SPI Flash controller supports cipher encryption and decryption circuits to protect data
which user places into external SPI Flash when DMA read/write mode and direct memory mapping
mode are used.
M480
6.23 I2C Serial Interface Controller (I2C)
6.23.1 Overview
2
I C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange
2
between devices. The I C standard is a true multi-master bus including collision detection and
arbitration that prevents data corruption if two or more masters attempt to control the bus
simultaneously.
2
There are two sets of I C controllers which support Power-down wake-up function.
6.23.2 Features
2
The I C bus uses two wires (SDA and SCL) to transfer information between devices connected to the
2
bus. The main features of the I C bus include:
2
M480 SERIES DATASHEET
Supports up to three I C ports
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Supports High speed mode 3.4Mbps
Supports Standard mode (100 kbps), Fast mode (400 kbps) and Fast mode plus (1
Mbps)
Arbitration between simultaneously transmitting masters without corruption of serial data
on the bus
Serial clock synchronization allow devices with different bit rates to communicate via one
serial bus
Serial clock synchronization used as a handshake mechanism to suspend and resume
serial transfer
Built-in 14-bit time-out counter requesting the I C interrupt if the I C bus hangs up and
timer-out counter overflow
Programmable clocks allow for versatile rate control
Supports 7-bit addressing and 10-bit addressing mode
Supports multiple address recognition ( four slave address with mask option)
Supports Power-down wake-up function
Supports PDMA with one buffer capability
Supports setup/hold time programmable
Supports Bus Management (SM/PM compatible) function
2
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6.24 USCI - Universal Serial Control Interface Controller (USCI)
6.24.1 Overview
The Universal Serial Control Interface (USCI) is a flexible interface module covering several serial
2
communication protocols. The user can configure this controller as UART, SPI, or I C functional
protocol.
6.24.2 Features
The controller can be individually configured to match the application needs. The following protocols
are supported:
UART
SPI
IC
2
M480 SERIES DATASHEET
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6.25 USCI – UART Mode
6.25.1 Overview
The asynchronous serial channel UART covers the reception and the transmission of asynchronous
data frames. It performs a serial-to-parallel conversion on data received from the peripheral, and a
parallel-to-serial conversion on data transmitted from the controller. The receiver and transmitter are
independent, and the transmission and reception can be started separately.
The UART controller also provides auto flow control. There are three conditions to wake up the
system.
6.25.2 Features
Supports one transmit buffer and two receive buffer for data payload
Supports hardware auto flow control function
Supports programmable baud-rate generator
Support 9-bit Data Transfer (Support 9-bit RS-485)
Baud rate detection possible by built-in capture event of baud rate generator
Supports PDMA transfer
Supports Wake-up function (Incoming Data and nCTS Wakeup Only)
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6.26 USCI - SPI Mode
6.26.1 Overview
The SPI protocol of USCI controller applies to synchronous serial data communication and allows full
duplex transfer. It supports both master and Slave operation mode with the 4-wire bi-direction
interface. SPI mode of USCI controller performs a serial-to-parallel conversion on data received from a
peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device. The
SPI mode is selected by FUNMODE (USPI_CTL[2:0]) = 0x1
This SPI protocol can operate as master or Slave mode by setting the SLAVE (USPI_PROTCTL[0]) to
communicate with the off-chip SPI Slave or master device. The application block diagrams in master
and Slave mode are shown below.
USCI
USCI SPI
SPI Master
Master
SPI Slave Device
SPI_MOSI
Master Transmit Data
(USCIx_DAT0)
SPI_MISO
Master Receive Data
(USCIx_DAT1)
Serial Bus Clock
SPI_CLK
(USCIx_CLK)
Slave Select
SPI_SS
(USCIx_CTL)
SPI_MOSI
SPI_MISO
SPI_CLK
SPI_SS
Note: x = 0, 1
Figure 6.26-1 SPI Master Mode Application Block Diagram
USCI
USCI SPI
SPI Slave
Slave
SPI Master Device
SPI_MOSI
(USCIx_DAT0)
Slave Transmit Data
SPI_MISO
(USCIx_DAT1)
Serial Bus Clock
SPI_CLK
(USCIx_CLK)
Slave Select
SPI_SS
(USCIx_CTL)
M480 SERIES DATASHEET
Slave Receive Data
SPI_MOSI
SPI_MISO
SPI_CLK
SPI_SS
Note: x = 0, 1
Figure 6.26-2 SPI Slave Mode Application Block Diagram
6.26.2 Features
Supports Master or Slave mode operation (the maximum frequency -- Master = fPCLK / 2,
Slave < fPCLK / 5)
Configurable bit length of a transfer word from 4 to 16-bit
Supports one transmit buffer and two receive buffers for data payload
Supports MSB first or LSB first transfer sequence
Supports Word Suspend function
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Supports PDMA transfer
Supports 3-wire, no slave select signal, bi-direction interface
Supports wake-up function by slave select signal in Slave mode
Supports one data channel half-duplex transfer
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6.27 USCI - I2C Mode
6.27.1 Overview
2
On I C bus, data is transferred between a Master and a Slave. Data bits transfer on the SCL and SDA
lines are synchronously on a byte-by-byte basis. Each data byte is 8-bit. There is one SCL clock pulse
for each data bit with the MSB being transmitted first, and an acknowledge bit follows each transferred
byte. Each bit is sampled during the high period of SCL; therefore, the SDA line may be changed only
during the low period of SCL and must be held stable during the high period of SCL. A transition on
the SDA line while SCL is high is interpreted as a command (START or STOP). Please refer to Figure
2
6.27-1 for more detailed I C BUS Timing.
STOP
Repeated
START
START
STOP
SDA
tBUF
tLOW
tr
SCL
tf
tHIGH
tHD_STA
tSU_DAT
tHD_DAT
tSU_STA
tSU_STO
2
Figure 6.27-1 I C Bus Timing
2
2
The device’s on-chip I C provides the serial interface that meets the I C bus standard mode
2
2
specification. The I C port handles byte transfers autonomously. The I C mode is selected by
2
FUNMODE (UI2C_CTL [2:0]) = 100B. When enable this port, the USCI interfaces to the I C bus via
2
2
two pins: SDA and SCL. When I/O pins are used as I C ports, user must set the pins function to I C in
advance.
2
Note: Pull-up resistor is needed for I C operation because the SDA and SCL are set to open-drain
2
pins when USCI is selected to I C operation mode.
Full master and slave device capability
Supports of 7-bit addressing, as well as 10-bit addressing
Communication in standard mode (100 kBit/s) or in fast mode (up to 400 kBit/s)
Supports multi-master bus
Supports one transmit buffer and two receive buffer for data payload
Supports 10-bit bus time-out capability
Supports bus monitor mode.
Supports Power down wake-up by START signal or address match
Supports setup/hold time programmable
Supports multiple address recognition (two slave address with mask option)
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6.27.2 Features
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M480
6.28 Controller Area Network (CAN)
6.28.1 Overview
The C_CAN consists of the CAN Core, Message RAM, Message Handler, Control Registers and
Module Interface. The CAN Core performs communication according to the CAN protocol version 2.0
part A and B. The bit rate can be programmed to values up to 1 Mbps. For the connection to the
physical layer, additional transceiver hardware is required.
For communication on a CAN network, individual Message Objects are configured. The Message
Objects and Identifier Masks for acceptance filtering of received messages are stored in the Message
RAM. All functions concerning the handling of messages are implemented in the Message Handler.
These functions include acceptance filtering, the transfer of messages between the CAN Core and the
Message RAM, and the handling of transmission requests as well as the generation of the module
interrupt.
The register set of the C_CAN can be accessed directly by the software through the module interface.
These registers are used to control/configure the CAN Core and the Message Handler and to access
the Message RAM.
6.28.2 Features
M480 SERIES DATASHEET
Supports CAN protocol version 2.0 part A and B
Bit rates up to 1 Mbps
32 Message Objects
Each Message Object has its own identifier mask
Programmable FIFO mode (concatenation of Message Objects)
Maskable interrupt
Disabled Automatic Re-transmission mode for Time Triggered CAN applications
Programmable loop-back mode for self-test operation
16-bit module interfaces to the AMBA APB bus
Supports wake-up function
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6.29 Secure Digital Host Controller (SDH)
6.29.1 Overview
The Secure Digital Host Controller (SD Host) has DMAC unit and SD unit. The DMAC unit provides a
DMA (Direct Memory Access) function for SD to exchange data between system memory and shared
buffer (128 bytes), and the SD unit controls the interface of SD/SDHC. The SDHOST controller can
support SD/SDHC and cooperated with DMAC to provide a fast data transfer between system memory
and cards.
6.29.2 Features
AMBA AHB master/slave interface compatible, for data transfer and register read/write.
Supports single DMA channel.
Supports hardware Scatter-Gather function.
Using single 128 Bytes shared buffer for data exchange between system memory and
cards.
Synchronous design for DMA with single clock domain, AHB bus clock (HCLK).
Interface with DMAC for register read/write and data transfer.
Supports SD/SDHC card.
Completely asynchronous design for Secure Digital with two clock domains, HCLK and
Engine clock, note that frequency of HCLK should be higher than the frequency of
peripheral clock.
Secure Digital Host Controllers
M48xID/M487KMCAN
M48xGC/M48xE8
2
1
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Table 6.29-1 SDH Features Comparison Table
Rev 3.00
M480
6.30 External Bus Interface (EBI)
6.30.1 Overview
This chip is equipped with an external bus interface (EBI) for external device use. To save the
connections between an external device and a chip, EBI is operating at address bus and data bus
multiplex mode. The EBI supports three chip selects that can connect three external devices with
different timing setting requirements.
6.30.2 Features
Supports up to three memory banks
Supports dedicated external chip select pin with polarity control for each bank
Supports accessible space up to 1 Mbytes for each bank, actually external addressable
space is dependent on package pin out
Supports 8-/16-bit data width
Supports byte write in nresetdata width mode
Supports Address/Data multiplexed Mode
Supports Timing parameters individual adjustment for each memory block
Supports LCD interface i80 mode
Supports PDMA mode
Supports variable external bus base clock (MCLK) which based on HCLK
Supports configurable idle cycle for different access condition: Idle of Write command
finish (W2X) and Idle of Read-to-Read (R2R)
Supports address bus and data bus separate mode
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6.31 USB 1.1 Device Controller (USBD)
6.31.1 Overview
There is one set of USB 2.0 full-speed device controller and transceiver in this device. It is compliant
with USB 2.0 full-speed device specification and supports control/bulk/interrupt/ isochronous transfer
types.
In this device controller, there are two main interfaces: the APB bus and USB bus which comes from
the USB PHY transceiver. For the APB bus, the CPU can program control registers through it. There
are 1 Kbytesytes internal SRAM as data buffer in this controller. For IN or OUT transfer, it is necessary
to write data to SRAM or read data from SRAM through the APB interface or SIE. User needs to set
the effective starting address of SRAM for each endpoint buffer through buffer segmentation register
(USBD_BUFSEGx).
There are 12 endpoints in this controller. Each of the endpoint can be configured as IN or OUT
endpoint. All the operations including Control, Bulk, Interrupt and Isochronous transfer are
implemented in this block. The block of “Endpoint Control” is also used to manage the data sequential
synchronization, endpoint states, current start address, transaction status, and data buffer status for
each endpoint.
There are four different interrupt events in this controller. They are the no-event-wake-up, device plugin or plug-out event, USB events, like IN ACK, OUT ACK etc, and BUS events, like suspend and
resume, etc. Any event will cause an interrupt, and users just need to check the related event flags in
interrupt event status register (USBD_INTSTS) to acknowledge what kind of interrupt occurring, and
then check the related USB Endpoint Status Register (USBD_EPSTS0 and USBD_EPSTS1) to
acknowledge what kind of event occurring in this endpoint.
A software-disconnect function is also supported for this USB controller. It is used to simulate the
disconnection of this device from the host. If user enables SE0 bit (USBD_SE0), the USB controller
will force the output of USB_D+ and USB_D- to level low and its function is disabled. After disable the
SE0 bit, host will enumerate the USB device again.
For more information on the Universal Serial Bus, please refer to Universal Serial Bus Specification
Revision 1.1.
Compliant with USB 2.0 Full-Speed specification
Provides 1 interrupt vector with 5 different interrupt events (SOF, NEVWK, VBUSDET,
USB and BUS)
Supports Control/Bulk/Interrupt/Isochronous transfer type
Supports suspend function when no bus activity existing for 3 ms
Supports 12 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer types
and maximum 1 Kbyte buffer size
Provides remote wake-up capability
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6.31.2 Features
M480
6.32 High Speed USB 2.0 Device Controller (HSUSBD)
6.32.1 Overview
The USB device controller interfaces the AHB bus and the UTMI bus. The USB controller contains
both the AHB master interface and AHB slave interface. CPU programs the USB controller registers
through the AHB slave interface. For IN or OUT transfer, the USB device controller needs to write data
to memory or read data from memory through the AHB master interface. The USB device controller is
complaint with USB 2.0 specification and it contains 12 configurable endpoints in addition to control
endpoint. These endpoints could be configured to BULK, INTERRUPT or ISO. The USB device
controller has a built-in DMA to relieve the load of CPU.
6.32.2 Features
USB Specification reversion 2.0 compliant
Supports 12 configurable endpoints in addition to Control Endpoint
Each of the endpoints can be Isochronous, Bulk or Interrupt and either IN or OUT direction
Three different operation modes of an in-endpoint － Auto Validation mode, Manual
Validation mode, Fly mode
Supports DMA operation
4092 Bytes Configurable RAM used as endpoint buffer
Supports Endpoint Maximum Packet Size up to 1024 bytes
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6.33 USB 1.1 Host Controller (USBH)
6.33.1 Overview
This chip is equipped with a USB 1.1 Host Controller (USBH) that supports Open Host Controller
Interface (OpenHCI, OHCI) Specification, a register-level description of a host controller, to manage
the devices and data transfer of Universal Serial Bus (USB).
The USBH supports an integrated Root Hub with a USB port, a DMA for real-time data transfer
between system memory and USB bus, port power control and port over current detection.
The USBH is responsible for detecting the connect and disconnect of USB devices, managing data
transfer, collecting status and activity of USB bus, providing power control and detecting over current
of attached USB devices.
6.33.2 Features
Compliant with Universal Serial Bus (USB) Specification Revision 1.1.
Supports Open Host Controller Interface (OpenHCI) Specification Revision 1.0.
Supports both full-speed (12Mbps) and low-speed (1.5Mbps) USB devices.
Supports Control, Bulk, Interrupt and Isochronous transfers.
Supports an integrated Root Hub.
Supports a USB host port shared with USB device (OTG function).
Supports port power control and port over current detection.
Supports DMA for real-time data transfer.
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6.34 USB 2.0 Host Controller (USBH)
6.34.1 Overview
This chip is equipped with a USB 2.0 HS/FS Host Controller (USBH) that supports Enhanced Host
Controller Interface (EHCI) and Open Host Controller Interface (OpenHCI, OHCI) Specification, a
register-level description of a host controller, to manage the devices and data transfer of Universal
Serial Bus (USB).
The USBH supports an integrated Root Hub with a USB port, a DMA for real-time data transfer
between system memory and USB bus, port power control and port over current detection.
The USBH is responsible for detecting the connect and disconnect of USB devices, managing data
transfer, collecting status and activity of USB bus, providing power control and detecting over current
of attached USB devices.
6.34.2 Features
Compliant with Universal Serial Bus (USB) Specification Revision 2.0.
Supports Enhanced Host Controller Interface (EHCI) Specification Revision 1.0
Supports Open Host Controller Interface (OpenHCI) Specification Revision 1.0.
Supports high-speed (480Mbps), full-speed (12Mbps) and low-speed (1.5Mbps) USB
devices.
Supports Control, Bulk, Interrupt, Isochronous and Split transfers.
Supports an integrated Root Hub.
Supports a port routing logic to route full/low speed device to OHCI controller.
Supports two USB host port shared with USB device (OTG function).
Supports port power control and port over current detection.
Supports DMA for real-time data transfer.
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6.35 USB On-The-Go (OTG)
6.35.1 Overview
The OTG controller interfaces to USB PHY and USB controllers which consist of a USB 1.1 host
controller and a USB 2.0 FS device controller. The OTG controller supports HNP and SRP protocols
defined in the “On-The-Go and Embedded Host Supplement to the USB 2.0 Revision 2.0
Specification”.
USB frame, including USB host, USB device, and OTG controller, can be configured as Host-only,
Device-only, ID-dependent or OTG Device mode defined in USBROLE (SYS_USBPHY[1:0]). In Hostonly mode, USB frame acts as USB host. USB frame can support both full-speed and low-speed
transfer. In Device-only mode, USB frame acts as USB device. USB frame only supports full-speed
transfer. In ID-dependent mode, USB frame can be USB Host or USB device depending on USB_ID
pin state. In OTG device mode, the role of USB frame depends on the definition of OTG specification.
USB frame only supports full-speed transfer when OTG device acts as a peripheral.
6.35.2 Features
Built-in USB PHY
Configurable to operate as:
–
Host-only
–
Device-only
–
ID-dependent: The role of USB frame is only dependent on USB_ID pin value--as
USB Host (USB_ID pin is low) or USB Device (USB_ID pin is high). Not support HNP
or SRP protocol.
–
OTG device: dependent on USB_ID pin status to be A-device (USB_ID pin is low) or
B-device (USB_ID pin is high). Support HNP and SRP protocols.
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6.36 High Speed USB On-The-Go (HSOTG)
6.36.1 Overview
The HSOTG controller interfaces to USB PHY and USB controllers which consist of a USB 2.0 host
controller and a USB 2.0 HS device controller. The OTG controller supports HNP and SRP protocols
defined in the “On-The-Go and Embedded Host Supplement to the USB 2.0 Revision 1.3
Specification”.
USB frame, including USB host, USB device, and OTG controller, can be configured as Host-only,
Device-only, ID-dependent or OTG Device mode defined in HSUSBROLE (SYS_USBPHY[17:16]). In
Host-only mode, USB frame acts as USB host. USB frame can support high-speed, full-speed and
low-speed transfer. In Device-only mode, USB frame acts as USB device. USB frame supports highspeed and full-speed transfer. In ID-dependent mode, USB frame can be USB Host or USB device
depends on USB_ID pin state. In OTG device mode, the role of USB frame depends on the definition
of OTG specification. USB frame supports high-speed and full-speed transfer when OTG device acts
as a peripheral.
6.36.2 Features
Built in USB PHY
Configurable to operate as:
–
Host-only
–
Device-only
–
ID-dependent: The role of USB frame is only dependent on USB_ID pin value--as
USB Host (USB_ID pin is low) or USB Device (USB_ID pin is high). Not support HNP
or SRP protocol.
–
OTG device: dependent on USB_ID pin status to be A-device (USB_ID pin is low) or
B-device (USB_ID pin is high). Support HNP and SRP protocols.
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6.37 CRC Controller (CRC)
6.37.1 Overview
The Cyclic Redundancy Check (CRC) generator can perform CRC calculation with four common
polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32 settings.
6.37.2 Features
Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32
16
5
CRC-CCITT: X
–
CRC-8: X + X + X + 1
–
CRC-16: X
16
+X
15
+X +1
–
CRC-32: X
32
+X
26
+X
8
+X
12
–
+X +1
2
2
23
+X
22
+X
16
+X
12
+X
11
+X
10
8
7
5
4
2
+X +X +X +X +X +X+1
Programmable seed value
Supports programmable order reverse setting for input data and CRC checksum
Supports programmable 1’s complement setting for input data and CRC checksum
Supports 8/16/32-bit of data width
–
8-bit write mode: 1-AHB clock cycle operation
–
16-bit write mode: 2-AHB clock cycle operation
–
32-bit write mode: 4-AHB clock cycle operation
Supports using PDMA to write data to perform CRC operation
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6.38 Cryptographic Accelerator (CRYPTO)
6.38.1 Overview
The Crypto (Cryptographic Accelerator) includes a secure pseudo random number generator (PRNG)
core and supports AES, DES/TDES, SHA, HMAC and ECC algorithms.
The PRNG core supports 64 bits, 128 bits, 192 bits, and 256 bits random number generation.
The AES accelerator is an implementation fully compliant with the AES (Advance Encryption
Standard) encryption and decryption algorithm. The AES accelerator supports ECB, CBC, CFB, OFB,
CTR, CBC-CS1, CBC-CS2, and CBC-CS3 mode.
The DES/TDES accelerator is an implementation fully compliant with the DES and Triple DES
encryption/decryption algorithm. The DES/TDES accelerator supports ECB, CBC, CFB, OFB, and
CTR mode.
The SHA accelerator is an implementation fully compliant with the SHA-160, SHA-224, SHA-256,
SHA-384 and SHA-512 and corresponding HMAC algorithms.
The ECC accelerator is an implementation fully compliant with elliptic curve cryptography by using
polynomial basis in binary field and prime filed.
6.38.2 Features
PRNG
–
M480 SERIES DATASHEET
Supports 64 bits, 128 bits, 192 bits, and 256 bits random number generation
AES
–
Supports FIPS NIST 197
–
Supports SP800-38A and addendum
–
Supports 128, 192, and 256 bits key
–
Supports both encryption and decryption
–
Supports ECB, CBC, CFB, OFB, CTR, CBC-CS1, CBC-CS2, and CBC-CS3 mode
–
Supports key expander
DES
–
Supports FIPS 46-3
–
Supports both encryption and decryption
–
Supports ECB, CBC, CFB, OFB, and CTR mode
TDES
–
Supports FIPS NIST 800-67
–
Implemented according to the X9.52 standard
–
Supports two keys or three keys mode
–
Supports both encryption and decryption
–
Supports ECB, CBC, CFB, OFB, and CTR mode
–
SHA
–
Supports FIPS NIST 180, 180-2
–
Supports SHA-160, SHA-224, SHA-256, SHA-384 and SHA-512
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HMAC
–
Supports FIPS NIST 180, 180-2
–
Supports HMAC-SHA-160, HMAC-SHA-224, HMAC-SHA-256, HMAC-SHA-384 and
HMAC-SHA-512
ECC
m
–
Supports both prime field GF(p) and binary filed GF(2 )
–
Supports NIST P-192, P-224, P-256, P-384 and P-521
–
Supports NIST B-163, B-233, B-283, B-409 and B-571
–
Supports NIST K-163, K-233, K-283, K-409 and K-571
–
Supports point multiplication, addition and doubling operations in GF(p) and GF(2 )
–
Supports modulus division, multiplication, addition and subtraction operations in GF(p)
Engine
m
Mode
M48xID/M487KMCAN
M48xGC/M48xE8
PRNG
●
●
AES
●
●
DES/TDES
●
SHA/HMAC
●
SHA-224
●
SHA-256
●
SHA-384
●
SHA-512
●
P-192/224/256
●
P-384/521
●
B-163/233
●
B-283/409/571
●
K-163/233
●
K-283/409/571
●
M480 SERIES DATASHEET
ECC
SHA-160
Curve25519
Side-channel attack
protection
Table 6.38-1 Crypto Features Comparison Table at Different Chip
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6.39 Camera Capture Interface Controller (CCAP)
6.39.1 Overview
The camera capture interface controller (CCAP) is designed to capture image data from a sensor.
After capturing or fetching image data, it processes the image data. Then, the embedded DMA
controller will move the data from the internal FIFO to system memory with AHB bus.
6.39.2 Features
CCIR601 & CCIR656 & 4-bit interfaces supported for connection to CMOS image sensor
YUV422 and RGB565 color format supported for data-in from CMOS sensor
YUV422, RGB565, RGB555 and Y-only color supported for packet data output.
Single interrupt source to interrupt controller from maskable interrupt source: Address
Match, Bus Master Transfer Error, Video Frame End
Embedded DMA controller supported to transfer data from internal FIFO to system
memory through AHB bus
CROP function supported to crop input image to the required size for digital application.
Frame rate scaling-down supported
Image scaling-down supported
Bit luma output with 8-bit threshold setting supported.
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6.40 Enhanced 12-bit Analog-to-Digital Converter (EADC)
6.40.1 Overview
The chip contains one or two 12-bit successive approximation analog-to-digital converter (SAR EADC
converter) with 16 external input channels and 3 internal channels. The EADC0/1 converter can be
started by software trigger, EPWM0/1 triggers, BPWM0/1 triggers, timer0~3 overflow pulse triggers,
ADINT0, ADINT1 interrupt EOC (End of conversion) pulse trigger and external pin (EADC0/1_ST)
input signal.
6.40.2 Features
Analog input voltage range: 0~ VREF (Max to 3.6V)
Reference voltage from VREF pin.
12-bit resolution and 10-bit accuracy is guaranteed
Up to 16 single-end analog external input channels or 8 pair differential analog input
channels
Up to 3 internal channels, they are band-gap voltage (VBG), temperature sensor (VTEMP),
and Battery power (VBAT)
Four EADC interrupts (ADINT0~3) with individual interrupt vector addresses for each
EADC
Maximum EADC clock frequency is 72 MHz for each EADC
Up to 5.14 MSPS conversion rate for each EADC at the same time
Configurable EADC internal sampling time for each EADC
12-bit, 10-bit, 8-bit, 6-bit configurable resolution for each EADC
Supports calibration and load calibration words capability for each EADC
Supports internal reference voltage VREF: 1.6V, 2.0V, 2.5V, and 3.0V.
Supports three power saving modes:
–
Deep Power-down mode
–
Power-down mode
–
Standby mode
Up to 19 sample modules
–
Each of sample modules which is configurable for EADC converter channel
(EADC0/1_CH0~15) and trigger source for each EADC
–
Sample module 16~18 is fixed for EADC0channel 16, 17, 18 input sources as bandgap voltage, temperature sensor, and battery power (VBAT)
–
Double buffer for sample control logic module 0~3
–
Configurable sampling time for each sample module
–
Conversion results are held in 19 data registers with valid and overrun indicators
Any EADC conversion of each EADC can be started by:
–
Write 1 to SWTRGn (EADC0/1_SWTRG[n], n = 0~18)
–
External pin EADC0/1_ST
–
Timer0~3 overflow pulse triggers
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–
ADINT0 and ADINT1 interrupt EOC (End of conversion) pulse triggers
–
EPWM/BPWM triggers
Supports PDMA transfer
Conversion Result Monitor by Compare Mode
Number of EADC
M48xID/M487KMCAN
M48xGC/M48xE8
1
2
Table 6.40-1 EADC Features Comparison Table
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6.41 Digital to Analog Converter (DAC)
6.41.1 Overview
The DAC module is a 12-bit, voltage output digital-to-analog converter. It can be configured to 12- or
8-bit output mode and can be used in conjunction with the PDMA controller. The DAC integrates a
voltage output buffer that can be used to reduce output impendence and drive external loads directly
without having to add an external operational amplifier.
6.41.2 Features
Analog output voltage range: 0~AVDD.
Supports 12- or 8-bit output mode.
Rail to rail settle time 6us.
Supports up to two 12-bit 1 MSPS voltage type DAC.
Reference voltage from internal reference voltage (INT_VREF), VREF pin.
DAC maximum conversion updating rate 1 MSPS.
Supports voltage output buffer mode and bypass voltage output buffer mode.
Supports software and hardware trigger, including Timer0~3, EPWM0, EPWM1, and
external trigger pin to start DAC conversion.
Supports PDMA mode.
Supports group mode of synchronized update capability for two DACs.
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6.42 Analog Comparator Controller (ACMP)
6.42.1 Overview
The chip provides two comparators. The comparator output is logic 1 when positive input is greater
than negative input; otherwise, the output is 0. Each comparator can be configured to generate an
interrupt when the comparator output value changes.
6.42.2 Features
Analog input voltage range: 0 ~ AVDD (voltage of AVDD pin)
Up to two rail-to-rail analog comparators
Supports hysteresis function
–
Supports programmable hysteresis window: 0mV, 10mV, 20mV and 30mV
Supports wake-up function
Supports programmable propagation speed and low power consumption
Selectable input sources of positive input and negative input
ACMP0 supports:
–
4 multiplexed I/O pins at positive sources:
–
M480 SERIES DATASHEET
ACMP0_P0, ACMP0_P1, ACMP0_P2, or ACMP0_P3
4 negative sources:
ACMP0_N
Comparator Reference Voltage (CRV)
Internal band-gap voltage (VBG)
DAC0 output (DAC0_OUT)
ACMP1 supports
–
4 multiplexed I/O pins at positive sources:
–
ACMP1_P0, ACMP1_P1, ACMP1_P2, or ACMP1_P3
4 negative sources:
ACMP1_N
Comparator Reference Voltage (CRV)
Internal band-gap voltage (VBG)
DAC0 output (DAC0_OUT)
Shares one ACMP interrupt vector for all comparators
Interrupts generated when compare results change (Interrupt event condition is
programmable)
Supports triggers for break events and cycle-by-cycle control for EPWM
Supports window compare mode and window latch mode
May 08, 2020
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M480
6.43 OP Amplifier (OPA)
6.43.1 Overview
This device is equipped with three operational amplifiers. Users can enable each of them individually,
by their application purpose.One of these OP amplifier outputs is connected to ADC channel for
measurement requirement.The OP amplifier circuit also can be used in the application of
Programmable Gain Amplifier (PGA).
6.43.2 Features
Analog input voltage range: 0~VDD.
Supports up to 3 operator amplifiers.
Supports to use Schmitt trigger buffer output for simple comparator function.
Supports to Schmitt trigger buffer output interrupts.
M480 SERIES DATASHEET
May 08, 2020
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M480
6.44 Peripherals Interconnection
6.44.1 Overview
Some peripherals have interconnections which allow autonomous communication or synchronous
action between peripherals without needing to involve the CPU. Peripherals interact without CPU
saves CPU resources, reduces power consumption, operates with no software latency and fast
responds.
6.44.2 Peripherals Interconnect Matrix Table
Destination
Source
BPWM
DAC
EADC
ECAP
EPWM
HIRC
IRCTRIM
HIRC48M TIMERPWM
M480 SERIES DATASHEET
ACMP
-
-
-
-
3
-
-
-
3,6
BOD
-
-
-
-
3
-
-
-
3
BPWM
4
-
1
-
4
-
-
-
-
Clock Fail
-
-
-
-
3
-
-
-
3
CPU Lockup
-
-
-
-
3
-
-
-
3
EADC
-
-
-
-
3
-
-
-
-
EPWM
4
1
1
-
4
-
-
-
-
IRCTRIM
-
-
-
-
-
2
-
2
-
LIRC
-
-
-
-
-
-
-
-
6
LXT
-
-
-
-
-
-
2
-
-
QEI
-
-
-
8
-
-
-
-
-
SRAM
-
-
-
-
3
-
-
-
3
TIMERPWM
5
1
1
-
5
-
-
-
7
USB11Device
-
-
-
-
-
-
2
-
-
QEI
9
Table 6.44-1 Peripherals Interconnect Matrix table
6.44.3 Functional Description
6.44.3.1 From EPWM, TIMER to EADC/DAC
EPWM Trigger EADC Conversion
EPWM can be one of the EADC conversion trigger source.
Setting the EADC external hardware trigger input source from EPWM trigger is described in TRM
section 6.40.5.8.
EPWM Trigger DAC Conversion
EPWM can also be used to trigger DAC conversion.
Setting the DAC hardware trigger input source from EPWM trigger is described in TRM section
6.41.5.6.
The detailed EPWM trigger conditions are described in TRM section 6.12.5.27.
May 08, 2020
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BPWM Trigger EADC Conversion
BPWM can be one of the EADC conversion trigger source.
Setting the EADC external hardware trigger input source from BPWM trigger is described in TRM
section 6.40.5.8.
The detailed BPWM trigger conditions are described in TRM section 6.13.5.16.
Timer Trigger EADC Conversion
Timer0 ~ Timer3 can be one of the EADC conversion trigger source. When timer counter value
matches the timer compared value or when the TMx_EXT pin edge transition meets setting, timer will
trigger the ADC to start the conversion.
Setting the EADC external hardware trigger input source from timer trigger is described in TRM
section 6.40.5.9.
Timer Trigger DAC Conversion
Setting the DAC hardware trigger input source from TIMER trigger is described in TRM section
6.41.5.6.
The detailed Timer trigger conditions are described in TRM section 6.8.5.10.
6.44.3.2 From LXT and USB 1.1 Device to HIRC TRIM & RC 48 MHz
Use LXT or USB Synchronous Mode to System Auto-trim HIRC Circuit
This chip supports auto-trim function: the HIRC trim (12 MHz RC oscillator) and RC 48 MHz oscillator,
according to the accurate external 32.768 kHz crystal oscillator or internal USB synchronous mode,
automatically gets accurate output frequency, 0.25 % deviation within all temperature ranges.
The detail of HIRC trim setting is described in section 6.2.9
EPWM Brake Source
EPWM brake source can be ACMP0/1_O output signal or EADC result monitor or several different
system fail conditions include clock fail, Brown-out detect, and Core lockup and SRAM Parity Error.
When system fault, EPWM brake signal generated, EPWM output will be set to protect the power
switch controlled by EPWM.
The detailed setting of EPWM brake function is described in TRM section 6.12.5.23.
TIMERPWM Brake Source
TIMERPWM brake source can be ACMP0/1_O output signal or several different system fail conditions
include clock fail, Brown-out detect, and Core lockup and SRAM Parity Error. When system fault,
EPWM brake signal generated, EPWM output will be set to protect the power switch controlled by
EPWM.
The detailed setting of TIMERPWM brake function is described in TRM section 6.8.6.17.
6.44.3.4 From EPWM/ BPWM to EPWM/ BPWM
EPWM Synchronous Start Function
Select synchronous source from EPWM0 or EPWM1 or BPWM0 or BPWM1, and select EPWM
May 08, 2020
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M480 SERIES DATASHEET
6.44.3.3 From ACMP, BOD, Clock Fail,SRAM Parity Error and CPU Lockup to EPWM/ TIMERPWM
M480
channels. The chosen EPWM channels will start counting at the same time once the synchronous
start function is enabled and CNTSEN(EPWM_SSTRG[0]) is set.
The detailed setting of EPWM synchronous start function is described in TRM section 6.12.5.19.
BPWM Synchronous Start Function
Select synchronous source from EPWM0 or EPWM1 or BPWM0 or BPWM1, and select BPWM
channels. The chosen BPWM channels will start counting at the same time once the synchronous
start function is enabled and CNTSEN(BPWM_SSTRG[0]) is set.
The detailed setting of BPWM synchronous start function is described in TRM section 6.13.5.11.
6.44.3.5 From TIMER to EPWM/BPWM
Timer Generates Trigger Pulses as EPWM External Clock Source
Timer0 ~ Timer3 can generates trigger pules as EPWM/BPWM external clock source.
When timer counter value matches the timer compared value or when the TMx_EXT pin edge
transition meets setting, timer can generate a trigger pulse by setting described in TRM section
6.8.5.10.
The setting of EPWM/BPWM clock source are described in TRM section 6.13.3 / 6.12.3.
6.44.3.6 From ACMP and LIRC to Timer Capture Function
Measure the Time Interval of ACMP0/1 Output Signal or LIRC Clock Speed
Sets the timer capture source from ACMP0/1 output signal or LIRC clock and measures the time
interval of the signal by using timer capture function. Users can use the results of time interval to trim
LIRC through software or to get the ACMP0/1 output pulse width.
The detail of time capture function setting is described in TRM section 6.8.5.8 and 6.8.5.9.
M480 SERIES DATASHEET
6.44.3.7 From Timer0/2 to Timer1/3
Inter-Timer Trigger Capture Mode
Timer0/2 will be forced in event counting mode, counting with external event, and will generate an
internal signal (INTR_TMR_TRG) to trigger Timer1/3 start or stop counting. The Timer1/3 will be
forced in capture mode and start/stop trigger-counting by Timer0/2 counter status.
The detail of inter-timer trigger capture mode is described in TRM section 6.8.5.11.
6.44.3.8 From QEI to ECAP
ECAP Input Noise Filter
The architecture of ECAP input noise filter is similar to that one used for QEI. With 6 sampling-rate
options, it supports a wide range of filtering noise, the duration of filtered noise and the duration of the
signal that is guaranteed to be sampled.
The detailed setting of modulation is described in TRM section 6.14.5.1.
6.44.3.9 From TIMER to QEI
TIMER TIF Event to QEI
When QEI bit HOLDCNT(QEI_CTL[24]) set, the CNT(QEI_CNT[31:0]) content will be captured into
QEI Counter Hold Register CNTHOLD(QEI_CNTHOLD[31:0]), the data will be held until the next
May 08, 2020
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HOLDCNT (QEI_CTL[24]) trigger comes. The bit HOLDCNT can be set by writing 1 to it or the rising
edge of timers interrupt flags TIF (TIMERx_INTSTS[0])The detailed setting of modulation is described
in TRM section 6.14.5.11.
The detailed setting of modulation is described in TRM section 6.8.5.1.
M480 SERIES DATASHEET
May 08, 2020
Page 405 of 523
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M480
7
APPLICATION CIRCUIT
7.1 Power Supply Scheme with External VREF
as close to AVDD as possible
L=30Z
EXT_PWR
1uF+0.1uF+0.01uF
AVDD
VDD
as close to LDO as possible
EXT_PWR
AVSS
10uF
LDO_CAP
VSS
as close to the EXT_PWR as possible
2.2uF
as close to VREF as possible
L=30Z
2.2uF+1uF+470pF
VREF
VBAT
10uF+0.1uF
AVSS
as close to VBAT as possible
0.1uF
VSS
L=30Z
as close to VDD as possible
VDD
VDDIO
VSS
VSS
as close to VDDIO as possible
0.1uF
0.1uF*N
EXT_VSS
EXT_VSS
M480 SERIES DATASHEET
May 08, 2020
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M480
7.2 Power Supply Scheme with Internal VREF
as close to AVDD as possible
L=30Z
EXT_PWR
1uF+0.1uF+0.01uF
AVDD
VDD
as close to LDO as possible
EXT_PWR
AVSS
L=30Z
VSS
as close to the EXT_PWR as possible
2.2uF
as close to VREF as possible
VREF
10uF+0.1uF
10uF
LDO_CAP
VBAT
0.1uF
AVSS
as close to VBAT as possible
0.1uF
VSS
as close to VDD as possible
VDD
VDDIO
VSS
VSS
as close to VDDIO as possible
0.1uF
0.1uF*N
EXT_VSS
EXT_VSS
M480 SERIES DATASHEET
May 08, 2020
Page 407 of 523
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M480
7.3 Power Supply Scheme with VREF and External RTC with Battery Power
EXT_PWR
Peripheral
EXT_PWR
L=30Z
PC.0
AVDD
Battery
Power
4.7K
4.7K
Wake up
I2C_SCL
CLK
VDD
DIO
VSS
AVSS
L=30Z
1uF+0.1uF+0.01uF
I2C_SDA
External RTC L=30Z
as close to AVDD as possible
L=30Z
VDD
VREF
10uF+0.1uF
VSS
as close to the EXT_PWR as possible
L=30Z
0.1uF+4.7uF
2.2uF+1uF+470pF
L=30Z
as close to VDD as possible
L=30Z
as close to VREF as possible
VDDIO
LDO_CAP
as close to VDDIO as possible
VSS
0.1uF
VSS
L=30Z
2.2uF*N
L=30Z
L=30Z
HSUSB_VDD33
as close to LDO as possible
HSUSB_VDD12_CAP
L=30Z
VDD
HSUSB_VRES
200
EXT_VSS
L=30Z
0.1uF*N
VSS
HSUSB_VSS
as close to VDD as possible
EXT_VSS
1uF
0.1uF
L=30Z
as close to HSUSB_VDD33 as possible
M480 SERIES DATASHEET
May 08, 2020
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M480
7.4 Power Supply Scheme with VREF and Internal RTC with Battery Power
as close to AVDD as possible
L=30Z
EXT_PWR
1uF+0.1uF+0.01uF
AVDD
VDD
as close to LDO as possible
EXT_PWR
AVSS
10uF
LDO_CAP
VSS
as close to the EXT_PWR as possible
2.2uF
as close to VREF as possible
L=30Z
2.2uF+1uF+470pF
VREF
VBAT
10uF+0.1uF
AVSS
as close to VBAT as possible
0.1uF
VSS
L=30Z
EXT_Battery
as close to VDD as possible
VDD
VDDIO
VSS
VSS
as close to VDDIO as possible
0.1uF
0.1uF*N
EXT_VSS
EXT_VSS
M480 SERIES DATASHEET
May 08, 2020
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M480
7.5 Peripheral Application Scheme
DVCC
5V
USB Full Speed
OTG Slot Power Switch
HSUSB_VDD33
(OTG Host)
0.1uF
5V
33R
33R
USB_VBUS
USB_DUSB_D+
USB_ID
HSUSB_VBUS
HSUSB_D-
USB High Speed
OTG Slot
HSUSB_D+
HSUSB_ID
HSUSB_VRES
HSUSB_VDD12_CAP
HSUSB_VSS
DVCC
100K
Power Switch
(OTG Host)
100K
200
1uF
VDD
ICE_DAT
SWD
Interface
ICE_CLK
nRESET
VSS
DVCC
M480 Series
20pF
XT1_IN
SPI_SS
SPI_CLK
SPI_MISO
SPI_MOSI
20pF
X32_IN
SPI Device
4.7K
4.7K
I2C_SCL
CLK
VDD
I2C_SDA
DIO
VSS
32.768 kHz
crystal
20pF
VSS
DVCC
XT1_OUT
Crystal
VDD
DVCC
4~24 MHz
crystal
20pF
CS
CLK
MISO
MOSI
I2C Device
DVCC
X32_OUT
SC_PWR
M480 SERIES DATASHEET
DVCC
Reset
Circuit
10K
nRESET
Smart Card Slot
SC_RST
SC_CLK
SC_DAT
SC_nCD
10uF/10V
CAN Transceiver
CAN_TX
D
CAN_H
CAN_RX
R
CAN_L
ODB Port
CAN
LDO_CAP
LDO
2.2uF
64K x 16-bit
SRAM
Addr[15:0]
Q
nOE
EBI_nRD
nWE
EBI_nWR
Data[15:0]
May 08, 2020
UART_TXD
TIN
RIN
TOUT
UART
EBI_ALE
EBI_nCS
nLB
ROUT
D
nCE
nUB
UART_RXD
LATCH
En
EBI
RS 232 Transceiver PC COM Port
Audio codec
IS
2
EBI_nWRL
EBI_nWRH
Line In
2
IC
NAU88L25
Line Out
EBI_AD[15:0]
Page 410 of 523
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M480
Note 1: USB_ID, HSUSB _ID could be floating using USB or USB HS without OTG.
Note 2: It is recommended to use 100 kΩ pull-up resistor on both ICE_DAT and ICE_CLK pin.
Note 3: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin.
M480 SERIES DATASHEET
May 08, 2020
Page 411 of 523
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M480
8
ELECTRICAL CHARACTERISTICS FOR M48XID/M487KMCAN
8.1 Absolute Maximum Ratings
8.1.1
Voltage Characteristics
Parameter
Symbol
Min
Max
Unit
VDD-VSS[*1]
DC Power Supply
-0.3
4
V
VDDIO-VSS
VDDIO Power Supply
-0.3
4
V
|VDDX – VDD|
Variations between different power pins
50
mV
|VDD –AVDD|
Allowed voltage difference for VDD and AVDD
50
mV
|VSSX - VSS|
Variations between different ground pins
50
mV
|VSS - AVSS|
Allowed voltage difference for VSS and AVSS
50
mV
Input Voltage on 5V-tolerance GPIO
5.5
V
Input Voltage on RTC domain (PF.6 ~ PF.11)
VDD
V
Input Voltage on any other pin[*2]
VDD
V
VIN
Note:
1. All main power (VDD, AVDD) and ground (VSS, AVSS) pins must always be connected to the external power supply, in
the permitted range.
2. Non 5V-tolerance PIN: PA.8 ~ 15; PB.0 ~ 15; PD.10, 11, 12; PF.2, 3, 4, 5; All USB High Speed PIN and nRESET
PIN.
Table 8.1-1 Voltage Characteristics
8.1.2
Current Characteristics
Parameter
IDD
Maximum Current into VDD
200
IDDIO
Maximum Current into VDDIO
100
ISS
Maximum Current out of VSS
100
Maximum Current sunk by a I/O Pin
20
Maximum Current Sourced by a I/O Pin
20
Maximum Current Sunk by Total I/O Pins
100
Maximum Current Sourced by Total I/O Pins
100
M480 SERIES DATASHEET
Symbol
Min
Max
Unit
mA
IIO
Table 8.1-2 Current Characteristics
8.1.3
Thermal Characteristics
Symbol
Parameter
Min
Max
TA
Operating Temperature ((M48xID))
-40
105
TA
Operating Temperature (M487KMCAN)
-40
85
TJ
Junction temperature
-40
125
TST
Storage Temperature
-65
150
May 08, 2020
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Unit
C
Rev 3.00
M480
Table 8.1-3 Thermal Characteristics
8.1.4
EMC Characteristics
Symbol
Parameter
Conditions
1.
Fast transient voltage burst limits to be
applied through 100 pF + 47uF on VDD and VSS
pins to induce a functional disturbance
VEFTB
Maximum
Value
Unit
VDD = 3.3 V, LQFP144, TA = +25
°C, fHCLK = 160 MHz
4.4
kV
2.
to be applied through 2.2uF on LDO_Pin
and VSS pins
Table 8.1-4 EMS Characteristics
Symbol
LU
Parameter
Static latch-up class
Conditions
TA
Value
Unit
400mA
mA
Note:
1. Guaranteed by characterization results, not tested in production.
Table 8.1-5 Electrical Characteristics
M480 SERIES DATASHEET
May 08, 2020
Page 413 of 523
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M480
8.2 General Operating Conditions
(VDD-VSS = 1.8 ~ 3.6V, TA = 25C, HCLK = 192 MHz unless otherwise specified.)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
192
MHz
fHCLK
Internal AHB clock frequency
VDD
Operation Voltage (M48xID)
1.8
3.6
VDD
Operation Voltage (M487KMCAN)
2.7
3.6
AVDD
Analog Operation Voltage
VDDIO
Power supply for PA.0 ~ 5
VLDO
LDO Output Voltage
VBG
Band-gap Voltage
CLDO
LDO Output capacitance on each
pin
VDD
V
1.8
1.26
VDD = 1.8 V ~ 3.6 V
1.17
1.23
2.2
VDD rise time rate
tVDD
3.6
10
-
BOD Disabled, LVR Enabled[*1]
400
-
BOD Disabled, LVR Enabled[*2]
500
BOD 1.6V Enabled
80
BOD 3.0V Enabled
80
uF
VDD fall time rate
Note:
1. LVR in active mode
2. LVR in low power mode
M480 SERIES DATASHEET
May 08, 2020
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M480
8.3 DC Electrical Characteristics
8.3.1
Typical Current Consumption(M487xID)
ALL GPIO pins are in push pull mode, output high.
LDO = 1.26V
The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature (T A), and
the typical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
VDD = AVDD = VDDIO
When the peripherals are enabled HCLK is the system clock, fPCLK0, 1 = fHCLK/2.
Program run while(1){} from Flash.
Typ
Symbol
Conditions
Normal Run, executed from Flash,
VDD = 3.3V, all peripherals disable
Normal run, External clock,
executed from Flash, VDD = 3.3V,
all peripherals enabled
HXT/LXT
192 MHz
12 MHz
-
V
34.00
160 MHz
12 MHz
-
V
28.76
144 MHz
12 MHz
-
V
26.00
120 MHz
12 MHz
-
V
22.21
12 MHz
12 MHz
-
-
3.49
192 MHz
-
12 MHz
V
33.29
160 MHz
-
12 MHz
V
28.11
144 MHz
-
12 MHz
V
25.51
120 MHz
-
12 MHz
V
21.59
HIRC/LIRC
PLL
Unit
TA = 25 °C
12 MHz
-
12 MHz
-
2.98
32.768 kHz
32.768 kHz
-
-
0.57
10 kHz
-
10 kHz
-
0.57
192 MHz
-
12 MHz
V
70.05
160 MHz
-
12 MHz
V
58.99
144 MHz
-
12 MHz
V
53.43
120 MHz
-
12 MHz
V
45.04
12 MHz
-
12 MHz
-
5.60
192 MHz
12 MHz
-
V
70.70
160 MHz
12 MHz
-
V
60.41
144 MHz
12 MHz
-
V
53.75
120 MHz
12 MHz
-
V
46.04
12 MHz
12 MHz
-
-
5.85
32.768 kHz
32.768 kHz
-
-
0.58
10 kHz
-
10 kHz
-
0.57
mA
Table 8.3-1 Current Consumption in Normal Run Mode
May 08, 2020
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M480 SERIES DATASHEET
IDD
FHCLK
M480
90
80
-40℃
IDD Current(mA)
70
-20℃
60
192M
180M
160M
105℃
144M
85℃
0
120M
10
90M
65℃
60M
20
30M
45℃
20M
30
12M
25℃
6M
40
4M
0℃
2M
50
125℃
CPU Frequency(Hz)
Figure 8.3-1 Current Consumption Versus Temperature in Normal Run Mode, VDD = 3.3V , All
Peripherals Disabled, PLL Source From HIRC
90
80
-40℃
-20℃
60
192M
180M
105℃
160M
85℃
0
144M
10
120M
65℃
90M
20
60M
45℃
30M
30
20M
25℃
12M
40
6M
0℃
4M
50
2M
M480 SERIES DATASHEET
IDD Current(mA)
70
125℃
CPU Frequency(Hz)
Figure 8.3-2 Current Consumption Versus Temperature in Normal Run Mode, VDD = 3.3V , All
Peripherals Enabled, PLL Source From HIRC
May 08, 2020
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M480
90
80
-40℃
IDD Current(mA)
70
-20℃
60
192M
180M
160M
105℃
144M
85℃
0
120M
10
90M
65℃
60M
20
30M
45℃
20M
30
12M
25℃
6M
40
4M
0℃
2M
50
125℃
CPU Frequency(Hz)
Figure 8.3-3 Current Consumption Versus Temperature in Normal Run Mode, VDD = 3.3V , All
Peripherals Disabled, PLL Source From HXT
90
80
-40℃
-20℃
60
192M
180M
105℃
160M
0
144M
85℃
120M
10
90M
65℃
60M
20
30M
45℃
20M
30
12M
25℃
6M
40
4M
0℃
2M
50
M480 SERIES DATASHEET
IDD Current(mA)
70
125℃
CPU Frequency(Hz)
Figure 8.3-4 Current Consumption Versus Temperature in Normal Run Mode, VDD = 3.3V , All
Peripherals Enabled, PLL Source From HXT
May 08, 2020
Page 417 of 523
Rev 3.00
M480
Typ
Symbol
Conditions
Idle mode, executed from Flash,
VDD = 3.3V, all peripherals disable
IDD
Idle
mode,
External
clock,
executed from Flash, VDD = 3.3V,
all peripherals enabled
M480 SERIES DATASHEET
FHCLK
HXT/LXT
192 MHz
12 MHz
-
V
10.32
160 MHz
12 MHz
-
V
8.95
144 MHz
12 MHz
-
V
8.23
120 MHz
12 MHz
-
V
7.23
12 MHz
12 MHz
-
-
1.98
192 MHz
-
12 MHz
V
9.76
160 MHz
-
12 MHz
V
8.40
144 MHz
-
12 MHz
V
7.72
120 MHz
-
12 MHz
V
6.70
12 MHz
-
12 MHz
-
1.47
32.768 kHz
32.768 kHz
-
-
0.57
10 kHz
-
10 kHz
-
0.57
192 MHz
-
12 MHz
V
49.64
160 MHz
-
12 MHz
V
41.82
144 MHz
-
12 MHz
V
37.89
120 MHz
-
12 MHz
V
31.96
12 MHz
-
12 MHz
-
4.03
192 MHz
12 MHz
-
V
50.36
160 MHz
12 MHz
-
V
42.75
144 MHz
12 MHz
-
V
38.29
120 MHz
12 MHz
-
V
32.70
12 MHz
12 MHz
-
-
4.52
32.768 kHz
32.768 kHz
-
-
0.58
10 kHz
-
10 kHz
-
0.57
HIRC/LIRC
PLL
Unit
TA = 25 °C
mA
Table 8.3-2 Current Consumption in Idle Mode
May 08, 2020
Page 418 of 523
Rev 3.00
M480
IDD Current(mA)
70
60
-40℃
50
-20℃
40
0℃
25℃
30
45℃
20
65℃
10
85℃
0
192M
180M
160M
144M
120M
90M
60M
30M
20M
12M
6M
4M
2M
105℃
125℃
CPU Frequency(Hz)
Figure 8.3-5 Current Consumption Versus Temperature in Idle Mode, VDD = 3.3V , All Peripherals
Disabled, PLL Source From HIRC
60
-40℃
50
-20℃
40
0℃
25℃
30
M480 SERIES DATASHEET
IDD Current(mA)
70
45℃
20
65℃
10
85℃
0
192M
180M
160M
144M
120M
90M
60M
30M
20M
12M
6M
4M
2M
105℃
125℃
CPU Frequency(Hz)
Figure 8.3-6 Current Consumption Versus Temperature in Idle Mode, VDD = 3.3V , All Peripherals
Enabled, PLL Source From HIRC
May 08, 2020
Page 419 of 523
Rev 3.00
M480
IDD Current(mA)
70
60
-40℃
50
-20℃
40
0℃
25℃
30
45℃
20
65℃
10
85℃
0
192M
180M
160M
144M
120M
90M
60M
30M
20M
12M
6M
4M
2M
105℃
125℃
CPU Frequency(Hz)
Figure 8.3-7 Current Consumption Versus Temperature in Idle Mode, VDD = 3.3V , All Peripherals
Disabled, PLL Source From HXT
M480 SERIES DATASHEET
IDD Current(mA)
70
60
-40℃
50
-20℃
40
0℃
25℃
30
45℃
20
65℃
10
85℃
0
192M
180M
160M
144M
120M
90M
60M
30M
20M
12M
6M
4M
2M
105℃
125℃
CPU Frequency(Hz)
Figure 8.3-8 Current Consumption Versus Temperature in Idle Mode, VDD = 3.3V , All Peripherals
Enabled, PLL Source From HXT
Typ
Symbol
Conditions
LXT
LIRC
PLL
Unit
TA = 25 °C
May 08, 2020
Page 420 of 523
Rev 3.00
M480
Fast wake-up Power-down mode, VDD = 3.3V, all peripherals
disabled
-
-
-
0.49
Fast wake-up Power-down mode, VDD = 3.3V,
RTC/WDT/Timer/UART enable
V
-
-
0.49
IDD_FWPD
mA
Fast wake-up Power-down mode, VDD = 3.3V, RTC/WDT/Timer
enable
-
V
-
0.49
Fast wake-up Power-down mode, VDD = 3.3V, WDT/Timer use LIRC,
RTC/UART use LXT
V
V
-
0.49
Power-down mode, VDD = 3.3V, all peripherals disabled
-
-
-
0.37
Power-down mode, VDD = 3.3V, RTC/WDT/Timer/UART enable
V
-
-
0.37
IDD_PD
mA
Power-down mode, VDD = 3.3V, RTC/WDT/Timer use LIRCT
-
V
-
0.37
Power-down mode, VDD = 3.3V, WDT/Timer use LIRC, RTC/UART
use LX
V
V
-
0.37
Low leakage Power-down mode, VDD = 3.3V, all peripherals disabled
-
-
-
0.14
Low leakage Power-down mode, VDD = 3.3V,
RTC/WDT/Timer/UART enable
V
-
-
0.37
IDD_LLPD
IDD_SPD1
-
V
-
0.37
Low leakage Power-down mode, VDD = 3.3V, WDT/Timer use
LIRC, RTC/UART use LX
V
V
-
0.37
Standby Power-down mode(SPD0), VDD = 3.3V, all peripherals
disabled
-
-
-
0.04
Standby Power-down mode(SPD0), VDD = 3.3V, RTC enable
V
-
-
0.04
Standby Power-down mode(SPD0), VDD = 3.3V, RTC enable
-
V
-
0.04
Standby Power-down mode(SPD1), VDD = 3.3V, all peripherals
disabled
-
-
-
0.03
Standby Power-down mode(SPD1), VDD = 3.3V, RTC enable
V
-
-
0.03
Standby Power-down mode(SPD1), VDD = 3.3V, RTC enable
-
V
-
0.03
May 08, 2020
Page 421 of 523
mA
mA
Rev 3.00
M480 SERIES DATASHEET
IDD_SPD0
mA
Low leakage Power-down mode, VDD = 3.3V, RTC/WDT/Timer
enable
M480
IDD_DPD
Deep Power-down mode(DPD), VDD = 3.3V, all peripherals disabled
-
-
-
0.95
uA
Note:
1.
VDD = AVDD = VDDIO = 3.3V
Table 8.3-3 Chip Current Consumption in Power-down Mode
8.3.2
Typical Current Consumption(M487KMCAN)
Normal Run Mode (CPU Normal Run that executed code from SPI Flash thru SPIM)
ALL GPIO pins are in push pull mode, output high.
LDO = 1.26V
The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature (T A), and
the typical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
VDD = AVDD = VDDIO
When the peripherals are enabled HCLK is the system clock, f PCLK0, 1 = fHCLK/2.
Program run while(1){} from SPI Flash.
Typ
Symbol
Conditions
M480 SERIES DATASHEET
Normal Run, executed from SPI
Flash, VDD = 3.3V, all peripherals
disable
IDD
Normal run, External clock,
executed from SPI Flash, VDD =
3.3V, all peripherals enabled
FHCLK
HXT/LXT
192 MHz
12 MHz
-
V
50.1
160 MHz
12 MHz
-
V
42.2
144 MHz
12 MHz
-
V
38.3
120 MHz
12 MHz
-
V
33.2
192 MHz
-
12 MHz
V
50.1
160 MHz
-
12 MHz
V
42.2
144 MHz
-
12 MHz
V
38.3
120 MHz
-
12 MHz
V
33.2
192 MHz
-
12 MHz
V
72.5
160 MHz
-
12 MHz
V
60.9
144 MHz
-
12 MHz
V
55.1
120 MHz
-
12 MHz
V
47.3
192 MHz
12 MHz
-
V
72.3
160 MHz
12 MHz
-
V
60.7
144 MHz
12 MHz
-
V
54.9
120 MHz
12 MHz
-
V
47.1
HIRC/LIRC
PLL
Unit
TA = 25 °C
mA
Table 8.3-4 Current Consumption in Normal Run Mode (Cache-on)
May 08, 2020
Page 422 of 523
Rev 3.00
M480
Typ
Symbol
Conditions
Normal Run, executed from SPI
Flash, VDD = 3.3V, all peripherals
disable
IDD
Normal run, External clock,
executed from SPI Flash, VDD =
3.3V, all peripherals enabled
FHCLK
HXT/LXT
192 MHz
12 MHz
-
V
35.5
160 MHz
12 MHz
-
V
30.3
144 MHz
12 MHz
-
V
27.7
120 MHz
12 MHz
-
V
24.8
192 MHz
-
12 MHz
V
35.5
160 MHz
-
12 MHz
V
30.3
144 MHz
-
12 MHz
V
27.7
120 MHz
-
12 MHz
V
24.8
192 MHz
-
12 MHz
V
57.7
160 MHz
-
12 MHz
V
48.9
144 MHz
-
12 MHz
V
44.4
120 MHz
-
12 MHz
V
38.6
192 MHz
12 MHz
-
V
57.4
160 MHz
12 MHz
-
V
48.5
144 MHz
12 MHz
-
V
44.1
120 MHz
12 MHz
-
V
38.4
HIRC/LIRC
PLL
Unit
TA = 25 °C
mA
Table 8.3-5 Current Consumption in Normal Run Mode (Cache-off)
Typ
Conditions
Idle mode, executed from SPI
Flash, VDD
= 3.3V, all
peripherals disable
IDD
Idle
mode,
External
clock,
executed from SPI Flash, VDD =
3.3V, all peripherals enabled
May 08, 2020
FHCLK
HXT/LXT
192 MHz
12 MHz
-
V
26.7
160 MHz
12 MHz
-
V
22.6
144 MHz
12 MHz
-
V
20.5
120 MHz
12 MHz
-
V
18.4
192 MHz
-
12 MHz
V
26.7
160 MHz
-
12 MHz
V
22.6
144 MHz
-
12 MHz
V
20.5
120 MHz
-
12 MHz
V
18.4
192 MHz
-
12 MHz
V
51.7
160 MHz
-
12 MHz
V
43.5
144 MHz
-
12 MHz
V
39.4
120 MHz
-
12 MHz
V
34.1
192 MHz
12 MHz
-
V
51.3
160 MHz
12 MHz
-
V
43.1
HIRC/LIRC
PLL
Unit
TA = 25 °C
Page 423 of 523
mA
Rev 3.00
M480 SERIES DATASHEET
Symbol
M480
144 MHz
12 MHz
-
V
39.0
120 MHz
12 MHz
-
V
33.7
Table 8.3-6 Current Consumption in Idle Mode (Cache-on)
Idle Mode (CPU Keeps in Idle Mode that executed code from SPI Flash thru SPIM and SPI Flash
enters the Standby by /CS pin = High)
Typ
Symbol
Idle mode, executed from Flash,
VDD = 3.3V, all peripherals disable
IDD
Idle
mode,
External
clock,
executed from Flash, VDD = 3.3V,
all peripherals enabled
M480 SERIES DATASHEET
FHCLK
HXT/LXT
192 MHz
12 MHz
-
V
13.98
160 MHz
12 MHz
-
V
11.98
144 MHz
12 MHz
-
V
10.98
120 MHz
12 MHz
-
V
10.43
192 MHz
-
12 MHz
V
13.98
160 MHz
-
12 MHz
V
11.98
144 MHz
-
12 MHz
V
10.98
120 MHz
-
12 MHz
V
10.44
192 MHz
-
12 MHz
V
39.17
160 MHz
-
12 MHz
V
32.97
144 MHz
-
12 MHz
V
29.87
120 MHz
-
12 MHz
V
26.16
192 MHz
12 MHz
-
V
38.71
160 MHz
12 MHz
-
V
32.49
144 MHz
12 MHz
-
V
29.41
120 MHz
12 MHz
-
V
25.68
Conditions
HIRC/LIRC
PLL
Unit
TA = 25 °C
mA
Table 8.3-7 Current Consumption in Idle Mode (Cache-off)
Power-down Mode (CPU runs the Power-down Mode that executed code from embedded Flash after
SPI Flash entered the power-down by the Power-down command (B9h))
Typ
Symbol
Conditions
LXT
LIRC
PLL
Unit
TA = 25 °C
Fast wake-up Power-down mode, VDD = 3.3V, all peripherals
disabled
-
-
-
0.49
IDD_FWPD
mA
Fast wake-up Power-down mode, VDD = 3.3V,
RTC/WDT/Timer/UART enable
May 08, 2020
Page 424 of 523
V
-
-
0.49
Rev 3.00
M480
Fast wake-up Power-down mode, VDD = 3.3V, RTC/WDT/Timer
enable
-
V
-
0.49
Fast wake-up Power-down mode, VDD = 3.3V, WDT/Timer use LIRC,
RTC/UART use LXT
V
V
-
0.49
Power-down mode, VDD = 3.3V, all peripherals disabled
-
-
-
0.37
Power-down mode, VDD = 3.3V, RTC/WDT/Timer/UART enable
V
-
-
0.37
IDD_PD
mA
Power-down mode, VDD = 3.3V, RTC/WDT/Timer use LIRCT
-
V
-
0.37
Power-down mode, VDD = 3.3V, WDT/Timer use LIRC, RTC/UART
use LX
V
V
-
0.37
Low leakage Power-down mode, VDD = 3.3V, all peripherals disabled
-
-
-
0.14
Low leakage Power-down mode, VDD = 3.3V,
RTC/WDT/Timer/UART enable
V
-
-
0.37
IDD_LLPD
mA
IDD_SPD1
-
V
-
0.37
Low leakage Power-down mode, VDD = 3.3V, WDT/Timer use
LIRC, RTC/UART use LX
V
V
-
0.37
Standby Power-down mode(SPD0), VDD = 3.3V, all peripherals
disabled
-
-
-
0.04
Standby Power-down mode(SPD0), VDD = 3.3V, RTC enable
V
-
-
0.04
Standby Power-down mode(SPD0), VDD = 3.3V, RTC enable
-
V
-
0.04
Standby Power-down mode(SPD1), VDD = 3.3V, all peripherals
disabled
-
-
-
0.04
Standby Power-down mode(SPD1), VDD = 3.3V, RTC enable
V
-
-
0.04
Standby Power-down mode(SPD1), VDD = 3.3V, RTC enable
-
V
-
0.04
mA
mA
Note:
2.
VDD = AVDD = VDDIO = 3.3V
Table 8.3-8 Chip Current Consumption in Power-down Mode
May 08, 2020
Page 425 of 523
Rev 3.00
M480 SERIES DATASHEET
IDD_SPD0
Low leakage Power-down mode, VDD = 3.3V, RTC/WDT/Timer
enable
M480
8.3.3
On-chip Peripheral Current Consumption
ALL GPIO pins are in push pull mode, output high.
LDO = 1.26V
The typical values for TA= 25 °C and VDD = AVDD = 3.3 V unless otherwise specified.
When the peripherals are enabled HCLK is the system clock, f HCLK = 192 MHz, fPCLK0, 1 = fHCLK/2.
Peripheral
IDD
DAC
58.4
ADC
338.6
ACMP01
85.2
OPA
123.3
QEI0
74.2
QEI1
81.9
ECAP0
74.3
ECAP1
69.8
EPWM0
907
EPWM1
896.5
BPWM0
263.8
BPWM1
245.2
WDT
49.6
SD0
1416.1
SD1
1263.6
SC0
66.6
SC1
76.6
SC2
73.6
I2S0
102.1
SPIM
14681.1
QSPI0
291.1
SPI0
315.5
SPI1
261.2
SPI2
137.2
SPI3
138.7
UART0
150.6
UART1
209.1
UART2
220.0
Unit
uA
M480 SERIES DATASHEET
May 08, 2020
Page 426 of 523
Rev 3.00
M480
UART3
160.5
UART4
186.5
UART5
177.5
I2C0
34.4
2
I C1
26.6
I2C2
32.7
CAN0
280.5
CAN1
257.6
USCI0
211.9
USCI1
205.4
EBI
209.6
TMR0
140.5
TMR1
130.1
TMR2
127.1
TMR3
121.2
USB HS OTG
248.7
USB FS OTG
503.1
Crypto
1550.4
EMAC
1768.1
Note:
8.3.4
Guaranteed by characterization results, not tested in production.
Wakeup Time
The wakeup times given in Table 8.3-9 is measured on a wakeup phase with a 12 MHz HIRC
oscillator. The clock source used to wake up the device depends from the current operating
mode:
–
Fast-wakeup, power down, low leakage Power-down mode: the clock source is the
RC oscillator
–
Standby and Deep Power-down mode: the clock source is the clock that was set
before entering Sleep mode.
The wakeup times are measured from the wakeup event to the point in which the application
code reads the first instruction.
The clock source is the RC oscillator from HIRC
Symbol
Parameter
Typ
Unit
5 Cycles
tWU_IDLE
Wakeup from IDLE mode
tWU_FWPD
Wakeup from Fast-wakeup power down mode
µs
May 08, 2020
Page 427 of 523
6
Rev 3.00
M480 SERIES DATASHEET
1.
M480
tWU_NPD
Wakeup from normal power down mode
12
tWU_LLPD
Wakeup from low leakage power down mode
54
tWU_SPD0
Wakeup from Standby Power-down mode 0 (SPD0)
527
tWU_SPD1
Wakeup from Standby Power-down mode 1 (SPD1)
527
tWU_DPD
Deep Power-down mode (DPD)
489
Table 8.3-9 Low-power Mode Wakeup Timings
8.3.5
PIN DC Characteristics
Symbol Parameter
VIL1
VIH1
Min.
Typ.
Max.
Unit
Test Conditions
0.8
V
VDD = VDDIO = 3.6 V
0.56
V
VDD = VDDIO = 1.8 V
2
V
VDD = VDDIO = 3.6V
1.04
V
VDD = VDDIO = 1.8V
V
VDD = VDDIO = 3.6V
Input Low Voltage (TTL input)
Input High Voltage (TTL input)
0.3*VDD
VIL2
Input Low Voltage (Schmitt input)
0.3*VDD
VDD = VDDIO = 1.8V
0.7*VDD
VIH2
VDD = VDDIO = 3.6V
Input High Voltage (Schmitt input)
V
0.7*VDD
M480 SERIES DATASHEET
VHY
Hysteresis voltage of (Schmitt input)
ILK
Input Leakage Current
RPU
Input Pull Up Resistor
RPD
VDD = VDDIO = 1.8V
0.2VDD
V
A
VDD = VDDIO = 3.6V, 0 < VIN <
VDD, Open-drain or input only
mode
50
KΩ
VDD = VDDIO = 3.3V
52
KΩ
VDD = VDDIO = 1.8V
50
KΩ
VDD = VDDIO = 3.3V
52
KΩ
VDD = VDDIO = 1.8V
-1
1
Input Pull down Resistor
Table 8.3-10 PIN Input Characteristics
Symbol Parameter
Min.
Typ.
Max.
Unit
Test Conditions
-18
mA
VDD = VDDIO = 3.3V
ISR4
Source Current
ISR5
-10
mA
VDD = VDDIO = 1.8V
ISR6
(Push-pull Mode, Set GPIO to output HIGH,
Apply GPIO pin VIN=(VDD-0.4)V for VDD and
measure the source current)
-8
mA
VDD = VDDIO = 1.8V
ISK1
Sink Current
17
mA
VDD = VDDIO = 3.3V
ISK2
10
mA
VDD = VDDIO = 1.8V
ISK3
(Push-pull Mode, Set GPIO to output LOW, Apply
GPIO pin VIN=(VSS+0.4)V for VSS and measure
the source current)
8
mA
VDD = VDDIO = 1.8V
CIO
I/O pin capacitance
5
pF
May 08, 2020
Page 428 of 523
Rev 3.00
M480
Table 8.3-11 PIN Output Characteristics
Symbol Parameter
VILR
VIHR
Min.
Typ.
Negative going threshold
(Schmitt input), nRESET
Positive going threshold
0.7*VDD
(Schmitt Input), nRESET
Max.
Unit
Test Conditions
0.3*VDD
V
VDD = 3.3V
V
VDD = 3.3V
RRST
Internal nRESET pin pull up resistor
50
KΩ
tFR1
nRESET input filtered time
32
uS
tFR2
nRESET input filtered time under SPD and DPD
mode
300
nS
VDD = 3.3V,
Table 8.3-12 nRESET PIN Characteristics
M480 SERIES DATASHEET
May 08, 2020
Page 429 of 523
Rev 3.00
M480
8.4 AC Electrical Characteristics
8.4.1
External 4~24 MHz High Speed Crystal (HXT) Characteristics
TA= 25 °C and VDD = 3.3 V unless otherwise specified.
Specifications
Sym.
Parameter
Test Condition
Min.
Typ.
Unit
3.6
V
VDD
Operating Voltage
Rf
Feedback resister
fHXT
Oscillator frequency
4
24
THXT
Temperature Range
-40
105
IHXT_INV
IHXT_GM
M480 SERIES DATASHEET
TS_GM
TS_INV
1.8
Max.
kΩ
1000
MHz
VDD = 1.8 ~ 3.6V
650
4 MHz
Current Consumption
1600
12 MHz
(INV-type Crystal)
2000
16 MHz
4000
24 MHz
160
4 MHz
Current Consumption
280
12 MHz
(GM-type Crystal)
400
16 MHz
600
24 MHz
1545
1752
4 MHz, -40 °C
1630
1757
4 MHz, 25 °C
1054
1988
4 MHz, 105 °C
484
512
12 MHz, -40 °C
484
544
12 MHz, 25 °C
386
606
12 MHz, 105 °C
349
375
16 MHz, -40 °C
337
399
16 MHz, 25 °C
281
444
16 MHz, 105 °C
259
303
24 MHz, -40 °C
248
330
24 MHz, 25 °C
210
403
24 MHz, 105 °C
1490
23432
4 MHz, -40 °C
1479
2352
4 MHz, 25 °C
1052
2105
4 MHz, 105 °C
464
558
12 MHz, -40 °C
481
554
12 MHz, 25 °C
Stable time (GM-type)
Stable time (INV-type)
May 08, 2020
Page 430 of 523
Rev 3.00
M480
Specifications
Sym.
Parameter
Test Condition
Min.
Clock Duty
Typ.
Max.
Unit
417
663
12 MHz, 105 °C
317
420
16 MHz, -40 °C
326
407
16 MHz, 25 °C
290
472
16 MHz, 105 °C
226
382
24 MHz, -40 °C
228
388
24 MHz, 25 °C
210
441
24 MHz, 105 °C
45
50
55
%
Table 8.4-1 External 4~24 MHz High Speed Crystal (HXT) Oscillator
8.4.1.1
Typical Crystal Application Circuits
Crystal
4 MHz ~ 24 MHz
C1
C2
R
20pF
20pF
without
XT_OUT
XT_IN
M480 SERIES DATASHEET
R1
C2
C1
Figure 8.4-1 Typical Crystal Application Circuit
8.4.2
External 4~24 MHz High Speed Clock Input (OSC) Characteristics
Specifications
Sym.
Parameter
Test Condition
Min.
Typ.
Max.
Unit
tCHCX
Clock High Time
18
nS
tCLCX
Clock Low Time
18
nS
tCLCH
Clock Rise Time
10
nS
tCHCL
Clock Fall Time
10
nS
May 08, 2020
Page 431 of 523
Rev 3.00
M480
Specifications
Sym.
Parameter
Test Condition
Min.
VIH
Input High Voltage
VIL
Input Low Voltage
Typ.
Max.
Unit
0.7*VDD
V
0.3*VDD
V
tCLCL
tCLCH
VIH
90%
tCLCX
10%
VIL
tCHCL
tCHCX
Note:
1. Guaranteed by design, not tested in production
2. Duty cycle is 50%.
8.4.3
External 32.768 kHz Low Speed Crystal (LXT) Characteristics
Specifications
Sym.
Parameter
Test Condition
Min.
VDD
Operation Voltage
fLXT
Oscillator frequency
TLXT
Temperature
ILXT
Operating current
1.8
Max.
Unit
3.6
V
32.768
-40
Duty cycle
M480 SERIES DATASHEET
TS
Typ.
45
Stable Time
kHz
105
C
0.5
A
55
%
500
ms
VDD = 1.8 ~ 3.6 V
VDD = 3.3V
Table 8.4-2 External 32.768 kHz Crystal
8.4.3.1
Typical Crystal Application Circuits
Crystal
32.768 kHz
May 08, 2020
C1
C2
R1
20pF
20pF
without
Page 432 of 523
Rev 3.00
M480
XT_OUT
XT_IN
R1
C2
C1
Figure 8.4-2 Typical Crystal Application Circuit
8.4.4
External 32.768 kHz Low Speed Clock Input (OSC) Characteristics
Specifications
Parameter
Sym.
Test Condition
Min.
Typ.
Max.
Unit
Clock High Time
tCHCX
450
-
-
nS
Clock Low Time
tCLCX
450
-
-
nS
Clock Rise Time
tCLCH
-
50
nS
Clock Fall Time
tCHCL
-
50
nS
LXT Input Pin Input High Voltage
Xin_VIH
LXT Input Pin Input Low Voltage
Xin_VIL
0.7*VDD
V
0.3*VDD
V
tCLCH
Xin_VIH
M480 SERIES DATASHEET
tCLCL
90%
tCLCX
Xin_VIL
10%
tCHCL
tCHCX
Note: Duty cycle is 50%.
8.4.5
12 MHz Internal High Speed RC Oscillator (HIRC)
Specifications
Sym.
Parameter
Test Condition
Min.
VHRC
Supply voltage
Typ.
1.8
Center Frequency
Max.
3.6
12
Unit
V
MHz
fHRC
Internal Oscillator Frequency[*1]
May 08, 2020
-1
1
Page 433 of 523
%
TA = 25 °C,
VDD = 3.3V
Rev 3.00
M480
Specifications
Sym.
Parameter
Test Condition
Min.
Typ.
-3
IHRC
Operating current
TS
Stable time
Max.
Unit
3
%
-40C ~ +105 °C,
VDD = 1.8 ~ 3.6V
A
155
4
us
Note:
1. Guaranteed by characterization, not tested in production
8.4.6
10 kHz Internal Low Speed RC Oscillator (LIRC)
Specifications
Sym.
Parameter
Test Condition
Min.
VLRC
Supply voltage
FLRC
Oscillator Frequency[*1]
ILRC
Operating current
TS
Stable time
Typ.
Max.
Unit
1.8
3.6
V
5
20
kHz
VDD=1.8V~3.6V, TA=-40~105°C
0.5
A
VDD = 3.3V
200
μs
Note:
1. Guaranteed by characterization, not tested in production
8.4.7
PLL Characteristics
M480 SERIES DATASHEET
Symbol
fPLL_IN
fPLL_OUT
TS
Jitter
IDD
Parameter
Conditions
Min
Typ
Max
Unit
PLL input clock
4
24
MHz
PLL multiplier output clock
50
480
MHz
PLL stable time[*1]
100
200
µs
Cycle-to-cycle Jitter[*2]
Peak to peak @ 480M
Power consumption
VDD=3.3V@500 MHz
250
ps
3
mA
Note:
1. Guaranteed by characterization, not tested in production
8.4.8
PIN AC Characteristics
CL = 51 pF
Px_SLEWCTL
May 08, 2020
Symbol
Parameter
Page 434 of 523
Conditions
Typ
Unit
Rev 3.00
M480
tf(IO)out
Output high to low level fall time
(90~10%)
VDD = 3.6 V
4.384
VDD = 1.8 V
8.532
VDD = 3.6 V
4.086
VDD = 1.8 V
8.225
VDD = 3.6 V
3.005
VDD = 1.8 V
6.153
VDD = 3.6 V
3.404
VDD = 1.8 V
6.29
VDD = 3.6 V
3.054
VDD = 1.8 V
6.152
VDD = 3.6 V
3.389
VDD = 1.8 V
6.269
00
tr(IO)out
tf(IO)out
output low to high level rise time
(10~90%)
Output high to low level fall time
(90~10%)
ns
01
tr(IO)out
tf(IO)out
output low to high level rise time
(10~90%)
Output high to low level fall time
(90~10%)
10
tr(IO)out
output low to high level rise time
(10~90%)
Table 8.4-3 I/O AC Characteristics
M480 SERIES DATASHEET
May 08, 2020
Page 435 of 523
Rev 3.00
M480
8.5 Analog Electrical Characteristics
8.5.1
LDO
Symbol
Parameter
Min
VDD
DC Power Supply
1.8
VLDO
Output Voltage
TA
Temperature
Typ
Max
Unit
3.6
V
1.26
-40
Test Condition
V
105
°C
Note:
1. It is recommended a 0.1μF bypass capacitor is connected between V DD and the closest VSS pin of the device.
2. For ensuring power stability, a 2.2μF capacitor must be connected between LDO_CAP pin and the closest VSS pin of
the device.
8.5.2
Low-Voltage Reset
Symbol
Parameter
Min
AVDD
Supply Voltage
TA
Temperature
ILVR
Operating Current
VLVR
M480 SERIES DATASHEET
8.5.3
Threshold Voltage
Typ
Max
Unit
0
3.6
V
-40
105
°C
-
uA
AVDD = 3.6V
0.5
Test Condition
1.40
1.48
1.56
V
TA = 105 °C
1.40
1.48
1.56
V
TA = 25 °C
1.40
1.48
1.56
V
TA = -40 °C
Typ
Max
Unit
Test Condition
Brown-out Detector
Symbol
Parameter
Min
AVDD
Supply Voltage
0
3.6
V
-
TA
Temperature
-40
105
°C
-
IBOD
Operating Current
mA
AVDD = 3.6V
VBOD_F
VBOD_R
May 08, 2020
66
2.9
3.0
3.1
V
BODVL [2:0] = 111
2.7
2.8
2.9
V
BODVL [2:0] = 110
2.5
2.6
2.7
V
BODVL [2:0] = 101
Brown-out Voltage
2.3
2.4
2.5
V
BODVL [2:0] = 100
(Falling edge)
2.1
2.2
2.3
V
BODVL [2:0] = 011
1.9
2.0
2.1
V
BODVL [2:0] = 010
1.7
1.8
1.9
V
BODVL [2:0] = 001
1.5
1.6
1.7
V
BODVL [2:0] = 000
Brown-out Voltage
3.0
3.1
3.2
V
BODVL [2:0] = 111
(Rising edge)
2.8
2.9
3.0
V
BODVL [2:0] = 110
Page 436 of 523
Rev 3.00
M480
TBOD_RE
8.5.4
2.6
2.7
2.8
V
BODVL [2:0] = 101
2.4
2.5
2.6
V
BODVL [2:0] = 100
2.2
2.3
2.4
V
BODVL [2:0] = 011
2.0
2.1
2.2
V
BODVL [2:0] = 010
1.8
1.9
2.0
V
BODVL [2:0] = 001
1.6
1.7
1.8
V
BODVL [2:0] = 000
ms
Respond Time
Respond Time
1
Power-on Reset
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
TA
Temperature
-40
-
+105
°C
-
VPOR
Reset Voltage
V
-
RRVDD
1.47
VDD Raising Rate to Ensure
Power-on Reset[*1]
VDD Falling Rate to Ensure
FRVDD
Power-on Reset[*1]
10
us/V
320
us/V
Note:
1. Guaranteed by characterization, not tested in production
VDD
M480 SERIES DATASHEET
t(don’t care)
FRVDD
RRVDD
VPOR
Time
Figure 8.5-1 Power-up Ramp Condition
8.5.5
Internal Voltage Reference
The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature (T A), and
the typical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
Symbol
Parameter
VREF_INT
Internal reference voltage
May 08, 2020
Min
Typ
Max
1.6
Page 437 of 523
Unit Comments
V
Rev 3.00
M480
2.0
2.5
3.0
2
VREF_OUT = 1.6 v
2.2
AVDD_min
VREF_OUT = 2.0 v
AVDD minimum voltage
Ts
V
2.7
VREF_OUT = 2.5 v
3.2
VREF_OUT = 3.0 v
0.7
2
ms
CL =4.7 uF, VREF initial=0
35
48
us
CL =0.1 uF, VREF initial=0
Stable time
Note:
1. Guaranteed by characterization, not tested in production
VREF
1uF
M480 SERIES DATASHEET
Figure 8.5-2 Typical Connection with Internal Voltage Reference
8.5.6
12-bit ADC
Fast Speed Channel
Specifications
Sym.
Parameter
Test Condition
Min.
Typ.
Max.
Unit
AVDD
Operating voltage
1.8
3.6
V
VREF
Reference voltage
1.6
AVDD
V
Temperature
-40
105
°C
TA
AVDD = VDD = VREF = 3.3V
Operating current (AVDD current)
IADC
(Enable ADC and disable all other analog
modules)
478
ADC channel input voltage
May 08, 2020
523
uA
ADC Clock Rate = 70 MHz
High speed channel
Resolution
VIN
AVDD = VDD
0
Page 438 of 523
12
Bit
VREF
V
Rev 3.00
M480
Specifications
Sym.
Parameter
Test Condition
Min.
Typ.
Unit
70
MHz
FADC
ADC Clock frequency
TSMP
Sampling Time
2
1/FADC
TCONV
Conversion time
14
1/FADC TCONV = TSMP + 12
FSPS
Sampling Rate (FADC/TCONV)
TPU
Power-up time
INL
Integral Non-Linearity Error
-4.29
-3.71
LSB
VREF = AVDD
DNL
Differential Non-Linearity Error
3.25
3.28
LSB
VREF = AVDD
EG
Gain error
2.25
2.31
LSB
VREF = AVDD
EOFFSET
Offset error
1.56
2.87
LSB
VREF = AVDD
EA
Absolute Error
4.5
4.94
LSB
VREF = AVDD
CIN
Internal Capacitance[*1]
-
0.14
Max.
5
MSPS High speed channel
μs
20
Monotonic
High speed channel
5
pF
Guaranteed
-
Low Speed Channel
Specifications
Sym.
Parameter
Test Condition
Min.
AVDD
Operating voltage
VREF
Reference voltage
1.8
Max.
Unit
3.6
V
AVDD
Temperature
AVDD = VDD
V
-40
105
210
231
°C
AVDD = VDD = VREF = 3.3V
ADC Clock Rate = 28 MHz
low speed channel
IADC1
uA
AVDD = VDD = VREF = 1.8V
131
ADC Clock Rate = 28 MHz
142
Operating current (AVDD current)
low speed channel
(Enable ADC and disable all other analog
modules)
AVDD = VDD = VREF = 3.3V
111
ADC Clock Rate = 14 MHz
123
low speed channel
IADC2
uA
AVDD = VDD = VREF = 1.8V
70
78
ADC Clock Rate = 14 MHz
low speed channel
Resolution
VIN
ADC channel input voltage
FADC
ADC Clock frequency
TSMP
Sampling Time
May 08, 2020
12
Bit
0
VREF
V
0.14
70
MHz
2
Page 439 of 523
Low speed channel
1/FADC
Rev 3.00
M480 SERIES DATASHEET
TA
Typ.
M480
Specifications
Sym.
Parameter
Test Condition
Min.
TCONV
Typ.
Conversion time
Max.
14
Unit
1/FADC TCONV = TSMP + 12
Low speed channel
Sampling Rate (FADC/TCONV)
TPU
Power-up time
INL
Integral Non-Linearity Error
-2.94
-1.32
LSB
VREF = AVDD
DNL
Differential Non-Linearity Error
1.25
2
LSB
VREF = AVDD
EG
Gain error
2.5
3.12
LSB
VREF = AVDD
EOFFSET
Offset error
2.44
3.69
LSB
VREF = AVDD
EA
Absolute Error
4.69
6.75
LSB
VREF = AVDD
CIN
Internal Capacitance[*1]
-
2
MSPS Note: it needs more extend
sampling time to slow down the
sampling rate.
FSPS
μs
20
Monotonic
5
pF
Guaranteed
-
EF (Full scale error) = EO + EG
Gain Error
EG
Offset Error
EO
4095
4094
4093
M480 SERIES DATASHEET
4092
Ideal transfer curve
7
6
ADC
output
code
5
Actual transfer curve
4
3
2
DNL
1
1 LSB
Offset Error
EO
Analog input voltage
(LSB)
4095
Note: The INL is the peak difference between the transition point of the steps of the calibrated transfer curve and the ideal
transfer curve. A calibrated transfer curve means it has calibrated the offset and gain error from the actual transfer curve.
May 08, 2020
Page 440 of 523
Rev 3.00
M480
VDD
(1)
RIN
EADC_CHx
12-bit
Converter
(1)
CIN
Note: GND < EADC_CHx < VREF
Refer to ADC spec for the values of RIN, CIN
8.5.7
Temperature Sensor
Symbol
Parameter
Min Typ
Max
Unit
VDD
Operating Voltage
1.8
3.6
V
TA
Temperature Range
-40
105
°C
ITEMP
Current Consumption [*3]
A
16
Temperature Coefficient [*3]
-1.77
Vos
Offset Voltage when TA = 0°C [*3]
710.2
tS
Stable time[*2]
1
µs
ADC sampling time when reading the temperature (5pF cap load) [*1]
3
µs
TS_temp
-1.82
-1.84
mV/°C
716.8
mV
Note:
1.
VTEMP (mV) = Tc (mV/°C) x Temperature (°C) + Vos (mV)
2.
Guaranteed by design, not tested in production
3.
Guaranteed by characteristic, not tested in production
8.5.8
Digital to Analog Converter (DAC)
Symbol
Parameter
Min
Typ
Max
AVDD
Analog supply voltage
1.8
-
3.6
NR
Resolution
VREF
Reference supply voltage
DNL
Differential non-linearity error[*4]
INL
May 08, 2020
Integral non-linearity error[*4]
12
Unit
Test Condition
V
-
bit
-
1.5
-
AVDD
V
VREF ≤ AVDD
-
-
±2
LSB
12-bit mode
-
-
±0.5
LSB
10-bit mode
-
-
±4
LSB
12-bit mode
Page 441 of 523
Rev 3.00
M480 SERIES DATASHEET
Tc
M480
OE
GE
AE
Offset Error[*4]
Gain Error[*4]
Absolute Error[*4]
-
Monotonic
VO
Output Voltage
M480 SERIES DATASHEET
RLOAD
Resistive load[*2]
Ro
Output impedance[*4]
CLOAD
Capacitive load[*3]
IAVDD
IREF
TS
-
-
±1
LSB
-
-
±30
LSB
-
-
±4
LSB
-
-
±2
LSB
-
-
±5
LSB
-
-
±4
LSB
-
-
±2
LSB
-
-
±8
LSB
-
-
±4
LSB
-
-
±2
LSB
10-bit guaranteed
AVDD 0.2
0.2
7.5
Settling Time
12-bit mode
DACOUT buffer OFF
10-bit mode
12-bit mode
DACOUT buffer ON
12-bit mode
DACOUT buffer OFF
10-bit mode
12-bit mode
DACOUT buffer ON
12-bit mode
DACOUT buffer OFF
10-bit mode
-
-
kΩ
DACOUT buffer ON
12
kΩ
DACOUT buffer OFF
-
-
50
-
-
180
pF
A
-
-
420
-
150
240
-
DACOUT buffer ON
DACOUT buffer ON
Current consumption on AVDD
supply[*4]
Current consumption on VREF
supply[*4]
12-bit mode
V
10
-
10-bit mode
5
6
AVDD = 3.6V, no load, lowest code
(0x000)
AVDD = 3.6V, no load, middle code
(0x800)
A
μs
VREF =3.6V, no load, middle code
(0x800)
Full scale: for a 12-bit input code
transition between the lowest and the
highest input codes when DAC_OUT
reaches final value +/-1 LSB,
CLOAD ≤ 50pF, RLOAD ≥ 7.5kΩ
Fs
TWAKEUP
Update Rate
Wake-up Time
-
-
-
9
1
15
MSPS
μs
Max. frequency for a correct
DAC_OUT change from core i to
i+1LSB, CLOAD ≤ 50pF, RLOAD ≥ 7.5kΩ
Wakeup time from OFF state. Input
code between lowest and highest
possible codes.
DAC clock source = 1 MHz
May 08, 2020
Page 442 of 523
Rev 3.00
M480
PSRR
Power Supply Rejection Ratio[*1]
-
-60
-40
dB
No RLOAD, CLOAD = 50pF
Note:
1.
Guaranteed by design, not tested in production.
2.
Resistive load between DACOUT and AVSS.
3.
Capacitive load at DACOUT pin.
4.
Guaranteed based on test during characterization.
8.5.9
Analog Comparator Controller (ACMP)
The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature (TA), and the typical
values for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
Symbol
Parameter
Min
Typ
Max
Unit Comments
AVDD
Analog supply voltage
1.8
3.6
V
TA
Temperature
-40
105
°C
MODESEL[1:0] = 00
1.2
MODESEL[1:0] = 01
3
IDD
A
Operating current
VCM
Input common mode voltage range [*2]
VDI
Differential input voltage sensitivity [*2]
Voffset
Input offset voltage
10
MODESEL[1:0] = 10
75
MODESEL[1:0] = 11
0.1
1/2
AVDD
10
20
5
AVDD 0.1
10
mV
Hysteresis disable
mV
Hysteresis disable,
0
HYSSEL[1:0] = 00
Av
Td
HYSSEL[1:0] = 01
Hysteresis window
DC voltage Gain[*1]
mV
20
HYSSEL[1:0] = 10
30
HYSSEL[1:0] = 11
70
dB
0.2
Hysteresis disable MODESEL[1:0] =
00
0.6
Hysteresis disable MODESEL[1:0] =
01
Propagation delay[*2]
uS
2
Hysteresis disable MODESEL[1:0] =
10
4.5
Hysteresis disable MODESEL[1:0] =
11
0.45
TSetup
Setup time[*2]
0.85
2.25
May 08, 2020
Page 443 of 523
Hysteresis disable MODESEL[1:0] =
00
uS
Hysteresis disable MODESEL[1:0] =
01
Hysteresis disable MODESEL[1:0] =
10
Rev 3.00
M480 SERIES DATASHEET
10
Vhys
M480
Hysteresis disable MODESEL[1:0] =
11
4.75
Note:
1.
Guaranteed by design, not tested in production
8.5.10 OP Amplifier (OPA)
The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature (T A), and
the typical values for TA = 25 °C and VDD = 3.3 V unless otherwise specified.
Symbol
Parameter
Min
Typ
Max
Unit
AVDD
Analog supply voltage
2.4
3.6
V
TA
Temperature
-40
105
°C
IDD
Consumption current
CMIR
Common mode input range
VOFFSET0
Input offset voltage(maximum calibration
range) [*2]
A
690
AVDD
0
VOFFSET1
4
Tj = 25°C, No Load
6
VCM = AVDD-10mV ~ AVDD-0.8V, All
Temp.
CALRVS =0: Other VCM
mV
6.5
3
VOFFSET2
Input offset voltage(After offset calibration)
[*2]
M480 SERIES DATASHEET
CMRR
Common Mode Rejection Ratio [*1]
PSRR
Power Supply Rejection Ratio [*1]
GBW
SR
CALRVS =1: VCM = AVDD-10mV ~
AVDD-0.8V
90
dB
117
dB
Bandwidth [*2]
8.2
MHz
Slew rate [*2]
4.7
V/s
AVDD0.1
VOHSAT
Rload=min. INPUT at AVDD
High saturation voltage [*2]
V
AVDD0.02
Rload=20K, INPUT at AVDD
100
VOLSAT
CALRVS=0: VCM = AVDD-10mV ~
AVDD-0.8V
CALRVS =1: Other VCM
5.2
73
AVDD=3.3V, Temperature=25 °C
V
3.2
Input offset voltage(After offset calibration)
[*2]
Comments
Low saturation voltage [*2]
Rload=min. INPUT at 0
mV
20
PM
Phase Margin [*1]
62
TWAKEUP
Wake up time from OFF state [*2]
2.8
RLOAD
Resistive load
CLOAD
Capacitive load
Rload=20K, INPUT at 0
degree
5
4
s
kΩ
50
pF
Note:
1.
Guaranteed by characteristic, not tested in production
May 08, 2020
Page 444 of 523
Rev 3.00
M480
8.6 Flash DC Electrical Characteristic
Symbol
Parameter
Min
VFLA[1]
Supply Voltage
1.08
NENDUR
Endurance
10000
TRET
Data Retention
TERASE
Typ
Max
Unit
1.32
V
-
-
cycles[2]
10
-
-
year
Page Erase Time
92
-
160
mS
TMER
Mass Erase Time
201
-
320
mS
TPROG
Program Time
-
16
uS
IDD1
Read Current
-
-
4.12
mA
IDD2
Program Current
-
-
5
mA
IDD3
Erase Current
-
-
5
uA
Test Condition
TA = 25°C
Note:
1.
VFLA is source from chip LDO output voltage.
2.
Number of program/erase cycles.
3.
This table is guaranteed by design, not test in production.
M480 SERIES DATASHEET
May 08, 2020
Page 445 of 523
Rev 3.00
M480
8.7 I2C Dynamic Characteristics
Standard Mode[1][2]
Symbol
Fast Mode[1][2]
Parameter
Unit
Min.
Max.
Min.
Max.
tLOW
SCL low period
4.7
-
1.2
-
uS
tHIGH
SCL high period
4
-
0.6
-
uS
tSU; STA
Repeated START condition setup time
4.7
-
1.2
-
uS
tHD; STA
START condition hold time
4
-
0.6
-
uS
tSU; STO
STOP condition setup time
4
-
0.6
-
uS
tBUF
Bus free time
4.7[3]
-
1.2[3]
-
uS
tSU;DAT
Data setup time
250
-
100
-
nS
tHD;DAT
Data hold time
0[4]
3.45[5]
0[4]
0.8[5]
uS
tr
SCL/SDA rise time
-
1000
20+0.1Cb
300
nS
tf
SCL/SDA fall time
-
300
-
300
nS
Cb
Capacitive load for each bus line
-
400
-
400
pF
Note:
M480 SERIES DATASHEET
1.
Guaranteed by characteristic, not tested in production
2.
HCLK must be higher than 2 MHz to achieve the maximum standard mode I 2C frequency. It must be higher
than 8 MHz to achieve the maximum fast mode I2C frequency.
3.
I2C controller must be retriggered immediately at slave mode after receiving STOP condition.
4.
The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
5.
The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period
of SCL signal.
STOP
Repeated
START
START
STOP
SDA
tBUF
tLOW
tr
SCL
tHD;STA
tf
tHIGH
tHD;DAT
tSU;DAT
tSU;STA
tSU;STO
2
Figure 8.7-1 I C Timing Diagram
May 08, 2020
Page 446 of 523
Rev 3.00
M480
8.8 SPI Dynamic Characteristics
Symbol
Parameter
Min.
Typ.
Max.
Unit
SPI MASTER MODE (VDD = 3.0~3.6 V, 30 PF LOADING CAPACITOR)
tCLKH
Clock output High time [*1]
TSPICLK / 2
ns
tCLKL
Clock output Low time [*1]
TSPICLK / 2
ns
tDS
Data setup time
0
-
-
ns
tDH
Data hold time
2
-
-
ns
tV
Data output valid time
-
0
1
ns
SPI MASTER MODE (VDD = 1.8~2.0 V, 30 PF LOADING CAPACITOR)
tCLKH
Clock output High time [*1]
TSPICLK / 2
ns
tCLKL
Clock output Low time [*1]
TSPICLK / 2
ns
tDS
Data setup time
0
-
-
ns
tDH
Data hold time
2
-
-
ns
tV
Data output valid time
-
-
1
ns
Note:
1. The minimum clock period for SPICLK is 10.4 ns (96 MHz).
tCLKH
tCLKL
CLKP=0
CLKP=1
tV
Data Valid
MOSI
Data Valid
tDS
MISO
Data Valid
CLKP=0, TX_NEG=1, RX_NEG=0
or
CLKP=1, TX_NEG=0, RX_NEG=1
tDH
Data Valid
tV
Data Valid
MOSI
tDS
MISO
Data Valid
CLKP=0, TX_NEG=0, RX_NEG=1
or
CLKP=1, TX_NEG=1, RX_NEG=0
tDH
Data Valid
Data Valid
Figure 8.8-1 SPI Master Mode Timing Diagram
Symbol
Parameter
May 08, 2020
Min.
Page 447 of 523
Typ.
Max.
Unit
Rev 3.00
M480 SERIES DATASHEET
SPICLK
M480
SPI SLAVE MODE (VDD = 3.0~3.6V, 30 PF LOADING CAPACITOR)
tCLKH
Clock output High time [*1]
-
tCLKL
Clock output Low time [*1]
-
tSS
Slave select setup time
1 TSPICLK + 2ns
tSH
Slave select hold time
1 TSPICLK
tDS
Data input setup time
0
tDH
Data input hold time
2
tV
Data output valid time
-
tCLKH
Clock output High time [*1]
-
TSPICLK / 2
ns
TSPICLK / 2
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
8
ns
TSPICLK / 2
ns
-
-
SPI SLAVE MODE (VDD = 1.8 V ~ 2.0 V, 30 PF LOADING CAPACITOR)
tCLKH
Clock output High time [*1]
-
-
TSPICLK / 2
ns
tCLKL
Clock output Low time [*1]
-
-
TSPICLK / 2
ns
tSS
Slave select setup time
1 TSPICLK + 3ns
-
-
ns
tSH
Slave select hold time
1 TSPICLK
-
-
ns
tDS
Data input setup time
0
-
-
ns
tDH
Data input hold time
2
-
-
ns
tV
Data output valid time
-
10
ns
Note:
1. The minimum clock period for SPICLK is 10.4 ns (96 MHz).
M480 SERIES DATASHEET
May 08, 2020
Page 448 of 523
Rev 3.00
M480
SSACTPOL=1
SPI SS
tSS
tSH
SSACTPOL=0
tCLKH
CLKPOL=0
TXNEG=1
RXNEG=0
tCLKL
SPI Clock
CLKPOL=1
TXNEG=0
RXNEG=1
tV
SPI data output
(SPI_MISO)
Data Valid
Data Valid
tDS
SPI data input
(SPI_MOSI)
Data Valid
SSACTPOL=1
SPI SS
tDH
Data Valid
tSS
tSH
SSACTPOL=0
CLKPOL=0
TXNEG=0
RXNEG=1
tCLKH
tCLKL
SPI Clock
CLKPOL=1
TXNEG=1
RXNEG=0
tV
Data Valid
tDS
SPI data input
(SPI_MOSI)
Data Valid
M480 SERIES DATASHEET
SPI data output
(SPI_MISO)
tDH
Data Valid
Data Valid
Figure 8.8-2 SPI Slave Mode Timing Diagram
May 08, 2020
Page 449 of 523
Rev 3.00
M480
8.9 I2S Dynamic Characteristics
Symbol
Parameter
2
I S clock high time
tw(CKH)
2
Min
Max
40
-
Unit
Test Conditions
Master fPCLK = MHz, data: 24 bits, audio
frequency = 256 kHz
tw(CKL)
I S clock low time
40
-
tv(WS)
WS valid time
4
16
th(WS)
WS hold time
1
-
Master mode
tsu(WS)
WS setup time
24
-
Slave mode
th(WS)
WS hold time
0
-
Slave mode
DuCy(SCK)
I2S slave input clock
duty cycle
30
70
10
-
Master receiver
7
-
Slave receiver
7
-
Master receiver
4
-
tsu(SD_MR)
%
Slave mode
Data input setup time
tsu(SD_SR)
th(SD_MR)
Master mode
ns
Data input hold time
th(SD_SR)
Slave receiver
ns
Data output valid time
-
10
Slave transmitter (after enable edge)
th(SD_ST)
Data output hold time
4
-
Slave transmitter (after enable edge)
tv(SD_MT)
Data output valid time
-
4
Master transmitter (after enable edge)
th(SD_MT)
Data output hold time
0
-
Master transmitter (after enable edge)
M480 SERIES DATASHEET
CK output
tv(SD_ST)
CPOL = 0
tw(CKH)
CPOL = 1
tw(CKL)
tv(WS)
th(WS)
WS output
tv(SD_ST)
SDtransmit
LSB transmit(2)
MSB transmit
tsu(SD_MR)
SDreceive
LSB receive(2)
Bitn transmit
th(SD_ST)
LSB transmit
th(SD_MR)
MSB receive
Bitn receive
LSB receive
2
Figure 8.9-1 I S Master Mode Timing Diagram
May 08, 2020
Page 450 of 523
Rev 3.00
M480
CK Input
CPOL = 0
CPOL = 1
tw(CKH)
tw(CKL)
th(WS)
WS input
tv(SD_ST)
tsu(WS)
SDtransmit
LSB transmit(2)
MSB transmit
tsu(SD_SR)
SDreceive
LSB receive(2)
Bitn transmit
th(SD_ST)
LSB transmit
th(SD_SR)
MSB receive
Bitn receive
LSB receive
2
Figure 8.9-2 I S Slave Mode Timing Diagram
M480 SERIES DATASHEET
May 08, 2020
Page 451 of 523
Rev 3.00
M480
8.10 USCI - I2C Dynamic Characteristics
Standard Mode[1][2]
Symbol
Fast Mode[1][2]
Unit
Parameter
Min.
Max.
Min.
Max.
tLOW
SCL low period
4.7
-
1.2
-
uS
tHIGH
SCL high period
4
-
0.6
-
uS
tSU; STA
Repeated START condition setup time
4.7
-
1.2
-
uS
tHD; STA
START condition hold time
4
-
0.6
-
uS
tSU; STO
STOP condition setup time
4
-
0.6
-
uS
tBUF
Bus free time
4.7[3]
-
1.2[3]
-
uS
tSU;DAT
Data setup time
250
-
100
-
nS
tHD;DAT
Data hold time
0[4]
3.45[5]
0[4]
0.8[5]
uS
tr
SCL/SDA rise time
-
1000
20+0.1Cb
300
nS
tf
SCL/SDA fall time
-
300
-
300
nS
Cb
Capacitive load for each bus line
-
400
-
400
pF
Note:
M480 SERIES DATASHEET
1.
Guaranteed by characteristic, not tested in production
2.
HCLK must be higher than 2 MHz to achieve the maximum standard mode I 2C frequency. It must be higher
than 8 MHz to achieve the maximum fast mode I2C frequency.
3.
I2C controller must be retriggered immediately at slave mode after receiving STOP condition.
4.
The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
5.
The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period
of SCL signal.
STOP
Repeated
START
START
STOP
SDA
tBUF
tLOW
tr
SCL
tHD;STA
tf
tHIGH
tHD;DAT
tSU;DAT
tSU;STA
tSU;STO
2
Figure 8.10-1 I C Timing Diagram
May 08, 2020
Page 452 of 523
Rev 3.00
M480
8.11 USCI - SPI Dynamic Characteristics
Symbol
Parameter
Min.
Typ.
Max.
Unit
SPI MASTER MODE (VDD = 3.0~3.6 V, 30 PF LOADING CAPACITOR)
tCLKH
Clock output High time [*1]
TSPICLK / 2
ns
tCLKL
Clock output Low time [*1]
TSPICLK / 2
ns
tDS
Data setup time
0
-
-
ns
tDH
Data hold time
2
-
-
ns
tV
Data output valid time
-
0
1
ns
SPI MASTER MODE (VDD = 1.8~2.0 V, 30 PF LOADING CAPACITOR)
tCLKH
Clock output High time [*1]
TSPICLK / 2
ns
tCLKL
Clock output Low time [*1]
TSPICLK / 2
ns
tDS
Data setup time
0
-
-
ns
tDH
Data hold time
2
-
-
ns
tV
Data output valid time
-
-
1
ns
Note:
1. The minimum clock period for SPICLK is 10.4 ns (96 MHz).
tCLKH
tCLKL
CLKP=0
CLKP=1
tV
MOSI
Data Valid
Data Valid
tDS
MISO
Data Valid
CLKP=0, TX_NEG=1, RX_NEG=0
or
CLKP=1, TX_NEG=0, RX_NEG=1
tDH
Data Valid
tV
Data Valid
MOSI
tDS
MISO
Data Valid
CLKP=0, TX_NEG=0, RX_NEG=1
or
CLKP=1, TX_NEG=1, RX_NEG=0
tDH
Data Valid
Data Valid
Figure 8.11-1 SPI Master Mode Timing Diagram
May 08, 2020
Page 453 of 523
Rev 3.00
M480 SERIES DATASHEET
SPICLK
M480
Symbol
Parameter
Min.
Typ.
Max.
Unit
TSPICLK / 2
ns
TSPICLK / 2
ns
SPI SLAVE MODE (VDD = 3.0~3.6V, 30 PF LOADING CAPACITOR)
tCLKH
Clock output High time [*1]
-
tCLKL
Clock output Low time [*1]
-
tSS
Slave select setup time
1 TSPICLK + 2ns
-
-
ns
tSH
Slave select hold time
1 TSPICLK
-
-
ns
tDS
Data input setup time
0
-
-
ns
tDH
Data input hold time
2
-
-
ns
tV
Data output valid time
-
8
ns
tCLKH
Clock output High time [*1]
-
TSPICLK / 2
ns
-
-
SPI SLAVE MODE (VDD = 1.8 V ~ 2.0 V, 30 PF LOADING CAPACITOR)
tCLKH
Clock output High time [*1]
-
-
TSPICLK / 2
ns
tCLKL
Clock output Low time [*1]
-
-
TSPICLK / 2
ns
tSS
Slave select setup time
1 TSPICLK + 3ns
-
-
ns
tSH
Slave select hold time
1 TSPICLK
-
-
ns
tDS
Data input setup time
0
-
-
ns
tDH
Data input hold time
2
-
-
ns
tV
Data output valid time
-
10
ns
Note:
M480 SERIES DATASHEET
1. The minimum clock period for SPICLK is 10.4 ns (96 MHz).
May 08, 2020
Page 454 of 523
Rev 3.00
M480
SSACTPOL=1
SPI SS
tSS
tSH
SSACTPOL=0
tCLKH
CLKPOL=0
TXNEG=1
RXNEG=0
tCLKL
SPI Clock
CLKPOL=1
TXNEG=0
RXNEG=1
tV
SPI data output
(SPI_MISO)
Data Valid
Data Valid
tDS
SPI data input
(SPI_MOSI)
Data Valid
SSACTPOL=1
SPI SS
tDH
Data Valid
tSS
tSH
SSACTPOL=0
CLKPOL=0
TXNEG=0
RXNEG=1
tCLKH
tCLKL
SPI Clock
CLKPOL=1
TXNEG=1
RXNEG=0
tV
Data Valid
tDS
SPI data input
(SPI_MOSI)
Data Valid
M480 SERIES DATASHEET
SPI data output
(SPI_MISO)
tDH
Data Valid
Data Valid
Figure 8.11-2 SPI Slave Mode Timing Diagram
May 08, 2020
Page 455 of 523
Rev 3.00
M480
8.12 USB Characteristics
8.12.1 USB Full-Speed
Symbol
Parameter
Min.
Typ.
Max.
Unit
3.6
V
Test Conditions
VDD
Operation Voltage
3.0
VIH
Input High (driven)
2.0
-
-
V
-
VIL
Input Low
-
-
0.8
V
-
VDI
Differential Input Sensitivity
0.2
-
-
V
|PADP-PADM|
0.8
-
2.5
V
Includes VDI range
0.8
-
2.0
V
-
Receiver Hysteresis
-
200
-
mV
-
VOL
Output Low (driven)
0
-
0.3
V
-
VOH
Output High (driven)
2.8
-
3.6
V
-
VCRS
Output Signal Cross Voltage
1.3
-
2.0
V
-
RPU
Pull-up Resistor
1.425
-
1.575
kΩ
-
RPD
Pull-down Resistor
14.25
-
15.75
kΩ
VTRM
TERMINATION
Voltage
Uptream port pull up (RPU)
3.0
-
3.6
V
ZDRV
Driver Output Resistance
-
13
-
Ω
Steady state drive*
CIN
Transceiver Capacitance
-
-
20
pF
Pin to GND
VCM
VSE
Differential
Common-mode Range
Single-ended
Threshold
Receiver
for
M480 SERIES DATASHEET
8.12.2 USB Full-Speed PHY Characteristics
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
TFR
Rise Time
4
-
20
ns
CL=50p
TFF
Fall Time
4
-
20
ns
CL=50p
Rise and Fall Time Matching
90
-
111.11
%
TFRFF=TFR/TFF
Unit
Test Condition
TFRFF
8.12.3 USB High-Speed Characteristics
Symbol
Parameter
Min
Typ
Max
TFR
High Speed Driver Rise Time
500
-
ps
CL=5pF
TFF
High Speed Driver Fall Time
500
-
ps
CL=5pF
TFRFF
Rise and Fall Time Matching
90
%
TFRFF=TFR/TFF
May 08, 2020
Page 456 of 523
111.11
Rev 3.00
M480
8.13 Ethernet Characteristics
8.13.1 RMII Interface Timing
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
TP_RMII_REFCLK
RMII_REFCLK Period
-
20.0 +/- 50
ppm
-
ns
-
TH_RMII_REFCLK
RMII_REFCLK High Time
8.0
10.0
12.0
ns
-
TL_RMII_REFCLK
RMII_REFCLK Low Time
8.0
10.0
12.0
ns
-
TDLY_RMII_TX
RMII_REFCLK Rising to Valid
RMII_TXEN, RMII_TXDATA0 and
RMII_TXDATA1 Delay
-
-
10
ns
-
TSU_RMII_RX
RMII_CRSDV, RMII_RXDATA0
and RMII_RXDATA1 Setup Time to
RMII_REFCLK Rising
5
-
-
ns
-
THD_RMII_RX
RMII_CRSDV, RMII_RXDATA0
and RMII_RXDATA1 Hold Time
from RMII_REFCLK Rising
2
-
-
ns
-
TP_RMII_REFCLK
TH_RMII_REFCLK
TL_RMII_REFCLK
RMIIx_REFCLK
RMIIx_TXEN
RMIIx_TXDATA0
RMIIx_TXDATA1
M480 SERIES DATASHEET
TDLY_RMII_TX
RMIIx_CRSDV
RMIIx_RXDATA0
RMIIx_RXDATA1
TSU_RMII_RX
THD_RMII_RX
Figure 8.13-1 RMII Interface Timing Diagram
8.13.2 Ethernet PHY Management Interface Timing
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
TP_RMII_MDC
RMII_MDC Period
400
-
-
ns
-
TH_RMII_MDC
RMII_MDC High Time
200
-
-
ns
-
TL_RMII_MDC
RMII_MDC Low Time
200
-
-
ns
-
TDLY_RMII_MDIOWR
RMII_MDC Falling to Valid
RMII_MDIO Delay
-
-
10
ns
-
May 08, 2020
Page 457 of 523
Rev 3.00
M480
TSU_RMII_MDIORD
RMII_MDIO Setup Time to
RMII_MDC Rising
10
-
-
ns
-
THD_RMII_MDIORD
RMII_MDIO Hold Time from
RMII_MDC Rising
10
-
-
ns
-
TP_RMII_MDC
TH_RMII_MDC
TL_RMII_MDC
RMIIx_MDC
RMIIx_MDIO
(Write)
TDLY_RMII_MDIOWR
RMIIx_MDIO
(Read)
TSU_RMII_MDIORD
THD_RMII_MDIORD
Figure 8.13-2 Ethernet PHY Management Interface Timing Diagram
M480 SERIES DATASHEET
May 08, 2020
Page 458 of 523
Rev 3.00
M480
8.14 SDIO Characteristics
8.14.1 Default Mode Timing
Symbol
Parameter
SD_CLK Period
TP_SD_CLK
(Data Transfer Mode)
SD_CLK Period
TP_SD_CLK_ID
(Identification Mode)
Min
Typ
Max
Unit
Test Condition
40
-
-
ns
-
2,500
-
-
ns
TH_SD_CLK
SD_CLK High Time
-
20
-
ns
-
TL_SD_CLK
SD_CLK Low Time
-
20
-
ns
-
5
-
-
ns
-
5
-
-
ns
-
-
-
14
ns
-
SD_DATA Setup Time to
TSU_SD_IN
SD_CLK Rising
SD_DATA Hold Time from
SD_CLK Rising
THD_SD_IN
SD_CLK Falling to
TDLY_SD_OUT
Valid SD_DATA Delay
TP_SD_CLK
TL_SD_CLK
TH_SD_CLK
SDx_CLK
M480 SERIES DATASHEET
SDx_CMD
SDx_DATA[3:0]
(Input Mode)
TSU_SD_IN
THD_SD_IN
SDx_CMD
SDx_DATA[3:0]
(Output Mode)
TDLY_SD_OUT
Figure 8.14-1 SDIO Default Mode
8.14.2 SDIO Dynamic Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
TP_SD_CLK
SD_CLK Period
20
-
-
ns
-
TH_SD_CLK
SD_CLK High Time
7
-
-
ns
-
TL_SD_CLK
SD_CLK Low Time
7
-
-
ns
-
May 08, 2020
Page 459 of 523
Rev 3.00
M480
SD_DATA Setup Time to
TSU_SD_IN
SD_CLK Rising
SD_DATA Hold Time from
SD_CLK Rising
THD_SD_IN
SD_CLK Falling to
TDLY_SD_OUT
Valid SD_DATA Delay
SD_DATA Hold Time from
SD_CLK Rising
THD_SD_OUT
6
-
-
ns
-
2
-
-
ns
-
-
-
14
ns
-
2.5
-
-
ns
-
TP_SD_CLK
TL_SD_CLK
TH_SD_CLK
SDx_CLK
SDx_CMD
SDx_DATA[3:0]
(Input Mode)
TSU_SD_IN
THD_SD_IN
SDx_CMD
SDx_DATA[3:0]
(Output Mode)
TDLY_SD_OUT
THD_SD_OUT
Figure 8.14-2 SDIO High-speed Mode
M480 SERIES DATASHEET
May 08, 2020
Page 460 of 523
Rev 3.00
M480
8.15 SPI Flash Characteristics (M487KMCAN)
Symbol
Parameter
Min
Typ
Max
Unit
NENDUR
Endurance
100K
cycles[1]
TRET
Data Retention
20
year
TPROG
Page Program Time(256 bytes)
0.4
3
ms
TSE
Sector Erase Time (4KB)
45
400
ms
TBE1
Block Erase Time (32KB)
120
1600
ms
TBE2
Block Erase Time (64KB)
150
2000
ms
TCE
Chip Erase Time
5
25
s
IDD1
Current Read Data
6
18
mA
IDD2
Current Page Program
20
25
mA
IDD3
Current Sector/Block Erase
20
25
mA
IDD3
Current Chip Erase
20
25
mA
Test Condition
VDD = 3.0 V,
TA = +25 °C
Note:
1.
Number of program/erase cycles.
2.
This table is guaranteed by design, not test in production.
M480 SERIES DATASHEET
May 08, 2020
Page 461 of 523
Rev 3.00
M480
9
ELECTRICAL CHARACTERISTICS FOR M48XGC/M48XE8
9.1 Absolute Maximum Ratings
Stresses above the absolute maximum ratings may cause permanent damage to the device. The
limiting values are stress ratings only and cannot be used to functional operation of the device.
Exposure to the absolute maximum ratings may affect device reliability and proper operation is not
guaranteed.
9.1.1
Voltage Characteristics
Symbol
Description
VDD-VSS[*1]
VDDIO-VSS
Min
Max
Unit
DC Power Supply
-0.3
4
V
VDDIO Power Supply
-0.3
4
V
|VDDX – VDD|
Variations between different power pins
50
mV
|VDD –AVDD|
Allowed voltage difference for VDD and AVDD
50
mV
|VSSX - VSS|
Variations between different ground pins
50
mV
|VSS - AVSS|
Allowed voltage difference for VSS and AVSS
50
mV
Input Voltage on 5V-tolerance GPIO
5.5
V
Input Voltage on RTC domain (PF.6 ~ PF.11)
VDD
V
Input Voltage on any other pin[*2]
VDD
V
VIN
Note:
1.
All main power (VDD, AVDD) and ground (VSS, AVSS) pins must always be connected to the external power
supply, in the permitted range.
2.
Non 5V-tolerance PIN: PA.8 ~ 15; PB.0 ~ 15; PD.10, 11, 12; PF.2, 3, 4, 5; All USB High Speed PIN and
nRESET PIN.
M480 SERIES DATASHEET
Table 9.1-1 Voltage Characteristics
9.1.2
Current Characteristics
Symbol
Min
Max
Maximum current into VDD
-
200
IDDIO
Maximum Current into VDDIO
-
100
IBAT
Maximum Current into VBAT
-
100
ΣISS
Maximum current out of VSS
-
100
Maximum current sunk by a I/O Pin
-
20
Maximum current sourced by a I/O Pin
-
20
Maximum current sunk by total I/O Pins[*2]
-
100
Maximum current sourced by total I/O Pins[*2]
-
100
Maximum injected current by a I/O Pin
-
±5
Maximum injected current by total I/O Pins
-
±25
ΣIDD[*1]
Description
Unit
mA
IIO
IINJ(PIN)
[*3]
ΣIINJ(PIN) [*3]
May 08, 2020
Page 462 of 523
Rev 3.00
M480
Note:
1.
Maximum allowable current is a function of device maximum power dissipation.
2.
This current consumption must be correctly distributed over all I/Os and control pins. The total output current
must not be sunk/sourced between two consecutive power supply pins.
3.
A positive injection is caused by VIN>AVDD and a negative injection is caused by VIN 30 sec.
Time with 5°C of actual peak temperature
Peak temperature range
260°C
Ramp-down rate
6℃/sec ax.
Time 25°C to peak temperature
8 min. max
Note:
1. Determined according to J-STD-020C
Table 9.1-8 Soldering Profile
May 08, 2020
Page 467 of 523
Rev 3.00
M480
9.2 General Operating Conditions
(VDD-VSS = 1.8 ~ 3.6V, TA = 25C, HCLK = 192 MHz unless otherwise specified.)
Symbol
TA
Parameter
Temperature
Min
Typ
Max
Unit
-40
-
105
°C
-
-
192
MHz
fHCLK
Internal AHB clock frequency
VDD
Operation voltage
1.8
-
3.6
VDDIO
VDDIO Operation voltage
1.8
-
3.6
VBAT
VBAT Operation voltage
1.8
-
3.6
AVDD[*1]
Analog operation voltage
VREF
Analog reference voltage
VLDO
LDO output voltage
VBG
Band-gap voltage
CLDO[*2]
VDD
V
1.8
-
AVDD
-
1.26
-
1.17
Test Conditions
1.23
1
µF
LQFP128/LQFP64
2.2
µF
LQFP48/QFN32
LDO output capacitor on each pin
RESR[*3]
ESR of CLDO output capacitor
0.1
-
10
Ω
IRUSH[*3]
InRush current on voltage
regulator power-on (POR or
wakeup from Standby)
-
150
-
mA
ERUSH[*3]
InRush energy on voltage
regulator power-on (POR or
wakeup from Standby)
-
3.65
-
µC
VDD = 1.8 V, TA = 105 °C,
IRUSH = 146 mA for 25 µs
Note:
M480 SERIES DATASHEET
1. It is recommended to power VDD and AVDD from the same source. A maximum difference of 0.3 V between V DD and
AVDD can be tolerated during power-on and power-off operation .
2. To ensure stability, an external 1 μF output capacitor, CLDO must be connected between the LDO_CAP pin and the
closest GND pin of the device. Solid tantalum and multilayer ceramic capacitors are suitable as output capacitor.
Additional 100 nF bypass capacitor between LDO_CAP pin and the closest GND pin of the device helps decrease
output noise and improves the load transient response.
3. Guaranteed by design, not tested in production
Table 9.2-1 General Operating Conditions
May 08, 2020
Page 468 of 523
Rev 3.00
M480
9.3 DC Electrical Characteristics
9.3.1
Supply Current Characteristics
The current consumption is a combination of internal and external parameters and factors such as
operating frequencies, device software configuration, I/O pin loading, I/O pin switching rate, program
location in memory and so on. The current consumption is measured as described in below condition
and table to inform test characterization result.
All GPIO pins are in push pull mode and output high.
The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature
(TA), and the typical values for T A= 25 °C and VDD = 1.8~3.6 V unless otherwise specified.
VDD = AVDD = VDDIO= VBAT
When the peripherals are enabled HCLK is the system clock, f PCLK0, 1 = fHCLK/2.
Program run while(1){} from Flash
Typ [*1]
Symbol
Conditions
Normal run mode, executed
from Flash, all peripherals
disable
HIRC, PLL, HXT,LIRC or LXT
clock
Max[*1][*2]
FHCLK
Unit
TA = 25 °C
TA = -40 °C
TA = 25 °C
TA = 105 °C
192 MHz
25.14
24.11
26.95
54.03
160 MHz
21.4
20.27
23.1
49.66
144 MHz
19.19
17.94
20.86
47
120 MHz
17.4
17
19.39
45.94
12 MHz
3.1
2.36
4.55
29.92
32.768 kHz
1.54
0.99
3.11
28.20
10 kHz
1.07
0.39
2.63
27.6
192 MHz
44.72
44.30
47.09
75.48
160 MHz
40.41
35.78
42.74
66.58
144 MHz
33.93
33.65
35.84
63.83
120 MHz
28.53
27.99
30.41
57.68
12 MHz
4.63
4.14
6.13
32.02
32.768 kHz
1.85
1.30
3.5
28.82
10 kHz
1.39
0.73
3.01
28.11
IDD_RUN
mA
HIRC, PLL, HXT, LIRC or LXT
clock
M480 SERIES DATASHEET
Normal run mode, executed
from Flash, all peripherals
enable
Note:
1. When analog peripheral blocks such as ADC, ACMP, PLL, HIRC, LIRC, HXT and LXT are ON, an additional power
consumption should be considered.
2. Based on characterization, not tested in production unless otherwise specified.
Table 9.3-1 Current Consumption in Normal Run Mode
Typ [*1]
Symbol
Conditions
FHCLK
Unit
TA = 25 °C
May 08, 2020
Max[*1][*2]
TA = -40 °C
Page 469 of 523
TA = 25 °C
TA = 105 °C
Rev 3.00
M480
Idle mode, all peripherals
disable
HIRC, PLL, HXT, LIRC or LXT
clock
192 MHz
8.92
7.95
10.40
36.28
160 MHz
7.82
6.92
9.27
35.06
144 MHz
7.29
6.41
8.78
34.46
120 MHz
6.47
5.63
7.95
33.56
12 MHz
2.15
1.5
3.61
28.9
32.768 kHz
1.54
0.99
3.11
28.18
10 kHz
1.07
0.68
2.63
27.58
192 MHz
30.59
29.51
32.44
59.22
160 MHz
25.95
24.95
27.72
54.28
144 MHz
23.63
22.67
25.37
51.83
120 MHz
20.13
19.25
21.82
48.15
12 MHz
3.80
3.1
5.36
30.80
32.768 kHz
1.88
1.31
3.49
28.74
10 kHz
1.39
1.01
3.01
28.12
IDD_IDLE
mA
Idle mode, all peripherals
enable
HIRC, PLL, HXT, LIRC or LXT
clock
Note:
1.
When analog peripheral blocks such as ADC, ACMP, PLL, HIRC, LIRC, HXT and LXT are ON, an additional
power consumption should be considered.
2.
Based on characterization, not tested in production unless otherwise specified.
Table 9.3-2 Current Consumption in Idle Mode
M480 SERIES DATASHEET
May 08, 2020
Page 470 of 523
Rev 3.00
M480
Symbol
Test Conditions
Deep Power-down mode, all peripherals
disable
LXT[*1] LIRC
Typ[*2]
32.768 10
kHz kHz
TA = 25
°C
TA = -40
°C
0.35
0.15
-
-
Max[*3][*4]
Unit
TA = 25 °C TA = 105 °C
0.52
14.5
IDD_DPD
µA
V
-
0.81
0.62
1.01
15
Standby Power-down mode, all peripherals
disabled
-
-
1.48
0.98
3.05
400
Standby Power-down mode, RTC enable
V
-
1.95
1.46
3.55
401
-
V
1.93
1.3
3.77
402
Standby Power-down mode with 16 KB RAM
retention:
-
-
5.89
1.6
13.75
520
Standby Power-down mode with 32 KB RAM
retention:
-
-
10.19
2.11
25.06
810
Standby Power-down mode with 64 KB RAM
retention:
-
-
18.35
3.19
46.46
1370
Standby Power-down mode with 128 KB
RAM retention:
-
-
34.42
5.31
88.15
2800
Low leakage Power-down mode, all
peripherals disabled
-
-
230
52.65
682
19161
Low leakage Power-down mode,
RTC/WDT/Timer/UART enable
V
-
231
54.23
683
19270
Standby Power-down mode, RTC enable
RTC with LIRC10k
IDD_SPD
IDD_LLPD
µA
µA
Low leakage Power-down mode,
RTC/WDT/Timer enable
-
V
230
54.16
681
19301
Low leakage Power-down mode,
WDT/Timer use LIRC, RTC/UART use LXT
V
V
232
54.32
685
19334
Normal-Power-down mode, all peripherals
disable
-
-
672
185
2062
32045
Normal-Power-down mode,
WDT/Timer/UART/RTC enable
V
-
677
187
2090
32167
-
V
677
186
2091
32121
RTC/WDT/Timer with LIRC10k
IDD_NPD
Normal-Power-down mode,
WDT/Timer/UART enable
µA
RTC/WDT/Timer with LIRC10k
May 08, 2020
Page 471 of 523
Rev 3.00
M480 SERIES DATASHEET
Deep Power-down mode, RTC enable
M480
IDD_FWPD
Normal-Power-down mode, WDT use LIRC,
UART/Timer/RTC use LXT
V
V
678
187
2092
32165
Fast wake up Power-down mode, all
peripherals disable
-
-
793
291
2204
32308
Fast wake up Power-down mode,
WDT/Timer/UART/RTC enable
V
-
797
293
2216
32403
µA
Fast wake up Power-down mode,
WDT/Timer/UART enable
-
V
796
293
2212
32357
V
V
796
293
2213
32383
RTC/WDT/Timer with LIRC10k
Fast wake up Power-down mode, WDT use
LIRC, UART/Timer/RTC use LXT
Note:
1. Crystal used: AURUM XF66RU000032C0 with a CL of 20 pF for L3 gain level
2. VDD = AVDD = 3.3V.
3. Based on characterization, not tested in production unless otherwise specified.
4. When analog peripheral blocks such as ADC and ACMP are ON, an additional power consumption should be
considered.
5. Based on characterization, tested in production.
Table 9.3-3 Chip Current Consumption in Power-down Mode
M480 SERIES DATASHEET
May 08, 2020
Page 472 of 523
Rev 3.00
M480
9.3.2
On-Chip Peripheral Current Consumption
The typical values for TA= 25 °C and VDD = AVDD = 3.3 V unless otherwise specified.
All GPIO pins are set as output high of push pull mode without multi-function.
HCLK is the system clock, fHCLK = 192 MHz, fPCLK0, 1 = fHCLK/2.
The result value is calculated by measuring the difference of current consumption between all
peripherals clocked off and only one peripheral clocked on
IDD[*1]
PDMA
1166.72
EBI
231.78
SDH0
1233.37
CRC
63.38
CCAP
1199.17
USBH
858.77
SDH1
59.21
WDT
45.9
RTC
127.59
TMR0
361.64
TMR1
352.25
TMR2
314.95
TMR3
295.1
CLKO
84.24
ACMP01
60.76
2
I C0
28.94
I2C1
17.5
2
May 08, 2020
I C2
48.25
QSPI0
575.19
QSPI1
418.16
SPI0
560.07
SPI1
595.36
SPI2
619
UART0
272.94
UART1
208.76
UART2
263.46
UART3
170.93
UART4
211.44
UART5
169.76
Page 473 of 523
Unit
µA
Rev 3.00
M480 SERIES DATASHEET
Peripheral
M480
UART6
168.87
UART7
192.85
CAN0
236.13
CAN1
216.79
CAN2
211.6
USB FS OTG
333.04
EADC0
391.46
EADC1
308.99
I2S0
307.91
SC0
212.34
DAC
35.64
EPWM0
364.43
EPWM1
333.4
BPWM0
363.07
BPWM1
278.82
QEI0
51.81
QEI1
34.86
TRNG
311.47
ECAP0
66.53
ECAP1
35.24
Note:
M480 SERIES DATASHEET
1. Guaranteed by characterization results, not tested in production.
2. When the ADC is turned on, add an additional power consumption per ADC for the analog part.
3. When the ACMP is turned on, add an additional power consumption per ACMP for the analog part.
Table 9.3-4 Peripheral Current Consumption
9.3.3
Wakeup Time from Low-Power Modes
The wakeup times given in Table 9.3-5 is measured on a wakeup phase with a 12 MHz HIRC
oscillator.
Symbol
Parameter
Typ
Unit
cycles
tWU_IDLE
Wakeup from IDLE mode
5
tWU_FWPD
Wakeup from Fast-wakeup power down mode
10
Wakeup from normal power down mode
15
tWU_LLPD
Wakeup from low leakage power down mode
58
tWU_SPD
Wakeup from Standby Power-down mode
200
tWU_DPD
Deep Power-down mode (DPD)
200
tWU_PD
May 08, 2020
Page 474 of 523
µs
Rev 3.00
M480
Note:
1. Based on test during characterization, not tested in production.
2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first
Table 9.3-5 Low-power Mode Wake-up Timings
M480 SERIES DATASHEET
May 08, 2020
Page 475 of 523
Rev 3.00
M480
9.3.4
I/O Current Injection Characteristics
In general, I/O current injection due to external voltages below VSS or above VDD should be avoided
during normal product operation. However, the analog compoenent of the MCU is most likely to be
affected by the injection current , but it is not easily clarified when abnormal injection accidentally
happens. It is recommended to add a Schottky diode (pin to ground or pin to V DD) to pins that include
analog function which may potentially injection currents.
Symbol
Parameter
IINJ(PIN) Injected current by a I/O Pin
Negative
Injection
Positive
Injection
-0
0
Injected current on nReset pins
-0
0
Injected current on PF2~PF5, PA10,
mA PA11 and PB0~PB15 for analog
input function
-5
+5
Injected current on any other I/O
except analog input pin
Unit
Test Condition
Table 9.3-6 I/O Current Injection Characteristics
9.3.5
I/O DC Characteristics
9.3.5.1
PIN Input Characteristics
Symbol
Parameter
Input low voltage (Schmitt trigger)
VIL
Min
Typ
Max
0
-
0.3*VDD
0
-
0.7
0
-
0.5
0.7*VDD
-
VDD
1.5
-
VDD
0.8
-
VDD
-
0.2*VDD
-
Unit
V
Test Conditions
VDD = 2.7 V
Input low voltage (TTL trigger)
Input high voltage (Schmitt trigger)
M480 SERIES DATASHEET
VIH
VDD = 1.8 V
V
VDD = 3.3 V
Input high voltage (TTL trigger)
VHY[*1]
Hysteresis voltage of schmitt input
-1
ILK[*2]
VDD = 1.8 V
V
VSS < VIN < VDD,
1
Open-drain or input only mode
A
Input leakage current
-1
VDD < VIN < 5 V, Open-drain or
input only mode on any other 5v
tolerance pins
1
RPU[*1]
Pull up resistor
45
52
57
kΩ
RPD[*1]
Pull down resistor
45
52
57
kΩ
Note:
1.
Guaranteed by characterization result, not tested in production.
2.
Leakage could be higher than the maximum value, if abnormal injection happens.
Table 9.3-7 I/O Input Characteristics
May 08, 2020
Page 476 of 523
Rev 3.00
M480
9.3.5.2
I/O Output Characteristics
Symbol
Parameter
Min
Source
current
for
quasi-bidirectional mode
and high level
Typ
Max
Unit
6.91
7.76
µA
6.79
7.59
µA
16.98
17.40
mA
9.85
10.19
mA
16.21
16.63
mA
9.59
10.41
mA
-
pF
ISR[*1] [*2]
Source current for pushpull mode and high level
Sinkcurrent for push-pull
mode and low level
ISK[*1] [*2]
CIO[*1]
I/O pin capacitance
-
5
Test Conditions
VDD = 3.3 V
VIN=(VDD-0.4) V
VDD = 1.8 V
VIN=(VDD-0.4) V
VDD = 3.3 V
VIN=(VDD-0.4) V
VDD = 1.8 V
VIN=(VDD-0.4) V
VDD = 3.3 V
VIN= 0.4 V
VDD = 1.8 V
VIN= 0.4 V
Note:
1.
Guaranteed by characterization result, not tested in production.
2.
The ISR and ISK must always respect the abslute maximum current and the sum of I/O, CPU and peripheral must
not exceed ΣIDD and ΣISS.
Table 9.3-8 I/O Output Characteristics
9.3.5.3
nRESET Input Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
Negative going threshold, nRESET
-
-
0.3*VDD
V
VIHR
Positive going threshold, nRESET
0.7*VDD
-
-
V
RRST[*1]
Internal nRESET pull up resistor
45
52
47
kΩ
-
24
-
-
24
-
75
-
155
tFR[*1]
nRESET input filtered pulse time
Normal run and Idle mode
µs
Fast wake up Power-down mode
Power-down mode
Note:
1.
Guaranteed by characterization result, not tested in production.
2.
It is recommended to add a 10 kΩ and 10uF capacitor at nRESET pin to keep reset signal stable.
Table 9.3-9 nRESET Input Characteristics
May 08, 2020
Page 477 of 523
Rev 3.00
M480 SERIES DATASHEET
VILR
Test Conditions
M480
9.4 AC Electrical Characteristics
9.4.1
48 MHz Internal High Speed RC Oscillator (HIRC48M)
The 48 MHz RC oscillator is calibrated in production.
Symbol.
VDD
Parameter
Min
Typ
Max
Unit
Operating voltage
1.75
-
3.6
V
Oscillator frequnecy
47.52
48
48.48
MHz
-1
-
1
%
-4[*1]
-
4[*1]
%
fHRC
Frequency drift over temperarure and
volatge
IHRC[*1]
Operating current
-
-
230
µA
TS[*2]
Stable time
-
-
20
µs
Test Conditions
TA = 25 °C,
VDD =1.8 ~ 3.6V
TA = 25 °C,
VDD = 1.8 ~ 3.6V
TA = -40C ~ +105 °C,
VDD = 1.8 ~ 3.6V
TA = -40C ~ +105 °C,
VDD = 1.8 ~ 3.6V
Note:
1. Guaranteed by characterization result, not tested in production.
2. Guaranteed by design.
Table 9.4-148 MHz Internal High Speed RC Oscillator(HIRC) Characteristics
M480 SERIES DATASHEET
May 08, 2020
Page 478 of 523
Rev 3.00
M480
9.4.2
12 MHz Internal High Speed RC Oscillator (HIRC)
The 12 MHz RC oscillator is calibrated in production.
Symbol.
VDD
Parameter
Min
Typ
Max
Unit
Operating voltage
1.75
-
3.6
V
Oscillator frequnecy
11.76
12
12.24
MHz
-1
-
1
%
-3[*1]
-
3[*1]
%
Operating current
-
-
215
µA
Stable time
-
-
20
µs
FMRC
Frequency drift over temperarure and
volatge
IMRC[*1]
TS[*2]
Test Conditions
TA = 25 °C,
VDD = 1.8 ~ 3.6V
TA = 25 °C,
VDD = 1.8 ~ 3.6V
TA = -40C ~ +105 °C,
VDD = 1.8 ~ 3.6V
TA = -40C ~ +105 °C,
VDD = 1.8 ~ 3.6V
Note:
1.
Guaranteed by characterization result, not tested in production.
2.
Guaranteed by design.
Table 9.4-2 12 MHz Internal High Speed RC Oscillator(HIRC) Characteristics
M480 SERIES DATASHEET
May 08, 2020
Page 479 of 523
Rev 3.00
M480
9.4.3
10 kHz Internal Low Speed RC Oscillator (LIRC)
Symbol
VDD
Parameter
Operating voltage
Oscillator frequnecy
FLRC [*2]
Min [*1]
Typ
Max [*1]
Unit
1.75
-
3.6
V
-
10
-
kHz
-1
-
1
%
-10
-
10
%
Frequency drift over temperarure
and volatge
Test Conditions
TA = 25 °C,
VDD = 1.8 ~ 3.6V
TA = 25 °C,
VDD = 1.8 ~ 3.6V
TA=-40~105°C
VDD=1.8V~3.6V
Without software calibration
ILRC
Operating current
-
0.85
1
µA
TS
Stable time
-
500
-
μs
VDD = 3.3V
TA=-40~105°C
VDD=1.8V~3.6V
Note:
1. Guaranteed by characterization, not tested in production.
2. The10 kHz low speed RC oscillator can be calibrated by user.
3. Guaranteed by design.
4. The LIRC duty cycle is 16/84, if need 50/50 duty clock output, user should divided by 2 at least.
Table 9.4-3 10 kHz Internal Low Speed RC Oscillator(LIRC) Characteristics
M480 SERIES DATASHEET
May 08, 2020
Page 480 of 523
Rev 3.00
M480
9.4.4
External 4~24 MHz High Speed Crystal/Ceramic Resonator (HXT) Characteristics
The high-speed external (HXT) clock can be supplied with a 4 to 24 MHz crystal/ceramic resonator
oscillator. All the information given in this secion are based on characterization results obtained with
typical external components. In the application, the external components have to be placed as close
as possible to the XT1_IN and XT1_Out pins and must not be connected to any other devices in order
to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer
for more details on the resonator characteristics (frequency, package, accuracy).
Min[*1]
Typ
Max[*1]
Unit
1.8
-
3.6
V
Internal feedback resister
-
1000
-
kΩ
Oscillator frequency
4
-
24
MHz
-
160
281
280
417
Symbol
VDD
Rf
fHXT
IHXT
TS
DuHXT
Vpp
Parameter
Operating voltage
Current consumption
Peak-to-peak amplitude
4 MHz, Gain = L0
12 MHz, Gain = L1
µA
-
400
540
16 MHz, Gain = L2
-
600
690
24 Mhz, Gain = L3
-
1300
1974
4 MHz, Gain = L0
458
605
Stable time
Duty cycle
Test Conditions
12 MHz, Gain = L1
µs
-
326
439
16 MHz, Gain = L2
-
268
414
24 Mhz, Gain = L3
40
-
60
%
-
1.47
-
V
VDD = 3.3V @ fHXT = 12 MHz
Note:
1. Guaranteed by characterization, not tested in production.
M480 SERIES DATASHEET
Table 9.4-4 External 4~24 MHz High Speed Crystal (HXT) Oscillator
May 08, 2020
Page 481 of 523
Rev 3.00
M480
Symbol
Parameter
Min [*1]
Typ
Max [*1]
-
-
150
Unit
Crystal @4 MHz
50
Rs
Test Conditions
Crystal @12 MHz
Ω
Equivalent series resisotr(ESR)
-
-
40
Crystal @16 MHz
-
-
40
Crystal @24 MHz
Note:
1.
Guaranteed by characterization, not tested in production.
Table 9.4-5 External 4~24 MHz High Speed Crystal Characteristics
9.4.4.1
Typical Crystal Application Circuits
For C1 and C2, it is recommended to use high-quality external ceramic capacitors in 10 pF ~ 25 pF
range, designed for high-frequency applications, and selected to match the requirements of the crystal
or resonator. The crystal manufacturer typically specifies a load capacitance which is the series
combination of C1 and C2. PCB and MCU pin capacitance must be included (8 pF can be used as a
rough estimate of the combined pin and board capacitance) when sizing C1 and C2.
CRYSTAL
C1
C2
R1
4 MHz ~ 24 MHz
20 pF
20 pF
without
XT1_OUT
M480 SERIES DATASHEET
C2
XT1_IN
R1
C1
Figure 9.4-1 Typical Crystal Application Circuit
May 08, 2020
Page 482 of 523
Rev 3.00
M480
9.4.5
External 4~24 MHz High Speed Clock Input Signal Characteristics
For clock input mode the HXT oscillator is switched off and XT1_IN is a standard input pin to receive
external clock. The external clock signal has to respect the Table 9.4-6. The characteristics result from
tests performed using a wavefrom generator.
Symbol
fHXT_ext
Parameter
External user clock source
frequency
Min [*1]
Typ
Max [*1]
Unit
4
-
24
MHz
Test Conditions
tCHCX
Clock high time
8
-
-
ns
tCLCX
Clock low time
8
-
-
ns
tCLCH
Clock rise time
-
-
10
ns
Low (10%) to high level (90%)
rise time
tCHCL
Clock fall time
-
-
10
ns
High (90%) to low level (10%)
fall time
40
-
60
%
DuE_HXT
Duty cycle
VIH
Input high voltage
0.7*VDD
-
VDD
V
VIL
Input low voltage
VSS
-
0.3*VDD
V
External
clock source
XT1_IN
tCLCL
M480 SERIES DATASHEET
tCLCH
VIH
VIL
90%
tCLCX
10%
tCHCL
tCHCX
Note:
1. Guaranteed by characterization, not tested in production.
Table 9.4-6 External 4~24 MHz High Speed Clock Input Signal
May 08, 2020
Page 483 of 523
Rev 3.00
M480
9.4.6
External 32.768 kHz Low Speed Crystal/Ceramic Resonator (LXT) Characteristics
The low-speed external (LXT) clock can be supplied with a 32.768 kHz crystal/ceramic resonator
oscillator. All the information given in this secion are based on characterization results obtained with
typical external components. In the application, the external components have to be placed as close
as possible to the X32_OUT and X32_IN pins and must not be connected to any other devices in
order to minimize output distortion and startup stabilization time. Refer to the crystal resonator
manufacturer for more details on the resonator characteristics (frequency, package, accuracy).
Symbol
Parameter
Min [*1]
Typ
Max [*1]
Unit
VDD
Operation voltage
1.8
-
3.6
V
TLXT
Temperature range
-40
-
105
C
-
15
-
MΩ
Rf
FLXT
Internal feedback resistor
Oscillator frequency
32.768
-
ILXT
kHz
0.25
0.49
0.42
0.8
-
0.85
1.66
Current consumption
Test Conditions
ESR=35 kΩ, Gain = L1
A
ESR=35 kΩ, Gain = L4
ESR=70 kΩ, Gain = L7
TsLXT
Stable time
-
1.5
2
s
DuLXT
Duty cycle
30
-
70
%
Note:
1. Guaranteed by characterization, not tested in production.
Table 9.4-7 External 32.768 kHz Low Speed Crystal (LXT) Oscillator
Symbol
Rs
Parameter
Equivalnet Series Resisotr(ESR)
Min
Typ
Max
Unit
Test Conditions
-
35
70
kΩ
Crystal @32.768 kHz
M480 SERIES DATASHEET
Table 9.4-8 External 32.768 kHz Low Speed Crystal Characteristics
9.4.6.1
Typical Crystal Application Circuits
CRYSTAL
C1
C2
R1
32.768 kHz, ESR < 70 KΩ
20 pF
20 pF
without
X32_OUT
C2
X32_IN
R1
C1
Figure 9.4-2 Typical 32.768 kHz Crystal Application Circuit
May 08, 2020
Page 484 of 523
Rev 3.00
M480
9.4.7
External 32.768 kHz Low Speed Clock Input Signal Characteristics
For clock input mode the LXT oscillator is switched off and X32_IN is a standard input pin to receive
external clock. The external clock signal has to respect the Table 9.4-9. The characteristics result from
tests performed using a wavefrom generator.
Symbol
Parameter
Min [*1]
Typ
Max [*1]
Unit
-
32.768
-
kHz
Test Conditions
fLSE_ext
External clock source frequency
tCHCX
Clock high time
450
-
-
ns
tCLCX
Clock low time
450
-
-
ns
tCLCH
Clock rise time
-
-
50
ns
Low (10%) to high level (90%)
rise time
tCHCL
Clock fall time
-
-
50
ns
High (90%) to low level (10%) fall
time
30
-
70
%
DuE_LXT
Duty cycle
Xin_VIH
LXT input pin input high voltage
0.7*VDD
-
VDD
V
Xin_VIL
LXT input pin input low voltage
VSS
-
0.3*VDD
V
External
clock source
X32_IN
tCLCL
tCLCH
VIH
90%
tCLCX
tCHCL
M480 SERIES DATASHEET
10%
VIL
tCHCX
Note:
1. Guaranteed by design, not tested in production
Table 9.4-9 External 32.768 kHz Low Speed Clock Input Signal
May 08, 2020
Page 485 of 523
Rev 3.00
M480
9.4.8
PLL Characteristics
Min[*1]
Typ
Max[*1]
Unit
PLL input clock
4
-
24
MHz
fPLL_OUT
PLL multiplier output clock
50
-
480
MHz
fPLL_REF
PLL reference clock
4
-
8
MHz
fPLL_VCO
PLL voltage controlled oscillator
200
-
480
MHz
PLL locking time
-
-
100
µs
Jitter[*2]
Cycle-to-cycle Jitter
-
-
500
ps
IDD
Power consumption
-
3.56
4.4
mA
Symbol
fPLL_in
TL
Parameter
Test Conditions
VDD=3.3V @ fPLL_VCO = 500
MHz
Note:
1. Guaranteed by characterization, not tested in production
2. Guaranteed by design, not tested in production
Table 9.4-10 PLL Characteristics
M480 SERIES DATASHEET
May 08, 2020
Page 486 of 523
Rev 3.00
M480
9.4.9
I/O AC Characteristics
Symbol
Parameter
Output high (90%) to low level (10%) fall time
(Normal Slew Rate)
tf(IO)out
Output high (90%) to low level (10%) fall time
(High Slew Rate)
Output high (90%) to low level (10%) fall time
(Fast Slew Rate)
(Normal Slew Rate)
tr(IO)out
Output low (10%) to high level (90%) rise time
Max[*1].
-
3.5
CL = 30 pF, VDD >= 3.6 V
-
2
CL = 10 pF, VDD >= 3.6 V
-
4.5
CL = 30 pF, VDD >= 2.7 V
-
3
CL = 10 pF, VDD >= 2.7 V
-
8
CL = 30 pF, VDD >= 1.8 V
-
5.5
CL = 10 pF, VDD >= 1.8 V
-
3
CL = 30 pF, VDD >= 3.6 V
-
1.5
CL = 10 pF, VDD >= 3.6 V
-
3.5
Test Conditions[*2]
CL = 30 pF, VDD >= 2.7 V
ns
-
2
CL = 10 pF, VDD >= 2.7 V
-
6.5
CL = 30 pF, VDD >= 1.8 V
-
3.5
CL = 10 pF, VDD >= 1.8 V
-
2.5
CL = 30 pF, VDD >= 3.6 V
-
1.5
CL = 10 pF, VDD >= 3.6 V
-
3
CL = 30 pF, VDD >= 2.7 V
-
2
CL = 10 pF, VDD >= 2.7 V
-
5.5
CL = 30 pF, VDD >= 1.8 V
-
3.5
CL = 10 pF, VDD >= 1.8 V
-
4
CL = 30 pF, VDD >= 3.6 V
-
2.5
CL = 10 pF, VDD >= 3.6 V
-
4.5
CL = 30 pF, VDD >= 2.7 V
ns
-
3
CL = 10 pF, VDD >= 2.7 V
-
8
CL = 30 pF, VDD >= 1.8 V
-
5.5
CL = 10 pF, VDD >= 1.8 V
-
2.5
CL = 30 pF, VDD >= 3.6 V
-
1.5
CL = 10 pF, VDD >= 3.6 V
-
3
-
2
CL = 10 pF, VDD >= 2.7 V
-
5
CL = 30 pF, VDD >= 1.8 V
(High Slew Rate)
May 08, 2020
Unit
Page 487 of 523
ns
CL = 30 pF, VDD >= 2.7 V
Rev 3.00
M480 SERIES DATASHEET
Output low (10%) to high level (90%) rise time
Typ.
M480
Output low (10%) to high level (90%) rise time
(Fasr Slew Rate)
I/O maximum frequency
(Normal Slew Rate)
fmax(IO)out[*3]
I/O maximum frequency
(High Slew Rate)
M480 SERIES DATASHEET
I/O maximum frequency
(Fastigh Slew Rate)
IDIO[*4]
-
3
CL = 10 pF, VDD >= 1.8 V
-
2.5
CL = 30 pF, VDD >= 3.6 V
-
1.5
CL = 10 pF, VDD >= 3.6 V
-
3
CL = 30 pF, VDD >= 2.7 V
ns
-
2
CL = 10 pF, VDD >= 2.7 V
-
5
CL = 30 pF, VDD >= 1.8 V
-
3
CL = 10 pF, VDD >= 1.8 V
-
88.9
CL = 30 pF, VDD >= 3.6 V
-
148.1
CL = 10 pF, VDD >= 3.6 V
-
74.1
CL = 30 pF, VDD >= 2.7 V
MHz
-
111.1
CL = 10 pF, VDD >= 2.7 V
-
41.7
CL = 30 pF, VDD >= 1.8 V
-
60.6
CL = 10 pF, VDD >= 1.8 V
-
121.2
CL = 30 pF, VDD >= 3.6 V
-
222.2
CL = 10 pF, VDD >= 3.6 V
-
102.6
CL = 30 pF, VDD >= 2.7 V
MHz
-
166.7
CL = 10 pF, VDD >= 2.7 V
-
58.0
CL = 30 pF, VDD >= 1.8 V
-
102.6
CL = 10 pF, VDD >= 1.8 V
-
133.3
CL = 30 pF, VDD >= 3.6 V
-
222.2
CL = 10 pF, VDD >= 3.6 V
-
111.1
CL = 30 pF, VDD >= 2.7 V
MHz
-
166.7
CL = 10 pF, VDD >= 2.7 V
-
63.5
CL = 30 pF, VDD >= 1.8 V
-
102.6
CL = 10 pF, VDD >= 1.8 V
2.77
-
1.19
-
I/O dynamic current consumption
CL = 30 pF, VDD = 3.3 V,
f(IO)out = 24 MHz
CL = 10 pF, VDD = 3.3 V,
f(IO)out = 24 MHz
mA
0.69
-
CL = 30 pF, VDD = 3.3 V,
f(IO)out = 6 MHz
0.3
May 08, 2020
Page 488 of 523
-
CL = 10 pF, VDD = 3.3 V,
f(IO)out = 6 MHz
Rev 3.00
M480
Note:
1.
Guaranteed by characterization result, not tested in production.
2.
CL is a external capacitive load to simulate PCB and device loading.
3.
The maximum frequency is defined by
4.
The I/O dynamic current consumption is defined by
.
Table 9.4-11 I/O AC Characteristics
M480 SERIES DATASHEET
May 08, 2020
Page 489 of 523
Rev 3.00
M480
9.5 Analog Characteristics
9.5.1
LDO
Symbol
Parameter
Min
Typ
Max
Unit
VDD
Power supply
1.8
-
3.6
V
VLDO
Output voltage
-
1.26
-
V
-40
-
105
°C
TA
Temperature
Test Condition
Note:
1.
It is recommended a 0.1μF bypass capacitor is connected between VDD and the closest VSS pin of the device.
2.
For ensuring power stability, a 1μF capacitor must be connected between LDO_CAP pin and the closest V SS
pin of the device.
9.5.2
Reset and Power Control Block Characteristics
The parameters in Table 9.5-1 are derived from tests performed under ambient temperature.
Symbol
Parameter
Min
Typ
Max
Unit
µA
Test Conditions
IPOR[*1]
POR operating current
-
35
45
ILVR[*1]
LVR operating current
-
0.3
0.6
AVDD = 3.6V, Normal mode
IBOD[*1]
BOD operating current
-
30
40
AVDD = 3.6V, Normal
mode
-
1
-
AVDD = 3.6V
AVDD = 3.6V, Low Power
mode
M480 SERIES DATASHEET
VPOR
POR reset voltage
1.38
1.46
1.54
VLVR
LVR reset voltage
1.45
1.50
1.55
-
VBOD
BOD brown-out detect voltage
1.50
1.60
1.70
BODVL = 0
1.70
1.80
1.90
BODVL = 1
1.90
2.00
2.10
BODVL = 2
2.10
2.20
2.30
BODVL = 3
2.30
2.40
2.50
BODVL = 4
2.50
2.60
2.70
BODVL = 5
2.70
2.80
2.90
BODVL = 6
2.90
3.00
3.10
BODVL = 7
1.58
1.68
1.78
BODVL = 0
1.78
1.88
1.98
BODVL = 1
1.98
2.08
2.18
BODVL = 2
2.18
2.28
2.38
BODVL = 3
2.38
2.48
2.58
BODVL = 4
2.58
2.68
2.78
BODVL = 5
2.78
2.88
2.98
BODVL = 6
(Falling edge)
BOD brown-out detect voltage
(Rising edge)
May 08, 2020
Page 490 of 523
V
-
Rev 3.00
M480
2.98
3.08
3.18
BODVL = 7
TLVR_SU[*1]
LVR startup time
-
200
256
TLVR_RE[*1]
LVR respond time
-
1
2
Normal mode
TBOD_SU[*1]
BOD startup time
-
1000
-
-
TBOD_RE[*1]
BOD respond time
-
-
100
-
-
12000
VDD rise time rate
10
-
-
VDD fall time rate
10
-
-
POR Enabled
300
-
-
LVR Enabled
666
-
-
BOD 1.6V Enabled,
Normal mode
285
-
-
BOD 1.8V Enabled,
Normal mode
180
-
-
BOD 2.0V Enabled,
Normal mode
133
-
-
BOD 2.2V Enabled,
Normal mode
105
-
-
BOD 2.4V Enabled,
Normal mode
85
-
-
BOD 2.6V Enabled,
Normal mode
75
-
-
BOD 2.8V Enabled,
Normal mode
RVDDR[*1]
RVDDF
[*1]
µs
-
Normal mode
Low Power mode
µs/V
POR Enabled
BOD 3.0V Enabled,
Normal mode
65
M480 SERIES DATASHEET
Note:
1. Guaranteed by characterization, not tested in production.
2. Design for specified applcaiton.
Table 9.5-1 Reset and Power Control Unit
VDD
RVDDR
RVDDF
VBOD
VLVR
VPOR
Time
Figure 9.5-1 Power Ramp Up/Down Condition
May 08, 2020
Page 491 of 523
Rev 3.00
M480
9.5.3
12-bit SAR ADC
9.5.3.1
ADC0 Characteristics
Fast Speed Channel
Symbol
Min
Typ
Max
Unit
Temperature
-40
-
105
°C
AVDD
Analog operating voltage
1.8
-
3.6
V
VREF
Reference voltage
1.6
-
AVDD
V
0
-
VREF
V
TA
VIN
Parameter
ADC channel input voltage
NR
AVDD = VDD
AVDD = VDD = VREF = 3.3V
Operating current (AVDD current)
IADC[*1]
Test Conditions
(Enable ADC and disable all other analog
modules)
599
-
629
µA
ADC Clock Rate = 80 MHz
High speed channel
Resolution
12
M480 SERIES DATASHEET
FADC
ADC Clock frequency
TSMP
Sampling Time
2
1/FADC
TCONV
Conversion time
14
1/FADC TCONV = TSMP + 12
FSPS
Sampling Rate
TBD
-
5
TEN
Enable to ready time
TBD
-
-
μs
INL
Integral Non-Linearity Error
-4.42
-
2.4
LSB
DNL
Differential Non-Linearity Error
-1
-
4.62
LSB
EG
Gain error
0.5
-
2.06
LSB
EO
Offset error
0
-
1.81
LSB
EA
Absolute Error
3.69
-
6.37
LSB
-
5
-
pF
CIN[*1]
Internal Capacitance
TBD
-
Bit
80
MHz
FADC = 1/TADC
MSPS High speed channel
VREF = AVDD = 3.3V
package with VREF pin
VREF = AVDD = 3.3V
package with VREF pin
VREF = AVDD = 3.3V
package with VREF pin
VREF = AVDD = 3.3V
package with VREF pin
VREF = AVDD = 3.3V
package with VREF pin
Note:
1. Guaranteed by characterization result, not tested in production.
2. REX max formula is used to determine the maximum external impedance allowed for 1/4 LSB error. N = 12 (based on
12-bit resoluton) and k is the number of sampling clocks (TSMP). CEX represents the capacitance of PCB and pad and
is combined with REX into a low-pass filter. Once the REX and CEX values are too large, it is possible to filter the real
signal and reduce the ADC accuracy.
Low Speed Channel
Symbol
May 08, 2020
Parameter
Min
Typ
Page 492 of 523
Max
Unit
Test Conditions
Rev 3.00
M480
Symbol
Min
Typ
Max
Unit
Temperature
-40
-
105
°C
AVDD
Analog operating voltage
1.8
-
3.6
V
VREF
Reference voltage
1.6
-
AVDD
V
0
-
VREF
V
TA
VIN
Parameter
ADC channel input voltage
NR
AVDD = VDD
AVDD = VDD = VREF = 1.62V ~ 3.3V
Operating current (AVDD current)
IADC[*1]
Test Conditions
(Enable ADC and disable all other analog
modules)
163
-
270
µA
ADC Clock Rate = 32 MHz
High speed channel
Resolution
12
TBD
-
Bit
FADC
ADC Clock frequency
80
MHz
FADC = 1/TADC
TSMP
Sampling Time
2
1/FADC
TCONV
Conversion time
14
1/FADC TCONV = TSMP + 12
Low speed channel
MSPS Note: it needs more extend
sampling time to slow down the
sampling rate.
FSPS
Sampling Rate
0.1
-
2
TEN
Enable to ready time
TBD
-
-
μs
INL
Integral Non-Linearity Error
-2.17
-
1.89
LSB
DNL
Differential Non-Linearity Error
-1
-
1.87
LSB
Gain error
0.31
-
2.56
LSB
EO
Offset error
-0.31
-
2.19
LSB
EA
Absolute Error
-3.5
-
5.87
LSB
-
5
-
pF
CIN[*1]
Internal Capacitance
package with VREF pin
VREF = AVDD = 1.62V ~ 3.3V
package with VREF pin
VREF = AVDD = 1.62V ~ 3.3V
package with VREF pin
VREF = AVDD = 1.62V ~ 3.3V
package with VREF pin
VREF = AVDD = 1.62V ~ 3.3V
package with VREF pin
Note:
1.
Guaranteed by characterization result, not tested in production.
2.
REX max formula is used to determine the maximum external impedance allowed for 1/4 LSB error. N = 12
(based on 12-bit resoluton) and k is the number of sampling clocks (TSMP). CEX represents the capacitance of
PCB and pad and is combined with REX into a low-pass filter. Once the REX and CEX values are too large, it is
possible to filter the real signal and reduce the ADC accuracy.
9.5.3.2
ADC1 Characteristics
Fast Speed Channel
Symbol
TA
Parameter
Temperature
May 08, 2020
Min
Typ
Max
Unit
-40
-
105
°C
Page 493 of 523
Test Conditions
Rev 3.00
M480 SERIES DATASHEET
EG
VREF = AVDD = 1.62V ~ 3.3V
M480
Symbol
Parameter
Min
Typ
Max
Unit
AVDD
Analog operating voltage
1.8
-
3.6
V
VREF
Reference voltage
1.6
-
AVDD
V
0
-
VREF
V
596
-
627
µA
VIN
ADC channel input voltage
NR
AVDD = VDD
AVDD = VDD = VREF = 3.3V
Operating current (AVDD current)
IADC[*1]
Test Conditions
(Enable ADC and disable all other analog
modules)
ADC Clock Rate = 80 MHz
High speed channel
Resolution
12
TBD
-
Bit
FADC
ADC Clock frequency
80
MHz
TSMP
Sampling Time
2
1/FADC
TCONV
Conversion time
14
1/FADC TCONV = TSMP + 12
FSPS
Sampling Rate
TBD
-
5
TEN
Enable to ready time
TBD
-
-
μs
INL
Integral Non-Linearity Error
-6.22
-
2.17
LSB
DNL
Differential Non-Linearity Error
-1
-
6.62
LSB
MSPS High speed channel
M480 SERIES DATASHEET
EG
Gain error
1.06
-
2.94
LSB
EO
Offset error
0
-
1.75
LSB
EA
Absolute Error
3
-
5.69
LSB
Internal Capacitance
-
5
-
pF
CIN[*1]
FADC = 1/TADC
VREF = AVDD = 3.3V
package with VREF pin
VREF = AVDD = 3.3V
package with VREF pin
VREF = AVDD = 3.3V
package with VREF pin
VREF = AVDD = 3.3V
package with VREF pin
VREF = AVDD = 3.3V
package with VREF pin
Note:
1.
Guaranteed by characterization result, not tested in production.
2.
REX max formula is used to determine the maximum external impedance allowed for 1/4 LSB error. N = 12
(based on 12-bit resoluton) and k is the number of sampling clocks (TSMP). CEX represents the capacitance of
PCB and pad and is combined with REX into a low-pass filter. Once the REX and CEX values are too large, it is
possible to filter the real signal and reduce the ADC accuracy.
Low Speed Channel
Symbol
Min
Typ
Max
Unit
Temperature
-40
-
105
°C
AVDD
Analog operating voltage
1.8
-
3.6
V
VREF
Reference voltage
1.6
-
AVDD
V
0
-
VREF
V
TA
VIN
Parameter
ADC channel input voltage
May 08, 2020
Page 494 of 523
Test Conditions
AVDD = VDD
Rev 3.00
M480
Symbol
Parameter
Min
Typ
Max
Unit
162
-
269
µA
AVDD = VDD = VREF = 1.62V ~ 3.3V
Operating current (AVDD current)
IADC[*1]
NR
Test Conditions
(Enable ADC and disable all other analog
modules)
ADC Clock Rate = 32 MHz
High speed channel
Resolution
12
1.5
-
Bit
FADC
ADC Clock frequency
32
MHz
TSMP
Sampling Time
2
1/FADC
TCONV
Conversion time
14
1/FADC TCONV = TSMP + 12
FSPS
Sampling Rate
0.1
-
2
TEN
Enable to ready time
TBD
-
-
μs
INL
Integral Non-Linearity Error
-1.96
-
1.22
LSB
DNL
Differential Non-Linearity Error
-1
-
1.94
LSB
MSPS Low speed channel
EG
Gain error
0.62
-
3.19
LSB
EO
Offset error
-0.44
-
2.62
LSB
EA
Absolute Error
2.81
-
6.19
LSB
-
5
-
pF
CIN[*1]
Internal Capacitance
FADC = 1/TADC
VREF = AVDD = 1.62V ~ 3.3V
package with VREF pin
VREF = AVDD = 1.62V ~ 3.3V
package with VREF pin
VREF = AVDD = 1.62V ~ 3.3V
package with VREF pin
VREF = AVDD = 1.62V ~ 3.3V
package with VREF pin
VREF = AVDD = 1.62V ~ 3.3V
package with VREF pin
Note:
Guaranteed by characterization result, not tested in production.
2.
REX max formula is used to determine the maximum external impedance allowed for 1/4 LSB error. N = 12
(based on 12-bit resoluton) and k is the number of sampling clocks (TSMP). CEX represents the capacitance of
PCB and pad and is combined with REX into a low-pass filter. Once the REX and CEX values are too large, it is
possible to filter the real signal and reduce the ADC accuracy.
May 08, 2020
Page 495 of 523
Rev 3.00
M480 SERIES DATASHEET
1.
M480
VDD
REX
EADC_CHx
RIN
CIN
CEX
VEX
12-bit
Converter
Note: Injection current is a important topic of ADC accuracy. Injecting current on any analog input pins
should be avoided to protect the conversion being performed on another analog input. It is
recommended to add Schottky diodes (pin to ground and pin to power) to analog pins which may
potentially inject currents.
EF (Full scale error) = EO + EG
Gain Error
EG
Offset Error
EO
4095
4094
4093
4092
M480 SERIES DATASHEET
Ideal transfer curve
7
6
ADC
output
code
5
Actual transfer curve
4
3
2
DNL
1
1 LSB
Offset Error
EO
Analog input voltage
(LSB)
4095
Note: The INL is the peak difference between the transition point of the steps of the calibrated transfer
curve and the ideal transfer curve. A calibrated transfer curve means it has calibrated the offset and
gain error from the actual transfer curve.
9.5.4
Temperature Sensor
May 08, 2020
Page 496 of 523
Rev 3.00
M480
Symbol
Parameter
Min Typ
Max
Unit
VDD
Operating Voltage
1.8
3.6
V
TA
Temperature Range
-40
105
°C
ITEMP
Current Consumption [*3]
A
16
Tc
Temperature Coefficient [*3]
-1.77
Vos
Offset Voltage when TA = 0°C [*3]
710.2
tS
Stable time[*2]
1
µs
ADC sampling time when reading the temperature (5pF cap load) [*1]
3
µs
TS_temp
-1.82
-1.84
mV/°C
716.8
mV
Note:
1.
VTEMP (mV) = Tc (mV/°C) x Temperature (°C) + Vos (mV)
2.
Guaranteed by design, not tested in production
3.
Guaranteed by characteristic, not tested in production
M480 SERIES DATASHEET
May 08, 2020
Page 497 of 523
Rev 3.00
M480
9.5.5
Analog Comparator Controller (ACMP)
The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature (TA), and the typical
values for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
Symbol
AVDD
TA
IACMP[*2]
Parameter
Min
Typ
Max Unit
Analog supply voltage
1.8
-
3.6
V
Temperature
-40
-
105
°C
-
75
90
-
10
30
-
3
10
MODESEL = 01
-
1.2
6
MODESEL = 00
ACMP operating current
Test Conditions
VDD = AVDD
MODESEL = 11
A
MODESEL = 10
VCM[*2]
Input common mode voltage range
0.1
1/2
AVDD
AVDD
-0.1
VDI[*2]
Differential input voltage sensitivity
-
10
-
mV Hysteresis disable (HYSSEL = 00)
Input offset voltage
-
5
10
mV Hysteresis disable (HYSSEL = 00)
-
10
20
mV HYSSEL = 01
20
40
HYSSEL = 10
30
60
HYSSEL = 11
43
70
-
-
180
250
-
350
600
Voffset[*2]
Vhys[*2]
Av[*1]
Td[*2]
Hysteresis window
DC voltage Gain
Propagation delay
dB
MODESEL = 11
MODESEL = 10
Ns
M480 SERIES DATASHEET
-
750
2000
MODESEL = 01
-
1600
4500
MODESEL = 00
250 + 450 +
Td
Td
TSetup[*2]
Setup time
-
ACRV[*2]
CRV output voltage
-5
-
5
%
RCRV[*2]
Unit resistor value
-
4.2
-
kΩ
Setup time
-
-
TBD
µs
Operating current
-
32.7
-
A
TSETUP_CRV[*2]
IDD_CRV[*2]
Us
AVDD x (1/6+CRVCTL/24)
CRV output voltage settle to ±5%
Note:
1. Guaranteed by design, not tested in production
2. Guaranteed by characteristic, not tested in production
Table 9.5-2 ACMP Characteristics
May 08, 2020
Page 498 of 523
Rev 3.00
M480
9.5.6
Digital to Analog Converter (DAC)
The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature (TA), and the typical
values for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
Symbol
Parameter
AVDD
Analog supply voltage
NR
Resolution
VREF
Reference supply voltage
DNL[*2]
INL[*2]
OE[*2]
GE[*2]
-
VO[*1]
Max
1.8
-
3.6
12
Unit
Test Condition
V
-
bit
-
1.5
-
AVDD
V
VREF ≤ AVDD
-
-
±2
LSB
12-bit mode
-
-
±0.5
LSB
8-bit mode
-
-
±4
LSB
12-bit mode
-
-
±1
LSB
8-bit mode
-
-
±30
LSB
-
-
±4
LSB
-
-
±2
LSB
-
-
±8
LSB
-
-
±4
LSB
-
-
±2
LSB
-
-
±10
LSB
-
-
±4
LSB
-
-
±2
LSB
Differential non-linearity error
Integral non-linearity error
Offset Error
Gain Error
Absolute Error
Monotonic
10-bit guaranteed
-
0.2
AVDD 0.2
1*LSB
VREF 1*LSB
V
12-bit mode
DACOUT buffer ON
12-bit mode
DACOUT buffer OFF
8-bit mode
12-bit mode
DACOUT buffer ON
12-bit mode
DACOUT buffer OFF
8-bit mode
12-bit mode
DACOUT buffer ON
12-bit mode
DACOUT buffer OFF
8-bit mode
DACOUT buffer ON
Output Voltage
RLOAD[*2] [*3] Resistive load
RO[*2]
Typ
M480 SERIES DATASHEET
AE[*2]
Min
Output impedance
7.5
-
-
10
-
-
DACOUT buffer OFF
-
kΩ
DACOUT buffer ON
12
kΩ
DACOUT buffer OFF
50
pF
DACOUT buffer ON
20
pF
DACOUT buffer OFF
CLOAD[*2] [*4] Capacitive load
May 08, 2020
Page 499 of 523
Rev 3.00
M480
IDAC_AVDD[*2] DAC operating current on AVDD supply
-
340
550
A
AVDD = 3.6V, no load, lowest code
(0x000)
AVDD = 3.6V, no load, middle code
(0x800)
IDAC_VREF[*2] DAC operating current on VREF supply
TB[*2]
Settling Time
-
-
-
5
160
6
A
μs
VREF =3.6V, no load, middle code
(0x800)
Full scale: for a 12-bit input code
transition between the lowest and
the highest input codes when
DAC_OUT reaches final value +/-1
LSB,
CLOAD ≤ 50pF, RLOAD ≥ 5kΩ
FS
Update Rate
TWAKEUP
Wake-up Time
-
-
-
9
1
15
MSPS
μs
Max. frequency for a correct
DAC_OUT change from core i to
i+1LSB, CLOAD ≤ 50pF, RLOAD ≥ 5kΩ
Wakeup time from OFF state. Input
code between lowest and highest
possible codes.
DAC clock source = 1 MHz
[*1]
PSRR
Power Supply Rejection Ratio
-
-60
-40
dB
No RLOAD, CLOAD = 50pF
Note:
1.
Guaranteed by design, not tested in production
2.
Guaranteed by characteristic, not tested in production.
3.
Resistive load between DACOUT and AVSS.
4.
Capacitive load at DACOUT pin.
M480 SERIES DATASHEET
May 08, 2020
Page 500 of 523
Rev 3.00
M480
9.5.7
Internal Voltage Reference
The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature (T A), and the
typical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
Symbol
VREF_INT
Parameter
Min
Typ
Max
1.55
1.6
1.65
1.95
2.0
2.05
Internal reference voltage
Ts[*1]
Unit Comments
AVDD >= 2.0 V
AVDD >= 2.2 V
V
2.45
2.5
2.55
AVDD >= 2.7 V
2.95
3.0
3.05
AVDD >= 3.2 V
-
0.5
0.8
ms
CL =4.7 uF, VREF initial=0
-
9.3
13
ms
CL =4.7 uF, VREF initial=3.6
-
24
180
us
CL =1 uF, VREF initial=0
-
2
2.6
ms
CL =1 uF, VREF initial=3.6
Stable time
Note:
1.
Guaranteed by characterization, not tested in production
VREF
1uF
M480 SERIES DATASHEET
Figure 9.5-2 Typical Connection with Internal Voltage Reference
May 08, 2020
Page 501 of 523
Rev 3.00
M480
9.6 Communications Characteristics
9.6.1
SPI Dynamic Characteristics
Specificaitons[*1]
Symbol
FSPICLK
1/ TSPICLK
Test Conditions
Parameter
Min
Typ
Max
-
-
96
SPI clock frequency
96
-
-
Unit
3.0 V ≤ VDD ≤ 3.6 V, CL = 30 pF
MHz
2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF
1.8 V ≤ VDD ≤ 3.6 V, CL = 30 pF
96
tCLKH
Clock output High time
TSPICLK / 2
ns
tCLKL
Clock output Low time
TSPICLK / 2
ns
tDS
Data input setup time
0
-
-
ns
tDH
Data input hold time
2
-
-
ns
-
-
2
ns
3.0 V ≤ VDD ≤ 3.6 V, CL = 30 pF
2
ns
2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF
2.2
ns
1.8 V ≤ VDD ≤ 3.6 V, CL = 30 pF
tV
Data output valid time
-
-
Note:
1. Guaranteed by design.
Table 9.6-1 SPI Master Mode Characteristics
M480 SERIES DATASHEET
tCLKH
tCLKL
CLKP=0
SPICLK
CLKP=1
tV
MOSI
Data Valid
Data Valid
tDS
MISO
Data Valid
CLKP=0, TX_NEG=1, RX_NEG=0
or
CLKP=1, TX_NEG=0, RX_NEG=1
tDH
Data Valid
tV
Data Valid
MOSI
tDS
MISO
Data Valid
CLKP=0, TX_NEG=0, RX_NEG=1
or
CLKP=1, TX_NEG=1, RX_NEG=0
tDH
Data Valid
Data Valid
Figure 9.6-1 SPI Master Mode Timing Diagram
May 08, 2020
Page 502 of 523
Rev 3.00
M480
Specificaitons[*1]
Symbol
FSPICLK
1/ TSPICLK
Test Conditions
Parameter
Min
Typ
Max
-
-
45
SPI clock frequency
45
-
-
Unit
3.0 V ≤ VDD ≤ 3.6 V, CL = 30 pF
MHz
1.8 V ≤ VDD ≤ 3.6 V, CL = 30 pF
33
tCLKH
Clock output High time
TSPICLK / 2
ns
tCLKL
Clock output Low time
TSPICLK / 2
ns
1
TSPICLK
+ 2ns
tSS
Slave select setup time
-
3.0 V ≤ VDD ≤ 3.6 V, CL = 30 pF
-
1
TSPICLK
+ 2ns
ns
1
TSPICLK
+ 3ns
-
-
Slave select hold time
1
TSPICLK
-
-
ns
tDS
Data input setup time
0
-
-
ns
tDH
Data input hold time
2
-
-
ns
-
-
11
Data output valid time
11
-
-
2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF
1.8 V ≤ VDD ≤ 3.6 V, CL = 30 pF
tSH
tV
2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF
3.0 V ≤ VDD ≤ 3.6 V, CL = 30 pF
ns
15
2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF
1.8 V ≤ VDD ≤ 3.6 V, CL = 30 pF
M480 SERIES DATASHEET
Note:
1. Guaranteed by design.
Table 9.6-2 SPI Slave Mode Characteristics
May 08, 2020
Page 503 of 523
Rev 3.00
M480
SSACTPOL=1
SPI SS
tSS
tSH
SSACTPOL=0
tCLKH
CLKPOL=0
TXNEG=1
RXNEG=0
tCLKL
SPI Clock
CLKPOL=1
TXNEG=0
RXNEG=1
tV
SPI data output
(SPI_MISO)
Data Valid
Data Valid
tDS
SPI data input
(SPI_MOSI)
Data Valid
SSACTPOL=1
SPI SS
tDH
Data Valid
tSS
tSH
SSACTPOL=0
CLKPOL=0
TXNEG=0
RXNEG=1
tCLKH
tCLKL
SPI Clock
CLKPOL=1
TXNEG=1
RXNEG=0
tV
M480 SERIES DATASHEET
SPI data output
(SPI_MISO)
Data Valid
tDS
SPI data input
(SPI_MOSI)
Data Valid
tDH
Data Valid
Data Valid
Figure 9.6-2 SPI Slave Mode Timing Diagram
May 08, 2020
Page 504 of 523
Rev 3.00
M480
SPI - I2S Dynamic Characteristics
9.6.2
Symbol
Parameter
Min [*1]
Max [*1]
2
Unit
Test Conditions
tw(CKH)
I S clock high time
80
-
tw(CKL)
I2S clock low time
80
-
tv(WS)
WS valid time
2
6
th(WS)
WS hold time
2
-
Master mode
tsu(WS)
WS setup time
24
-
Slave mode
th(WS)
WS hold time
0
-
Slave mode
I2S slave input clock duty
cycle
30
70
10
-
Master receiver
7
-
Slave receiver
7
-
Master receiver
4
-
Master fPCLK = 48 MHz, data: 24 bits, audio
frequency = 128 kHz
Master mode
ns
DuCy(SCK)
tsu(SD_MR)
Slave mode
Data input setup time
tsu(SD_SR)
th(SD_MR)
%
Data input hold time
th(SD_SR)
Slave receiver
ns
tv(SD_ST)
Data output valid time
-
25
Slave transmitter (after enable edge)
th(SD_ST)
Data output hold time
4
-
Slave transmitter (after enable edge)
tv(SD_MT)
Data output valid time
-
4
Master transmitter (after enable edge)
th(SD_MT)
Data output hold time
0
-
Master transmitter (after enable edge)
Note:
1. Guaranteed by design.
2
M480 SERIES DATASHEET
CK output
Table 9.6-3 I S Characteristics
CPOL = 0
tw(CKH)
CPOL = 1
tw(CKL)
tv(WS)
th(WS)
WS output
tv(SD_ST)
SDtransmit
LSB transmit(2)
MSB transmit
tsu(SD_MR)
SDreceive
LSB receive(2)
Bitn transmit
th(SD_ST)
LSB transmit
th(SD_MR)
MSB receive
Bitn receive
LSB receive
2
Figure 9.6-3 I S Master Mode Timing Diagram
May 08, 2020
Page 505 of 523
Rev 3.00
M480
CK Input
CPOL = 0
CPOL = 1
tw(CKH)
tw(CKL)
th(WS)
WS input
tv(SD_ST)
tsu(WS)
SDtransmit
LSB transmit(2)
MSB transmit
tsu(SD_SR)
SDreceive
LSB receive(2)
Bitn transmit
th(SD_ST)
LSB transmit
th(SD_SR)
MSB receive
Bitn receive
LSB receive
2
Figure 9.6-4 I S Slave Mode Timing Diagram
M480 SERIES DATASHEET
May 08, 2020
Page 506 of 523
Rev 3.00
M480
I2S Dynamic Characteristics
9.6.3
Symbol
Parameter
2
Min
Max
Unit
Test Conditions
tw(CKH)
I S clock high time
40
-
tw(CKL)
I2S clock low time
40
-
tv(WS)
WS valid time
4
16
th(WS)
WS hold time
1
-
Master mode
tsu(WS)
WS setup time
24
-
Slave mode
th(WS)
WS hold time
0
-
Slave mode
I2S slave input clock
duty cycle
30
70
10
-
Master receiver
7
-
Slave receiver
7
-
Master receiver
4
-
Master fPCLK = MHz, data: 24 bits, audio
frequency = 256 kHz
Master mode
ns
DuCy(SCK)
tsu(SD_MR)
Slave mode
Data input setup time
tsu(SD_SR)
th(SD_MR)
%
Data input hold time
th(SD_SR)
Slave receiver
ns
tv(SD_ST)
Data output valid time
-
10
Slave transmitter (after enable edge)
th(SD_ST)
Data output hold time
4
-
Slave transmitter (after enable edge)
tv(SD_MT)
Data output valid time
-
4
Master transmitter (after enable edge)
th(SD_MT)
Data output hold time
0
-
Master transmitter (after enable edge)
Note:
1.
Guaranteed by design.
2
CPOL = 0
tw(CKH)
CPOL = 1
tw(CKL)
tv(WS)
th(WS)
WS output
tv(SD_ST)
SDtransmit
LSB transmit(2)
MSB transmit
tsu(SD_MR)
SDreceive
LSB receive(2)
Bitn transmit
th(SD_ST)
LSB transmit
th(SD_MR)
MSB receive
Bitn receive
LSB receive
2
Figure 9.6-5 I S Master Mode Timing Diagram
May 08, 2020
Page 507 of 523
Rev 3.00
M480 SERIES DATASHEET
CK output
Table 9.6-4 I S Characteristics
M480
CK Input
CPOL = 0
CPOL = 1
tw(CKH)
tw(CKL)
th(WS)
WS input
tv(SD_ST)
tsu(WS)
SDtransmit
LSB transmit(2)
MSB transmit
tsu(SD_SR)
SDreceive
LSB receive(2)
Bitn transmit
th(SD_ST)
LSB transmit
th(SD_SR)
MSB receive
Bitn receive
LSB receive
2
Figure 9.6-6 I S Slave Mode Timing Diagram
M480 SERIES DATASHEET
May 08, 2020
Page 508 of 523
Rev 3.00
M480
9.6.4
I2C Dynamic Characteristics
Symbol
Parameter
Standard Mode[1][2]
Fast Mode[1][2]
Min
Max
Min
Max
Unit
tLOW
SCL low period
4.7
-
1.3
-
µs
tHIGH
SCL high period
4
-
0.6
-
µs
4.7
-
0.6
-
µs
tSU; STA
Repeated START condition setup time
tHD; STA
START condition hold time
4
-
0.6
-
µs
tSU; STO
STOP condition setup time
4
-
0.6
-
µs
Bus free time
4.7[3]
-
1.2[3]
-
µs
tSU;DAT
Data setup time
250
-
100
-
ns
tHD;DAT
Data hold time
0[4]
3.45[5]
0[4]
0.8[5]
µs
tBUF
tr
SCL/SDA rise time
-
1000
20+0.1Cb
300
ns
tf
SCL/SDA fall time
-
300
-
300
ns
Cb
Capacitive load for each bus line
-
400
-
400
pF
Note:
1. Guaranteed by characteristic, not tested in production
2. HCLK must be higher than 2 MHz to achieve the maximum standard mode I 2C frequency. It must be higher than 8
MHz to achieve the maximum fast mode I2C frequency.
3. I2C controller must be retriggered immediately at slave mode after receiving STOP condition.
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL.
2
Table 9.6-5 I C Characteristics
STOP
Repeated
START
START
STOP
SDA
tBUF
tLOW
tr
SCL
tHD;STA
tf
tHIGH
tHD;DAT
tSU;DAT
tSU;STA
tSU;STO
2
Figure 9.6-7 I C Timing Diagram
May 08, 2020
Page 509 of 523
Rev 3.00
M480 SERIES DATASHEET
5. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of
SCL signal.
M480
9.6.5
USB Characteristics
9.6.5.1
USB Full-Speed Characteristics
Symbol
Parameter
Min.
Typ.
Max.
Unit
3.6
V
Test Conditions
VDD
Operation Voltage
3.0
VIH
Input High (driven)
2.0
-
-
V
-
VIL
Input Low
-
-
0.8
V
-
VDI
Differential Input Sensitivity
-
0.2
-
V
|PADP-PADM|
0.8
-
2.5
V
-
0.8
-
2.0
V
-
Receiver Hysteresis
-
200
-
mV
Single End RX
VOL
Output Low (driven)
0
-
0.3
V
-
VOH
Output High (driven)
2.8
-
3.6
V
-
VCRS
Output Signal Cross Voltage
1.3
-
2.0
V
-
RPU
Pull-up Resistor
0.9
1.2
1.575
kΩ
DATARPU2=1
RPU
Pull-up Resistor
1.425
2.3
3.09
kΩ
DATARPU2=0
RPD
Pull-down Resistor
14.25
19.5
24.8
kΩ
-
VTRM
TERMINATION
Voltage
Uptream port pull up (RPU)
3.0
-
3.6
V
-
ZDRV
Driver Output Resistance
-
10
-
Ω
-
CIN
Transceiver Capacitance
-
-
26
pF
-
Differential
VCM
Common-mode Range
Single-ended
Threshold
VSE
Receiver
for
M480 SERIES DATASHEET
Table 9.6-6 USB Full-Speed Characteristics
9.6.5.2
USB Full-Speed PHY characteristics
Symbol
Parameter
Min [*1]
Typ
Max [*1]
Unit
Test Conditions
TFR
rise time
4
-
20
ns
-
TFF
fall time
4
-
20
ns
-
rise and fall time matching
90
-
111.11
%
TFRFF = TFR/TFF
TFRFF
Note:
1. Guaranteed by characterization result, not tested in production.
Table 9.6-7 USB Full-Speed PHY Characteristics
May 08, 2020
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M480
9.6.6
SDIO Characteristics
9.6.6.1
SDIO Default Mode Timing
Symbol
Parameter
SD_CLK Period
TP_SD_CLK
(Data Transfer Mode)
SD_CLK Period
TP_SD_CLK_ID
(Identification Mode)
Min
Typ
Max
Unit
Test Condition
40
-
-
ns
-
2,500
-
-
ns
TH_SD_CLK
SD_CLK High Time
-
20
-
ns
-
TL_SD_CLK
SD_CLK Low Time
-
20
-
ns
-
5
-
-
ns
-
5
-
-
ns
-
-
-
14
ns
-
SD_DATA Setup Time to
TSU_SD_IN
SD_CLK Rising
SD_DATA Hold Time from
SD_CLK Rising
THD_SD_IN
SD_CLK Falling to
TDLY_SD_OUT
Valid SD_DATA Delay
Note:
1.
Guaranteed by characterization result, not tested in production.
Table 9.6-8 SDIO Default Mode Timing
TP_SD_CLK
TL_SD_CLK
TH_SD_CLK
SDx_CLK
M480 SERIES DATASHEET
SDx_CMD
SDx_DATA[3:0]
(Input Mode)
TSU_SD_IN
THD_SD_IN
SDx_CMD
SDx_DATA[3:0]
(Output Mode)
TDLY_SD_OUT
Figure 9.6-8 SDIO Default Mode
9.6.6.2
SDIO Dynamic characteristics
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
TP_SD_CLK
SD_CLK Period
20
-
-
ns
-
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M480
TH_SD_CLK
SD_CLK High Time
7
-
-
ns
-
TL_SD_CLK
SD_CLK Low Time
7
-
-
ns
-
6
-
-
ns
-
2
-
-
ns
-
-
-
14
ns
-
2.5
-
-
ns
-
SD_DATA Setup Time to
TSU_SD_IN
SD_CLK Rising
SD_DATA Hold Time from
SD_CLK Rising
THD_SD_IN
SD_CLK Falling to
TDLY_SD_OUT
Valid SD_DATA Delay
SD_DATA Hold Time from
SD_CLK Rising
THD_SD_OUT
Note:
1.
Guaranteed by characterization result, not tested in production.
Table 9.6-9 SDIO Dynamic Characteristics
TP_SD_CLK
TL_SD_CLK
TH_SD_CLK
SDx_CLK
SDx_CMD
SDx_DATA[3:0]
(Input Mode)
TSU_SD_IN
M480 SERIES DATASHEET
THD_SD_IN
SDx_CMD
SDx_DATA[3:0]
(Output Mode)
TDLY_SD_OUT
THD_SD_OUT
Figure 9.6-9 SDIO High-speed Mode
May 08, 2020
Page 512 of 523
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M480
9.6.7
Camera Capture Interface (CCAP) Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
20
-
-
ns
TP_CCAP_PCLK
CCAP_PCLK Period
TH_CCAP_PCLK
CCAP_PCLK High Time
-
10.0
-
ns
TL_CCAP_PCLK
CCAP_PCLK Low Time
-
10.0
-
ns
TSU_CCAP_IN
CCAP_HSYNC, CCAP_VSYNC,
CCAP_FIELD and CCAP_DATA
Setup Time to CCAP_PCLK Rising
4
-
-
ns
THD_CCAP_IN
CCAP_HSYNC, CCAP_VSYNC,
CCAP_FIELD and CCAP_DATA
Hold Time from CCAP_PCLK
Rising
1
-
-
ns
Test Condition
Note:
1.
Guaranteed by design.
Table 9.6-10 Camera Capture Interface Timing
TP_CCAP_PCLK
TL_CCAP_PCLK
TH_CCAP_PCLK
CCAP_PCLK
CCAP_HSYNC
CCAP_VSYNC
CCAP_FIELD
CCAP_DATA
TSU_CCAP_IN
THD_CCAP_IN
M480 SERIES DATASHEET
Figure 9.6-10 Camera Capture Interface Timing Diagram
May 08, 2020
Page 513 of 523
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M480
9.7 Flash DC Electrical Characteristics
The devices are shipped to customers with the Flash memory erased.
Symbol
Parameter
Min
Typ
Max
Unit
1.08
-
1.32
V
Test Condition
VFLA[1]
Supply voltage
TERASE
Page erase time
-
-
160
ms
TPROG
Program time
-
-
16
µs
IDD1
Read current
-
4.12
-
mA
IDD2
Program current
-
5
-
mA
IDD3
Erase current
-
5
-
mA
10,000
-
TBD
-
-
year
10 kcycle[3] TA = 55°C
10
-
-
year
10 kcycle[3] TA = 85°C
TBD
-
-
year
10 kcycle[3] TA = 125°C
NENDUR
TRET
Endurance
Data retention
cycles[2]
TA = 25°C
TJ = -40℃~125°C
Note:
1.
VFLA is source from chip internal LDO output voltage.
2.
Number of program/erase cycles.
3.
Guaranteed by design.
M480 SERIES DATASHEET
May 08, 2020
Page 514 of 523
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M480
10 ABBREVIATIONS
10.1 Abbreviations
Description
ACMP
Analog Comparator Controller
ADC
Analog-to-Digital Converter
AES
Advanced Encryption Standard
APB
Advanced Peripheral Bus
AHB
Advanced High-Performance Bus
BOD
Brown-out Detection
CAN
Controller Area Network
CCAP
Camera Capture Interface
DAP
Debug Access Port
DES
Data Encryption Standard
EADC
Enhanced Analog-to-Digital Converter
EBI
External Bus Interface
EMAC
Ethernet MAC Controller
EPWM
Enhanced Pulse Width Modulation
FIFO
First In, First Out
FMC
Flash Memory Controller
FPU
Floating-point Unit
GPIO
General-Purpose Input/Output
HCLK
The Clock of Advanced High-Performance Bus
HIRC
12 MHz Internal High Speed RC Oscillator
HXT
4~24 MHz External High Speed Crystal Oscillator
IAP
In Application Programming
ICP
In Circuit Programming
ISP
In System Programming
LDO
Low Dropout Regulator
LIN
Local Interconnect Network
LIRC
10 kHz internal low speed RC oscillator (LIRC)
MPU
Memory Protection Unit
NVIC
Nested Vectored Interrupt Controller
PCLK
The Clock of Advanced Peripheral Bus
PDMA
Peripheral Direct Memory Access
PLL
Phase-Locked Loop
May 08, 2020
Page 515 of 523
M480 SERIES DATASHEET
Acronym
Rev 3.00
M480
PWM
Pulse Width Modulation
QEI
Quadrature Encoder Interface
SD
Secure Digital
SPI
Serial Peripheral Interface
SPS
Samples per Second
TDES
Triple Data Encryption Standard
TK
Touch Key
TMR
Timer Controller
UART
Universal Asynchronous Receiver/Transmitter
UCID
Unique Customer ID
USB
Universal Serial Bus
WDT
Watchdog Timer
WWDT
Window Watchdog Timer
Table 10.1-1 List of Abbreviations
M480 SERIES DATASHEET
May 08, 2020
Page 516 of 523
Rev 3.00
M480
11 PACKAGE DIMENSIONS
11.1 QFN 33L (5x5x0.8 mm3 Pitch 0.5 mm)
M480 SERIES DATASHEET
May 08, 2020
Page 517 of 523
Rev 3.00
M480
11.2 LQFP 48L (7x7x1.4 mm3 Footprint 2.0mm)
H
36
25
37
24
48
13
H
12
1
Controlling dimension : Millimeters
M480 SERIES DATASHEET
Symbol
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
Y
0
May 08, 2020
Dimension in inch
Dimension in mm
Min Nom Max
Min Nom Max
0.002 0.004
0.006
0.05
0.053 0.055
0.057
1.35
1.40
1.45
0.006 0.008
0.010
0.15
0.20
0.25
0.004 0.006
0.008
0.10
0.15
0.20
0.272 0.276
0.280
6.90
7.00
7.10
0.272 0.276
0.280
6.90
7.00
7.10
0.020
0.026
0.35
0.50
0.65
0.014
0.10
0.15
0.350
0.354
0.358
8.90
9.00
9.10
0.350
0.354
0.358
8.90
9.00
9.10
0.018
0.024
0.030
0.45
0.60
0.75
1.00
0.039
0.004
0
7
Page 518 of 523
0.10
0
7
Rev 3.00
M480
11.3 LQFP 64L (7x7x1.4 mm3 footprint 2.0 mm)
M480 SERIES DATASHEET
May 08, 2020
Page 519 of 523
Rev 3.00
M480
11.4 LQFP 128L (14x14x1.4 mm3 footprint 2.0 mm)
M480 SERIES DATASHEET
May 08, 2020
Page 520 of 523
Rev 3.00
M480
11.5 LQFP 144L (20x20x1.4 mm3 footprint 2.0 mm)
M480 SERIES DATASHEET
May 08, 2020
Page 521 of 523
Rev 3.00
M480
12 REVISION HISTORY
Date
Revision
Description
2018.03.30
1.00
1.
Preliminary version.
1.
Added the note “the SRAM bank2 has additional two wait cycles when reading
data” in section 6.2.7.
2.
Added the note that HXT should be 12 MHz for USB High-speed application in
Figure 6.3-1.
1.
Added new M480 256 KB Flash product lines.
2.
Added features comparison tables in FMC, BPWM, SDH, Crypto and EADC
peripherals.
3.
Added section 6.44 Peripherals Interconnection which allow autonomous
communication or synchronous action between peripherals.
1.
Removed M48xGAAE parts information in Selection Guide.
1.
Added new M480 128 KB Flash product lines:
2018.07.16
2019.06.20
2019.08.20
2019.10.20
1.01
2.00
2.01
– M481 product line: M481ZE8AE, M481LE8AE and M481SE8AE
2.02
– M482 product line: M482ZE8AE, M482LE8AE and M482SE8AE
– M483 product line: M483SE8AE
2020.05.08
1.
Added new part M487KMCAN
2.
Added notes about the hardware reference design for ICE_DAT, ICE_CLK and
nRESET pins in section 4.2, 4.3 and chapter 7.
3.
Fix SPIx clock PCLK define in Figure 6.3-1.
4.
Add CCAP_SCLK and remove HSOTG clock in Figure 6.3-2.
3.00
M480 SERIES DATASHEET
May 08, 2020
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M480
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
May 08, 2020
Page 523 of 523
Rev 3.00
M480 SERIES DATASHEET
Important Notice
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