NUC505DS13Y

NUC505 ARM® Cortex® -M4 32-bit Microcontroller NuMicro® Family NUC505 Series Datasheet Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based system design. Nuvoton assumes no responsibility for errors or omissions. All data and specifications are subject to change without notice. For additional information or questions, please contact: Nuvoton Technology Corporation. www.nuvoton.com Aug. 15, 2017 Page 1 of 130 Rev.1.07 NUC505 SERIES DATASHEET The information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. NUC505 TABLE OF CONTENTS 1 GENERAL DESCRIPTION .............................................................. 8 2 FEATURES ................................................................................ 9 2.1 3 ABBREVIATIONS ....................................................................... 14 3.1 4 4.2 4.3 Selection Guide ............................................................................15 4.1.1 NuMicro NUC505 Base Series Selection Guide ...................................... 15 4.1.2 NuMicro NUC505 Base Series Naming Rule .......................................... 16 ® ® Pin Configuration ..........................................................................17 4.2.1 NuMicro NUC505DLA LQFP 48-pin .................................................... 17 4.2.2 NuMicro NUC505DL13Y LQFP 48-pin ................................................. 18 4.2.3 NuMicro NUC505YLA QFN 48-pin ...................................................... 19 4.2.4 NuMicro NUC505YLA2Y QFN 48-pin .................................................. 20 4.2.5 NuMicro NUC505DSA LQFP 64-pin .................................................... 21 4.2.6 NuMicro NUC505DS13Y LQFP 64-pn.................................................. 22 4.2.7 NuMicro NUC505YO13Y QFN 88-pin .................................................. 23 ® ® ® ® ® ® ® Pin Description .............................................................................24 NUC505 SERIES DATASHEET 4.3.1 NuMicro NUC505DLA LQFP 48-pin Description ...................................... 24 4.3.2 NuMicro NUC505DL13Y LQFP 48-pin Description................................... 28 4.3.3 NuMicro NUC505YLA QFN 48-pin Description ....................................... 33 4.3.4 NuMicro NUC505YLA2Y QFN 48-pin Description .................................... 37 4.3.5 NuMicro NUC505DSA LQFP 64-pin Description ..................................... 42 4.3.6 NuMicro NUC505DS13Y LQFP 64-pin Description .................................. 48 4.3.7 NuMicro NUC505YO13Y QFN 88-pin Description ................................... 54 4.3.8 Summary GPIO Multi-function Pin Description ......................................... 62 4.3.9 GPIO Multi-function Pin Summary........................................................ 64 ® ® ® ® ® ® ® BLOCK DIAGRAM ...................................................................... 68 5.1 6 Abbreviations...............................................................................14 PARTS INFORMATION LIST AND PIN CONFIGURATION ..................... 15 4.1 5 NUC505 Features .......................................................................... 9 NuMicro® NUC505 Series Block Diagram .............................................68 FUNCTIONAL DESCRIPTION ........................................................ 69 6.1 ARM® Cortex® -M4 Core ..................................................................69 6.2 System Manager ..........................................................................72 Aug. 15, 2017 Page 2 of 130 Rev.1.07 NUC505 6.3 6.4 6.5 6.7 6.8 6.9 Overview ...................................................................................... 72 6.2.2 System Reset ................................................................................ 72 6.2.3 System Power-on Setting .................................................................. 73 6.2.4 System Power Distribution ................................................................. 73 6.2.5 System Memory Mapping .................................................................. 74 6.2.6 SRAM Memory Organization .............................................................. 76 6.2.7 AHB Bus Arbitration ......................................................................... 78 6.2.8 System Timer (Systick) ..................................................................... 80 6.2.9 Nested Vectored Interrupt Control (NVIC) ............................................... 81 Clock Controller............................................................................84 6.3.1 Overview ...................................................................................... 84 6.3.2 Clock Diagram ............................................................................... 85 6.3.3 Clock Generator ............................................................................. 86 6.3.4 Power-down Mode Clock .................................................................. 87 General Purpose I/O (GPIO) ............................................................88 6.4.1 Overview ...................................................................................... 88 6.4.2 Features ...................................................................................... 88 Timer Controller (TIMER) ................................................................90 6.5.1 Overview ...................................................................................... 90 6.5.2 Features ...................................................................................... 90 PWM Generator and Capture Timer (PWM) ..........................................91 6.6.1 Overview ...................................................................................... 91 6.6.2 Features ...................................................................................... 91 Watchdog Timer (WDT) ..................................................................92 6.7.1 Overview ...................................................................................... 92 6.7.2 Features ...................................................................................... 92 Window Watchdog Timer (WWDT) .....................................................92 6.8.1 Overview ...................................................................................... 92 6.8.2 Features ...................................................................................... 92 Real Time Clock (RTC) ...................................................................93 6.9.1 Overview ...................................................................................... 93 6.9.2 Features ...................................................................................... 93 6.10 UART Interface Controller (UART) .....................................................94 6.10.1 Overview ...................................................................................... 94 Aug. 15, 2017 Page 3 of 130 Rev.1.07 NUC505 SERIES DATASHEET 6.6 6.2.1 NUC505 6.10.2 Features ...................................................................................... 94 6.11 I2C Serial Interface Controller (Master/Slave) ........................................95 6.11.1 Overview ...................................................................................... 95 6.11.2 Features ...................................................................................... 96 6.12 Serial Peripheral Interface (SPI) ........................................................97 6.12.1 Overview ...................................................................................... 97 6.12.2 Features ...................................................................................... 97 6.13 SPI Memory Interface Controller (SPIM) ..............................................98 6.13.1 Overview ...................................................................................... 98 6.13.2 Features ...................................................................................... 98 6.14 I2S Controller with Internal Audio CODEC (I2S) ......................................99 6.14.1 Overview ...................................................................................... 99 6.14.2 Features ...................................................................................... 99 6.15 USB 2.0 Device Controller (USBD)................................................... 100 6.15.1 Overview .................................................................................... 100 6.15.2 Features .................................................................................... 100 6.16 USB 1.1 Host Controller (USBH) ..................................................... 101 6.16.1 Overview .................................................................................... 101 6.16.2 Features .................................................................................... 101 6.17 Secure-Digital Host Controller (SDHC) .............................................. 102 NUC505 SERIES DATASHEET 6.17.1 Overview .................................................................................... 102 6.17.2 Features .................................................................................... 102 6.18 12-bit Analog-to-Digital Converter (ADC) ............................................ 103 6.18.1 Overview .................................................................................... 103 6.18.2 Features .................................................................................... 103 7 ELECTRICAL CHARACTERISTICS ................................................104 7.1 Absolute Maximum Ratings............................................................ 104 7.2 DC Characteristics ...................................................................... 105 7.3 AC Electrical Characteristics .......................................................... 108 7.4 7.3.1 External 12 MHz Crystal ................................................................. 108 7.3.2 External 12 MHz High Speed Oscillator ............................................... 108 7.3.3 Typical Crystal Application Circuits ..................................................... 108 7.3.4 Internal 32 kHz Low Speed Oscillator .................................................. 109 Analog Characteristics.................................................................. 110 Aug. 15, 2017 Page 4 of 130 Rev.1.07 NUC505 7.4.1 Specifications of 12-bit SARADC ....................................................... 110 7.4.2 Specifications of 24-bit Delta-Sigma CODEC......................................... 112 7.4.3 Specification of LDO ...................................................................... 113 7.4.4 Specification of Low Voltage Reset .................................................... 114 7.4.5 Specifications of Power-on Reset ...................................................... 114 7.4.6 USB PHY Specifications ................................................................. 116 7.4.7 I C Dynamic Characteristics ............................................................. 118 7.4.8 SPI Dynamic Characteristics ............................................................ 119 7.4.9 I S Dynamic Characteristics ............................................................. 121 2 2 8 APPLICATION CIRCUIT ..............................................................123 9 PACKAGE DIMENSIONS ............................................................124 10 9.1 LQFP 48L (7x7x1.4mm footprint 2.0mm) ............................................ 124 9.2 QFN 48 (7x7x0.8mm) ................................................................... 125 9.3 LQFP 64L (7x7x1.4mm footprint 2.0mm) ............................................ 126 9.4 QFN 88 (10x10x0.9mm)................................................................ 127 REVISION HISTORY ..................................................................129 NUC505 SERIES DATASHEET Aug. 15, 2017 Page 5 of 130 Rev.1.07 NUC505 List of Figures ® Figure 4.1-1 NuMicro NUC505 Base Series Selection Code ....................................................... 16 ® Figure 4.2-1 NuMicro NUC505DLA LQFP 48-pin Diagram.......................................................... 17 ® Figure 4.2-2 NuMicro NUC505DL13Y LQFP 48-pin Diagram...................................................... 18 ® Figure 4.2-3 NuMicro NUC505YLA QFN 48-pin Diagram............................................................ 19 ® Figure 4.2-4 NuMicro NUC505YLA2Y QFN 48-pin Diagram ....................................................... 20 ® Figure 4.2-5 NuMicro NUC505DSA LQFP 64-pin Diagram ......................................................... 21 ® Figure 4.2-6 NuMicro NUC505DS13Y LQFP 64-pin Diagram ..................................................... 22 ® Figure 4.2-7 NuMicro NUC505YO13Y QFN 88-pin Diagram ....................................................... 23 ® Figure 5.1-1 NuMicro NUC505 Block Diagram ............................................................................ 68 ® Figure 6.1-1 Cortex -M4 Block Diagram ........................................................................................ 69 ® Figure 6.2-1 NuMicro NUC505 Power Distribution Diagram ........................................................ 74 Figure 6.2-2 SRAM Block Diagram ................................................................................................ 76 Figure 6.2-3 SRAM Memory Organization ..................................................................................... 77 Figure 6.2-4 Vector Map Module Block .......................................................................................... 78 Figure 6.3-1 Clock Generator Global View Diagram ...................................................................... 85 Figure 6.3-2 Clock Generator Block Diagram ................................................................................ 86 Figure 6.3-3 Crystal Oscillator Circuit ............................................................................................ 87 Figure 6.4-1 I/O Pin Block Diagram ............................................................................................... 88 2 Figure 6.11-1 I C Bus Timing ......................................................................................................... 95 Figure 7.3-1 Typical Crystal Application Circuit ........................................................................... 109 NUC505 SERIES DATASHEET Figure 7.4-1 Power-up Ramp Condition ...................................................................................... 115 2 Figure 7.4-2 I C Timing Diagram ................................................................................................. 118 Figure 7.4-3 SPI Master Mode Timing Diagram .......................................................................... 119 Figure 7.4-4 SPI Slave Mode Timing Diagram ............................................................................ 120 Figure 7.4-5 I2S Master Mode Timing Diagram ........................................................................... 122 2 Figure 7.4-6 I S Slave Mode Timing Diagram.............................................................................. 122 Aug. 15, 2017 Page 6 of 130 Rev.1.07 NUC505 List of Tables Table 3.1-1 List of Abbreviations .................................................................................................... 14 ® Table 4.1-1 NuMicro NUC505 Base Series Selection Guide ....................................................... 15 Table 4.3-1 NUC505 GPIO Multi-function Table ............................................................................ 67 Table 6.2-1 System Power-on Setting Guide ................................................................................. 73 Table 6.2-2 Address Space Assignments for On-Chip Controllers ................................................ 75 Table 6.2-3 AHB Bus Priority Order in Fixed Priority Mode ........................................................... 79 Table 6.2-4 Exception Model ....................................................................................................... 82 Table 6.2-5 Interrupt Number Table ............................................................................................... 83 Table 6.3-1 Recommended Load Capacitance Values and Resistance Values. .......................... 87 NUC505 SERIES DATASHEET Aug. 15, 2017 Page 7 of 130 Rev.1.07 NUC505 1 GENERAL DESCRIPTION ® ® ® The NuMicro NUC505 series 32-bit microcontrollers are embedded with ARM Cortex -M4F core for consumer and industrial applications which need high computing power and rich communication interfaces. ® ® ® The ARM Cortex -M4F core within NuMicro NUC505 series can run up to 100 MHz and support ® DSP extensions and Floating Point Unit (FPU) function. The NuMicro NUC505 series supports 128 Kbytes embedded SRAM with zero-wait state and 512 KB/ 2 Mbytes embedded SPI Flash memory, and is equipped with plenty of high performance peripheral devices, such as 24-bit Audio CODEC, USB2.0 High-speed Device, USB2.0 Full-speed Host, and other peripheral. ® The NuMicro NUC505 series is suitable for a wide range of applications such as:  Audio and Wireless Audio Applications  Thermal printerDid not find any incorrect format  GPS Tracker / VTDR (Vehicle Travelling Data Recorder)  Others high performance or data intensive computing applications Key Features:  Core ® ® ─ ARM Cortex -M4F core running up to 100 MHz (with DSP and FPU)  Memory ─ 128 KB of SRAM with zero-wait state ─ 512 KB/ 2 MB of SPI Flash  Security for code protection ─ 128-bit key for code protection against pirating ─ Up to 15 times programming the key NUC505 SERIES DATASHEET  Clock Control ─ 12 MHz crystal oscillator input ─ Up to two PLLs for system clock and Audio  Up to 12 Communication interfaces ─ USB 2.0 HS Device interface ─ Up to two USB 2.0 FS Host interfaces ─ Up to three UARTs ─ Up to three SPIs ─ Up to two I²C interfaces (up to 1 MHz) ─ SD Host  GPIO ─ Supports up to 25/35/52 GPIOs for QFN88/LQFP64/LQFP48 respectively  Timer ─ Supports four sets of 32-bit timers ─ Supports two watchdog timers (Independent and Window)  Audio CODEC ─ Embedded Stereo 24-bit Sigma-Delta CODEC ─ MIC/LINE-In-THDN: -80 dB, Dynamic Range SNR: 90 dB (A-Weighted) ─ Headphone Output-THDN:-60dB, Dynamic Range SNR: 93 dB (AWeighted) ─ Sample Rate: 8 kHz to 96 kHz  12-bit ADC ─ Analog input voltage range: 0~ AVDD ─ Supports single 12-bit SAR ADC conversion ─ Up to 8 channels ─ Up to 1 MSPS conversion with ADC_CH1, and up to 200 kSPS with other channels (except ADC_CH0).  Built-in LDO with operating voltage 3.3V  Low Voltage Detector (LVD) ─ With 2 levels: 2.8V / 2.6V  Low Voltage Reset (LVR) ─ Threshold voltage level: 2.4 V  RTC ─ Supports external power pin VBAT ─ 32 bytes spare registers ─ Internal 32.768 kHz RC with calibration Aug. 15, 2017 2 I S ─ Supports Master or Slave mode operation ─ Supports PCM mode A, PCM mode B, 2 I S and MSB justified data format ─ Supports DMA mode  Packages ─ LQFP48, LQFP64, QFN88 ─ Temperature range: -40℃~+85℃ Page 8 of 130 Rev.1.07 NUC505 2 2.1 FEATURES NUC505 Features Core ® ® ─ ARM Cortex -M4F core running up to 100 MHz ─ Supports DSP extension with hardware divider ─ Supports IEEE 754 compliant Floating Point Unit (FPU) ─ Supports Memory Protection Unit (MPU) ─ One 24-bit system timer ─ Supports Power-down mode by WFI and WFE instructions ─ Single-cycle 32-bit hardware multiplier ─ Supports programmable 16 level priorities of Nested Vectored Interrupt Controller (NVIC) ─ Supports programmable mask-able interrupts ─ Boots from SPI Flash Memory or USB Device SRAM Memory ─ 128 KB embedded SRAM with zero-wait state ─ Supports byte-, half-word- and word-access SPI Memory Interface Controller Supports external SPI Flash memory ─ Supports code protection ─ Supports DMA mode for code transfer from SPI Flash memory to SRAM ─ Supports CPU direct read from SPI Flash memory. ─ Supports standard (1-bit), dual (2-bit), and quad (4-bit) I/O transfer mode ─ Supports general SPI master interface protocol NUC505 SERIES DATASHEET ─ Embedded SPI Flash ─ 512 KB/ 2 MB SPI Flash ─ Configurable program code/data allocation ─ Supports 2-wired ICP update through SWD/ICE interface ─ Supports ISP update ─ Supports standard (1-bit), dual (2-bit), and quad (4-bit) I/O transfer mode ─ Supports 100 MHz clock for standard I/O transfer mode ─ Supports 80 MHz clock for dual and quad I/O transfer mode Security for code protection ─ 128-bit key for code protection against pirating ─ Up to 15 times programming of the key Clock Control ─ Aug. 15, 2017 Built-in 32.768 kHz internal low speed RC oscillator (LIRC) for RTC function, Page 9 of 130 Rev.1.07 NUC505 Watchdog timer and wake-up operation ─ Supports 32.768 kHz external low speed crystal oscillator (LXT) for RTC function and low-power system operation ─ Supports 12 MHz external high speed crystal oscillator (HXT) for precise timing operation ─ Supports one PLL up to 240 MHz for high performance system operation. The external high speed crystal oscillator (HXT) is used as the clock source for the PLL. ─ Supports Master or Slave mode operation ─ Internal PLL for frequency adjustment ─ Capable of handling 8-, 16-, 24- and 32-bit word sizes ─ Supports Mono and Stereo audio data ─ Supports PCM mode A, PCM mode B, I S and MSB justified data format ─ Each provides two 16-word FIFO data buffers, one for transmitting and the other for receiving ─ Generates interrupt requests when buffer levels cross a programmable boundary ─ Supports DMA mode ─ Interface with internal or external audio CODEC 2 I S 2 Audio CODEC NUC505 SERIES DATASHEET ─ Embedded Stereo 24-bit Sigma-Delta CODEC output ─ ADC-THDN: -80 dB, Dynamic Range SNR: 90 dB (A-Weighted) ─ Headphone Output-THDN:-60dB, Dynamic Range SNR: 93 dB (A-Weighted) ─ Sample Rate: 8 kHz to 96 kHz USB 2.0 High-speed device ─ 12 programmable endpoints for Control, Bulk IN/OUT, Interrupt and Isochronous transfers ─ 2K-byte buffer ─ Auto suspend function ─ Remote wake-up capability USB 2.0 Full-speed host ─ Fully compliant with USB revision 1.1 specification ─ Open Host Controller Interface (OHCI) revision 1.0 compatible ─ Full-speed (12Mbps) and Low-speed (1.5Mbps) device supported ─ Control, Bulk, Interrupt and Isochronous transfers supported SD Host Interface ─ Supports SD (Secure Digital) card and SD_HOST interface ─ Compliant with SD Memory Card Specification Version 2.0 Aug. 15, 2017 Page 10 of 130 Rev.1.07 NUC505 ─ Supports 1 and 4-bit modes ─ Supports 50 MHz to achieve 200 Mbps at 3.3V operation ─ Supports DMA master Timer ─ Supports 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit prescale counter ─ Independent clock source for each timer ─ Provides One-shot, periodic, toggle and continuous counting operation modes ─ Supports event counting function to count the event from external pin ─ Supports input capture function to capture or reset counter value Watchdog Timer ─ Supports multiple clock sources from LIRC (default selection), HXT and LXT ─ 8 selectable time-out period from 1.6ms ~ 26.0sec (depending on clock source) ─ Interrupt or reset selectable on watchdog time-out Window Watchdog Timer ─ Supports multiple clock sources from LIRC (default selection), HXT and LXT ─ Window set by 6-bit counter with 11-bit prescale ─ Interrupt or reset selectable on time-out GPIO Four I/O modes ─ CMOS/Schmitt trigger input selectable ─ I/O pin configured as interrupt source with edge trigger setting ─ Supports 5V-tolerance function (except PA.7~PA.0 and PD.4~PD.2 only support 3.3 V) ─ Supports up to 52/35(34)/25(18) GPIOs for QFN88/LQFP64/LQFP48 respectively UART ─ Supports up to three UARTs – UART0, UART1 and UART2 ─ Supports 16-byte FIFOs with programmable level trigger with UART0 ─ Supports 64-byte FIFOs with programmable level trigger with UART1 and UART2 ─ Supports auto flow control (nCTS and nRTS) with UART1 and UART2 ─ Supports IrDA (SIR) function ─ Supports RS-485 9-bit mode and direction control ─ UART1 and UART2 support LIN function ─ Programmable baud-rate generator up to 1/16 system clock ─ Supports nCTS and data wake-up function SPI ─ Supports two sets of SPI controller – SPI0 and SPI1 ─ Supports Master or Slave mode operation Aug. 15, 2017 Page 11 of 130 Rev.1.07 NUC505 SERIES DATASHEET ─ NUC505 ─ Supports 1-bit Transfer mode ─ Configurable bit length of a transfer word from 8 to 32-bit ─ Provides separate 8-level depth transmit and receive FIFO buffers ─ Supports MSB first or LSB first transfer sequence ─ Supports the byte reorder function ─ Supports Byte or Word Suspend mode ─ Supports 3-wired, no slave select signal, bi-direction interface ─ Supports up to 50 MHz ─ Supports up to two sets of I C devices ─ Supports Master/Slave mode ─ Bidirectional data transfer between masters and slaves ─ Multi-master bus (no central master) ─ Arbitration between simultaneously transmitting masters without corruption of serial data on the bus ─ Serial clock synchronization allows devices with different bit rates to communicate via one serial bus ─ Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer ─ Programmable clocks allow versatile rate control ─ Supports multiple address recognition (four slave address with mask option) ─ Supports SMBus and PMBus ─ Supports speed up to 1Mbps ─ Supports multi-address Power-down wake-up function 2 I C 2 NUC505 SERIES DATASHEET PWM ─ Four 16-bit timers ─ Programmable duty control of output waveform (PWM) ─ Auto reload mode or one-shot pulse mode ─ Capture and compare function RTC ─ Supports external power pin RTC_VDD33 ─ Supports 32.768 kHz crystal oscillation circuit ─ Supports RTC counter (second, minute, hour) and calendar counter (day, month, year) ─ Supports Alarm registers (second, minute, hour, day, month, year) ─ Supports 32 bytes spare registers ─ Wake up from Deep Power-down mode or from Power-down mode ─ Supports wake up from Power-down mode by input pin Aug. 15, 2017 Page 12 of 130 Rev.1.07 NUC505 ─ Supports chip Power-off by register setting ─ Supports Power-on time-out for low battery protection Analog to Digital Converter ─ Analog input voltage range: 0~ AVDD ─ Supports single 12-bit SAR ADC conversion ─ 12-bit resolution and 10-bit accuracy is guaranteed ─ Up to 1MSPS conversion with ADC_CH1, and up to 200 kSPS with others (except ADC_CH0). ─ Up to 8 external single-ended analog input channels ─ Supports single ADC interrupt ─ An A/D conversion can be triggered by software control Built-in LDO with operating voltage 3.3V Low Voltage Detector (LVD) ─ With 2 levels: 2.8V / 2.6V Low Voltage Reset (LVR) ─ Threshold voltage level: 2.4 V Power Management ─ Advanced power management including Deep Power-down, Power-down, Idle and Normal Operating modes ─ Normal Operating mode  ─ CPU runs normally and all clocks on; the current consumption is around 46 mA (at 96 MHz CPU clock) Idle mode ─ CPU clock stop, and all other clocks on Power-down mode  ─ All clocks stop, except LXT and LIRC, with SRAM retention; the current consumption is around 700 uA Deep Power-down mode  All clocks stop, except LXT and LIRC, without SRAM retention; the current consumption is around 7 uA Operating Temperature: -40℃~+85℃ Packages ─ All Green package (RoHS) ─ QFN 88-pin (10mm x 10mm) ─ LQFP 64-pin (7mm x 7mm) ─ LQFP 48-pin (7mm x 7mm) ─ QFN 48-pin (7mm x 7mm) Aug. 15, 2017 Page 13 of 130 Rev.1.07 NUC505 SERIES DATASHEET  NUC505 3 ABBREVIATIONS 3.1 Abbreviations NUC505 SERIES DATASHEET Acronym Description ADC Analog-to-Digital Converter APB Advanced Peripheral Bus AHB Advanced High-Performance Bus DMA Direct Memory Access FIFO First In, First Out FPU Floating Point Unit GPIO General-Purpose Input/Output HCLK The Clock of Advanced High-Performance Bus HXT 12 MHz External High Speed Crystal Oscillator ICP In Circuit Programming ISP In System Programming LDO Low Dropout Regulator LIN Local Interconnect Network LIRC 32.768 kHz Internal Low Speed RC Oscillator LXT 32.768 kHz External Low Speed Crystal Oscillator LVD Low Voltage Detection MPU Memory Protection Unit NVIC Nested Vectored Interrupt Controller PCLK The Clock of Advanced Peripheral Bus PLL Phase-Locked Loop PWM Pulse Width Modulation SD Secure Digital SPI Serial Peripheral Interface SPIM Serial Master Interface Controller SPS Samples per Second TMR Timer Controller UART Universal Asynchronous Receiver/Transmitter USB Universal Serial Bus WDT Watchdog Timer WWDT Window Watchdog Timer Table 3.1-1 List of Abbreviations Aug. 15, 2017 Page 14 of 130 Rev.1.07 NUC505 4 PARTS INFORMATION LIST AND PIN CONFIGURATION 4.1 Selection Guide NuMicro® NUC505 Base Series Selection Guide 4.1.1 [1]: *√ marked in the table means that only NUC505DS13Y supports Headphone Out. Serial Flash (KB) SRAM (KB) ISP ROM (KB) I/O Timer (32-Bit) SD HOST I2S SPI UART USB 2.0 HS Device USB 2.0 FS Host PWM (16-Bit) 24-Bit Audio CODEC[1] DIGITAL MIC ADC (12-Bit) RTC IC ISP/ICP Package[2] LQFP64*: 7x7mm Part Number [2]: The packages are not pin-to-pin compatible even though they are the same packages. NUC505DLA 512 128 8 18 4 2 - 2 2 1 1 - - √ 1 5CH - √ LQFP48 NUC505DL13Y 2048 128 8 25 4 2 1 3 3 1 1 1 4 - 1 5CH √ √ LQFP48 NUC505YLA 512 128 8 18 4 2 - 2 2 1 1 - - √ 1 5CH - √ QFN48 NUC505YLA2Y 512 128 8 25 4 2 1 3 3 1 1 1 4 - 1 5CH √ √ QFN48 NUC505DSA 512 128 8 34 4 2 1 3 3 1 1 1 4 √ 1 5CH - √ LQFP64* NUC505DS13Y 2048 128 8 35 4 2 1 3 3 1 1 1 4 √* 1 8CH √ √ LQFP64* NUC505YO13Y 2048 128 8 52 4 2 1 3 3 1 1 2 4 √ 1 8CH √ √ QFN88 2 Connectivity ® Table 4.1-1 NuMicro NUC505 Base Series Selection Guide NUC505 SERIES DATASHEET Aug. 15, 2017 Page 15 of 130 Rev.1.07 NUC505 4.1.2 NuMicro® NUC505 Base Series Naming Rule A: 512KByte ® Figure 4.1-1 NuMicro NUC505 Base Series Selection Code NUC505 SERIES DATASHEET Aug. 15, 2017 Page 16 of 130 Rev.1.07 NUC505 MIC_BIAS MIC0_N MIC0_P AVDDCODEC VMID AVSSHP RHPOUT LHPOUT AVDDHP VSS USB_VBUS 35 34 33 32 31 30 29 28 27 26 25 NuMicro® NUC505DLA LQFP 48-pin VDD12 4.2.1 Pin Configuration 36 4.2 37 24 PB.5 AVDDADC 38 23 PB.4 AVSSADC 39 22 PB.3 PA.0 40 21 PB.2 PA.1 41 20 PB.1 PA.2 42 19 PB.0 PA.3 43 18 VDD PA.4 44 17 PA.11 VDD12 45 16 PA.10 VDD 46 15 PA.9 LDO_CAP 47 14 PA.8 VSS 48 13 USB_REXT 11 12 AVDDUSB 9 VDD12 USB_D+ 8 XT1_OUT 10 7 XT1_IN USB_D- 6 4 PB.14 VDD 3 PD.1\ICE_DAT 5 2 PD.0\ICE_CLK PB.15 1 nRESET LQFP 48-pin ® Figure 4.2-1 NuMicro NUC505DLA LQFP 48-pin Diagram Aug. 15, 2017 Page 17 of 130 Rev.1.07 NUC505 SERIES DATASHEET PD.4 NUC505 PA.0 AVSSADC AVDDADC VSS PB.9 PB.8 USB_VBUS PB.7 PB.6 PB.5 PB.4 PB.3 36 35 34 33 32 31 30 29 28 27 26 25 NuMicro® NUC505DL13Y LQFP 48-pin PA.1 37 24 PB.2 PA.2 38 23 PB.1 PA.3 39 22 PB.0 PA.4 40 21 VDD VDD12 41 20 PA.11 PB.10 42 19 PA.10 PB.11 43 18 PA.9 PB.12 44 17 PA.8 VDD 45 16 RTC_nRWAKE VDD 46 15 RTC_RPWR LDO_CAP 47 14 VBAT VSS 48 13 USB_REXT 11 12 AVDDUSB 9 VDD12 USB_D+ 8 XT1_OUT 10 7 XT1_IN USB_D- 6 VSS 4 PB.13 5 3 PD.1\ICE_DAT VDD 2 PD.0\ICE_CLK NUC505 SERIES DATASHEET 1 LQFP 48-pin nRESET 4.2.2 ® Figure 4.2-2 NuMicro NUC505DL13Y LQFP 48-pin Diagram Aug. 15, 2017 Page 18 of 130 Rev.1.07 NUC505 USB_VBUS VSS AVDDHP LHPOUT RHPOUT AVSSHP VMID AVDDCODEC MIC0_P MIC0_N PB.2 PA.1 41 20 PB.1 PA.2 42 19 PB.0 PA.3 43 18 VDD PA.4 44 17 PA.11 VDD12 45 16 PA.10 VDD 46 15 PA.9 LDO_CAP 47 14 PA.8 VSS 48 13 USB_REXT 25 21 26 40 27 PA.0 28 PB.3 29 22 30 39 31 AVSSADC 32 PB.4 33 23 34 38 9 VDD12 12 8 XT1_OUT AVDDUSB 7 XT1_IN 11 6 VDD USB_D+ 5 PB.15 10 4 PB.14 USB_D- 3 PD.1\ICE_DAT Note: The thermal pad (EPD) should be connected to GND. ® Figure 4.2-3 NuMicro NUC505YLA QFN 48-pin Diagram Aug. 15, 2017 Page 19 of 130 Rev.1.07 NUC505 SERIES DATASHEET 2 QFN 48-pin PD.0\ICE_CLK AVDDADC 35 PB.5 36 24 1 37 nRESET PD.4 MIC_BIAS NuMicro® NUC505YLA QFN 48-pin VDD12 4.2.3 NUC505 PB.3 PB.4 PB.5 PB.6 PB.7 USB_VBUS PB.8 PB.9 VSS AVDDADC VDD VDD12 41 20 PA.11 PB.10 42 19 PA.10 PB.11 43 18 PA.9 PB.12 44 17 PA.8 VDD 45 16 RTC_nRWAKE VDD 46 15 RTC_RPWR LDO_CAP 47 14 VBAT VSS 48 13 USB_REXT 25 21 26 40 27 PA.4 28 PB.0 29 22 30 39 31 PA.3 32 PB.1 33 23 34 38 9 VDD12 12 8 XT1_OUT AVDDUSB 7 XT1_IN 11 6 VSS USB_D+ 5 VDD 10 4 PB.13 USB_D- 3 PD.1\ICE_DAT NUC505 SERIES DATASHEET 2 QFN 48-pin PD.0\ICE_CLK PA.2 35 PB.2 36 24 1 37 nRESET PA.1 AVSSADC NuMicro® NUC505YLA2Y QFN 48-pin PA.0 4.2.4 Note: The thermal pad (EPD) should be connected to GND. ® Figure 4.2-4 NuMicro NUC505YLA2Y QFN 48-pin Diagram Aug. 15, 2017 Page 20 of 130 Rev.1.07 NUC505 AVDDADC PD.4 VDD12 MIC_BIAS MIC0_N MIC0_P AVDDCODEC VMID AVSSHP RHPOUT LHPOUT AVDDHP VSS USB_VBUS PB.5 PB.4 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 NuMicro® NUC505DSA LQFP 64-pin 48 4.2.5 49 32 PB.3 PA.0 50 31 PB.2 PA.1 51 30 PB.1 PA.2 52 29 PB.0 PA.3 53 28 VDD PA.4 54 27 PC.10 VDD12 55 26 PC.9 PB.10 56 25 PC.8 PB.11 57 24 PA.15 PB.12 58 23 PA.14 VDD 59 22 PA.13 PC.11 60 21 PA.12 PC.12 61 20 PA.11 VDD 62 19 PA.10 LDO_CAP 63 18 PA.9 VSS 64 17 PA.8 10 11 12 13 14 15 16 XT1_IN XT1_OUT VDD12 USB_D- USB_D+ AVDDUSB USB_REXT PB.15 VSS 6 PB.14 9 5 8 4 PB.13 VDD 3 PD.1\ICE_DAT 7 2 PD.0\ICE_CLK PC.0 1 nRESET LQFP 64-pin ® Figure 4.2-5 NuMicro NUC505DSA LQFP 64-pin Diagram Aug. 15, 2017 Page 21 of 130 Rev.1.07 NUC505 SERIES DATASHEET AVSSADC NUC505 AVSSADC AVDDADC AVDDCODEC VMID AVSSHP RHPOUT LHPOUT AVDDHP VSS PB.9 PB.8 USB_VBUS PB.7 PB.6 PB.5 PB.4 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 NuMicro® NUC505DS13Y LQFP 64-pn 49 32 PB.3 PA.1 50 31 PB.2 PA.2 51 30 PB.1 PA.3 52 29 PB.0 PA.4 53 28 VDD PA.5 54 27 PA.15 PA.6 55 26 PA.14 PA.7 56 25 PA.13 VDD12 57 24 PA.12 PB.10 58 23 PA.11 PB.11 59 22 PA.10 PB.12 60 21 PA.9 VDD 61 20 PA.8 VDD 62 19 RTC_nRWAKE LDO_CAP 63 18 RTC_RPWR VSS 64 17 VBAT 10 11 12 13 14 15 16 XT1_IN XT1_OUT VDD12 USB_D- USB_D+ AVDDUSB USB_REXT 9 VSS 6 PB.15 8 5 PB.14 VDD 4 PB.13 7 3 PD.1\ICE_DAT PC.0 2 PD.0\ICE_CLK LQFP 64-pin 1 NUC505 SERIES DATASHEET PA.0 nRESET 4.2.6 ® Figure 4.2-6 NuMicro NUC505DS13Y LQFP 64-pin Diagram Aug. 15, 2017 Page 22 of 130 Rev.1.07 NUC505 PD.4 PD.3 PD.2 VDD12 MIC_BIAS MIC0_N MIC0_P AVDDCODEC VMID AVSSHP RHPOUT VCMBF LHPOUT AVDDHP VDD PB.9 PB.8 USB_VBUS PB.7 PB.6 PB.5 PB.4 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 NuMicro® NUC505YO13Y QFN 88-pin 66 4.2.7 AVDDADC 67 44 PB.3 AVSSADC 68 43 PB.2 PA.0 69 42 PB.1 PA.1 70 41 PB.0 PA.2 71 40 VDD PA.3 72 39 PC.10 PA.4 73 38 PC.8 PA.5 74 37 PC.8 PA.6 75 36 PC.7 PA.7 76 35 PA.15 34 PA.14 33 PA.13 77 78 PB.11 79 32 PA.12 PB.12 80 31 PA.11 VDD 81 30 PA.10 PC.11 82 29 PA.9 PC.12 83 28 PA.8 PC.13 84 27 X32_OUT PC.14 85 26 X32_IN VDD 86 25 RTC_nRWAKE LDO_CAP 87 24 RTC_RPWR VSS 88 23 VBAT 20 21 22 USB_D- USB_D+ AVDDusb USB_REXT 18 19 17 VDD12 PC.3 XT1_OUT 11 VDD 16 10 PC.2 XT1_IN 9 15 8 PC.0 PC.1 PC.6 7 VDD12 6 PB.15 14 5 PB.14 13 4 PB.13 12 3 PD.0\ICE_CLK PD.1\ICE_DAT PC.5 2 PC.4 1 nRESET QFN 88-pin Note: The thermal pad (EPD) should be connected to GND. ® Figure 4.2-7 NuMicro NUC505YO13Y QFN 88-pin Diagram Aug. 15, 2017 Page 23 of 130 Rev.1.07 NUC505 SERIES DATASHEET VDD12 PB.10 NUC505 4.3 Pin Description 4.3.1 NuMicro® NUC505DLA LQFP 48-pin Description MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH) PA.0 MFP0 means SYS_GPA_MFPL[2:0]=0x0. PA.9 MFP5 means SYS_GPA_MFPH[6:4]=0x5. Pin No. Pin Name Type MFP* Description 1 nRESET I MFP0 External reset input: active LOW, with an internal pull-up. Set this pin low reset to initial state. 2 ICE_CLK O MFP0 Serial wired debugger clock pin. (In ICE mode) PD.0 I/O MFP0 General purpose digital I/O pin. I2C0_SCL O MFP2 I2C0 clock pin. ICE_DAT I/O MFP0 Serial wired debugger data pin. (In ICE mode) PD.1 I/O MFP0 General purpose digital I/O pin. I2C0_SDA I/O MFP2 I2C0 data input/output pin. PB.14 I/O MFP0 General purpose digital I/O pin. USBH1_D+ I/O MFP1 USB host-lite 1differential signal D+. I2C1_SCL O MFP2 I2C1 clock pin. PB.15 I/O MFP0 General purpose digital I/O pin. USBH1_D- I/O MFP1 USB host-lite 1 differential signal D-. I2C1_SDA I/O MFP2 I2C1 data input/output pin. 3 4 NUC505 SERIES DATASHEET 5 6 VDD A MFP0 Power supply for I/O ports, DC 3.3V. 7 XT1_IN I MFP0 External 12 MHz (high speed) crystal input pin. 8 XT1_OUT O MFP0 External 12 MHz (high speed) crystal output pin. 9 VDD12 A MFP0 Power supply for I/O ports, DC 1.2V 10 USB_D- A MFP0 USB differential signal D-. 11 USB_D+ A MFP0 USB differential signal D+. 12 AVDDUSB A MFP0 Power supply for analog USB, DC 3.3V. 13 USB_REXT A MFP0 12.1 KΩ used internally for USB circuitry. Aug. 15, 2017 Page 24 of 130 Rev.1.07 NUC505 14 I/O MFP0 General purpose digital I/O pin. SPIM_SS O MFP1 SPIM slave select pin. I2S_LRCLK I/O MFP2 I2S left right channel clock. UART1_TXD O MFP3 Data transmitter output pin for UART1. PA.9 I/O MFP0 General purpose digital I/O pin. SPIM_CLK O MFP1 SPIM serial clock pin. I2S_BCLK I/O MFP2 I2S bit clock pin. UART1_RXD I MFP3 Data receiver input pin for UART1. SYSCFG[0] I MFP0 System configuration setting bit 0. PA.10 I/O MFP0 General purpose digital I/O pin. SPIM_MOSI I/O MFP1 SPIM MOSI (Master Out, Slave In) pin. I2C1_SCL O MFP2 I2C1 clock pin. SD_CLK O MFP4 SD/SDH mode - clock. SYSCFG[1] I MFP0 System configuration setting bit 1. PA.11 I/O MFP0 General purpose digital I/O pin. SPIM_MISO I/O MFP1 SPIM MISO (Master In, Slave Out) pin. I2C1_SDA I/O MFP2 I2C1 data input/output pin. SD_CMD I MFP4 SD/SDH mode – command/response. 18 VDD A MFP0 Power supply for I/O ports, DC 3.3V. 19 PB.0 I/O MFP0 General purpose digital I/O pin. I2C0_SCL O MFP2 I2C0 clock pin. UART0_TXD O MFP3 Data transmitter output pin for UART0. SD_DAT2 I/O MFP4 SD/SDH mode data line bit 2. PB.1 I/O MFP0 General purpose digital I/O pin. I2C0_SDA I/O MFP2 I2C0 data input/output pin. I MFP3 Data receiver input pin for UART0. I/O MFP4 SD/SDH mode data line bit 3. 15 16 17 20 UART0_RXD SD_DAT3 Aug. 15, 2017 Page 25 of 130 NUC505 SERIES DATASHEET PA.8 Rev.1.07 NUC505 21 PB.2 I/O MFP0 General purpose digital I/O pin. SPI0_SS O MFP1 SPI0 slave select pin. SD_CMD I MFP4 SD/SDH mode – command/response. PB.3 I/O MFP0 General purpose digital I/O pin. SPI0_CLK O MFP1 SPI0 serial clock pin. SD_CLK O MFP4 SD/SDH mode – clock. SYSCFG[2] I MFP0 System configuration setting bit 2. PB.4 I/O MFP0 General purpose digital I/O pin. SPI0_MOSI O MFP1 SPI0 MOSI (Master Out, Slave In) pin. SYSCFG[3] I MFP0 System configuration setting bit 3. I/O MFP0 General purpose digital I/O pin. SPI0_MISO I MFP1 SPI0 MISO (Master In, Slave Out) pin. SD_nCD I MFP4 SD/SDH mode – card detect. 25 USB_VBUS33 I MFP0 Detects whether USB is plug-in. 26 VSS A MFP0 Ground 27 AVDDHP A MFP0 Power supply for analog CODEC headphone, DC 3.3V. 28 LHPOUT A MFP0 Headphone left channel output pin. 29 RHPOUT A MFP0 Headphone right channel output pin. 30 AVSSHP A MFP0 Ground for analog CODEC headphone. 31 VMID A MFP0 Headphone reference power. 32 AVDDCODEC A MFP0 Power supply for analog CODEC, DC 3.3V. 33 MIC0_P A MFP0 Microphone 0 positive input. 34 MIC0_N A MFP0 Microphone 0 negative input. 35 MIC_BIAS A MFP0 CODEC left line-in channel or Microphone bias. 36 VDD12 A MFP0 Power supply for I/O ports, DC 1.2V 37 PD.4 I/O MFP0 General purpose digital I/O pin. A MFP1 CODEC right line-in channel. 22 23 24 PB.5 NUC505 SERIES DATASHEET RLINEIN Aug. 15, 2017 Page 26 of 130 Rev.1.07 NUC505 AVDDADC A MFP0 Power supply for analog SAR-ADC, DC 3.3V. 39 AVSSADC A MFP0 Ground pin for analog SAR-ADC. 40 PA.0 I/O MFP0 General purpose digital I/O pin. A MFP1 ADC channel 0 analog input. I/O MFP0 General purpose digital I/O pin. A MFP1 ADC channel 1 analog input. I/O MFP0 General purpose digital I/O pin. ADC_CH2 A MFP1 ADC channel 2 analog input. I2S_MCLK O MFP2 I2S master clock output pin. PA.3 I/O MFP0 General purpose digital I/O pin. ADC_CH3 A MFP1 ADC channel 3 analog input. I2S_DI I MFP2 I2S data input. I/O MFP0 General purpose digital I/O pin. ADC_CH4 A MFP1 ADC channel 4 analog input. I2S_DO O MFP2 I2S data output. 45 VDD12 A MFP0 Power supply for I/O ports, DC 1.2V 46 VDD A MFP0 Power supply, DC 3.3V. 47 LDO_CAP A MFP0 LDO output pin. 48 VSS A MFP0 Ground. ADC_CH0 41 PA.1 ADC_CH1 42 43 44 PA.2 PA.4 Aug. 15, 2017 Page 27 of 130 NUC505 SERIES DATASHEET 38 Rev.1.07 NUC505 4.3.2 NuMicro® NUC505DL13Y LQFP 48-pin Description MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH) PA.0 MFP0 means SYS_GPA_MFPL[2:0]=0x0. PA.9 MFP5 means SYS_GPA_MFPH[6:4]=0x5. Pin No. Pin Name Type MFP* Description 1 nRESET I MFP0 External reset input: active LOW, with an internal pull-up. Set this pin low reset to initial state. 2 ICE_CLK O MFP0 Serial wired debugger clock pin. (In ICE mode) PD.0 I/O MFP0 General purpose digital I/O pin. I2C0_SCL O MFP2 I2C0 clock pin. ICE_DAT I/O MFP0 Serial wired debugger data pin. (In ICE mode) PD.1 I/O MFP0 General purpose digital I/O pin. I2C0_SDA I/O MFP2 I2C0 data input/output pin. PB.13 I/O MFP0 General purpose digital I/O pin. SPI1_MISO I MFP1 SPI1 MISO (Master In, Slave Out) pin. USBH1_D- I/O MFP2 USB host-lite 1 differential signal D-. UART2_nRTS O MFP3 Request to Send output pin for UART2. PWM_CH3 I/O MFP4 PWM channel3 output/capture input. 3 4 NUC505 SERIES DATASHEET 5 VDD A MFP0 Power supply for I/O ports, DC 3.3V. 6 VSS A MFP0 Ground. 7 XT1_IN I MFP0 External 12 MHz (high speed) crystal input pin. 8 XT1_OUT O MFP0 External 12 MHz (high speed) crystal output pin. 9 VDD12 A MFP0 Power supply for I/O ports, DC 1.2V 10 USB_D- A MFP0 USB differential signal D-. 11 USB_D+ A MFP0 USB differential signal D+. 12 AVDDUSB A MFP0 Power supply for analog USB, DC 3.3V. 13 USB_REXT A MFP0 12.1 KΩ used internally for USB circuitry. 14 VBAT A MFP0 Power supply by batteries for RTC, DC 3.3V. Aug. 15, 2017 Page 28 of 130 Rev.1.07 NUC505 RTC_RPWR O MFP0 Enable external power control source when active high. 16 RTC_nRWAKE I MFP0 System power enable trigger when active low. 17 PA.8 I/O MFP0 General purpose digital I/O pin. SPIM_SS O MFP1 SPIM slave select pin. I2S_LRCLK I/O MFP2 I2S left right channel clock. UART1_TXD O MFP3 Data transmitter output pin for UART1. PA.9 I/O MFP0 General purpose digital I/O pin. SPIM_CLK O MFP1 SPIM serial clock pin. I2S_BCLK I/O MFP2 I2S bit clock pin. UART1_RXD I MFP3 Data receiver input pin for UART1. SYSCFG[0] I MFP0 System configuration setting bit 0. PA.10 I/O MFP0 General purpose digital I/O pin. SPIM_MOSI I/O MFP1 SPIM MOSI (Master Out, Slave In) pin. I2C1_SCL O MFP2 I2C1 clock pin. SD_CLK O MFP4 SD/SDH mode - clock. SYSCFG[1] I MFP0 System configuration setting bit 1. PA.11 I/O MFP0 General purpose digital I/O pin. SPIM_MISO I/O MFP1 SPIM MISO (Master In, Slave Out) pin. I2C1_SDA I/O MFP2 I2C1 data input/output pin. SD_CMD I MFP4 SD/SDH mode – command/response. 21 VDD A MFP0 Power supply for I/O ports, DC 3.3V. 22 PB.0 I/O MFP0 General purpose digital I/O pin. I2C0_SCL O MFP2 I2C0 clock pin. UART0_TXD O MFP3 Data transmitter output pin for UART0. SD_DAT2 I/O MFP4 SD/SDH mode data line bit 2. PB.1 I/O MFP0 General purpose digital I/O pin. I2C0_SDA I/O MFP2 I2C0 data input/output pin. 18 19 20 23 Aug. 15, 2017 Page 29 of 130 NUC505 SERIES DATASHEET 15 Rev.1.07 NUC505 UART0_RXD 24 25 26 27 28 NUC505 SERIES DATASHEET 29 I MFP3 Data receiver input pin for UART0. SD_DAT3 I/O MFP4 SD/SDH mode data line bit 3. PB.2 I/O MFP0 General purpose digital I/O pin. SPI0_SS O MFP1 SPI0 slave select pin. SD_CMD I MFP4 SD/SDH mode – command/response. PB.3 I/O MFP0 General purpose digital I/O pin. SPI0_CLK O MFP1 SPI0 serial clock pin. SD_CLK O MFP4 SD/SDH mode – clock. SYSCFG[2] I MFP0 System configuration setting bit 2. PB.4 I/O MFP0 General purpose digital I/O pin. SPI0_MOSI O MFP1 SPI0 MOSI (Master Out, Slave In) pin. SYSCFG[3] I MFP0 System configuration setting bit 3. I/O MFP0 General purpose digital I/O pin. SPI0_MISO I MFP1 SPI0 MISO (Master In, Slave Out) pin. SD_nCD I MFP4 SD/SDH mode – card detect. PB.6 I/O MFP0 General purpose digital I/O pin. UART1_TXD O MFP3 Data transmitter output pin for UART1. SD_DAT0 I/O MFP4 SD/SDH mode data line bit 0. PB.7 I/O MFP0 General purpose digital I/O pin. I MFP3 Data receiver input pin for UART1. I/O MFP4 SD/SDH mode data line bit 1. I MFP0 Detects whether USB is plug-in. PB.5 UART1_RXD SD_DAT1 30 USB_VBUS33 31 PB.8 I/O MFP0 General purpose digital I/O pin. USBH_PWEN O MFP1 USB host mode to control an external overcurrent source. TM1_CNT_OUT I/O MFP2 Timer1 event counter input/toggle output. I MFP3 Clear to Send input pin for UART1. I/O MFP4 SD/SDH mode data line bit 2. UART1_nCTS SD_DAT2 Aug. 15, 2017 Page 30 of 130 Rev.1.07 NUC505 32 PB.9 I/O MFP0 General purpose digital I/O pin. USBH_OVD I MFP1 USB host bus power over voltage detector. TM1_EXT I MFP2 Timer1 external capture input. UART1_nRTS O MFP3 Request to Send output pin for UART1. SD_DAT3 I/O MFP4 SD/SDH mode data line bit 3. VSS A MFP0 Ground 34 AVDDADC A MFP0 Power supply for analog SAR-ADC, DC 3.3V. 35 AVSSADC A MFP0 Ground pin for analog SAR-ADC. 36 PA.0 I/O MFP0 General purpose digital I/O pin. A MFP1 ADC channel 0 analog input. I/O MFP0 General purpose digital I/O pin. A MFP1 ADC channel 1 analog input. I/O MFP0 General purpose digital I/O pin. ADC_CH2 A MFP1 ADC channel 2 analog input. I2S_MCLK O MFP2 I2S master clock output pin. PA.3 I/O MFP0 General purpose digital I/O pin. ADC_CH3 A MFP1 ADC channel 3 analog input. I2S_DI I MFP2 I2S data input. I/O MFP0 General purpose digital I/O pin. ADC_CH4 A MFP1 ADC channel 4 analog input. I2S_DO O MFP2 I2S data output. 41 VDD12 A MFP0 Power supply for I/O ports, DC 1.2V 42 PB.10 I/O MFP0 General purpose digital I/O pin. SPI1_SS O MFP1 SPI1 slave select pin. I2C1_SCL O MFP2 I2C1 clock pin. UART2_TXD O MFP3 Data transmitter output pin for UART2. PWM_CH0 I/O MFP4 PWM channel0 output/capture input. ADC_CH0 37 PA.1 ADC_CH1 38 39 40 PA.2 PA.4 Aug. 15, 2017 Page 31 of 130 NUC505 SERIES DATASHEET 33 Rev.1.07 NUC505 43 PB.11 I/O MFP0 General purpose digital I/O pin. SPI1_CLK O MFP1 SPI1 serial clock pin. I2C1_SDA I/O MFP2 I2C1 data input/output pin. I MFP3 Data receiver input pin for UART2. PWM_CH1 I/O MFP4 PWM channel1 output/capture input. PB.12 I/O MFP0 General purpose digital I/O pin. SPI1_MOSI O MFP1 SPI1 MOSI (Master Out, Slave In) pin. USBH1_D+ I/O MFP2 USB host-lite 1 differential signal D+ I MFP3 Clear to send input pin for UART2. I/O MFP4 PWM channel2 output/capture input. UART2_RXD 44 UART2_nCTS PWM_CH2 45 VDD A MFP0 Power supply for I/O ports, DC 3.3V. 46 VDD A MFP0 Power supply, DC 3.3V. 47 LDO_CAP A MFP0 LDO output pin. 48 VSS A MFP0 Ground. NUC505 SERIES DATASHEET Aug. 15, 2017 Page 32 of 130 Rev.1.07 NUC505 4.3.3 NuMicro® NUC505YLA QFN 48-pin Description MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH) PA.0 MFP0 means SYS_GPA_MFPL[2:0]=0x0. PA.9 MFP5 means SYS_GPA_MFPH[6:4]=0x5. Pin No. Pin Name Type MFP* Description nRESET I MFP0 External reset input: active LOW, with an internal pull-up. Set this pin low reset to initial state. 2 ICE_CLK O MFP0 Serial wired debugger clock pin. (In ICE mode) PD.0 I/O MFP0 General purpose digital I/O pin. I2C0_SCL O MFP2 I2C0 clock pin. ICE_DAT I/O MFP0 Serial wired debugger data pin. (In ICE mode) PD.1 I/O MFP0 General purpose digital I/O pin. I2C0_SDA I/O MFP2 I2C0 data input/output pin. PB.14 I/O MFP0 General purpose digital I/O pin. USBH1_D+ I/O MFP1 USB host-lite 1differential signal D+. I2C1_SCL O MFP2 I2C1 clock pin. PB.15 I/O MFP0 General purpose digital I/O pin. USBH1_D- I/O MFP1 USB host-lite 1 differential signal D-. I2C1_SDA I/O MFP2 I2C1 data input/output pin. 3 4 5 6 VDD A MFP0 Power supply for I/O ports, DC 3.3V. 7 XT1_IN I MFP0 External 12 MHz (high speed) crystal input pin. 8 XT1_OUT O MFP0 External 12 MHz (high speed) crystal output pin. 9 VDD12 A MFP0 Power supply for I/O ports, DC 1.2V 10 USB_D- A MFP0 USB differential signal D-. 11 USB_D+ A MFP0 USB differential signal D+. 12 AVDDUSB A MFP0 Power supply for analog USB, DC 3.3V. 13 USB_REXT A MFP0 12.1 KΩ used internally for USB circuitry. 14 PA.8 I/O MFP0 General purpose digital I/O pin. Aug. 15, 2017 Page 33 of 130 NUC505 SERIES DATASHEET 1 Rev.1.07 NUC505 SPIM_SS O MFP1 SPIM slave select pin. I2S_LRCLK I/O MFP2 I2S left right channel clock. UART1_TXD O MFP3 Data transmitter output pin for UART1. PA.9 I/O MFP0 General purpose digital I/O pin. SPIM_CLK O MFP1 SPIM serial clock pin. I2S_BCLK I/O MFP2 I2S bit clock pin. UART1_RXD I MFP3 Data receiver input pin for UART1. SYSCFG[0] I MFP0 System configuration setting bit 0. PA.10 I/O MFP0 General purpose digital I/O pin. SPIM_MOSI I/O MFP1 SPIM MOSI (Master Out, Slave In) pin. I2C1_SCL O MFP2 I2C1 clock pin. SD_CLK O MFP4 SD/SDH mode - clock. SYSCFG[1] I MFP0 System configuration setting bit 1. PA.11 I/O MFP0 General purpose digital I/O pin. SPIM_MISO I/O MFP1 SPIM MISO (Master In, Slave Out) pin. I2C1_SDA I/O MFP2 I2C1 data input/output pin. SD_CMD I MFP4 SD/SDH mode – command/response. 18 VDD A MFP0 Power supply for I/O ports, DC 3.3V. 19 PB.0 I/O MFP0 General purpose digital I/O pin. I2C0_SCL O MFP2 I2C0 clock pin. UART0_TXD O MFP3 Data transmitter output pin for UART0. SD_DAT2 I/O MFP4 SD/SDH mode data line bit 2. PB.1 I/O MFP0 General purpose digital I/O pin. I2C0_SDA I/O MFP2 I2C0 data input/output pin. I MFP3 Data receiver input pin for UART0. SD_DAT3 I/O MFP4 SD/SDH mode data line bit 3. PB.2 I/O MFP0 General purpose digital I/O pin. 15 16 17 NUC505 SERIES DATASHEET 20 UART0_RXD 21 Aug. 15, 2017 Page 34 of 130 Rev.1.07 NUC505 O MFP1 SPI0 slave select pin. SD_CMD I MFP4 SD/SDH mode – command/response. PB.3 I/O MFP0 General purpose digital I/O pin. SPI0_CLK O MFP1 SPI0 serial clock pin. SD_CLK O MFP4 SD/SDH mode – clock. SYSCFG[2] I MFP0 System configuration setting bit 2. PB.4 I/O MFP0 General purpose digital I/O pin. SPI0_MOSI O MFP1 SPI0 MOSI (Master Out, Slave In) pin. SYSCFG[3] I MFP0 System configuration setting bit 3. I/O MFP0 General purpose digital I/O pin. SPI0_MISO I MFP1 SPI0 MISO (Master In, Slave Out) pin. SD_nCD I MFP4 SD/SDH mode – card detect. 25 USB_VBUS33 I MFP0 Detects whether USB is plug-in. 26 VSS A MFP0 Ground 27 AVDDHP A MFP0 Power supply for analog CODEC headphone, DC 3.3V. 28 LHPOUT A MFP0 Headphone left channel output pin. 29 RHPOUT A MFP0 Headphone right channel output pin. 30 AVSSHP A MFP0 Ground for analog CODEC headphone. 31 VMID A MFP0 Headphone reference power. 32 AVDDCODEC A MFP0 Power supply for analog CODEC, DC 3.3V. 33 MIC0_P A MFP0 Microphone 0 positive input. 34 MIC0_N A MFP0 Microphone 0 negative input. 35 MIC_BIAS A MFP0 CODEC left line-in channel or Microphone bias. 36 VDD12 A MFP0 Power supply for I/O ports, DC 1.2V 37 PD.4 I/O MFP0 General purpose digital I/O pin. RLINEIN A MFP1 CODEC right line-in channel. AVDDADC A MFP0 Power supply for analog SAR-ADC, DC 3.3V. 22 23 24 38 PB.5 Aug. 15, 2017 Page 35 of 130 NUC505 SERIES DATASHEET SPI0_SS Rev.1.07 NUC505 39 AVSSADC A MFP0 Ground pin for analog SAR-ADC. 40 PA.0 I/O MFP0 General purpose digital I/O pin. A MFP1 ADC channel 0 analog input. I/O MFP0 General purpose digital I/O pin. A MFP1 ADC channel 1 analog input. I/O MFP0 General purpose digital I/O pin. ADC_CH2 A MFP1 ADC channel 2 analog input. I2S_MCLK O MFP2 I2S master clock output pin. PA.3 I/O MFP0 General purpose digital I/O pin. ADC_CH3 A MFP1 ADC channel 3 analog input. I2S_DI I MFP2 I2S data input. I/O MFP0 General purpose digital I/O pin. ADC_CH4 A MFP1 ADC channel 4 analog input. I2S_DO O MFP2 I2S data output. 45 VDD12 A MFP0 Power supply for I/O ports, DC 1.2V 46 VDD A MFP0 Power supply, DC 3.3V. 47 LDO_CAP A MFP0 LDO output pin. 48 VSS A MFP0 Ground. ADC_CH0 41 PA.1 ADC_CH1 42 43 44 PA.2 PA.4 NUC505 SERIES DATASHEET Note: The thermal pad (EPD) on the bottom of QFN package should be connected to GND. Aug. 15, 2017 Page 36 of 130 Rev.1.07 NUC505 4.3.4 NuMicro® NUC505YLA2Y QFN 48-pin Description MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH) PA.0 MFP0 means SYS_GPA_MFPL[2:0]=0x0. PA.9 MFP5 means SYS_GPA_MFPH[6:4]=0x5. Pin No. Pin Name Type MFP* Description nRESET I MFP0 External reset input: active LOW, with an internal pull-up. Set this pin low reset to initial state. 2 ICE_CLK O MFP0 Serial wired debugger clock pin. (In ICE mode) PD.0 I/O MFP0 General purpose digital I/O pin. I2C0_SCL O MFP2 I2C0 clock pin. ICE_DAT I/O MFP0 Serial wired debugger data pin. (In ICE mode) PD.1 I/O MFP0 General purpose digital I/O pin. I2C0_SDA I/O MFP2 I2C0 data input/output pin. PB.13 I/O MFP0 General purpose digital I/O pin. SPI1_MISO I MFP1 SPI1 MISO (Master In, Slave Out) pin. USBH1_D- I/O MFP2 USB host-lite 1 differential signal D-. UART2_nRTS O MFP3 Request to Send output pin for UART2. PWM_CH3 I/O MFP4 PWM channel3 output/capture input. 3 4 5 VDD A MFP0 Power supply for I/O ports, DC 3.3V. 6 VSS A MFP0 Ground. 7 XT1_IN I MFP0 External 12 MHz (high speed) crystal input pin. 8 XT1_OUT O MFP0 External 12 MHz (high speed) crystal output pin. 9 VDD12 A MFP0 Power supply for I/O ports, DC 1.2V 10 USB_D- A MFP0 USB differential signal D-. 11 USB_D+ A MFP0 USB differential signal D+. 12 AVDDUSB A MFP0 Power supply for analog USB, DC 3.3V. 13 USB_REXT A MFP0 12.1 KΩ used internally for USB circuitry. 14 VBAT A MFP0 Power supply by batteries for RTC, DC 3.3V. Aug. 15, 2017 Page 37 of 130 NUC505 SERIES DATASHEET 1 Rev.1.07 NUC505 15 RTC_RPWR O MFP0 Enable external power control source when active high. 16 RTC_nRWAKE I MFP0 System power enable trigger when active low. 17 PA.8 I/O MFP0 General purpose digital I/O pin. SPIM_SS O MFP1 SPIM slave select pin. I2S_LRCLK I/O MFP2 I2S left right channel clock. UART1_TXD O MFP3 Data transmitter output pin for UART1. PA.9 I/O MFP0 General purpose digital I/O pin. SPIM_CLK O MFP1 SPIM serial clock pin. I2S_BCLK I/O MFP2 I2S bit clock pin. UART1_RXD I MFP3 Data receiver input pin for UART1. SYSCFG[0] I MFP0 System configuration setting bit 0. PA.10 I/O MFP0 General purpose digital I/O pin. SPIM_MOSI I/O MFP1 SPIM MOSI (Master Out, Slave In) pin. I2C1_SCL O MFP2 I2C1 clock pin. SD_CLK O MFP4 SD/SDH mode - clock. SYSCFG[1] I MFP0 System configuration setting bit 1. PA.11 I/O MFP0 General purpose digital I/O pin. SPIM_MISO I/O MFP1 SPIM MISO (Master In, Slave Out) pin. I2C1_SDA I/O MFP2 I2C1 data input/output pin. SD_CMD I MFP4 SD/SDH mode – command/response. 21 VDD A MFP0 Power supply for I/O ports, DC 3.3V. 22 PB.0 I/O MFP0 General purpose digital I/O pin. I2C0_SCL O MFP2 I2C0 clock pin. UART0_TXD O MFP3 Data transmitter output pin for UART0. SD_DAT2 I/O MFP4 SD/SDH mode data line bit 2. PB.1 I/O MFP0 General purpose digital I/O pin. I2C0_SDA I/O MFP2 I2C0 data input/output pin. 18 19 NUC505 SERIES DATASHEET 20 23 Aug. 15, 2017 Page 38 of 130 Rev.1.07 NUC505 UART0_RXD 24 25 26 27 28 MFP3 Data receiver input pin for UART0. SD_DAT3 I/O MFP4 SD/SDH mode data line bit 3. PB.2 I/O MFP0 General purpose digital I/O pin. SPI0_SS O MFP1 SPI0 slave select pin. SD_CMD I MFP4 SD/SDH mode – command/response. PB.3 I/O MFP0 General purpose digital I/O pin. SPI0_CLK O MFP1 SPI0 serial clock pin. SD_CLK O MFP4 SD/SDH mode – clock. SYSCFG[2] I MFP0 System configuration setting bit 2. PB.4 I/O MFP0 General purpose digital I/O pin. SPI0_MOSI O MFP1 SPI0 MOSI (Master Out, Slave In) pin. SYSCFG[3] I MFP0 System configuration setting bit 3. I/O MFP0 General purpose digital I/O pin. SPI0_MISO I MFP1 SPI0 MISO (Master In, Slave Out) pin. SD_nCD I MFP4 SD/SDH mode – card detect. PB.6 I/O MFP0 General purpose digital I/O pin. UART1_TXD O MFP3 Data transmitter output pin for UART1. SD_DAT0 I/O MFP4 SD/SDH mode data line bit 0. PB.7 I/O MFP0 General purpose digital I/O pin. I MFP3 Data receiver input pin for UART1. I/O MFP4 SD/SDH mode data line bit 1. I MFP0 Detects whether USB is plug-in. PB.5 UART1_RXD SD_DAT1 NUC505 SERIES DATASHEET 29 I 30 USB_VBUS33 31 PB.8 I/O MFP0 General purpose digital I/O pin. USBH_PWEN O MFP1 USB host mode to control an external overcurrent source. TM1_CNT_OUT I/O MFP2 Timer1 event counter input/toggle output. I MFP3 Clear to Send input pin for UART1. I/O MFP4 SD/SDH mode data line bit 2. UART1_nCTS SD_DAT2 Aug. 15, 2017 Page 39 of 130 Rev.1.07 NUC505 32 PB.9 I/O MFP0 General purpose digital I/O pin. USBH_OVD I MFP1 USB host bus power over voltage detector. TM1_EXT I MFP2 Timer1 external capture input. UART1_nRTS O MFP3 Request to Send output pin for UART1. SD_DAT3 I/O MFP4 SD/SDH mode data line bit 3. 33 VSS A MFP0 Ground 34 AVDDADC A MFP0 Power supply for analog SAR-ADC, DC 3.3V. 35 AVSSADC A MFP0 Ground pin for analog SAR-ADC. 36 PA.0 I/O MFP0 General purpose digital I/O pin. A MFP1 ADC channel 0 analog input. I/O MFP0 General purpose digital I/O pin. A MFP1 ADC channel 1 analog input. I/O MFP0 General purpose digital I/O pin. ADC_CH2 A MFP1 ADC channel 2 analog input. I2S_MCLK O MFP2 I2S master clock output pin. PA.3 I/O MFP0 General purpose digital I/O pin. ADC_CH3 A MFP1 ADC channel 3 analog input. I2S_DI I MFP2 I2S data input. I/O MFP0 General purpose digital I/O pin. ADC_CH4 A MFP1 ADC channel 4 analog input. I2S_DO O MFP2 I2S data output. 41 VDD12 A MFP0 Power supply for I/O ports, DC 1.2V 42 PB.10 I/O MFP0 General purpose digital I/O pin. SPI1_SS O MFP1 SPI1 slave select pin. I2C1_SCL O MFP2 I2C1 clock pin. UART2_TXD O MFP3 Data transmitter output pin for UART2. PWM_CH0 I/O MFP4 PWM channel0 output/capture input. ADC_CH0 37 PA.1 ADC_CH1 38 39 NUC505 SERIES DATASHEET 40 PA.2 PA.4 Aug. 15, 2017 Page 40 of 130 Rev.1.07 NUC505 43 PB.11 I/O MFP0 General purpose digital I/O pin. SPI1_CLK O MFP1 SPI1 serial clock pin. I2C1_SDA I/O MFP2 I2C1 data input/output pin. I MFP3 Data receiver input pin for UART2. PWM_CH1 I/O MFP4 PWM channel1 output/capture input. PB.12 I/O MFP0 General purpose digital I/O pin. SPI1_MOSI O MFP1 SPI1 MOSI (Master Out, Slave In) pin. USBH1_D+ I/O MFP2 USB host-lite 1 differential signal D+ I MFP3 Clear to send input pin for UART2. I/O MFP4 PWM channel2 output/capture input. UART2_RXD 44 UART2_nCTS PWM_CH2 45 VDD A MFP0 Power supply for I/O ports, DC 3.3V. 46 VDD A MFP0 Power supply, DC 3.3V. 47 LDO_CAP A MFP0 LDO output pin. 48 VSS A MFP0 Ground. Note: The thermal pad (EPD) on the bottom of QFN package should be connected to GND. NUC505 SERIES DATASHEET Aug. 15, 2017 Page 41 of 130 Rev.1.07 NUC505 4.3.5 NuMicro® NUC505DSA LQFP 64-pin Description MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH) PA.0 MFP0 means SYS_GPA_MFPL[2:0]=0x0. PA.9 MFP5 means SYS_GPA_MFPH[6:4]=0x5. Pin No. Pin Name Type MFP Description 1 nRESET I MFP0 External reset input: active LOW, with an internal pull-up. Set this pin low reset to initial state. 2 ICE_CLK O MFP0 Serial wired debugger clock pin. (In ICE mode) PD.0 I/O MFP0 General purpose digital I/O pin. I2C0_SCL O MFP2 I2C0 clock pin. ICE_DAT I/O MFP0 Serial wired debugger data pin. (In ICE mode) PD.1 I/O MFP0 General purpose digital I/O pin. I2C0_SDA I/O MFP2 I2C0 data input/output pin. PB.13 I/O MFP0 General purpose digital I/O pin. SPI1_MISO I MFP1 SPI1 MISO (Master In, Slave Out) pin. USBH1_D- I/O MFP2 USB host-lite 1 differential signal D-. UART2_nRTS O MFP3 Request to Send output pin for UART2. PWM_CH3 I/O MFP4 PWM channel3 output/capture input. PB.14 I/O MFP0 General purpose digital I/O pin. USBH1_D+ I/O MFP1 USB host-lite 1 differential signal D+. I2C1_SCL O MFP2 I2C1 clock pin. PB.15 I/O MFP0 General purpose digital I/O pin. USBH1_D- I/O MFP1 USB host-lite 1differential signal D-. I2C1_SDA I/O MFP2 I2C1 data input/output pin. PC.0 I/O MFP0 General purpose digital I/O pin. SD_CMD I MFP1 SD/SDH mode – command/response. 8 VDD A MFP0 Power supply for I/O ports, DC 3.3V. 9 VSS A MFP0 Ground 3 4 NUC505 SERIES DATASHEET 5 6 7 Aug. 15, 2017 Page 42 of 130 Rev.1.07 NUC505 XT1_IN I MFP0 External 12 MHz (high speed) crystal input pin. 11 XT1_OUT O MFP0 External 12 MHz (high speed) crystal output pin. 12 VDD12 A MFP0 Power supply for I/O ports, DC 1.2V 13 USB_D- A MFP0 USB differential signal D-. 14 USB_D+ A MFP0 USB differential signal D+. 15 AVDDUSB A MFP0 Power supply for analog USB, DC 3.3V. 16 USB_REXT A MFP0 12.1 KΩ used internally for USB circuitry. 17 PA.8 I/O MFP0 General purpose digital I/O pin. SPIM_SS O MFP1 SPIM slave select pin. I2S_LRCLK I/O MFP2 I2S left right channel clock. UART1_TXD O MFP3 Data transmitter output pin for UART1. PA.9 I/O MFP0 General purpose digital I/O pin. SPIM_CLK O MFP1 SPIM serial clock pin. I2S_BCLK I/O MFP2 I2S bit clock pin. UART1_RXD I MFP3 Data receiver input pin for UART1. SYSCFG[0] I MFP0 System configuration setting bit 0. PA.10 I/O MFP0 General purpose digital I/O pin. SPIM_MOSI I/O MFP1 SPIM MOSI (Master Out, Slave In) pin. 18 19 NUC505 SERIES DATASHEET 10 (Data 0 pin for Quad Mode I/O). 20 I2C1_SCL O MFP2 I2C1 clock pin. SD_CLK O MFP4 SD/SDH mode – clock. SYSCFG[1] I MFP0 System configuration setting bit 1. PA.11 I/O MFP0 General purpose digital I/O pin. SPIM_MISO I/O MFP1 SPIM MISO (Master In, Slave Out) pin. (Data 1 pin for Quad Mode I/O). 21 I2C1_SDA I/O MFP2 I2C1 data input/output pin. SD_CMD I MFP4 SD/SDH mode – command/response. I/O MFP0 General purpose digital I/O pin. PA.12 Aug. 15, 2017 Page 43 of 130 Rev.1.07 NUC505 SPIM_D2 I/O MFP1 SPIM data 2 pin for Quad Mode I/O. I MFP2 Timer0 event counter input/toggle output. PA.13 I/O MFP0 General purpose digital I/O pin. SPIM_D3 I/O MFP1 SPIM data 3 pin for Quad Mode I/O. TM0_EXT I MFP2 Timer0 external capture input. SD_nCD I MFP4 SD/SDH mode – card detect. PA.14 I/O MFP0 General purpose digital I/O pin. I2C0_SCL O MFP2 I2C0 clock pin. SD_DAT0 I/O MFP4 SD/SDH mode data line bit 0. PA.15 I/O MFP0 General purpose digital I/O pin. I2C0_SDA I/O MFP2 I2C0 data input/output pin. SD_DAT1 I/O MFP4 SD/SDH mode data line bit 1. PC.8 I/O MFP0 General purpose digital I/O pin. I2S_MCLK O MFP1 I2S master clock output pin. PC.9 I/O MFP0 General purpose digital I/O pin. I MFP1 I2S data input. TM2_CNT_OUT I/O MFP2 Timer2 event counter input/toggle output. PWM_CH0 I/O MFP3 PWM channel0 output/capture input. PC.10 I/O MFP0 General purpose digital I/O pin. I2S_DO O MFP1 I2S data output. TM2_EXT I MFP2 Timer2 external capture input. PWM_CH1 I/O MFP3 PWM channel1 output/capture input. TM0_CNT_OUT 22 23 24 25 26 I2S_DI NUC505 SERIES DATASHEET 27 28 VDD A MFP0 Power supply for I/O ports, DC 3.3V. 29 PB.0 I/O MFP0 General purpose digital I/O pin. I2C0_SCL O MFP2 I2C0 clock pin. UART0_TXD O MFP3 Data transmitter output pin for UART0. SD_DAT2 I/O MFP4 SD/SDH mode data line bit 2. Aug. 15, 2017 Page 44 of 130 Rev.1.07 NUC505 30 I/O MFP0 General purpose digital I/O pin. I2C0_SDA I/O MFP2 I2C0 data input/output pin. I MFP3 Data receiver input pin for UART0. SD_DAT3 I/O MFP4 SD/SDH mode data line bit 3. PB.2 I/O MFP0 General purpose digital I/O pin. SPI0_SS O MFP1 SPI0 slave select pin. SD_CMD I MFP4 SD/SDH mode – command/response. PB.3 I/O MFP0 General purpose digital I/O pin. SPI0_CLK O MFP1 SPI0 serial clock pin. SD_CLK O MFP4 SD/SDH mode – clock. SYSCFG[2] I MFP0 System configuration setting bit 2. PB.4 I/O MFP0 General purpose digital I/O pin. SPI0_MOSI O MFP1 SPI0 MOSI (Master Out, Slave In) pin. SYSCFG[3] I MFP0 System configuration setting bit 3. I/O MFP0 General purpose digital I/O pin. SPI0_MISO I MFP1 SPI0 MISO (Master In, Slave Out) pin. SD_nCD I MFP4 SD/SDH mode – card detect. 35 USB_VBUS33 I MFP0 Power supply from USB host or HUB. 36 VSS A MFP0 Ground. 37 AVDDHP AP VDD Power supply for analog CODEC headphone, DC 3.3V. 38 LHPOUT A MFP0 Headphone left channel output pin. 39 RHPOUT A MFP0 Headphone right channel output pin. 40 AVSSHP A MFP0 Ground for analog CODEC headphone. 41 VMID A MFP0 Headphone reference power. 42 AVDDCODEC A MFP0 Power supply for analog CODEC, DC 3.3V. 43 MIC0_P A MFP0 Microphone 0 positive input. 44 MIC0_N A MFP0 Microphone 0 negative input. UART0_RXD 31 32 33 34 PB.5 Aug. 15, 2017 Page 45 of 130 Rev.1.07 NUC505 SERIES DATASHEET PB.1 NUC505 45 MIC_BIAS A MFP0 CODEC left line-in channel or Microphone bias. 46 VDD12 A MFP0 Power supply for I/O ports, DC 1.2V 47 PD.4 I/O MFP0 General purpose digital I/O pin. RLINEIN A MFP1 CODEC right line-in channel. 48 AVDDADC A MFP0 Power supply for analog SAR-ADC, DC 3.3V. 49 AVSSADC A MFP0 Ground pin for analog SAR-ADC. 50 PA.0 I/O MFP0 General purpose digital I/O pin. A MFP1 ADC channel 0 analog input. I/O MFP0 General purpose digital I/O pin. A MFP1 ADC channel 1 analog input. I/O MFP0 General purpose digital I/O pin. ADC_CH2 A MFP1 ADC channel 2 analog input. I2S_MCLK O MFP2 I2S master clock output pin. PA.3 I/O MFP0 General purpose digital I/O pin. ADC_CH3 A MFP1 ADC channel 3 analog input. I2S_DI I MFP2 I2S data input. I/O MFP0 General purpose digital I/O pin. ADC_CH4 A MFP1 ADC channel 4 analog input. I2S_DO O MFP2 I2S data output. 55 VDD12 A MFP0 Power supply for I/O ports, DC 1.2V 56 PB.10 I/O MFP0 General purpose digital I/O pin. SPI1_SS O MFP1 SPI1 slave select pin. I2C1_SCL O MFP2 I2C1 clock pin. UART2_TXD O MFP3 Data transmitter output pin for UART2. PWM_CH0 I/O MFP4 PWM channel0 output/capture input. PB.11 I/O MFP0 General purpose digital I/O pin. SPI1_CLK O MFP1 SPI1 serial clock pin. ADC_CH0 51 PA.1 ADC_CH1 52 53 NUC505 SERIES DATASHEET 54 57 PA.2 PA.4 Aug. 15, 2017 Page 46 of 130 Rev.1.07 NUC505 I2C1_SDA I/O MFP2 I2C1 data input/output pin. I MFP3 Data receiver input pin for UART2. PWM_CH1 I/O MFP4 PWM channel1 output/capture input. PB.12 I/O MFP0 General purpose digital I/O pin. SPI1_MOSI O MFP1 SPI1 MOSI (Master Out, Slave In) pin. USBH1_D+ I/O MFP2 USB host-lite 1 differential signal D+ I MFP3 Clear to Send input pin for UART2. I/O MFP4 PWM channel2 output/capture input. A MFP0 Power supply for I/O ports, DC 3.3V. UART2_RXD 58 UART2_nCTS PWM_CH2 VDD 60 PC.11 I/O MFP0 General purpose digital I/O pin. I2S_LRCLK I/O MFP1 I2S left right channel clock. TM3_CNT_OUT I/O MFP2 Timer3 event counter input/toggle output. PWM_CH2 I/O MFP3 PWM channel2 output/capture input. PC.12 I/O MFP0 General purpose digital I/O pin. I2S_BCLK I/O MFP1 I2S bit clock pin. TM3_EXT I MFP2 Timer3 external capture input. PWM_CH3 I/O MFP3 PWM channel3 output/capture input. 61 62 VDD A MFP0 Power supply, DC 3.3V. 63 LDO_CAP A MFP0 LDO output pin. 64 VSS A MFP0 Ground. Aug. 15, 2017 Page 47 of 130 NUC505 SERIES DATASHEET 59 Rev.1.07 NUC505 4.3.6 NuMicro® NUC505DS13Y LQFP 64-pin Description MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH) PA.0 MFP0 means SYS_GPA_MFPL[2:0]=0x0. PA.9 MFP5 means SYS_GPA_MFPH[6:4]=0x5. Pin No. Pin Name Type MFP Description 1 nRESET I MFP0 External reset input: active LOW, with an internal pull-up. Set this pin low reset to initial state. 2 ICE_CLK O MFP0 Serial wired debugger clock pin. (In ICE mode) PD.0 I/O MFP0 General purpose digital I/O pin. I2C0_SCL O MFP2 I2C0 clock pin. ICE_DAT I/O MFP0 Serial wired debugger data pin. (In ICE mode) PD.1 I/O MFP0 General purpose digital I/O pin. I2C0_SDA I/O MFP2 I2C0 data input/output pin. PB.13 I/O MFP0 General purpose digital I/O pin. SPI1_MISO I MFP1 SPI1 MISO (Master In, Slave Out) pin. USBH1_D- I/O MFP2 USB host-lite 1 differential signal D-. UART2_nRTS O MFP3 Request to Send output pin for UART2. PWM_CH3 I/O MFP4 PWM channel3 output/capture input. PB.14 I/O MFP0 General purpose digital I/O pin. USBH1_D+ I/O MFP1 USB host-lite 1 differential signal D+. I2C1_SCL O MFP2 I2C1 clock pin. PB.15 I/O MFP0 General purpose digital I/O pin. USBH1_D- I/O MFP1 USB host-lite 1differential signal D-. I2C1_SDA I/O MFP2 I2C1 data input/output pin. PC.0 I/O MFP0 General purpose digital I/O pin. SD_CMD I MFP1 SD/SDH mode – command/response. 8 VDD A MFP0 Power supply for I/O ports, DC 3.3V. 9 VSS A MFP0 Ground 3 4 NUC505 SERIES DATASHEET 5 6 7 Aug. 15, 2017 Page 48 of 130 Rev.1.07 NUC505 XT1_IN I MFP0 External 12 MHz (high speed) crystal input pin. 11 XT1_OUT O MFP0 External 12 MHz (high speed) crystal output pin. 12 VDD12 A MFP0 Power supply for I/O ports, DC 1.2V 13 USB_D- A MFP0 USB differential signal D-. 14 USB_D+ A MFP0 USB differential signal D+. 15 AVDDUSB A MFP0 Power supply for analog USB, DC 3.3V. 16 USB_REXT A MFP0 12.1 KΩ used internally for USB circuitry. 17 VBAT A MFP0 Power supply by batteries for RTC, DC 3.3V. 18 RTC_RPWR O MFP0 Enable external power control source when active high. 19 RTC_nRWAKE I MFP0 System power enable trigger when active low. 20 PA.8 I/O MFP0 General purpose digital I/O pin. SPIM_SS O MFP1 SPIM slave select pin. I2S_LRCLK I/O MFP2 I2S left right channel clock. UART1_TXD O MFP3 Data transmitter output pin for UART1. PA.9 I/O MFP0 General purpose digital I/O pin. SPIM_CLK O MFP1 SPIM serial clock pin. I2S_BCLK I/O MFP2 I2S bit clock pin. UART1_RXD I MFP3 Data receiver input pin for UART1. SYSCFG[0] I MFP0 System configuration setting bit 0. PA.10 I/O MFP0 General purpose digital I/O pin. SPIM_MOSI I/O MFP1 SPIM MOSI (Master Out, Slave In) pin. 21 22 NUC505 SERIES DATASHEET 10 (Data 0 pin for Quad Mode I/O). 23 I2C1_SCL O MFP2 I2C1 clock pin. SD_CLK O MFP4 SD/SDH mode – clock. SYSCFG[1] I MFP0 System configuration setting bit 1. PA.11 I/O MFP0 General purpose digital I/O pin. SPIM_MISO I/O MFP1 SPIM MISO (Master In, Slave Out) pin. (Data 1 pin for Quad Mode I/O). Aug. 15, 2017 Page 49 of 130 Rev.1.07 NUC505 24 I2C1_SDA I/O MFP2 I2C1 data input/output pin. SD_CMD I MFP4 SD/SDH mode – command/response. PA.12 I/O MFP0 General purpose digital I/O pin. SPIM_D2 I/O MFP1 SPIM data 2 pin for Quad Mode I/O. I MFP2 Timer0 event counter input/toggle output. PA.13 I/O MFP0 General purpose digital I/O pin. SPIM_D3 I/O MFP1 SPIM data 3 pin for Quad Mode I/O. TM0_EXT I MFP2 Timer0 external capture input. SD_nCD I MFP4 SD/SDH mode – card detect. PA.14 I/O MFP0 General purpose digital I/O pin. I2C0_SCL O MFP2 I2C0 clock pin. SD_DAT0 I/O MFP4 SD/SDH mode data line bit 0. PA.15 I/O MFP0 General purpose digital I/O pin. I2C0_SDA I/O MFP2 I2C0 data input/output pin. SD_DAT1 I/O MFP4 SD/SDH mode data line bit 1. TM0_CNT_OUT 25 26 27 NUC505 SERIES DATASHEET 28 VDD A MFP0 Power supply for I/O ports, DC 3.3V. 29 PB.0 I/O MFP0 General purpose digital I/O pin. I2C0_SCL O MFP2 I2C0 clock pin. UART0_TXD O MFP3 Data transmitter output pin for UART0. SD_DAT2 I/O MFP4 SD/SDH mode data line bit 2. PB.1 I/O MFP0 General purpose digital I/O pin. I2C0_SDA I/O MFP2 I2C0 data input/output pin. I MFP3 Data receiver input pin for UART0. SD_DAT3 I/O MFP4 SD/SDH mode data line bit 3. PB.2 I/O MFP0 General purpose digital I/O pin. SPI0_SS O MFP1 SPI0 slave select pin. SD_CMD I MFP4 SD/SDH mode – command/response. 30 UART0_RXD 31 Aug. 15, 2017 Page 50 of 130 Rev.1.07 NUC505 32 33 34 35 36 I/O MFP0 General purpose digital I/O pin. SPI0_CLK O MFP1 SPI0 serial clock pin. SD_CLK O MFP4 SD/SDH mode – clock. SYSCFG[2] I MFP0 System configuration setting bit 2. PB.4 I/O MFP0 General purpose digital I/O pin. SPI0_MOSI O MFP1 SPI0 MOSI (Master Out, Slave In) pin. SYSCFG[3] I MFP0 System configuration setting bit 3. I/O MFP0 General purpose digital I/O pin. SPI0_MISO I MFP1 SPI0 MISO (Master In, Slave Out) pin. SD_nCD I MFP4 SD/SDH mode – card detect. PB.6 I/O MFP0 General purpose digital I/O pin. UART1_TXD O MFP3 Data transmitter output pin for UART1. SD_DAT0 I/O MFP4 SD/SDH mode data line bit 0. PB.7 I/O MFP0 General purpose digital I/O pin. I MFP3 Data receiver input pin for UART1. I/O MFP4 SD/SDH mode data line bit 1. I MFP0 Detects whether USB is plug-in. PB.5 UART1_RXD SD_DAT1 37 USB_VBUS33 38 PB.8 I/O MFP0 General purpose digital I/O pin. USBH_PWEN O MFP1 USB host mode to control an external overcurrent source. TM1_CNT_OUT I/O MFP2 Timer1 event counter input/toggle output. I MFP3 Clear to Send input pin for UART1. SD_DAT2 I/O MFP4 SD/SDH mode data line bit 2. PB.9 I/O MFP0 General purpose digital I/O pin. USBH_OVD I MFP1 USB host bus power over voltage detector. TM1_EXT I MFP2 Timer1 external capture input. UART1_nRTS O MFP3 Request to Send output pin for UART1. SD_DAT3 I/O MFP4 SD/SDH mode data line bit 3. UART1_nCTS 39 Aug. 15, 2017 Page 51 of 130 Rev.1.07 NUC505 SERIES DATASHEET PB.3 NUC505 40 VSS A MFP0 Ground. 41 AVDDHP AP VDD Power supply for analog CODEC headphone, DC 3.3V. 42 LHPOUT A MFP0 Headphone left channel output pin. 43 RHPOUT A MFP0 Headphone right channel output pin. 44 AVSSHP A MFP0 Ground for analog CODEC headphone. 45 VMID A MFP0 Headphone reference power. 46 AVDDCODEC A MFP0 Power supply for analog CODEC, DC 3.3V. 47 AVDDADC A MFP0 Power supply for analog SAR-ADC, DC 3.3V. 48 AVSSADC A MFP0 Ground pin for analog SAR-ADC. 49 PA.0 I/O MFP0 General purpose digital I/O pin. A MFP1 ADC channel 0 analog input. I/O MFP0 General purpose digital I/O pin. A MFP1 ADC channel 1 analog input. I/O MFP0 General purpose digital I/O pin. ADC_CH2 A MFP1 ADC channel 2 analog input. I2S_MCLK O MFP2 I2S master clock output pin. PA.3 I/O MFP0 General purpose digital I/O pin. ADC_CH3 A MFP1 ADC channel 3 analog input. I2S_DI I MFP2 I2S data input. I/O MFP0 General purpose digital I/O pin. ADC_CH4 A MFP1 ADC channel 4 analog input. I2S_DO O MFP2 I2S data output. PA.5 I/O MFP0 General purpose digital I/O pin. A MFP1 ADC channel 5 analog input. I/O MFP0 General purpose digital I/O pin. A MFP1 ADC channel 6 analog input. I/O MFP0 General purpose digital I/O pin. ADC_CH0 50 PA.1 ADC_CH1 51 NUC505 SERIES DATASHEET 52 53 54 PA.2 PA.4 ADC_CH5 55 PA.6 ADC_CH6 56 PA.7 Aug. 15, 2017 Page 52 of 130 Rev.1.07 NUC505 A MFP1 ADC channel 7 analog input. 57 VDD12 A MFP0 Power supply for I/O ports, DC 1.2V 58 PB.10 I/O MFP0 General purpose digital I/O pin. SPI1_SS O MFP1 SPI1 slave select pin. I2C1_SCL O MFP2 I2C1 clock pin. UART2_TXD O MFP3 Data transmitter output pin for UART2. PWM_CH0 I/O MFP4 PWM channel0 output/capture input. PB.11 I/O MFP0 General purpose digital I/O pin. SPI1_CLK O MFP1 SPI1 serial clock pin. I2C1_SDA I/O MFP2 I2C1 data input/output pin. I MFP3 Data receiver input pin for UART2. PWM_CH1 I/O MFP4 PWM channel1 output/capture input. PB.12 I/O MFP0 General purpose digital I/O pin. SPI1_MOSI O MFP1 SPI1 MOSI (Master Out, Slave In) pin. USBH1_D+ I/O MFP2 USB host-lite 1 differential signal D+ I MFP3 Clear to Send input pin for UART2. I/O MFP4 PWM channel2 output/capture input. 59 UART2_RXD 60 UART2_nCTS PWM_CH2 61 VDD A MFP0 Power supply for I/O ports, DC 3.3V. 62 VDD A MFP0 Power supply, DC 3.3V. 63 LDO_CAP A MFP0 LDO output pin. 64 VSS A MFP0 Ground. Aug. 15, 2017 Page 53 of 130 NUC505 SERIES DATASHEET ADC_CH7 Rev.1.07 NUC505 4.3.7 NuMicro® NUC505YO13Y QFN 88-pin Description MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH) PA.0 MFP0 means SYS_GPA_MFPL[2:0]=0x0. PA.9 MFP5 means SYS_GPA_MFPH[6:4]=0x5. Pin No. Pin Name Type MFP Description 1 nRESET I MFP0 External reset input: active LOW, with an internal pull-up. Set this pin low reset to initial state. 2 ICE_CLK O MFP0 Serial wired debugger clock pin. (In ICE mode) PD.0 I/O MFP0 General purpose digital I/O pin. I2C0_SCL O MFP2 I2C0 clock pin. ICE_DAT I/O MFP0 Serial wired debugger data pin. (In ICE mode) PD.1 I/O MFP0 General purpose digital I/O pin. I2C0_SDA I/O MFP2 I2C0 data input/output pin. PB.13 I/O MFP0 General purpose digital I/O pin. SPI1_MISO I MFP1 SPI1 MISO (Master In, Slave Out) pin. USBH1_D- I/O MFP2 USB host-lite 1 differential signal D-. UART2_nRTS O MFP3 Request to Send output pin for UART2. PWM_CH3 I/O MFP4 PWM channel3 output/capture input. PB.14 I/O MFP0 General purpose digital I/O pin. USBH1_D+ I/O MFP1 USB host-lite 1differential signal D+. I2C1_SCL O MFP2 I2C1 clock pin. PB.15 I/O MFP0 General purpose digital I/O pin. USBH1_D- I/O MFP1 USB host-lite 1 differential signal D-. I2C1_SDA I/O MFP2 I2C1 data input/output pin. PC.0 I/O MFP0 General purpose digital I/O pin. I MFP1 SD/SDH mode – command/response. PC.1 I/O MFP0 General purpose digital I/O pin. SD_CLK O MFP1 SD/SDH mode – clock. 3 4 NUC505 SERIES DATASHEET 5 6 7 SD_CMD 8 Aug. 15, 2017 Page 54 of 130 Rev.1.07 NUC505 Pin No. Type MFP Description I/O MFP0 General purpose digital I/O pin. SD_nCD I MFP1 SD/SDH mode – card detect. 10 VDD A MFP0 Power supply for I/O ports, DC 3.3V. 11 PC.3 I/O MFP0 General purpose digital I/O pin. 12 PC.4 I/O MFP0 General purpose digital I/O pin. SD_DAT0 I/O MFP1 SD/SDH mode data line bit 0. PC.5 I/O MFP0 General purpose digital I/O pin. SD_DAT1 I/O MFP1 SD/SDH mode data line bit 1. PC.6 I/O MFP0 General purpose digital I/O pin. SD_DAT2 I/O MFP1 SD/SDH mode data line bit 2. 9 13 14 Pin Name PC.2 VDD12 A MFP0 Power supply for I/O ports, DC 1.2V 16 XT1_IN I MFP0 External 12 MHz (high speed) crystal input pin. 17 XT1_OUT O MFP0 External 12 MHz (high speed) crystal output pin. 18 VDD12 A MFP0 Power supply for I/O ports, DC 1.2V 19 USB_D- A MFP0 USB differential signal D-. 20 USB_D+ A MFP0 USB differential signal D+. 21 AVDDUSB A MFP0 Power supply for analog USB, DC 3.3V. 22 USB_REXT A MFP0 12.1 KΩ used internally for USB circuitry. 23 VBAT A MFP0 Power supply by batteries for RTC, DC 3.3V. 24 RTC_RPWR O MFP0 Enable external power control source when active high. 25 RTC_nRWAKE I MFP0 System power enable trigger when active low. 26 X32_IN I MFP0 External 32.768 kHz (low speed) crystal input pin. 27 X32_OUT O MFP0 External 32.768 kHz (low speed) crystal output pin. 28 PA.8 I/O MFP0 General purpose digital I/O pin. SPIM_SS O MFP1 SPIM slave select pin. I2S_LRCLK I/O MFP2 I2S left right channel clock. Aug. 15, 2017 Page 55 of 130 Rev.1.07 NUC505 SERIES DATASHEET 15 NUC505 Pin No. 29 30 Pin Name Type MFP Description UART1_TXD O MFP3 Data transmitter output pin for UART1. PA.9 I/O MFP0 General purpose digital I/O pin. SPIM_CLK O MFP1 SPIM serial clock pin. I2S_BCLK I/O MFP2 I2S bit clock pin. UART1_RXD I MFP3 Data receiver input pin for UART1. SYSCFG[0] I MFP0 System configuration setting bit 0. PA.10 I/O MFP0 General purpose digital I/O pin. SPIM_MOSI I/O MFP1 SPIM MOSI (Master Out, Slave In) pin. (Data 0 pin for Quad Mode I/O). 31 I2C1_SCL O MFP2 I2C1 clock pin. SD_CLK O MFP4 SD/SDH mode – clock. SYSCFG[1] I MFP0 System configuration setting bit 1. PA.11 I/O MFP0 General purpose digital I/O pin. SPIM_MISO I/O MFP1 SPIM MISO (Master In, Slave Out) pin. (Data 1 pin for Quad Mode I/O). NUC505 SERIES DATASHEET 32 33 34 I2C1_SDA I/O MFP2 I2C1 data input/output pin. SD_CMD I MFP4 SD/SDH mode – command/response. PA.12 I/O MFP0 General purpose digital I/O pin. SPIM_D2 I/O MFP1 SPIM data 2 pin for Quad Mode I/O. TM0_CNT_OUT I/O MFP2 Timer0 event counter input/toggle output. PA.13 I/O MFP0 General purpose digital I/O pin. SPIM_D3 I/O MFP1 SPIM data 3 pin for Quad Mode I/O. TM0_EXT I MFP2 Timer0 external capture input. SD_nCD I MFP4 SD/SDH mode – card detect. PA.14 I/O MFP0 General purpose digital I/O pin. I2C0_SCL O MFP2 I2C0 clock pin. SD_DAT0 I/O MFP4 SD/SDH mode data line bit 0. Aug. 15, 2017 Page 56 of 130 Rev.1.07 NUC505 Pin No. 35 36 37 38 Pin Name Type MFP Description PA.15 I/O MFP0 General purpose digital I/O pin. I2C0_SDA I/O MFP2 I2C0 data input/output pin. SD_DAT1 I/O MFP4 SD/SDH mode data line bit 1. PC.7 I/O MFP0 General purpose digital I/O pin. SD_DAT3 I/O MFP1 SD/SDH mode data line bit 3. PC.8 I/O MFP0 General purpose digital I/O pin. I2S_MCLK O MFP1 I2S master clock output pin. PC.9 I/O MFP0 General purpose digital I/O pin. I MFP1 I2S data input. TM2_CNT_OUT I/O MFP2 Timer2 event counter input/toggle output. PWM_CH0 I/O MFP3 PWM channel0 output/capture input. PC.10 I/O MFP0 General purpose digital I/O pin. I2S_DO O MFP1 I2S data output. TM2_EXT I MFP2 Timer2 external capture input. PWM_CH1 I/O MFP3 PWM channel1 output/capture input. I2S_DI 39 VDD A MFP0 Power supply for I/O ports, DC 3.3V. 41 PB.0 I/O MFP0 General purpose digital I/O pin. I2C0_SCL O MFP2 I2C0 clock pin. UART0_TXD O MFP3 Data transmitter output pin for UART0. SD_DAT2 I/O MFP4 SD/SDH mode data line bit 2. PB.1 I/O MFP0 General purpose digital I/O pin. I2C0_SDA I/O FMP2 I2C0 data input/output pin. I FMP3 Data receiver input pin for UART0. SD_DAT3 I/O MFP4 SD/SDH mode data line bit 3. PB.2 I/O MFP0 General purpose digital I/O pin. SPI0_SS O MFP1 SPI0 slave select pin. 42 UART0_RXD 43 Aug. 15, 2017 Page 57 of 130 NUC505 SERIES DATASHEET 40 Rev.1.07 NUC505 Pin No. 44 45 46 47 48 NUC505 SERIES DATASHEET Pin Name Type MFP Description SD_CMD I MFP4 SD/SDH mode – command/response. PB.3 I/O MFP0 General purpose digital I/O pin. SPI0_CLK O MFP1 SPI0 serial clock pin. SD_CLK O MFP4 SD/SDH mode – clock. SYSCFG[2] I MFP0 System configuration setting bit 2. PB.4 I/O MFP0 General purpose digital I/O pin. SPI0_MOSI O MFP1 SPI0 MOSI (Master Out, Slave In) pin. SYSCFG[3] I MFP0 System configuration setting bit 3. I/O MFP0 General purpose digital I/O pin. SPI0_MISO I MFP1 SPI0 MISO (Master In, Slave Out) pin. SD_nCD I MFP4 SD/SDH mode – card detect. PB.6 I/O MFP0 General purpose digital I/O pin. UART1_TXD O MFP3 Data transmitter output pin for UART1. SD_DAT0 I/O MFP4 SD/SDH mode data line bit 0. PB.7 I/O MFP0 General purpose digital I/O pin. I MFP3 Data receiver input pin for UART1. I/O MFP4 SD/SDH mode data line bit 1. I MFP0 Detects whether USB is plug-in. PB.5 UART1_RXD SD_DAT1 49 USB_VBUS33 50 PB.8 I/O MFP0 General purpose digital I/O pin. USBH_PWEN O MFP1 USB host mode to control an external overcurrent source. TM1_CNT_OUT I/O MFP2 Timer1 event counter input/toggle output. I MFP3 Clear to Send input pin for UART1. SD_DAT2 I/O MFP4 SD/SDH mode data line bit 2. PB.9 I/O MFP0 General purpose digital I/O pin. USBH_VOD I MFP1 USB host bus power over voltage detector. TM1_EXT I MFP2 Timer1 external capture input. UART1_nCTS 51 Aug. 15, 2017 Page 58 of 130 Rev.1.07 NUC505 Pin No. Pin Name Type MFP Description UART1_nRTS O MFP3 Request to Send output pin for UART1. SD_DAT3 I/O MFP4 SD/SDH mode data line bit 3. VDD A MFP0 Power supply for I/O ports, DC 3.3V. 53 AVDDHP A MFP0 Power supply for analog CODEC headphone, DC 3.3V. 54 LHPOUT A MFP0 Headphone left channel output pin. 55 VCMBF A MFP0 Internal CODEC function, keep floating. 56 RHPOUT A MFP0 Headphone right channel output pin. 57 AVSSHP A MFP0 Ground for analog CODEC headphone. 58 VMID A MFP0 Headphone reference power. 59 AVDDCODEC A MFP0 Power supply for analog CODEC, DC 3.3V. 60 MIC0_P A MFP0 Microphone 0 positive input. 61 MIC0_N A MFP0 Microphone 0 negative input. 62 MIC_BIAS A MFP0 CODEC left line-in channel or Microphone bias. 63 VDD12 A MFP0 Power supply for I/O ports, DC 1.2V 64 PD.2 I/O MFP0 General purpose digital I/O pin. A MFP1 Microphone 1 positive input. I/O MFP0 General purpose digital I/O pin. A MFP1 Microphone 1 negative input. I/O MFP0 General purpose digital I/O pin. RLINEIN A MFP1 CODEC right line-in channel. 67 AVDDADC A MFP0 Power supply for analog SAR-ADC, DC 3.3V. 68 AVSSADC A MFP0 Ground pin for analog SAR-ADC. 69 PA.0 I/O MFP0 General purpose digital I/O pin. A MFP1 ADC channel 0 analog input. I/O MFP0 General purpose digital I/O pin. A MFP1 ADC channel 1 analog input. MIC1_P 65 PD.3 MIC1_N 66 PD.4 ADC_CH0 70 PA.1 ADC_CH1 Aug. 15, 2017 Page 59 of 130 NUC505 SERIES DATASHEET 52 Rev.1.07 NUC505 Pin No. Type MFP Description I/O MFP0 General purpose digital I/O pin. ADC_CH2 A MFP1 ADC channel 2 analog input. I2S_MCLK O MFP2 I2S master clock output pin. PA.3 I/O MFP0 General purpose digital I/O pin. ADC_CH3 A MFP1 ADC channel 3 analog input. I2S_DI I MFP2 I2S data input. I/O MFP0 General purpose digital I/O pin. ADC_CH4 A MFP1 ADC channel 4 analog input. I2S_DO O MFP2 I2S data output. PA.5 I/O MFP0 General purpose digital I/O pin. A MFP1 ADC channel 5 analog input. I/O MFP0 General purpose digital I/O pin. A MFP1 ADC channel 6 analog input. I/O MFP0 General purpose digital I/O pin. ADC_CH7 A MFP1 ADC channel 7 analog input. 77 VDD12 A MFP0 Power supply for I/O ports, DC 1.2V 78 PB.10 I/O MFP0 General purpose digital I/O pin. SPI1_SS O MFP1 SPI1 slave select pin. I2C1_SCL O MFP2 I2C1 clock pin. UART2_TXD O MFP3 Data transmitter output pin for UART2. PWM_CH0 I/O MFP4 PWM channel0 output/capture input. PB.11 I/O MFP0 General purpose digital I/O pin. SPI1_CLK O MFP1 SPI1 serial clock pin. I2C1_SDA I/O MFP2 I2C1 data input/output pin. I MFP3 Data receiver input pin for UART2. I/O MFP4 PWM channel1 output/capture input. 71 72 73 74 Pin Name PA.2 PA.4 ADC_CH5 75 PA.6 ADC_CH6 76 NUC505 SERIES DATASHEET 79 PA.7 URAT2_RXD PWM_CH1 Aug. 15, 2017 Page 60 of 130 Rev.1.07 NUC505 Pin No. 80 Pin Name Type MFP Description PB.12 I/O MFP0 General purpose digital I/O pin. SPI1_MOSI O MFP1 SPI1 MOSI (Master Out, Slave In) pin. USBH1_D+ I/O MFP2 USB host-lite 1 differential signal D+. I MFP3 Clear to Send input pin for UART2. I/O MFP4 PWM channel2 output/capture input. A MFP0 Power supply for I/O ports, DC 3.3V. UART2_nCTS PWM_CH2 VDD 82 PC.11 I/O MFP0 General purpose digital I/O pin. I2S_LRCLK I/O MFP1 I2S left right channel clock. TM3_CNT_OUT I/O MFP2 Timer3 event counter input/toggle output. PWM_CH2 I/O MFP3 PWM channel2 output/capture input. PC.12 I/O MFP0 General purpose digital I/O pin. I2S_BCLK I/O MFP1 I2S bit clock pin. TM3_EXT I MFP2 Timer3 external capture input. PWM_CH3 I/O MFP3 PWM channel3 output/capture input. PC.13 I/O MFP0 General purpose digital I/O pin. USBH2_D+ I/O MFP1 USB host-lite 2 differential signal D+. PC.14 I/O MFP0 General purpose digital I/O pin. USBH2_D- I/O MFP1 USB host-lite 2 differential signal D-. 83 84 85 86 VDD A MFP0 Power supply, DC 3.3V. 87 LDO_CAP A MFP0 LDO output pin. 88 VSS A MFP0 Ground. NUC505 SERIES DATASHEET 81 Note: The thermal pad (EPD) on the bottom of QFN package should be connected to GND. Aug. 15, 2017 Page 61 of 130 Rev.1.07 NUC505 4.3.8 Summary GPIO Multi-function Pin Description NUC505 SERIES DATASHEET MPF0 MPF1 MPF2 MPF3 MPF4 Other Driving PA.0 ADC_CH0 2~16mA PA.1 ADC_CH 1 2~16mA PA.2 ADC_CH 2 2~16mA PA.3 ADC_CH 3 2~16mA PA.4 ADC_CH 4 2~16mA PA.5 ADC_CH 5 2~16mA PA.6 ADC_CH 6 2~16mA PA.7 ADC_CH 7 2~16mA PA.8 SPIM_SS I2S_LRCLK UART1_TXD PA.9 SPIM_CLK I2S_BCLK UART1_RXD PA.10 SPIM_MOSI I2C1_SCL SD_CLK PA.11 SPIM_MISO I2C1_SDA SD_CMD PA.12 SPIM_D2 TM0_CNT_OUT PA.13 SPIM_D3 TM0_EXT SD_nCD 8mA PA.14 I2C0_SCL SD_DAT0 4mA PA.15 I2C0_SDA SD_DAT1 4mA PB.0 I2C0_SCL UART0_TXD SD_DAT2 4mA PB.1 I2C0_SDA UART0_RXD SD_DAT3 4mA 4mA 8mA SYSCFG[0] 8mA SYSCFG[1] 8mA 8mA 8mA PB.2 SPI0_SS SD_CMD PB.3 SPI0_CLK SD_CLK PB.4 SPI0_MOSI PB.5 SPI0_MISO SYSCFG[2] 4mA SYSCFG[3] 4mA SD_nCD 4mA PB.6 UART1_TXD SD_DAT0 4mA PB.7 UART1_RXD SD_DAT1 4mA PB.8 USBH_PWEN TM1_CNT_OUT UART1_nCTS SD_DAT2 4mA PB.9 USBH_OVD TM1_EXT UART1_nRTS SD_DAT3 4mA PB.10 SPI1_SS I2C1_SCL UART2_TXD PWM_CH0 4mA PB.11 SPI1_CLK I2C1_SDA UART2_RXD PWM_CH1 4mA PB.12 SPI1_MOSI USBH1_D+ UART2_nCTS PWM_CH2 8mA PB.13 SPI1_MISO USBH1_D- UART2_nRST PWM_CH3 8mA PB.14 USBH1_D+ I2C1_SCL 8mA PB.15 USBH1_D- I2C1_SDA 8mA Aug. 15, 2017 Page 62 of 130 Rev.1.07 NUC505 PC.0 SD_CMD 8mA PC.1 SD_CLK 8mA PC.2 SD_nCD 8mA PC.3 8mA PC.4 SD_DAT0 8mA PC.5 SD_DAT1 8mA PC.6 SD_DAT2 8mA PC.7 SD_DAT3 8mA PC.8 I2S_MCLK 4mA PC.9 I2S_DI TM2_CNT_OUT PWM_CH0 4mA PC.10 I2S_DO TM2_EXT PWM_CH1 4mA PC.11 I2S_LRCLK TM3_CNT_OUT PWM_CH2 4mA PC.12 I2S_BCLK TM3_EXT PWM_CH3 4mA PC.13 USBH2_D+ 8mA PC.14 USBH2_D- 8mA PD.0 I2C0_SCL ICE_CLK 4mA PD.1 I2C0_SDA ICE_DAT 4mA MIC1_P 2~16mA PD.3 MIC1_N 2~16mA PD.4 RLINEIN 2~16mA Aug. 15, 2017 Page 63 of 130 Rev.1.07 NUC505 SERIES DATASHEET PD.2 NUC505 4.3.9 GPIO Multi-function Pin Summary MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH) PA.0 MFP0 means SYS_GPA_MFPL[2:0]=0x0. PA.9 MFP5 means SYS_GPA_MFPH[6:4]=0x5. Group Pin Name GPIO MFP* Type Description ADC_CH0 PA.0 MFP1 A ADC0 analog input. ADC_CH1 PA.1 MFP1 A ADC1 analog input. ADC_CH2 PA.2 MFP1 A ADC2 analog input. ADC_CH3 PA.3 MFP1 A ADC3 analog input. ADC_CH4 PA.4 MFP1 A ADC4 analog input. ADC_CH5 PA.5 MFP1 A ADC5 analog input. ADC_CH6 PA.6 MFP1 A ADC6 analog input. ADC_CH7 PA.7 MFP1 A ADC7 analog input. MIC1_P PD.2 MFP1 A Audio MIC1 analog positive input pin MIC1_N PD.3 MFP1 A Audio MIC1 analog negative input pin RLINEIN PD.4 MFP1 A Audio right line-in analog pin. I2C0_SCL PA.14 MFP2 I/O I2C0 clock pin. I2C0_SCL PB.0 MFP2 I/O I2C0 clock pin. I2C0_SCL PD.0 MFP2 I/O I2C0 clock pin. I2C0_SDA PA.15 MFP2 I/O I2C0 data input/output pin. I2C0_SDA PB.1 MFP2 I/O I2C0 data input/output pin. I2C0_SDA PD.1 MFP2 I/O I2C0 data input/output pin. I2C1_SCL PA.10 MFP2 I/O I2C1 clock pin. I2C1_SCL PB.10 MFP2 I/O I2C1 clock pin. I2C1_SCL PB.14 MFP2 I/O I2C1 clock pin. I2C1_SDA PA.11 MFP2 I/O I2C1 data input/output pin. I2C1_SDA PB.11 MFP2 I/O I2C1 data input/output pin. I2C1_SDA PB.15 MFP2 I/O I2C1 data input/output pin. I2S_MCLK PA.2 MFP2 O I2S master clock output pin. I2S_MCLK PC.8 MFP1 O I2S master clock output pin. I2S_BCLK PA.9 MFP2 I/O I2S bit clock pin. I2S_BCLK PC.12 MFP1 I/O I2S bit clock pin. I2S_LRCLK PA.8 MFP2 I/O I2S left right channel pin. I2S_LRCLK PC.11 MFP1 I/O I2S left right channel pin. ADC CODEC I2C0 NUC505 SERIES DATASHEET I2C1 I2S Aug. 15, 2017 Page 64 of 130 Rev.1.07 NUC505 Group Pin Name GPIO MFP* Type Description I2S_DO PA.4 MFP2 O I2S data output. I2S_DO PC.10 MFP1 O I2S data output. I2S_DI PA.3 MFP2 I I2S data input. I2S_DI PC.9 MFP1 I I2S data input. ICE_CLK PD.0 MFP0 I Serial wired debugger clock pin ICE_DAT PD.1 MFP0 I/O Serial wired debugger data pin PWM_CH0 PB.10 MFP4 I/O PWM output/capture input. PWM_CH0 PC.9 MFP3 I/O PWM output/capture input. PWM_CH1 PB.11 MFP4 I/O PWM output/capture input. PWM_CH1 PC.10 MFP3 I/O PWM output/capture input. PWM_CH2 PB.12 MFP4 I/O PWM output/capture input. PWM_CH2 PC.11 MFP3 I/O PWM output/capture input. PWM_CH3 PB.13 MFP4 I/O PWM output/capture input. PWM_CH3 PC.12 MFP3 I/O PWM output/capture input. SPIM_SS PA.8 MFP1 O SPIM slave select pin. SPIM_CLK PA.9 MFP1 O SPIM serial clock pin. SPIM_MOSI PA.10 MFP1 I/O SPIM MOSI (Master Out, Slave In) pin. SPIM_MISO PA.11 MFP1 I/O SPIM MISO (Master In, Slave Out) pin. SPIM_D2 PA.12 MFP1 I/O SPIM data-2 bit in quad mode. SPIM_D3 PA.13 MFP1 I/O SPIM data-3 bit in quad mode. SPI0_SS PB.2 MFP1 O SPI0 slave select pin. SPI0_CLK PB.3 MFP1 O SPI0 serial clock pin. SPI0_MOSI PB.4 MFP1 I/O SPI0 MOSI (Master Out, Slave In) pin. SPI0_MISO PB.5 MFP1 I/O SPI0 MISO (Master In, Slave Out) pin. SPI1_SS PB.10 MFP1 O SPI1 slave select pin. SPI1_CLK PB.11 MFP1 O SPI1 serial clock pin. SPI1_MOSI PB.12 MFP1 I/O SPI1 MOSI (Master Out, Slave In) pin. SPI1_MISO PB.13 MFP1 I/O SPI1 MISO (Master In, Slave Out) pin. TM0_CNT_OUT PA.12 MFP2 I/O Timer0 event counter input / toggle output. TM0_EXT PA.13 MFP2 I TM1_CNT_OUT PB.8 MFP2 I/O TM1_EXT PB.9 MFP2 I TM2_CNT_OUT PC.9 MFP2 I/O ICE PWM SPIM SPI1 Timer Aug. 15, 2017 Page 65 of 130 Timer0 external counter input Timer1 event counter input / toggle output. Timer1 external counter input Timer2 event counter input / toggle output. Rev.1.07 NUC505 SERIES DATASHEET SPI0 NUC505 Group Pin Name GPIO MFP* Type Description TM2_EXT PC.10 MFP2 I TM3_CNT_OUT PC.11 MFP2 I/O TM3_EXT PC.12 MFP2 I Timer3 external counter input UART0_RXD PB.1 MFP3 I Data receiver input pin for UART0. UART0_TXD PB.0 MFP3 O Data transmitter output pin for UART0. UART1_RXD PA.9 MFP3 I Data receiver input pin for UART1. UART1_RXD PB.7 MFP3 I Data receiver input pin for UART1. UART1_TXD PA.8 MFP3 O Data transmitter output pin for UART1. UART1_TXD PB.6 MFP3 O Data transmitter output pin for UART1. UART1_nCTS PB.8 MFP3 I Clear to Send input pin for UART1. UART1_nRTS PB.9 MFP3 O Request to Send output pin for UART1. UART2_RXD PB.11 MFP3 I Data receiver input pin for UART2. UART2_TXD PB.10 MFP3 O Data transmitter output pin for UART2. UART2_nCTS PB.12 MFP3 I Clear to Send input pin for UART2. UART2_nRTS PB.13 MFP3 O Request to Send output pin for UART2. USBH_PWEN PB.8 MFP1 O USB host to control an external overcurrent source. USBH_VOD PB.9 MFP1 I USB host lite over voltage detector USBH2_D+ PC.13 MFP1 A USB host lite 2 differential signal D+. USBH2_D- PC.14 MFP1 A USB host lite 2 differential signal D-. USBH1_D+ PB.12 MFP2 A USB host lite 1 differential signal D+. USBH1_D+ PB.14 MFP1 A USB host lite 1 differential signal D+. USBH1_D- PB.13 MFP2 A USB host lite 1 differential signal D-. USBH1_D- PB.15 MFP1 A USB host lite 1 differential signal D-. SD_CLK PA.10 MFP4 O SD/SDH mode - clock SD_CLK PB.3 MFP4 O SD/SDH mode – clock SD_CLK PC.1 MFP1 O SD/SDH mode – clock SD_CMD PA.11 MFP4 O SD/SDH mode – command/response SD_CMD PB.2 MFP4 O SD/SDH mode – command/response SD_CMD PC.0 MFP1 O SD/SDH mode – command/response SD_nCD PA.13 MFP4 I SD/SDH mode – card detect. SD_nCD PB.5 MFP4 I SD/SDH mode – card detect. SD_nCD PC.2 MFP1 I SD/SDH mode – card detect. SD_DAT0 PA.14 MFP4 I/O SD/SDH mode data line bit 0. Timer2 external counter input Timer3 event counter input / toggle output. UART0 UART1 UART2 USB Host Lite NUC505 SERIES DATASHEET SDH Aug. 15, 2017 Page 66 of 130 Rev.1.07 NUC505 Group Pin Name GPIO MFP* Type Description SD_DAT0 PB.6 MFP4 I/O SD/SDH mode data line bit 0. SD_DAT0 PC.4 MFP1 I/O SD/SDH mode data line bit 0. SD_DAT1 PA.15 MFP4 I/O SD/SDH mode data line bit 1. SD_DAT1 PB.7 MFP4 I/O SD/SDH mode data line bit 1. SD_DAT1 PC.5 MFP1 I/O SD/SDH mode data line bit 1. SD_DAT2 PB.0 MFP4 I/O SD/SDH mode data line bit 2. SD_DAT2 PB.8 MFP4 I/O SD/SDH mode data line bit 2. SD_DAT2 PC.6 MFP1 I/O SD/SDH mode data line bit 2. SD_DAT3 PB.1 MFP4 I/O SD/SDH mode data line bit 3. SD_DAT3 PB.9 MFP4 I/O SD/SDH mode data line bit 3. SD_DAT3 PC.7 MFP1 I/O SD/SDH mode data line bit 3. Table 4.3-1 NUC505 GPIO Multi-function Table NUC505 SERIES DATASHEET Aug. 15, 2017 Page 67 of 130 Rev.1.07 NUC505 5 BLOCK DIAGRAM 5.1 NuMicro® NUC505 Series Block Diagram Memory ARM Cortex® _M4 (DSP & FPU) 100 MHz Power Control LDO 1.2V SRAM 128 KB POR, LVR, LVD Timer / PWM ADC/AUDIO/OTP 32-bit Timer 4-ch 12-bit ADC with 8-ch RTC (RTC_VDD33) 24-bit Audio Codec Watchdog Timers PWM 4-ch I²S Multi-entry OTP AHB Bus APB Bus Clock Control Connectivity Connectivity System PLL SPIM I²C X 2 Audio PLL SD Host SPI X 2 HS Ext. Crystal Osc. 12 MHz USB 2.0 Full Speed Host UART X 3 LIRC / LS Ext. Crystal Osc. 32.768 kHz USB 2.0 High Speed Device General Purpose I/O ® Figure 5.1-1 NuMicro NUC505 Block Diagram NUC505 SERIES DATASHEET Aug. 15, 2017 Page 68 of 130 Rev.1.07 NUC505 6 6.1 FUNCTIONAL DESCRIPTION ARM® Cortex® -M4 Core ® The Cortex -M4 processor, a configurable, multistage, 32-bit RISC processor, has three AMBA AHB-Lite interfaces for best parallel performance and includes a NVIC component. The processor has optional hardware debug functionality, which can execute Thumb code, and is compatible ® with other Cortex -M profile processors. The profile supports two modes -Thread mode and Handler mode. Handler mode is entered as a result of an exception. An exception return can only be issued in Handler mode. Thread mode is entered on Reset, and can be entered as a result of ® ® an exception return. The Cortex -M4F is a processor with the same capability as the Cortex -M4 processor and includes floating point arithmetic functionality. The NUC505 is embedded with ® ® ® Cortex -M4F processor. Throughout this document the name Cortex -M4 refers to both Cortex ® M4 and Cortex -M4F processors. The following figure shows the functional controller of the processor. NUC505 SERIES DATASHEET ® Figure 6.1-1 Cortex -M4 Block Diagram ® Cortex -M4 processor features:  A low gate count processor core, with low latency interrupt processing that has: ─ Aug. 15, 2017 A subset of the Thumb instruction set, defined in the ARMv7-M Architecture Reference Manual. Page 69 of 130 Rev.1.07 NUC505 ─ Banked Stack Pointer (SP). ─ Hardware integer divide instructions, SDIV and UDIV. ─ Handler and Thread modes. ─ Thumb and Debug states. ─ Support for interruptible-continued instructions LDM, STM, PUSH, and POP for low interrupt latency. ─ Automatic processor state saving and restoration for low latency Interrupt Service Routine (ISR) entry and exit. ─ Support for ARMv6 big-endian byte-invariant or little-endian accesses. ─ Support for ARMv6 unaligned accesses. ®  Floating Point Unit (FPU) in the Cortex -M4F processor providing: ─ 32-bit instructions for single-precision (C float) data-processing operations. ─ Combined Multiply and Accumulate instructions for increased precision (Fused MAC). ─ Hardware support for conversion, addition, subtraction, multiplication with optional accumulate, division, and square-root. ─ Hardware support for denormals and all IEEE rounding modes. ─ 32 dedicated 32-bit single precision registers, also addressable as 16 double-word registers. ─ Decoupled three-stage pipeline.  Nested Vectored Interrupt Controller (NVIC) closely integrated with the processor core to achieve low latency interrupt processing. Features include: NUC505 SERIES DATASHEET ─ External interrupts. Configurable from 1 to 240; the NUC505 has been configured with 32 interrupts. ─ Bits of priority, configurable from bit 3 to bit 7. ─ Dynamic reprioritization of interrupts. ─ Supports priority grouping which enables selection of preempting interrupt levels and non-preempting interrupt levels. ─ Supports tril-chaining and late arrival of interrupts, which enables back-to- back interrupt processing without the overhead of state saving and restoration between interrupts. ─ Processor state automatically saved on interrupt entry, and restored on interrupt exit with on instruction overhead. ─ Supports Wake-up Interrupt Controller (WIC) with Power-down mode.  Memory Protection Unit (MPU). An optional MPU for memory protection, including: ─ Eight memory regions. ─ Sub Region Disable (SRD), enabling efficient use of memory regions. ─ The ability to enable a background region that implements the default memory map attributes.  Low-cost debug solution that features: Aug. 15, 2017 Page 70 of 130 Rev.1.07 NUC505 ─ Debug access to all memory and registers in the system, including access to memory mapped devices, access to internal core registers when the core is halted, and access to debug control registers even while SYSRESETn is asserted. ─ Serial Wire Debug Port (SW-DP) or Serial Wire JTAG Debug Port (SWJ-DP) debug access. But NUC505 only supports SW-DP. ─ Optional Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and code patches. ─ Optional Data Watchpoint and Trace (DWT) unit for implementing watchpoints, data tracing, and system profiling. ─  Bus interfaces: ─ Three Advanced High-performance Bus-Lite (AHB-Lite) interfaces: ICode, Dcode, and System bus interfaces. Private Peripheral Bus (PPB) based on Advanced Peripheral Bus (APB) interface. ─ Bit-band support that includes atomic bit-band write and read operations. ─ Memory access alignment. ─ Write buffer for buffering of write data. ─ Exclusive access transfers for multiprocessor systems. NUC505 SERIES DATASHEET Aug. 15, 2017 Page 71 of 130 Rev.1.07 NUC505 6.2 System Manager 6.2.1 Overview The following functions are included in system manager section  System reset  System memory map  Bus arbitration algorithm  Global control registers  System Timer (Systick)  Nested Vectored Interrupt Control (NVIC)  System control register map and description 6.2.2 System Reset  Hardware Reset ─ Power-on Reset (POR) ─ Low level on the nRESET Pin (nRST) ─ Watchdog time-out reset (WDT) ─ Low voltage reset (LVR)  Software Reset ─ SYSRESETREQ (AIRCR[2]) ─ CPU Reset (SYS_IPRST0[0]) ─ CHIPRST (SYS_IPRST0 [1]) NUC505 SERIES DATASHEET Note1: SYSRESETREQ (AIRCR[2]) reset the whole chip including all peripherals, but does not reset SPIM function, vector map module parameter setting, and PA.8~PA.15 multi-function setting. Note2: CPU Rest (SYS_IPRST0[0]) only resets the CPU function. Note3: CHIPRST (SYS_IPRST0[1]) reset the whole chip including all peripherals. Aug. 15, 2017 Page 72 of 130 Rev.1.07 NUC505 6.2.3 System Power-on Setting The power-on setting is used to configure the chip to enter the specified state when the chip is powered up or reset. Since each pin of power-on setting has an internal pulled-up resistor during reset period, if the application needs to set the configuration to “0”, the proper pull-down must be added for the corresponding configuration pins. PB.4 PB.3 PA.10 PA.9 Description Register Mapping 1 1 1 1 Boot from Internal MCP SPI Flash SYS_BOOTSET[3:0] 1 1 1 0 Boot from USB SYS_BOOTSET[3:0] 1 1 0 1 Boot from External SPI Flash SYS_BOOTSET[3:0] 1 0 1 1 Boot from ICP Mode SYS_BOOTSET[3:0] 0 1 1 1 SWD/ICE Mode with Internal SPI Flash SYS_BOOTSET[3:0] 0 1 1 0 SWD/ICE Mode with External SPI Flash SYS_BOOTSET[3:0] Table 6.2-1 System Power-on Setting Guide 6.2.4 System Power Distribution In this chip, power distribution is divided into five segments: Audio CODEC power from AVDDCODEC, AVDDHP, and AVSSHP provides the power for audio CODEC operation.  Analog-to-Digital converter (ADC) power from AVDDADC and AVSSADC provides the power for ADC operation.  Digital power from VDD and VSS supplies the power to the internal regulator which provides a fixed 1.2 V power for digital operation and I/O pins.  USB transceiver power from AVDDUSB offers the power for operating the USB transceiver.  RTC power from VBAT provides the power for RTC and 80 bytes backup registers. The outputs of internal voltage regulators, LDO and VDD, require an external capacitor which should be located close to the corresponding pin. Analog power (AVDDCODEC and AVDDADC) should be the same voltage level of the digital power (VDD). The following figure shows the power ® distribution of the NuMicro NUC505. Aug. 15, 2017 Page 73 of 130 Rev.1.07 NUC505 SERIES DATASHEET  X32_OUT X32_IN VBAT AVSSADC AVDDADC NUC505 32.768 kHz crystal oscillator 3.3V 3.3V AVDDCODEC USB Transceiver 12-bit ADC 24-bit Audio CODEC AVDDHP 32 bytes backup register RTC 3.3V AVSSHP USB_D+ USB_D- AVDDUSB 3.3V 1.2V LDO_CAP 4.7uF PLL XT1_OUT 12 MHz crystal oscillator XT1_IN POR12 SRAM 3.3V à 1.2V LDO POR33 Power On Control Digital Logic IO Cell GPIO 3.3V NUC505 power distribution VSS Low Voltage Reset VDD NUC505 SERIES DATASHEET Low Voltage Detector ® Figure 6.2-1 NuMicro NUC505 Power Distribution Diagram 6.2.5 System Memory Mapping The NUC505 provides a 4G-byte address space for programmers. The memory locations assigned to each on-chip modules are shown in Table 6.2-2. The detailed registers and memory addressing or programming will be described in the following sections for individual on-chip modules. The NUC505 only supports little-endian data format. Address Space Token Modules IBR_BA Internal Boot ROM (IBR) Memory Space Memory Space 0x1FFF_0000 – 0x1FFF_7FFF Aug. 15, 2017 Page 74 of 130 Rev.1.07 NUC505 0x2000_0000 – 0x2000_7FFF SRAM1_BA SRAM1 Memory Space (32K Bytes) 0x2000_8000 – 0x2000_FFFF SRAM2_BA SRAM2 Memory Space (32K Bytes) 0x2001_0000 – 0x2001_7FFF SRAM3_BA SRAM3 Memory Space (32K Bytes) 0x2001_8000 – 0x2001_FFFF SRAM4_BA SRAM4 Memory Space (32K Bytes) 0x0000_0000 – 0x0FFF_FFFF FLASH_BA SPI Flash/ROM Memory Space AHB Controllers Space (0x4000_0000 ~0x4000FFFF) 0x4000_0000 – 0x4000_01FF GCR_BA Global Control Registers 0x4000_0200 – 0x4000_02FF CLK_BA Clock Control Registers 0x4000_7000 – 0x4000_7FFF SPIM_BA SPIM Control Register 0x4000_9000 – 0x4000_9FFF USBD_BA USB Device Controller Registers 0x4000_A000 – 0x4000_AFFF SDH_BA SDH Control Register 0x4000_B000 – 0x4000_BFFF USBH_BA USB Host Controller Registers APB Controllers Space (0x400E_0000~0x400E_FFFF) SPI1_BA SPI1 Master/Slave Controller Registers (SPI1) 0x400E_2000 – 0x400E_2FFF ADC_BA ADC Controller Registers 0x400E_3000 – 0x400E_3FFF GPIO_BA GPIO Controller Registers 0x400E_4000 – 0x400E_4FFF I2C0_BA I2C0 Interface Control Registers 0x400E_5000 – 0x400E_5FFF I2C1_BA I2C1 Interface Control Registers 0x400E_6000 – 0x400E_6FFF PWM_BA PWM Controller Registers 0x400E_7000 – 0x400E_7FFF RTC_BA Real Time Clock (RTC) Control Register 0x400E_8000 – 0x400E_8FFF I2S_BA Inter-IC Sound (I2S) Control Register 0x400E_9000 – 0x400E_9FFF SPI0_BA SPI0 Master/Slave Controller Registers (SPI0) 0x400E_A000 – 0x400E_AFFF Timer01_BA Timer0/Timer1 Control Registers 0x400E_B000 – 0x400E_BFFF Timer23_BA Timer2/Timer3 Control Registers 0x400E_C000 – 0x400E_CFFF UART0_BA UART0 Control Registers (Normal Speed) 0x400E_D000 – 0x400E_DFFF UART1_BA UART1 Control Registers (High Speed) 0x400E_E000 – 0x400E_EFFF UART2_BA UART2 Control Registers (High Speed) 0x400E_F000 – 0x400E_FFFF WDT_BA WDT Interface Control Registers NUC505 SERIES DATASHEET 0x400E_1000 – 0x400E_1FFF System Controllers Space (0xE000_E000 ~ 0xE000_EFFF) 0xE000_E010 – 0xE000_E0FF SCS_BA System Timer Control Registers 0xE000_E100 – 0xE000_ECFF SCS_BA External Interrupt Controller Control Registers 0xE000_ED00 – 0xE000_ED8F SCS_BA System Control Registers Table 6.2-2 Address Space Assignments for On-Chip Controllers Aug. 15, 2017 Page 75 of 130 Rev.1.07 NUC505 6.2.6 SRAM Memory Organization The NUC505 supports embedded SRAM with a total of 128 Kbytes and the SRAM organization is separated to four banks: SRAM bank0, SRAM bank1, SRAM bank2, and SRAM bank3. Each of these four banks has 32 Kbytes address space and can be accessed simultaneously. Supports a total of 128 Kbytes SRAM  Supports byte / half word / word write  Supports fixed 32 Kbytes SRAM banks for independent access  Supports remap address to 0x1FF0_0000  Supports remap arbitrary memory block of 128 Kbytes SRAM to 0x0000_0000 by using vector map module AHB Bus  NUC505 SERIES DATASHEET AHB interface controller SRAM decoder SRAM bank0 AHB interface controller SRAM decoder SRAM bank1 AHB interface controller SRAM decoder SRAM bank2 AHB interface controller SRAM decoder SRAM bank3 Figure 6.2-2 SRAM Block Diagram Figure 6.2-3 shows the SRAM organization of NUC505. There are four SRAM banks in NUC505 and each bank is addressed to 32 Kbytes. The bank0 address space is from 0x2000_0000 to 0x2000_7FFF. The bank1 address space is from 0x2000_8000 to 0x2000_FFFF. The bank2 address space is from 0x2001_0000 to 0x2001_7FFF. The bank3 address space is from 0x2001_8000 to 0x2001_FFFF. The address of each bank is remapping from 0x2000_0000 to 0x1FF0_0000. CPU can access SRAM bank0 through 0x2000_0000 to 0x2000_7FFF or 0x1FF0_0000 to 0x1FF0_7FFF, SRAM bank1 through 0x2000_8000 to 0x2000_FFFF or 0x1FF0_8000 to 0x1FF0_FFFF, SRAM bank2 through 0x2001_0000 to 0x2001_7FFF or 0x1FF1_0000 to 0x1FF1_7FFF, and SRAM bank3 through 0x2001_8000 to 0x2001_FFFF or 0x1FF1_8000 to 0x1FF1_FFFF. Aug. 15, 2017 Page 76 of 130 Rev.1.07 NUC505 0x3FFF_FFFF 512MB Reserved 0x2002_0000 0x2001_FFFF 0x1FF1_FFFF 32K byte SRAM bank3 0x2001_8000 0x2001_7FFF 0x1FF1_8000 0x1FF1_7FFF 32K byte SRAM bank2 32K byte SRAM bank2 remapping 0x1FF1_0000 0x1FF0_FFFF 32K byte SRAM bank1 32K byte SRAM bank1 remapping 0x2000_8000 0x2000_7FFF NUC505 SERIES DATASHEET 0x2001_0000 0x2000_FFFF 0x2000_0000 32K byte SRAM bank3 remapping 0x1FF0_8000 0x1FF0_7FFF 32K byte SRAM bank0 remapping 0x1FF0_0000 128K byte device 32K byte SRAM bank0 128K byte device Figure 6.2-3 SRAM Memory Organization Figure 6.2-4 shows the vector map module diagram. Arbitrary memory block in 128 Kbytes SRAM can be remapped to the SPI flash block and its start address is 0x0000_0000. The location and size with the memory block are controlled by the register SYS_RVMPADDR[31:0] and the register SYS_RVMPLEN[31:24]. The SYS_RVMPADDR indicates the start address of the memory block and SYS_RVMPLEN describes about the size of the memory block (the unit is 1 Kbyte). Aug. 15, 2017 Page 77 of 130 Rev.1.07 NUC505 0x001F_FFFF Example: SYS_RVMPADDR[31:0] = 0x2000_AB00 SYS_RVMPLEN[31:24] = 0x02 SPI Flash 0x2000_B2FF 2 Kbytes Vector mapping 0x0000_0800 0x0000_07FF 128KB SRAM 2MB 0x2001_FFFF 0x2000_AB00 2 Kbytes 0x0000_0000 0x2000_0000 Figure 6.2-4 Vector Map Module Block 6.2.7 AHB Bus Arbitration NUC505 SERIES DATASHEET The internal bus of NUC505 is an AHB-Compliant Bus and supports to connect with the standard AHB master or slave. The NUC505 AHB arbiter provides a choice of two arbitration algorithms for simultaneous requests. These two arbitration algorithms are the Fixed-priority mode and the Roundrobin- priority (rotate) mode. The selection of modes and types is determined in the PRISEL field of the SYS_AHBCTL control register. 6.2.7.1 Fixed Priority Mode Fixed priority mode is selected if PRISEL = 0. The order of priorities on the AHB mastership among the on-chip master modules are listed in Table 6.2-3. Priority Sequence AHB Bus Priority (PRISEL = 0) Aug. 15, 2017 1 (Lowest) Cortex-M4 I 2 Cortex-M4 D 3 Cortex-M4 System 4 SPIM 5 USBD Page 78 of 130 Rev.1.07 NUC505 6 USBH 6 SDH 8 (Highest) I2S Table 6.2-3 AHB Bus Priority Order in Fixed Priority Mode If two or more master modules request to access AHB bus at the same time, the higher priority request will get the permission to access AHB bus. Priority Sequence AHB Bus Priority (PRISEL = 0) 1 (Lowest) Cortex-M4 I 2 Cortex-M4 D 3 Cortex-M4 System 4 SPIM 5 USBD 6 USBH 6 SDH 8 (Highest) I2S Table 6.2-3 AHB Bus Priority Order in Fixed Priority Mode The programmer can recover the original priority order by directly writing “1” to clear the PRISTS bit. For example, this can be done that at the end of an interrupt service routine. Note that PRISTS only can be automatically set to 1 by an external interrupt when CPUHPRI = 1. It will not take effect for a programmer to directly write 1 to PRISTS to raise ARM core’s AHB priority. 6.2.7.2 Round Robin Priority Mode Round-robin priority mode is selected if PRISEL = 1. The AHB bus arbiter uses a round robin arbitration scheme for every master module to gain the bus ownership in turn. That is the requestor having the highest priority becomes the lowest-priority requestor after it has been granted access. 6.2.7.3 Rotate rule Example 2 In the default sequence of AHB Master Bus, the priority is I S>SDH > USBH > USBD >SPIM >M4(S) > M4(D) > M4(I). Aug. 15, 2017 Page 79 of 130 Rev.1.07 NUC505 SERIES DATASHEET The SPI flash controller normally has the lowest priority (except CPU interface) under the fixed priority mode. The NUC505 provides a mechanism to raise the priority of CPU request to the highest. If the CPUHPRI bit (bit-4 of SYS_AHBCTL control register) is set to 1, the PRISTS bit (bit-5 of SYS_AHBCTL control register) will be automatically set to 1 while an unmasked external IRQ occurs. Under this circumstance, the ARM core will become the highest priority to access AHB bus. NUC505 6.2.8 System Timer (Systick) ® The Cortex -M4 includes an integrated system timer, SysTick, which provides a simple, 24-bit clearon-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used as a Real Time Operating System (RTOS) tick timer or as a simple counter. When system timer is enabled, it will count down from the value in the SysTick Current Value Register (SYST_CVR) to zero, and reload (wrap) to the value in the SysTick Reload Value Register (SYST_RVR) on the next clock cycle, and then decrement on subsequent clocks. When the counter transitions to zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads. The SYST_CVR value is UNKNOWN on reset. Software should write to the register to clear it to zero before enabling the feature. This ensures the timer will count from the SYST_RVR value rather than an arbitrary value when it is enabled. If the SYST_RVR is zero, the timer will be maintained with a current value of zero after it is reloaded with this value. This mechanism can be used to disable the feature independently from the timer enable bit. ® ® For more detailed information, please refer to the “ARM Cortex -M4 Technical Reference Manual” ® and “ARM v6-M Architecture Reference Manual”. NUC505 SERIES DATASHEET Aug. 15, 2017 Page 80 of 130 Rev.1.07 NUC505 6.2.9 Nested Vectored Interrupt Control (NVIC) The NVIC and the processor core interface are closely coupled to enable low latency interrupt processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge of the stacked, or nested, interrupts to enable tail-chaining of interrupts. Users can only fully access the NVIC from privileged mode, but this may cause interrupts to enter a pending state in user mode if enabling the Configuration and Control Register. Any other user mode access causes a bus fault. Users can access all NVIC registers using byte, halfword, and word accesses unless otherwise stated. NVIC registers are located within the SCS (System Control Space). All NVIC registers and system debug registers are little-endian regardless of the endianness state of the processor.  An implementation-defined number of interrupts, in the range 1-240 interrupts.  A programmable priority level of 0-16 for each interrupts. A higher level corresponds to a lower priority, so level 0 is the highest interrupt priority.  Level and pulse detection of interrupt signals.  Dynamic reprioritization of interrupts.  Grouping of priority values into group priority and subpriority fields.  Interrupt tail-chaining.  An external Non Maskable Interrupt (NMI)  WIC, providing Power-down mode support. The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no instruction overhead. This provides low latency exception handling. 6.2.9.1 Exception Model and System Interrupt Map The following table lists the exception model supported by NUC505 series. Software can set 16 levels of priority on some of these exceptions as well as on all interrupts. The highest user-configurable priority is denoted as “0x00” and the lowest priority is denoted as “0xF0” (The 4-LSB always 0). The default priority of all the user-configurable interrupts is “0x00”. Note that priority “0” is treated as the fourth priority on the system, after three system exceptions “Reset”, “NMI” and “Hard Fault”. The vector table contains the initialization value for the stack pointer on reset, and the entry point addresses for all exception handlers. The vector number on previous page defines the order of entries in the vector table associated with exception handler entry as illustrated in previous section. Aug. 15, 2017 Page 81 of 130 Rev.1.07 NUC505 SERIES DATASHEET When any interrupts is accepted, the processor will automatically fetch the starting address of the interrupt service routine (ISR) from a vector table in memory. On system reset, the vector table is fixed at address 0x00000000. Privileged software can write to the VTOR to relocate the vector table start address to a different memory location, in the range 0x00000080 to 0x3FFFFF80, NUC505 Exception Type Vector Number Vector Address Priority Reset 1 0x00000004 -3 NMI 2 0x00000008 -2 Hard Fault 3 0x0000000C -1 Memory Manager Fault 4 0x00000010 Configurable Bus Fault 5 0x00000014 Configurable Usage Fault 6 0x00000018 Configurable Reserved 7 ~ 10 SVCall 11 0x0000002C Configurable Debug Monitor 12 0x00000030 Configurable Reserved 13 PendSV 14 0x00000038 Configurable SysTick 15 0x0000003C Configurable Interrupt (IRQ0 ~ IRQ31) 16 ~ 47 Reserved Reserved 0x00000000 + (Vector Number)*4 Configurable Table 6.2-4 Exception Model Vector Number Interrupt Number Interrupt Name Interrupt Description (Bit in Interrupt Registers) NUC505 SERIES DATASHEET 0 ~ 15 - - System exceptions 16 0 PWR_INT Power On Interrupt 17 1 WDT_INT Watch Dog Timer interrupt 18 2 Reserved Reserved 19 3 I2S_INT I2S interrupt 20 4 EINT0_INT External GPIO Group 0 interrupt 21 5 EINT1_INT External GPIO Group 1 interrupt 22 6 EINT2_INT External GPIO Group 2 interrupt 23 7 EINT3_INT External GPIO Group 3 interrupt 24 8 SPIM_INT SPIM interrupt 25 9 USBD_INT USB Device 20 interrupt 26 10 TM0_INT Timer0 interrupt 27 11 TM1_INT Timer1 interrupt 28 12 TM2_INT Timer2 interrupt Aug. 15, 2017 Page 82 of 130 Rev.1.07 NUC505 29 13 TM3_INT Timer3 interrupt 30 14 SDH_INT SDH interrupt 31 15 PWM0_INT PWM0 interrupt 32 16 PWM1_INT PWM1 interrupt 33 17 PWM2_INT PWM2 interrupt 34 18 PWM3_INT PWM3 interrupt 35 19 RTC_INT Real Time Clock interrupt 36 20 SPI0_INT SPI0 interrupt 37 21 I2C1_INT I2C1 interrupt 38 22 I2C0_INT I2C0 interrupt 39 23 UART0_INT UART0 interrupt 40 24 UART1_INT UART1 interrupt 41 25 ADC_INT ADC interrupt 42 26 wwdt_INT Window Watch Dog Timer interrupt 43 27 USBH_INT USB Host 1.1 interrupt 44 28 UART2_INT UART2 interrupt 45 29 LVD_INT Low Voltage Detection interrupt 46 30 SPI1_INT SPI1 interrupt 47 31 Reserved Reserved Table 6.2-5 Interrupt Number Table NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-Enable or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-1-to-clear policy, both registers reading back the current enabled state of the corresponding interrupts. When an interrupt is disabled, interrupt assertion will cause the interrupt to become Pending, however, the interrupt will not activate. If an interrupt is Active when it is disabled, it remains in its Active state until cleared by reset or an exception return. Clearing the enable bit prevents new activations of the associated interrupt. NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used to enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers reading back the current pended state of the corresponding interrupts. The Clear-Pending Register has no effect on the execution status of an Active interrupt. NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register supporting four interrupts, and each interrupt uses MSB 4 bits of the 8-bit field). The general registers associated with the NVIC are all accessible from a block of memory in the System Control Space and will be described in next section. Aug. 15, 2017 Page 83 of 130 Rev.1.07 NUC505 SERIES DATASHEET 6.2.9.2 Operation Description NUC505 6.3 Clock Controller 6.3.1 Overview The clock controller generates clocks for the whole chip. The clocks include AHB, APB and engine clocks for all of devices like USB device, USB host, UART and so on. There are two PLL clocks, PLL and APLL, derived from external HXT clock input. The PLL clock allows the processor to operate at a high internal clock frequency. Also, the APLL is used to generate more accuracy frequency for audio CODEC. They also implement the power control function, include the individually clock on or off control register, clock source selector and divider. These functions minimize the extra power consumption and the chip runs on the just right condition. In Powerdown mode, the controller turns off the crystal oscillator to minimize the chip power consumption. NUC505 SERIES DATASHEET Aug. 15, 2017 Page 84 of 130 Rev.1.07 NUC505 6.3.2 Clock Diagram PLL_FOUT 12 MHz External 32.768 kHz 12 MHz CPUCLK CPU HCLK SRAM01 SPIM 1 0 1/(SYSCLK_N+1) SRAM23 CLKDIV0[7] Internal 32.768 kHz 1/(PCLKDIV_N+1) 12 MHz I2C0 I2C1 Internal 32.768 kHz 12 MHz PCLK PLL_FOUT APLL_FOUT External 32.768 kHz 1 RTC_32K RTC 1/(SDHDIV+1) SDHC 0 RTC_CLKSRC[0] PLL_FOUT PLL_FOUT 1/(USBHDIV+1) USBH 12MHz 1 0 CLKDIV1[30] PLL_FOUT 12MHz CPUCLK 1 1/(USBDDIV+1) USBD 0 12MHz 1 SysTick 1/(STICKDIV+1) SYST_CSR[2] CLKDIV0[23] PLL_FOUT 12MHz PLL_FOUT 1 1/(SPI0_CLKDIV+1) SPI0 0 12MHz PLL_FOUT 1 1/(SPI1_CLKDIV+1) SPI1 0 PLL_FOUT 12MHz 1/(ADCDIV+1) ADC 1/(UART0DIV+1) UART0 1/(UART1DIV+1) UART1 1/(UART2DIV+1) UART2 1/(TMR3DIV+1) TMR 3 0 12MHz 1 0 PLL_FOUT 11 10 01 12MHz 1/(I2SDIV+1) I2S 1 0 CLKDIV3[12] 00 PLL_FOUT 12MHz CLKDIV2[25:24] 1 0 CLKDIV3[20] RTC_32K 12MHz 1 1/(TMR0DIV+1) TMR0 0 RTC_32K 12MHz CLKDIV4[24] 1 0 CLKDIV5[24] RTC_32K 12MHz 1 1/(TMR1DIV+1) TMR1 0 RTC_32K 12MHz CLKDIV4[25] 1 1/(WDGCLK_N+1) WDT 1/(PWMDIV+1) PWM 0 CLKDIV5[25] RTC_32K 12MHz 1 0 1/(TMR2DIV+1) TMR2 PLL_FOUT 12MHz CLKDIV4[26] 1 0 CLKDIV5[26] Figure 6.3-1 Clock Generator Global View Diagram Aug. 15, 2017 Page 85 of 130 Rev.1.07 NUC505 SERIES DATASHEET Reserved 1 CLKDIV3[4] CLKDIV2[29] APLL_FOUT 12MHz CLKDIV1[28] CLKDIV2[28] PLL_FOUT 0 NUC505 6.3.3 Clock Generator The clock generator consists of 4 clock sources, which are listed below:  Real-time clock (RTC_CLK) source can be selected from external 32.768 kHz external low speed crystal oscillator (LXT) or 32.768 kHz internal low speed RC oscillator (LIRC)  12 MHz external high speed crystal oscillator (HXT)  Programmable System PLL output clock frequency (PLL_FOUT)  Programmable Audio PLL output clock frequency (APLL_FOUT) Internal 32.768 kHz Oscillator (LIRC) RTC_CLKSRC[0] LIRC LXT RTC_CLK 1 0 X32_IN External 32.768 kHz Crystal (LXT) X32_OUT HXTEN (CLK_PWRCTL[0]) HXT XT1_IN NUC505 SERIES DATASHEET External 12 MHz Crystal (HXT) XT1_OUT PLL APLL PLL_FOUT APLL_FOUT Figure 6.3-2 Clock Generator Block Diagram The external crystal oscillator and two capacitors are connected to the pad “XT1_IN / X32_IN” and pad “XT1_OUT / X32_OUT”. The capacitance value of the two capacitors may be changed for differential crystal oscillator from different vender. The load capacitance values and resistance values must be adjusted according to the selected oscillator. The recommended load capacitance values and resistance values as Crystal Oscillator Aug. 15, 2017 Capacitance Values Page 86 of 130 Resistance Values Rev.1.07 NUC505 12 MHz 20pF 1 MΩ 32.768 kHz 33pF 10 MΩ Table 6.3-1 Recommended Load Capacitance Values and Resistance Values. BOARD C1 CHIP XT_IN / X32_IN crystal External Crystal R CLOCK_OUT C2 XT_OUT / X32_OUT Figure 6.3-3 Crystal Oscillator Circuit 6.3.4 Power-down Mode Clock When entering Power-down mode, system clocks, some clock sources and some peripheral clocks are disabled. Some clock sources and peripherals clock are still active in Power-down mode. The clocks which still keep active are listed below:  Clock Generator 32.768 kHz internal low speed RC oscillator (LIRC) clock  32.768 kHz external low speed crystal oscillator (LXT) clock In Power-down mode, If the woke-up even occurred, the disabled clocks will be regenerated after PDWKPSC (CLK_PWRCTL[23:8]) x 256 HXT cycle. Aug. 15, 2017 Page 87 of 130 Rev.1.07 NUC505 SERIES DATASHEET  NUC505 6.4 General Purpose I/O (GPIO) 6.4.1 Overview The NUC505 series has up to 52 General Purpose I/O pins to be shared with other function pins depending on the chip configuration. The 52 pins are arranged in 4 ports named as PA, PB, PC, and PD. PA and PB have 16 pins on port, PC has 15 pins on port, and PD has 5 pins on port. Each of the 52 pins is independent and has the corresponding register bits to control the pin mode function and data. The I/O type of each I/O pins can be configured by software individually as Input or Push-pull output mode. After the chip is reset, the I/O mode of all pins is input mode with no pull-up and pull-down enable (except PB.2, it is pull-up enable). Each I/O pin has an individual pull-up and pull-down resistor which is about 40 k ~ 50 k for VDD and Vss. User can set Px_PUEN to control I/O pins to pull-up or pull-down. PIN[n] (Px_PIN) PULLSEL[0] (Px_PUEN) DOUT[n] (Px_DOUT) PAD MODE[n] (Px_MODE) NUC505 SERIES DATASHEET PULLSEL[1] (Px_PUEN) Note: Px_ means PA_, PB_, PC_, or PD_ Figure 6.4-1 I/O Pin Block Diagram 6.4.2  Features Two I/O modes:  Push-Pull Output mode  Input only with high impendence mode  CMOS/Schmitt trigger input selectable (refers SYS_GPAIBE register on TRM)  I/O pin can be configured as interrupt source with edge setting Aug. 15, 2017 Page 88 of 130 Rev.1.07 NUC505  I/O pin has individual internal pull-up resistor and pull-down resistor  Enabling the pin interrupt function will also enable the wake-up function NUC505 SERIES DATASHEET Aug. 15, 2017 Page 89 of 130 Rev.1.07 NUC505 6.5 Timer Controller (TIMER) 6.5.1 Overview The Timer Controller includes four 32-bit timers, TIMER0 ~ TIMER3, allowing user to easily implement a timer control for applications. The timer can perform functions, such as frequency measurement, delay timing, clock generation, and event counting by external input pins, and interval measurement by external capture pins. 6.5.2 Features  Four sets of 32-bit timers with 24-bit up counter and one 8-bit prescale counter  Independent clock source for each timer  Provides One-shot, Periodic, Toggle and Continuous Counting operation modes  Time-out period = (Period of timer clock input) * (8-bit prescale counter+1) * CMPDAT (TIMERx_CMP[23:0])  Maximum counting cycle time = (1 / T MHz) * (2 ) * (2 ), T is the period of timer clock  24-bit up counter value is readable through TIMERx_CNT (Timer Data Register)  Supports event counting function to count the event from external pin (TM0_CNT_OUT~TM3_CNT_OUT)  Supports external capture pin (TM0_EXT~TM3_EXT) for interval measurement  Supports external capture pin (TM0_EXT~TM3_EXT) to reset 24-bit up counter  Supports chip wake-up from Idle mode, Power-down mode and Deep Power-down mode, if a timer interrupt signal is generated. 8 24 NUC505 SERIES DATASHEET Aug. 15, 2017 Page 90 of 130 Rev.1.07 NUC505 6.6 PWM Generator and Capture Timer (PWM) 6.6.1 Overview The NUC505 series has one PWM generator that can support four channels PWM output or four channels input capture sharing the same pins (PWM_CH0/ PWM_CH1/PWM_CH2/PWM_CH3). The PWM generator has a 16-bit PWM counter and comparator, and the PWM generator supports two standard PWM output modes: Independent output mode and Complementary output mode with 8-bit Dead-time generator. Each mode can be used as a timer and issues interrupt independently. In addition, It also has an 8-bit prescaler and clock divider with 5 divided frequencies (1, 1/2, 1/4, 1/8, 1/16) to support wide range clock frequency of PWM counter. For PWM output control unit, it supports polarity output function. The PWM generator also supports input capture function. It supports latch PWM counter value to corresponding register when input channel has a rising transition, falling transition or both transition is happened. After the capture feature is enabled, the capture always latches PWM-counter to RCAPDATn when input channel has a rising transition and latched PWM-counter to FCAPDATn when input channel has a falling transition. Capture channel 0 interrupt is programmable by setting CRLIEN0 (PWM_CAPCTL01[1]) (Rising latch Interrupt enable) and CFLIEN0 (PWM_CAPCTL01[2]) (Falling latch Interrupt enable) to determine the condition of interrupt occur. Capture channel 1 has the same feature by setting CRLIEN1 (PWM_CAPCTL01[17]) and CFLIEN1 (PWM_CAPCTL01[18]). The capture channel 2 & 3 has the same feature by setting CRLIEN2 (PWM_CAPCTL23[1]),CFLIEN2 (PWM_CAPCTL23[2]) and CRLIEN3 (PWM_CAPCTL23[17]), CFLIEN3 (PWM_CAPCTL23[18]) respectively. Whenever Capture issues Interrupt 0/1/2/3, the PWM counter 0/1/2/3 will be reload at this moment. There are only four interrupts from PWM. PWM 0 and Capture 0 share the same interrupt; PWM 1 and Capture 1 share the same interrupt and so on. Therefore, PWM function and Capture function in the same channel cannot be used at the same time. 6.6.2.1 Features NUC505 SERIES DATASHEET 6.6.2 PWM function features  Supports 4 PWM output channels with 16-bit resolution  Supports 8-bit prescaler and clock divider  Supports 4 PWM interrupts  Supports One-shot or Auto-reload PWM counter operation mode  Supports 8-bit Dead-time 6.6.2.2 Capture function features  Supports 4 capture input channels with 16-bit resolution  Supports rising or falling capture condition  Supports 4 Capture interrupts Aug. 15, 2017 Page 91 of 130 Rev.1.07 NUC505 6.7 Watchdog Timer (WDT) 6.7.1 Overview The Watchdog Timer is used to perform a system reset when system runs into an unknown state. This prevents system from hanging for an infinite period of time. Besides, the Watchdog Timer supports the function to wake up system from Power-down mode. 6.7.2 Features  18-bit free running up counter for Watchdog Timer time-out interval.  Selectable time-out interval (2 ~ 2 ) WDT_CLK cycle and the time-out interval period is 32.5 ms ~ 8.224 s if WDT_CLK = 32 kHz.  System kept in reset state for a period of (1 / WDT_CLK) * 63  Supports selectable Watchdog Timer reset delay period, including 1026、130 、18 or 3 WDT_CLK reset delay period.  Supports Watchdog Timer time-out wake-up function when Watchdog Timer clock source is selected as 32 kHz low-speed oscillator. 6.8 4 18 Window Watchdog Timer (WWDT) 6.8.1 Overview The Window Watchdog Timer is used to perform a system reset within a specified window period to prevent software run to uncontrollable status by any unpredictable condition. NUC505 SERIES DATASHEET 6.8.2 Features  6-bit down counter CNTDAT (WWDT_CNT[5:0]) and 6-bit compare value CMPDAT (WWDT_CTL[21:16]) to make the window period flexible  Selectable maximum 11-bit WWDT clock prescale PSCSEL (WWDT_CTL[11:8]) to make WWDT time-out interval variable Aug. 15, 2017 Page 92 of 130 Rev.1.07 NUC505 6.9 Real Time Clock (RTC) 6.9.1 Overview The Real Time Clock (RTC) block can be operated by independent power supply while the system power is off. The RTC uses a 32.768 kHz external crystal (LXT) or internal oscillator (LIRC), and offers programmable time tick and alarm match interrupts. The data format of time and calendar messages are expressed in BCD format. A digital frequency compensation feature is available to compensate the frequency accuracy of external crystal oscillator (LXT) or internal oscillator (LIRC). The RTC controller also offers 32 bytes spare registers to store user’s important information. The wake-up signal is used to wake the system from Idle mode, Power-down mode and Deep Power-down mode. 6.9.2 Features Supports real time counter in RTC_TIME (hour, minute, second) and calendar counter in RTC_CAL (year, month, day) for RTC time and calendar check  Supports alarm time (hour, minute, second) and calendar (year, month, day) settings in RTC_TALM and RTC_CALM  Selectable 12-hour or 24-hour time scale in RTC_CLKFMT register  Supports Leap Year indication in RTC_LEAPYEAR register  Supports Day of the Week counter in RTC_WEEKDAY register  Frequency of RTC clock source compensate by RTC_FREQADJ register  All time and calendar message expressed in BCD format  Supports periodic RTC Time Tick interrupt with 8 period interval options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second  Supports RTC Time Tick and Alarm Match interrupt  Supports chip wake-up from Idle mode, Power-down mode and Deep Power-down mode while a RTC interrupt signal is generated  Supports 32 bytes spare registers and these registers values are preserved when RTC power domain is existed Aug. 15, 2017 Page 93 of 130 Rev.1.07 NUC505 SERIES DATASHEET  NUC505 6.10 UART Interface Controller (UART) 6.10.1 Overview The NUC505 series provides three channels of Universal Asynchronous Receiver/Transmitters (UART). The UART Controller performs a serial-to-parallel conversion on data received from the peripheral and a parallel-to-serial conversion on data transmitted from the CPU. Each UART Controller channel supports ten types of interrupts. The UART controller also supports IrDA SIR, RS-485, auto-flow control function and auto-baud rate measuring function. 6.10.2 Features  Full-duplex asynchronous communications  Separates receive and transmit 16/16(UART0) / 64/64(UART1 and UART2) bytes entry FIFO for data payloads  Supports hardware auto-flow control ( nCTS and nRTS) with UART1 and UART2  Programmable receiver buffer trigger level  Supports programmable baud rate generator for each channel individually  Supports nCTS and data wake-up function  Supports 8-bit receiver buffer time-out detection function  Programmable transmitting data delay time between the last stop and the next start bit by setting DLY (UART_TOUT [15:8])  Supports Auto-Baud Rate measurement  Supports break error, frame error, parity error and receive/transmit buffer overflow detection function  Fully programmable serial-interface features NUC505 SERIES DATASHEET   Programmable number of data bit, 5-, 6-, 7-, 8- bit character  Programmable parity bit, even, odd, no parity or stick parity bit generation and detection  Programmable stop bit, 1, 1.5, or 2 stop bit generation Supports IrDA SIR function mode    Supports for 3/16 bit duration for normal mode Supports LIN function mode (Only UART1 /UART2 with LIN function)  Supports LIN Master/Slave mode  Supports programmable break generation function for transmitter  Supports break detection function for receiver Supports RS-485 function mode  Supports RS-485 9-bit mode  Supports hardware or software enables to program nRTS pin to control RS-485 transmission direction Aug. 15, 2017 Page 94 of 130 Rev.1.07 NUC505 6.11 I2C Serial Interface Controller (Master/Slave) 6.11.1 Overview I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. The I2C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously. Data is transferred between a Master and a Slave synchronously to SCL on the SDA line on a byte-by-byte basis. Each data byte is 8-bit long. There is one SCL clock pulse for each data bit with the MSB being transmitted first. An acknowledge bit follows each transferred byte. Each bit is sampled during the high period of SCL; therefore, the SDA line may be changed only during the low period of SCL and must be held stable during the high period of SCL. A transition on the SDA line while SCL is high is interpreted as a command (START or STOP). Please refer to the following figure for more details about I2C Bus Timing. STOP Repeated START START STOP SDA SCL Figure 6.11-1 I2C Bus Timing Aug. 15, 2017 Page 95 of 130 Rev.1.07 NUC505 SERIES DATASHEET The device on-chip I2C logic provides the serial interface that meets the I2C bus standard mode specification. The I2C port handles byte transfers autonomously. To enable this port, the bit I2CEN (I2C_CTL[6]) should be set to '1'. The I2C H/W interfaces to the I2C bus via two pins: SDA and SCL. Pull up resistor is needed for I2C operation as these are open drain pins. When the I/O pins are used as I2C port, user must set the pins function to I2C in advance. NUC505 6.11.2 Features The NUC505 series provides two channels of I2C. The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to the bus. The main features of the bus include:  Master/Slave mode and General Call Mode  Bidirectional data transfer between masters and slaves  Multi-master bus  Arbitration between simultaneously transmitting masters without corruption of serial data on the bus  Serial clock synchronization allows devices with different bit rates to communicate via one serial bus  Serial clock synchronization can be used as a handshake mechanism to stretch and un-stretch serial transfer  Built-in a 14-bit time-out counter will request the I2C interrupt if the I2C bus hangs up and time-out counter overflows.  Programmable divider allowing for versatile rate control  Supports 7-bit addressing mode  Supports multiple address recognition (four slave addresses with mask option)  Supports address match wake-up function NUC505 SERIES DATASHEET Aug. 15, 2017 Page 96 of 130 Rev.1.07 NUC505 6.12 Serial Peripheral Interface (SPI) 6.12.1 Overview The Serial Peripheral Interface (SPI) is a synchronous serial data communication protocol that operates in full duplex mode. Devices communicate in Master/Slave mode with the 4-wire bidirection interface. The NUC505 series contains one set of SPI controller performing a serial-toparallel conversion on data received from a peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device. Also, the SPI controller can be configured as a master or a slave device. 6.12.2 Features  Supports Master or Slave mode operation  Configurable bit length of a transfer word from 8 to 32-bit  Provides separate 8-level depth transmit and receive FIFO buffers  Supports MSB first or LSB first transfer sequence  Supports byte reorder function  Supports Byte or Word Suspend mode  Supports 3-wire, no slave select signal, bi-direction interface  Up to 2 sets of SPI controllers NUC505 SERIES DATASHEET Aug. 15, 2017 Page 97 of 130 Rev.1.07 NUC505 6.13 SPI Memory Interface Controller (SPIM) 6.13.1 Overview The SPI Memory Interface Controller performs a serial-to-parallel conversion on data received from the peripheral, and a parallel-to-serial conversion on data received from CPU. This controller can drive up to 2 external peripherals (embedded SPI Flash or external SPI Flash) and act as a SPI master. It can generate an interrupt signal when data transfer is finished and can be cleared by writing 1 to the interrupt flag. The active level of device/slave select signal can be chosen to low active or high active, which depends on the peripheral. Writing a divisor into the SPIM_CTL1 register can program the frequency of serial clock output to the peripheral. This controller contains four 32-bit transmit/receive buffers, and can provide 1 to 4 burst mode operation. The number of bits in each transaction can be 8, 16, 24, or 32; data can be transmitted/received up to four successive transactions in one transfer. 6.13.2 Features  Supports SPI master mode  Supports DMA mode (DMA Write and DMA Read), Direct Memory Map (DMM) mode, and I/O mode  8-, 16-, 24-, and 32-bit length of transaction  Supports standard (1-bit), dual (2-bit), and quad (4-bit) I/O transfer mode  Provides burst mode operation, which can transmit/receive data up to four successive transactions in one transfer  Two slave/device select lines (embedded SPI Flash or external SPI Flash)  Fully static synchronous design with one clock domain NUC505 SERIES DATASHEET Aug. 15, 2017 Page 98 of 130 Rev.1.07 NUC505 6.14 I2S Controller with Internal Audio CODEC (I2S) 6.14.1 Overview 2 2 The I S controller consists of I S protocol interface to internal audio CODEC and supports to use 2 external audio CODEC. The I S controller includes two 16 words FIFO for transfer path and receiver path respectively and is capable of handling 8, 16, 24, or 32 bits word sizes sample. The structure of internal audio CODEC is a delta-sigma 24-bit CODEC with microphone input, audio line-in input, and headphone output. 6.14.2 Features 2 I S Controller  Supports Master mode and Slave mode  Capable of handling 8-, 16-, 24- and 32-bit word sizes sample  Supports Mono and Stereo audio data  Supports I2S and most significant bit (MSB) justified data format  Supports PCM-A and PCM-B data format  Provides two 16 words FIFO, one for transmitting and the other for receiving  Generates interrupt requests when FIFO levels cross a programmable boundary  Supports TX DMA function for transmitting and RX DMA function receiving  Supports RX Data Power Measurement  Supports connecting to external audio CODEC Aug. 15, 2017 Page 99 of 130 Rev.1.07 NUC505 SERIES DATASHEET Internal CODEC  Supports mono microphone input and stereo audio line-in input  Supports stereo headphone output  Supports stereo and mono mode  Features of ADC ─ Total-Harmonic-Distortion with Noise (THD+N): -80 dB ─ Dynamic-Range (DR) and Signal-to-Noise ratio (SNR): 90 dB (A-Weighted)  Features of DAC (headphone out with 32Ω loading) ─ Total-Harmonic-Distortion with Noise (THD+N): -60 dB ─ Dynamic-Range (DR) and Signal-to-Noise ratio (SNR): 93 dB (A-Weighted)  Supports sampling rate with 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, and 96 kHz NUC505 6.15 USB 2.0 Device Controller (USBD) 6.15.1 Overview The USB device controller interfaces the AHB bus and the UTMI bus. The USB controller contains both the AHB master interface and AHB slave interface. CPU programs the USB controller registers through the AHB slave interface. For IN or OUT transfer, the USB device controller needs to write data to memory or read data from memory through the AHB master interface. The USB device controller is complaint with USB 2.0 specification and it contains 12 configurable endpoints in addition to control endpoint. These endpoints could be configured to BULK, INTERRUPT or ISO. The USB device controller has a built-in DMA to relieve the load of CPU. 6.15.2 Features  USB Specification reversion 2.0 compliant  Supports 12 configurable endpoints in addition to Control Endpoint  Each of the endpoints can be Isochronous, Bulk or Interrupt and either IN or OUT direction  Three different operation modes of an in-endpoint － Auto Validation mode, Manual Validation mode, Fly mode  Supports DMA operation  2048 Bytes Configurable RAM used as endpoint buffer  Supports Endpoint Maximum Packet Size up to 1024 bytes NUC505 SERIES DATASHEET Aug. 15, 2017 Page 100 of 130 Rev.1.07 NUC505 6.16 USB 1.1 Host Controller (USBH) 6.16.1 Overview The NUC505 series is equipped with one USB 1.1 Host Controller (USBH) that supports Open Host Controller Interface (OpenHCI, OHCI) Specification and register-level description of a host controller to manage the devices and data transfer of Universal Serial Bus (USB). The USBH supports an integrated Root Hub with a USB port, a DMA for real-time data transfer between system memory and USB bus, port power control and port overcurrent detection. The USBH is responsible for detecting the connect and disconnect of USB devices, managing data transfer, collecting status and activity of USB bus, providing power control and detecting overcurrent of attached USB devices. 6.16.2 Features  Supports Universal Serial Bus (USB) Specification Revision 1.1.  Supports Open Host Controller Interface (OpenHCI) Specification Revision 1.0.  Supports both full-speed (12Mbps) and low-speed (1.5Mbps) USB devices.  Supports Control, Bulk, Interrupt and Isochronous transfers.  Supports an integrated Root Hub.  Supports one USB host port in LQFP48 or LQFP64 and two USB host ports in QFN88  Supports port power control and port overcurrent detection.  Supports DMA for real-time data transfer. NUC505 SERIES DATASHEET Aug. 15, 2017 Page 101 of 130 Rev.1.07 NUC505 6.17 Secure-Digital Host Controller (SDHC) 6.17.1 Overview The Secure-Digital Host Controller (SDH Controller) includes a DMAC (Direct Memory Access Controller) unit and a SD unit. The DMAC unit provides a DMA (Direct Memory Access) function for SD to exchange data between system memory and shared buffer (128 bytes), and the SD unit controls the interface of SD/SDHC/MMC. The SD HOST controller can support SD/SDHC/MMC with DMAC to provide a fast data transfer between system memory and cards. 6.17.2 Features  Supports single DMA channel.  Supports hardware Scatter-Gather function.  Using single 128 Bytes shared buffer for data exchange between system memory and cards.  Interface with DMAC for register read/write and data transfer.  Supports SD/SDHC/MMC card.  The frequency of HCLK should be higher than the frequency of peripheral clock. NUC505 SERIES DATASHEET Aug. 15, 2017 Page 102 of 130 Rev.1.07 NUC505 6.18 12-bit Analog-to-Digital Converter (ADC) 6.18.1 Overview The NUC505 series contains one 12-bit successive approximation analog-to-digital converter (ADC) with 8 single-end external input channels (ADC_CH0, ADC_CH1, … ADC_CH7). The ADC_CH0 has an internal 10 kΩ resistor divider for battery detection. The ADC_CH2 also supports key pad comparator function. User can control the A/D conversion by setting the SWTRG (ADC_CTL[0]). 6.18.2 Features  Analog input voltage range: 0~AVDDADC.  12-bit resolution and 10-bit accuracy guaranteed.  Up to 8 single-end analog input channels.  ADC clock frequency up to 16 MHz.  Up to 1 MSPS conversion rate when using in ADC_CH1 channel.  Up to 200 kSPS conversion rate when using in ADC_CH2, …ADC_CH7 channels.  Configurable ADC internal sampling time.  Supports key pad comparator (ADC_CH2).  Built-in 10 kΩ resistor divider for battery detection (ADC_CH0). NUC505 SERIES DATASHEET Aug. 15, 2017 Page 103 of 130 Rev.1.07 NUC505 7 ELECTRICAL CHARACTERISTICS 7.1 Absolute Maximum Ratings Symbol VDD  VSS VIN Parameter Max Unit -0.3 +4.0 V VSS - 0.3 VDD + 0.3 V 12 MHz DC Power Supply Input Voltage 1/tCLCL Min Oscillator Frequency TA Operating Temperature -40 +85 TST Storage Temperature -55 +150 ℃ IDD Maximum Current into VDD - 160 mA ISS Maximum Current out of VSS 160 mA Maximum Current sunk by a I/O pin I/O pin[*2, 3, 4] mA Maximum Current sourced by a I/O pin I/O pin[*2, 3, 4] mA Maximum Current sunk by total I/O pins 100 mA Maximum Current sourced by total I/O pins 100 mA IIO Note: 1. 2. 3. NUC505 SERIES DATASHEET 4. Exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the lift and reliability of the device. 4mA: PA.14, PA.15, PB.0, PB.1, PB.2, PB.3, PB.4, PB.5, PB.6, PB.7, PB.8, PB.9, PB.10, PB.11, PC.8, PC.9, PC.10, PC.11, PC.12, PD.0, PD.1 8mA: PA.8, PA.9, PA.10, PA.11, PA.12, PA.13, PB.12, PB.13, PB.14, PB.15, PC.0, PC.1, PC.2, PC.3, PC.4, PC.5, PC.6, PC.7, PC.13, PC.14 Can setting strength for 2mA, 6.5mA, 8.7mA, 13mA, 15.2mA, 19.5mA, 21.7mA, 26.1mA: PA.0, PA.1, PA.2, PA.3, PA.4, PA.5, PA.6, PA.7, PD.2, PD.3, PD.4 Aug. 15, 2017 Page 104 of 130 Rev.1.07 NUC505 7.2 DC Characteristics (VDD - VSS = 3 ~ 3.6 V, TA = 25C) SPECIFICATION SYMBOL PARAMETER TEST CONDITIONS MIN. MAX. 3 3.3 3.6 V Power Ground -0.3 - - V VDD12 Core Logic and I/O Buffer Pre-Driver Voltage 1.08 1.2 1.32 V VBAT RTC Power Supply 2 - 3.6 V IBAT_EX External crystal RTC Supply Current - 4 - uA IBAT_IN Internal RC RTC Supply Current 0.1 0.6 0.9 uA FINT_RC Internal RC frequency 15 32 90 Khz VOH High Level Output Voltage 2.4 - - V VOL Low Level Output Voltage - - 0.4 V VIH Input High Voltage 2.0 - - V VIL Input Low Voltage - - 0.8 V 1.05 1.2 V Schmitt-falling-trigger Switch Threshold 0.87 VTH 1.65 1.9 2.1 V Schmitt-rising-trigger 32 53 120 kΩ VIN = Vss VDD VSS AVSS RPU Aug. 15, 2017 Operation Voltage Input Pull-up Resist Page 105 of 130 UNIT NUC505 SERIES DATASHEET TYP. Rev.1.07 NUC505 SPECIFICATION SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT RPD Input Pull-down Resistance 37 49 120 kΩ IL Input Leakage Current -10 - 10 uA IOZ Tri-State Output Leakage Current -10 - 10 uA IOL1 4 - - mA IOL2 8 - - mA IOL3 2、6.5、 8.7、 13、 15.2、 19.5、 21.7、 26.1 - - mA IOH1 4 - - mA IOH2 8 - - mA Low level sink current [*1] High level source current [*2] IOH3 NUC505 SERIES DATASHEET 2、6.5、 8.7、 13、 15.2、 19.5、 21.7、 26.1 VIN = VDD VOL = 0.4V VOH = 2.4V - - mA HXT - IDD1 18.83 LXT 12Mhz - All digital 96Mhz module PLL Code ✔ ✕ ✔ ✕ SPI ✔ ✕ ✔ ✔ SPI ✔ ✕ ✔ ✕ RAM ✔ ✕ ✔ ✔ RAM - 27.33 - - 25.38 - - 32.13 - - 4.53 ✔ ✕ ✕ ✕ SPI - 6.47 ✔ ✕ ✕ ✔ SPI IDD7 5.23 ✔ ✕ ✕ ✕ RAM IDD8 5.94 ✔ ✕ ✕ ✔ RAM IDD2 IDD3 IDD4 IDD5 IDD6 Aug. 15, 2017 VDD= 3.3V, Operating current Normal Run Mode while(1){} executed from SPI flash or RAM Page 106 of 130 mA Rev.1.07 NUC505 SPECIFICATION SYMBOL PARAMETER TEST CONDITIONS MIN. VDD= 3.3V, Operating Current Idle Mode at 12 MHz IIDLE1 IIDLE2 VDD =3.3V, Standby current Power-down (Deep Sleep)mode IPWD - TYP. 17 MAX. UNIT HXT RTC PLL All digital module ✔ ✕ ✕ ✔ ✔ ✕ ✕ ✕ HXT RTC PLL RAM retention ✕ ✕ ✕ ✔ mA - 12.3 - 700 - - uA Note: 1. 2. 3. 4mA: PA.14, PA.15, PB.0, PB.1, PB.2, PB.3, PB.4, PB.5, PB.6, PB.7, PB.8, PB.9, PB.10, PB.11, PC.8, PC.9, PC.10, PC.11, PC.12, PD.0, PD.1 8mA: PA.8, PA.9, PA.10, PA.11, PA.12, PA.13, PB.12, PB.13, PB.14, PB.15, PC.0, PC.1, PC.2, PC.3, PC.4, PC.5, PC.6, PC.7, PC.13, PC.14 Can setting strength for 2mA, 6.5mA, 8.7mA, 13mA, 15.2mA, 19.5mA, 21.7mA, 26.1mA: PA.0, PA.1, PA.2, PA.3, PA.4, PA.5, PA.6, PA.7, PD.2, PD.3, PD.4 NUC505 SERIES DATASHEET Aug. 15, 2017 Page 107 of 130 Rev.1.07 NUC505 7.3 AC Electrical Characteristics 7.3.1 External 12 MHz Crystal t CLCL t CLCH t CLCX tCHCL t CHCX Note: Duty cycle is 50%. PARAMETER SYMBOL MIN. TYP. MAX. UNITS Clock High Time tCHCX - 41.6 - nS Clock Low Time tCLCX - 41.6 - nS Clock Rise Time tCLCH - - 25 nS Clock Fall Time tCHCL - - 25 nS 7.3.2 External 12 MHz High Speed Oscillator NUC505 SERIES DATASHEET SYMBOL PARAMETER CONDITION fHXT Input clock frequency External crystal for XIN TA Temperature - VHXT VDD - IHXT Operating current 12 MHz@ VDD = 3.3V 7.3.3 CONDITIO N MIN. TYP. MAX. 12 -40 - MHz 85 3.3 - 3 UNIT ℃ V - mA Typical Crystal Application Circuits Crystal Oscillator Capacitance Values Resistance Values 12 MHz 20pF 1 MΩ 32.768 kHz 33pF 10 MΩ Aug. 15, 2017 Page 108 of 130 Rev.1.07 NUC505 20p XT1_IN 1M 20p XT1_OUT 12 MHz crystal 33p XT32_IN 10M 33p 32.768 Khz crystal XT32_OUT Figure 7.3-1 Typical Crystal Application Circuit 7.3.4 Internal 32 kHz Low Speed Oscillator PARAMETER CONDITION MIN. TYP. MAX. UNIT Supply voltage - 3 - 3.6 V Center Frequency - - 32 - kHz Operating current VDD =3.3V - 0.5 - uA NUC505 SERIES DATASHEET Aug. 15, 2017 Page 109 of 130 Rev.1.07 NUC505 7.4 Analog Characteristics 7.4.1 Specifications of 12-bit SARADC SPECIFICATIONS Symbol PARAMETER AVDD_ADC Operating Voltage TEST CONDITIONS MIN TYP MAX UNIT 2.7 3.3 3.6 V RADC Resolution - - 12 bit VREF Reference Voltage 2 - AVDD_ADC V VIN ADC input Voltage 0 - VREF V RIN Analog input impedance 2 MΩ ADC Clock = 16MHz - FSPS - 1M Hz ADC Clock = 3.2MHz Sampling Rate - - 200k Hz NUC505 SERIES DATASHEET EQ Gain Error (Transfer Gain ) - -2 -4 LSB EA Absolute Error - 3 - LSB INL Integral Non-linearity Error - ±3 - LSB DNL Differential Non-linearity Error -1 - +1.5 LSB ±1 ±3 LSB EO SNR - Free Running Conversion(ADC_CH1) Offset Error S/N - 62 - dB Total Harmonic Distortion - 62 - dB Free Running Conversion(ADC_CH2, ADC_CH3, ADC_CH4, ADC_CH5, ADC_CH6, ADC_CH7) Note: 1. 2. The performance measurement is in ADC only condition (all other module are in reset statue). Design by guarantee, no test in production. Aug. 15, 2017 Page 110 of 130 Rev.1.07 NUC505 EF (Full scale error) = EO + EG Gain Error EG Offset Error EO 4095 4094 4093 4092 Ideal transfer curve 7 6 ADC output code 5 Actual transfer curve 4 3 2 DNL 1 1 LSB Offset Error EO Analog input voltage (LSB) 4095 Aug. 15, 2017 Page 111 of 130 Rev.1.07 NUC505 SERIES DATASHEET Note: The INL is the peak difference between the transition point of the steps of the calibrated transfer curve and the ideal transfer curve. A calibrated transfer curve means it has calibrated the offset and gain error from the actual transfer curve. NUC505 7.4.2 Specifications of 24-bit Delta-Sigma CODEC Specifications Symbol Parameter Test Conditions Min. Typ Max. Unit - V - V Reference VMID - 0.5*AVDD_CO DEC Microphone Bias 0.75*AVDD_C Bias Voltage - Maximum Output Current - - 3 mA Capacitive Load - - 50 pF Resolution - 24 - Bit THD Total Harmonic Distortion - -80 -70 dB DR Dynamic Range 80 90 - dB S/N 80 90 - dB Channel Separation - 100 - dB Channel Matching - 0.2 - dB Full Scale Output Voltage - 0.93*AVDD_C ODEC/3.3 - Vrms Input Impedance 10 - - kΩ - 10 - pF ODEC Line Input SNR NUC505 SERIES DATASHEET VFS Input Capacitor -60dB input, A-Weighted Headphone Output THD Total Harmonic Distortion - -80 - dB THD Total Harmonic Distortion - -60 - dB SNR S/N 90 93 - dB RL = 0 Ω, Po = 10mW RL = 32 Ω, Po = 10mW A-Weighted Power Supply Current (No PLL, No Loading) AVDD_CODEC - 8 - mA AVDD_HP - 4 - mA Aug. 15, 2017 Page 112 of 130 Rev.1.07 NUC505 Note: The performance measurement is in CODEC only condition (All other module are in reset statue). 7.4.3 Specification of LDO Symbol Parameter Min. Typ Max. Unit VDD Input Voltage 1.62 3.3 3.6 V VLDO Output Voltage -10% 1.2 +10% V -40 25 85 - 4.7 - TA Temperature ECAP External Capacitor Note AVDD_LDO input voltage μF Notes: 1. It is recommended a 0.1μF bypass capacitor is connected between VDD and the closest VSS pin of the device. 2. For ensuring power stability, a 4.7μF or higher capacitor must be connected between LDO_CAP pin and the closest VSS pin of the device. NUC505 SERIES DATASHEET Aug. 15, 2017 Page 113 of 130 Rev.1.07 NUC505 7.4.4 Specification of Low Voltage Reset Test Condition Symbol Parameter Min. Typ Max. Unit VDD Supply Voltage 0 - 3.6 V TA Temperature -40 25 85 ILVR Quiescent Current - 25 40 uA VDD=3.3V VLVR Threshold Voltage 2.16 2.4 2.64 V TA=-45 ~ 85 Unit Test Condition VDD>Reset voltage 7.4.5 Specifications of Power-on Reset Symbol TA Parameter Min. Typ Max. Temperature -40 25 85 - 33 50 uA NUC505 SERIES DATASHEET IPOR Quiescent Current VPOR Reset Voltage 1.6 2 2.4 V VPOR VDD Start Voltage to Ensure Poweron Reset - - 100 mV RPVDD VDD Raising Rate to Ensure Power-on Reset 0.025 - - V/ms tPOR Minimum Time for VDD Stays at VPOR to Ensure Poweron Reset 0.5 - - ms Aug. 15, 2017 Page 114 of 130 TA=-40 ~ 85 Rev.1.07 NUC505 VDD tPOR RRVDD VPOR Time Figure 7.4-1 Power-up Ramp Condition NUC505 SERIES DATASHEET Aug. 15, 2017 Page 115 of 130 Rev.1.07 NUC505 7.4.6 USB PHY Specifications 7.4.6.1 USB DC Electrical Characteristics Symbol Parameter Min. Typ Max. Unit 2.0 - - V - - 0.8 V USB_DP-USB_DM 0.2 - - V Includes VDI range 0.8 - 2.5 V 0.8 - 2.0 V Receiver hysteresis - 400 - mV VOL Output low (driven) 0 - 0.3 V VOH Output high (driven) 2.8 - 3.6 V VCRS Output signal cross voltage 1.3 - 2.0 V RPU Pull-up resistor 1.425 - 1.575 kΩ VTRM Pull-down resistor 14.25 - 15.75 kΩ ZDRV Termination Voltage for upstream port pull up (RPU) 3.0 - 3.6 V 28 - 49.5 Ω - - 20 pF VIH Input high (driven) VIL Input low VDI Differential input sensitivity Differential VCM VSE common-mode range Conditions Single-ended receiver threshold NUC505 SERIES DATASHEET CIN Driver output resistance Steady state drive* VIH Transceiver capacitance Pin to VSS Note: Driver output resistance does not include series resistor resistance. Aug. 15, 2017 Page 116 of 130 Rev.1.07 NUC505 7.4.6.2 USB Full-Speed Driver Electrical Characteristics Symbol Parameter Conditions Min. Typ Max. Unit TFR Rising time CL = 50p 4 - 20 ns TFF Falling time CL = 50p 4 - 20 ns Rising and falling time matching TFRFF = TFR / TFF 90 - 111.11 % Min. Typ Max. Unit TFRFF 7.4.6.3 USB High-Speed Driver Electrical Characteristics Symbol Parameter Conditions TFR Rising time CL = 5p 500 ns TFF Falling time CL = 5p 500 ns Rising and falling time matching TFRFF = TFR / TFF 90 TFRFF 111 % NUC505 SERIES DATASHEET Aug. 15, 2017 Page 117 of 130 Rev.1.07 NUC505 I2C Dynamic Characteristics 7.4.7 Standard Mode[1][2] Symbol Fast Mode[1][2] Parameter Min. Max. Min. Max. Unit tLOW SCL low period 4.7 - 1.2 - uS tHIGH SCL high period 4 - 0.6 - uS 4.7 - 1.2 - uS tSU; STA Repeated START setup time tHD; STA START condition hold time 4 - 0.6 - uS tSU; STO STOP condition setup time 4 - 0.6 - uS 4.7[3] - 1.2[3] - uS tBUF condition Bus free time tSU;DAT Data setup time 250 - 100 - nS tHD;DAT Data hold time 0[4] 3.45[5] 0[4] 0.8[5] uS tr SCL/SDA rise time - 1000 20+0.1Cb 300 nS tf SCL/SDA fall time - 300 - 300 nS Capacitive load for each bus line - 400 - 400 pF Cb Notes: 1. 2. NUC505 SERIES DATASHEET 3. 4. 5. Guaranteed by design, not tested in production. 2 HCLK must be higher than 2 MHz to achieve the maximum standard mode I C frequency. It must be 2 higher than 8 MHz to achieve the maximum fast mode I C frequency. 2 I C controller must be retriggered immediately at slave mode after receiving STOP condition. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of SCL signal. STOP Repeated START START STOP SDA tBUF tLOW tr SCL tHD;STA tf tHIGH tHD;DAT tSU;DAT tSU;STA tSU;STO 2 Figure 7.4-2 I C Timing Diagram Aug. 15, 2017 Page 118 of 130 Rev.1.07 NUC505 7.4.8 SPI Dynamic Characteristics Symbol Parameter Min. Typ. Max. Unit SPI Master Mode (VDD = 3.0 V ~ 3.6 V, 0 pF loading Capacitor) tDS Data setup time 0 - - ns tDH Data hold time 4.5 - - ns tV Data output valid time - 2 4 ns SPI Slave Mode (VDD = 3.0 V ~ 3.6 V, 0 pF loading Capacitor) tDS Data setup time 0 - - ns tDH Data hold time 4.5 - - ns tV Data output valid time - 18 24 ns CLKP=0 SPICLK CLKP=1 tV MOSI Data Valid Data Valid tDS MISO Data Valid CLKP=0, TX_NEG=1, RX_NEG=0 or CLKP=1, TX_NEG=0, RX_NEG=1 tDH Data Valid Data Valid MOSI tDS MISO Data Valid CLKP=0, TX_NEG=0, RX_NEG=1 or CLKP=1, TX_NEG=1, RX_NEG=0 tDH Data Valid Data Valid Figure 7.4-3 SPI Master Mode Timing Diagram Aug. 15, 2017 Page 119 of 130 Rev.1.07 NUC505 SERIES DATASHEET tV NUC505 CLKP=0 SPICLK CLKP=1 tDS MOSI Data Valid tDH Data Valid CLKP=0, TX_NEG=1, RX_NEG=0 or CLKP=1, TX_NEG=0, RX_NEG=1 tv MISO Data Valid tDS MOSI Data Valid tDH Data Valid Data Valid Data Valid Data Valid tv MISO CLKP=0, TX_NEG=0, RX_NEG=1 or CLKP=1, TX_NEG=1, RX_NEG=0 Figure 7.4-4 SPI Slave Mode Timing Diagram NUC505 SERIES DATASHEET Aug. 15, 2017 Page 120 of 130 Rev.1.07 NUC505 7.4.9 I2S Dynamic Characteristics Symbol th(WS) Parameter I2S clock high time Min. Max. 42 - Unit Test Conditions Master fPCLK = 12.288 MHz, data: 24 bits, audio frequency = 48 kHz tsu(WS) I2S clock low time 37 - th(WS) LRCLK valid time 7 - DuCy(SCK) LRCLK hold time 1 - Master mode tsu(SD_MR) LRCLK setup time 34 - Slave mode tsu(SD_SR) LRCLK hold time 0 - Slave mode th(SD_MR) I2S slave input clock duty cycle 25 75 0 - Master receiver 0 - Slave receiver 0 - Master receiver 0 - Master mode ns th(SD_SR) % Slave mode Data input setup time tv(SD_ST) th(SD_ST) Data input hold time tv(SD_MT) Slave receiver ns Data output valid time - 32 Slave transmitter (after enable edge) th(WS) Data output hold time 16 - Slave transmitter (after enable edge) tsu(WS) Data output valid time - 5 Master transmitter (after enable edge) th(WS) Data output hold time 0 - Master transmitter (after enable edge) Aug. 15, 2017 Page 121 of 130 Rev.1.07 NUC505 SERIES DATASHEET th(SD_MT) NUC505 tw(CKH) BCLK output tw(CKL) tv(LRCLK) th(LRCLK) LRCLK output tv(SD_ST) LSB transmit(2) SDtransmit MSB transmit tsu(SD_MR) LSB receive(2) SDreceive Bitn transmit th(SD_ST) LSB transmit th(SD_MR) MSB receive Bitn receive LSB receive Figure 7.4-5 I2S Master Mode Timing Diagram BCLK input tw(CKH) tw(CKL) th(LRCLK) LRCLK input tv(SD_ST) tsu(LRCLK) SDtransmit LSB transmit(2) MSB transmit NUC505 SERIES DATASHEET tsu(SD_SR) SDreceive LSB receive(2) Bitn transmit th(SD_ST) LSB transmit th(SD_SR) MSB receive Bitn receive LSB receive 2 Figure 7.4-6 I S Slave Mode Timing Diagram Aug. 15, 2017 Page 122 of 130 Rev.1.07 NUC505 8 APPLICATION CIRCUIT AVCC USB_DUSB_D+ USB_VBUS AVDDADC AVDDCODE AVDDHP VBAT FB DVCC USB Device USB_VDD33_CAP VDD Power 1uF AVDDUSB DVCC 0.1uF 0.1uF VSS AVSSADC LDO_AVSS AVSSHP VDD ICE_CLK ICE_CLK nRESET VSS SWD Interface 20p CS CLK MISO MOSI SPI1_SS SPI1_CLK SPI1_MISO SPI1_MOSI FB VDD SPI Device VSS DVCC NUC505 Series 4.7K DVCC 4.7K I2C1_SCL CLK VDD I2C1_SDA DATA VSS I2 C Device XT1_IN 1M 20p 33p Crystal 5VCC XT1_OUT 12 MHz crystal Curret Protect IC X32_IN GPIO 10M 33p X32_OUT USBH_DUSBH_D+ USB HOST 32.768 kHz crystal DVCC RHP_OUT LHP_OUT 10K Speaker NUC505 SERIES DATASHEET Reset Circuit Line In AUDIO_R_IN AUDIO_L_IN nRESET 10uF/10V RS 232 Transceiver LDO_CAP LDO Aug. 15, 2017 RXD ROUT TXD TIN PC COM Port RIN TOUT UART 4.7 uF Page 123 of 130 Rev.1.07 NUC505 9 9.1 PACKAGE DIMENSIONS LQFP 48L (7x7x1.4mm footprint 2.0mm) NUC505 SERIES DATASHEET Aug. 15, 2017 Page 124 of 130 Rev.1.07 NUC505 9.2 QFN 48 (7x7x0.8mm) NUC505 SERIES DATASHEET Aug. 15, 2017 Page 125 of 130 Rev.1.07 NUC505 9.3 LQFP 64L (7x7x1.4mm footprint 2.0mm) NUC505 SERIES DATASHEET Aug. 15, 2017 Page 126 of 130 Rev.1.07 NUC505 9.4 QFN 88 (10x10x0.9mm) NUC505 SERIES DATASHEET Aug. 15, 2017 Page 127 of 130 Rev.1.07 NUC505 NUC505 SERIES DATASHEET Aug. 15, 2017 Page 128 of 130 Rev.1.07 NUC505 10 REVISION HISTORY Date Revision Description 2014.04.23 1.01 Preliminary version 2015.05.28 1.02 2015.11.04 2016.05.09 2016.12.02 2017.08.15 1.04 1.05 1.06 1.07 1. Added new part number: NUC505DLA, NUC505YLA, and NUC505DSA in Chapter 4. 2. Updated embedded SPI Flash memory size to 512 KB for new part number. 1. Added a note to indicate that NUC505DS13Y only supports Headphone Out in section 4.1.1. 2. Added a note to indicate the packages are not pin-to-pin compatible in section 4.1.1. 3. Added section 9.2 QFN 48 (7x7x0.8mm) package specification. 4. Added part number NUC505YLA2Y in section 4.1.1, 4.2.4, and 4.3.4. 5. Replaced power mode name of Sleep mode and Deep-sleep mode with Idle mode and Power-down mode respectively. 1. Added a note to Pin Diagram and Pin Description for QFN 48/88-pin packages. 1. Corrected the typo in the Pin Configuration section 4.2.4/4.2.5/4.2.6 and Pin Description section 4.3.5. and Pin Description section 4.3.5. 2. Modified section 4.1.1 NUC505DLA and NUC505YLA SPI should be two. 3. Modified pin name from VBUS to VBUS33. 1. Modified VBUS33 pin description. 2. Modified USB transceiver power description in section 6.2.4. 3. Modified USB Host clock source only from PLL in section 6.3.2. 4. Modified VCMBF pin description in section 4.3.7. 5. Fixed VFS unit typo in section 7.4.2. NUC505 SERIES DATASHEET Aug. 15, 2017 Page 129 of 130 Rev.1.07 NUC505 NUC505 SERIES DATASHEET Important Notice Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are deemed, “Insecure Usage”. Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life. All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the damages and liabilities thus incurred by Nuvoton. Aug. 15, 2017 Page 130 of 130 Rev.1.07