AW8646
February 2019 V1.2
AW8646 Dual H-Bridge Stepper Motor Driver
GENERAL DESCRIPTION
3V to 12V Supply Voltage Range
1.4A Full Scale current per H-Bridge
Rdson HS + LS: Typical 0.8Ω
Support up to 1/32th Microstepping
Decay Modes supported:
The AW8646 is a flexible microstepping stepper
motor driver. It is designed to operate bipolar
stepper motor with up to 1/32th step mode for mobile
phones, tablets, and other automated equipment
applications. The device can be controlled by
simple STEP/DIR interface allowing easy
interfacing to controller circuits. The output block of
each H-bridge driver consists of N-channel and Pchannel power MOSFETS configured as full Hbridges to drive the motor windings.
Mixed Decay
Slow Decay
Fast Decay
Support 1.8V Logic Level
Programmable off-time
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Pins allow configuration of the motor in full-step up
to 1/32th step modes. Decay mode is configurable
so that adaptive decay, slow decay, fast decay, and
mixed decay can be used. A low power sleep mode
is provided to achieve very-low quiescent current
draw.
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Adaptive Decay Technology
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FEATURES
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10,20, or 30s off-time
Programmable Motor Torque Current
Short-Circuit Protection, Over-Temperature
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Protection, Under-Voltage Protection
Fault Condition Indication
QFN 4mm X4mm X0.85mm-24L package
The device offers a complete set of protection
features including UVLO, overcurrent protection,
short circuit protection, and over temperature. Fault
conditions are indicated via the nFAULT pin.
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AW8646 is capable of driving up to 1.4A (Full Scale)
or 1A (RMS) current per H-Bridge
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APPLICATIONS
Mobile phones
Tablets
Printer
Video Security Cameras
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Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW8646
February 2019 V1.2
D0
T1
T0
ADECAY
24
23
22
21
20
19
18 GND
AO1 1
ASEN 2
5
15 VDD
14 VREF
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BSEN
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16 NC
25
EPAD
13 DIR
8
9
10
11
12
MODE0
MODE1
TOFF
nEN
STEP
3YYE - AW8646QNR
XXXX - Production Tracing Code
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7
nFAULT
BO1 6
n
4
n
17 VREG
AO2 3
BO2
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nSLEEP
AW8646QNR Marking
(Top View)
D1
AW8646QNR
(Top View)
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PIN CONFIGURATION AND TOP MARK
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Figure 1 Pin Configuration And Top Mark
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Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW8646
February 2019 V1.2
PIN DEFINITION
No.
NAME
DESCRIPTION
1
AO1
2
ASEN
3
AO2
H-bridge A output
4
BO2
H-bridge B output
5
BSEN
6
BO1
7
nFAULT
Pulled low when a failure occurs, open-drain output requires external pull up
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MODE0
Tri-level pin, low bit of step mode setting pins, controls step mode (full, half, up to
1/32th step) , see description section
9
MODE1
Tri-level pin, high bit of step mode setting pins, controls step mode (full, half, up to
1/32th step) , see description section
10
TOFF
11
nEN
12
STEP
13
DIR
14
VREF
Full scale current reference input, Voltage on this pin sets the full scale current;
short to VREG if not supplying an external reference voltage
15
VDD
Power supply, Connect to motor power supply
16
NC
17
VREG
18
GND
19
ADECAY
H-bridge A output
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Sense output of bridge A, If current regulation is not required it must connect to
GND
Sense output of bridge B, If current regulation is not required it must connect to
GND
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H-bridge B output
Tri-level pin, decay mode off time set, sets the off-time during current control
Driver enable control input pin. Logic low to enable device outputs, logic high to
disable device outputs
n
Step input, A rising or falling edge increases one step
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Direction input, sets the direction of stepping
No connect, Unused pin
Internal regulator, Internal supply voltage
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Ground pin, both the GND pin and device thermal pad must be connected to
ground
Adaptive Decay mode control pin, when set to logic low, decay modes controlled
by D0 and D1 pins; when set to logic high, Adaptive Decay mode is enabled, must
be set prior to coming out of sleep
T0
Tri-level pin, Scales the torque current from 100% to 12.5% in 12.5% steps, see
description section
T1
Tri-level pin, Scales the torque current from 100% to 12.5% in 12.5% steps, see
description section
22
D0
Tri-level pin, Decay mode setting pins, see description section
23
20
nSLEEP
24
D1
25
EPAD
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Sleep mode input, Logic high to enable device; logic low to enter low-power sleep
mode; internal pull down
Tri-level pin, Decay mode setting pins, see description section
Thermal pad, must be connected to GND
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Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW8646
February 2019 V1.2
FUNCTIONAL BLOCK DIAGRAM
VDD
VREG
LDO
2.2μF
0.1μF 10μF
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OCP/UVL
VREF
VDD
nEN
AO1
STEP
n
Gate
Drive
DIR
MODE0
Controller
BO1
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n
nFAULT
o
Gate
Drive
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C
ADECAY
BO2
BSEN
Bsensor
OTP
EPAD
GND
Figure 2 Functional Block Diagram
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ASEN
OCP/UVL
VDD
TOFF
Logic supply
nSLEEP
D1
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Asensor
T0
D0
Stepper
Motor
AO2
MODE1
T1
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VDD
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Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW8646
February 2019 V1.2
TYPICAL APPLICATION CIRCUITS
VDD
C2
0.1μF
25V
VREG
7
12
VDD
VREF
AO1
STEP
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1
RASEN
2 0.5ohm
Stepper
Motor
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ASEN
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AO2 3
AW8646
19
ADECAY
20 T0
21
T1
22 D0
23 nSLEEP
24
D1
BO2
4
BSEN 5
RBSEN
0.5ohm
6
n
BO1
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GND
16
NC
nFAULT
13
DIR
8
MODE0
9 MODE1
10
TOFF
11 nEN
CPU
15
14
17
R1
10Kohm
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VCC
Logic supply
C1
10μF
25V
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C3
2.2μF
10V
18
EPAD
25
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Tri-level Inputs: T0,T1,MODE0,MODE1,D0,D1,TOFF
Logic-level inputs: DIR, nEN, nSLEEP, ADECAY
PWM signal: STEP
The current of RxSEN is equal to the current of
motor, refer to the application maxium motor
current when calculate the power of RxSEN
Figure 3 Typical Application Circuit of AW8646
All trademarks are the property of their respective owners.
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Notice for Typical Application Circuits:
1：Please place C1，C2，C3 as close to the chip as possible. The capacitors should be placed in the same
layer with the AW8646 chip.
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2：For the sake of driving capability, the power lines (especially the one to Pin C2) and output lines should be
short and wide as possible.
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3：Table 1 lists the recommended external components for the device.
COMPONENT
C1
C2
C3
R1
RASEN
RBSEN
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Table 1
PIN 1
VDD
VDD
VREG
VCC
ASEN
BSEN
PIN 2
GND
GND
GND
nFAULT
GND
GND
5
External Components
RECOMMENDED
25V, 10μF (minimum) ceramic capacitor rated for VDD
25V, 0.1μF ceramic capacitor rated for VDD
10V, 2.2μF ceramic capacitor
>5kΩ
Sense resistor, see applications section for sizing
Sense resistor, see applications section for sizing
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW8646
February 2019 V1.2
ORDERING INFORMATION
Temperature
Package
Marking
Moisture
Sensitivity
Level
Environmental
Information
Delivery Form
AW8646
QNR
-40℃~85℃
QFN
4mmX4mm24L
3YYE
MSL3
ROHS+HF
6000 units/Tape
and Reel
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Part
Number
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ABSOLUTE MAXIMUM RATINGS(NOTE1)
RANGE
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PARAMETERS
Power supply voltage (VDD)
Power supply voltage ramp rate (VDD)
Analog input pin voltage (VREF)
0V/s to 2 V/s
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Internal regulator voltage (VREG)
-0.3V to 16V
-0.3V to 3.6V
-0.3V to 3.6V
-0.3V to 7V
Continuous phase node pin voltage (AO1, AO2, BO1, BO2)
-0.3V to (VDD+0.6)V
Continuous shunt amplifier input pin voltage (ASEN, BSEN)
-0.6V to 0.6V
Peak drive current (AO1, AO2, BO1, BO2, ASEN, BSEN)
Internally limited
Junction-to-ambient thermal resistance θJA
60°C /W
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Control pin voltage (nEN, STEP, DIR, T0, T1, MODE0, MODE1, D0, D1,
TOFF, nSLEEP,nFAULT, ADECAY)
Operating free-air temperature range
-40°C to 85°C
165°C
Storage temperature TSTG
-65°C to 150°C
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Maximum operating junction temperature TJMAX
Lead temperature (soldering 10 seconds)
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ESD(Including CDM HBM MM)
260°C
(NOTE 2)
HBM(Human Body Model)
±4kV
CDM(Charge Device Model)
±1.5kV
Latch-Up
Test Condition: JEDEC STANDARD NO.78E
+IT：200mA
-IT：-200mA
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NOTE1: Conditions out of those ranges listed in "absolute maximum ratings" may cause permanent damages
to the device. In spite of the limits above, functional operation conditions of the device should within the ranges
listed in "recommended operating conditions". Exposure to absolute-maximum-rated conditions for prolonged
periods may affect device reliability.
NOTE2: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. Test
method: ANSI/ESDA/JEDEC JS-001
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Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW8646
February 2019 V1.2
ELECTRICAL CHARACTERISTICS
VDD=5V, TA=25°C for typical values (unless otherwise noted)
MAX
3
5
12
1.0
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7
4.0
mA
0.1
1
A
0.7
0.5
ms
ms
0.5
ms
3.3
3.47
V
0.45
5.5
V
V
mV
A
A
100
–1
1
1
40
200
500
200
600
0
kΩ
ns
ns
0.45
0.9
1.3
V
V
5.5
100
V
mV
–22
–1
A
1
40
A
in
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V
2.5
0
1.3
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3.13
UNIT
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TYP
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VDD = 5 V, excluding winding
IVDD
VDD operating supply current current,
nSLEEP = 1, nEN = 0 or 1
VDD sleep mode supply
VDD = 5 V, nSLEEP = 0, nEN = 0
IVDDQ
current
or 1
tSLEEP
Sleep time
nSLEEP = 0 to sleep mode
tWAKE
Wake time
nSLEEP = 1 to output transition
VDD > VUVLO rising to output
tON
Power-on time
transition
VREG
VREG voltage
VDD > 4 V, IOUT = 0 A to 1 mA
LOGIC-LEVEL INPUTS (STEP, DIR, nEN, nSLEEP, ADECAY)
VIL
Input logic low voltage
VIH
Input logic high voltage
VHYS
Input logic hysteresis
IIL
Input logic low current
VIN = 0 V
IIH
Input logic high current
VIN = 5 V
nEN, STEP, DIR, ADECAY
RPD
Pulldown resistance
nSLEEP
tDEG
Input deglitch time
tPROP
Propagation delay
STEP edge to current change
TRI-LEVEL INPUTS (T0, T1, MODE0, MODE1, D0, D1, TOFF)
Tri-level input logic low
VIL
voltage
VIZ
Tri-level input Hi-Z voltage
Tri-level input logic high
VIH
voltage
VHYS
Tri-level input hysteresis
Tri-level input logic low
IIL
VIN = 0 V
current
Tri-level input logic high
IIH
VIN = 5 V
current
RPD
Tri-level pulldown resistance
To GND
RPU
Tri-level pullup resistance
To VREG
CONTROL OUTPUTS (nFAULT)
VOL
Output logic low voltage
IO = 5 mA
IOH
Output logic high leakage
VO = 3.3 V
MOTOR DRIVER OUTPUTS (AO1, AO2, BO1, BO2)
RDS(ON)
High-side FET on resistance
VDD = 5 V, I = 0.5 A, TJ = 25°C
RDS(ON)
Low-side FET on resistance
VDD = 5 V, I = 0.5 A, TJ = 25°C
tRISE
Output rise time
tFALL
Output fall time
tDEAD
Output dead time
Internal dead time
PWM CURRENT CONTROL (VREF, ASEN, BSEN)
Externally applied VREF
IREF
VREF = 1 to 3.3 V
input current
For 100% current step with VREF
VTRIP
xSEN trip voltage
= 3.3 V
MIN
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TEST CONDITIONS
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PARAMETER
POWER SUPPLIES (VDD, VREG)
VDD
VDD operating voltage
180
480
kΩ
kΩ
0.5
1
–1
V
A
430
300
50
50
150
mΩ
mΩ
ns
ns
ns
2
A
500
mV
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW8646
February 2019 V1.2
TEST CONDITIONS
Reference Only
TOFF = GND
TOFF = Hi-Z
TOFF = VREG
Current control constant off
time
tOFF
MIN
TYP
6.6
20
10
30
MAX
PROTECTION CIRCUITS
Overcurrent Protection Trip
Level
Overcurrent Deglitch Time
Overcurrent Protection
Period
Thermal shutdown
temperature
Thermal shutdown hysteresis
tOCP
tRETRY
TTSD
THYS
2
Die Temperature TJ
Die Temperature TJ
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TIMING REQUIREMENTS
V
A
0.1
s
1.6
ms
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IOCP
2.7
2.8
s
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VDD falling; UVLO Report
VDD rising; UVLO Recovery
VDD under voltage lockout
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VUVLO
UNIT
V/V
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PARAMETER
Current sense amplifier gain
K
160
°C
30
°C
VDD=5V, TA=25°C for typical values (unless otherwise noted)
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tWH(STEP)
tWL(STEP)
tSU(STEP)
tH(STEP)
DESCRIPTION
Step Frequency
Pulse Duration, STEP High
Pulse Duration, STEP Low
Setup Time, DIR or Mx to STEP Rising
Hold Time, DIR or Mx to STEP Rising
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NAME
ƒSTEP
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NO.
1
2
3
4
5
MIN
1.9
1.9
200
600
MAX
250
UNIT
KHz
s
s
ns
ns
①
②
③
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STEP
④⑤
Figure 4 Timing Diagram
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DIR,MODE0,MODE1
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Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW8646
February 2019 V1.2
DETAILED FUNCTIONAL DESCRIPTION
OVERVIEW
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The AW8646 is a bipolar stepper motors driver integrating 2 H-bridges that use NMOS low-side drivers and
PMOS high-side drivers, two PWM current controller, and a microstepping sequencer. The AW8646 can be
powered with a supply range between 3 to 12V. The AW8646 is capable of driving up to 1.4A (Full Scale) or
1A (RMS) current per H-Bridge.
At each STEP rising edge or falling edge(some step mode), the sequencer of the device increased or
decreased as step mode configuration.
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The internal sequencer is able to execute high-accuracy microstepping setting the reference value of the PWM
current controller and the direction of the current for both of the H-bridge.
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The total PWM off-time, tOFF can be adjusted to 10, 20, or 30s.
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The AW8646 has Adaptive Decay Technology that automatically adjusts the decay setting to minimize current
ripple. This feature allows the device to quickly be integrated into a system.
The torque current can be adjusted using digital input pins. This allows the controller to save power by
decreasing the current consumption when not required.
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A low-power sleep mode is included, which allows the system to save power when not driving the motor.
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Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW8646
February 2019 V1.2
FEATURE DESCRIPTION
PWM MOTOR DRIVERS
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AW8646 contains two identical H-bridge motor drivers with current-control PWM circuitry. Figure 2 shows
a block diagram of the circuitry.
VDD
STEP
step_cnt
OCP
DIR
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XO1
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pwm
control
Vref
VREF
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gatedrive
Stepper
Motor
XO2
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OCP
-
K=6.6
XSEN
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+
buffer
T1
C
T0
DAC
3
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from step_cnt
5
SIN
DAC
Figure 5 PWM Motor Driver Circuitry
MICRO-STEPPING SEQUENCER
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Through step and direction interface the device contains a microstepping sequencer to control the state of the
H-bridges automatically. When the correct transition is applied at the STEP input, thesequencer moves to the
next step, according to the direction set by the DIR pin. In 1/8 th, 1/16th,and 1/32th step modes, both the rising
and falling edges of the STEP input may be used to advance the sequencer, depending on the MODE0/MODE1
setting.
The nEN pin can disable the output stage. When nEN = 1, the sequencer inputs are still active and respond to
the STEP and DIR input pins; only the output stage is disabled.
The sequencer logic in the AW8646 allows a number of different stepping configurations. The MODE0 and
MODE1 pins configure the stepping format (see Table 2).
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Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW8646
February 2019 V1.2
Table 2
Step Mode Settings
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MODE1
MODE0
STEP MODE
0
0
Full step, rising-edge only
0
Z
1/2 step, rising-edge only
0
1
1/4 step, rising-edge only
Z
0
8 microsteps/step, rising-edge only
Z
Z
8 microsteps/step, rising and falling edges
Z
1
16 microsteps/step, rising-edge only
1
0
16 microsteps/step, rising and falling edges
1
Z
32 microsteps/step, rising-edge only
1
1
32 microsteps/step, rising and falling edges
For 1/8, 1/16, and 1/32-step modes, selections are available to advance the sequencer only on the rising edge
of the STEP input, or on both the rising and falling edges.
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The step mode may be changed on-the-fly while the motor is moving. The sequencer advances to the next
valid state for the new MODE0 / MODE1 setting at the next rising edge of STEP.
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The home state is 45°. The sequencer enters the home state after power-up, after exiting UVLO, or after exiting
sleep mode.
CURRENT REGULATION
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The current through the motor windings is regulated by an adjustable fixed-off-time PWM current regulation
circuit. When an H-bridge is enabled, current rises through the winding at a rate dependent on the DC voltage,
inductance of the winding, and the magnitude of the back EMF present. After the current reaches the current
control threshold, the bridge enters a decay mode for a fixed period of time to decrease the current, which is
configurable between 10 to 30 μs through the tri-level input TOFF. After the time expires, the bridge is reenabled, starting another PWM cycle.
Fixed Off-Time Selection
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Table 3
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TOFF
TOFF Duration
Z
10 s
0
20 s
1
30 s
The PWM current control is set by a comparator which compares the voltage across a current sense resistor
connected to the xSEN pin, with a reference voltage. The reference voltage can be supplied by an internal
reference of 3.3 V (which requires VREG to be connected to VREF), or externally supplied to the VREF pin.
The reference voltage is then scaled first by the 3-bit torque DAC, then by the output of a sine lookup table
that is applied to a sine-weighted DAC (sine DAC). The voltage is attenuated by a factor of 6.6.
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The full-scale (100%) control current is calculated as follows:
I FS
VREF
xTORQUE
6.6xR XSEN
where
• IFS is the full scale regulated current
• VREF is the voltage on the VREF pin
• RXSEN is the resistance of the sense resistor
• TORQUE is the scaling percentage from the torque DAC.
Example: Using VREF is 3.3 V, torque DAC = 100%, and a 500 mΩ sense resistor, the full-scale control current
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Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW8646
February 2019 V1.2
is 3.3 V / (6.6 × 500 mΩ) × 100% = 1 A.
The current for both motor windings is scaled depending on the T0 and T1 pins as in Table 4.
Table 4
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CURRENT SCALING (TORQUE)
100.0%
87.5%
75.0%
62.5%
50.0%
37.5%
25.0%
12.5%
0% (outputs disabled)
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T0
0
Z
1
0
Z
1
0
Z
1
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T1
0
0
0
Z
Z
Z
1
1
1
Torque DAC Settings
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DECAY MODE
After the control current threshold is reached, the drive current is interrupted, but due to the inductive nature
of the motor, current must continue to flow for some period of time (called recirculation current). To handle this
recirculation current, the H-bridge can operate in two different states, fast decay or slow decay (or a mixture
of fast and slow decay).
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In fast-decay mode, after the PWM control current level is reached, the H-bridge reverses state to allow winding
current to flow through the opposing FETs. As the winding current approaches 0, the bridge is disabled to
prevent any reverse current flow. For fast-decay mode, see number 2 in Figure 3.
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VDD
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In slow-decay mode, winding current is recirculated by enabling both of the low-side FETs in the bridge. For
slow-decay mode, see number 3 in Figure 3.
VDD
VDD
①
xO2
xO1
xO2
xO2
xO1
②
③
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xO1
① Drive
② Fast decay
③ Slow decay
Figure 6 Decay Modes
The AW8646 supports fast, slow, mixed, and Adaptive Decay modes. With stepper motors, the decay mode is
chosen for a given stepper motor and operating conditions to minimize mechanical noise and vibration.
In mixed decay mode, the current recirculation begins as fast decay, but at a fixed period of time (determined
by the state of the D1 and D0 pins shown in Table 5) the current recirculation switches to slow decay mode for
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Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW8646
February 2019 V1.2
the remainder of the fixed PWM period. Note that the D1 and D0 pins are tri-level inputs; these pins can be
driven logic low, logic high, or high-impedance (Z).
Table 5
Decay Pins Configuration
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Current of A
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D1
D0
Decay Mode (Increasing Current)
Decay Mode (Decreasing Current)
0
0
Slow decay
Slow decay
0
Z
Slow decay
Mixed decay: 25% fast
0
1
Slow decay
Mixed decay: 1 tBLANK
Z
0
Mixed decay: 1 tBLANK
Mixed decay: 1 tBLANK
Z
Z
Mixed decay: 50% fast
Mixed decay: 50% fast
Z
1
Mixed decay: 25% fast
Mixed decay: 25% fast
1
0
Slow decay
Mixed decay: 50% fast
1
Z
Slow decay
Mixed decay: 12.5% fast
1
1
Slow decay
Fast decay
Figure 4 shows increasing and decreasing current. When current is decreasing, the decay mode used is fast,
slow, or mixed as commanded by the D1 and D0 pins. Three DEC pin selections allow for mixed decay during
increasing current.
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increasing decreasing
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Current of B
C
SineDAC_A
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increasing decreasing
increasing
decreasing
in
increasing decreasing
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SineDAC_B
Figure 7 Increasing and Decreasing Current
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Adaptive Decay Technology simplifies the decay mode selection by dynamically changing to adjust for current
level, step change, supply variation, BEMF, and load. To enable Adaptive Decay mode, pull the ADECAY pin
to logic high. The state of the ADECAY pin is only evaluated when exiting sleep mode. (ADECAY pin must be
high before exiting sleep to enable Adaptive Decay mode.)
Figure 5 shows Adaptive Decay mode adjusts the time spent in fast decay to minimize current ripple and
quickly adjust to current-step changes. If the drive time is longer than the minimum (t BLANK), in order to reach
the current trip point, the decay mode applied is slow decay. When the minimum drive time (tBLANK) provides
more current than the regulation point, fast decay of 1 tBLANK is applied. If the second drive period also provides
more current than the regulation point, fast decay of 2 t BLANK is applied. If a third (or more) consecutive period
provides more current than the regulation point, fast decay using 25% of tOFF time is applied. When the
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13
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW8646
February 2019 V1.2
minimum drive time is insufficient to reach the current regulation level, slow decay is applied until the current
exceeds the current reference level.
ti
a
l
Current
Iref
fi
d
OVERCURRENT PROTECTION (OCP)
e
Figure 8 Adaptive Decay mode
n
STEP
n
An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive. If this
analog current limit persists for longer than the OCP deglitch time t OCP, all FETs in the H-bridge are disabled
and the nFAULT pin is driven low. The device remains disabled until the retry time, t RETRY, occurs. The OCP is
independent for each H-bridge.
o
Overcurrent conditions are detected independently on both high-side and low-side devices; that is, a short to
ground, supply, or across the motor winding all result in an OCP event. Note that OCP does not use the current
sense circuitry used for PWM current control, so OCP functions without the presence of the xSEN resistors.
C
THERMAL SHUTDOWN (TSD)
If the die temperature exceeds safe limits, all FETs in the H-bridge are disabled and the nFAULT pin is driven
low. After the die temperature falls to a safe level, operation automatically resumes. The nFAULT pin is
released after operation has resumed.
ic
UNDERVOLTAGE LOCKOUT (UVLO)
in
If at any time the voltage on the VDD pin falls below the UVLO falling threshold voltage, V UVLO, all circuitry in
the device is disabled, and all internal logic is reset. Operation resumes when VDD rises above the UVLO
rising threshold. The nFAULT pin is driven low during an under voltage condition and is released after operation
has resumed.
Table 6
Fault Behavior
Error Report
nFAULT unlatched
H-Bridge
Disabled
Internal Circuits
Shut down
OCP
nFAULT unlatched
Disabled
Operating
TSD
nFAULT unlatched
Disabled
Operating
a
w
Fault
VDD UVLO
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Recovery
System and fault clears on recovery
System and fault clears on recovery
and motor is driven after time, TRETRY
System and fault clears on recovery
Copyright © 2018 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW8646
February 2019 V1.2
DEVICE FUNCTIONAL MODES
l
The AW8646 device is active unless the nSLEEP pin is driven low. In sleep mode, the VREG regulator is
disabled and the H-bridge FETs are disabled (Hi-Z). The time TSLEEP must elapse after a falling edge on the
nSLEEP pin before the device enters sleep mode. The AW8646 is brought out of sleep mode by bringing the
nSLEEP pin high. The time TWAKE must elapse, after nSLEEP is brought high, before the outputs change state.
Table 7
ti
a
If the nEN pin is brought high, the H-bridge outputs are disabled, but the internal logic is still active. An
appropriate edge on STEP (depending on the step mode) advances the sequencer, but the outputs do not
change state until nEN is driven low.
Operating Modes
Condition
H-Bridge
VREG
Operating
3V
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