UMW LM75B
1. Features and benefits
Pin-for-pin replacement for industry standard LM75 and LM75A and offers improved
temperature resolution of 0.125 C and specification of a single part over power supply
range from 2.8 V to 5.5 V
I2C-bus interface with up to 8 devices on the same bus
Power supply range from 2.8 V to 5.5 V
Temperatures range from 55 C to +125 C
Frequency range 20 Hz to 400 kHz with bus fault time-out to prevent hanging up the
bus
11-bit ADC that offers a temperature resolution of 0.125 C
Temperature accuracy of:
±0.5 C from C to +50 C
±1 C from 25 C to +100 C
±1.5 C from 55 C to +125 C
Programmable temperature threshold and hysteresis set points
Supply current of 1.0 A in shutdown mode for power conservation
Stand-alone operation as thermostat at power-up
ESD protection exceeds 4000 V HBM per JESD22-A114 and 2000 V CDM per
JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
2. Applications
System thermal management
Personal computers
Electronics equipment
Industrial controllers
3. Ordering information
Table 1.
Type
Ordering information
number
Topside
mark
Package
Name
Description
LM75BD
LM75BD
SOP8
plastic small outline package; 8 leads;
V1.0
LM75BDP
LM75B
MSOP8
plastic thin shrink small outline package; 8 leads;
V1.0
Version
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4. Pinning information
4.1 Pinning
LM75BDP
LM75BD
4.2
Pin description
Table 3.
Pin description
Symbol
Pin
Description
SDA
1
Digital I/O. I2C-bus serial bidirectional data line; open-drain.
SCL
2
Digital input. I2C-bus serial clock input.
OS
3
Overtemperature Shutdown output; open-drain.
GND
4
Ground. To be connected to the system ground.
A2
5
Digital input. User-defined address bit 2.
A1
6
Digital input. User-defined address bit 1.
A0
7
Digital input. User-defined address bit 0.
VCC
8
Power supply.
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5. General description
The LM75B is a temperature-to-digital converter using an on-chip band gap
temperature sensor and Sigma-Delta A-to-D conversion technique with an over
temperature detection output. The LM75B contains a number of data registers:
Configuration register (Conf) to store the device settings such as device operation mode,
OS operation mode, OS polarity and OS fault queue as described in Section 7 “Functional
description”; temperature register (Temp) to store the digital temp reading, and set-point
registers (Tos and Thyst) to store programmable over temperature shutdown and
hysteresis limits, that can be communicated by a controller via the 2-wire serial I2C-bus
interface. The device also includes an open-drain output (OS) which becomes active when
the temperature exceeds the programmed limits. There are three selectable logic address
pins so that eight devices can be connected on the same bus without address conflict.
The LM75B can be configured for different operation conditions. It can be set in
normal mode to periodically monitor the ambient temperature, or in shutdown mode to
minimize power consumption. The OS output operates in either of two selectable modes:
OS comparator mode or OS interrupt mode. Its active state can be selected as either
HIGH or LOW. The fault queue that defines the number of consecutive faults in order to
activate the OS output is programmable as well as the set-point limits.
The temperature register always stores an 11-bit two’s complement data giving a
temperature resolution of 0.125 C. This high temperature resolution is particularly useful
in applications of measuring precisely the thermal drift or runaway. When the LM75B is
accessed the conversion in process is not interrupted (that is, the I2C-bus section is totally
independent of the Sigma-Delta converter section) and accessing the LM75B continuously
without waiting at least one conversion time between communications will
not prevent the device from updating the Temp register with a new conversion result. The
new conversion result will be available immediately after the Temp register is updated.
The LM75B powers up in the normal operation mode with the OS in comparator
mode, temperature threshold of 80 C and hysteresis of 75 C, so that it can be used
as a stand-alone thermostat with those pre-defined temperature set points.
6. Block diagram
VCC
LM75B
BIAS
REFERENCE
BAND GAP
TEMP SENSOR
POINTER
REGISTER
CONFIGURATION
REGISTER
COUNTER
TEMPERATURE
REGISTER
11-BIT SIGMADELTA A-to-D
CONVERTER
TIMER
OSCILLATOR
COMPARATOR/
INTERRUPT
TOS
REGISTER
THYST
REGISTER
POWER-ON
RESET
OS
LOGIC CONTROL AND INTERFACE
A2
A1
A0
SCL SDA
002aad453
GND
Fig 1.
Block diagram of LM75B
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7. Functional description
7.1 General operation
The LM75B uses the on-chip band gap sensor to measure the device temperature with
the resolution of 0.125 C and stores the 11-bit two’s complement digital data, resulted
from 11-bit A-to-D conversion, into the device Temp register. This Temp register can be
read at any time by a controller on the I2C-bus. Reading temperature data does not affect
the conversion in progress during the read operation.
The device can be set to operate in either mode: normal or shutdown. In normal operation
mode, the temp-to-digital conversion is executed every 100 ms and the Temp register is
updated at the end of each conversion. During each ‘conversion period’ (Tconv) of about
100 ms the device takes only about 10 ms, called ‘temperature conversion time’ (tconv(T)),
to complete a temperature-to-data conversion and then becomes idle for the time
remaining in the period. This feature is implemented to significantly reduce the device
power dissipation. In shutdown mode, the device becomes idle, data conversion is
disabled and the Temp register holds the latest result; however, the device I2C-bus
interface is still active and register write/read operation can be performed. The device
operation mode is controllable by programming bit B0 of the configuration register. The
temperature conversion is initiated when the device is powered-up or put back into normal
mode from shutdown.
In addition, at the end of each conversion in normal mode, the temperature data (or Temp)
in the Temp register is automatically compared with the over temperature shutdown
threshold data (or Tth(ots)) stored in the Tos register, and the hysteresis data (or Thys)
stored in the Thyst register, in order to set the state of the device OS output accordingly.
The device Tos and Thyst registers are write/read capable, and both operate with 9-bit
two’s complement digital data. To match with this 9-bit operation, the Temp register uses
only the 9 MSB bits of its 11-bit data for the comparison.
The way that the OS output responds to the comparison operation depends upon the OS
operation mode selected by configuration bit B1, and the user-defined fault queue defined
by configuration bits B3 and B4.
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In OS comparator mode, the OS output behaves like a thermostat. It becomes active
when the Temp exceeds the Tth(ots), and is reset when the Temp drops below the Thys.
Reading the device registers or putting the device into shutdown does not change the
state of the OS output. The OS output in this case can be used to control cooling fans or
thermal switches.
In OS interrupt mode, the OS output is used for thermal interruption. When the device is
powered-up, the OS output is first activated only when the Temp exceeds the Tth(ots); then
it remains active indefinitely until being reset by a read of any register. Once the OS output
has been activated by crossing Tth(ots) and then reset, it can be activated again only when
the Temp drops below the Thys; then again, it remains active indefinitely until being reset
by a read of any register. The OS interrupt operation would be continued in this sequence:
Tth(ots) trip, Reset, Thys trip, Reset, Tth(ots) trip, Reset, Thys trip, Reset, etc. Putting the
device into the shutdown mode by setting the bit 0 of the configuration register also resets
the OS output.
In both cases, comparator mode and interrupt mode, the OS output is activated only if a
number of consecutive faults, defined by the device fault queue, has been met. The fault
queue is programmable and stored in the two bits, B3 and B4, of the Configuration
register. Also, the OS output active state is selectable as HIGH or LOW by setting
accordingly the configuration register bit B2.
At power-up, the device is put into normal operation mode, the Tth(ots) is set to 80 C, the
Thys is set to 75 C, the OS active state is selected LOW and the fault queue is equal to 1.
The temp reading data is not available until the first conversion is completed in about
100 ms.
The OS response to the temperature is illustrated in Figure 6.
Tth(ots)
Thys
reading temperature limits
OS reset
OS active
OS reset
(1)
OS active
OS output in comparator mode
(1)
(1)
OS output in interrupt mode
002aae334
(1) OS is reset by either reading register or putting the device in shutdown mode. It is assumed that
the fault queue is met at each Tth(ots) and Thys crossing point.
Fig 6.
OS response to temperature
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7.2 I2C-bus serial interface
The LM75B can be connected to a compatible 2-wire serial interface I2C-bus as a
slave device under the control of a controller or master device, using two device terminals,
SCL and SDA. The controller must provide the SCL clock signal and write/read data
to/from the device through the SDA terminal. Notice that if the I2C-bus common pull-up
resistors have not been installed as required for I2C-bus, then an external pull-up resistor,
about 10 k, is needed for each of these two terminals. The bus communication protocols
are described in Section 7.10.
7.2.1 Bus fault time-out
If the SDA line is held LOW for longer than tto (75 ms minimum / 13.3 Hz; guaranteed at
50 ms minimum / 20 Hz), the LM75B will reset to the idle state (SDA released) and wait
for a new START condition. This ensures that the LM75B will never hang up the
bus should there be conflict in the transmission sequence.
7.3 Slave address
The LM75B slave address on the I2C-bus is partially defined by the logic applied to the
device address pins A2, A1 and A0. Each of them is typically connected either to GND for
logic 0, or to VCC for logic 1. These pins represent the three LSB bits of the device 7-bit
address. The other four MSB bits of the address data are preset to ‘1001’ by hard wiring
inside the LM75B . Table 4 shows the device’s complete address and indicates that up to
8 devices can be connected to the same bus without address conflict. Because the input
pins, SCL, SDA and A2 to A0, are not internally biased, it is important that they should not
be left floating in any application.
Table 4.
Address table
1 = HIGH; 0 = LOW.
MSB
1
LSB
0
0
1
A2
A1
A0
7.4 Register list
The LM75B contains four data registers beside the pointer register as listed in Ta ble
5. The pointer value, read/write capability and default content at power-up of the
registers are also shown in Table 5.
Table 5.
Register table
Register Pointer
name
value
R/W
POR
state
Description
Conf
01h
R/W
00h
Configuration register: contains a single 8-bit data
byte; to set the device operating condition; default = 0.
Temp
00h
read only
n/a
Temperature register: contains two 8-bit data bytes;
to store the measured Temp data.
Tos
03h
R/W
5000h
Over temperature shutdown threshold register:
contains two 8-bit data bytes; to store the over
temperature shutdown Tth(ots) limit;
default = 80 C.
Thyst
02h
R/W
4B00h
Hysteresis register: contains two 8-bit data bytes;
to store the hysteresis Thys limit; default = 75 C.
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7.4.1 Pointer register
The Pointer register contains an 8-bit data byte, of which the two LSB bits represent the
pointer value of the other four registers, and the other 6 MSB bits are equal to 0, as shown
in Table 6 and Table 7. The Pointer register is not accessible to the user, but is used to
select the data register for write/read operation by including the pointer data byte in the
bus command.
Table 6.
Pointer register
B7
B6
B5
B4
B3
B2
B[1:0]
0
0
0
0
0
0
pointer value
Table 7.
Pointer value
B1
B0
Selected register
0
0
Temperature register (Temp)
0
1
Configuration register (Conf)
1
0
Hysteresis register (Thyst)
1
1
Overtemperature shutdown register (Tos)
Because the Pointer value is latched into the Pointer register when the bus command
(which includes the pointer byte) is executed, a read from the LM75B may or may not
include the pointer byte in the statement. To read again a register that has been recently
read and the pointer has been preset, the pointer byte does not have to be included. To
read a register that is different from the one that has been recently read, the pointer byte
must be included. However, a write to the LM75B must always include the pointer byte
in the statement. The bus communication protocols are described in Section 7.10.
At power-up, the Pointer value is equal to 00 and the Temp register is selected; users can
then read the Temp data without specifying the pointer byte.
7.4.2 Configuration register
The Configuration register (Conf) is a write/read register and contains an 8-bit
non-complement data byte that is used to configure the device for different operation
conditions. Table 8 shows the bit assignments of this register.
Table 8.
Conf register
Legend: * = default value.
Bit
Symbol
Access Value Description
B[7:5]
reserved
R/W
B[4:3]
OS_F_QUE[1:0] R/W
B2
OS_POL
000*
reserved for manufacturer’s use; should be kept as
zeroes for normal operation
OS fault queue programming
00*
queue value = 1
01
queue value = 2
10
queue value = 4
11
queue value = 6
R/W
OS polarity selection
0*
OS active LOW
1
OS active HIGH
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Table 8.
Conf register …continued
Legend: * = default value.
Bit
Symbol
B1
OS_COMP_INT R/W
B0
Access Value Description
SHUTDOWN
OS operation mode selection
0*
OS comparator
1
OS interrupt
R/W
device operation mode selection
0*
normal
1
shutdown
7.4.3 Temperature register
The Temperature register (Temp) holds the digital result of temperature measurement or
monitor at the end of each analog-to-digital conversion. This register is read-only and
contains two 8-bit data bytes consisting of one Most Significant Byte (MSByte) and one
Least Significant Byte (LSByte). However, only 11 bits of those two bytes are used to store
the Temp data in two’s complement format with the resolution of 0.125 C. Table 9 shows
the bit arrangement of the Temp data in the data bytes.
Table 9.
Temp register
MSByte
LSByte
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
When reading register Temp, all 16 bits of the two data bytes (MSByte and LSByte) are
provided to the bus and must be all collected by the controller to complete the bus
operation. However, only the 11 most significant bits should be used, and the 5 least
significant bits of the LSByte are zero and should be ignored. One of the ways to calculate
the Temp value in C from the 11-bit Temp data is:
1. If the Temp data MSByte bit D10 = 0, then the temperature is positive and Temp value
(C) = +(Temp data) 0.125 C.
2. If the Temp data MSByte bit D10 = 1, then the temperature is negative and
Temp value (C) = (two’s complement of Temp data) 0.125 C.
Examples of the Temp data and value are shown in Table 10.
Table 10.
Temp register value
11-bit binary
(two’s complement)
Hexadecimal value
Decimal value
Value
011 1111 1000
3F8
1 016
+127.000 C
011 1111 0111
3F7
1 015
+126.875 C
011 1111 0001
3F1
1 009
+126.125 C
011 1110 1000
3E8
1 000
+125.000 C
000 1100 1000
0C8
200
+25.000 C
000 0000 0001
001
1
+0.125 C
000 0000 0000
000
0
0.000 C
111 1111 1111
7FF
1
0.125 C
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Table 10.
Temp register value …continued
11-bit binary
(two’s complement)
Hexadecimal value
Decimal value
Value
111 0011 1000
738
200
25.000 C
110 0100 1001
649
439
54.875 C
110 0100 1000
648
440
55.000 C
For 9-bit Temp data application in replacing the industry standard LM75, just use only
9 MSB bits of the two bytes and disregard 7 LSB of the LSByte. The 9-bit Temp data with
0.5 C resolution of the LM75B is defined exactly in the same way as for the standard
LM75 and it is here similar to the Tos and Thyst registers.
The only MSByte of the temperature can also be read with the use of a one-byte reading
command. Then the temperature resolution will be 1.00 C instead.
7.4.4 Overtemperature shutdown threshold (Tos) and hysteresis (Thyst) registers
These two registers, are write/read registers, and also called set-point registers. They are
used to store the user-defined temperature limits, called overtemperature shutdown
threshold (Tth(ots)) and hysteresis temperature (Thys), for the device watchdog operation.
At the end of each conversion the Temp data will be compared with the data stored in
these two registers in order to set the state of the device OS output; see Section 7.1.
Each of the set-point registers contains two 8-bit data bytes consisting of one MSByte and
one LSByte the same as register Temp. However, only 9 bits of the two bytes are used to
store the set-point data in two’s complement format with the resolution of 0.5 C. Ta ble 11
and Table 12 show the bit arrangement of the Tos data and Thyst data in the data bytes.
Notice that because only 9-bit data are used in the set-point registers, the device uses
only the 9 MSB of the Temp data for data comparison.
Table 11.
Tos register
MSByte
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
Table 12.
Thyst register
MSByte
LSByte
7
LSByte
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
When a set-point register is read, all 16 bits are provided to the bus and must be collected
by the controller to complete the bus operation. However, only the 9 most significant bits
should be used and the 7 LSB of the LSByte are equal to zero and should be ignored.
Table 13 shows examples of the limit data and value.
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Table 13.
Tos and Thyst limit data and value
11-bit binary
(two’s complement)
Hexadecimal value
Decimal value
Value
0 1111 1010
0FA
250
+125.0 C
0 0011 0010
032
50
+25.0 C
0 0000 0001
001
1
+0.5 C
0 0000 0000
000
0
0.0 C
1 1111 1111
1FF
1
0.5 C
1 1100 1110
1CE
50
25.0 C
1 1001 0010
192
110
55.0 C
7.5 OS output and polarity
The OS output is an open-drain output and its state represents results of the device
watchdog operation as described in Section 7.1. In order to observe this output state, an
external pull-up resistor is needed. The resistor should be as large as possible, up to
200 k, to minimize the Temp reading error due to internal heating by the high OS sinking
current.
The OS output active state can be selected as HIGH or LOW by programming bit B2
(OS_POL) of register Conf: setting bit OS_POL to logic 1 selects OS active HIGH and
setting bit B2 to logic 0 sets OS active LOW. At power-up, bit OS_POL is equal to logic 0
and the OS active state is LOW.
7.6 OS comparator and interrupt modes
As described in Section 7.1, the device OS output responds to the result of the
comparison between register Temp data and the programmed limits, in registers Tos and
Thyst, in different ways depending on the selected OS mode: OS comparator or
OS interrupt. The OS mode is selected by programming bit B1 (OS_COMP_INT) of
register Conf: setting bit OS_COMP_INT to logic 1 selects the OS interrupt mode, and
setting to logic 0 selects the OS comparator mode. At power-up, bit OS_COMP_INT is
equal to logic 0 and the OS comparator is selected.
The main difference between the two modes is that in OS comparator mode, the OS
output becomes active when Temp has exceeded Tth(ots) and reset when Temp has
dropped below Thys, reading a register or putting the device into shutdown mode does not
change the state of the OS output; while in OS interrupt mode, once it has been activated
either by exceeding Tth(ots) or dropping below Thys, the OS output will remain active
indefinitely until reading a register, then the OS output is reset.
Temperature limits Tth(ots) and Thys must be selected so that Tth(ots) > Thys. Otherwise, the
OS output state will be undefined.
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7.7 OS fault queue
Fault queue is defined as the number of faults that must occur consecutively to activate
the OS output. It is provided to avoid false tripping due to noise. Because faults are
determined at the end of data conversions, fault queue is also defined as the number of
consecutive conversions returning a temperature trip. The value of fault queue is
selectable by programming the two bits B4 and B3 (OS_F_QUE[1:0]) in register Conf.
Notice that the programmed data and the fault queue value are not the same. Table 14
shows the one-to-one relationship between them. At power-up, fault queue data = 0 and
fault queue value = 1.
Table 14.
Fault queue table
Fault queue data
Fault queue value
OS_F_QUE[1]
OS_F_QUE[0]
Decimal
0
0
1
0
1
2
1
0
4
1
1
6
7.8 Shutdown mode
The device operation mode is selected by programming bit B0 (SHUTDOWN) of register
Conf. Setting bit SHUTDOWN to logic 1 will put the device into shutdown mode. Resetting
bit SHUTDOWN to logic 0 will return the device to normal mode.
In shutdown mode, the device draws a small current of approximately 1.0 A and the
power dissipation is minimized; the temperature conversion stops, but the I2C-bus
interface remains active and register write/read operation can be performed. When the
shutdown is set, the OS output will be unchanged in comparator mode and reset in
interrupt mode.
7.9 Power-up default and power-on reset
The LM75B always powers-up in its default state with:
•
•
•
•
•
•
Normal operation mode
OS comparator mode
Tth(ots) = 80 C
Thys = 75 C
OS output active state is LOW
Pointer value is logic 00 (Temp)
When the power supply voltage is dropped below the device power-on reset level of
approximately 1.0 V (POR) for over 2 s and then rises up again, the device will be reset
to its default condition as listed above.
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7.10 Protocols for writing and reading the registers
The communication between the host and the LM75B must strictly follow the rules as
defined by the I2C-bus management. The protocols for LM75B register read/write
operations are illustrated in Figure 7 to Figure 12 together with the following definitions:
1. Before a communication, the I2C-bus must be free or not busy. It means that the SCL
and SDA lines must both be released by all devices on the bus, and they become
HIGH by the bus pull-up resistors.
2. The host must provide SCL clock pulses necessary for the communication. Data is
transferred in a sequence of 9 SCL clock pulses for every 8-bit data byte followed by
1-bit status of the acknowledgement.
3. During data transfer, except the START and STOP signals, the SDA signal must be
stable while the SCL signal is HIGH. It means that the SDA signal can be changed
only during the LOW duration of the SCL line.
4. S: START signal, initiated by the host to start a communication, the SDA goes from
HIGH to LOW while the SCL is HIGH.
5. RS: RE-START signal, same as the START signal, to start a read command that
follows a write command.
6. P: STOP signal, generated by the host to stop a communication, the SDA goes from
LOW to HIGH while the SCL is HIGH. The bus becomes free thereafter.
7. W: write bit, when the write/read bit = LOW in a write command.
8. R: read bit, when the write/read bit = HIGH in a read command.
9. A: device acknowledge bit, returned by the LM75B . It is LOW if the device
works properly and HIGH if not. The host must release the SDA line during this
period in order to give the device the control on the SDA line.
10. A’: master acknowledge bit, not returned by the device, but set by the master or host
in reading 2-byte data. During this clock period, the host must set the SDA line to
LOW in order to notify the device that the first byte has been read for the device to
provide the second byte onto the bus.
11. NA: Not Acknowledge bit. During this clock period, both the device and host release
the SDA line at the end of a data transfer, the host is then enabled to generate the
STOP signal.
12. In a write protocol, data is sent from the host to the device and the host controls the
SDA line, except during the clock period when the device sends the device
acknowledgement signal to the bus.
13. In a read protocol, data is sent to the bus by the device and the host must release the
SDA line during the time that the device is providing data onto the bus and controlling
the SDA line, except during the clock period when the master sends the master
acknowledgement signal to the bus.
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1
2
3
4
5
6
7
8
0
0
1
A2 A1 A0 W
9
1
2
3
4
5
6
7
8
9
1
2
3
0
0
0
0
0
0
0
1
A
0
0
0
4
5
6
7
8
9
SCL
SDA
S
1
A
D4 D3 D2 D1 D0 A
P
device address
START
pointer byte
write
configuration data byte
device
acknowledge
device
acknowledge
device
acknowledge
STOP
001aad624
Fig 7.
Write configuration register (1-byte data)
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
(next)
SCL
SDA
S
1
0
0
1
A2
A1
A0 W
0
A
0
0
0
0
0
0
1
A
device address
START
1
2
3
4
5
6
7
1
0
0
1
A2
A1
device
acknowledge
write
device
acknowledge
pointer byte
8
9
1
2
3
4
(next)
RS
5
6
7
RE-START
8
9
SCL (cont.)
SDA (cont.)
A0 R
A
D7 D6 D5 D4 D3 D2 D1 D0 NA
P
device address
data byte from device
STOP
master not
acknowledged
read
device
acknowledge
001aad625
Fig 8.
Read configuration register including pointer byte (1-byte data)
1
2
3
4
5
6
7
1
0
0
1
A2
A1
8
9
1
2
3
4
5
6
7
8
9
SCL
SDA
S
A0 R
A
D7 D6 D5 D4 D3 D2 D1 D0 NA
P
device address
START
data byte from device
master not
acknowledged
read
device
acknowledge
STOP
001aad626
Fig 9.
Read configuration or temp register with preset pointer (1-byte data)
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13
友台半导体有限公司
UMW LM75B
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCL
(next)
SDA
S
1
0
0
1
A2
A1
A0
W
A
0
0
0
0
0
0
P1
P0
(next)
A
device address
pointer byte
START
device
acknowledge
write
device
acknowledge
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCL (cont.)
SDA (cont.)
D7 D6 D5 D4 D3 D2 D1 D0 A
D7 D6 D5 D4 D3 D2 D1 D0
A
P
MSByte data
LSByte data
STOP
device
acknowledge
device
acknowledge
002aad036
Fig 10. Write Tos or Thyst register (2-byte data)
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
0
SCL
SDA
(next)
S
1
0
0
1
A2 A1 A0 W A
0
0
0
0
0
0
P1 P0 A
RS (next)
device address
START
SCL (cont)
1
SDA (cont)
1
pointer byte
write
2
3
4
device
acknowledge
5 6 7 8
0
0
1
A2 A1 A0 R
RE-START
device
acknowledge
9
1
2
3
4
5
6
7
8
9
A
D7 D6 D5 D4 D3 D2 D1 D0 A'
1
2
3
4
5
6
7
8
9
D7 D6 D5 D4 D3 D2 D1 D0 NA
P
device address
MSByte from device
read
LSByte from device
master
acknowledge
device
acknowledge
master not
acknowledged
STOP
002aad037
Fig 11. Read Temp, Tos or Thyst register including pointer byte (2-byte data)
1
2
3
4
0
0
1
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
A2 A1 A0 R
A
D7 D6 D5 D4 D3 D2 D1 D0 A' D7 D6 D5 D4 D3 D2 D1 D0 NA
SCL
SDA
S
1
P
device address
START
MSByte from device
read
master
acknowledge
device
acknowledge
LSByte from device
master not
acknowledged
STOP
002aad038
Fig 12. Read Temp, Tos or Thyst register with preset pointer (2-byte data)
.
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14
友台半导体有限公司
UMW LM75B
8. Application design-in information
8.1 Typical application
power supply
BUS
10 kΩ
PULL-UP
RESISTORS
0.1 μF
VCC
10 kΩ
10 kΩ
I2C-BUS
SCL
SDA
8
2
1
A2
A1
DIGITAL LOGIC
INTERRUPT LINE
5
6
A0
GND
002aad457
Fig 13. Typical application
8.2 LM75A and LM75B comparison
Table 15.
LM75A and LM75B comparison
Description
LM75A
LM75B
availability of the XSON8U (3 mm 2 mm) package type
no
yes
OS output auto-reset when SHUTDOWN bit is set in interrupt mode
no
yes
support single-byte reading of the Temp registers without bus lockup
no
yes
bus fault time-out (75 ms, 200 ms)
no
yes
minimum data hold time (tHD;DAT)
10 ns
0 ns
ratio of conversion time / conversion period (typical)
100 ms / 100 ms
10 ms / 100 ms
supply current in shutdown mode (typical value)
3.5 A
0.2 A
HBM ESD protection level (minimum)
>2000 V
>4000 V
MM ESD protection level (minimum)
>200 V
>450 V
CDM ESD protection level (minimum)
>1000 V
>2000 V
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15
友台半导体有限公司
UMW LM75B
8.3 Temperature accuracy
Because the local channel of the temperature sensor measures its own die temperature
that is transferred from its body, the temperature of the device body must be stabilized and
saturated for it to provide the stable readings. Because the LM75B operates at a low
power level, the thermal gradient of the device package has a minor effect on the
measurement. The accuracy of the measurement is more dependent upon the definition
of the environment temperature, which is affected by different factors: the printed-circuit
board on which the device is mounted; the air flow contacting the device body (if the
ambient air temperature and the printed-circuit board temperature are much different,
then the measurement may not be stable because of the different thermal paths between
the die and the environment). The stabilized temperature liquid of a thermal bath will
provide the best temperature environment when the device is completely dipped into it. A
thermal probe with the device mounted inside a sealed-end metal tube located in
consistent temperature air also provides a good method of temperature measurement.
If you would like to calculate the effect of self-heating, use Equation 1 below:
Equation 1 is the formula to calculate the effect of self-heating:
T = R th j - a
V DD I DD AV + V OL SDA I OL sin k SDA + V OL EVENT I OL sin k EVEN T
(1)
where:
T = Tj Tamb
Tj = junction temperature
Tamb = ambient temperature
Rth(j-a) = package thermal resistance
VDD = supply voltage
IDD(AV) = average supply current
VOL(SDA) = LOW-level output voltage on pin SDA
VOL(EVENT) = LOW-level output voltage on pin EVENT
IOL(sink)(SDA) = SDA output current LOW
IOL(sink)EVENT = EVENT output current LOW
Calculation example:
Tamb (typical temperature inside the notebook) = 50 C
IDD(AV) = 400 A
VDD = 3.6 V
Maximum VOL(SDA) = 0.4 V
IOL(sink)(SDA) = 1 mA
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友台半导体有限公司
UMW LM75B
VOL(EVENT) = 0.4 V
IOL(sink)EVENT = 3 mA
Rth(j-a) = 56 C/W
Self heating due to power dissipation is:
T = 56 3.6 0.4 + 0.4 3 + 0.4 1 = 56 C W 3.04 mW = 0.17 C
(2)
8.4 Noise effect
The LM75B device design includes the implementation of basic features for a good
noise immunity:
• The low-pass filter on both the bus pins SCL and SDA;
• The hysteresis of the threshold voltages to the bus input signals SCL and SDA, about
500 mV minimum;
• All pins have ESD protection circuitry to prevent damage during electrical surges. The
ESD protection on the address, OS, SCL and SDA pins it to ground. The latch-back
based device breakdown voltage of address/OS is typically 11 V and SCL/SDA is
typically 9.5 V at any supply voltage but will vary over process and temperature. Since
there are no protection diodes from SCL or SDA to VCC, the LM75B will not hold the
I2C lines LOW when VCC is not supplied and therefore allow continued I2C-bus
operation if the LM75B is de-powered.
However, good layout practices and extra noise filters are recommended when the device
is used in a very noisy environment:
•
•
•
•
www.umw-ic.com
Use decoupling capacitors at VCC pin.
Keep the digital traces away from switching power supplies.
Apply proper terminations for the long board traces.
Add capacitors to the SCL and SDA lines to increase the low-pass filter
characteristics.
17
友台半导体有限公司
UMW LM75B
9. Limiting values
Table 16. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VCC
supply voltage
0.3
+6.0
V
VI
input voltage
at input pins
0.3
+6.0
V
II
input current
at input pins
5.0
+5.0
mA
IO(sink)
output sink current
on pin OS
-
10.0
mA
on pin OS
VO
output voltage
Tstg
storage temperature
Tj
junction temperature
0.3
+6.0
V
65
+150
C
-
150
C
10. Recommended operating conditions
Table 17.
Recommended operating characteristics
Symbol
Parameter
VCC
supply voltage
Tamb
ambient temperature
www.umw-ic.com
Conditions
18
Min
Typ
Max
Unit
2.8
-
5.5
V
55
-
+125
C
友台半导体有限公司
UMW LM75B
11. Static characteristics
Table 18. Static characteristics
VCC = 2.8 V to 5.5 V; Tamb = 55 C to +125 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[ 1]
Max
Unit
Tacc
temperature accuracy
Tamb = 25 C to +100 C
2
-
+2
C
Tamb = 55 C to +125 C
3
-
+3
C
Tres
temperature resolution
11-bit digital temp data
-
0.125
-
C
tconv(T)
temperature conversion
time
normal mode
-
10
-
ms
Tconv
conversion period
normal mode
-
100
-
ms
average supply current
IDD(AV)
normal mode:
I2C-bus
inactive
normal mode: I2C-bus active;
fSCL = 400 kHz
-
100
200
A
-
-
300
A
shutdown mode
-
0.2
A
1.0
VIH
HIGH-level input voltage
digital pins (SCL, SDA, A2 to A0)
0.7 VCC
-
VCC + 0.3
V
VIL
LOW-level input voltage
digital pins
0.3
-
0.3 VCC
V
VI(hys)
hysteresis of input voltage SCL and SDA pins
-
300
-
mV
A2, A1, A0 pins
-
150
-
mV
IIH
HIGH-level input current
digital pins; VI = VCC
1.0
-
+1.0
A
IIL
LOW-level input current
digital pins; VI = 0 V
1.0
-
+1.0
A
VOL
LOW-level output voltage
SDA and OS pins; IOL = 3 mA
-
-
0.4
V
IOL = 4 mA
-
-
0.8
V
A
ILO
output leakage current
SDA and OS pins; VOH = VCC
-
-
10
Nfault
number of faults
programmable; conversions in
overtemperature-shutdown fault
queue
1
-
6
-
C
Thys
hysteresis temperature
default value
-
75
-
C
Ci
input capacitance
digital pins
-
20
-
pF
80
overtemperature
shutdown threshold
temperature
Tth(ots)
default value
-
[1]
Typical values are at VCC = 3.3 V and Tamb = 25 C.
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19
友台半导体有限公司
UMW LM75B
002aae198
300
IDD(AV)
(μA)
200
IDD(AV)
(μA)
VCC = 5.5 V
4.5 V
3.3 V
2.8 V
200
100
002aae199
VCC = 5.5 V
4.5 V
3.3 V
2.8 V
300
100
0
−75
−25
25
75
0
−75
125
Tamb (°C)
−25
25
75
125
Tamb (°C)
Fig 14. Average supply current versus temperature;
I2C-bus inactive
Fig 15. Average supply current versus temperature;
I2C-bus active
002aae200
0.5
IDD(sd)
(μA)
0.4
VCC = 5.5 V
4.5 V
3.3 V
2.8 V
0.3
0.3
0.2
0.2
0.1
0.1
VCC = 5.5 V
4.5 V
3.3 V
2.8 V
002aae201
0.5
VOL(OS)
(V)
0.4
0
−75
−25
25
75
0
−75
125
Tamb (°C)
−25
25
75
125
Tamb (°C)
Fig 17. LOW-level output voltage on pin OS
versus temperature; IOL = 4 mA
Fig 16. Shutdown mode supply current
versus temperature
0.5
VOL(SDA)
(V)
0.4
0.3
002aae202
Tacc
(°C)
VCC = 5.5 V
4.5 V
3.3 V
2.8 V
1.0
0.1
0
−75
−1.0
0
0.2
002aae203
2.0
−25
25
75
125
Tamb (°C)
−2.0
−75
−25
25
75
125
Tamb (°C)
Fig 18. LOW-level output voltage on pin SDA
versus temperature; IOL = 4 mA
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Fig 19. Typical temperature accuracy versus
temperature; VCC = 3.3 V
20
友台半导体有限公司
UMW LM75B
12. Dynamic characteristics
Table 19. I2C-bus interface dynamic characteristics[1]
VCC = 2.8 V to 5.5 V; Tamb = 55 C to +125 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fSCL
SCL clock frequency
see Figure 20
0.02
-
400
kHz
tHIGH
HIGH period of the SCL clock
0.6
-
-
s
1.3
-
-
s
tSU;STO
LOW period of the SCL clock
hold time (repeated) START condition
data set-up time
data hold time
set-up time for STOP condition
tf
fall time
tto
time-out time
tLOW
tHD;STA
tSU;DAT
tHD;DAT
SDA and OS outputs;
CL = 400 pF; IOL = 3 mA
[2][3]
100
-
-
ns
100
-
-
ns
0
-
-
ns
100
-
-
ns
-
250
-
ns
75
-
200
ms
[1]
These specifications are guaranteed by design and not tested in production.
[2]
This is the SDA time LOW for reset of serial interface.
[3]
Holding the SDA line LOW for a time greater than tto will cause the LM75B to reset SDA to the idle state of the serial bus communication
(SDA set HIGH).
SDA
tLOW
tf
tSU;DAT
tr
tHD;STA
tSP
tf
0.7 × VDD
0.3 × VDD
tBUF
tr
0.7 × VDD
0.3 × VDD
SCL
tHD;STA
S
tSU;STA
tHIGH
tHD;DAT
Sr
tSU;STO
P
S
002aab271
Fig 20. Timing diagram
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友台半导体有限公司
UMW LM75B
13. Package outline
SOP8: plastic small outline package; 8 leads; body width 3.9 mm
D
A
E
X
c
y
HE
v M A
Z
5
8
Q
A2
pin 1 index
A
(A 3)
A1
θ
Lp
1
L
4
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
D (1)
E (2)
UNIT
A1
A2
A3
bp
c
e
HE
max.
mm
inches
1.75
0.25
0.10
1.45
0.25
1.25
0.49
0.36
0.069
0.010
0.004
0.057
0.01
0.049
0.019 0.0100
0.014 0.0075
0.25
0.19
5.0
4.8
4.0
3.8
0.20
0.19
0.16
0.15
1.27
6.2
5.8
0.05
0.244
0.228
L
Lp
Q
v
1.05
1.0
0.4
0.7
0.6
0.25
0.039
0.041
0.016
0.028
0.024
0.01
w
0.25
0.01
y
Z (1)
0.1
0.7
0.3
0.004
0.028
0.012
θ
o
8
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
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友台半导体有限公司
UMW LM75B
MSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm
D
E
A
X
c
y
HE
v M A
Z
5
8
A2
pin 1 index
(A3)
A1
A
θ
Lp
L
1
4
detail X
e
bp
w M
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
A1
A2
A3
bp
c
UNIT
max.
0.15
0.95
0.45
0.28
mm
1.1
0.25
0.05
0.80
0.25
0.15
D(1)
3.1
2.9
E(2)
3.1
2.9
e
0.65
HE
5.1
4.7
L
0.94
Lp
0.7
0.4
v
0.1
w
0.1
y
Z(1)
0.1
0.70
0.35
θ
6°
0°
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
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