GT24C64A
Advanced
GT24C64A
2-WIRE
64K Bits
Serial EEPROM
Copyright © 2014 Giantec Semiconductor Inc. (Giantec). All rights reserved. Giantec reserves the right to make changes to this specification and its products at any time without
notice. Giantec products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for critical medical or surgical equipment,
aerospace or military, or other applications planned to support or sustain life. It is the customer's obligation to optimize the design in their own products for the best performance
and optimization on the functionality and etc. Giantec assumes no liability arising out of the application or use of any information, products or services described herein. Customers
are advised to obtain the latest version of this device specification before relying on any published information and prior placing orders for products.
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GT24C64A
Table of Contents
1.
2.
3.
4.
5.
6.
7.
8.
9.
Features ...................................................................................................................................................................... 4
General Description .............................................................................................................................................. 4
Functional Block Diagram ................................................................................................................................. 5
Pin Configuration.................................................................................................................................................... 6
4.1 8-Pin SOIC, TSSOP, PDIP and MSOP ................................................................................................... 6
4.2 8-Lead UDFN .......................................................................................................................................... 6
4.3 5-Lead TSOT23 ...................................................................................................................................... 6
4.4 Pin Definition ........................................................................................................................................... 6
4.4 Pin Descriptions ...................................................................................................................................... 6
Device Operation.................................................................................................................................................... 8
5.1 2-WIRE Bus ............................................................................................................................................ 8
5.2 The Bus Protocol .................................................................................................................................... 8
5.3 Start Condition ........................................................................................................................................ 8
5.4 Stop Condition......................................................................................................................................... 8
5.5 Acknowledge ........................................................................................................................................... 8
5.6 Reset ....................................................................................................................................................... 8
5.7 Standby Mode ......................................................................................................................................... 8
5.8 Device Addressing .................................................................................................................................. 8
5.9 Write Operation ....................................................................................................................................... 8
5.10 Read Operation..................................................................................................................................... 9
5.11 Diagrams ............................................................................................................................................. 11
5.12 Timing Diagrams ................................................................................................................................. 14
Electrical Characteristics ............................................................................................................................... 15
6.1 Absolute Maximum Ratings .................................................................................................................. 15
6.2 Operating Range................................................................................................................................... 15
6.3 Capacitance .......................................................................................................................................... 15
6.4 DC Electrical Characteristic .................................................................................................................. 16
6.5 AC Electrical Characteristic .................................................................................................................. 17
Ordering Information.......................................................................................................................................... 18
Top Markings .......................................................................................................................................................... 19
8.1 SOIC package ....................................................................................................................................... 19
8.2 TSSOP package ................................................................................................................................... 19
8.3 UDFN package ..................................................................................................................................... 19
8.4 PDIP package ....................................................................................................................................... 19
8.5 MSOP package ..................................................................................................................................... 20
8.6 TSOT23 package .................................................................................................................................. 20
Package Information .......................................................................................................................................... 21
9.1 SOIC ..................................................................................................................................................... 21
9.2 TSSOP .................................................................................................................................................. 22
9.3 UDFN .................................................................................................................................................... 23
9.4 PDIP ...................................................................................................................................................... 24
9.5 MSOP.................................................................................................................................................... 25
9.6 TSOT23-5 ............................................................................................................................................. 26
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GT24C64A
10. Revision History ................................................................................................................................................. 27
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GT24C64A
1. Features
2
–
TM
Two-Wire Serial Interface, I C
Compatible
–
–
Bi-directional data transfer protocol
Wide-voltage Operation
–
Page write mode
Partial page writes allowed
Addition write lockable page (Identification
Page)
VCC = 1.7V to 5.5V
Speed: 400 KHz (1.7V) and 1 MHz (2.5V~5.5V)
Self timed write cycle: 5 ms (max.)
Standby current (max.): 1 A, 1.7V
Noise immunity on inputs, besides Schmitt trigger
Read current (max.): 0.5 mA, 5.5V
High-reliability
Write current (max.): 0.8 mA, 5.5V
Hardware Data Protection
–
Write Protect Pin
Sequential & Random Read Features
Memory organization: 64Kb (8,192 x 8)
Page Size: 32 bytes
–
–
Endurance: 1 million cycles
Data retention: 100 years
Industrial grade
Packages: SOIC, TSSOP, UDFN, PDIP, TSOT23
and MSOP
Lead-free, RoHS, Halogen free, Green
2. General Description
The GT24C64A is an industrial standard electrically
stored inside the memory array.
erasable programmable read only memory (EEPROM)
In order to refrain the state machine from entering into a
device that utilizes the industrial standard 2-wire interface
wrong state during power-up sequence or a power toggle
for communications. The GT24C64A contains a memory
off-on condition, a power on reset circuit is embedded.
array of 64K bits (8,192x8), which is organized in 32-byte
During power-up, the device does not respond to any
per page.
instructions until the supply voltage (VCC) has reached an
The EEPROM operates in a wide voltage range from 1.7V
acceptable stable level above the reset threshold voltage.
to 5.5V, which fits most application. The product provides
Once VCC passes the power on reset threshold, the device
low-power operations and low standby current. The device
is reset and enters into the Standby mode. This would also
is offered in Lead-free, RoHS, halogen free or Green
avoid any inadvertent Write operations during power-up
package. The available package types are 8-pin SOIC,
stage. During power-down process, the device will enter
TSSOP, UDFN, PDIP, TSOT23 and MSOP.
into standby mode, once VCC drops below the power on
The GT24C64A is compatible to the standard 2-wire bus
reset threshold voltage. In addition, the device will be in
protocol. The simple bus consists of Serial Clock (SCL) and
standby mode after receiving the Stop command, provided
Serial Data (SDA) signals. Utilizing such bus protocol, a
that no internal write operation is in progress. Nevertheless,
Master device, such as a microcontroller, can usually
it is illegal to send a command unless the VCC is within its
control one or more Slave devices, alike this GT24C64A.
operating level.
The bit stream over the SDA line includes a series of bytes,
This product offers an additional page (Identification Page)
which identifies a particular Slave device, an instruction, an
of 32 bytes. The Identification Page can be used to store
address within that Slave device, and a series of data, if
sensitive application parameters which can be (later)
appropriate. The GT24C64A also has a Write Protect
permanently locked in Read-only mode.
function via WP pin to cease from overwriting the data
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GT24C64A
3. Functional Block Diagram
8
SDA
5
SCL
6
WP
7
CONTROL LOGIC
SLAVE ADDRESS
REGISTER &
COMPARATOR
A0
1
A1
2
A2
3
X DECODER
VCC
HIGH VOLTAGE
GENERATOR
TIMING &
CONTROL
WORD ADDRESS
COUNTER
ACK
Y DECODER
CLOCK
DI/O
GND 4
DATA REGISTER
nMOS
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GT24C64A
4. Pin Configuration
4.1 8-Pin SOIC, TSSOP, PDIP and MSOP
4.2 8-Lead UDFN
Top View
Top View
A0
1
8
VCC
A0
1
8
VCC
A1
2
7
WP
A1
2
7
WP
A2
3
6
SCL
A2
3
6
SCL
GND
4
5
SDA
GND
4
5
SDA
4.3 5-Lead TSOT23
Top View
SCL
1
GND
2
SDA
3
5
WP
4
VCC
4.4 Pin Definition
Pin No.
Pin Name
I/O
Definition
1
A0
I
Device Address Input
2
A1
I
Device Address Input
3
A2
I
Device Address Input
4
GND
-
Ground
5
SDA
I/O
6
SCL
I
Serial Clock Input
7
WP
I
Write Protect Input
8
VCC
-
Power Supply
Serial Address and Data input and Data out put
4.4 Pin Descriptions
SCL
and data into and out of the device. The SDA pin is an open
This input clock pin is used to synchronize the data transfer
drain output and can be wired with other open drain or open
to and from the device.
collector outputs. However, the SDA pin requires a pull-up
SDA
resistor connected to the power supply.
The SDA is a bi-directional pin used to transfer addresses
A0, A1, A2
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GT24C64A
The A0, A1 and A2 are the device address inputs.
becomes Write Protected (i.e. the device becomes Read
Typically, the A0, A1, and A2 pins are for hardware
only). When WP is tied to Ground or left floating, the normal
addressing and a total of 8 devices can be connected on a
write operations are allowed.
single bus system. When A0, A1, and A2 are left floating,
VCC
the inputs are defaulted to zero.
Supply voltage
WP
GND
WP is the Write Protect pin. While the WP pin is connected
Ground of supply voltage
to the power supply of GT24C64A, the entire array
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5. Device Operation
The GT24C64A serial interface supports communications
2
loss), or needs to be terminated mid-stream. The reset is
using industrial standard 2-wire bus protocol, such as I C.
initiated when the Master device creates a Start condition.
5.1 2-WIRE Bus
To do this, it may be necessary for the Master device to
The two-wire bus is defined as Serial Data (SDA), and
monitor the SDA line while cycling the SCL up to nine times.
Serial Clock (SCL). The protocol defines any device that
(For each clock signal transition to High, the Master checks
sends data onto the SDA bus as a transmitter, and the
for a High level on SDA.)
receiving devices as receivers. The bus is controlled by
5.7 Standby Mode
Master device that generates the SCL, controls the bus
While in standby mode, the power consumption is minimal.
access, and generates the Start and Stop conditions. The
The GT24C64A enters into standby mode during one of the
GT24C64A is the Slave device.
following conditions: a) After Power-up, while no Op-code is
5.2 The Bus Protocol
sent; b) After the completion of an operation and followed
Data transfer may be initiated only when the bus is not busy.
by the Stop signal, provided that the previous operation is
During a data transfer, the SDA line must remain stable
not Write related; or c) After the completion of any internal
whenever the SCL line is high. Any changes in the SDA line
write operations.
while the SCL line is high will be interpreted as a Start or
5.8 Device Addressing
Stop condition.
The Master begins a transmission on by sending a Start
The state of the SDA line represents valid data after a Start
condition, then sends the address of the particular Slave
condition. The SDA line must be stable for the duration of
devices to be communicated. The Slave device address is 8
the High period of the clock signal. The data on the SDA line
bits format as shown in Figure. 5-5.
may be changed during the Low period of the clock signal.
The four most significant bits of the Slave address are fixed
There is one clock pulse per bit of data. Each data transfer
(1010) for GT24C64A.
is initiated with a Start condition and terminated by a Stop
The next three bits, A0, A1 and A2, of the Slave address are
condition.
specifically related to EEPROM. Up to eight GT24C64A
5.3 Start Condition
units can be connected to the 2-wire bus.
The Start condition precedes all commands to the device
The last bit of the Slave address specifies whether a Read
and is defined as a High to Low transition of SDA when SCL
or Write operation is to be performed. When this bit is set to
is High. The EEPROM monitors the SDA and SCL lines and
1, Read operation is selected. While it is set to 0, Write
will not respond until the Start condition is met.
operation is selected.
5.4 Stop Condition
After the Master transmits the Start condition and Slave
The Stop condition is defined as a Low to High transition of
address byte appropriately, the associated 2-wire Slave
SDA when SCL is High. All operations must end with a Stop
device, GT24C64A, will respond with ACK on the SDA line.
condition.
Then GT24C64A will pull down the SDA on the ninth clock
5.5 Acknowledge
cycle, signaling that it received the eight bits of data.
After a successful data transfer, each receiving device is
The GT24C64A then prepares for a Read or Write operation
required to generate an ACK. The Acknowledging device
by monitoring the bus.
pulls down the SDA line.
5.9 Write Operation
5.6 Reset
5.9.1 Byte Write
The GT24C64A contains a reset function in case the 2-wire
In the Byte Write mode, the Master device sends the Start
bus transmission on is accidentally interrupted (e.g. a power
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GT24C64A
condition and the Slave address information (with the R/W
completed the Write operation, an ACK will be returned and
set to Zero) to the Slave device. After the Slave generates
the host can then proceed with the next Read or Write
an ACK, the Master sends the byte address that is to be
operation.
written into the address pointer of the GT24C64A. After
5.9.4 Write Identification Page
receiving another ACK from the Slave, the Master device
transmits the data byte to be written into the address
memory location. The GT24C64A acknowledges once more
and the Master generates the Stop condition, at which time
the device begins its internal programming cycle. While this
internal cycle is in progress, the device will not respond to
The Identification Page (32 bytes) is an additional page
which can be written and (later) permanently locked in
Read-only mode. It is written by issuing the Write
Identification Page instruction. This instruction uses the
same protocol and format as Page Write (into memory
array), except for the following differences:
any request from the Master device.
Device type identifier = 1011b
5.9.2 Page Write
MSB address bits A15/A5 are don't care except for
The GT24C64A is capable of 32-byte Page-Write operation.
address bit A10 which must be ‗0‘. LSB address bits
A Page-Write is initiated in the same manner as a Byte
A4/A0 define the byte address inside the Identification
Write, but instead of terminating the internal Write cycle
page.
after the first data word is transferred, the Master device
If the Identification page is locked, the data bytes
can transmit up to 31 more bytes. After the receipt of each
transferred during the Write Identification Page instruction
data word, the EEPROM responds immediately with an
are not acknowledged (NoAck).
ACK on SDA line, and the five lower order data word
5.9.5 Lock Identification Page
address bits are internally incremented by one, while the
The
higher order bits of the data word address remain constant.
permanently locks the Identification page in Read-only
If a byte address is incremented from the last byte of a page,
mode. The Lock ID instruction is similar to Byte Write (into
it returns to the first byte of that page. If the Master device
memory array) with the following specific conditions:
should transmit more than 32 bytes prior to issuing the Stop
Device type identifier = 1011b.
condition, the address counter will ―roll over,‖ and the
Address bit A10 must be ‗1‘; all other address bits are
previously written data will be overwritten. Once all 32 bytes
are received and the Stop condition has been sent by the
Master, the internal programming cycle begins. At this point,
Lock
Identification
Page
instruction
(Lock
ID)
don't care.
The data byte must be equal to the binary value xxxx
xx1x, where x is don't care.
all received data is written to the GT24C64A in a single
5.10 Read Operation
Write cycle. All inputs are disabled until completion of the
Read operations are initiated in the same manner as Write
internal Write cycle.
operations, except that the (R/W) bit of the Slave address is
5.9.3 Acknowledge (ACK) Polling
set to ―1‖. There are three Read operation options: current
The disabling of the inputs can be used to take advantage
address read, random address read and sequential read.
of the typical Write cycle time. Once the Stop condition is
5.10.1 Current Address Read
issued to indicate the end of the host's Write operation, the
The GT24C64A contains an internal address counter which
GT24C64A initiates the internal Write cycle. ACK polling
maintains the address of the last byte
can be initiated immediately. This involves issuing the Start
incremented by one. For example, if the previous operation
condition followed by the Slave address for a Write
is either a Read or Write operation addressed to the
operation. If the EEPROM is still busy with the Write
address location n, the internal address counter would
operation, no ACK will be returned. If the GT24C64A has
increment to address location n+1. When the EEPROM
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GT24C64A
receives the Slave Addressing Byte with a Read operation
memory address boundary of the array is reached, the
(R/W bit set to ―1‖), it will respond an ACK and transmit the
address counter ―rolls over‖ to address 0, and the device
8-bit data byte stored at address location n+1. The Master
continues to output data. (Refer to Figure 5-10. Sequential
should not acknowledge the transfer but should generate a
Read Diagram).
Stop condition so the GT24C64A discontinues transmission.
5.10.4 Read Identification Page
If 'n' is the last byte of the memory, the data from location '0'
The Identification Page (32 bytes) is an additional page
will be transmitted. (Refer to Figure 5-8. Current Address
which can be written and (later) permanently locked in
Read Diagram.)
Read-only mode.
5.10.2 Random Address Read
The Identification Page can be read by issuing an Read
Selective Read operations allow the Master device to select
at random any memory location for a Read operation. The
Master device first performs a 'dummy' Write operation by
sending the Start condition, Slave address and byte
address of the location it wishes to read. After the
GT24C64A acknowledges the byte address, the Master
device resends the Start condition and the Slave address,
this time with the R/W bit set to one. The EEPROM then
responds with its ACK and sends the data requested. The
Master device does not send an ACK but will generate a
Stop condition. (Refer to Figure 5-9. Random Address Read
Diagram.)
5.10.3 Sequential Read
Sequential Reads can be initiated as either a Current
Address Read or Random Address Read. After the
GT24C64A sends the initial byte sequence, the Master
device now responds with an ACK indicating it requires
additional data from the GT24C64A. The EEPROM
continues to output data for each ACK received. The Master
device terminates the sequential Read operation by pulling
SDA High (no ACK) indicating the last data word to be read,
followed by a Stop condition. The data output is sequential,
with the data from address n followed by the data from
Identification Page instruction. This instruction uses the
same protocol and format as the Random Address Read
(from memory array) with device type identifier defined as
1011b. The MSB address bits A15/A5 are don't care, the
LSB address bits A4/A0 define the byte address inside the
Identification Page. The number of bytes to read in the ID
page must not exceed the page boundary (e.g.: when
reading the Identification Page from location 10d, the
number of bytes should be less than or equal to 22, as the
ID page boundary is 32 bytes).
5.10.5 Read the lock status
The locked/unlocked status of the Identification page can
be checked by transmitting a specific truncated command
[Identification Page Write instruction + one data byte] to the
device. The device returns an acknowledge bit if the
Identification page is unlocked, otherwise a NoAck bit if the
Identification page is locked.
Right after this, it is recommended to transmit to the device
a Start condition followed by a Stop condition, so that:
Start: the truncated command is not executed because
the Start condition resets the device internal logic,
Stop: the device is then set back into Standby mode by
the Stop condition.
address n+1,n+2 ... etc. The address counter increments by
one automatically, allow the entire memory contents to be
serially read during sequential Read operation. When the
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5.11 Diagrams
Figure 5-1. Typical System Bus Configuration
VCC
SDA
SCL
Master
Transmitter/Receiver
GT24CXX
Figure 5-2. output Acknowledge
SCL from Master
1
8
9
Data Output from
Transmitter
TAA
Data Output from
Receiver
TAA
ACK
SDA
STOP
CONDITION
SCL
START
CONDITION
Figure 5-3. Start and Stop Conditions
Figure 5-4. Data Validity Protocol
Data Change
SCL
Data Stable
Data Stable
SDA
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Figure 5-5. Slave Address
Bit
7
6
5
4
3
2
1
0
1
0
1
0
A2
A1
A0
R/W
Figure 5-6. Byte Write
S
T
A
R
T
W
R
I
T
E
Device
Address
SDA
Bus
Activity
M
S
B
Word Address Word Address
A
A
A
C* * *
C
C
K
K
K
L
M
S
S
B
B
R/W
S
T
O
P
Data
A
C
K
* =Don‘t care bits
Figure 5-7. Page Write
S
T
A
R
T
Device
Address
SDA
Bus
Activity
M
S
B
W
R
I
T
E Word Address(n) Word Address(n)
A
A
A
C** *
C
C
K
K
K
L
M
S
S
B
B
R/W
Data(n)
Data(n+1)
A
C
K
S
T
O
P
Data(n+31)
A
C
K
A
C
K
* =Don‘t care bits
Figure 5-8. Current Address Read
S
T
A
R
T
R
E
A
D
Device
Address
Data
A
C
K
SDA
Bus
Activity
M
S
B
L
S
B
R/W
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GT24C64A
Figure 5-9. Random Address Read
S
T
A
R
T
W
R
I
T
E
Device
Address
SDA
Bus
Activity
Word
Address(n)
A
C* **
K
M
S
B
L
S
B
R/W
S
T
A
R
T
Word
Address(n)
A
C
K
Device
Address
R
E
A
D
A
C
K
S
T
O
P
Data n
A
C
K
N
O
* =Don‘t care bits
A
C
K
DUMMY WRITE
Figure 5-10. Sequential Read
Device
Address
SDA
Bus
Activity
R
E
A
D
Data Byte n
A
C
K
Data Byte n+1
A
C
K
S
T
O
Data Byte n+x P
Data Byte n+2
A
C
K
A
C
K
N
O
R/W
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GT24C64A
5.12 Timing Diagrams
Figure 5-11. Bus Timing
TR
TF
THIGH
TLOW
TSU:STO
SCL
TSU:STA
THD:STA
TSU:DAT
THD:DAT
TBUF
SDAIN
TAA
TDH
SDAOUT
TSU:WP THD:WP
WP
Figure 5-12. Write Cycle Timing
SCL
SDA
ACK
Word n
TWR
STOP
Condition
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GT24C64A
6. Electrical Characteristics
6.1 Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
VS
Supply Voltage
-0.5 to + 6.5
V
VP
Voltage on Any Pin
-0.5 to + 6.5
V
TBIAS
Temperature Under Bias
–55 to +125
°C
TSTG
Storage Temperature
–65 to +150
°C
IOUT
Output Current
5
mA
Note: Stress greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other condition outside those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
6.2 Operating Range
Range
Ambient Temperature (TA)
VCC
Industrial
–40°C to +85°C
1.7V to 5.5V
Note: Giantec offers Industrial grade for Commercial applications (0C to +70C).
6.3 Capacitance
Symbol
Parameter[1, 2]
Conditions
Max.
Unit
CIN
Input Capacitance
VIN = 0V
6
pF
CI/O
Input / Output Capacitance
VI/O = 0V
8
pF
Notes:
[1]
Tested initially and after any design or process changes that may affect these parameters and not 100% tested.
Test conditions: TA = 25°C, f = 1 MHz, VCC = 5.0V.
[2]
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GT24C64A
6.4 DC Electrical Characteristic
Industrial: TA = –40°C to +85°C, VCC = 1.7V ~ 5.5V
Symbol
Parameter
[1]
VCC
Test Conditions
Min.
Typ.
Max.
Unit
1.7
5.5
V
VCC
Supply Voltage
VIH
Input High Voltage
0.7*VCC
VCC+1
V
VIL
Input Low Voltage
-1
0.3* VCC
V
ILI
Input Leakage Current
5V
—
2
μA
ILO
Output Leakage
5V
—
2
μA
VIN = VCC max
Current
VOL1
Output Low Voltage
1.7V
IOL = 0.15 mA
—
0.2
V
VOL2
Output Low Voltage
2.5V
IOL = 2.1 mA
—
0.4
V
ISB1
Standby Current
1.7V
VIN = VCC or GND
—
0.2
1
μA
ISB2
Standby Current
2.5V
VIN = VCC or GND
—
0.3
1
μA
ISB3
Standby Current
5.5V
VIN = VCC or GND
—
0.5
1
μA
1.7V
Read at 400 KHz
—
0.15
mA
2.5V
Read at 1 MHz
—
0.2
mA
5.5V
Read at 1 MHz
—
0.5
mA
1.7V
Write at 400 KHz
—
0.5
mA
2.5V
Write at 1 MHz
—
0.6
mA
5.5V
Write at 1 MHz
—
0.8
mA
ICC1
ICC2
Read Current
Write Current
Note: The parameters are characterized but not 100% tested.
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GT24C64A
6.5 AC Electrical Characteristic
Industrial: TA = –40°C to +85°C, Supply voltage = 1.7V to 5.5V
Symbol
Parameter
[1] [2]
1.7VVCC5.5V
Min.
Max.
FSCL
SCK Clock Frequency
TLOW
Clock Low Period
1200
—
THIGH
Clock High Period
600
2.5VVCC5.5V
Min.
400
Unit
Max.
1000
KHz
600
—
ns
—
400
—
ns
TR
Rise Time (SCL and SDA)
—
300
—
300
ns
TF
Fall Time (SCL and SDA)
—
300
—
100
ns
TSU:STA
Start Condition Setup Time
500
—
200
—
ns
TSU:STO
Stop Condition Setup Time
500
—
200
—
ns
THD:STA
Start Condition Hold Time
500
—
200
—
ns
TSU:DAT
Data In Setup Time
100
—
40
—
ns
THD:DAT
Data In Hold Time
0
—
0
—
ns
100
900
50
400
ns
100
—
50
—
ns
—
5
—
5
ms
1000
—
400
—
ns
TAA
Clock to Output Access time (SCL
Low to SDA Data Out Valid)
TDH
Data Out Hold Time (SCL Low to
SDA Data Out Change)
TWR
Write Cycle Time
TBUF
Bus Free Time Before New
Transmission
TSU:WP
WP pin Setup Time
1000
—
400
THD:WP
WP pin Hold Time
1000
—
400
—
ns
—
100
—
50
ns
T
Notes:
Noise Suppression Time
[1]
[2]
The parameters are characterized but not 100% tested.
AC measurement conditions:
RL (connects to VCC): 1.3 kΩ (2.5V, 5.0V), 10 kΩ (1.7V)
CL = 100 pF
Input pulse voltages: 0.3*VCC to 0.7*VCC
Input rise and fall times: ≤ 50 ns
Timing reference voltages: half VCC level
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GT24C64A
7. Ordering Information
Industrial Grade: -40°C to +85°C, Lead-free
Voltage Range
Part Number*
Package (8-pin)*
1.7V to 5.5V
GT24C64A-2GLI-TR
150-mil SOIC
GT24C64A-2ZLI-TR
3 x 4.4 mm TSSOP
GT24C64A-2UDLI-TR
2 x 3 x 0.55 mm UDFN
GT24C64A-2PLI
300mil PDIP
GT24C64A-2TLI-TR
2.9 x 1.6 mm TSOT23
GT24C64A-2SLI-TR
3 x 3 mm MSOP
*
1. Contact Giantec Sales Representatives for availability and other package information.
2. The product is packed in tape and reel ―-TR‖ (4K per reel), except UDFN is 5K per reel.
3. Refer to Giantec website for related declaration document on lead free, RoHS, halogen free or Green, whichever is applicable.
4. Giantec offers Industrial grade for Commercial applications (0C to +70C).
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GT24C64A
8. Top Markings
8.1 SOIC package
G: Giantec Logo
464A-2GLI: GT24C64A-2GLI-TR
YWW: Date Code, Y=year, WW=week
8.2 TSSOP package
GT: Giantec Logo
464A-2ZLI: GT24C64A-2ZLI-TR
YWW: Date Code, Y=year, WW=week
8.3 UDFN package
GT: Giantec Logo
46A: GT24C64A-2UDLI-TR
YWW: Date Code, Y=year, WW=week
8.4 PDIP package
GT: Giantec Logo
2464A-2PLI: GT24C64A-2PLI
YWW: Date Code, Y=year, WW=week
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GT24C64A
8.5 MSOP package
GT: Giantec Logo
464A2SU: GT24C64A-2SLI-TR
YWW: Date Code, Y=year, WW=week
8.6 TSOT23 package
464A: GT24C64A-2TFLI-TR
YW: Date Code, Y=year, WW=week
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GT24C64A
9. Package Information
9.1 SOIC
8L 150mil SOIC Package Outline
Detail A
D
E
E1
b
ZD
Detail A
GAUGE
PLANE
A
SEATING
PLANE
e
SYMBOLS
A1
DIMENSIONS IN MILLIMETERS
Θ
DIMENSIONS IN INCHES
MIN
NOM
MAX
MIN
NOM
MAX
A
1.35
--
1.75
0.053
--
0.069
A1
0.10
--
0.25
0.004
--
0.010
b
0.33
--
0.51
0.013
--
0.020
D
4.80
--
5.00
0.189
--
0.197
Note:
E
5.80
--
6.20
0.228
--
0.244
1. Controlling Dimension:MM
E1
3.80
--
4.00
0.150
--
0.157
2. Dimension D and E1 do not include
Mold protrusion
3. Dimension b does not include
dambar protrusion/intrusion.
4. Refer to Jedec standard MS-012
5. Drawing is not to scale
e
L
1.27 BSC.
0.38
L1
Θ
--
0.050 BSC.
1.27
0.015
0.25 BSC.
ZD
--
0.050
0.010 BSC.
0.545 REF.
0
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L
L1
0.021 REF.
8°
0
--
8°
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21/27
GT24C64A
9.2 TSSOP
8L 3x4.4mm TSSOP Package Outline
D
C
e
8
L
E
E1
1
Θ
12°(4X)
A2
0.10mm
b
A1
A
SYMBOLS
A
A1
A2
b
c
D
E
E1
e
L
Θ
DIMENSIONS IN MILLIMETERS
MIN
-0.05
0.80
0.19
0.09
2.90
4.30
0.45
0
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Note:
1. Controlling Dimension:MM
2. Dimension D and E do not include Mold protrusion
3. Dimension b does not include dambar protrusion/intrusion.
4. Refer to Jedec standard MO-153 AA
5. Drawing is not to scale
6. Package may have exposed tie bar.
NOM
--1.00
--3.00
4.40
6.4 BSC
0.65 BSC
0.60
--
DIMENSIONS IN INCHES
MAX
1.20
0.15
1.05
0.30
0.20
3.10
4.50
MIN
-0.002
0.031
0.007
0.004
0.114
0.169
0.75
8°
0.018
0
NOM
--0.039
--0.118
0.173
0.252 BSC
0.026 BSC
0.024
--
MAX
0.047
0.006
0.041
0.012
0.008
0.122
0.177
0.030
8°
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GT24C64A
9.3 UDFN
8L 2x3mm UDFN Package Outline
D2
D
e
K
E2
E
PIN#1
IDENTIFICATION
CHAMFER
L
PIN#1 DOT
BY MARKING
BOTTOM VIEW
TOP VIEW
b
A
A1
A2
SIDE VIEW
SYMBOLS
DIMENSIONS IN MILLIMETERS
A
A1
b
A2
D
D2
E
E2
e
K
L
MIN
0.50
0.00
0.18
1.25
1.15
0.40
0.20
NOM
0.55
-0.25
0.152 REF
2.00 BSC
1.40
3.00 BSC
1.30
0.50 BSC.
-0.30
DIMENSIONS IN INCHES
MAX
0.60
0.05
0.30
MIN
0.020
0.000
0.007
1.50
0.049
1.40
0.045
-0.40
0.016
0.008
NOM
0.022
-0.010
0.006 REF
0.079 BSC
0.055
0.118 BSC
0.051
0.020 BSC.
-0.012
MAX
0.024
0.002
0.012
0.059
0.055
-0.016
Note:
1. Controlling Dimension:MM
2. Drawing is not to scale
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GT24C64A
9.4 PDIP
8L 300mil PDIP Package Outline
D
E
E1
eB
ZD
A2
A1
A
L
Note:
1. Controlling Dimension:MM
2. Dimension D and E1 do not include Mold protrusion
3. Dimension b2 and b3 do not include dambar protrusion/instrusion
4. Drawing is not to scale
b3
e
SYMBOLS
b
DIMENSIONS IN MILLIMETERS
A
A1
A2
b
b2
b3
D
E
E1
e
eB
L
ZD
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MIN
3.60
0.38
3.25
0.36
1.40
0.81
9.01
7.49
6.20
8.12
3.18
NOM
---------2.54 BSC.
--0.825 REF.
DIMENSIONS IN INCHES
MAX
4.20
0.75
3.45
0.56
1.65
1.17
9.53
8.26
6.60
MIN
0.142
0.015
0.128
0.014
0.055
0.032
0.355
0.295
0.244
9.65
3.80
0.320
0.125
NOM
---------0.100 BSC.
--0.032 REF.
MAX
0.165
0.030
0.136
0.022
0.065
0.046
0.375
0.325
0.260
0.380
0.150
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GT24C64A
9.5 MSOP
8L 120mil MSOP package Outline
D
C
e
L
E
12°(4X)
E1
A2
θ
A
A1
b
SYMBOLS
DIMENSIONS IN MILLIMETERS
A
A1
A2
b
C
D
E
E1
e
L
Θ
DIMENSIONS IN INCHES
MIN
NOM
MAX
MIN
NOM
MAX
-0.05
0.75
0.25
0.13
2.90
2.90
--0.85
--3.00
3.00
4.90 BSC
0.65 BSC
---
1.10
0.15
0.95
0.40
0.23
3.10
3.10
-0.002
0.030
0.010
0.005
0.114
0.114
0.043
0.006
0.037
0.016
0.009
0.122
0.122
0.55
7°
-0
--0.033
--0.118
0.118
0.193 BSC
0.026 BSC
---
-0
0.022
7°
Note:
1. Controlling Dimension:MM
2. Dimension D and E do not include Mold protrusion
3. Refer to Jedec standard MO187
4. Drawing is not to scale
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GT24C64A
9.6 TSOT23-5
5L 2.9x1.6mm TSOT23
D
0.25
b
L
E1
E
Θ
c
e
e1
Note:
1. Dimension D and E1 do not include Mold protrusion
2. Dimension b does not include dambar protrusion/intrusion.
A2
A
3. Refer to Jedec standard MO-193 AB
4. Drawing is not to scale
A1
SYMBOLS
DIMENSIONS IN MILLIMETERS
MIN
NOM
MAX
MIN
NOM
MAX
A
--
--
0.900
--
--
0.035
A1
0.020
0.055
0.090
0.001
--
0.004
A2
0.700
0.750
0.800
0.028
0.030
0.031
b
0.350
--
0.500
0.014
--
0.020
c
0.080
--
0.200
0.003
--
0.008
D
2.820
2.920
3.020
0.111
0.115
0.119
E
2.650
2.800
2.950
0.104
0.110
0.116
E1
1.600
1.650
1.700
0.063
0.065
0.067
e
0.95(BSC)
e1
1.90(BSC)
0.037(BSC)
0.075(BSC)
L
0.300
0.450
0.600
0.012
0.018
0.024
Θ
0°
--
8°
0°
--
8°
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DIMENSIONS IN INCHES
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GT24C64A
10. Revision History
Revision
Date
Descriptions
C0
Feb. 2014
Initial version
C1
Jun. 2016
Update table6.1 and table6.4
C2
Nov.2017
Add TSOT23-5 package information
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