HT8563ARZ

HT8563A CMOS Real-time clock/calendar Microcircuit HT8563A is essentially the complete binary-decimal digital watch with calendar, alarm, timer and possesses low power consumption. Addresses and data are transferred in series via the double wire bi-directional bus. The microcircuit is intended for count of real time in hours, minutes and seconds, count of week days, date, month and year. The last day of the month is automatically adjusted for the months with fewer, than 31 days, including correction for the leap year. The watch functions in the 24 hour mode. The microcircuit HT8563A has the built-in power control circuit, which determines the power level < 1V and forms the bit, signaling, that information about the real time may not be correct. Functions and Features  count of seconds, minutes, hours, week days, date, months and years with consideration of leap years (until 2100);  400 kHz, double wire serial interface;  programmed orthogonal output signal;  function programming of alarm, timer and interruption;  automatic determination of the supply voltage drop;  consumption current of less, than 450 nA with supply of 2V with the operating oscillator;  operating temperature range: -40С – 85С. tructural Diagram HT8563A OSCI OSCILLATOR 32.768 kHz DIVIDER CLOCK OUT CLKOUT OSCO CONTROL MONITOR (1) 00 CONTROL_STATUS_1 01 CONTROL_STATUS_2 0D CLKOUT_CONTROL 02 VL_SECONDS 03 MINUTES 04 HOURS POWER ON RESET TIME VDD VSS WATCH DOG 05 DAYS 06 WEEKDAYS 07 CENTURY_MONTHS 08 YEARS ALARM FUNCTION SDA SCL I2C-BUS INTERFACE 09 MINUTE_ALARM 0A HOUR_ALARM 0B DAY_ALARM 0C WEEKDAY_ALARM INTERRUPT INT TIMER FUNCTION HT8563A 0E TIMER_CONTROL 0F TIMER Rev. 01 HT8563A Operating temperature range HT8563A Operating temperature range of the microcircuit HT8563A: ТА = - 40 ... + 85 С. Limit operating mode HT8563A Limit and limit permissible operating modes of the microcircuit HT8563A are listed in the table Norm Parameter Description, IdentifiLimit Permissible Limit Measurement Unit cation Not less Not over Not less Not over VDD 1.0 5.5 –0.5 6.5 Supply voltage, V Ptot Dissipated power, mWt 300 0 Input voltage SCL, SDA, OSCI, V 5.5 –0.5 6.5 VI 0 Output voltage CLKOUT,INT, V 5.5 –0.5 6.5 VO Direct input or output current via –10 10 IIO any pin, mА All voltages are listed relative to ground. Under influence of the limit mode serviceability of the microcircuits is not guaranteed. After plotting the limit mode serviceability is guaranteed in the limit permissible mode. Electric Parameters HT8563A Electric parameters of the microcircuit HT8563A at the temperature of ТА = –40...+ 85С, VCC = 4.5 – 5.5 В are indicated in the table Norm Parameter Description, Identifi Measurement Mode Not Not over Remark Measurement Unit -cation less 1 2 3 4 5 6 VDD 1.8 5.5 I2C bus –active; FSCL = 400 kHz Supply voltage, V 1.0 5.5 1,2 in the non-active mode ILI VIN =VDD; VIN =VSS 1 Input leakage current, µА I V =V ; V =V Output leakage current, µА 1 LO OUT DD OUT SS IDD1 Consumption current, µА 800 CLKOUT–off, FSCL =400 kHz 200 CLKOUT–off, FSCL =100 kHz 0.55 1,2 CLKOUT–off, FSCL =0 kHz, VDD=5V 0.45 1,2 CLKOUT–off, FSCL =0 kHz, VDD=2V VIL VSS Low level input voltage, V 0.3VDD VIH VDD High level input voltage, V 0.7VDD IOL1 Low level output current at VOL = 0.4 V, VDD =5 V 1 pin CLKOUT, mА IOH1 High level output current at VOH = 4.6 V, VDD =5 V 1 pin CLKOUT, mА IOL2 Low level output current at 1 VOL = 0.4 V, VDD =5 V pin INT, mА Rev. 01 HT8563A 1 2 3 4 5 IOL3 Low level output current at VOL = 0.4 V, VDD =5 3 pin SDA, mА V VLOW Supply low level, detected 1 by the circuit, V Remarks 1 Ta=(25 ± 5)oC 2 Parameters of the quartz oscillator: fOSC=32.768 kHz, RS≤40 kOhm, CL=8 пF Dynamic parameters of the microcircuit ТА = –40...+ 85С, VCC = 4,5 – 5,5 V are listed in the table Parameter Description, Measurement Unit HT8563A at the 6 1 temperature Identification Measurement Mode Cycle frequency SCL, kHz fSCL – 0 400 Time of bus vacant condition between the conditions STOP and START, usec tBUF – 4.7 – – 0.6 – – 1.3 – Hold time (repeated) of the condition START, usec Low condition duration of the cycle pulse SCL, usec tHD:STA tLOW Norm Not less Not over 1) High condition duration of the cycle pulse tHIGH 0.6 – – SCL, usec Presetting time for the repeated condition tSU:STA 0.6 – – START, usec 2) tHD:DAT – 0 – Data hold time, usec tSU:DAT – – Data presetting time, nsec 100 – – Rise time for signals SDA and SCL, nsec 300 tR – – Drop time for signals SDA and SCL, nsec 300 tF Presetting time for the condition STOP, tSU:STO 0.6 – – usec Total capacitance load on each bus line, CB 400 – – pF CI/O – Capacity input/output, pF 10 10 Load capacitance of the quartz resonator, – СLX 12.5 12.5 pF 1) After this time interval the first cycle signal is formed; 2) The device should internally ensure the hold time, at least, 300 nsec for the signal SDA (relative to VIHMIN of the signal SCL) in order to overlap the indeterminancy area of the signal SCL drop front Maximum value tHD:DAT should be definite in that case, if the device does not increase duration of the low condition (tLOW ) of the signal SCL Rev. 01 HT8563A Timing diagramm HT8563A Operation description HT8563A operates as the «slave» device on the serial bus. For access to it expedient to set the condition START and transfer after the register address the device identification code.The next registers can be address in series till the condition STOP is preset. With VCC below 1.8 V, access granting to the device by the serial interface is not guaranteed. The current time is counted with the supply voltage 1 ÷ 5.5 V. When the supply level becomes lower, than 1V, the bit VL=1 is formed, signaling, that the information about the current time may be incorrect. Description of Signals VDD– connection of the constant supply. VDD – input from +1 till +5 V. With supply < 1.8 V access to the interface circuit is not guaranteed. INT – interruption output. Interruption condition is formed with coincidence of the current time with the alarm settings, or with attainment of the condition “0” of the timer countdown. Interruption, formed from the alarm, forms the continous signal, and from the timer can be both continous and pulse one. SCL (Input of serial synchrosignal) – SCL is used for synchronization of the dasta transfer by the serial interface. SDA (Input/Output of serial data) – SDA is input/output for the double wire serial interface. Output SDA is the open drain, for which the external load resistor is required to be connected. CLKOUT (Former output of the orthogonal signal) – For output activation the bit FE is preset to “1”. CLKOUT generates the orthogonal signal of four different frequencies (1 Hz, 32 Hz, 1 kHz, 32 kHz). Output CLKOUT is essentially the open drain, for which the external load resistor is required to be connected. OSCI, OSCO – connection of the standard quartz resonator for the frequency 32.768 kHz. Capacitance load of the internal oscillator for the quartz resonator is equal to Rev. 01 HT8563A 12 pF. HT8563A can operate from the external oscillator with the frequency 32.768 kHz. With this configuration the output OSCI is connected to the signal external oscillator, and OSCO is left unconnected. Watch and Calendar Acquisition of information on time and date is performed by means of reading the appropriate register bytes. Presetting and time and calendar initialization is performed by means of the appropriate bytes. Information, contained in the time, calendar and alarm registers, is essentially the binary-decimal code. Bit 7 of register 2 is essentially the indication bit of the supply level decrease. < 1V (VL). When this bit = “1” , this signifies, that the supply voltage was below the norm, and the information on the current time may be unreliable. When switching power supply on, all register bits are preset to "0", with the exception of bits FE, VL, TD1, TD0, TESTC and AE, which are preset to "1". When applying the signal “START” on the double wire bus, the current time transfer occurs from the counters to the auxiliary set of registers. The data on time are read out from these auxiliary registers, while the watch continue to operate. This eliminates the necessity in the repeated reading in case of updating the basic registers in the access process. Registers RTC HT8563A Address Data Registers / Range D7 D6 D5 D4 D3 D2 D1 D0 0 STOP 0 0 0 Control 1 0 0 TI/TP TEST C AF 0 01H TEST 1 0 TF AIE TIE Control 2 02H 03H 04H 05H 06H 07H VL х х х х С 08H 09H AE 0AH 0BH 0CH AE AE AE х х х 0DH FE х х 0EH 0FH TE х х 00H Tens of seconds Tens of minutes х Tens of hours Tens of date х х х х х х 10 М. х Tens of years Tens of minutes Tens of hours Tens of date х х х х х х х Value of timer Units of seconds Units of minutes Units of hours Units of date Day of week Units of month Seconds Minutes Hours Dates Day of week Century / month Units of years Units of minutes Year Minutes of alarm Hours of alarm Date of alarm Week day of alarm Control of CLKOUT Control of timer Timer Units of hours Units of date Day of week х FD1 FD0 х TD1 TD0 00 – 59 00 – 59 00 – 23 01 – 31 0–6 0-1/0112 00 – 99 00 – 59 00 – 23 01 – 31 0–6 Rev. 01 HT8563A Control Registers Control Register 1 TEST1 (activation of test mode) – This bit, preset to logic “1”, activates the test mode, with logic “0” normal functioning of the circuit. STOP – This bit, preset to logic “1” in the test mode perform the zero setting of all dividers, with logic “0” – normal functioning of the circuit. TESTC (activation of the test mode) – This bit, preset to logic “1”, activates the test mode, with logic “0” normal functioning of the circuit. Control Register 2 TI/TP (formation of the pulse interruption signal at output INT) – This bit, preset to logic “0”, with appearance of the timer flag TF at output INT forms the constant interruption signal of the low level. The bit, preset to logic “1” at output INT, forms the interruption pulse signal (signal frequencies are listed in the table). Period INT (sec).[1] Timer Input Frequency (Hz) N>1 4096 N =1 [2] 1/8192 1/4096 64 1/128 1/64 1 1/64 1/64 1/60 1/64 1/64 [1] TF and INT become active simultaneously. [2] N – value, loaded to the timer register. Timer is stopped with N = 0. AF (alarm flag) - bit, in logic “1” informs about interruption by actuation of the alarm, by means of software the bit AF can be reset only. TF (timer flag) - bit, in logic “1” informs about interruption by actuation of the timer, by the software means the bit TF can be reset only. AIE (activation of alarm) - bit, preset to logic “1”, activates operation of the alarm. TIE (activation of timer) - bit, preset to logic “1”, activates operation of the alarm. Control Register CLKOUT. FE (output activation CLKOUT): This bit, preset to logic “1”, activates output CLKOUT. Frequency of the output orthogonal signal is determined by the bits FD0 and FD1. FD – bits determine the frequency of the output orthogonal signal, when output of the orthogonal signal is activated. The frequencies are listed in the table, which can be selected by bits FD. FD1 FD0 Frequency CLKOUT 0 0 1 1 0 1 0 1 32.768 kHz 8.192 kHz 4.096 kHz 1 Hz Rev. 01 HT8563A Timer Control Register TE (timer activation): This bit, preset to logic “1”, activates the frequency application to the timer input from the oscillator. The signal frequency is determined by bits TD0 and TD1. ТD1 ТD0 Timer Input Frequency 0 0 1 1 0 1 0 1 4096 Hz 64 Hz 1 Hz 1 / 60 Hz Double Wire Serial Data Bus HT8563A supports the bi-directional double wire bus and the data transfer protocol. The bus can be controlled by the “master” device, which generates the cycle signal (SCL), controls access to the bus, generates the conditions START and STOP. Typical bus configuration with the double wire is indicated in the Figure. VDD SDA SCL 1F MASTER TRANSMITTER/ RECEIVER 100 nF VDD SCL CLOCK CALENDAR OSCI OSCO HT8563A SDA VDD VSS R R R: pull-up resistor tr R= Cb SDA SCL (I2C-bus) Rev. 01 HT8563A Data transfer can be started only when the bus is not busy. In the process of the data transfer, the data line should remain stable, while the cycle signal line is in the HIGH condition. Alterations of the data line conditions at that moment, when the cycle line is in the high condition, will be regarded as the control signals. In compliance with this the following conditions are determined: Bus is not busy: both lines of data and cycle signal are in the HIGH condition. Data transfer start: Alteration of the data line condition during transition from HIGH to LOW, while the cycle line is in the HIGH condition, is determined as the status START. Depending on the status of the bit R /W , two types of transfer are possible: 1.Data are transferred from the «master» transmiter to the «slave» receiver. The first byte, transferred by the «master» one, is the address of the «slave» one. Then follows sequence of the data bytes. The «slave» one returns the reception confirmation bits after each received byte. Order of the data transfer: the first one is the most senior digit (MSB). 2.Data are transferred from the «slave» transmiter to the «master» receiver. The first byte (address of «slave») is transferred to the «master» one. Then the «master» returns the confirmation bit. This follows after the «slave» one of the data sequence. The «master» one returns the reception confirmation bit after each received byte, with exception of the last byte. After reception of the last byte the reception confirmation bit does not return. The «master» device generates all cycle pulse and the conditions START and STOP. Transmission completes with emergence of the condition STOP or the repeated emergence of the condition START. As the repeated condition START is the beginning of the next serial transmission, then the bus is not vacated. Data transfer order: the first one is the most senior digit (MSB). HT8563A : 1.Mode of the «slave» receiver (writing mode of HT8563A): Serial data and cycles are received via SDA and SCL appropriately. After transfer of each byte the confirming bit is transferred. Conditions START and STOP are understood as the start and end of the serial transmission. Address recognition is performed by the hardware means after reception of the address of the «slave» one and the direction bit. The address byte is the first byte, received after emergence of the condition START, generated by the «master» one. Address byte contains seven address bits HT8563A, equal to 1010001, accompanied by the direction bit ( R /W ), which is equal to 0 for writing. After reception and decoding the address HT8563A provides confirmation on the line SDA. After confirmation by HT8563A of the «slave» address and the write bit, the «master» one transmits the register address of HT8563A. Thus, the register indicator will be set in HT8563A. Then the «master» one will start to transfer each data byte with the subsequent confirmation reception of each byte receipt. Upon completion of writing the «master» one will form the condition STOP, for termination of the data transfer. Rev. 01 HT8563A Data writing – mode of the receiver 2. Mode of the «slave» transmitter (read-out mode from HT8563A): The first byte is accepted and is processed as in the mode of the «slave» receiver. But in this mode the direction bit will indicate, that the transmission direction is altered. The serial data are transferred by HT8563A by means of SDA, the cycle pulses – by means of SCL. The statuses of START and STOP are recognized as the start and end of transmission in series. The address byte is the first byte, received after emergence of the status START, generated by the «slave» one. The address byte contains the seven address bits HT8563A, equal to 1010001, accompanied with the direction bit ( R /W ), which is equal to 1 for reading. After reception and decoding the address byte HT8563A accepts confirmation from the line SDA. Then HT8563A starts to transmit the data from the address, to which the register indicator indicates. If the register indicator is not written prior to initialization of the writing mode, then the first read address will be the last address, stored in the register indicator. HT8563A should transmit the bit of «nonconfirmation», in order to complete reading. Pins Description Microcircuit Pin Identification Number 01 OSCI 02 OSCO 03 INT VSS 04 05 SDA 06 SCL 07 CLKOUT VDD 08 Purpose of Pin Pin for connection of the quartz resonator Pin for connection of the quartz resonator Interruption output Common pin Input / Output of data Synchrosignal input Frequency divider output Supply source pin VDD OSCI CLKOUT OSCO HT8563A SCL INT VSS SDA HT8563A Rev. 01 HT8563A DIP8 Unit:mm SOP8 Unit:mm Rev. 01 HT8563A TSSOP 8 U n i t : mm Rev. 01