X1000/E
IoT Application Processor
Data Sheet
Release Date: Sep. 6, 2017
X1000/E IoT Application Processor
Data Sheet
Copyright © 2005-2017 Ingenic Semiconductor Co., Ltd. All rights reserved.
Disclaimer
This documentation is provided for use with Ingenic products. No license to Ingenic property rights is
granted. Ingenic assumes no liability, provides no warranty either expressed or implied relating to the
usage, or intellectual property right infringement except as provided for by Ingenic Terms and
Conditions of Sale.
Ingenic products are not designed for and should not be used in any medical or life sustaining or
supporting equipment.
All information in this document should be treated as preliminary. Ingenic may make changes to this
document without notice. Anyone relying on this documentation should contact Ingenic for the current
documentation and errata.
Ingenic Semiconductor Co., Ltd.
Ingenic Headquarters, East Bldg. 14, Courtyard #10,
Xibeiwang East Road, Haidian District, Beijing 100193, China
Tel: 86-10-56345000
Fax: 86-10-56345001
Http: //www.ingenic.com
CONTENTS
CONTENTS
1 Overview .......................................................................................... 1
1.1
Block Diagram ......................................................................................................................... 1
1.2
Features .................................................................................................................................. 1
1.2.1
CPU Core ........................................................................................................................ 1
1.2.2
Image Core ...................................................................................................................... 2
1.2.3
Display/Camera/Audio ..................................................................................................... 2
1.2.4
Memory Interface ............................................................................................................ 4
1.2.5
System Functions ............................................................................................................ 5
1.2.6
Peripherals ...................................................................................................................... 6
1.2.7
Bootrom ........................................................................................................................... 8
2 Pinout Information ............................................................................ 9
2.1
Pin Map ................................................................................................................................... 9
2.2
Pin Descriptions ..................................................................................................................... 11
2.2.1
GPIO Group A ................................................................................................................ 11
2.2.2
GPIO Group B ............................................................................................................... 12
2.2.3
GPIO Group C ............................................................................................................... 14
2.2.4
GPIO Group D ............................................................................................................... 15
2.3
X1000/E FUNCTION PIN DESCRIPTION ............................................................................ 16
2.4
X1000/E FUNCTION DESCRIPTION ................................................................................... 20
3 Electrical Specifications .................................................................. 26
3.1
Absolute Maximum Ratings .................................................................................................. 26
3.2
Recommended operating conditions .................................................................................... 27
3.3
DC Specifications .................................................................................................................. 28
3.4
Audio codec .......................................................................................................................... 30
3.5
Power On, Reset and BOOT ................................................................................................ 31
3.5.1
Power-On Timing........................................................................................................... 31
3.5.2
Reset procedure ............................................................................................................ 33
3.5.3
BOOT ............................................................................................................................ 34
4 Packaging Information .................................................................... 36
4.1
Overview ............................................................................................................................... 36
4.2
X1000/E Device Dimensions ................................................................................................ 36
4.3
Solder Ball Materials ............................................................................................................. 37
4.4
Moisture Sensitivity Level ..................................................................................................... 37
5 PCB Mounting Guidelines............................................................... 38
5.1
RoHS compliance ................................................................................................................. 38
5.2
Reflow profile ........................................................................................................................ 38
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X1000 IoT Application Processor Data Sheet
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TABLES
TABLES
Table 2-1
GPIO Group A Pinmux(32) ................................................................................................. 11
Table 2-2
GPIO Group B Pinmux(32) ...............................................................................................12
Table 2-3
GPIO Group C Pinmux(26) .................................................................................................14
Table 2-4
GPIO Group D Pinmux(6) ...................................................................................................15
Table 2-5
X1000/E function pin description ........................................................................................16
Table 2-6
X1000/E Function Description ............................................................................................20
Table 3-1
Absolute Maximum Ratings ................................................................................................26
Table 3-2
Recommended operating conditions for power supplies....................................................27
Table 3-3
Recommended operating conditions for VDDMEM supplied pins .....................................27
Table 3-4
Recommended operating conditions for VDDIO/VDDIO_5T/VDDIO_Codec/VDDRTC
supplied pins .........................................................................................................................................27
Table 3-5
Recommended operating conditions for others ..................................................................28
Table 3-6
DC characteristics for VREFMEM ..........................................................................................28
Table 3-7
DC characteristics for VDDmem supplied pins in LPDDR application .............................28
Table 3-8
DC characteristics for VDDIO/VDDIO_5T/VDDIO_Codec/VDDRTC supplied pins for 1.8V
application .............................................................................................................................................28
Table 3-9
DC characteristics for VDDIO/VDDIO_5T/VDDIO_Codec/VDDRTC supplied pins for 2.5V
application .............................................................................................................................................29
Table 3-10
DC characteristics for VDDIO/VDDIO_5T/VDDIO_Codec/VDDRTC supplied pins for 3.3V
application .............................................................................................................................................30
Table 3-11
Power-On Timing Parameters ..........................................................................................32
Table 3-12
Boot Configuration of X1000/E .......................................................................................34
i
X1000 IoT Application Processor Data Sheet
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FIGURES
FIGURES
Figure 1-1 X1000/E Diagram ................................................................................................................. 1
Figure 2-1 X1000/E pin to ball assignment .......................................................................................... 10
Figure 3-1 Power-On Timing Diagram ................................................................................................. 33
Figure 3-2 Boot flow diagram of X1000/E ............................................................................................ 35
Figure 4-1 X1000/E package outline drawing ...................................................................................... 37
i
X1000 IoT Application Processor Data Sheet
Copyright © 2005-2017 Ingenic Semiconductor Co., Ltd. All rights reserved.
Overview
1 Overview
X1000/E is a low power consumption, high performance and high integrated application processor, the
application is focus on IoT devices. And it can match the requirements of many other embedded
products.
NAME
SIP LPDDR
X1000
32MB
X1000E
64MB
1.1 Block Diagram
Figure 1-1 X1000/E Diagram
1.2 Features
1.2.1
CPU Core
®
MIPS-Based XBurst cores (up to 1.0GHz)
MIPS-Based
®
XBurst CPU
– XBurst
®
RISC instruction set
– XBurst
®
SIMD instruction set
– XBurst
®
FPU instruction set supporting both single and double floating point format
1
X1000 IoT Application Processor Data Sheet
Copyright © 2005-2017 Ingenic Semiconductor Co., Ltd. All rights reserved.
Overview
which are IEEE754 compatible
– XBurst
®
9-stage pipeline micro-architecture
MMU
– 32-entry joint-TLB
– 4 entry Instruction TLB
– 4 entry data TLB
L1 Cache
– 16KB instruction cache
– 16KB data cache
Hardware debug support
16KB tight coupled memory
L2 Cache
– 128KB unify cache
1.2.2
The XBurst® processor system supports little endian only
Image Core
Hardware JPEG encoder
– Baseline ISO/IEC 10918-1 JPEG compliant
– 8-bit pixel depth support
– Support for YUY2 ([Y0,U0,Y1,V0]) color
– Up to four programmable Quantization tables
– Fully programmable Huffman tables
– Image size up to 2M pixels
1.2.3
Display/Camera/Audio
LCD controller
– Basic Features
Display size up to 640x480@60Hz,24BPP
– Colors Supports
Support up to 16,777,216 (16M) colors
– Panel Supports
16bit 8080 once parallel interface
9 bits twice 8080 parallel interface
8 bits twice/third times 8080 parallel
Supports different size of display panel
Supports internal DMA operation and register operation
Camera interface module
– Input image size up to 2M pixels
– Integrated DMA
– Supported data format: YCbCr 4:2:2
– Supports ITU656 (YCbCr 4:2:2) input
2
X1000 IoT Application Processor Data Sheet
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Overview
– Configurable VSYNC and HSYNC signals: active high/low
– Configurable PCLK: active edge rising/falling
– PCLK max. 80MHz
– Configurable output order
AIC controller
– I2S features
8, 16, 18, 20 and 24 bit audio sample data sizes supported, 16 bits packed sample
data is supported
Up to 8 channels sample data supported
DMA transfer mode supported
Stop serial clock supported
Programmable Interrupt function supported
Support share clock mode and split clock mode.
Support mono PCM data to stereo PCM data expansion on audio play back
Support endian switch on 16-bits normal audio samples play back
Internal programmable or external serial clock and optional system clock supported
for I2S or MSB-Justified format
Internal I2S CODEC supported
Two FIFOs for transmit and receive respectively
PCM interface
– Support master mode and slave mode
– Data starts with the frame PCMSYN or one PCMCLK later
– Support three modes of operation for PCM
Short frame sync mode
Long frame sync mode
Multi-slot mode
– Data is transferred and received with the MSB first
– The PCM serial output data, PCMDOUT, is clocked out using the rising edge of the
PCMSCLK
– The PCM serial input data, PCMDIN, is clocked in on the falling edge of the PCMSCLK
– 8/16 bit sample data sizes supported
– DMA transfer mode supported
– Two FIFOs for transmit and receive respectively with 16 samples capacity in every
direction
Internal CODEC
– 24 bits ADC and DAC(digital output)
– PWM line out and can load down to 16 Ohm
– Sample rate supported: 8k, 11.025k, 12k, 16k, 22.05k, 24k, 32k, 44.1k, 48k, 88.2k, 96k,
176.4k, and 192k
– Mono line input
– DAC(digital output and converter to analog by external circuit): SNR: 95dB A-Weighted,
THD: -80dB @FS-1dB
– Line input to ADC path: SNR: 90dB A-Weighted, THD: -80dB @FS-1dB
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X1000 IoT Application Processor Data Sheet
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Overview
– Separate power-down modes for ADC and DAC path with several shutdown modes
– Reduction of audible glitches systems: Soft Mute mode
– Embedded low noise Linear Regulator
– 1 MIC in path or 1 line in path Maximum (Total 1 analog input)
Low power DMIC Controller
– 16 bits data interface and 20bit precision internal controller.
– SNR: 90dB, THD: -90dB @ FS -20dB
– Linear high pass filter include. Attenuation: -2.9dB@100Hz, -22dB@27Hz. -36dB@10Hz
– Low power voice trigger when waiting to start talking.
– 1 to 4 channel MIC support.
– Support voice data pre-fetch when trigger enable and the data interface disable, but do
not increase the power dissipation.
– Sample rate supported: 8k, 16k.
– Support low power mode
1.2.4
Memory Interface
DDR Controller
– Support LPDDR, DDR2, DDR3
– 16 bit data width
– Support size up to 1GB (1 chip select, 3-bit Bank,15-bit Row, 11-bit Column,)
– Asynchornize to system bus and each port.
– Support clock-stop mode
– Support auto self-refresh mode
– Support power-down mode and deep-power-down mode
– Programmable DDR timing parameters
– Programmable DDR row and column address width and order
X1000:
32MB SIP LPDDR
X1000E: 64MB SIP LPDDR
Serial nand/nor flash interface(SFC)
– SPI protocol support: Standard, Dual, Quad SPI
– Standard I/O data transfer up to 80Mbits/s
– Dual I/O data transfer up to 160Mbits/s
– Quad I/O data transfer up to 240Mbits/s
– transmit-only or receive-only operation
– MSB always be first in intra transfer of one byte. Least Significant Byte first for inter
transfer of data bytes, and Most Significant Byte first for inter transfer of command or
address bytes.
– one device select
– Configurable sampling point for reception
– Configurable timing parameters: tSLCH, tCHSH and tSHSL
– Configurable flash address wide are supported
4
X1000 IoT Application Processor Data Sheet
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Overview
– 7 transfer formats: Standard SPI, Dual-Output/Dual-Input SPI, Quad-Output/Quad-Input
SPI, Dual-I/O SPI, Quad-I/O SPI, Full Dual-I/O SPI, Full Quad-I/O SPI
– two data transfer mode: slave mode and DMA mode
– Configurable 6 phases for software flow
1.2.5
System Functions
Clock generation and power management
– On-chip oscillator circuit (support 24MHz, 26MHz)
– Two phase-locked loops (PLL) with programmable multiplier
– CCLK, HHCLK, H2CLK, PCLK, H0CLK, DDR_CLK frequency can be changed
separately for software by setting registers
– Functional-unit clock gating
– Supply block power shut down
Timer and counter unit with PWM output and/or input edge counter
– Provide 5 channels, all can generate PWM, two of them have input signal transition edge
counter
– 16-bit A counter and 16-bit B counter with auto-reload function every channel
– Support interrupt generation when the A counter underflows
– Three clock sources: RTCLK (real time clock), EXCLK (external clock input), PCLK (APB
Bus clock) selected with 1, 4, 16, 64, 256 and 1024 clock dividing selected
OS timer
– One channel
– 32-bit counter and 32-bit compare register
– Support interrupt generation when the counter matches the compare register
– Three clock sources: RTCLK (real time clock), EXCLK (external clock input), PCLK (APB
Bus clock) selected with 1, 4, 16, 64, 256 and 1024 clock dividing selected
Interrupt controller
– Total 64 interrupt sources
– Each interrupt source can be independently enabled
– Priority mechanism to indicate highest priority interrupt
– All the registers are accessed by CPU and PDMA
– Unmasked interrupts can wake up the chip in sleep mode
– Another set of source, mask and pending registers to serve for PDMA
Watchdog timer
– Generates WDT reset
– A 16-bit Data register and a 16-bit counter
– Counter clock uses the input clock selected by software
PCLK, EXTAL and RTCCLK can be used as the clock for counter
5
X1000 IoT Application Processor Data Sheet
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Overview
The division ratio of the clock can be set to 1, 4, 16, 64, 256 and 1024 by software
PDMA Controller
– Support up to 8 independent DMA channels
– Descriptor or No-Descriptor Transfer mode
®
– A simple Xburst -1 CPU supports smart transfer mode controlled by programmable
firmware
– Transfer data units: 1-byte, 2-byte, 4-byte, 16-byte, 32-byte, 64-byte, 128-byte
– Transfer number of data unit: 1 ~ 2
24
-1
– Independent source and destination port width: 8-bit, 16-bit, 32-bit
– Fixed three priorities of channel groups: 0~3, highest; 4~11: mid; 12~31: lowest
– An extra INTC IRQ can be bound to one programmable DMA channel
RTC (Real Time Clock)
– Need external 32768Hz oscillator for 32KHz clock generation.
– RTCLK selectable from the oscillator or from the divided clock of EXCLK, so that 32k
crystal can be absent if the hibernating mode is not needed
– 32-bits second counter
– Programmable and adjustable counter to generate accurate 1 Hz clock
– Alarm interrupt, 1Hz interrupt
– Stand alone power supply, work in hibernating mode
– Power down controller
– Alarm wakeup
– External pin wakeup with up to 2s glitch filter
1.2.6
Peripherals
General-Purpose I/O ports
– Each port can be configured as an input, an output or an alternate function port
– Each port can be configured as an interrupt source of low/high level or rising/falling edge
triggering. Every interrupt source can be masked independently
– Each port has an internal pull-up or pull-down resistor connected. The pull-up/down
resistor can be disabled
– GPIO output 4 interrupts, 1 for every group, to INTC
Three I2C Controller (I2C0, I2C1, I2C2)
– Two-wire I2C serial interface – consists of a serial data line (SDA) and a serial clock
(SCL)
– Two speeds
Standard mode (100 Kb/s)
Fast mode (400 Kb/s)
– Device clock is identical with pclk
– Programmable SCL generator
6
X1000 IoT Application Processor Data Sheet
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Overview
– Master or slave I2C operation
– 7-bit addressing/10-bit addressing
– -level transmit and receive FIFOs
– Interrupt operation
– The number of devices that you can connect to the same I2C-bus is limited only by the
maximum bus capacitance of 400pF
One Smart Card Controller (SCC)
– Supports normal card and UIM card.
– Supports asynchronous character (T=0) communication modes.
– Supports asynchronous block (T=1) communication modes.
– Supports setting of clock-rate conversion factor F (372, 512, 558, etc.), and bit-rate
adjustment factor D (1, 2, 4, 8, 16, 32, 12, 20, etc.).
– Supports extra guard time waiting.
– Auto-error detection in T=0 receive mode.
– Auto-character repeat in T=0 transmit mode.
– Transforms inverted format to regular format and vice versa.
– Support stop clock function in some power consuming sensitive applications.
One Synchronous serial interfaces (SSI0)
– 3 protocols support: National’s Microwire, TI’s SSP, and Motorola’s SPI
– Full-duplex or transmit-only or receive-only operation
– Programmable transfer order: MSB first or LSB first
– Configurable normal transfer mode or Interval transfer mode
– Programmable clock phase and polarity for Motorola’s SSI format
– Two slave select signal (SSI0_CE0_ / SSI0_CE1_) supporting up to 2 slave devices
– Back-to-back character transmission/reception mode
– Loop back mode for testing
– Data transfer up to 30Mbits/s
Three UARTs (UART0, UART1, UART2)
– Full-duplex operation
– 5-, 6-, 7- or 8-bit characters with optional no parity or even or odd parity and with 1, 1½,
or 2 stop bits
– Independently controlled transmit, receive (data ready or timeout), line status interrupts
– Internal diagnostic capability Loopback control and break, parity, overrun and
framing-error is provided
– Separate DMA requests for transmit and receive data services in FIFO mode
– Supports modem flow control by software or hardware
– Slow infrared asynchronous interface that conforms to IrDA specification
Two MMC/SD/SDIO controllers (MSC0, MSC1)
– Fully compatible with the MMC System Specification version 4.5
7
X1000 IoT Application Processor Data Sheet
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Overview
– Support SD Specification 3.0
– Support SD I/O Specification 1.0 with 1 command channel and 4 data channels
– Consumer Electronics Advanced Transport Architecture (CE-ATA – version 1.1)
– Maximum data rate is 50MBps
– Both support MMC data width 1bit ,4bit, only MSC0 support 8bit
– Built-in programmable frequency divider for MMC/SD bus
– Built-in Special Descriptor DMA
– Mask-able hardware interrupt for SDIO interrupt, internal status and FIFO status
– Multi-SD function support including multiple I/O and combined I/O and memory
– IRQ supported enable card to interrupt MMC/SD controller
– Single or multi block access to the card including erase operation
– Stream access to the MMC card
– Supports SDIO read wait, interrupt detection during 1-bit or 4-bit access
– Supports CE-ATA digital protocol commands
– Support Command Completion Signal and interrupt to CPU
– Command Completion Signal disable feature
– The maximum block length is 4096bytes
USB 2.0 OTG interface
– Complies with the USB 2.0 standard for high-speed (480 Mbps) functions and with the
On-The-Go supplement to the USB 2.0 specification
– Operates either as the function controller of a high- /full-speed USB peripheral or as the
host/peripheral in point-to-point or multi-point communications with other USB functions
– Supports Session Request Protocol (SRP) and Host Negotiation Protocol (HNP)
– UTMI+ Level 3 Transceiver Interface
– Soft connect/disconnect
– 8 endpoints in device mode, 16 channels for host mode.
– Dedicate FIFO
– Supports control, interrupt, ISO and bulk transfer
MAC controller
– 10/100 Mbps operation
– Supports RMII PHY interfaces
– Supports VLAN and CRC
– Station Management Agent (SMA)
– remote wake-up frame and magic packet frame processing
OTP Slave Interface
– Total 1Kb.
1.2.7
Bootrom
16KB Boot ROM memory
8
X1000 IoT Application Processor Data Sheet
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Pinout Information
2 Pinout Information
2.1 Pin Map
The X1000/E pin to ball assignment is shown in Figure 2-1.
9
X1000 IoT Application Processor Data Sheet
Copyright © 2005-2017 Ingenic Semiconductor Co., Ltd. All rights reserved.
Pinout Information
Figure 2-1 X1000/E pin to ball assignment
10
X1000 IoT Application Processor Data Sheet
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Pinout Information
2.2 Pin Descriptions
2.2.1
GPIO Group A
Table 2-1 GPIO Group A Pinmux(32)
Ball
No.
Ball Name
In/Out
Pull
Pull
Driven
Default
Strength
Schmitt
Slewrate
limitate
GPIO
Func0
Func1
Func2
Extra
Func
Power
F16
SD0_SLCD_D0_I2C1_SCK_PA00
IO
PU
Enable
8mA
No
GPA[0]
SD0
SLCD_D0
I2C1_SCK
WKUP
VDDIO
G15
SD1_SLCD_D1_I2C1_SDA_PA01
IO
PU
Enable
8mA
No
GPA[1]
SD1
SLCD_D1
I2C1_SDA
WKUP
VDDIO
E16
SD2_SLCD_D2_UART2_RXD_PA02
IO
PU
Enable
8mA
No
GPA[2]
SD2
SLCD_D2
UART2_RXD
WKUP
VDDIO
F15
SD3_SLCD_D3_UART2_TXD_PA03
IO
PU
Enable
8mA
No
GPA[3]
SD3
SLCD_D3
UART2_TXD
WKUP
VDDIO
D16
SD4_SLCD_D4_UART1_RXD_PA04
IO
PU
Enable
8mA
No
GPA[4]
SD4
SLCD_D4
UART1_RXD
WKUP
VDDIO
C16
SD5_SLCD_D5_UART1_TXD_PA05
IO
PU
Enable
8mA
No
GPA[5]
SD5
SLCD_D5
UART_TXD
WKUP
VDDIO
E15
SD6_SLCD_D6_PA06
IO
PU
Enable
8mA
No
GPA[6]
SD6
SLCD_D6
WKUP
VDDIO
B16
SD7_SLCD_D7_PA07
IO
PU
Enable
8mA
No
GPA[7]
SD7
SLCD_D7
WKUP
VDDIO
C15
SD8_SLCD_D8_CIM_PCLK_PA08
IO
PU
Enable
8mA
No
GPA[8]
SD8
SLCD_D8
CIM_PCLK
WKUP
VDDIO
B15
SD9_SLCD_D9_CIM_HSYN_PA09
IO
PU
Enable
8mA
No
GPA[9]
SD9
SLCD_D9
CIM_HSYN
WKUP
VDDIO
A15
SD10_SLCD_D10_CIM_VSYN_PA10
IO
PU
Enable
8mA
No
GPA[10]
SD10
SLCD_D10
CIM_VSYN
WKUP
VDDIO
C14
SD11_SLCD_D11_CIM_MCLK_PA11
IO
PU
Enable
8mA
No
GPA[11]
SD11
SLCD_D11
CIM_MCLK
WKUP
VDDIO
D11
SD12_SLCD_D12_CIM_D7_PA12
IO
PU
Enable
8mA
No
GPA[12]
SD12
SLCD_D12
CIM_D7
WKUP
VDDIO
C11
SD13_SLCD_D13_CIM_D6_PA13
IO
PU
Enable
8mA
No
GPA[13]
SD13
SLCD_D13
CIM_D6
WKUP
VDDIO
A11
SD14_SLCD_D14_CIM_D5_PA14
IO
PU
Enable
8mA
No
GPA[14]
SD14
SLCD_D14
CIM_D5
WKUP
VDDIO
B11
SD15_SLCD_D15_CIM_D4_PA15
IO
PU
Enable
8mA
No
GPA[15]
SD15
SLCD_D15
CIM_D4
WKUP
VDDIO
C10
MSC0_D7_CIM_D3_PA16
IO
PU
Enable
8mA
No
GPA[16]
MSC0_D7
CIM_D3
WKUP
VDDIO
A9
MSC0_D6_CIM_D2_PA17
IO
PU
Enable
8mA
No
GPA[17]
MSC0_D6
CIM_D2
WKUP
VDDIO
B10
MSC0_D5_CIM_D1_PA18
IO
PU
Enable
8mA
No
GPA[18]
MSC0_D5
CIM_D1
WKUP
VDDIO
11
X1000 IoT Application Processor Data Sheet
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Pinout Information
A10
MSC0_D4_CIM_D0_PA19
IO
PU
Enable
8mA
No
GPA[19]
MSC0_D4
CIM_D0
WKUP
VDDIO
B14
MSC0_D3_SSI0_GPC_PA20
IO
PU
Enable
8mA
No
GPA[20]
MSC0_D3
SSI0_GPC
WKUP
VDDIO
A14
MSC0_D2_SSI0_CE1_PA21
IO
PU
Enable
8mA
No
GPA[21]
MSC0_D2
SSI0_CE1
WKUP
VDDIO
B13
MSC0_D1_SSI0_DT_PA22
IO
PU
Enable
8mA
No
GPA[22]
MSC0_D1
SSI0_DT
WKUP
VDDIO
A13
MSC0_D0_SSI0_DR_PA23
IO
PU
Enable
8mA
No
GPA[23]
MSC0_D0
SSI0_DR
WKUP
VDDIO
B12
MSC0_CLK_SSI0_CLK_PA24
IO
PU
Enable
8mA
No
GPA[24]
MSC0_CLK
SSI0_CLK
WKUP
VDDIO
A12
MSC0_CMD_SSI0_CE0_PA25
IO
PU
Enable
8mA
No
GPA[25]
MSC0_CMD
SSI0_CE0
WKUP
VDDIO
A7
SFC_CLK_SSI0_CLK_PA26
IO
PU
Enable
8mA
No
GPA[26]
SFC_CLK
SSI0_CLK
WKUP
VDDIO
C7
SFC_CE_SSI0_CE0_PA27
IO
PU
Enable
8mA
No
GPA[27]
SFC_CE
SSI0_CE0
WKUP
VDDIO
B8
SFC_DR_SSI0_DR_PA28
IO
PU
Enable
8mA
No
GPA[28]
SFC_DR
SSI0_DR
WKUP
VDDIO
B7
SFC_DT_SSI0_DT_PA29
IO
PU
Enable
8mA
No
GPA[29]
SFC_DT
SSI0_DT
WKUP
VDDIO
D6
SFC_WP_SSI0_CE1_PA30
IO
PU
Enable
8mA
No
GPA[30]
SFC_WP
SSI0_CE1
WKUP
VDDIO
C6
SFC_HOLD_SSI0_GPC_PA31
IO
PU
Enable
8mA
No
GPA[31]
SFC_HOLD
SSI0_GPC
WKUP
VDDIO
2.2.2
GPIO Group B
Table 2-2 GPIO Group B Pinmux(32)
Ball
Ball Name
No.
In/Out
Pull
Pull
Driven
Default
Strength
Schmitt
Slewrate
limitate
GPIO
Func0
Func1
Func2
Extra
Func
Power
R2
SA0_I2S_MCLK_PB00
IO
PU
Enable
8mA
No
GPB[0]
SA0
I2S_MCLK
WKUP
VDDIO
T2
SA1_I2S_BCLK_PB01
IO
PU
Enable
8mA
No
GPB[1]
SA1
I2S_BCLK
WKUP
VDDIO
T3
SA2_I2S_LRCLK_PB02
IO
PU
Enable
8mA
No
GPB[2]
SA2
I2S_LRCLK
WKUP
VDDIO
R3
SA3_I2S_DI_PB03
IO
PU
Enable
8mA
No
GPB[3]
SA3
I2S_DI
WKUP
VDDIO
R4
SA4_I2S_DO_PB04
IO
PU
Enable
8mA
No
GPB[4]
SA4
I2S_DO
WKUP
VDDIO
12
X1000 IoT Application Processor Data Sheet
Copyright © 2005-2017 Ingenic Semiconductor Co., Ltd. All rights reserved.
Pinout Information
T4
SA5_DMIC1_IN_PB05
IO
PU
Enable
8mA
No
GPB[5]
SA5
DMIC1_IN
WKUP
VDDIO
L15
SA6_MAC_PHY_CLK_PWM3_PB06
IO
PU
Enable
8mA
No
GPB[6]
SA6
MAC_PHY_CLK
WKUP
VDDIO
L14
SA7_MAC_CRS_DV_PB07
IO
PU
Enable
8mA
No
GPB[7]
SA7
MAC_CRS_DV
WKUP
VDDIO
K16
SA8_MAC_RXD1_PB08
IO
PU
Enable
8mA
No
GPB[8]
SA8
MAC_RXD1
WKUP
VDDIO
K15
SA9_MAC_RXD0_PB09
IO
PU
Enable
8mA
No
GPB[9]
SA9
MAC_RXD0
WKUP
VDDIO
K14
SA10_MAC_TXEN_PB10
IO
PU
Enable
8mA
No
GPB[10]
SA10
MAC_TXEN
WKUP
VDDIO
J16
SA11_MAC_TXD1_PB11
IO
PU
Enable
8mA
No
GPB[11]
SA11
MAC_TXD1
WKUP
VDDIO
H16
SA12_MAC_TXD0_PB12
IO
PU
Enable
8mA
No
GPB[12]
SA12
MAC_TXD0
WKUP
VDDIO
J15
SA13_MAC_MDC_PB13
IO
PU
Enable
8mA
No
GPB[13]
SA13
MAC_MDC
WKUP
VDDIO
G16
SA14_MAC_MDIO_PB14
IO
PU
Enable
8mA
No
GPB[14]
SA14
MAC_MDIO
WKUP
VDDIO
H15
SA15_MAC_REF_CLK_PB15
IO
PU
Enable
8mA
No
GPB[15]
SA15
MAC_REF_CLK
WKUP
VDDIO
G14
RD_SLCD_RD_PB16
IO
PU
Enable
8mA
No
GPB[16]
RD
SLCD_RD
WKUP
VDDIO
D15
WE_SLCD_WR_PB17
IO
PU
Enable
8mA
No
GPB[17]
WE
SLCD_WR
WKUP
VDDIO
F14
CS1_SLCD_CE_PB18
IO
PU
Enable
8mA
No
GPB[18]
CS1
SLCD_CE
WKUP
VDDIO
E13
CS2_SLCD_TE_PB19
IO
PU
Enable
8mA
No
GPB[19]
CS2
SLCD_TE
WKUP
VDDIO
E14
WAIT_SLCD_DC_PB20
IO
PU
Enable
8mA
No
GPB[20]
WAIT
SLCD_DC
WKUP
VDDIO
R5
DMIC_CLK_PB21
IO
PU
Enable
8mA
No
GPB[21]
DMIC_CLK
WKUP
VDDIO
G3
DMIC0_IN_PB22
IO
PU
Enable
8mA
No
GPB[22]
DMIC0_IN
WKUP
VDDIO
J2
I2C0_SCK_SCC_CLK_PB23
IO
PU
Enable
8mA
No
GPB[23]
I2C0_SC
SCC_CLK
WKUP
VDDIO
H1
I2C0_SDA_SCC_DATA_PB24
IO
PU
Enable
8mA
No
GPB[24]
I2C0_SDA
SCC_DATA
WKUP
VDDIO
T11
DRV_VBUS_PB25
IO
PD
Enable
8mA
No
GPB[25]
DRV_VBUS
WKUP
VDDIO
T5
RTC32K_PB26
IO
PU
Enable
8mA
No
GPB[26]
RTC32K
WKUP
VDDIO
F1
EXCLK_PB27
IO
PU
Enable
8mA
No
GPB[27]
EXCLK
WKUP
VDDIO
M2
BOOT_SEL0_PB28
IO
PU
Disable
8mA
No
GPB[28]
BOOT_SEL0
WKUP
VDDIO
L2
BOOT_SEL1_PB29
IO
PU
Disable
8mA
No
GPB[29]
BOOT_SEL1
WKUP
VDDIO
PWM3
13
X1000 IoT Application Processor Data Sheet
Copyright © 2005-2017 Ingenic Semiconductor Co., Ltd. All rights reserved.
Pinout Information
M1
BOOT_SEL2_PB30
IO
PU
Disable
8mA
No
GPB[30]
BOOT_SEL2
WKUP
VDDIO
R6
WKUP_PB31
IO
PU
Enable
8mA
Yes
GPB[31]
WKUP
WKUP
VDDRTC
2.2.3
GPIO Group C
Table 2-3 GPIO Group C Pinmux(26)
Ball
Ball Name
No.
In/Out
Pull
Pull
Driven
Default
Strength
Schmitt
Slewrate
limitate
GPIO
Func0
Func1
Func2
Extra
Func
Power
E1
MSC1_CLK_PC00
IO
PU
Enable
8mA
No
GPC[0]
MSC1_CLK
WKUP
VDDIO
F2
MSC1_CMD_PC01
IO
PU
Enable
8mA
No
GPC[1]
MSC1_CMD
WKUP
VDDIO
D1
MSC1_D0_PC02
IO
PU
Enable
8mA
No
GPC[2]
MSC1_D0
WKUP
VDDIO
E2
MSC1_D1_PC03
IO
PU
Enable
8mA
No
GPC[3]
MSC1_D1
WKUP
VDDIO
F3
MSC1_D2_PC04
IO
PU
Enable
8mA
No
GPC[4]
MSC1_D2
WKUP
VDDIO
E3
MSC1_D3_PC05
IO
PU
Enable
8mA
No
GPC[5]
MSC1_D3
WKUP
VDDIO
C1
PCM_CLK_PC06
IO
PU
Enable
8mA
No
GPC[6]
PCM_CLK
WKUP
VDDIO
B1
PCM_DO_PC07
IO
PU
Enable
8mA
No
GPC[7]
PCM_DO
WKUP
VDDIO
D2
PCM_DI_PC08
IO
PU
Enable
8mA
No
GPC[8]
PCM_DI
WKUP
VDDIO
C2
PCM_SYN_PC09
IO
PU
Enable
8mA
No
GPC[9]
PCM_SYN
WKUP
VDDIO
B6
UART0_RXD_PC10
IO
PU
Enable
8mA
No
GPC[10]
UART0_RXD
WKUP
VDDIO
A6
UART0_TXD_PC11
IO
PU
Enable
8mA
No
GPC[11]
UART0_TXD
WKUP
VDDIO
B5
UART0_CTS_PC12
IO
PU
Enable
8mA
No
GPC[12]
UART0_CTS
WKUP
VDDIO
A5
UART0_RTS_PC13
IO
PU
Enable
8mA
No
GPC[13]
UART0_RTS
WKUP
VDDIO
B2
PC16
IO
PU
Enable
8mA
Yes
GPC[16]
WKUP
VDDIO
A2
PC17
IO
PU
Enable
8mA
Yes
GPC[17]
WKUP
VDDIO
C3
PC18
IO
PU
Enable
8mA
Yes
GPC[18]
WKUP
VDDIO
14
X1000 IoT Application Processor Data Sheet
Copyright © 2005-2017 Ingenic Semiconductor Co., Ltd. All rights reserved.
Pinout Information
B3
PC19
IO
PU
Enable
8mA
Yes
GPC[19]
WKUP
VDDIO
A3
PC20
IO
PU
Enable
8mA
Yes
GPC[20]
WKUP
VDDIO
E4
PC21
IO
PU
Enable
8mA
Yes
GPC[21]
WKUP
VDDIO
B4
PC22
IO
PU
Disable
8mA
Yes
GPC[22]
WKUP
VDDIO
A4
PC23
IO
PU
Disable
8mA
Yes
GPC[23]
WKUP
VDDIO
L1
PWM4_PC24
IO
PU
Enable
8mA
No
GPC[24]
PWM4
WKUP
VDDIO
K1
PWM0_PC25
IO
PD
Enable
8mA
No
GPC[25]
PWM0
WKUP
VDDIO
K2
I2C1_SCK_PWM1_PC26
IO
PU
Enable
8mA
No
GPC[26]
I2C1_SCK
PWM1
WKUP
VDDIO
J1
I2C1_SDA_PWM2_PC27
IO
PU
Enable
8mA
No
GPC[27]
I2C1_SDA
PWM2
WKUP
VDDIO
2.2.4
GPIO Group D
Table 2-4 GPIO Group D Pinmux(6)
Ball
No.
Ball Name
In/
Out
Pull
Pull
Driven
Default
Strength
Schmitt
Slewrate
limitate
GPIO
Func0
Func1
Func2
Extra
Func
Power
P3
SSI0_CLK_I2C2_SCK_PD00
IO
PU
Enable
8mA
No
5V
GPD[0]
SSI0_CLK
I2C2_SCK
WKUP
VDDIO_5T
R1
SSI0_CE0_I2C2_SDA_PD01
IO
PU
Enable
8mA
No
5V
GPD[1]
SSI0_CE0
I2C2_SDA
WKUP
VDDIO_5T
P2
SSI0_DT_UART1_RXD_PD02
IO
PU
Enable
8mA
No
5V
GPD[2]
SSI0_DT
UART1_RXD
WKUP
VDDIO_5T
P1
SSI0_DR_UART1_TXD_PD03
IO
PU
Enable
8mA
No
5V
GPD[3]
SSI0_DR
UART1_TXD
WKUP
VDDIO_5T
N2
UART2_TXD_UART1_CTS_PD04
IO
PU
Enable
8mA
No
5V
GPD[4]
UART2_TXD
UART1_CTS
WKUP
VDDIO_5T
N1
UART2_RXD_UART1_RTS_PD05
IO
PU
Enable
8mA
No
5V
GPD[5]
UART2_RXD
UART1_RTS
WKUP
VDDIO_5T
15
X1000 IoT Application Processor Data Sheet
Copyright © 2005-2017 Ingenic Semiconductor Co., Ltd. All rights reserved.
Pinout Information
2.3 X1000/E FUNCTION PIN DESCRIPTION
Table 2-5 X1000/E function pin description
Ball No.
Pin Names
IO
Power
Pin Description
K3
pad_TRST_
I
VDDIO
JTAG reset
G1
TDO_UART2_TXD
O
VDDIO
JTAG serial data output
G2
TDI_UART2_RXD
I
VDDIO
JTAG serial data input
L3
TCK
I
VDDIO
JTAG clock
M3
TMS
I
VDDIO
JTAG mode select
E6
LPDDR_VDD
P
-
Power for SIP LPDDR 1.8V
F6
LPDDR_VDD
P
-
Power for SIP LPDDR 1.8V
G6
LPDDR_VDD
P
-
Power for SIP LPDDR 1.8V
J7
LPDDR_VSS
P
-
Ground for SIP LPDDR
K7
LPDDR_VSS
P
-
Ground for SIP LPDDR
L7
LPDDR_VSS
P
-
Ground for SIP LPDDR
F5
LPDDR_VDDQ
P
-
Power for SIP LPDDR 1.8V
G5
LPDDR_VDDQ
P
-
Power for SIP LPDDR 1.8V
H5
LPDDR_VDDQ
P
-
Power for SIP LPDDR 1.8V
H6
LPDDR_VDDQ
P
-
Power for SIP LPDDR 1.8V
H7
LPDDR_VDDQ
P
-
Power for SIP LPDDR 1.8V
J5
LPDDR_VSSQ
P
-
Ground for SIP LPDDR
J6
LPDDR_VSSQ
P
-
Ground for SIP LPDDR
K5
LPDDR_VSSQ
P
-
Ground for SIP LPDDR
Debug
Memory
16
X1000 IoT Application Processor Data Sheet
Copyright © 2005-2017 Ingenic Semiconductor Co., Ltd. All rights reserved.
Pinout Information
K6
LPDDR_VSSQ
P
-
Ground for SIP LPDDR
L6
LPDDR_VSSQ
P
-
Ground for SIP LPDDR
B9
ZQ
DDR PHY ZQ calibration resistor
A8
VREF0
DDR PHY VREF
Power and Ground
E7
VDDMEM
P
-
IO digital power for DRAM 1.8V
E8
VDDMEM
P
-
IO digital power for DRAM 1.8V
F7
VDDMEM
P
-
IO digital power for DRAM 1.8V
F8
VDDMEM
P
-
IO digital power for DRAM 1.8V
G7
VDDMEM
P
-
IO digital power for DRAM 1.8V
G8
VDDMEM
P
-
IO digital power for DRAM 1.8V
E9
VSSMEM
P
-
IO digital ground for DRAM, 0V
E10
VSSMEM
P
-
IO digital ground for DRAM, 0V
F9
VSSMEM
P
-
IO digital ground for DRAM, 0V
F10
VSSMEM
P
-
IO digital ground for DRAM, 0V
G9
VSSMEM
P
-
IO digital ground for DRAM, 0V
G10
VSSMEM
P
-
IO digital ground for DRAM, 0V
K11
VDDIO
P
-
IO digital power for none DRAM 1.8~3.3V
K12
VDDIO
P
-
IO digital power for none DRAM 1.8~3.3V
L12
VDDIO
P
-
IO digital power for none DRAM 1.8~3.3V
N6
VDDIO_5T
P
-
IO digital power for none DRAM (5V tolerant)
J10
VSS
P
-
Core digital gound for none DRAM and CORE digital ground, 0V
K8
VSS
P
-
Core digital gound for none DRAM and CORE digital ground, 0V
K9
VSS
P
-
Core digital gound for none DRAM and CORE digital ground, 0V
K10
VSS
P
-
Core digital gound for none DRAM and CORE digital ground, 0V
L8
VSS
P
-
Core digital gound for none DRAM and CORE digital ground, 0V
17
X1000 IoT Application Processor Data Sheet
Copyright © 2005-2017 Ingenic Semiconductor Co., Ltd. All rights reserved.
Pinout Information
L9
VSS
P
-
Core digital gound for none DRAM and CORE digital ground, 0V
L10
VSS
P
-
Core digital gound for none DRAM and CORE digital ground, 0V
L11
VSS
P
-
Core digital gound for none DRAM and CORE digital ground, 0V
M8
VSS
P
-
Core digital gound for none DRAM and CORE digital ground, 0V
M9
VSS
P
-
Core digital gound for none DRAM and CORE digital ground, 0V
M10
VSS
P
-
Core digital gound for none DRAM and CORE digital ground, 0V
F11
VDD
P
-
CORE digital power, 1.2V
G11
VDD
P
-
CORE digital power, 1.2V
G12
VDD
P
-
CORE digital power, 1.2V
H10
VDD
P
-
CORE digital power, 1.2V
H11
VDD
P
-
CORE digital power, 1.2V
H12
VDD
P
-
CORE digital power, 1.2V
J11
VDD
P
-
CORE digital power, 1.2V
J12
VDD
P
-
CORE digital power, 1.2V
Audio Codec
P16
CODEC_AVDD
S
-
Analog positive power supply
P14
CODEC_AVSS
S
-
Analog negative power supply 2 Ohms max
P15
CODEC_VREFP
S
-
Analog negative power supply for ADC part
T15
VCAP
AO
AVD
Decoupling cap for internal biasing voltage for core part
R16
AIP
AI
AVD
Left channel single-ended or positive analog input
R15
AIN
AI
AVD
R14
MICBIAS
AO
AVD
L16
VDDIO_CODEC
S
-
PWM digital line out IO positive power supply
M14
VSSIO_CODEC
S
-
PWM digital line out IO negative power supply
N15
CODEC_PWMLP
DO
VDDIO_CODEC
Left channel negative analog input 1.Must be left floating in single-ended
configuration
Electric microphone biasing voltage
PWM digital line out positive left channel
18
X1000 IoT Application Processor Data Sheet
Copyright © 2005-2017 Ingenic Semiconductor Co., Ltd. All rights reserved.
Pinout Information
N16
CODEC_PWMLN
DO
VDDIO_CODEC
PWM digital line out negative left channel
M15
COEDC_PWMRP
DO
VDDIO_CODEC
PWM digital line out positive right channel
M16
CODEC_PWMRN
DO
VDDIO_CODEC
PWM digital line out negative right channel
R12
USB_DP0(OTG_DP)
AIO
AVDUSB33
USB OTG data plus
T12
USB_DM0(OTG_DM)
AIO
AVDUSB33
USB OTG data minus
P13
USB_VBUS(OTG_VBUS)
AIO
5V
P11
USB_ID(OTG_ID)
AI
AVDUSB25
R13
OTG_TXR_RKL
AIO
AVDUSB25
T14
AVDOTG
P
-
USB analog power.3.3V
R11
AVSOTG
P
-
USB analog ground.
T13
AVDOTG25
P
-
USB OTG analog power, 2.5V
AVDEFUSE
P
AVEFUSE
T10
EXCLK_XI(EXCLK_I)
AI
VDDIO
OSC input.
R10
EXCLK_XO(EXCLK_O)
AO
VDDIO
OSC output.
USB OTG
USB 5-V power supply pin for USB OTG. An external charge pump must provide
power to this pin
USB mini-receptacle identifier. It differentiates a mini-A from a mini-B plug. If this
signal is not used, internal resistance pulls the signal’s voltage level to AVDUSB25.
Transmitter resister tune. It connects to an external resistor of 43.2Ω with 1%
tolerance to analog ground, that adjusts the USB 2.0 high-speed source impedance
EFUSE
H2
EFUSE programming power, 0V/2.5V
CPM
T9
PLL_DVDD
P
-
PLL digital power, 1.2V
P9
PLL_DVSS
P
-
PLL digital ground
R9
PLL_AVDD
P
-
PLL analog power, 1.2V
P10
PLL_AVSS
P
-
PLL analog ground
R8
RTCLK
AI
VDDRTC
T8
XRTCLK
AO
-
RTC
OSC input or 32768Hz clock input
OSC output
19
X1000 IoT Application Processor Data Sheet
Copyright © 2005-2017 Ingenic Semiconductor Co., Ltd. All rights reserved.
Pinout Information
R7
PWRON
O
VDDRTC
Power on/off control of main power
P6
PPRST_
I
VDDRTC
RTC power on reset and RESET-KEY reset input
P7
TEST_TE
I
VDDRTC
Manufacture test enable, program readable
T7
LDOOUT
P
-
capacitor pin for RTC LDO need a 1nF decoupling capacitor to ground
N7
VSSRTC
P
-
RTC ground
T6
VDDRTC
P
-
VDDRTC: 3.3V power for RTC and hibernating mode controlling that never power
down(normally you can use 1.8V instead to reduce power consumption)
2.4 X1000/E FUNCTION DESCRIPTION
Table 2-6 X1000/E Function Description
Signal Name
In/Out
Description
SLCD(Smart LCD)
SLCD_D0
Output
Smart LCD data output bit 0
SLCD_D1
Output
Smart LCD data output bit 1
SLCD_D2
Output
Smart LCD data output bit 2
SLCD_D3
Output
Smart LCD data output bit 3
SLCD_D4
Output
Smart LCD data output bit 4
SLCD_D5
Output
Smart LCD data output bit 5
SLCD_D6
Output
Smart LCD data output bit 6
SLCD_D7
Output
Smart LCD data output bit 7
SLCD_D8
Output
Smart LCD data output bit 8
SLCD_D9
Output
Smart LCD data output bit 9
SLCD_D10
Output
Smart LCD data output bit 10
SLCD_D11
Output
Smart LCD data output bit 11
20
X1000 IoT Application Processor Data Sheet
Copyright © 2005-2017 Ingenic Semiconductor Co., Ltd. All rights reserved.
Pinout Information
SLCD_D12
Output
Smart LCD data output bit 12
SLCD_D13
Output
Smart LCD data output bit 13
SLCD_D14
Output
Smart LCD data output bit 14
SLCD_D15
Output
Smart LCD data output bit 15
SLCD_RD
Output
Smart LCD read signal
SLCD_WR
Output
Smart LCD write signal
SLCD_CE
Output
Smart LCD chip select signal
SLCD_TE
Input
SLCD_DC
Output
Smart LCD tearing effect signal
Smart LCD data/command select signal
CIM(Camera Interface)
CIM_PCLK
Input
CIM pixel clock input
CIM_HSYN
Input
CIM line horizonal sync input
CIM_VSYN
Input
CIM vertical sync input
CIM_MCLK
Output
CIM_D7
Input
CIM data input bit 7
CIM_D6
Input
CIM data input bit 6
CIM_D5
Input
CIM data input bit 5
CIM_D4
Input
CIM data input bit 4
CIM_D3
Input
CIM data input bit 3
CIM_D2
Input
CIM data input bit 2
CIM_D1
Input
CIM data input bit 1
CIM_D0
Input
CIM data input bit 0
I2S_MCLK
Output
I2S master clock out
I2S_BCLK
Bidirection
I2S bit clock
I2S_LRCLK
Bidirection
I2S LR clock
CIM master clock output
I2S
21
X1000 IoT Application Processor Data Sheet
Copyright © 2005-2017 Ingenic Semiconductor Co., Ltd. All rights reserved.
Pinout Information
I2S_DI
Input
I2S_DO
Output
PCM_CLK
Bidirection
PCM_DO
Output
PCM_DI
Input
PCM_SYN
Bidirection
I2S data input
I2S data output
PCM
PCM clock
PCM data out
PCM data in
PCM sync
DMIC
DMIC0_IN
Input
Digital MIC data input(Left/Right Front/Back channel)
DMIC1_IN
Input
Digital MIC data input(channel)
DMIC_CLK
Output
Digital MIC clock output
SFC_CLK
Output
Serial Flash clock output
SFC_CE_
Output
Serial Flash chip enable
SFC_DR
Bidirection
Serial Flash data input
SFC_DT
Bidirection
Serial Flash data output
SFC_WP
Bidirection
Serial Flash write protect signal
SRC_HOLD
Bidirection
Serial Flash hold signal
PWMn
Bidirection
PWM output or pulse input channel n
RTC32K
Output
I2Cn_SCK
Bidirection
I2C n serial clock
I2Cn_SDA
Bidirection
I2C n serial data
SFC
PWM
RTC
32768Hz clock output
I2C
SCC
22
X1000 IoT Application Processor Data Sheet
Copyright © 2005-2017 Ingenic Semiconductor Co., Ltd. All rights reserved.
Pinout Information
SCC_CLK
Bidirection
Smart Card clock
SCC_DATA
Bidirection
Smart Card data
SSIn_CLK
Output
SSI n clock output
SSIn_CE0_
Output
SSI n chip enable 0
SSIn_CE1_
Output
SSI n chip enable 1
SSIn_GPC
Output
SSI n general-purpose control signal
SSIn_DT
Output
SSI n data output
SSIn_DR
Input
SSI n data input
UARTn_RXD
Input
UART n receiving data
UARTn_TXD
Output
UARTn_CTS_
Input
UARTn_RTS_
Output
SSI
UART
UART n transmitting data
UART Clear to send control
UART Request to send control
MSC
MSCn_D7
Bidirection
MSC(MMC/SD) n data bit 7
MSCn_D6
Bidirection
MSC(MMC/SD) n data bit 6
MSCn_D5
Bidirection
MSC(MMC/SD) n data bit 5
MSCn_D4
Bidirection
MSC(MMC/SD) n data bit 4
MSCn_D3
Bidirection
MSC(MMC/SD) n data bit 3
MSCn_D2
Bidirection
MSC(MMC/SD) n data bit 2
MSCn_D1
Bidirection
MSC(MMC/SD) n data bit 1
MSCn_D0
Bidirection
MSC(MMC/SD) n data bit 0
MSCn_CLK
Output
MSCn_CMD
Bidirection
MSC(MMC/SD) n clock output
MSC(MMC/SD) n command
USB 2.0 OTG
23
X1000 IoT Application Processor Data Sheet
Copyright © 2005-2017 Ingenic Semiconductor Co., Ltd. All rights reserved.
Pinout Information
DRV_VBUS
Output
USB OTG VBUS driver control signal
MAC_PHY_CLK
Output
Ethernet PHY clock (50MHz)
MAC_CRS_DV
Input
Ethernet carrier sense
MAC_RXD1
Input
Ethernet receive data bit 1 for RMII
MAC_RXD0
Input
Ethernet receive data bit 0 for RMII
MAC_TXEN
Output
Ethernet transmit enable
MAC_TXD1
Output
Ethernet transmit data bit 1 for RMII
MAC_TXD0
Output
Ethernet transmit data bit 0 for RMII
MAC_MDC
Output
Ethernet management clock
MAC_MDIO
Bidirection
Ethernet management data
MAC_REF_CLK
Input
MAC
Ethernet reference clock (50MHz)
NOTES:
1
The meaning of phases in IO cell characteristics are:
a
Bi-dir, Single-end: bi-direction and single-ended DDR IO are used.
b
Output, Single-end: output and single-ended DDR IO are used.
c
Output, Differential: output and differential signal DDR IO are used.
d
Bi-dir, Differential: bi-direction and differential signal DDR IO are used.
e
4mA, 8mA, 16mA out: The IO cell’s output driving strength is about 4mA,8mA,16mA.
4/8mA means the IO cell's output driving strength is selected and can be set as 4mA or 8mA.
2/4mA means the IO cell's output driving strength is selected and can be set as 2mA or 4mA.
f
Pull-up: The IO cell contains a pull-up resistor.
g
Pull-down: The IO cell contains a pull-down resistor.
h
Pullup-pe: The IO cell contains a pull-up resistor and the pull-up resistor can be enabled or disabled by setting corresponding register.
i
Pulldown-pe: The IO cell contains a pull-down resistor and the pull-down resistor can be enabled or disabled by setting corresponding register.
j
rst-pe: these pins are initialed (during reset and after reset) to IO internal pull (up or down) enabled. Otherwise, the pins are initialed to pull
24
X1000 IoT Application Processor Data Sheet
Copyright © 2005-2017 Ingenic Semiconductor Co., Ltd. All rights reserved.
Pinout Information
disabled
2
k
Schmitt: The IO cell is Schmitt trig input.
l
~SL: The IO cell do not limited slew rate.
All GPIO shared pins are reset to GPIO input
25
X1000 IoT Application Processor Data Sheet
Copyright © 2005-2017 Ingenic Semiconductor Co., Ltd. All rights reserved.
Electrical Specifications
3 Electrical Specifications
3.1 Absolute Maximum Ratings
The absolute maximum ratings for the processors are listed in Table 3-1. Do not exceed these
parameters or the part may be damaged permanently. Operation at absolute maximum ratings is not
guaranteed.
Table 3-1 Absolute Maximum Ratings
Parameter
Min
Max
Unit
Storage Temperature
-65
150
C
Operation Temperature
-40
85
C
VDDMEM power supplies voltage
-0.5
1.98
V
VDDIO power supplies voltage
-0.5
3.6
V
VDDIO_5T
-0.5
3.6
V
-0.5
3.6
V
VDD core power supplies voltage
-0.2
1.32
V
PLLVDD12 power supplies voltage
-0.2
1.32
V
PLLAVDD power supplies voltage
-0.2
1.32
V
AVDEFUSE power supplies voltage
-0.5
2.75
V
VDDRTC power supplies voltage
-0.5
3.63
V
AVDUSB25 power supplies voltage
-0.5
2.75
V
AVDUSB33 power supplies voltage
-0.5
3.63
V
AVDCDC power supplies voltage
-0.5
3.63
V
Input voltage to VDDMEM supplied non-supply pins
-0.3
1.98
V
-0.5
5.5
V
Input voltage to VDDIO supplied non-supply pins without 5V tolerance
-0.5
3.6
V
Input voltage to VDDIO_Codec supplied non-supply pins
-0.5
3.6
V
Input voltage to VDDRTC supplied non-supply pins
-0.5
3.6
V
Input voltage to AVDCDC supplied non-supply pins
-0.5
3.63
V
Input voltage to AVDUSB25 supplied non-supply pins
-0.5
2.75
V
Input voltage to AVDUSB33 supplied non-supply pins
-0.5
3.63
V
Output voltage from VDDMEM supplied non-supply pins
-0.5
1.98
V
Output voltage from VDDIO supplied non-supply pins
-0.5
3.6
V
Output voltage from VDDIO_Codec supplied non-supply pins
-0.5
3.6
V
Output voltage from VDDIO_5T supplied non-supply pins
-0.5
3.6
V
Output voltage from VDDRTC supplied non-supply pins
-0.5
3.6
V
Output voltage from AVDUSB25 supplied non-supply pins
-0.5
2.75
V
Output voltage from AVDUSB33 supplied non-supply pins
-0.5
3.6
V
Output voltage from AVDCDC supplied non-supply pins
-0.5
3.63
V
power supplies voltage
VDDIO_Codec
power supplies voltage
Input voltage to VDDIO_5T supplied non-supply pins with 5V
tolerance
26
X1000 IoT Application Processor Data Sheet
Copyright © 2005-2017 Ingenic Semiconductor Co., Ltd. All rights reserved.
Electrical Specifications
Maximum ESD stress voltage, Human Body Model; Any pin to any
supply pin, either polarity, or Any pin to all non-supply pins together,
2000
V
either polarity. Three stresses maximum.
3.2 Recommended operating conditions
Table 3-2 Recommended operating conditions for power supplies
Symbol
Description
Min
Typical
Max
Unit
VDDMEM voltage for LPDDR
1.65
1.8
1.95
V
VDDMEM voltage for SSTL18 (DDR2)
1.7
1.8
1.9
V
VDDMEM voltage for DDR3
1.425
1.5
1.575
V
VDDMEM voltage for DDR3L
1.28
1.35
1.45
V
VIO(1.8V)
VDDIO voltage, use as 1.8V
1.62
1.8
1.98
V
VIO5(1.8V)
VDDIO_5T voltage, use as 1.8V
1.62
1.8
1.98
V
VIOC(1.8V)
VDDIO_Codec voltage, use as 1.8V
1.62
1.8
1.98
V
VIO(2.5V)
VDDIO voltage, use as 2.5V
2.25
2.5
2.75
V
VIO5(2.5V)
VDDIO_5T voltage, use as 2.5V
2.25
2.5
2.75
V
VIOC(2.5V)
VDDIO_Codec voltage, use as 2.5V
2.25
2.5
2.75
V
VIO(3.3V)
VDDIO voltage, use as 3.3V
2.97
3.3
3.63
V
VIO5(3.3V)
VDDIO_5T voltage, use as 3.3V
2.97
3.3
3.63
V
VIOC(3.3V)
VDDIO_Codec voltage, use as 3.3V
2.97
3.3
3.63
V
VCORE
VDD core voltage
1.08
1.2
1.32
V
VPLL12
PLLVDD, PLLAVDD voltage
1.08
1.2
1.32
V
VEFUSE
AVDEFUSE voltage
2.25
2.5
2.75
V
VRTC33
VDDRTC voltage
1.8
1.8
3.63
V
VUSB25
AVDOTG25 voltage
2.25
2.5
2.75
V
VUSB33
AVDOTG voltage
3.0
3.3
3.6
V
2.97
3.3
3.63
V
VMEM
VCDC
CODEC_AVDD
voltage
Table 3-3 Recommended operating conditions for VDDMEM supplied pins
Symbol
Parameter
Min
Typical
Max
Unit
VI18
Input voltage for LPDDR applications
0
1.8
1.9
V
VO18
Output voltage for LPDDR applications
0
1.8
1.9
V
Table 3-4 Recommended operating conditions for VDDIO/VDDIO_5T/VDDIO_Codec/VDDRTC
supplied pins
Symbol
Parameter
Min
Typical
Max
Unit
VIH18
Input high voltage for 1.8V I/O application
1.17
1.8
3.6
V
VIL18
Input low voltage for 1.8V I/O application
–0.3
0
0.63
V
27
X1000 IoT Application Processor Data Sheet
Copyright © 2005-2017 Ingenic Semiconductor Co., Ltd. All rights reserved.
Electrical Specifications
VIH25
Input high voltage for 2.5V I/O application
1.7
2.5
3.6
V
VIL25
Input low voltage for 2.5V I/O application
–0.3
0
0.7
V
VIH33
Input high voltage for 3.3V I/O application
2
3.3
3.6
V
VIL33
Input low voltage for 3.3V I/O application
–0.3
0
0.8
V
Max
Unit
85
C
Table 3-5 Recommended operating conditions for others
Symbol
Description
TA
Min
Typical
–40
Ambient temperature
3.3 DC Specifications
The DC characteristics for each pin include input-sense levels and output-drive levels and currents.
These parameters can be used to determine maximum DC loading, and also to determine maximum
transition times for a given load. All DC specification values are valid for the entire temperature range
of the device.
Table 3-6 DC characteristics for VREFMEM
Symbol
VREFM
Parameter
Min
Typical
Max
Unit
Reference voltage supply
0.49
0.5
0.51
VMEM
Table 3-7 DC characteristics for VDDmem supplied pins in LPDDR application
Symbol
VIH(DC)
Parameter
Input logic threshold High
VIL(DC)
Min
Typical
Max
Unit
0.7* VMEM
VMEM+0.3
V
Input logic threshold Low
VMEM-0.3
0.3* VMEM
V
VIH(AC)
AC Input logic High
0.8* VMEM
VMEM+0.3
V
VIL(AC)
AC Input logic Low
VMEM-0.3
0.2* VMEM
V
VOH
DC output logic High
0.9*VMEM
V
(IOH=-0.1mA)
VOL
DC output logic Low
0.1 *VMEM
V
(IOL=0.1mA)
ILL
Input leakage current
0.01
6.45
uA
IMEM
VMEM quiescent current
0.02
15.03
uA
Table 3-8 DC characteristics for VDDIO/VDDIO_5T/VDDIO_Codec/VDDRTC supplied pins for
1.8V application
Symbol
Parameter
Min
Typical
Max
Unit
VT
Threshold point
0.79
0.86
0.94
V
VT+
Schmitt trig low to high threshold point
0.95
1.06
1.16
V
28
X1000 IoT Application Processor Data Sheet
Copyright © 2005-2017 Ingenic Semiconductor Co., Ltd. All rights reserved.
Electrical Specifications
VT–
Schmitt trig high to low threshold point
0.58
0.69
0.79
V
VTPU
Threshold point with pull-up resistor enabled
0.79
0.86
0.94
V
VTPD
Threshold point with pull-down resistor enabled
0.79
0.86
0.94
V
0.95
1.06
1.16
V
0.58
0.68
0.78
V
0.96
1.07
1.17
V
0.59
0.69
0.79
V
VTPU+
VTPU–
VTPD+
VTPD–
Schmitt trig low to high threshold point with pull-up
resistor enabled
Schmitt trig high to low threshold point with pull-down
resistor enabled
Schmitt trig low to high threshold point with pull-down
resistor enabled
Schmitt trig high to low threshold point with pull-up
resistor enabled
IL
Input Leakage Current @ VI=1.8V or 0V
±10
μA
IOZ
Tri-State output leakage current @ VI=1.8V or 0V
±10
μA
RPU
Pull-up Resistor
66
114
211
kΩ
RPD
Pull-down Resistor
58
103
204
kΩ
VOL
Output low voltage
0.45
V
VOH
Output high voltage
IOL
Low level output current @ VOL(max)
IOH
High level output current @ VOH(min)
1.35
V
8mA
5.3
9.8
15.8
mA
16mA
10.8
19.7
31.8
mA
8mA
3.3
8.3
16.6
mA
16mA
6.6
16.5
33.2
mA
Table 3-9 DC characteristics for VDDIO/VDDIO_5T/VDDIO_Codec/VDDRTC supplied pins for
2.5V application
Symbol
Parameter
Min
Typical
Max
Unit
VT
Threshold point
1.06
1.17
1.27
V
VT+
Schmitt trig low to high threshold point
1.27
1.40
1.50
V
VT–
Schmitt trig high to low threshold point
0.86
0.98
1.09
V
VTPU
Threshold point with pull-up resistor enabled
1.05
1.16
1.25
V
VTPD
Threshold point with pull-down resistor enabled
1.06
1.17
1.27
V
1.27
1.39
1.48
V
0.85
0.97
1.08
V
1.27
1.41
1.50
V
0.88
0.99
1.10
V
VTPU+
VTPU–
VTPD+
VTPD–
Schmitt trig low to high threshold point with pull-up
resistor enabled
Schmitt trig high to low threshold point with pull-down
resistor enabled
Schmitt trig low to high threshold point with pull-down
resistor enabled
Schmitt trig high to low threshold point with pull-up
resistor enabled
IL
Input Leakage Current @ VI=1.8V or 0V
±10
μA
IOZ
Tri-State output leakage current @ VI=1.8V or 0V
±10
μA
RPU
Pull-up Resistor
120
kΩ
43
69
29
X1000 IoT Application Processor Data Sheet
Copyright © 2005-2017 Ingenic Semiconductor Co., Ltd. All rights reserved.
Electrical Specifications
RPD
Pull-down Resistor
41
VOL
Output low voltage
VOH
Output high voltage
IOL
Low level output current @ VOL(max)
IOH
High level output current @ VOH(min)
66
124
kΩ
0.7
V
1.7
V
8mA
11.6
19.4
28.4
mA
16mA
23.3
39.1
57.2
mA
8mA
9.3
19.4
34.6
mA
16mA
18.6
38.7
69.2
mA
Table 3-10 DC characteristics for VDDIO/VDDIO_5T/VDDIO_Codec/VDDRTC supplied pins for
3.3V application
Symbol
Parameter
Min
Typical
Max
Unit
VT
Threshold point
1.39
1.50
1.65
V
VT+
Schmitt trig low to high threshold point
1.62
1.75
1.90
V
VT–
Schmitt trig high to low threshold point
1.18
1.29
1.44
V
VTPU
Threshold point with pull-up resistor enabled
1.36
1.48
1.64
V
VTPD
Threshold point with pull-down resistor enabled
1.40
1.52
1.66
V
1.62
1.75
1.89
V
1.16
1.28
1.43
V
1.64
1.77
1.91
V
1.19
1.31
1.45
V
VTPU+
VTPU–
VTPD+
VTPD–
Schmitt trig low to high threshold point with pull-up
resistor enabled
Schmitt trig high to low threshold point with pull-down
resistor enabled
Schmitt trig low to high threshold point with pull-down
resistor enabled
Schmitt trig high to low threshold point with pull-up
resistor enabled
IL
Input Leakage Current @ VI=1.8V or 0V
±10
μA
IOZ
Tri-State output leakage current @ VI=1.8V or 0V
±10
μA
RPU
Pull-up Resistor
34
51
81
kΩ
RPD
Pull-down Resistor
35
51
88
kΩ
VOL
Output low voltage
0.4
V
VOH
Output high voltage
IOL
Low level output current @ VOL(max)
IOH
High level output current @ VOH(min)
2.4
V
8mA
10.0
15.2
20.2
mA
16mA
20.2
30.6
40.6
mA
8mA
13.9
28.0
48.2
mA
16mA
27.8
56.0
96.3
mA
3.4 Audio codec
30
X1000 IoT Application Processor Data Sheet
Copyright © 2005-2017 Ingenic Semiconductor Co., Ltd. All rights reserved.
Electrical Specifications
Analog power supply
10
uF
0.1
uF
Logic Power Supply
X1000
VDDD
VSSD
AVDCDC
AIP1
VREFP
MICBIAS
1nF
AVSCDC
AGND
Differential analog input
AIN1
Low noise
Linear Regulator
VCAP
10
uF
0.1
uF
VSSIO_CODEC
Low noise
High PSRR
power supply
LDO
O
10
uF
line out P
4.7nF
150
line out P
150
4.7nF
line out N
150
1uF
150
1uF
150
1uF
150
1uF
150
line out N
150
VDDIO_CODEC
0.1
uF
4.7nF
4.7nF
CODEC_PWMLP
CODEC_PWMLN
CODEC_PWMRP
CODEC_PWMRN
Note: 1. The single-ended/differential input port AIP1/AIN1 can be configure to microphone input or
line input by software.
2. VCAP/AVDCDC each of them requires connecting decoupling capacitors (0.1uF) between the
pads VCAP/AVDCDC and AVSCDC. This ceramic capacitor has to be kept as close as possible
to IC package (closer than 0.2 inch).
3.5 Power On, Reset and BOOT
3.5.1
Power-On Timing
The external voltage regulator and other power-on devices must provide the X1000/E processor with a
specific sequence of power and resets to ensure proper operation. Figure 3-1shows this sequence
and Table 3-11 gives the timing parameters. Following are the name of the power.
VDDRTC: VDDRTC
AVDAUD: AVDCDC
31
X1000 IoT Application Processor Data Sheet
Copyright © 2005-2017 Ingenic Semiconductor Co., Ltd. All rights reserved.
Electrical Specifications
VDD: all 1.2V power supplies, include VDDCORE, PLLVDD12, PLLAVDD
AVD: all other analog power supplies:
VDDIO: all other digital IO, include DDR power supplies: VDDMEM, VDDIO, VDDIO_5T,
VDDIO_Codec
AVDUSB25, AVDUSB33
AVDEFUSE
Table 3-11 Power-On Timing Parameters
Symbol
tR_VDDRTC
tR_VDDIO
Parameter
VDDRTC rise time
VDDIO rise time
[1]
[1]
Delay between VDD arriving 50% (or 90%) to VDDIO
tD_VDDIO
arriving 50% (or 90%)
tR_VDD
VDD rise time
[1]
Delay between VDDRTC arriving 50% (or 90%) to VDD
tD_VDD
arriving 50% (or 90%)
[1]
tR_AVDAUD
AVDAUD rise time
tD_AVDAUD
Delay between AVDAUD arriving 90% to VDD arriving 90%
[1]
tR_AVD
AVD rise time
tD_AVD
Delay between VDDIO arriving 90% to AVD arriving 90%
tD_PPRST_
tD_AVDEFUSE
Delay between AVD stable and PPRST_ de-asserted
Delay between PPRST_ finished and E-fuse programming
power apply
Min
Max
0
5
ms
0
5
ms
0
–
ms
0
5
ms
0
1
ms
0
5
ms
0.01
1
ms
0
5
ms
1
ms
–
ms
–
ms
0
TBD
0
[3]
Unit
[2]
NOTES:
1
The power rise time is defined as 10% to 90%.
2
The PPRST_ must be kept at least 100us. After PPRST_ is deasserted, the corresponding
chip reset will be extended at least 40ms.
3
It must make sure the EXCLK is stable and all power(except AVDEFUSE) is stable.
32
X1000 IoT Application Processor Data Sheet
Copyright © 2005-2017 Ingenic Semiconductor Co., Ltd. All rights reserved.
Electrical Specifications
tR_VDDRTC
VDDRTC
tD_VDD
tD_VDD
tR_VDD
VDD
tD_VDDIO
tD_VDDIO
tR_VDDIO
VDDIO
tD_AVD
tR_AVD
AVD
tD_AVDAUD
tR_AVDAUD
AVDAUD
tD_PPRST_
PPRST_
tD_AVDEFUSE
AVDEFUSE
Figure 3-1 Power-On Timing Diagram
3.5.2
Reset procedure
There 3 reset sources: 1 PPRST_ pin reset; 2 WDT timeout reset; and 3 hibernating reset when exiting
hibernating mode. After reset, program start from boot.
1
PPRST_ pin reset.
This reset is trigged when PPRST_ pin is put to logic 0. It happens in power on RTC power
and RESET-KEY pressed to reset the chip from unknown dead state. The reset end time is
about 1M EXCLK cycles after rising edge of PPRST_.
2
WDT reset.
This reset happens in case of WDT timeout. The reset keeps for about a few RTCLK cycles.
3
Hibernating reset.
This reset happens in case of wakeup the main power from power down. The reset keeps for
about 1ms ~ 125ms programable, plus 1M EXCLK cycles, start after WKUP_ signal is
recognized.
33
X1000 IoT Application Processor Data Sheet
Copyright © 2005-2017 Ingenic Semiconductor Co., Ltd. All rights reserved.
Electrical Specifications
After reset, all GPIO shared pins are put to GPIO input function and most of their internal pull-up/down
resistor are set to on, see “2.5 Pin Descriptions” for details. The PWRON is output 1. The oscillators
are on. The USB 2.0 OTG PHY, the audio CODEC DAC/ADC put in suspend mode.
3.5.3
BOOT
The boot sequence of the X1000/E is controlled by boot_sel [2:0] pin values. The following table lists
them:
Table 3-12
Boot Configuration of X1000/E
boot_sel[2]
boot_sel[1]
boot_sel[0]
Boot configuration
1
X
X
EXTCLK is 26MHz
0
X
X
EXTCLK is 24MHz
X
1
1
Boot from SFC0
X
0
1
Boot from MSC0
X
1
0
Boot from USB 2.0 device
X: means "Don't Care"
The boot procedure is showed in the following flow chart:
After reset, the boot program on the internal boot ROM executes as follows:
1
Disable all interrupts and read boot_sel[2:0] to determine the boot method.
2
If it is boot from MMC/SD card at MSC0, its function pins MSC0_D0, MSC0_CLK,
MSC0_CMD are initialized, the boot program loads the 12KB code from MMC/SD card to
tcsm and jump to it. Only one data bus which is MSC0_D0 is used. The clock EXTCLK/128 is
used initially. When reading data, the clock EXTCLK/4 is used.
3
If it is boot from USB, a block of code will be received through USB cable connected with host
PC and be stored in tcsm. Then branch to this area in tcsm.
4
If it is boot from SPI nor/nand at SFC, its function pins SFC_CLK,SFC_CE,SFC_DR,SFC_DT,
SFC_WP, SFC_HOLD
are initialized, the boot program loads the 12KB code from
MMC/SD card to tcsm and jump to it.
34
X1000 IoT Application Processor Data Sheet
Copyright © 2005-2017 Ingenic Semiconductor Co., Ltd. All rights reserved.
Electrical Specifications
Figure 3-2 Boot flow diagram of X1000/E
35
X1000 IoT Application Processor Data Sheet
Copyright © 2005-2017 Ingenic Semiconductor Co., Ltd. All rights reserved.
Packaging Information
4 Packaging Information
4.1 Overview
X1000/E processor is offered in 190-pin BGA package, which is 13mm x 13mm x 1.2mm outline, 16 x
16 matrix ball grid array and 0.8mm ball pitch, show in Figure 4-1.
4.2 X1000/E Device Dimensions
36
X1000 IoT Application Processor Data Sheet
Copyright © 2005-2017 Ingenic Semiconductor Co., Ltd. All rights reserved.
Packaging Information
Figure 4-1 X1000/E package outline drawing
Notes:
1.
BALL PAD OPENING: 0.315mm；
2.
PRIMARY DATUM C AND SEATING PLANE ARE THE SOLDER BALLS；
3.
DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER,PARALLEL
TO PRIMARY DATUM C；
4.
SPECIAL CHARACTERISTICS C CLASS: bbb,ddd；
5.
THE PATTERN OF PIN 1 FIDUCIAL IS FOR REFERENCE ONLY；
6.
BAN TO USE THE LEVEL 1 ENVIRONMENT-RELATED SUBSTANCES OF JCET
PRESCRIBING；
7.
ALL UNITS ARE IN MILLIMETER；
4.3 Solder Ball Materials
Both the top (joint) and bottom solder ball materials of X1000/E are SAC105.
4.4 Moisture Sensitivity Level
X1000/E package moisture sensitivity is level 3.
37
X1000 IoT Application Processor Data Sheet
Copyright © 2005-2017 Ingenic Semiconductor Co., Ltd. All rights reserved.
PCB Mounting Guidelines
5 PCB Mounting Guidelines
5.1 RoHS compliance
TBD.
5.2 Reflow profile
X1000/E package is lead-free. It’s reflow profile follows the IPC/JEDEC lead-free reflow profile as
contained in J-STD-020C.
38
X1000 IoT Application Processor Data Sheet
Copyright © 2005-2017 Ingenic Semiconductor Co., Ltd. All rights reserved.
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