3.3V QUAD IO Serial Flash
XT25F32B-S
XT25F32B-S
Quad IO Serial NOR Flash
Datasheet
深圳市芯天下技术有限公司
XTX Technology Limited
Tel: (86 755) 28229862
Fax: (86 755) 28229847
Web Site: http://www.xtxtech.com/
Technical Contact: fae@xtxtech.com
* Information furnished is believed to be accurate and reliable. However, XTX Technology Limited assumes no responsibility for the consequences of use of such information or for any infringement of
patents of other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of XTX Technology Limited. Specifications mentioned in this
publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. XTX Technology Limited products are not authorized for use as critical
components in life support devices or systems without express written approval of XTX Technology
Limited. The XTX logo is a registered trademark of XTX Technology Limited. All other names are the
property of their respective own.
Rev 1.2
March/30/2020
Page 1
XT25F32B-S
3.3V QUAD IO Serial Flash
Serial NOR Flash Memory
3.3V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase
e
32M -bit Serial Flash
4096K-byte
256 bytes per programmable page
Temperature Range & Moisture Sensitivity Level
Industrial Level Temperature. (-40℃ to
+85℃), MSL3
Support SFDP & Unique ID
Standard, Dual, Quad SPI
12uA typical standby current
Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#
0.1uA typical power down current
Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#
Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3
QPI: SCLK, CS#, IO0, IO1, IO2, IO3
Sector of 4K-byte
Block of 32/64k-byte
Enable/Disable protection with WP# Pin
Top or Bottom, Sector or Block selection
High Speed Clock Frequency
Package Options
See 1.1 Available Ordering OPN
All Pb-free packages are compliant RoHS,
Halogen-Free and REACH.
Rev 1.2
2.7~3.6V
Minimum 100,000 Program/Erase Cycle
Software/Hardware Write Protection
Write protect all/portion of memory via
software
Single Power Supply Voltage: Full voltage range:
4*256-Byte Security Registers With OTP Lock
Low Power Consumption
Advanced security Features
Flexible Architecture
March/30/2020
108MHz for fast read with 30PF load
Dual I/O Data transfer up to 216Mbits/s
Quad I/O Data transfer up to 344Mbits/s
QPI Mode Data transfer up to 288Mbits/s
Continuous Read With 8/16/32/64-byte
Wrap
Program/Erase Speed
Page Program time: 350us typical
Sector Erase time: 70ms typical
Block Erase time: 0.15/0.25s typical
Chip Erase time: 10s typical
Page 2
3.3V QUAD IO Serial Flash
XT25F32B-S
CONTENTS
1.
GENERAL DESCRIPTION ............................................................................................................................................. 5
1.1.
1.2.
1.3.
1.4.
AVAILABLE ORDERING OPN ...................................................................................................................................... 5
CONNECTION DIAGRAM ........................................................................................................................................... 6
PIN DESCRIPTION ................................................................................................................................................... 6
BLOCK DIAGRAM .................................................................................................................................................... 7
2.
MEMORY ORGANIZATION ......................................................................................................................................... 8
3.
DEVICE OPERATION ................................................................................................................................................... 9
4.
DATA PROTECTION .................................................................................................................................................. 10
5.
STATUS REGISTER .................................................................................................................................................... 13
6.
COMMANDS DESCRIPTION ...................................................................................................................................... 15
6.1.
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
6.8.
6.9.
6.10.
6.11.
6.12.
6.13.
6.14.
6.15.
6.16.
6.17.
6.18.
6.19.
6.20.
6.21.
6.22.
6.23.
6.24.
6.25.
6.26.
6.27.
6.28.
6.29.
6.30.
6.31.
6.32.
6.33.
6.34.
6.35.
7.
WRITE ENABLE (WREN) (06H) .............................................................................................................................. 19
WRITE ENABLE FOR VOLATILE STATUS REGISTER (50H) ................................................................................................. 19
WRITE DISABLE (WRDI) (04H) ............................................................................................................................... 20
READ STATUS REGISTER (RDSR) (05H OR 35H) .......................................................................................................... 21
WRITE STATUS REGISTER (WRSR) (01H) .................................................................................................................. 22
READ DATA BYTES (READ) (03H) ........................................................................................................................... 22
READ DATA BYTES AT HIGHER SPEED (FAST READ) (0BH) .............................................................................................. 23
DUAL OUTPUT FAST READ (3BH) ............................................................................................................................. 24
QUAD OUTPUT FAST READ (6BH) ............................................................................................................................ 24
DUAL I/O FAST READ (BBH) .................................................................................................................................. 25
QUAD I/O FAST READ (EBH) .................................................................................................................................. 27
QUAD I/O WORD FAST READ (E7H) ........................................................................................................................ 29
SET BURST WITH WRAP (77H) ................................................................................................................................ 30
PAGE PROGRAM (PP) (02H) .................................................................................................................................. 31
QUAD PAGE PROGRAM (QPP) (32H) ....................................................................................................................... 32
SECTOR ERASE (SE) (20H) ..................................................................................................................................... 33
32KB BLOCK ERASE (BE) (52H) .............................................................................................................................. 34
64KB BLOCK ERASE (BE) (D8H) ............................................................................................................................. 35
CHIP ERASE (CE) (60/C7H) ................................................................................................................................... 36
DEEP POWER-DOWN (DP) (B9H)............................................................................................................................ 38
RELEASE FROM DEEP POWER-DOWN AND READ DEVICE ID (RDI) (ABH) .......................................................................... 39
READ MANUFACTURE ID/ DEVICE ID (REMS) (90H) ................................................................................................... 41
READ MANUFACTURE ID/ DEVICE ID DUAL I/O (92H) ................................................................................................. 42
READ MANUFACTURE ID/ DEVICE ID QUAD I/O (94H) ................................................................................................. 43
READ IDENTIFICATION (RDID) (9FH) ........................................................................................................................ 43
ERASE SECURITY REGISTERS (44H) ........................................................................................................................... 44
PROGRAM SECURITY REGISTERS (42H) ...................................................................................................................... 44
READ SECURITY REGISTERS (48H) ............................................................................................................................ 45
SET READ PARAMETERS (C0H) ................................................................................................................................ 46
BURST READ WITH WRAP (0CH).............................................................................................................................. 47
ENABLE QPI (38H) .............................................................................................................................................. 47
CONTINUOUS READ MODE RESET (CRMR) (FFH)/ DISABLE QPI (FFH) ............................................................................ 48
ENABLE RESET (66H) AND RESET (99H) .................................................................................................................... 49
READ SERIAL FLASH DISCOVERABLE PARAMETER (5AH) ................................................................................................. 50
READ UNIQUE ID (RUID) ...................................................................................................................................... 51
ELECTRICAL CHARACTERISTICS................................................................................................................................. 56
7.1.
7.2.
7.3.
7.4.
Rev 1.2
POWER-ON TIMING .............................................................................................................................................. 56
INITIAL DELIVERY STATE ......................................................................................................................................... 56
DATA RETENTION AND ENDURANCE .......................................................................................................................... 56
LATCH UP CHARACTERISTICS .................................................................................................................................... 56
March/30/2020
Page 3
3.3V QUAD IO Serial Flash
7.5.
7.6.
7.7.
7.8.
XT25F32B-S
ABSOLUTE MAXIMUM RATINGS ............................................................................................................................... 57
CAPACITANCE MEASUREMENT CONDITION ................................................................................................................. 57
DC CHARACTERISTICS ............................................................................................................................................ 58
AC CHARACTERISTICS ............................................................................................................................................ 59
8.
ORDERING INFORMATION ....................................................................................................................................... 62
9.
PACKAGE INFORMATION ......................................................................................................................................... 63
9.1.
9.2.
9.3.
9.4.
9.5.
10.
Rev 1.2
PACKAGE SOP8 150MIL ....................................................................................................................................... 63
PACKAGE SOP8 208MIL ....................................................................................................................................... 64
PACKAGE DFN8 (2X3X0.55) MM ............................................................................................................................ 65
PACKAGE DFN8 (2X3X0.40) MM ............................................................................................................................ 66
PACKAGE DFN8 (4X3X0.55) MM ............................................................................................................................ 67
REVISION HISTORY .............................................................................................................................................. 68
March/30/2020
Page 4
XT25F32B-S
3.3V QUAD IO Serial Flash
1.
GENERAL DESCRIPTION
The XT25F32B-S (32M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3
(HOLD#). The Dual I/O data is transferred with speed of 216Mbits/s and the Quad I/O & Quad output data is
transferred with speed of 344 Mbits/s.
1.1. Available Ordering OPN
Rev 1.2
OPN
Package Type
Package Carrier
XT25F32BSOIGU-S
SO8 150mil
Tube
XT25F32BSOIGT-S
SO8 150mil
Tape & Reel
XT25F32BSSIGU-S
SO8 208mil
Tube
XT25F32BSSIGT-S
SO8 208mil
Tape & Reel
XT25F32BWOIGT-S
WSON8 6x5mm
Tape & Reel
XT25F32BDFIGT-S
DFN8 2x3x0.55 mm
Tape & Reel
XT25F32BDTIGT-S
DFN8 2x3x0.40 mm
Tape & Reel
XT25F32BDXIGT-S
DFN8 4x3x0.55 mm
Tape & Reel
March/30/2020
Page 5
XT25F32B-S
3.3V QUAD IO Serial Flash
1.2. Connection Diagram
CS#
1
8
VCC
SO(IO1)
2
7
HOLD#(IO3)
Top View
WP#(IO2)
3
6
SCLK
VSS
4
5
SI(IO0)
8-PIN SOP/DFN/WSON
1.3. Pin Description
Pin Name
I/O
CS#
I
SO (IO1)
I/O
Data Output (Data Input Output 1)
WP# (IO2)
I/O
Write Protect Input (Data Input Output 2)
VSS
Rev 1.2
Chip Select Input
Ground
SI (IO0)
I/O
SCLK
I
HOLD# (IO3)
I/O
VCC
Description
Data Input (Data Input Output 0)
Serial Clock Input
Hold Input (Data Input Output 3)
Power Supply
March/30/2020
Page 6
XT25F32B-S
3.3V QUAD IO Serial Flash
1.4. Block Diagram
Write
Control
Logic
Status
Register
HOLD#(IO3)
SCLK
CS#
SPI
Command &
Control
Logic
High Voltage
Generators
Page Address
Latch/Counter
Rev 1.2
Flash
Memory
Column Decode And
256-Byte Page Buffer
SI(IO0)
SO(IO1)
Write Protect Logic
And Row Decode
WP#(IO2)
Byte Address
Latch/Counter
March/30/2020
Page 7
XT25F32B-S
3.3V QUAD IO Serial Flash
2.
MEMORY ORGANIZATION
XT25F32B-S
Each Device has
Each block has
Each sector has
Each page has
Remark
4M
64K/32K
4K
256
bytes
16K
256/128
16
-
pages
1K
16/8
-
-
sectors
64/128
-
-
-
blocks
UNIFORM BLOCK SECTOR ARCHITECTURE
XT25F32B-S 64K Bytes Block Sector Architecture
Block
63
62
……
……
2
1
0
Rev 1.2
Sector
Address range
1023
3FF000H
3FFFFFH
……
……
……
1008
3F0000H
3F0FFFH
1007
3EF000H
3EFFFFH
……
……
……
992
3E0000H
3E0FFFH
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
47
02F000H
02FFFFH
……
……
……
32
020000H
020FFFH
31
01F000H
01FFFFH
……
……
……
16
010000H
010FFFH
15
00F000H
00FFFFH
……
……
……
0
000000H
000FFFH
March/30/2020
Page 8
3.3V QUAD IO Serial Flash
3.
XT25F32B-S
DEVICE OPERATION
SPI Mode
Standard SPI
The XT25F32B-S features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#),
Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is
latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK. Note: “WP#” & “HOLD#” pin
require external pull-up.
Dual SPI
The XT25F32B-S supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast
Read” (3BH and BBH) commands. These commands allow data to be transferred to or from the device at two
times the rate of the standard SPI. When using the Dual SPI command the SI and SO pins become bidirectional
I/O pins: IO0 and IO1. Note: “WP#” & “HOLD#” pin require external pull-up.
Quad SPI
The XT25F32B-S supports Quad SPI operation when using the “Quad Output Fast Read”,” Quad I/O Fast
Read”, “Quad I/O Word Fast Read” (6BH, EBH, E7H) commands. These commands allow data to be transferred
to or from the device at four times the rate of the standard SPI. When using the Quad SPI command the SI and
SO pins become bidirectional I/O pins: IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3. Quad SPI
commands require the non-volatile Quad Enable bit (QE) in Status Register to be set.
QPI
The XT25F32B-S supports Quad Peripheral Interface (QPI) operations only when the device is switched
from Standard/Dual/Quad SPI mode to QPI mode using the “Enable the QPI (38H)” command. The QPI mode
utilizes all four IO pins to input the command code. Standard/Dual/Quad SPI mode and QPI mode are exclusive.
Only one mode can be active at any given times. “Enable the QPI (38H)” and “Disable the QPI (FFH)” commands
are used to switch between these two modes. Upon power-up and after software reset using “Reset (99H)”
command, the default state of the device is Standard/Dual/Quad SPI mode. The QPI mode requires the nonvolatile Quad Enable bit (QE) in Status Register to be set.
Hold
The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation of write status register, programming, or erasing in progress.
The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal
being low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends
on rising edge of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until
SCLK being low).
Both SI and SCLK don’t care during the HOLD operation, if CS# drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and then
CS# must be at low.
Rev 1.2
March/30/2020
Page 9
3.3V QUAD IO Serial Flash
XT25F32B-S
Figure1. Hold Condition
CS#
SCLK
HOLD#
HOLD
HOLD
4.
DATA PROTECTION
The XT25F32B-S provides the following data protection methods:
Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL
bit will return to reset by the following situation:
Power-Up
Write Disable (WRDI)
Write Status Register (WRSR)
Page Program (PP)
Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)
Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1, BP0) bits define the section of the
memory array that can be read but not change.
Hardware Protection Mode: WP# going low to protected the BP0~BP4 bits and SRP bit.
Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release
from Deep Power-Down Mode command.
Rev 1.2
March/30/2020
Page 10
XT25F32B-S
3.3V QUAD IO Serial Flash
Table1.0 XT25F32B-S Protected area size (CMP=0)
Status Register Content
Memory Content
BP4
BP3
BP2
BP1
BP0
Blocks
Addresses
Density
Portion
X
X
0
0
0
NONE
NONE
NONE
NONE
0
0
0
0
1
63
3F0000H-3FFFFFH
64KB
Upper 1/64
0
0
0
1
0
62 to 63
3E0000H-3FFFFFH
128KB
Upper 1/32
0
0
0
1
1
60 to 63
3C0000H-3FFFFFH
256KB
Upper 1/16
0
0
1
0
0
56 to 63
380000H-3FFFFFH
512KB
Upper 1/8
0
0
1
0
1
48 to 63
300000H-3FFFFFH
1MB
Upper 1/4
0
0
1
1
0
32 to 63
200000H-3FFFFFH
2MB
Upper 1/2
0
1
0
0
1
0
000000H-00FFFFH
64KB
Lower 1/64
0
1
0
1
0
0 to 1
000000H-01FFFFH
128KB
Lower 1/32
0
1
0
1
1
0 to 3
000000H-03FFFFH
256KB
Lower 1/16
0
1
1
0
0
0 to 7
000000H-07FFFFH
512KB
Lower 1/8
0
1
1
0
1
0 to 15
000000H-0FFFFFH
1MB
Lower 1/4
0
1
1
1
0
0 to 31
000000H-1FFFFFH
2MB
Lower 1/2
X
X
1
1
1
0 to 63
000000H-3FFFFFH
4MB
ALL
1
0
0
0
1
63
3FF000H-3FFFFFH
4KB
Top Block
1
0
0
1
0
63
3FE000H-3FFFFFH
8KB
Top Block
1
0
0
1
1
63
3FC000H-3FFFFFH
16KB
Top Block
1
0
1
0
X
63
3F8000H-3FFFFFH
32KB
Top Block
1
0
1
1
0
63
3F8000H-3FFFFFH
32KB
Top Block
1
1
0
0
1
0
000000H-000FFFH
4KB
Bottom Block
1
1
0
1
0
0
000000H-001FFFH
8KB
Bottom Block
1
1
0
1
1
0
000000H-003FFFH
16KB
Bottom Block
1
1
1
0
X
0
000000H-007FFFH
32KB
Bottom Block
1
1
1
1
0
0
000000H-007FFFH
32KB
Bottom Block
Rev 1.2
March/30/2020
Page 11
XT25F32B-S
3.3V QUAD IO Serial Flash
Table1.1 XT25F32B-S Protected area size (CMP=1)
Status Register Content
Memory Content
BP4
BP3
BP2
BP1
BP0
Blocks
Addresses
Density
Portion
X
X
0
0
0
ALL
000000H-3FFFFFH
4MB
ALL
0
0
0
0
1
0 to 62
000000H-3EFFFFH
4032KB
Lower 63/64
0
0
0
1
0
0 to 61
000000H-3DFFFFH
3968KB
Lower 31/32
0
0
0
1
1
0 to 59
000000H-3BFFFFH
3840KB
Lower 15/16
0
0
1
0
0
0 to 55
000000H-37FFFFH
3584KB
Lower 7/8
0
0
1
0
1
0 to 47
000000H-2FFFFFH
3MB
Lower 3/4
0
0
1
1
0
0 to 31
000000H-1FFFFFH
2MB
Lower 1/2
0
1
0
0
1
1 to 63
000000H-00FFFFH
4032KB
Upper 63/64
0
1
0
1
0
2 to 63
000000H-01FFFFH
3968KB
Upper 31/32
0
1
0
1
1
4 to 63
000000H-03FFFFH
3840KB
Upper 15/16
0
1
1
0
0
8 to 63
000000H-07FFFFH
3584KB
Upper 7/8
0
1
1
0
1
16 to 63
000000H-0FFFFFH
3MB
Upper 3/4
0
1
1
1
0
32 to 63
000000H-1FFFFFH
2MB
Upper 1/2
X
X
1
1
1
NONE
NONE
NONE
NONE
1
0
0
0
1
0 to 63
000000H-3FEFFFH
4092KB
L-1023/1024
1
0
0
1
0
0 to 63
000000H-3FDFFFH
4088KB
L-511/512
1
0
0
1
1
0 to 63
000000H-3FBFFFH
4080KB
L-255/256
1
0
1
0
X
0 to 63
000000H-3F7FFFH
4064KB
L-127/128
1
0
1
1
0
0 to 63
000000H-3F7FFFH
4064KB
L-127/128
1
1
0
0
1
0 to 63
001000H-3FFFFFH
4092KB
U-1023/1024
1
1
0
1
0
0 to 63
002000H-3FFFFFH
4088KB
U-511/512
1
1
0
1
1
0 to 63
004000H-3FFFFFH
4080KB
U-255/256
1
1
1
0
X
0 to 63
008000H-3FFFFFH
4064KB
U-127/128
1
1
1
1
0
0 to 63
008000H-3FFFFFH
4064KB
U-127/128
Rev 1.2
March/30/2020
Page 12
XT25F32B-S
3.3V QUAD IO Serial Flash
5.
STATUS REGISTER
S15
S14
S13
S12
S11
S10
S9
S8
Reserved
CMP
Reserved
Reserved
Reserved
LB
QE
SRP1
S7
S6
S5
S4
S3
S2
S1
S0
SRP0
BP4
BP3
BP2
BP1
BP0
WEL
WIP
The status and control bits of the Status Register are as follows:
WIP bit.
The Write In Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress. When WIP bit sets to 1, means the device is busy in program/erase/write status register progress,
when WIP bit sets 0, means the device is not in program/erase/write status register progress.
WEL bit.
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the
internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erase command is accepted.
BP4, BP3, BP2, BP1, BP0 bits.
The Block Protect (BP4, BP3, BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against Program and Erase commands. These bits are written with the Write Status Register
(WRSR) command. When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant memory area
(as defined in Table1) becomes protected against Page Program (PP), Sector Erase (SE) and Block Erase (BE)
commands. The Block Protect (BP4, BP3, BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The Chip Erase (CE) command is executed if the Block Protect (BP2, BP1, BP0) bits are
0 and CMP=0 or the Block Protect (BP2, BP1, BP0) bits are 1 and CMP=1.
SRP1, SRP0 bits.
The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The
SRP bits control the method of write protection: software protection, hardware protection, power supply lockdown or one-time programmable protection.
SRP1
SRP0
WP#
0
0
X
Software Protected
The Status Register can be written to after a Write Enable
command, WEL=1. (Default)
0
1
0
Hardware Protected
WP#=0, the Status Register locked and cannot be written
until the next power-up.
0
1
1
Hardware Unprotected
WP#=1, the Status Register is unlocked and can be written to
after a Write Enable command, WEL=1.
1
0
X
Power Supply LockDown(1)(2)
Status Register is protected and cannot be written to again
until the next Power-Down, Power-Up cycle.
1
1
X
Rev 1.2
Status Register
Description
One-Time Program(2)
Status Register is permanently protected and cannot be written to.
March/30/2020
Page 13
3.3V QUAD IO Serial Flash
XT25F32B-S
NOTE:
1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.
2. This feature is available on special order(XT25F32B-SxxSx). Please contact XTX for details.
QE bit.
The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation.
When the QE bit is set to 0 (Default) the WP# pin and HOLD# pin are enable. When the QE pin is set to 1, the
Quad IO2 and IO3 pins are enabled. (The QE bit should never be set to 1 during standard SPI or Dual SPI operation if the WP# or HOLD# pins are tied directly to the power supply or ground).
LB bit.
The LB bit is a non-volatile One Time Program (OTP) bit in Status Register (S10) that provide the write protect control and status to the Security Registers. The default state of LB is 0, the security registers are unlocked.
LB can be set to 1 using the Write Register instruction. LB is One Time Programmable, once it’s set to 1, the Security Registers will become read-only permanently.
CMP bit.
The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction with the
BP4-BP0 bits to provide more flexibility for the array protection. Please see the Status registers Memory Protection table for details. The default setting is CMP=0.
Rev 1.2
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XT25F32B-S
3.3V QUAD IO Serial Flash
6.
COMMANDS DESCRIPTION
All commands, addresses and data are shifted in and out of the device, beginning with the most significant
bit on the first rising edge of SCLK after CS# is driven low. Then, the one-byte command code must be shifted in
to the device, most significant bit first on SI, each bit being latched on the rising edges of SCLK.
See Table2, every command sequence starts with a one-byte command code. Depending on the command,
this might be followed by address bytes, or by data bytes, or by both or none. CS# must be driven high after the
last bit of the command sequence has been shifted in. For the command of Read, Fast Read, Read Status Register or Release from Deep Power-Down, and Read Device ID, the shifted-in command sequence is followed by a
data-out sequence. CS# can be driven high after any bit of the data-out sequence is being shifted out.
For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable, Write Disable or Deep Power-Down command, CS# must be driven high exactly at a byte boundary, otherwise the command is rejected, and is not executed. That is CS# must be driven high when the number of clock
pulses after CS# being driven low is an exact multiple of eight. For Page Program, if at any time the input byte is
not a full byte, nothing will happen and WEL will not be reset.
Table 2. Commands
Command Name
Byte1
Byte2
Byte3
Byte4
Byte5
Byte6
n-Bytes
Write Enable
06H
Write Enable for Volatile
Status Register
50H
Write Disable
04H
Read Status Register
05H
(S7-S0)
(continuous)
Read Status Register-1
35H
(S15-S8)
(continuous)
Write Status Register
01H
(S7-S0)
(S15-S8)
Read Data
03H
A23-A16
A15-A8
A7-A0
(D7-D0)
Fast Read
0BH
A23-A16
A15-A8
A7-A0
dummy
Dual Output Fast Read
3BH
A23-A16
A15-A8
A7-A0
dummy
Dual I/O Fast Read
Quad Output Fast Read
Quad I/O Fast Read
(continuous)
(D7-D0)(1) (continuous)
A23-A8(2)
M7-M0(2)
(D7-D0)(1)
(continuous)
6BH
A23-A16
A15-A8
A7-A0
Dummy(5)
(D7-D0)(3)
(continuous)
M7-M0(4)
Dummy(6)
(D7-D0)(3)
(continuous)
dummy
(D7-D0)(3) (continuous)
A23-A0
EBH
M7-M0(4)
A23-A0
E7H
Continuous Read Reset
FFH
Page Program
02H
A23-A16
A15-A8
A7-A0
(D7-D0)
Quad Page Program
32H
A23-A16
A15-A8
A7-A0
(D7-D0)(3)
Sector Erase
20H
A23-A16
A15-A8
A7-A0
Block Erase(32KB)
52H
A23-A16
A15-A8
A7-A0
Block Erase(64KB)
D8H
A23-A16
A15-A8
A7-A0
dummy
dummy
dummy
Rev 1.2
(continuous)
BBH
Read
Enable QPI
Set Burst with Wrap
(D7-D0)
A7-A0
Quad I/O Word Fast
Chip Erase
(Next byte) (continuous)
(Next byte)
C7/60H
38H
77H
March/30/2020
W6-W4
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XT25F32B-S
3.3V QUAD IO Serial Flash
Deep Power-Down
B9H
Release From Deep
Power-Down, And Read
Device ID
Release From Deep
Power-Down
ABH
dummy
dummy
dummy
(DID7-DID0)
ABH
(continuous)
(MID7MID0)
Manufacturer/Device ID
90H
dummy
dummy
00H
Manufacturer/Device ID
by Dual I/O
92H
A23-A8
A7-A0,
M[7:0]
(M7-M0)
(ID7-ID0)
(continuous)
Manufacturer/Device ID
by Quad I/O
94H
A23-A0,
M[7:0]
dummy
(M7-M0)
(ID7-ID0)
(continuous)
Read Serial Flash
Discoverable Parameters
5AH
A23-A16
A15-A8
A7-A0
dummy
(D7-D0)
Read Unique ID
5AH
00H
01H
94H
dummy
(D7-D0)
Read Identification
9FH
(MID7MID0)
(JDID15-J
(JDID7-JDI
DID8)
D0)
Erase Security Register(8)
Program Security
44H
A23-A16
A15-A8
A7-A0
Register(8)
Read Security Register(8)
42H
A23-A16
A15-A8
A7-A0
(D7-D0)
(Next byte)
48H
A23-A16
A15-A8
A7-A0
dummy
(D7-D0)
Enable Reset
66H
Reset
99H
Rev 1.2
March/30/2020
(DID7-DID0)
(continuous)
(continuous)
(continuous)
(continuous)
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XT25F32B-S
3.3V QUAD IO Serial Flash
Table2a. Commands (QPI)
Command Name
Byte1
Byte2
Byte3
Byte4
Byte5
Byte6
Clock Number
（0,1）
（2,3）
（4,5）
（6,7）
（8,9）
（10,11）
Write Enable
06H
Write Enable for Volatile Status
Register
50H
Write Disable
04H
Read Status Register
05H
(S7-S0)
Read Status Register-1
35H
(S15-S8)
Write Status Register
01H
(S7-S0)
(S15-S8)
Page Program
02H
A23-A16
A15-A8
A7-A0
(D7-D0)
(Next byte)
Sector Erase
20H
A23-A16
A15-A8
A7-A0
Block Erase(32KB)
52H
A23-A16
A15-A8
A7-A0
Block Erase(64KB)
D8H
A23-A16
A15-A8
A7-A0
Chip Erase
C7/60H
Deep Power-Down
B9H
Set Read Parameters
C0H
P7-P0
Fast Read
0BH
A23-A16
A15-A8
A7-A0
dummy
(D7-D0)
Burst Read with Wrap
0CH
A23-A16
A15-A8
A7-A0
dummy
(D7-D0)
Quad I/O Fast Read
EBH
A23-A0
dummy(5)
(D7-D0)(3)
Release from Deep PowerDown, And Read Device ID(10)
ABH
M7-M0(4)
dummy
dummy
dummy * N
(ID7-ID0)
Manufacturer/Device ID(11)
90H
dummyx2
00H
dummy * N
MID7~MID0
Disable QPI
FFH
Enable Reset
66H
Reset
99H
(ID7-ID0)
NOTE:
1. Dual Output data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
2. Dual Input Address
IO0 = A22, A20, A18, A16, A14, A12, A10, A8,A6, A4, A2, A0, M6, M4, M2, M0
IO1 = A23, A21, A19, A17, A15, A13, A11, A9,A7, A5, A3, A1, M7, M5, M3, M1
3. Quad Output Data
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3, …..)
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3.3V QUAD IO Serial Flash
4. Quad Input Address
IO0 = A20, A16, A12, A8, A4, A0, M4, M0
IO1 = A21, A17, A13, A9, A5, A1, M5, M1
IO2 = A22, A18, A14, A10, A6, A2, M6, M2
IO3 = A23, A19, A15, A11, A7, A3, M7, M3
5. Quad I/O Fast Read Data
IO0 = (x, x, x, x, D4, D0,…)
IO1 = (x, x, x, x, D5, D1,…)
IO2 = (x, x, x, x, D6, D2,…)
IO3 = (x, x, x, x, D7, D3,…)
6. Quad I/O Word Fast Read Data
IO0 = (x, x, D4, D0,…)
IO1 = (x, x, D5, D1,…)
IO2 = (x, x, D6, D2,…)
IO3 = (x, x, D7, D3,…)
7. Quad I/O Word Fast Read Data: the lowest address bit must be 0.
8. Security Registers Address:
Security Register1: A23-A16=00H, A15-A8=01H, A7-A0= Byte Address;
Security Register2: A23-A16=00H, A15-A8=02H, A7-A0= Byte Address;
Security Register3: A23-A16=00H, A15-A8=03H, A7-A0= Byte Address.
Security Register4: A23-A16=00H, A15-A8=04H, A7-A0= Byte Address.
9. QPI Command, Address, Data input/output format:
CLK# 0 1 2 3
4 5
6 7 8 9 10 11
IO0 = C4, C0, A20, A16, A12, A8, A4, A0, D4, D0, D4, D0
IO1 = C5, C1, A21, A17, A13, A9, A5, A1, D5, D1, D5, D1
IO2 = C6, C2, A22, A18, A14, A10, A6, A2, D6, D2, D6, D2
IO3 = C7, C3, A23, A19, A15, A11, A7, A3, D7, D3, D7, D3
10. QPI mode: Release from Deep Power-Down, And Read Device ID (ABH)
N dummy cycles should be inserted before ID read cycle, refer to C0H command
11. QPI mode: Manufacturer/Device ID (90H)
N dummy cycles should be inserted before ID read cycle, refer to C0H command
Table of ID Definitions:
XT25F32B-S
Operation Code
MID7-MID0
ID15-ID8
9FH
0B
40
90H
0B
16
15
ABH
Rev 1.2
ID7-ID0
15
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3.3V QUAD IO Serial Flash
XT25F32B-S
6.1. Write Enable (WREN) (06H)
The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch
(WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE) and
Write Status Register (WRSR) command. The Write Enable (WREN) command sequence: CS# goes low sending
the Write Enable command CS# goes high.
Figure2. Write Enable Sequence Diagram
CS#
0 1 2 3 4 5 6 7
SCLK
Command
SI
SO
06H
High-Z
Figure 2a. Write Enable Sequence Diagram (QPI)
CS#
0
1
SCLK
06H
SI(IO0)
0
0
SO(IO1)
0
1
WP#(IO2)
0
1
0
HOLD#(IO3)
0
6.2. Write Enable for Volatile Status Register (50H)
The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to
change the system configuration and memory protection schemes quickly without waiting for the typical nonvolatile bit write cycles or affecting the endurance of the Status Register non-volatile bits. The Write Enable for
Volatile Status Register command must be issued prior to a Write Status Register command and any other commands can't be inserted between them. Otherwise, Write Enable for Volatile Status Register will be cleared. The
Write Enable for Volatile Status Register command will not set the Write Enable Latch bit, it is only valid for the
Write Status Register command to change the volatile Status Register bit values.
Figure3. Write Enable for Volatile Status Register Sequence Diagram
CS#
0 1 2 3 4 5 6 7
SCLK
Command
SI
SO
Rev 1.2
50H
High-Z
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3.3V QUAD IO Serial Flash
XT25F32B-S
Figure3a. Write Enable for Volatile Status Register Sequence Diagram (QPI)
CS#
0
1
SCLK
50H
SI(IO0)
1
0
SO(IO1)
0
0
WP#(IO2)
1
HOLD#(IO3)
0
0
0
6.3. Write Disable (WRDI) (04H)
The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command
sequence: CS# goes low sending the Write Disable commandCS# goes high. The WEL bit is reset by following condition: Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block
Erase and Chip Erase commands.
Figure 4. Write Disable Sequence Diagram
CS#
0 1 2 3 4 5 6 7
SCLK
Command
SI
SO
04H
High-Z
Figure 4a. Write Disable Sequence Diagram (QPI)
CS#
0
1
SCLK
04H
Rev 1.2
SI(IO0)
0
0
SO(IO1)
0
0
WP#(IO2)
0
HOLD#(IO3)
0
1
0
March/30/2020
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XT25F32B-S
3.3V QUAD IO Serial Flash
6.4. Read Status Register (RDSR) (05H or 35H)
The Read Status Register (RDSR) command is for reading the Status Register. The Status Register can be
read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these
cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new command
to the device. It is also possible to read the Status Register continuously. For command code “05H”, the SO will
output Status Register bits S7~S0. The command code “35H”, the SO will output Status Register bits S15~S8.
Figure 5. Read Status Register Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK
Command
SI
05H or 35H
S7~S0 or S15~S8 out
High-Z
SO
7 6 5 4 3 2 1
S7~S0 or S15~S8 out
0 7 6 5 4 3 2 1
MSB
0 7
MSB
Figure5a. Read Status Register Sequence Diagram (QPI)
CS#
0
1
2
3
4
5
SCLK
05H
SI(IO0)
0
1
4
0
4
0
SO(IO1)
0
0
5
1
5
1
WP#(IO2)
0
1
6
2
6
2
HOLD#(IO3)
0
0
7
3
7
3
S7~S0
S7~S0
CS#
0
1
2
3
4
5
SCLK
35H
SI(IO0)
1
1
4
0
4
0
SO(IO1)
1
0
5
1
5
1
WP#(IO2)
0
1
6
2
6
2
HOLD#(IO3)
0
0
7
3
7
3
S15~S8
Rev 1.2
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S15~S8
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3.3V QUAD IO Serial Flash
6.5. Write Status Register (WRSR) (01H)
The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before
it can be accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable (WREN) command has been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) command has no effect on S15, S13, S12, S11, S1 and S0 of the Status
Register. CS# must be driven high after the eighth or sixteen bit of the data byte has been latched in. If not, the
Write Status Register (WRSR) command is not executed. If CS# is driven high after eighth bit of the data byte,
the CMP and QE bit will be cleared to 0. As soon as CS# is driven high, the self-timed Write Status Register cycle
(whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may
still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the
self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write
Enable Latch (WEL) is reset.
The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4,
BP3, BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table1.
The Write Status Register (WRSR) command also allows the user to set or reset the Status Register Protect (SRP)
bit in accordance with the Write Protect (WP#) signal. The Status Register Protect (SRP) bit and Write Protect
(WP#) signal allow the device to be put in the Hardware Protected Mode. The Write Status Register (WRSR)
command is not executed once the Hardware Protected Mode is entered.
Figure 6. Write Status Register Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK
Command
SI
Status Register in
7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8
01H
MSB
MSB
High-Z
SO
Figure 6a. Write Status Register Sequence Diagram (QPI)
CS#
0
1
2
3
4
5
SCLK
01H
SI(IO0)
0
1
4
0
12
8
SO(IO1)
0
0
5
1
13
9
WP#(IO2)
0
0
6
2
14
10
HOLD#(IO3)
0
0
7
3
15
S7~S0
11
S15~S8
6.6. Read Data Bytes (READ) (03H)
The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), each bit being latched-in
during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being
shifted out, at a Max frequency fR, during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next address after each byte of data is shifted out. The
whole memory can, therefore, be read with a single Read Data Bytes (READ) command. Any Read Data Bytes
(READ) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects
Rev 1.2
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XT25F32B-S
3.3V QUAD IO Serial Flash
on the cycle that is in progress.
Figure 7. Read Data Bytes Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 10 11
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
SCLK
Command
SI
24-bit address(A23:A0)
03H
23 22 21 20 19
7 6 5 4 3 2 1 0
MSB
Data Out1
High-Z
SO
MSB
Data Out2
7 6 5 4 3 2 1 0
6.7. Read Data Bytes At Higher Speed (Fast Read) (0BH)
The Read Data Bytes at Higher Speed (Fast Read) command is for fast reading data out. It is followed by a 3byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the
memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC, during
the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next address after each byte of data is shifted out.
Figure 8. Read Data Bytes at Higher Speed Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 10 11
24 25 26 27 28 29 30 31
SCLK
Command
SI
24-bit address(A23:A0)
0BH
23 22 21 20 19
7 6 5 4 3 2 1
0
MSB
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
Dummy Byte
SI
7 6 5 4 3 2 1
0
Data Out1
SO
7 6 5 4 3 2 1
MSB
Data Out2
0 7 6 5 4 3 2 1
Data Out3
0
MSB
Fast Read (0BH) in QPI mode
The Fast Read command is also supported in QPI mode. In QPI mode, the number of dummy clocks is configured by the “Set Read Parameters (C0H)” command to accommodate a wide range application with different
needs for either maximum Fast Read frequency or minimum data access latency. Depending on the Read Parameter Bits P[5:4] setting, the number of dummy clocks can be configured as either 4/6/8. When the dummy
cycle is configured to 4, addr [0] input must be 0.
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XT25F32B-S
3.3V QUAD IO Serial Flash
Figure 8a. Read Data Bytes at Higher Speed Sequence Diagram (QPI)
CS#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCLK
0BH
SI(IO0)
0
1
4
0
4
0
4
0
4
0
4
0
4
0
SO(IO1)
0
1
5
1
5
1
5
1
5
1
5
1
5
1
WP#(IO2)
0
0
6
2
6
2
6
2
6
2
6
2
6
2
HOLD#(IO3)
0
1
7
3
7
3
7
3
7
3
7
3
7
3
A23-16
A15-8
A7-0
dummy*
Byte1
Byte2
Byte3
*Set Read Parameters Command (C0H) can set the number of dummy cycles
6.8. Dual Output Fast Read (3BH)
The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit
being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle
from SI and SO. The command sequence is shown in Figure 9. The first byte addressed can be at any location.
The address is automatically incremented to the next address after each byte of data is shifted out.
Figure 9. Dual Output Fast Read Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 10 11
24 25 26 27 28 29 30 31
SCLK
Command
SI
3BH
24-bit address(A23:A0)
23 22 21 20 19
7 6 5 4 3 2 1
0
MSB
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
Dummy Byte
SI
6 4 2 0 6 4 2
Data Out1
SO
0 6 4 2 0 6 4 2
Data Out2
7 5 3 1 7 5 3
MSB
MSB
Data Out3
0
6
Data Out4
1 7 5 3 1 7 5 3
MSB
MSB
1
7
6.9. Quad Output Fast Read (6BH)
The Quad Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit
being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle
from IO3, IO2, IO1 and IO0. The command sequence is shown in Figure 10. The first byte addressed can be at
any location. The address is automatically incremented to the next address after each byte of data is shifted out.
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XT25F32B-S
3.3V QUAD IO Serial Flash
Figure 10. Quad Output Fast Read Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 10 11
24 25 26 27 28 29 30 31
SCLK
Command
SI(IO0)
24-bit address(A23:A0)
6BH
23 22 21 20 19
7 6 5 4 3 2 1
0
MSB
High-Z
SO(IO1)
High-Z
WP#(IO2)
High-Z
HOLD#(IO3)
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
Dummy Byte
SI(IO0)
4 0 4 0 4 0 4
0 4 0 4 0 4 0 4
0
4
SO(IO1)
5 1 5 1 5 1 5
1 5 1 5 1 5 1 5
1
5
WP#(IO2)
6 2 6 2 6 2 6
2 6 2 6 2 6 2 6
2
6
7 3 7 3 7 3 7
3 7 3 7 3 7 3 7
3
7
HOLD#(IO3)
Byte1 Byte2 Byte3 Byte4 Byte5 Byte6 Byte7 Byte8
6.10. Dual I/O Fast Read (BBH)
The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the capability
to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte 2-bit per clock by SI and SO, each bit
being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle
from SI and SO. The command sequence is shown in Figure 11. The first byte addressed can be at any location.
The address is automatically incremented to the next address after each byte of data is shifted out.
Dual I/O Fast Read with “Continuous Read Mode”
The Dual I/O Fast Read command can further reduce command overhead through setting the “Continuous
Read Mode” bits (M7- 0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5- 4)
=(1, 0), then the next Dual I/O Fast Read command (after CS# is raised and then lowered) does not require the
BBH command code. The command sequence is shown in figure 11a. If the “Continuous Read Mode” bits (M5- 4)
do not equal (1, 0), the next command requires the first BBH command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M5- 4) before issuing normal command.
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3.3V QUAD IO Serial Flash
Figure 11. Dual I/O Fast Read Sequence Diagram (M5-4≠(1, 0))
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
SI(IO0)
6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0
BBH
SO(IO1)
7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1
A23-16
A15-8
A7-0
M7-0
CS#
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
SI(IO0)
6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6
SO(IO1)
7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
Byte1
Byte5
Byte4
Byte3
Byte2
Byte6
Figure 11a. Dual I/O Fast Read Sequence Diagram (M5-4= (1, 0))
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK
SI(IO0)
6 4 2 0 6 4 2
0 6 4 2 0 6 4 2
0
SO(IO1)
7 5 3 1 7 5 3
1 7 5 3 1 7 5 3
1
A23-16
A15-8
A7-0
M7-0
CS#
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK
SI(IO0)
6 4 2 0 6 4 2
0 6 4 2 0 6 4 2
0 6
SO(IO1)
7 5 3 1 7 5 3
1 7 5 3 1 7 5 3
1 7
Byte1
Rev 1.2
Byte2
Byte3
March/30/2020
Byte4
Page 26
XT25F32B-S
3.3V QUAD IO Serial Flash
6.11. Quad I/O Fast Read (EBH)
The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to
input the 3-byte address (A23-0) and a “Continuous Read Mode” byte and 4-dummy clock 4-bit per clock by IO0,
IO1, IO3, IO4, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted
out 4-bit per clock cycle from IO0, IO1, IO2, IO3. The command sequence is shown in Figure 12. The first byte
addressed can be at any location. The address is automatically incremented to the next address after each byte
of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to enable for the Quad I/O
Fast read command.
Quad I/O Fast Read with “Continuous Read Mode”
The Quad I/O Fast Read command can further reduce command overhead through setting the “Continuous
Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5- 4) =(1,
0), then the next Quad I/O Fast Read command (after CS# is raised and then lowered) does not require the EBH
command code. The command sequence is shown in Figure 12a. If the “Continuous Read Mode” (M5- 4) do not
equal (1, 0), the next command requires the first EBH command code, thus returning to normal operation. A
“Continuous Read Mode” Reset command can be used to reset (M5- 4) before issuing normal command.
Figure 12. Quad I/O Fast Read Sequence Diagram (M5-4≠(1, 0))
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
SI(IO0)
4 0 4 0 4 0 4
0
4 0 4
0
4
SO(IO1)
5 1 5 1 5 1 5
1
5 1 5
1
5
WP#(IO2)
6 2 6 2 6 2 6
2
6 2 6
2
6
HOLD#(IO3)
7 3 7 3 7 3 7
3
7 3 7
3
7
EBH
A23-16 A15-8 A7-0 M7-0
Byte1 Byte2
Dummy
Figure 12a. Quad I/O Fast Read Sequence Diagram (M5-4= (1, 0))
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK
SI(IO0)
4 0 4 0 4 0 4
0
4 0 4
0
4
SO(IO1)
5 1 5 1 5 1 5
1
5 1 5
1
5
WP#(IO2)
6 2 6 2 6 2 6
2
6 2 6
2
6
7 3 7 3 7 3 7
3
7 3 7
3
7
HOLD#(IO3)
A23-16 A15-8 A7-0 M7-0
Rev 1.2
March/30/2020
Dummy
Byte1 Byte2
Page 27
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3.3V QUAD IO Serial Flash
Quad I/O Fast Read with ““8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Quad I/O Fast Read command can be used to access a specific portion within a page by issuing “Set
Burst with Wrap” (77H) commands prior to EBH. The “Set Burst with Wrap” (77H) command can either enable
or disable the “Wrap Around” feature for the following EBH commands. When “Wrap Around” is enabled, the
data being accessed can be limited to either an 8/16/32/64-byte section of a 256-byte page. The output data
starts at the initial address specified in the command, once it reaches the ending boundary of the 8/16/32/64byte section, the output will wrap around the beginning boundary automatically until CS# is pulled high to terminate the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill
the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands.
The “Set Burst with Wrap” command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable or
disable the “Wrap Around” operation while W6-W5 is used to specify the length of the wrap around section
within a page.
Quad I/O Fast Read (EBH) in QPI mode
The Quad I/O Fast Read command is also supported in QPI mode. See Figure12b. In QPI mode, the number
of dummy clocks is configured by the “Set Read Parameters (C0H)” command to accommodate a wide range
application with different needs for either maximum Fast Read frequency or minimum data access latency. Depending on the Read Parameter Bits P[5:4] setting, the number of dummy clocks can be configured as either
4/6/8. When the dummy cycle is configured to 4, addr*0+ input must be 0. In QPI mode, the “Continuous Read
Mode” bits M7-M0 are also considered as dummy clocks. “Continuous Read Mode” feature is also available in
QPI mode for Quad I/O Fast Read command. “Wrap Around” feature is not available in QPI mode for Quad I/O
Fast Read command. To perform a read operation with fixed data length wrap around in QPI mode, a dedicated
“Burst Read with Wrap” (0CH) command must be used.
Figure12b. Quad I/O Fast Read Sequence Diagram (M5-4= (1, 0) QPI)
CS#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCLK
EBH
SI(IO0)
0
1
4
0
4
0
4
0
4
0
4
0
4
0
4
0
SO(IO1)
1
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
WP#(IO2)
1
0
6
2
6
2
6
2
6
2
6
2
6
2
6
2
HOLD#(IO3)
1
1
7
3
7
3
7
3
7
3
7
3
7
3
7
3
A23-16
A15-8
A7-0
M7~M0 *
dummy*
Byte1
Byte2
Byte3
*Set Read Parameters Command (C0H) can set the number of dummy cycles
Rev 1.2
March/30/2020
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3.3V QUAD IO Serial Flash
6.12. Quad I/O Word Fast Read (E7H)
The Quad I/O Word Fast Read command is similar to the Quad I/O Fast Read command except that the lowest address bit (A0) must equal 0 and only 2-dummy clock. The command sequence is shown in followed
Figure 13. The first byte addressed can be at any location. The address is automatically incremented to the next
higher address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be
set to enable for the Quad I/O Word Fast read command.
Quad I/O Word Fast Read with “Continuous Read Mode”
The Quad I/O Word Fast Read command can further reduce command overhead through setting the “Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits
(M5- 4) =(1, 0), then the next Quad I/O Word Fast Read command (after CS# is raised and then lowered) does
not require the E7H command code. The command sequence is shown in followed Figure 13a. If the “Continuous Read Mode” bits (M5- 4) do not equal (1, 0), the next command requires the first E7H command code, thus
returning to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M7-0) before
issuing normal command.
Figure 13. Quad I/O Word Fast Read Sequence Diagram (M5-4≠(1, 0))
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
SI(IO0)
4 0 4 0 4 0 4 0
4 0 4 0 4 0
4
SO(IO1)
5 1 5 1 5 1 5 1
5 1 5 1 5 1
5
WP#(IO2)
6 2 6 2 6 2 6 2
6 2 6 2 6 2
6
7 3 7 3 7 3 7 3
7 3 7 3 7 3
7
E7H
HOLD#(IO3)
A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Byte3
Figure13a. Quad I/O Word Fast Read Sequence Diagram (M5-4= (1, 0))
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK
SI(IO0)
4 0 4 0 4 0 4 0
4 0 4 0 4 0
4
SO(IO1)
5 1 5 1 5 1 5 1
5 1 5 1 5 1
5
WP#(IO2)
6 2 6 2 6 2 6 2
6 2 6 2 6 2
6
HOLD#(IO3)
7 3 7 3 7 3 7 3
7 3 7 3 7 3
7
A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte1 Byte2
Rev 1.2
March/30/2020
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XT25F32B-S
3.3V QUAD IO Serial Flash
Quad I/O Word Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Quad I/O Word Fast Read command can be used to access a specific portion within a page by issuing
“Set Burst with Wrap” (77H) commands prior to E7H. The “Set Burst with Wrap” (77H) command can either enable or disable the “Wrap Around” feature for the following E7H commands. When “Wrap Around” is enabled,
the data being accessed can be limited to either an 8/16/32/64-byte section of a 256-byte page. The output data
starts at the initial address specified in the command, once it reaches the ending boundary of the 8/16/32/64byte section, the output will wrap around the beginning boundary automatically until CS# is pulled high to terminate the command. The Burst with Wrap feature allows applications that use cache to quickly fetch a critical
address and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. The “Set Burst with Wrap” command allows three “Wrap Bits” W6-W4 to be set. The W4
bit is used to enable or disable the “Wrap Around” operation while W6-W5 is used to specify the length of the
wrap around section within a page.
6.13. Set Burst with Wrap (77H)
The Set Burst with Wrap command is used in conjunction with “Quad I/O Fast Read” and “Quad I/O Word
Fast Read” command to access a fixed length of 8/16/32/64-byte section within a 256-byte page, in standard SPI
mode. The Set Burst with Wrap command sequence: CS# goes low Send Set Burst with Wrap command
Send 24 dummy bits Send 8 bits “Wrap bits”CS# goes high
W6,W5
W4=0
W4=1(default)
Wrap Around
Wrap Length
Wrap Around
Wrap Length
0,0
Yes
8-byte
No
N/A
0,1
Yes
16-byte
No
N/A
1,0
Yes
32-byte
No
N/A
1,1
Yes
64-byte
No
N/A
If the W6-W4 bits are set by the Set Burst with Wrap command, all the following “Quad I/O Fast Read” and
“Quad I/O Word Fast Read” command will use the W6-W4 setting to access the 8/16/32/64-byte section within
any page. To exit the “Wrap Around” function and return to normal read operation, another Set Burst with
Wrap command should be issued to set W4=1. In QPI mode, the “Burst Read with Wrap (0CH)” command should
be used to perform the Read Operation with “Wrap Around” feature. The Wrap Length set by W5-W6 in Standard SPI mode is still valid in QPI mode and can also be re-configured by “Set Read Parameters (C0H) command.
Figure 14. Set Burst with Wrap Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SCLK
Command
SI(IO0)
77H
X X X X X X 4 X
SO(IO1)
X X X X X X 5 X
WP#(IO2)
X X X X X X 6 X
HOLD#(IO3)
X X X X X X X X
W6-W4
Rev 1.2
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3.3V QUAD IO Serial Flash
6.14. Page Program (PP) (02H)
The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command.
The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three address bytes and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all
transmitted data that goes beyond the end of the current page are programmed from the start address of the
same page (from the address whose 8 least significant bits (A7-A0) are all zero). CS# must be driven low for the
entire duration of the sequence. The Page Program command sequence: CS# goes low sending Page Program
command 3-byte address on SI at least 1 byte data on SI CS# goes high. The command sequence is shown
in Figure15. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256
data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are
sent to device, they are correctly programmed at the requested addresses without having any effects on the
other bytes of the same page. CS# must be driven high after the eighth bit of the last data byte has been
latched in; otherwise the Page Program (PP) command is not executed.
As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While
the Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is
completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Page Program (PP) command applied to a page which is protected by the Block Protect (BP4, BP3, BP2,
BP1, BP0) is not executed.
Figure 15. Page Program Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 10 11
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
24-bit address(A23:A0)
Command
SI
02H
23 22 21 20 19
Data Byte1
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB
MSB
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
2072
2073
2074
2075
2076
2077
2078
2079
CS#
SCLK
Data Byte2
SI
MSB
Rev 1.2
Data Byte3
Data Byte4
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB
MSB
March/30/2020
Data Byte256
7 6 5 4 3 2 1 0
MSB
Page 31
XT25F32B-S
3.3V QUAD IO Serial Flash
Figure15a. Page Program Sequence Diagram (QPI)
CS#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCLK
02H
SI(IO0)
0
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
SO(IO1)
0
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
WP#(IO2)
0
0
6
2
6
2
6
2
6
2
6
2
6
2
6
2
HOLD#(IO3)
0
0
7
3
7
3
7
3
7
3
7
3
7
3
7
A23-16
A15-8
A7-0
Byte1
Byte2
Byte3
3
Byte4
6.15. Quad Page Program (QPP) (32H)
The Quad Page Program command is for programming the memory using four pins: IO0, IO1, IO2, and IO3.
To use Quad Page Program the Quad enable in status register Bit9 must be set (QE=1). A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page
Program command. The Quad Page Program command is entered by driving CS# Low, followed by the command
code (32H), three address bytes and at least one data byte on IO pins.
The command sequence is shown in Figure 16. If more than 256 bytes are sent to the device, previously
latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the
same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. CS# must be driven high after the
eighth bit of the last data byte has been latched in; otherwise the Quad Page Program command is not executed.
As soon as CS# is driven high, the self-timed Quad Page Program cycle (whose duration is tPP) is initiated.
While the Quad Page Program cycle is in progress, the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Quad Page Program cycle,
and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch
(WEL) bit is reset.
A Quad Page Program command applied to a page which is protected by the Block Protect (BP4, BP3, BP2,
BP1, BP0) will not be executed.
Rev 1.2
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3.3V QUAD IO Serial Flash
Figure 16. Quad Page Program Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 10 11
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
24-bit address(A23:A0)
Command
SI
32H
23 22 21 20 19
7 6 5 4 3 2 1
0 4 0 4 0 4 0 4
0
SO(IO1)
5 1 5 1 5 1 5
1
WP#(IO2)
6 2 6 2 6 2 6
2
HOLD#(IO3)
7 3 7 3 7 3 7
3
MSB
Byte1
Byte2
Byte3
Byte4
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
536
537
538
539
540
541
542
543
CS#
SCLK
SI(IO0)
4 0 4 0 4 0 4
0 4 0 4 0 4 0 4
0 4 0 4 0 4 0 4
0
4 0 4 0 4 0 4
0
SO(IO1)
5 1 5 1 5 1 5
1 5 1 5 1 5 1 5
1 5 1 5 1 5 1 5
1
5 1 5 1 5 1 5
1
WP#(IO2)
6 2 6 2 6 2 6
2 6 2 6 2 6 2 6
2 6 2 6 2 6 2 6
2
6 2 6 2 6 2 6
2
HOLD#(IO3)
7 3 7 3 7 3 7
3 7 3 7 3 7 3 7
3 7 3 7 3 7 3 7
3
7 3 7 3 7 3 7
3
Byte5
Byte6
Byte7
Byte8
Byte9
Byte10 Byte11 Byte12 Byte13 Byte14 Byte15 Byte16
Byte253 Byte254 Byte255 Byte256
6.16. Sector Erase (SE) (20H)
The Sector Erase (SE) command is for erasing the all data of the chosen sector. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE)
command is entered by driving CS# low, followed by the command code, and 3-address byte on SI. Any address
inside the sector is a valid address for the Sector Erase (SE) command. CS# must be driven low for the entire duration of the sequence.
The Sector Erase command sequence: CS# goes low sending Sector Erase command 3-byte address on
SI CS# goes high. The command sequence is shown in Figure 17. CS# must be driven high after the eighth bit
of the last address byte has been latched in; otherwise the Sector Erase (SE) command is not executed. As soon
as CS# is driven high, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase
cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The
Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some
unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE)
com-mand applied to a sector which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) bit (see Table1.0&1.1) will not be executed.
Note: Power disruption during erase operation will cause incomplete erase, thus recommend to perform a
re-erase once power resume.
Rev 1.2
March/30/2020
Page 33
XT25F32B-S
3.3V QUAD IO Serial Flash
Figure 17. Sector Erase Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 10 11
24 25 26 27 28 29 30 31
SCLK
Command
SI
24-bit address(A23:A0)
20H
23 22 21 20 19
7 6 5 4 3 2 1
0
MSB
Figure17a. Sector Erase Sequence Diagram (QPI)
CS#
0
1
2
3
4
5
6
7
SCLK
20H
SI(IO0)
0
0
4
0
4
0
4
0
SO(IO1)
1
0
5
1
5
1
5
1
WP#(IO2)
0
0
6
2
6
2
6
2
HOLD#(IO3)
0
0
7
3
7
3
7
A23~A16
A15~A8
3
A7~A0
6.17. 32KB Block Erase (BE) (52H)
The 32KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit. The 32KB Block Erase
(BE) command is entered by driving CS# low, followed by the command code, and three address bytes on SI. Any
address inside the block is a valid address for the 32KB Block Erase (BE) command. CS# must be driven low for
the entire duration of the sequence.
The 32KB Block Erase command sequence: CS# goes low sending 32KB Block Erase command 3-byte
address on SICS# goes high. The command sequence is shown in Figure18. CS# must be driven high after the
eighth bit of the last address byte has been latched in; otherwise the 32KB Block Erase (BE) command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While
the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress
(WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A
32KB Block Erase (BE) command applied to a block which is protected by the Block Protect (BP4, BP3, BP2, BP1,
BP0) bits (see Table1.0 & 1.1) will not be executed.
Note: Power disruption during erase operation will cause incomplete erase, thus recommend to perform a
re-erase once power resume.
Rev 1.2
March/30/2020
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XT25F32B-S
3.3V QUAD IO Serial Flash
Figure 18. 32KB Block Erase Sequence Diagram
CS
0 1 2 3 4 5 6 7 8 9 10 11
24 25 26 27 28 29 30 31
SCLK
Command
SI
24-bit address(A23:A0)
52H
23 22 21 20 19
7 6 5 4 3 2 1
0
MSB
Figure 18a. 32KB Block Erase Sequence Diagram (QPI)
CS#
0
1
2
3
4
5
6
7
SCLK
52H
SI(IO0)
1
0
4
0
4
0
4
0
SO(IO1)
0
1
5
1
5
1
5
1
WP#(IO2)
1
0
6
2
6
2
6
2
HOLD#(IO3)
0
0
7
3
7
3
7
A23~A16
A15~A8
3
A7~A0
6.18. 64KB Block Erase (BE) (D8H)
The 64KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase
(BE) command is entered by driving CS# low, followed by the command code, and three address bytes on SI. Any
address inside the block is a valid address for the 64KB Block Erase (BE) command. CS# must be driven low for
the entire duration of the sequence.
The 64KB Block Erase command sequence: CS# goes low sending 64KB Block Erase command 3-byte
address on SICS# goes high. The command sequence is shown in Figure 19. CS# must be driven high after the
eighth bit of the last address byte has been latched in; otherwise the 64KB Block Erase (BE) command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While
the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress
(WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A
64KB Block Erase (BE) command applied to a block which is protected by the Block Protect (BP4, BP3, BP2, BP1,
BP0) bits (see Table1.0 & 1.1) will not be executed.
Note: Power disruption during erase operation will cause incomplete erase, thus recommend to perform a
re-erase once power resume.
Rev 1.2
March/30/2020
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XT25F32B-S
3.3V QUAD IO Serial Flash
Figure 19. 64KB Block Erase Sequence Diagram
CS
0 1 2 3 4 5 6 7 8 9 10 11
24 25 26 27 28 29 30 31
SCLK
Command
SI
24-bit address(A23:A0)
D8H
23 22 21 20 19
7 6 5 4 3 2 1
0
MSB
Figure19a. 64KB Block Erase Sequence Diagram (QPI)
CS#
0
1
2
3
4
5
6
7
SCLK
D8H
SI(IO0)
1
0
4
0
4
0
4
0
SO(IO1)
0
0
5
1
5
1
5
1
WP#(IO2)
1
0
6
2
6
2
6
2
HOLD#(IO3)
1
1
7
3
7
3
7
A23~A16
A15~A8
3
A7~A0
6.19. Chip Erase (CE) (60/C7H)
The Chip Erase (CE) command is for erasing the all data of the chip. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit .The Chip Erase (CE) command is entered
by driving CS# Low, followed by the command code on Serial Data Input (SI). CS# must be driven Low for the entire duration of the sequence.
The Chip Erase command sequence: CS# goes low sending Chip Erase commandCS# goes high. The
command sequence is shown in Figure 20. CS# must be driven high after the eighth bit of the command code
has been latch in, otherwise the Chip Erase command is not executed. As soon as CS# is driven high, the selftimed Chip Erase cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status
Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Chip Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle
is completed, the Write Enable Latch (WEL) bit is reset. The Chip Erase (CE) command is executed if the Block
Protect (BP2, BP1, BP0) bits are all 0. The Chip Erase (CE) command is ignored if one or more sectors are protected.
Note: Power disruption during erase operation will cause incomplete erase and data corruption, thus recommend to perform a re-erase once power resume.
Rev 1.2
March/30/2020
Page 36
3.3V QUAD IO Serial Flash
XT25F32B-S
Figure 20. Chip Erase Sequence Diagram
CS#
0 1 2 3 4 5 6 7
SCLK
Command
SI
60H or C7H
Figure20a. Chip Erase Sequence Diagram (QPI)
CS#
0
1
SCLK
C7H
SI(IO0)
0
1
SO(IO1)
0
1
WP#(IO2)
HOLD#(IO3)
1
1
0
1
CS#
0
1
SCLK
60H
SI(IO0)
0
0
SO(IO1)
1
0
WP#(IO2)
1
0
HOLD#(IO3)
Rev 1.2
0
0
March/30/2020
Page 37
XT25F32B-S
3.3V QUAD IO Serial Flash
6.20. Deep Power-Down (DP) (B9H)
Executing the Deep Power-Down (DP) command is the only way to put the device in the lowest consumption mode (the Deep Power-Down Mode). It can also be used as an extra software protection mechanism, while
the device is not in active use, since in this mode, the device ignores all Write, Program and Erase commands.
Driving CS# high deselects the device, and puts the device in the Standby Mode (if there is no internal cycle currently in progress). But this mode is not the Deep Power-Down Mode. The Deep Power-Down Mode can only be
entered by executing the Deep Power-Down (DP) command. Once the device has entered the Deep PowerDown Mode, all commands are ignored except the Release from Deep Power-Down and Read Device ID (RDI)
command. This releases the device from this mode. The Release from Deep Power-Down and Read Device ID
(RDI) command also allows the Device ID of the device to be output on SO.
The Deep Power-Down Mode automatically stops at Power-Down, and the device always Power-Up in the
Standby Mode. The Deep Power-Down (DP) command is entered by driving CS# low, followed by the command
code on SI. CS# must be driven low for the entire duration of the sequence.
The Deep Power-Down command sequence: CS# goes lowsending Deep Power-Down commandCS#
goes high. The command sequence is shown in Figure 21. CS# must be driven high after the eighth bit of the
command code has been latched in; otherwise the Deep Power-Down (DP) command is not executed. As soon
as CS# is driven high, it requires a delay of tDP before the supply current is reduced to ICC2 and the Deep PowerDown Mode is entered. Any Deep Power-Down (DP) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Figure 21. Deep Power-Down Sequence Diagram
CS#
tDP
0 1 2 3 4 5 6 7
SCLK
Stand-by mode
Command
SI
Deep Power-down mode
B9H
Figure 21a. Deep Power-Down Sequence Diagram (QPI)
tPD
CS#
0
1
SCLK
B9H
SI(IO0)
1
1
SO(IO1)
1
0
WP#(IO2)
0
0
1
1
HOLD#(IO3)
Standby Mode
Rev 1.2
March/30/2020
Deep Power Down Mode
Page 38
XT25F32B-S
3.3V QUAD IO Serial Flash
6.21. Release from Deep Power-Down and Read Device ID (RDI) (ABH)
The Release from Power-Down and Read/Device ID command is a multi-purpose command. It can be used
to release the device from the Power-Down state or obtain the devices electronic identification (ID) number.
To release the device from the Power-Down state, the command is issued by driving the CS# pin low, shifting the instruction code “ABH” and driving CS# high as shown in Figure22. Release from Power-Down will take
the time duration of tRES1 (See AC Characteristics) before the device will resume normal operation and other
command are accepted. The CS# pin must remain high during the tRES1 time duration.
When used only to obtain the Device ID while not in the Power-Down state, the command is initiated by
driving the CS# pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The Device ID bits
are then shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure22b. The
Device ID value for the device is listed in Manufacturer and Device Identification table. The Device ID can be
read continuously. The command is completed by driving CS# high.
When used to release the device from the Power-Down state and obtain the Device ID, the command is the
same as previously described, and shown in Figure 22b, except that after CS# is driven high it must remain high
for a time duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal operation and other command will be accepted. If the Release from Power-Down/Device ID command is issued
while an Erase, Program or Write cycle is in process (when WIP equal 1) the command is ignored and will not
affects on the current cycle.
Figure 22. Release Power-Down Sequence Diagram
CS
tRES1
0 1 2 3 4 5 6 7
SCLK
Command
SI
ABH
Deep Power-down mode
Stand-by mode
Figure 22a. Release Power-Down Sequence Diagram (QPI)
CS#
tRES1
0
1
SCLK
ABH
SI(IO0)
SO(IO1)
WP#(IO2)
HOLD#(IO3)
0
1
0
1
1
1
0
1
Deep Power Down Mode
Rev 1.2
March/30/2020
Standby Mode
Page 39
XT25F32B-S
3.3V QUAD IO Serial Flash
Figure 22b. Release Power-Down/Read Device ID Sequence Diagram
CS
0 1 2 3 4 5 6 7 8 9 10 11
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
SCLK
Command
SI
tRES2
3 Dummy Bytes
ABH
23 22 21 20 19
7 6 5 4 3 2 1 0
MSB
Device ID
High-Z
SO
MSB
7 6 5 4 3 2 1 0
Stand-by Mode
Figure 22c. Release Power-Down/Read Device ID Sequence Diagram (QPI)
CS#
tRES2
0
1
2
3
4
5
6
7
8
9
SCLK
ABH
SI(IO0)
0
1
4
0
4
0
4
0
4
0
SO(IO1)
1
1
5
1
5
1
5
1
5
1
WP#(IO2)
0
0
6
2
6
2
6
2
6
2
HOLD#(IO3)
1
1
7
3
7
3
7
3
7
3
Deep Power Down Mode
dummy
dummy
dummy*
Standby Mode
Device ID
*Set Read Parameters Command (C0H) can set the number of dummy cycles
Rev 1.2
March/30/2020
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XT25F32B-S
3.3V QUAD IO Serial Flash
6.22. Read Manufacture ID/ Device ID (REMS) (90H)
The Read Manufacturer/Device ID command is an alternative to the Release from Power-Down / Device ID
command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID.
The command is initiated by driving the CS# pin low and shifting the command code “90H” followed by a
24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the
falling edge of SCLK with most significant bit (MSB) first is shown in Figure 23. If the 24-bit address is initially set
to 000001H, the Device ID will be read first. In QPI mode the dummy cycles can be configured by C0H command.
When the dummy cycle is configured to 4, addr[0] input must be 0.
Figure 23. Read Manufacture ID/ Device ID Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 10 11
24 25 26 27 28 29 30 31
SCLK
Command
SI
24-bit address(A23:A0)
90H
23 22 21 20 19
7 6 5 4 3 2 1 0
MSB
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
SI
Manufacturer ID
SO
Manufacturer ID
Device ID
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB
MSB
MSB
Figure 23a. Read Manufacture ID/ Device ID Sequence Diagram (QPI)
CS#
0
1
2
3
4
5
6
7
8
9
10
11
SCLK
90H
SI(IO0)
1
0
4
0
4
0
4
0
4
0
4
0
SO(IO1)
0
0
5
1
5
1
5
1
5
1
5
1
WP#(IO2)
0
0
6
2
6
2
6
2
6
2
6
2
HOLD#(IO3)
1
0
7
3
7
3
7
3
7
3
7
3
dummy
dummy
dummy*
MID
Device ID
*Set Read Parameters Command (C0H) can set the number of dummy cycles
Rev 1.2
March/30/2020
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XT25F32B-S
3.3V QUAD IO Serial Flash
6.23. Read Manufacture ID/ Device ID Dual I/O (92H)
The Read Manufacturer/Device ID Dual I/O command is an alternative to the Release from Power-Down /
Device ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by dual
I/O.
The command is initiated by driving the CS# pin low and shifting the command code “92H” followed by a
24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the
falling edge of SCLK with most significant bit (MSB) first as shown in Figure 24 If the 24-bit address is initially set
to 000001H, the Device ID will be read first.
Figure 24. Read Manufacture ID/ Device ID Dual I/O Sequence Diagram
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
SI(IO0)
92H
SO(IO1)
6 4 2 0 6 4 2
0 6 4 2 0 6 4 2
0
7 5 3 1 7 5 3
1 7 5 3 1 7 5 3
1
A23-16
A15-8
A7-0
M7-0
CS
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
SI(IO0)
6 4 2 0 6 4 2
0 6 4 2 0 6 4 2
0 6 4 2 0 6 4 2
0 6
SO(IO1)
7 5 3 1 7 5 3
1 7 5 3 1 7 5 3
1 7 5 3 1 7 5 3
1 7
MFR ID
Rev 1.2
Device ID
MFR ID
(Repeat)
Device ID
(Repeat)
March/30/2020
MFR ID
(Repeat)
Device ID
(Repeat)
Page 42
XT25F32B-S
3.3V QUAD IO Serial Flash
6.24. Read Manufacture ID/ Device ID Quad I/O (94H)
The Read Manufacturer/Device ID Quad I/O command is an alternative to the Release from Power-Down /
Device ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by quad
I/O. The command is initiated by driving the CS# pin low and shifting the command code “94H” followed by a
24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the
falling edge of SCLK with most significant bit (MSB) first is shown in Figure 25. If the 24-bit address is initially set
to 000001H, the Device ID will be read first.
Figure 25. Read Manufacture ID/ Device ID Quad I/O Sequence Diagram
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK
Command
SI(IO0)
4 0 4 0 4 0 4 0
4 0 4 0 4 0 4 0 4 0 4 0
SO(IO1)
5 1 5 1 5 1 5 1
5 1 5 1 5 1 5 1 5 1 5 1
WP#(IO2)
6 2 6 2 6 2 6 2
6 2 6 2 6 2 6 2 6 2 6 2
7 3 7 3 7 3 7 3
7 3 7 3 7 3 7 3 7 3 7 3
94H
HOLD#(IO3)
A23-16 A15-8 A7-0 M7-0
Dummy
MID
DID
MID
DID
MID
DID
6.25. Read Identification (RDID) (9FH)
The Read Identification (RDID) command allows the 8-bit manufacturer identification to be read, followed
by two bytes of device identification. The device identification indicates the memory type in the first byte, and
the memory capacity of the device in the second byte. Any Read Identification (RDID) command while an Erase
or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) command should not be issued while the device is in Deep Power-Down Mode.
The device is first selected by driving CS# to low. Then, the 8-bit command code for the command is shifted
in. This is followed by the 24-bit device identification, stored in the memory, being shifted out on Serial Data
Output, each bit being shifted out during the falling edge of Serial Clock. The command sequence is shown in
Figure26. The Read Identification (RDID) command is terminated by driving CS# to high at any time during data
output. When CS# is driven high, the device is put in the Standby Mode. Once in the Standby Mode, the device
waits to be selected, so that it can receive, decode and execute commands.
Figure 26. Read Identification ID Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK
Command
SI
9FH
Manufacturer ID
SO
High-Z
7 6 5 4 3 2 1
Memory Type
JDID15-JDID8
0 7 6 5 4 3 2 1
Capacity
JDID7-JDID0
0 7 6 5 4 3 2 1
0
High-Z
MSB
Rev 1.2
March/30/2020
Page 43
XT25F32B-S
3.3V QUAD IO Serial Flash
6.26. Erase Security Registers (44H)
The XT25F32B-S provides four 256-byte Security Registers which only erased all at once but able to program individually. These registers may be used by the system manufacturers to store security and other important information separately from the main memory array.
The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit.
The Erase Security Registers command sequence: CS# goes lowsending Erase Security Registers CommandCS# goes high. The command sequence is shown in Figure 29. CS# must be driven high after the eighth
bit of the command code has been latched in, otherwise the Erase Security Registers command is not executed.
As soon as CS# is driven high, the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated.
While the Erase Security Registers cycle is in progress, the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Erase Security Registers
cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable
Latch (WEL) bit is reset. The Security Registers Lock Bit (LB) in the Status Register can be used to OTP protect the
security registers. Once the LB bit is set to 1, the Security Registers will be permanently locked; the Erase Security Registers command will be ignored.
Address
A23-A16
A15-A10
A9-A0
Security Registers
00000000
000000
Don’t Care
Figure 29. Erase Security Registers command Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 10 11
24 25 26 27 28 29 30 31
SCLK
Command
SI
44H
24-bit address(A23:A0)
23 22 21 20 19
7 6 5 4 3 2 1
0
MSB
6.27. Program Security Registers (42H)
The Program Security Registers command is similar to the Page Program command. It allows from 1 to 256
bytes Security Registers data to be programmed. A Write Enable (WREN) command must previously have been
executed to set the Write Enable Latch (WEL) bit before sending the Program Security Registers command. The
Program Security Registers command is entered by driving CS# Low, followed by the command code (42H),
three address bytes and at least one data byte on SI. As soon as CS# is driven high, the self-timed Program Security Registers cycle (whose duration is tPP) is initiated. While the Program Security Registers cycle is in progress,
the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP)
bit is 1 during the self-timed Program Security Registers cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
If the Security Registers Lock Bit (LB) is set to 1, the Security Registers will be permanently locked. Program
Security Registers command will be ignored.
Address
Rev 1.2
A23-A16
A15-A8
Security Registers 0
00H
00H
Byte Address
Security Registers 1
00H
01H
Byte Address
Security Registers 2
00H
02H
Byte Address
Security Registers 3
00H
03H
Byte Address
March/30/2020
A7-A0
Page 44
XT25F32B-S
3.3V QUAD IO Serial Flash
Figure 30. Program Security Registers command Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 10 11
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
24-bit address(A23:A0)
Command
SI
42H
23 22 21 20 19
Data Byte1
7 6 5 4 3 2 1
0 7 6 5 4 3 2 1
MSB
0
MSB
2072
2073
2074
2075
2076
2077
2078
2079
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
SCLK
Data Byte2
SI
Data Byte3
7 6 5 4 3 2 1
MSB
Data Byte4
0 7 6 5 4 3 2 1
0 7 6 5 4 3 2 1
MSB
MSB
Data Byte256
0
7 6 5 4 3 2 1
0
MSB
6.28. Read Security Registers (48H)
The Read Security Registers command is similar to Fast Read command. The command is followed by a 3byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the
memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC, during
the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next address after each byte of data is shifted out. Once the A9-A0 address reaches the last byte of the
register (Byte 3FFH), it will reset to 000H, the command is completed by driving CS# high.
Address
A23-A16
A15-A10
A9-A0
Security Registers
00000000
000000
Address
Figure 31. Read Security Registers command Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 10 11
24 25 26 27 28 29 30 31
SCLK
Command
SI
48H
24-bit address(A23:A0)
23 22 21 20 19
7 6 5 4 3 2 1
0
MSB
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
Dummy Byte
SI
7 6 5 4 3 2 1
0
Data Out1
SO
7 6 5 4 3 2 1
Data Out2
0 7 6 5 4 3 2 1
0
MSB
MSB
Rev 1.2
Data Out3
March/30/2020
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XT25F32B-S
3.3V QUAD IO Serial Flash
6.29. Set Read Parameters (C0H)
In QPI mode the “Set Read Parameters (C0H)” command can be used to configure the number of dummy
clocks for “Fast Read (0BH)”, “Quad I/O Fast Read (EBH)” and “Burst Read with Wrap (0CH)” command, and to
configure the number of bytes of “Wrap Length” for the “Burst Read with Wrap (0CH)” command. The “Wrap
Length” is set by W5-6 bit in the “Set Burst with Wrap (77H)” command. This setting will remain unchanged
when the device is switched from Standard SPI mode to QPI mode.
P5-P4
Dummy Clocks
Maximum Read Freq.
P1-P0
Wrap Length
00
4
48MHz
00
8-byte
01
4
48MHz
01
16-byte
10
6
48MHz
10
32-byte
11
8
48MHz
11
64-byte
Figure32. Set Read Parameters command Sequence Diagram
CS#
0
1
2
3
SCLK
C0H
SI(IO0)
0
0
P4
P0
SO(IO1)
0
0
P5
P1
WP#(IO2)
1
0
P6
P2
HOLD#(IO3)
1
0
P7
P3
Read
Parameter
Rev 1.2
March/30/2020
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XT25F32B-S
3.3V QUAD IO Serial Flash
6.30. Burst Read with Wrap (0CH)
The “Burst Read with Wrap (0CH)” command provides an alternative way to perform the read operation
with “Wrap Around” in QPI mode. This command is similar to the “Fast Read (0BH)” command in QPI mode, except the addressing of the read operation will “Wrap Around” to the beginning boundary of the “Wrap Around”
once the ending boundary is reached. The “Wrap Length” and the number of dummy clocks can be configured
by the “Set Read Parameters (C0H)” command. When the dummy cycle is configured to 4, addr[0] input must be
0.
Figure 33. Burst Read with Wrap command Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCLK
0CH
SI(IO0)
0
0
4
0
4
0
4
0
4
0
4
0
4
0
SO(IO1)
0
0
5
1
5
1
5
1
5
1
5
1
5
1
WP#(IO2)
0
1
6
2
6
2
6
2
6
2
6
2
6
2
HOLD#(IO3)
0
1
7
3
7
3
7
3
7
3
7
3
7
3
A23-16
A15-8
A7-0
dummy*
Byte1
Byte2
Byte3
*Set Read Parameters Command (C0H) can set the number of dummy cycles
6.31. Enable QPI (38H)
The device support both Standard/Dual/Quad SPI and QPI mode. The “Enable QPI (38H)” command can
switch the device from SPI mode to QPI mode. See the command Table 2a for all support QPI commands. In order to switch the device to QPI mode, the Quad Enable (QE) bit in Status Register-1 must be set to 1 first, and
“Enable QPI (38H)” command must be issued. If the QE bit is 0, the “Enable QPI (38H)” command will be ignored
and the device will remain in SPI mode. When the device is switched from SPI mode to QPI mode, the existing
Write Enable Latch and the Wrap Length setting will remain unchanged.
Figure 34. Enable QPI mode command Sequence Diagram
CS
0 1 2 3 4 5 6 7
SCLK
Command
SI
SO
Rev 1.2
38H
High-Z
March/30/2020
Page 47
3.3V QUAD IO Serial Flash
XT25F32B-S
6.32. Continuous Read Mode Reset (CRMR) (FFH)/ Disable QPI (FFH)
The Dual/Quad I/O Fast Read operations, “Continuous Read Mode” bits (M7-0) are implemented to
further reduce command overhead. By setting the (M7-0) to AXH, the next Dual/Quad I/O Fast Read
operations do not require the BBH/EBH/E7H command code.
Because the XT25F32B-S has no hardware reset pin, so if Continuous Read Mode bits are set to “AXH”,
the XT25F32B-S will not recognize any standard SPI commands. So Continuous Read Mode Reset command
will release the Continuous Read Mode from the “AXH” state and allow standard SPI command to be recognized.
The command sequence is show in Figure35.
Figure 35. Continuous Read Mode Reset Sequence Diagram
CS#
Mode Bit Reset for Quad/
Dual I/O
0 1 2 3 4 5 6 7
SCLK
SI(IO0)
FFH
SO(IO1)
Don’t care
WP#(IO2)
Don’t care
HOLD#(IO3)
Don’t care
Disable QPI (FFH)
To exit the QPI mode and return to Standard/Dual/Quad SPI mode, the “Disable QPI (FFH)” command must
be issued. When the device is switched from QPI mode to SPI mode, the existing Write Enable Latch and the
Wrap Length setting will remain unchanged. When the device is in QPI mode, the first FFH command will exit
continuous read mode and the second FFH command will exit QPI mode.
Figure 35a. Disable QPI mode command Sequence Diagram
CS#
0
1
SCLK
FFH
Rev 1.2
SI(IO0)
1
1
SO(IO1)
1
1
WP#(IO2)
WP#(IO2)
1
1
HOLD#(IO3)
HOLD#(IO3)
1
1
March/30/2020
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XT25F32B-S
3.3V QUAD IO Serial Flash
6.33. Enable Reset (66H) and Reset (99H)
If the Reset command is accepted, any on-going internal operation will be terminated and the device will
return to its default power-on state and lose all the current volatile settings, such as Volatile Status Register bits,
Write Enable Latch status (WEL), Read Parameter setting (P7-P0) and Wrap Bit Setting (W6-W4).
The “Reset (99H)” command sequence as follow: CS# goes low Sending Enable Reset command CS#
goes high CS# goes low Sending Reset command CS# goes high. Once the Reset command is accepted
by the device, the device will take approximately tRST_R to reset. During this period, no command will be accepted. Data corruption may happen if there is an on-going internal Erase or Program operation when Reset
command sequence is accepted by the device. It is recommended to check the BUSY bit and the SUS bit in Status Register before issuing the Reset command sequence.
Figure 36. Enable Reset and Reset command Sequence Diagram
CS#
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
SCLK
Command
SI
High-Z
Command
66H
99H
Figure 36a. Enable Reset and Reset command Sequence Diagram (QPI)
CS#
0
1
0
1
SCLK
66H
SI(IO0)
99H
0
SO(IO1)
1
1
WP#(IO2)
1
1
HOLD#(IO3)
Rev 1.2
0
0
1
0
0
0
0
0
1
March/30/2020
1
1
Page 49
XT25F32B-S
3.3V QUAD IO Serial Flash
6.34. Read Serial Flash Discoverable Parameter (5AH)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the
functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These
parameter tables can be interrogated by host system software to enable adjustments needed to accommodate
divergent features from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC
Standard, JESD68 on CFI. SFDP is a standard of JEDEC Standard No.216.
Figure 37. Read Serial Flash Discoverable Parameter command Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 10 11
24 25 26 27 28 29 30 31
SCLK
Command
SI
24-bit address(A23:A0)
5AH
23 22 21 20 19
7 6 5 4 3 2 1
0
MSB
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
Dummy Byte
SI
7 6 5 4 3 2 1
0
Data Out1
SO
Data Out2
7 6 5 4 3 2 1
Data Out3
0 7 6 5 4 3 2 1
0
MSB
MSB
Figure 37a. Read Serial Flash Discoverable Parameter command Sequence Diagram (QPI)
CS#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCLK
5AH
SI(IO0)
1
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
SO(IO1)
0
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
WP#(IO2)
1
0
6
2
6
2
6
2
6
2
6
2
6
2
6
2
HOLD#(IO3)
0
1
7
3
7
3
7
3
7
3
7
3
7
3
7
3
A23-16
A15-8
A7-0
dummy*
Byte1
Byte2
Byte3
*Set Read Parameters Command (C0H) can set the number of dummy cycles
Rev 1.2
March/30/2020
Page 50
XT25F32B-S
3.3V QUAD IO Serial Flash
6.35. Read Unique ID (RUID)
The Read Unique ID command accesses a factory-set read-only 128bit number that is unique to each
XT25F32B-S device. The Unique ID can be used in conjunction with user software methods to help prevent copying or cloning of a system.
The Read Unique ID command sequence: CS# goes low → sending Read Unique ID command →00H →01H
→94H → Dummy byte 128bit Unique ID Out → CS# goes high.
The command sequence is show below.
Figure 37.1. Read Unique ID (RUID) Sequence (Command 5AH)
CS#
0 1 2 3 4 5 6 7 8 9 10 11
24 25 26 27 28 29 30 31
SCLK
Command
SI
24-bit address(A23:A0)
5AH
23 22 21 20 19
7 6 5 4 3 2 1
0
MSB
High-Z
SO
CS#
32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47
160 161 162 163 164 165 166 167
SCLK
Dummy Byte
SI
7 6 5 4 3 2 1
0
128 bit unique serial number
SO
12 12 12 12 12 12 12
7 6 5 4 3 2 1
12
0
7
6
5
4
3
2
1
0
MSB
Rev 1.2
March/30/2020
Page 51
XT25F32B-S
3.3V QUAD IO Serial Flash
Table 3. Signature and Parameter Identification Data Values
Description
SFDP Signature
Comment
Fixed:50444653H
Add(H)
DW Add
(Byte)
(Bit)
Data
Data
00H
07:00
53H
53H
01H
15:08
46H
46H
02H
23:16
44H
44H
03H
31:24
50H
50H
SFDP Minor Revision Number
Start from 00H
04H
07:00
00H
00H
SFDP Major Revision Number
Start from 01H
05H
15:08
01H
01H
Number of Parameters Headers
Start from 00H
06H
23:16
01H
01H
07H
31:24
FFH
FFH
08H
07:00
00H
00H
Contains 0xFFH and can never be
Unused
changed
00H: It indicates a JEDEC specified
ID number (JEDEC)
header
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Start from 0x00H
09H
15:08
00H
00H
Number
Parameter Table Length
Start from 0x01H
0AH
23:16
01H
01H
(in double word)
Parameter table
0BH
31:24
09H
09H
Parameter Table Pointer (PTP)
How many DWORDs in the
0CH
07:00
30H
30H
First address of JEDEC Flash
0DH
15:08
00H
00H
Parameter table
0EH
23:16
00H
00H
0FH
31:24
FFH
FFH
10H
07:00
0BH
0BH
Contains 0xFFH and can never be
Unused
ID Number(XTX Manufacturer ID)
changed
It is indicates XTX manufacturer ID
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Start from 0x00H
11H
15:08
00H
00H
Number
Parameter Table Length
Start from 0x01H
12H
23:16
01H
01H
(in double word)
Parameter table
13H
31:24
03H
03H
14H
07:00
60H
60H
First address of XTX Flash
15H
15:08
00H
00H
Parameter table
16H
23:16
00H
00H
17H
31:24
FFH
FFH
Parameter Table Pointer (PTP)
How many DWORDs in the
Contains 0xFFH and can never be
Unused
Rev 1.2
changed
March/30/2020
Page 52
XT25F32B-S
3.3V QUAD IO Serial Flash
Table 4. Parameter Table (0): JEDEC Flash Parameter Tables
Description
Comment
Add(H)
DW Add
(Byte)
(Bit)
Data
01:00
01b
02
1b
03
0b
Data
00: Reserved; 01: 4KB erase;
10: Reserved;
Block/Sector Erase Size
11: not support 4KB erase
Write Granularity
0: 1Byte, 1: 64Byte or larger
Write Enable Instruction Re-
0: Nonvolatile status
quested for Writing to Volatile
bit 1: Volatile statusbit
Status Registers
(BP status register bit)
0: Use 50H Opcode,
1: Use 06H Opcode,
Write Enable Opcode Select for
Writing to Volatile Status Registers
30H
Note:If target flash status register is
E5H
04
0b
07:05
111b
15:08
20H
16
1b
18:17
00b
19
0b
20
1b
21
1b
22
1b
23
1b
33H
31:24
FFH
37H:34H
31:00
Nonvolatile, then bits 3 and 4
must be set to 00b.
Contains 111b and can never be
Unused
changed
31H
4KB Erase Opcode
(1-1-2) Fast Read
0=Not support, 1=Support
Address Bytes Number used in
00: 3Byte only, 01: 3 or 4Byte,
addressing flash array
Double Transfer Rate (DTR)
10: 4Byte only, 11: Reserved
clocking
(1-2-2) Fast Read
0=Not support, 1=Support
0=Not support, 1=Support
(1-4-4) Fast Read
0=Not support, 1=Support
(1-1-4) Fast Read
0=Not support, 1=Support
32H
Unused
Unused
Flash Memory Density
(1-4-4) Fast Read Number of
0 0000b: Wait states (Dummy
Wait states
(1-4-4) Fast Read Number of
Clocks) not support
Mode Bits
(1-4-4) Fast Read Opcode
000b:Mode Bits not support
(1-1-4) Fast Read Number of
0 0000b: Wait states (Dummy
Wait states
(1-1-4) Fast Read Number of
Clocks) not support
Mode Bits
(1-1-4) Fast Read Opcode
000b:Mode Bits not support
Rev 1.2
04:00
March/30/2020
FFH
00100b
44H
07:05
010b
15:08
EBH
20:16
01000b
3AH
3BH
F1H
003FFFFFH
38H
39H
20H
EBH
08H
23:21
000b
31:24
6BH
6BH
Page 53
XT25F32B-S
3.3V QUAD IO Serial Flash
Description
Comment
(1-1-2) Fast Read Number of
0 0000b: Wait states (Dum-
Wait states
(1-1-2) Fast Read Number
my Clocks) not support
of Mode Bits
(1-1-2) Fast Read Opcode
000b: Mode Bits not support
Add(H)
DW Add
(Byte)
(Bit)
Data
04:00
01000b
3CH
3DH
Data
08H
07:05
000b
15:08
3BH
20:16
00010b
3BH
(1-2-2) Fast Read Number of Wait
states
(1-2-2) Fast Read Number of Mode
3EH
Bits
(1-2-2) Fast Read Opcode
(2-2-2) Fast Read
3FH
0=not support 1=support
Unused
(4-4-4) Fast Read
0=not support 1=support
40H
Unused
42H
23:21
010b
31:24
BBH
00
0b
03:01
111b
04
1b
07:05
111b
BBH
EEH
Unused
43H:41H
31:08
0xFFH
0xFFH
Unused
45H:44H
15:00
0xFFH
0xFFH
20:16
00000b
(2-2-2) Fast Read Number of Wait
0 0000b: Wait states (Dummy
states
(2-2-2) Fast Read Number of Mode
Clocks) not support
Bits
(2-2-2) Fast Read Opcode
000b: Mode Bits not support
46H
Unused
(4-4-4) Fast Read Number of Wait
0 0000b: Wait states (Dummy
states
(4-4-4) Fast Read Number of Mode
Clocks) not support
Bits
(4-4-4) Fast Read Opcode
000b: Mode Bits not support
00H
23:21
000b
47H
31:24
FFH
FFH
49H:48H
15:00
0xFFH
0xFFH
20:16
00000b
4AH
00H
23:21
000b
4BH
31:24
FFH
FFH
4CH
07:00
0CH
0CH
4DH
15:08
20H
20H
4EH
23:16
0FH
0FH
4FH
31:24
52H
52H
50H
07:00
10H
10H
51H
15:08
D8H
D8H
52H
23:16
00H
00H
53H
31:24
FFH
FFH
Sector/block size=2^N bytes
Sector Type 1 Size
0x00b: this sector type don’t exist
Sector Type 1 erase Opcode
Sector/block size=2^N bytes
Sector Type 2 Size
0x00b: this sector type don’t exist
Sector Type 2 erase Opcode
Sector/block size=2^N bytes
Sector Type 3 Size
0x00b: this sector type don’t exist
Sector Type 3 erase Opcode
Sector/block size=2^N bytes
Sector Type 4 Size
0x00b: this sector type don’t exist
Sector Type 4 erase Opcode
Rev 1.2
March/30/2020
Page 54
XT25F32B-S
3.3V QUAD IO Serial Flash
Table 5. Parameter Table (1): XTX Flash Parameter Tables
Description
Comment
Add(H)
DW Add
(Byte)
(Bit)
Data
Data
61H:60H
15:00
3600H
3600H
63H:62H
31:16
2700H
2700H
2000H=2.000V
2700H=2.700V
Vcc Supply Maximum Voltage
3600H=3.600V
1650H=1.650V
2250H=2.250V
Vcc Supply Minimum Voltage
2300H=2.300V
2700H=2.700V
HW Reset# pin
0=not support 1=support
00
0b
HW Hold# pin
0=not support 1=support
01
1b
Deep Power Down Mode
0=not support 1=support
02
1b
SW Reset
0=not support 1=support
03
1b
11:04
99H
12
0b
13
0b
14
1b
15
1b
66H
23:16
FFH
FFH
67H
31:24
64H
64H
0=not support 1=support
00
0b
0=Volatile 1=Nonvolatile
01
0b
09:02
FFH
Should be issue Reset
SW Reset Opcode
Program Suspend/Resume
Enable(66H) before Reset cmd
0=not support 1=support
Erase Suspend/Resume
0=not support 1=support
65H:64H
Unused
Wrap-Around Read mode
0=not support 1=support
Wrap-Around Read mode Opcode
7994H
08H:support 8B wrap-around
read 16H:8B&16B
Wrap-Around Read data length
32H:8B&16B&32B
64H:8B&16B&32B&64B
Individual block lock
Individual block lock bit
(Volatile/Nonvolatile)
Individual block lock Opcode
Individual block lock Volatile
protect bit default protect status
Secured OTP
0=protect 1=unprotect
10
0b
0=not support 1=support
11
0b
Read Lock
0=not support 1=support
12
0b
Permanent Lock
0=not support 1=support
13
1b
Unused
15:14
11b
Unused
31:16
FFFFH
Rev 1.2
March/30/2020
6BH:68H
E3FCH
FFFFH
Page 55
XT25F32B-S
3.3V QUAD IO Serial Flash
7.
ELECTRICAL CHARACTERISTICS
7.1. Power-on Timing
Vcc(max)
Chip Selection is not allowed
Vcc(min)
Reset
State
tVSL
Device is fully
accessible
VWI
tPUW
Time
Table3. Power-Up Timing and Write Inhibit Threshold
Note: At power-down, need to ensure VCC drop to 0.5V before the next power-on in order for the device to
have a proper power-on reset.
Symbol
Parameter
Min
Max
Unit
tVSL
VCC(min) To CS# Low
10
us
tPUW
Time Delay Before Write Instruction
1
-
ms
VWI
Write Inhibit Voltage
1.5
2.5
V
7.2. Initial Delivery State
The device is delivered with the memory array erased: all bits are set to 1(each byte contains FFH).The
Status Register contains 00H (all Status Register bits are 0).
7.3. Data Retention and Endurance
Parameter
Typical
Unit
Data Retention Time
20
Years
Erase/Program Endurance
100K
Cycles
Min
Max
7.4. Latch up Characteristics
Parameter
Input Voltage Respect To VSS On I/O Pins
-1.0V
VCC Current
Rev 1.2
-100mA
March/30/2020
VCC+1.0V
100mA
Page 56
XT25F32B-S
3.3V QUAD IO Serial Flash
7.5. Absolute Maximum Ratings
Parameter
Value
Unit
Ambient Operating Temperature
-40 to 85
℃
Storage Temperature
-65 to 150
℃
Output Short Circuit Current
200
mA
Applied Input/Output Voltage
-0.5 to 4.0
V
-0.5 to 4.0
V
VCC
7.6. Capacitance Measurement Condition
Symbol
Parameter
Min
Typ
Max
Unit
Conditions
CIN
Input Capacitance
6
pF
VIN=0V
COUT
Output Capacitance
8
pF
VOUT=0V
CL
Load Capacitance
30
Input Rise And Fall time
pF
5
ns
Input Pulse Voltage
0.1VCC to 0.8VCC
V
Input Timing Reference Voltage
0.2VCC to 0.7VCC
.8
0.5VCC
V
Output Timing Reference Voltage
V
VCC
Figure38. Input Test Waveform and Measurement Level
Maximum Negative Overshoot Waveform
20ns
20ns
VSS
VSS-2.0V
20ns
Maximum Positive Overshoot Waveform
20ns
VCC+2.0V
VCC
20ns
Rev 1.2
March/30/2020
20ns
Page 57
XT25F32B-S
3.3V QUAD IO Serial Flash
7.7. DC Characteristics
(T=-40℃~85℃,VCC=2.7~3.6V)
Symbol
ILI
Parameter
Input Leakage Current
Test Condition
Min.
Typ
(1)
(1)
Max.
Unit
±2
μA
±2
μA
ILO
Output Leakage Current
ICC1
Standby Current
CS#=VCC
12
40
μA
Deep Power-Down Current
VIN=VCC or VSS
CS#=VCC
VIN=VCC or VSS
0.1
4
μA
15
20
mA
13
18
mA
7
10
mA
ICC2
CLK=0.1VCC/0.9VCC at
108MHz, Q=Open(*1,*2
I/O)
CLK=0.1VCC/0.9VCC at
ICC3
Operating Current(Read)
(2)
80MHz, Q=Open(*1,*2,*4
I/O)
CLK=0.1VCC/0.9VCC at
50MHZ,Q=Open(*1,*2,*4
I/O)
ICC4
Operating Current(PP)
CS#=VCC
30
mA
ICC5
Operating Current(WRSR)
CS#=VCC
30
mA
ICC6
Operating Current(SE)
CS#=VCC
30
mA
ICC7
Operating Current(BE)
CS#=VCC
30
mA
VIL
Input Low Voltage
-0.5
0.2VCC
V
VIH
Input High Voltage
0.7VCC
VCC+0.4
V
VOL
Output Low Voltage
IOL=1.6mA
0.4
V
VOH
Output High Voltage
IOH=-100uA
VCC-0.2
V
Notes:
1. Tested on sample basis and specified through design and characterization data. TA = 25° C, VCC = 3.3V.
2. Pattern 00 FF.
Rev 1.2
March/30/2020
Page 58
XT25F32B-S
3.3V QUAD IO Serial Flash
7.8. AC Characteristics
(T=-40℃~85℃,VCC=2.7~3.6V，CL=30pF)
Symbol
Parameter
fC
Max.
Unit
Serial Clock Frequency For: Fast Read (0BH),
Dual Output(3BH)
108
MHz
fC1
Serial Clock Frequency For: Dual I/O (BBH),
Quad I/O(EBH),Quad Output(6BH)
86
MHz
fC2
Serial Clock Frequency For QPI (0BH, EBH)
72
MHz
fR
Serial Clock Frequency For: Read Data(03H), Read
Device ID(9FH),Read Manufacture ID (90H)
72
MHz
tCLH
Serial Clock High Time
45% PC
ns
tCLL
Serial Clock Low Time
45% PC
ns
tCLCH
Serial Clock Rise Time(Slew Rate)
0.2
V/ns
tCHCL
Serial Clock Fall Time(Slew Rate)
0.2
V/ns
tSLCH
CS# Active Setup Time
5
ns
tCHSH
CS# Active Hold Time
5
ns
tSHCH
CS# Not Active Setup Time
5
ns
tCHSL
CS# Not Active Hold Time
5
ns
tSHSL
CS# High Time (read/write)
20
ns
tSHQZ
Output Disable Time
tCLQX
Output Hold Time
1
ns
tDVCH
Data In Setup Time
2
ns
tCHDX
Data In Hold Time
2
ns
tHLCH
Hold# Low Setup Time(relative to Clock)
5
ns
tHHCH
Hold# High Setup Time(relative to Clock)
5
ns
tCHHL
Hold# High Hold Time(relative to Clock)
5
ns
tCHHH
Hold# Low Hold Time(relative to Clock)
5
ns
tCLQV
Clock Low To Output Valid
tWHSL
Write Protect Setup Time Before CS# Low
20
ns
tSHWL
Write Protect Hold Time After CS# High
100
ns
tDP
CS# High To Deep Power-Down Mode
0.1
µs
tRES1
CS# High To Standby Mode Without Electronic Signature Read
20
µs
tRES2
CS# High To Standby Mode With Electronic Signature
Read
20
µs
tRST_R
CS# High To Next Command After Reset (from read)
20
µs
tRST_P
CS# High To Next Command After Reset (from program)
20
µs
tRST_E
CS# High To Next Command After Reset (from erase)
12
ms
tW
Write Status Register Cycle Time
50
800
ms
tPP
Page Programming Time
0.35
0.7
ms
tSE
Sector Erase Time
70
800
ms
Rev 1.2
Min.
Typ.
6
6.5
March/30/2020
ns
ns
Page 59
XT25F32B-S
3.3V QUAD IO Serial Flash
tBE1
Block Erase Time(32K Bytes)
0.15
1.2
s
tBE2
Block Erase Time(64K Bytes)
0.25
1.6
s
tCE
Chip Erase Time
10
30
s
Note:
1.
2.
3.
Clock high or Clock low must be more than or equal to 45%Pc. Pc=1/fC(MAX)
Maximum Serial Clock Frequencies are measured results picked at the falling edge.
Typical values given for TA=25°C. Value guaranteed by design and/or characterization, are not 100% tested in production.
Rev 1.2
March/30/2020
Page 60
XT25F32B-S
3.3V QUAD IO Serial Flash
Figure 39. Serial Input Timing
tSHSL
CS#
tCHSL
tCHSH
tSLCH
tSHCH
SCLK
tDVCH
SI
tCHCL
tCLCH
tCHDX
MSB
LSB
High-Z
SO
Figure 40. Output Timing
CS#
tCLH
tSHQZ
SCLK
tCLQV
tCLQX
tCLL
tCLQV
tCLQX
LSB
SO
SI
Least significant address bit (LSB) in
Figure 41. Hold Timing
CS#
tCHHL
tHLCH
tHHCH
SCLK
tHLQZ
SO
tCHHH
tHHQX
HOLD#
SI do not care during HOLD operation
NOTE:
Standard bulk shipment is in Tube. Any alternation of packing method (for Tape, Reel and Tray etc.), please advise in
advance.
Rev 1.2
March/30/2020
Page 61
XT25F32B-S
3.3V QUAD IO Serial Flash
8.
ORDERING INFORMATION
The ordering part number is formed by a valid combination of the following
XT
25F 32B
SO I
G
U -S
Company Prefix
XT = XTX
Product Family
25F = 2.7~3.6V Serial Flash Memory
with 4KB Uniform-Sector
Product Density
32B = 32M bit
Product Package
SO = 8-pin SOP8(150mil)
SS = 8-pin SOP8(208mil)
DF = 8-pad DFN8(2x3x0.55mm)
DT = 8-pad DFN8(2x3x0.40mm)
DX = 8-pin DFN8(4x3x0.55mm)
WO = WSON 6x5
Temperature & Moisture Sensitivity Level
I = Industrial Level Temp. (-40℃ to +85℃), MSL3
Green Code
G = Green/Reach Package
Product Carrier
U = Tube; T = Tape & Reel; A = Tray
Internal Version = “S”
Rev 1.2
March/30/2020
Page 62
XT25F32B-S
3.3V QUAD IO Serial Flash
9.
PACKAGE INFORMATION
9.1. Package SOP8 150MIL
e
8
5
12*(2
X)
1200
15*(2
X)
Detail “A”
Θ0.8
1
b
“B”
b
4
Base Metal
A2
A
c
0.813
L
L1
Θ
E1
E
10°
h
Detail “B”
SEATING PLANE
c
A1
D
“A”
Symbol
A
A1
A2
b
c
D
E1
e
E
h
L
L1
θ
Min
1.350
0.100
1.300
0.330
0.190
4.700
3.800
---5.800
0.2500
0.508
0.837
0°
Dimensions in Millimeters
Norm
---------------4.900
3.900
1.270
6.000
0.350
0.635
1.040
----
Max
1.750
0.250
1.500
0.510
0.250
5.000
4.000
---6.200
0.500
0.762
1.243
8°
Note:
1. Coplanarity: 0.1mm
2. Max allowable mold flash is 0.15mm at the package ends. 0.25mm between leads.
3. All dimensions follow JEDEC MS-012 standard.
Rev 1.2
March/30/2020
Page 63
XT25F32B-S
3.3V QUAD IO Serial Flash
E
E1
9.2. Package SOP8 208MIL
0.8
0.8
C
A
L
0.25
e
0°
GAGE PLANE
SEATING PLANE
A2
A1
D
b
Dimensions in Millimeters
Symbol
Min
Norm
Max
A
1.750
1.950
2.160
A1
0.050
0.150
0.250
A2
1.700
1.800
1.910
b
0.350
0.420
0.480
c
0.190
0.20
0.250
D
5.130
5.230
5.330
E
7.700
7.900
8.100
E1
5.180
5.280
5.380
e
1.270 BSC
L
0.500
0.650
0.800
θ
0°
----
8°
Note:
1. JEDEC Outline : N/A
2. Coplanarity: 0.1mm
3. Max allowable mold flash is 0.15mm at the package ends. 0.25mm between leads.
Rev 1.2
March/30/2020
Page 64
XT25F32B-S
3.3V QUAD IO Serial Flash
9.3. Package DFN8 (2x3x0.55) mm
b
e
L
L1
D
h
Pin 1
Corner
1
2
Nd
EXPOSED THERMAL
PAD ZONE
BOTTOM VIEW
c
A1
A
TOP VIEV
h
E
E2
D2
SIDE VIEW
SYMBOL
A
A1
b
c
D
D2
e
Nd
E
E2
L
L1
h
Rev 1.2
MIN
0.50
0
0.18
0.10
1.90
1.50
2.90
0.10
0.30
0.05
0.05
MILLIMETER
NOM
0.55
0.02
0.25
0.15
2.00
1.60
0.50BSC
1.50BSC
3.00
0.20
0.35
0.10
0.15
March/30/2020
MAX
0.60
0.05
0.30
0.20
2.10
1.70
3.10
0.30
0.40
0.15
0.25
Page 65
XT25F32B-S
3.3V QUAD IO Serial Flash
9.4. Package DFN8 (2x3x0.40) mm
D
L1
e
b
2
L
8
E
E2
D2
h
h
PIN1
Lsser Mark
1
b1
2
TOP VIEW
2
1
Nd
EXPOSED THERMAL
PAD ZONE
SIDE VIEW
A1
c
A
BOTTOM VIEW
SYMBOL
A
A1
b
b1
c
D
D2
e
Nd
E
E2
L
L1
h
Rev 1.2
MIN
0.36
0
0.20
0.15
1.90
1.5
2.90
0.10
0.40
0.05
0.05
MILLIMETER
NOM
—
0.02
0.25
0.20
0.127REF
2.00
1.6
0.50BSC
1.50BSC
3.00
0.20
0.45
0.10
0.15
March/30/2020
MAX
0.40
0.05
0.30
0.25
2.10
1.7
3.10
0.30
0.50
0.15
0.25
Page 66
XT25F32B-S
3.3V QUAD IO Serial Flash
9.5. Package DFN8 (4x3x0.55) mm
D
A
△
B
A2
0.10 C
//
0.10 C
?
E
△
0.10 C
A
Side View
Top View
y C
A1
0.10 M C A B
C AB
D1
b
E1
0.10
0.10 M C A B
0.10 M C
L
E2
E1
0.10 M C A B
E2
ee/2
Bottom View
Symbol
Unit
Min
A
A1
0.50
0.00
Milli- Norm 0.55
mete
Max 0.60
A2
0.15
0.05
b
D
D1
E
E1
E2
e
0.25
2.90
0.10
3.90
0.70
0.30
3.00
0.25
4.00
0.80 0.80BSC 0.80BSC
0.35
3.10
0.40
4.10
0.90
y
L
0.00
0.50
0.60
0.08
0.70
Note:
1. Both package length and width do not include mold flash.
2. The exposed metal pad area on the bottom of the package is connected to device ground
(GND pin), so both Floating and connecting GND of exposed pad are also available.
Rev 1.2
March/30/2020
Page 67
3.3V QUAD IO Serial Flash
XT25F32B-S
10. REVISION HISTORY
Revision
Description
Date
1.0
Initial version
Jan-25-2019
1.1
Updated 7.1 Power-on Timing figure and description
Sep-18-2019
Updated to delete high temperature OPNs and changed operation current
to 30mA. Changed maximum sector erase time and write security register
time and typical page program time based on actual test result
DPD maximum change from 0.2uA to 4uA.
1.2
Standby maximum changed from 20uA to 40uA.
Mar-30-2020
Read Current at 50Mhz changed from 5/7mA to 7/10mA
Deleted tHLQZ, tHHQX, and updated description of Hold in Device Operation.
Updated 32K/64K tBE max to 1.2/1.6s
Rev 1.2
March/30/2020
Page 68
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