RTL8316E
LAYER 2 16-PORT 10/100M SINGLE-CHIP
SWITCH CONTROLLER
RTL8324E
LAYER 2 24-PORT 10/100M SWITCH
CONTROLLER WITH ONE XSMII
DATASHEET
(CONFIDENTIAL: Development Partners Only)
Rev. 1.0
24 April 2013
Track ID: JATR-8275-15
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211 Fax: +886-3-577-6047
www.realtek.com
RTL8316E/RTL8324E
Datasheet
COPYRIGHT
©2013 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document ‘as is’, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the hardware and software engineer’s general information on the Realtek
RTL8316E/RTL8324E chips.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.
REVISION HISTORY
Revision
1.0
Release Date
2013/04/24
Summary
First release.
Layer 2 16-Port & 24-Port 10/100M Switch Controllers
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RTL8316E/RTL8324E
Datasheet
Table of Contents
1.
GENERAL DESCRIPTION ..............................................................................................................................................1
2.
FEATURES .........................................................................................................................................................................2
3.
BLOCK DIAGRAMS.........................................................................................................................................................3
3.1.
3.2.
4.
SYSTEM APPLICATIONS...............................................................................................................................................5
4.1.
4.2.
5.
RTL8316E BLOCK DIAGRAM ......................................................................................................................................3
RTL8324E BLOCK DIAGRAM ......................................................................................................................................4
RTL8316E: 16*10/100M SWITCH ...............................................................................................................................5
RTL8324E: 24*10/100M SWITCH ...............................................................................................................................6
PIN ASSIGNMENTS AND DESCRIPTIONS (RTL8316E)...........................................................................................7
5.1.
PIN ASSIGNMENTS FIGURE (RTL8316E) .....................................................................................................................7
5.2.
PACKAGE IDENTIFICATION ...........................................................................................................................................7
5.3.
PIN ASSIGNMENTS TABLE DEFINITIONS (RTL8316E)..................................................................................................8
5.4.
PIN ASSIGNMENTS TABLE (RTL8316E).......................................................................................................................8
5.5.
PIN DESCRIPTIONS (RTL8316E) ................................................................................................................................10
5.5.1. Media Connection Pins (RTL8316E)....................................................................................................................10
5.5.2. Serial LED/LED IC Interface Pins (RTL8316E) ..................................................................................................11
5.5.3. SCAN LED Interface Pins (RTL8316E) ...............................................................................................................11
5.5.4. Miscellaneous Interface Pins (RTL8316E)...........................................................................................................11
5.5.5. Configuration Strapping Pins (RTL8316E)..........................................................................................................12
5.5.6. Power and GND Pins (RTL8316E) ......................................................................................................................13
6.
PIN ASSIGNMENTS AND DESCRIPTIONS (RTL8324E).........................................................................................14
6.1.
PIN ASSIGNMENTS FIGURE (RTL8324E) ...................................................................................................................14
6.2.
PACKAGE IDENTIFICATION .........................................................................................................................................14
6.3.
PIN ASSIGNMENTS TABLE DEFINITIONS (RTL8324E)................................................................................................15
6.4.
PIN ASSIGNMENTS TABLE (RTL8324E).....................................................................................................................15
6.5.
PIN DESCRIPTIONS (RTL8324E) ................................................................................................................................17
6.5.1. Media Connection Pins (RTL8324E)....................................................................................................................17
6.5.2. Serial LED Interface Pins (RTL8324E)................................................................................................................18
6.5.3. Miscellaneous Interface Pins (RTL8324E)...........................................................................................................18
6.5.4. Configuration Strapping Pins (RTL8324E)..........................................................................................................18
6.5.5. XSMII Interface Pins (RTL8324E) .......................................................................................................................19
6.5.6. Power and GND Pins (RTL8324E) ......................................................................................................................19
7.
PHYSICAL LAYER FUNCTIONAL OVERVIEW......................................................................................................20
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
8.
MDI INTERFACE ........................................................................................................................................................20
100BASE-TX TRANSMIT FUNCTION...........................................................................................................................20
100BASE-TX RECEIVE FUNCTION .............................................................................................................................20
10BASE-T TRANSMIT FUNCTION ...............................................................................................................................20
10BASE-T RECEIVE FUNCTION ..................................................................................................................................20
AUTO-NEGOTIATION FOR UTP ..................................................................................................................................21
CROSSOVER DETECTION AND AUTO CORRECTION .....................................................................................................21
POLARITY CORRECTION .............................................................................................................................................21
SWITCH FUNCTION DESCRIPTION .........................................................................................................................22
8.1.
HARDWARE RESET AND SOFTWARE RESET ................................................................................................................22
8.1.1. Hardware Reset ....................................................................................................................................................22
8.1.2. Software Reset ......................................................................................................................................................22
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8.2.
LAYER 2 LEARNING AND FORWARDING .....................................................................................................................22
8.2.1. Learning ...............................................................................................................................................................22
8.2.2. Forwarding...........................................................................................................................................................22
8.2.3. Address Table Aging.............................................................................................................................................22
8.3.
RESERVED MULTICAST ADDRESS HANDLING ............................................................................................................23
8.4.
IEEE 802.3X FLOW CONTROL ...................................................................................................................................23
8.5.
HALF DUPLEX BACKPRESSURE ..................................................................................................................................24
8.5.1. Collision-Based Backpressure (Jam Mode) .........................................................................................................24
8.5.2. Carrier-Based Backpressure (Defer Mode) .........................................................................................................25
8.6.
IEEE 802.3AZ ENERGY EFFICIENT ETHERNET (EEE) ................................................................................................25
8.7.
GREEN ETHERNET ......................................................................................................................................................25
8.7.1. Link Down Power Saving .....................................................................................................................................25
8.8.
IEEE 802.1P AND IEEE 802.1Q (VLAN) ..................................................................................................................25
8.9.
LOOP DETECTION .......................................................................................................................................................26
8.10.
LAYER 2 TRAFFIC SUPPRESSION (STORM CONTROL) .................................................................................................26
8.11.
IEEE 802.3AD LINK AGGREGATION PROTOCOL ........................................................................................................26
8.12.
BANDWIDTH CONTROL ..............................................................................................................................................26
8.12.1.
Input Bandwidth Control .................................................................................................................................26
8.12.2.
Output Bandwidth Control...............................................................................................................................26
8.13.
QUALITY OF SERVICE (QOS)......................................................................................................................................27
8.13.1.
Priority Arbitration..........................................................................................................................................27
8.13.2.
Port-Based Priority Assignment ......................................................................................................................27
8.13.3.
IEEE 802.1Q-Based Priority Assignment........................................................................................................27
8.13.4.
DSCP-Based Priority Assignment ...................................................................................................................27
8.13.5.
Internal Priority to Queue ID Table ................................................................................................................27
8.14.
PACKET SCHEDULING (WRR AND WFQ)...................................................................................................................28
8.15.
EGRESS PACKET REMARKING ....................................................................................................................................28
8.16.
INGRESS AND EGRESS PORT MIRROR .........................................................................................................................28
8.17.
MANAGEMENT INFORMATION BASE (MIB) ...............................................................................................................28
8.18.
REALTEK CABLE TESTER ...........................................................................................................................................29
8.19.
EEPROM CONFIGURATION .......................................................................................................................................29
9.
INTERFACE DESCRIPTIONS ......................................................................................................................................30
9.1.
9.2.
9.3.
9.4.
9.5.
9.6.
10.
XSMII INTERCONNECTION ........................................................................................................................................30
I2C-LIKE LED ...........................................................................................................................................................30
SERIAL LED CONNECTION.........................................................................................................................................31
SCAN LED FOR RTL8316E (NOT SUPPORTED IN THE RTL8324E)............................................................................32
I2C MASTER FOR EEPROM ......................................................................................................................................33
SERIAL CPU INTERFACE ............................................................................................................................................33
ELECTRICAL AC/DC CHARACTERISTICS ........................................................................................................34
10.1.
ABSOLUTE MAXIMUM RATINGS ................................................................................................................................34
10.2.
OPERATING RANGE ....................................................................................................................................................34
10.3.
DC CHARACTERISTICS ...............................................................................................................................................34
10.4.
AC CHARACTERISTICS ...............................................................................................................................................35
10.4.1.
XSMII Transmitter Signal Electrical Characteristics......................................................................................35
10.4.2.
XSMII Receiver Signal Electrical Characteristics...........................................................................................35
10.4.3.
Serial LED Signal Timing................................................................................................................................35
10.4.4.
Scan LED Mode Signal Timing (RTL8316E)...................................................................................................36
10.4.5.
I2C Master for EEPROM Timing ....................................................................................................................36
10.4.6.
SCK/SDA Power on Timing.............................................................................................................................37
10.4.7.
EEPROM Auto-Load Timing ...........................................................................................................................37
10.4.8.
I2C Master Mode Timing Characteristics .......................................................................................................37
10.4.9.
Serial CPU Interface Timing ...........................................................................................................................38
10.4.10.
Serial CPU Interface Timing Characteristics..................................................................................................38
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10.5.
SMI TIMING CHARACTERISTICS (RTL8324E ONLY) .................................................................................................38
11.
MECHANICAL DIMENSIONS.................................................................................................................................39
12.
ORDERING INFORMATION ...................................................................................................................................40
List of Tables
TABLE 1. PIN ASSIGNMENTS TABLE (RTL8316E).........................................................................................................................8
TABLE 2. MEDIA CONNECTION PINS (RTL8316E) ......................................................................................................................10
TABLE 3. SERIAL LED/LED IC INTERFACE PINS (RTL8316E) ...................................................................................................11
TABLE 4. SCAN LED INTERFACE PINS (RTL8316E)..................................................................................................................11
TABLE 5. MISCELLANEOUS INTERFACE PINS (RTL8316E)..........................................................................................................11
TABLE 6. CONFIGURATION STRAPPING PINS (RTL8316E) ..........................................................................................................12
TABLE 7. POWER AND GND PINS (RTL8316E)...........................................................................................................................13
TABLE 8. RTL8324E PIN ASSIGNMENTS TABLE (RTL8324E) ....................................................................................................15
TABLE 9. MEDIA CONNECTION PINS (RTL8324E) ......................................................................................................................17
TABLE 10. LED INTERFACE PINS (RTL8324E).............................................................................................................................18
TABLE 11. MISCELLANEOUS INTERFACE PINS (RTL8324E) .........................................................................................................18
TABLE 12. CONFIGURATION STRAPPING PINS (RTL8324E)..........................................................................................................18
TABLE 13. XSMII INTERFACE PINS (RTL8324E) .........................................................................................................................19
TABLE 14. POWER AND GND PINS (RTL8324E) ..........................................................................................................................19
TABLE 15. RESERVED MULTICAST ADDRESS DEFAULT ACTIONS .................................................................................................23
TABLE 16. ABSOLUTE MAXIMUM RATINGS ..................................................................................................................................34
TABLE 17. RECOMMENDED OPERATING RANGE ...........................................................................................................................34
TABLE 18. DC CHARACTERISTICS .................................................................................................................................................34
TABLE 19. XSMII TRANSMITTER SIGNAL ELECTRICAL CHARACTERISTICS ..................................................................................35
TABLE 20. XSMII RECEIVER SIGNAL ELECTRICAL CHARACTERISTICS ........................................................................................35
TABLE 21. I2C MASTER MODE TIMING CHARACTERISTICS ..........................................................................................................37
TABLE 22. SERIAL CPU INTERFACE TIMING CHARACTERISTICS ...................................................................................................38
TABLE 23. SMI TIMING CHARACTERISTICS (RTL8324E ONLY)...................................................................................................38
TABLE 24. ORDERING INFORMATION ............................................................................................................................................40
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Datasheet
List of Figures
FIGURE 1. RTL8316E BLOCK DIAGRAM .......................................................................................................................................3
FIGURE 2. RTL8324E BLOCK DIAGRAM .......................................................................................................................................4
FIGURE 3. RTL8316E: 16*10/100M SWITCH ................................................................................................................................5
FIGURE 4. RTL8324E: 24*10/100M SWITCH ................................................................................................................................6
FIGURE 5. PIN ASSIGNMENTS (RTL8316E) ...................................................................................................................................7
FIGURE 6. PIN ASSIGNMENTS (RTL8324E) .................................................................................................................................14
FIGURE 7. CONCEPTUAL EXAMPLE OF POLARITY CORRECTION ..................................................................................................21
FIGURE 8. TX PAUSE FRAME FORMAT ........................................................................................................................................23
FIGURE 9. FLOW CONTROL STATE MACHINE ..............................................................................................................................24
FIGURE 10. COLLISION-BASED BACKPRESSURE SIGNAL TIMING ..................................................................................................24
FIGURE 11. XSMII INTERCONNECTION .........................................................................................................................................30
FIGURE 12. SERIAL LED CONNECTION .........................................................................................................................................31
FIGURE 13. SCAN LED MODE CONNECTION .................................................................................................................................32
FIGURE 14. LARGE SIZE (32KB~512KB) EEPROM READ/WRITE TIMING ...................................................................................33
FIGURE 15. SMALL SIZE (4KB~8KB) EEPROM READ/WRITE TIMING .........................................................................................33
FIGURE 16. SERIAL CPU INTERFACE ACCESS DATA SEQUENCE ...................................................................................................33
FIGURE 17. SERIAL LED SIGNAL TIMING......................................................................................................................................35
FIGURE 18. SCAN LED MODE SIGNAL TIMING (RTL8316E) ........................................................................................................36
FIGURE 19. I2C MASTER MODE TIMING .......................................................................................................................................36
FIGURE 20. SCK/SDA POWER ON TIMING ....................................................................................................................................37
FIGURE 21. EEPROM AUTO-LOAD TIMING..................................................................................................................................37
FIGURE 22. SERIAL CPU INTERFACE TIMING ................................................................................................................................38
Layer 2 16-Port & 24-Port 10/100M Switch Controllers
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Datasheet
1. General Description
The RTL8316E and RTL8324E are Layer 2 16/24-port 10/100M switch controllers that integrate 16/24
MACs and 16 physical layer transceivers for 100Base-TX and 10Base-T operation.
The RTL8324E (only) supports one XSMII (Eight Serial Media Independent Interface), which can be
connected to an Octal PHY RTL8208D to provide a convenient solution for a 24-port Fast Ethernet
switch.
The RTL8316E/RTL8324E provides an 8K-entry L2 table with a 4-way hash algorithm for MAC address
learning and searching. The RTL8316E/RTL8324E supports IVL (Independent VLAN Learning), SVL
(Shared VLAN Learning), and IVL/SVL (Both Independent and Shared VLAN Learning) for flexible
network topology architecture. The RTL8316E/RTL8324E has a 512-entry VLAN table and 16-entry
VLAN CAM table for VLAN operation.
Per-port ingress/egress bandwidth control and per-port/per-queue egress bandwidth control are supported,
with four physical queues in each port. The RTL8316E/RTL8324E provides three types of packet
scheduling, including SP (Strict Priority), WRR (Weighted Round Robin) and WFQ (Weighted Fair
Queuing).
A loop-detection function provides notification of network loops. The RTL8316E/RTL8324E also
supports port mirror configuration to mirror ingress and egress traffic, and link aggregation to increase
link bandwidth and redundancy.
Layer 2 16-Port & 24-Port 10/100M Switch Controllers
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Datasheet
2. Features
Hardware Interface
RTL8316E: 16-port 10/100M high
performance Ethernet switch controller,
and 16 FE PHYs for 100Base-TX and
10Base-T
RTL8324E: 24-port 10/100M high
performance Ethernet switch controller,
and 16 FE PHYs for 100Base-TX and
10Base-T
RTL8324E (only) supports XSMII
interface to connect with octal FE PHY
RTL8316E (only) supports SCAN LED
RTL8316E/RTL8324E Support serial
LED interface
MAC Function
Supports 2KB jumbo frames
8K-entry L2 MAC table with 4-way
hashing algorithm
Supports source MAC blocking and
Destination MAC blocking
Supports Reserved Multicast Addresses
processing
Supports MAC Address learning
constraints on each port
L2 Miscellaneous Functions
Supports RLDP (Realtek Loop Detection
Protocol)
Supports cable diagnostics technology
Supports broadcast, multicast, unknownmulticast, and unknown-unicast packet
suppression control
Supports IEEE 802.3az (Energy
Efficient Ethernet, EEE) and Realtek
Green Ethernet
Supports TX and RX Port Mirroring
Supports Link Aggregation
(IEEE 802.3ad) for 4 groups of link
aggregators with up to 8 ports per-group
Port isolation function enhances port
security
QoS Functions
Four priority queues per port
Supports SP, WRR, WFQ scheduling
Ingress and egress rate limiting per port
MIB Functions
RFC2819 -- RMON MIB group 1, 2, 3, 9
RFC3635/RFC2863/RFC1213/RFC4188
/RFC4363
VLAN Function
Supports IVL, SVL, and IVL/SVL
Supports IEEE 802.1Q VLAN
512-entry VLAN Table
Port-based VLAN
Layer 2 16-Port & 24-Port 10/100M Switch Controllers
Others
55nm CMOS process
3.3V/1.2V dual-power input
LQFP128 E-PAD package
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Datasheet
3. Block Diagrams
3.1. RTL8316E Block Diagram
I2C
Serial LED/LED IC
Register
Controller
LED
Controller
SCAN LED
Storm Control
802.1x/STP/VLAN Egress Filter
802.1x/STP/VLAN Ingress Filter
802.3ad
按鈕
Input Bandwidth Control
Packet Remarking
L2 Table
QoS Manager
Mirror Process
Flow Control
Manager
MAC0
MAC 0
10/100M
Table Manager
Packet Buffer
Packet Filter
MAC2
MAC 0
10/100M
MAC4
MAC 0
10/100M
VLAN Table
Packet Modify
MAC6
MAC 0
10/100M
PHY0-7 (10Base-T/100Base -TX)
MAC8
MAC 0
10/100M
MAC10
MAC 0
10/100M
MAC12
MAC 0
10/100M
MAC14
MAC 0
10/100M
PHY8-15 (10Base-T/100Base-TX)
Figure 1. RTL8316E Block Diagram
Layer 2 16-Port & 24-Port 10/100M Switch Controllers
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3.2. RTL8324E Block Diagram
Serial LED/LED IC
MDC/MDIO and XSMII
MAC16
MAC20
10/100M
10/100M
MAC20
MAC
0
10/100M
MAC
0
MAC20
10/100M
I2C
MAC 0
MAC 0
Register
Controller
LED
Controller
Storm Control
802.1x/STP/VLAN Egress Filter
802.1x/STP/VLAN Ingress Filter
802.3ad
按鈕
Input Bandwidth Control
Packet Remarking
QoS Manager
Flow Control
Manager
MAC2
MAC 0
10/100M
MAC4
MAC 0
10/100M
VLAN Table
Table Manager
Packet Buffer
Packet Filter
MAC0
MAC 0
10/100M
L2 Table
Mirror Process
Packet Modify
MAC6
MAC 0
10/100M
PHY0-7 (10Base-T/100Base -TX)
MAC8
MAC 0
10/100M
MAC10
MAC 0
10/100M
MAC12
MAC 0
10/100M
MAC14
MAC 0
10/100M
PHY8-15 (10Base-T/100Base-TX)
Figure 2. RTL8324E Block Diagram
Layer 2 16-Port & 24-Port 10/100M Switch Controllers
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Datasheet
4. System Applications
4.1. RTL8316E: 16*10/100M Switch
EEPROM
FDR
Button
RTL8316E
SCAN
LED
8*MDI
8*MDI
LQFP128 E-PAD
Magnetics
Magnetics
FE P0-P7
FE P8-P15
Figure 3. RTL8316E: 16*10/100M Switch
Layer 2 16-Port & 24-Port 10/100M Switch Controllers
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Datasheet
4.2. RTL8324E: 24*10/100M Switch
EEPROM
FDR
Button
RTL8324E
RTL8231
LQFP128 E-PAD
8*MDI
Magnetics
Magnetics
FE P0-P7
RTL8208D
8*MDI
8*MDI
XSMII
FE P8-P15
Magnetics
FE P16-P23
Figure 4. RTL8324E: 24*10/100M Switch
Layer 2 16-Port & 24-Port 10/100M Switch Controllers
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Datasheet
5. Pin Assignments and Descriptions (RTL8316E)
For RTL8324E Pin Assignments and Descriptions, see section 6, page 14.
DVDD33
LED_SCAN2/LED_DEF
LED_SCAN3/LED_MODE_0
LED_SCAN4/EEPROMTYPE
LED_SCAN5/RESERVED
DVDD12
DVDD12
LED_DA
I2C_SCK
I2C_SDA
DVDD33
EN_STORMFILTER
PHY_PWRDOWN
LED_Mode_1
RESERVED
RESERVED
RESERVED
DVDD12
VDD12_PLL
GND_PLL
XI
XO
AVDD33_XTAL
GND_REXT
DVDD33
LED_STA0
LED_STA1
LED_STA2
LED_STA3
DVDD12
LED_STA4
LED_STA5
LED_SCAN0/DIS_FC
LED_SCAN1/EN_ISL
FDR#
LED_CK
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
DVDD12
RESET#
5.1. Pin Assignments Figure (RTL8316E)
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
RTL8316E
LLLLLLL
GXXXX TAIWAN
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
AVDD12
RXIP15
RXIN15
TXOP15
TXON15
AVDD33
TXON14
TXOP14
RXIN14
RXIP14
AVDD12
RXIP13
RXIN13
TXOP13
TXON13
AVDD33
TXON12
TXOP12
RXIN12
RXIP12
AVDD12
RXIP11
RXIN11
TXOP11
TXON11
AVDD33
TXON5
TXOP5
RXIN5
RXIP5
AVDD12
RXIP6
RXIN6
TXOP6
TXON6
AVDD33
TXON7
TXOP7
RXIN7
RXIP7
AVDD12
RXIP8
RXIN8
TXOP8
TXON8
AVDD33
TXON9
TXOP9
RXIN9
RXIP9
AVDD12
RXIP10
RXIN10
TXOP10
TXON10
AVDD33
DVDD12
DVDD12
AVDD12
RXIP4
RXIN4
TXOP4
TXON4
AVDD33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
DVDD12
AVDD33
IBREF
AVDD12
RXIP0
RXIN0
TXOP0
TXON0
AVDD33
TXON1
TXOP1
RXIN1
RXIP1
AVDD12
RXIP2
RXIN2
TXOP2
TXON2
AVDD33
TXON3
TXOP3
RXIN3
RXIP3
AVDD12
DVDD12
DVDD12
Figure 5. Pin Assignments (RTL8316E)
5.2. Package Identification
Green package is indicated by the ‘G’ in GXXXX (Figure 5).
Layer 2 16-Port & 24-Port 10/100M Switch Controllers
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Datasheet
5.3. Pin Assignments Table Definitions (RTL8316E)
Upon Reset: Defined as a short time after the end of a hardware reset.
After Reset: Defined as the time after the specified ‘Upon Reset’ time.
I: Input Pin
AI: Analog Input Pin
O: Output Pin
AO: Analog Output Pin
I/O: Bi-Directional Input/Output Pin
AI/O: Analog Bi-Directional Input/Output Pin
P: Digital Power Pin
AP: Analog Power Pin
G: Digital Ground Pin
AG: Analog Ground Pin
IPU: Input Pin With Pull-Up Resistor;
(Typical Value is 75KΩ)
IPD: Input Pin With Pull-Down Resistor;
(Typical Value is 75KΩ)
I/OPU: IPU and OPU
OPU: Output Pin With Pull-Up Resistor;
(Typical Value is 75KΩ)
OPD: Output Pin With Pull-Down Resistor;
(Typical Value is 75KΩ)
I/OPD: IPD and OPD
5.4. Pin Assignments Table (RTL8316E)
Name
DVDD12
AVDD12
RXIP4
RXIN4
TXOP4
TXON4
AVDD33
TXON5
TXOP5
RXIN5
RXIP5
AVDD12
RXIP6
RXIN6
TXOP6
TXON6
AVDD33
Table 1. Pin Assignments Table (RTL8316E)
Pin No.
Type
Name
1
P
TXON7
2
AP
TXOP7
3
AI/O
RXIN7
4
AI/O
RXIP7
5
AI/O
AVDD12
6
AI/O
RXIP8
7
AP
RXIN8
8
AI/O
TXOP8
9
AI/O
TXON8
10
AI/O
AVDD33
11
AI/O
TXON9
12
AP
TXOP9
13
AI/O
RXIN9
14
AI/O
RXIP9
15
AI/O
AVDD12
16
AI/O
RXIP10
17
AP
RXIN10
Layer 2 16-Port & 24-Port 10/100M Switch Controllers
8
Pin No.
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Type
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
Track ID: JATR-8275-15 Rev. 1.0
RTL8316E/RTL8324E
Datasheet
Name
TXOP10
TXON10
AVDD33
DVDD12
AVDD33
TXON11
TXOP11
RXIN11
RXIP11
AVDD12
RXIP12
RXIN12
TXOP12
TXON12
AVDD33
TXON13
TXOP13
RXIN13
RXIP13
AVDD12
RXIP14
RXIN14
TXOP14
TXON14
AVDD33
TXON15
TXOP15
RXIN15
RXIP15
AVDD12
DVDD12
DVDD12
LED_SCAN5/RESERVED
LED_SCAN4/EEPROMTYPE
LED_SCAN3/LED_MODE_0
LED_SCAN2/LED_DEF
DVDD33
LED_SCAN1/EN_ISL
LED_SCAN0/DIS_FC
LED_STA5
LED_STA4
DVDD12
LED_STA3
LED_STA2
Pin No.
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
Type
AI/O
AI/O
AP
P
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
P
P
I/OPD
I/OPD
I/OPD
I/OPD
P
I/OPD
I/OPD
OPD
OPD
P
OPD
OPD
Layer 2 16-Port & 24-Port 10/100M Switch Controllers
Name
LED_STA1
LED_STA0
DVDD33
GND_REXT
AVDD33_XTAL
XO
XI
GND_PLL
VDD12_PLL
DVDD12
RESERVED
RESERVED
RESERVED
LED_MODE_1
PHY_PWRDOWN
EN_STORMFILTER
DVDD33
I2C_SDA
I2C_SCK
LED_DA
LED_CK
FDR#
RESET#
DVDD12
DVDD12
AVDD33
IBREF
AVDD12
RXIP0
RXIN0
TXOP0
TXON0
AVDD33
TXON1
TXOP1
RXIN1
RXIP1
AVDD12
RXIP2
RXIN2
TXOP2
TXON2
AVDD33
TXON3
9
Pin No.
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
Type
OPD
OPD
P
AG
AP
AO
AI
AG
AP
P
I/OPD
I/OPD
I/OPD
IPD
IPD
IPD
P
I/OPU
I/OPU
I/OPU
OPU
IPU
AIPU
P
P
AP
AO
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
Track ID: JATR-8275-15 Rev. 1.0
RTL8316E/RTL8324E
Datasheet
Name
TXOP3
RXIN3
RXIP3
AVDD12
Pin No.
123
124
125
126
Type
AI/O
AI/O
AI/O
AP
Name
DVDD12
DVDD12
DGND
Pin No.
127
128
EPAD
Type
P
P
G
5.5. Pin Descriptions (RTL8316E)
5.5.1.
Media Connection Pins (RTL8316E)
Pin Name
RXIP15/RXIN15
RXIP14/RXIN14
RXIP13/RXIN13
RXIP12/RXIN12
RXIP11/RXIN11
RXIP10/RXIN10
RXIP9/RXIN9
RXIP8/RXIN8
RXIP7/RXIN7
RXIP6/RXIN6
RXIP5/RXIN5
RXIP4/RXIN4
RXIP3/RXIN3
RXIP2/RXIN2
RXIP1/RXIN1
RXIP0/RXIN0
TXOP15/TXON15
TXOP14/TXON14
TXOP13/TXON13
TXOP12/TXON12
TXOP11/TXON11
TXOP10/TXON10
TXOP9/TXON9
TXOP8/TXON8
TXOP7/TXON7
TXOP6/TXON6
TXOP5/TXON5
TXOP4/TXON4
TXOP3/TXON3
TXOP2/TXON2
TXOP1/TXON1
TXOP0/TXON0
Table 2.
Pin No.
63, 62
55, 56
53, 52
45, 46
43, 42
33, 34
31, 30
23, 24
21, 20
13, 14
11, 10
3, 4
125, 124
117, 118
115, 114
107, 108
61, 60
57, 58
51, 50
47, 48
41, 40
35, 36
29, 28
25, 26
19, 18
15, 16
9, 8
5, 6
123, 122
119, 120
113, 112
109, 110
Media Connection Pins (RTL8316E)
Type
Drive (mA) Description
AI/O
Differential Receive Data Input:
Port0~15 support 100Base-TX, 10Base-T
AI/O
Layer 2 16-Port & 24-Port 10/100M Switch Controllers
-
Differential Transmit Data Output:
Port0~15 support 100Base-TX, 10Base-T
10
Track ID: JATR-8275-15 Rev. 1.0
RTL8316E/RTL8324E
Datasheet
5.5.2.
Serial LED/LED IC Interface Pins (RTL8316E)
Table 3. Serial LED/LED IC Interface Pins (RTL8316E)
Pin No.
Type
Drive (mA) Description
99
OPU
4
In Serial LED mode: Reference output clock for serial LED
interface and Data is latched on the rising of LEDCK.
In I2C-like LED mode: Reference output clock for I2C-like
interface.
98
I/OPU
4
Serial LED Data Output.
In Serial LED mode: Serial bit stream of link status info.
In I2C-like LED mode: The data written to LED IC.
Pin Name
LED_CK
LED_DA
5.5.3.
SCAN LED Interface Pins (RTL8316E)
Pin Name
LED_STA[5:0]
LED_SCAN5/
RESERVED
Table 4. SCAN LED Interface Pins (RTL8316E)
Pin No.
Type
Drive (mA) Description
OPD
8
Scan LED Mode Status Pins.
74, 75, 77,
78, 79, 80
8
Scan LED Mode Scan Pins.
I/OPD
67
LED_SCAN4/
EEPROMTYPE
68
LED_SCAN3/
LED_MODE_0
69
LED_SCAN2/
LED_DEF
70
LED_SCAN1/
EN_ISL
72
LED_SCAN0/
DIS_FC
73
5.5.4.
Pin Name
I2C_SCK
I2C_SDA
FDR#
XI
Miscellaneous Interface Pins (RTL8316E)
Table 5. Miscellaneous Interface Pins (RTL8316E)
Pin No.
Type
Drive (mA) Description
97
I/OPU
4
I2C Interface Clock.
For normal mode (100KHz), a cycle time is 10µs. For fast
mode (400KHz), it is 2.5µs.
96
I/OPU
4
I2C Interface Data Input/Output.
100
IPU
Factory default recovery input pin.
Takes effect when asserted low for at least 3 seconds.
85
AI
25MHz Crystal Clock Input and Feedback Pin.
Layer 2 16-Port & 24-Port 10/100M Switch Controllers
11
Track ID: JATR-8275-15 Rev. 1.0
RTL8316E/RTL8324E
Datasheet
Pin Name
XO
RESET#
IBREF
Pin No.
84
101
105
Type
AO
AIPU
AO
Drive (mA)
-
RESERVED
91, 90,
89
67
I/OPD
-
Description
25MHz Crystal Clock Output Pin.
System Pin Reset Input.
Reference Resistor for PHY Bandgap.
A 2.49KΩ (1%) resistor should be connected between IBREF
and GND.
Reserved for internal use.
I/OPD
-
Reserved for internal use.
RESERVED /
LED_SCAN5
5.5.5.
Configuration Strapping Pins (RTL8316E)
Pin Name
EEPROMTYPE/
LED_SCAN4
LED_MODE_1
LED_MODE_0/
LED_SCAN3
LED_DEF/
LED_SCAN2
Table 6. Configuration Strapping Pins (RTL8316E)
Pin No.
Type
Default
Description
68
I/OPD
Select EEPROM Auto-Load Address Byte Size.
0: 2-Byte (default)
1: 1-Byte
LED Mode Select.
IPD
92
00: Serial LED mode (default)
69
01: I2C-like LED mode
10: SCAN LED mode
11: Reserved
70
I/OPD
LED Status Default Mode Select.
0: Select mode0 (default)
1: Select mode1
LED Group
Mode0
Mode1
LED0
Link/Act
Spd100Link/Act
LED1
Speed100
Spd10Link/Act
LED2
Speed10
Full Duplex
EN_ISL/
LED_SCAN1
72
I/OPD
-
DIS_FC/
LED_SCAN0
73
I/OPD
-
PHY_PWRDOWN
93
IPD
-
EN_STORMFILTER
94
IPD
-
Layer 2 16-Port & 24-Port 10/100M Switch Controllers
Enable Port Isolation.
0: Disable port isolation (default)
1: Enable port isolation
Enable All Port Flow Control.
0: Enable (default)
1: Disable
Enable PHY Power Down When Power On.
0: Normal (default)
1: Enable PHY power down when power on
Enable Broadcast Storm Filter.
0: Disable traffic storm filter (default)
1: Enable traffic storm filter
12
Track ID: JATR-8275-15 Rev. 1.0
RTL8316E/RTL8324E
Datasheet
5.5.6.
Power and GND Pins (RTL8316E)
Pin Name
AVDD33
AVDD12
DVDD33
DVDD12
VDD12_PLL
GND_PLL
AVDD33_XTAL
GND_REXT
Table 7. Power and GND Pins (RTL8316E)
Pin No.
Type
Description
AP
Analog Power 3.3V.
7, 17, 27, 37, 39, 49,
59, 104, 111, 121
AP
Analog Power 1.2V.
2, 12, 22, 32, 44, 54,
64, 106, 116, 126
71, 81, 95
P
Digital Power 3.3V for IO Pad.
P
Digital Power 1.2V for Core Voltage.
1, 38, 65, 66, 76, 88,
102, 103, 127, 128
87
AP
Power for PLL.
86
AG
Ground for PLL.
83
AP
Analog Power for Crystal.
82
AG
Analog Ground.
Layer 2 16-Port & 24-Port 10/100M Switch Controllers
13
Track ID: JATR-8275-15 Rev. 1.0
RTL8316E/RTL8324E
Datasheet
6. Pin Assignments and Descriptions (RTL8324E)
For RTL8316E Pin Assignments and Descriptions, see section 5, page 7.
6.1. Pin Assignments Figure (RTL8324E)
DVDD12
AVDD33
IBREF
AVDD12
RXIP0
RXIN0
TXOP0
TXON0
AVDD33
TXON1
TXOP1
RXIN1
RXIP1
AVDD12
RXIP2
RXIN2
TXOP2
TXON2
AVDD33
TXON3
TXOP3
RXIN3
RXIP3
AVDD12
DVDD12
DVDD12
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
RTL8324E
LLLLLLL
GXXXX TAIWAN
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
AVDD12
RXIP15
RXIN15
TXOP15
TXON15
AVDD33
TXON14
TXOP14
RXIN14
RXIP14
AVDD12
RXIP13
RXIN13
TXOP13
TXON13
AVDD33
TXON12
TXOP12
RXIN12
RXIP12
AVDD12
RXIP11
RXIN11
TXOP11
TXON11
AVDD33
Figure 6. Pin Assignments (RTL8324E)
6.2. Package Identification
Green package is indicated by the ‘G’ in GXXXX (Figure 6).
Layer 2 16-Port & 24-Port 10/100M Switch Controllers
14
Track ID: JATR-8275-15 Rev. 1.0
RTL8316E/RTL8324E
Datasheet
6.3. Pin Assignments Table Definitions (RTL8324E)
Upon Reset: Defined as a short time after the end of a hardware reset.
After Reset: Defined as the time after the specified ‘Upon Reset’ time.
I: Input Pin
AI: Analog Input Pin
O: Output Pin
AO: Analog Output Pin
I/O: Bi-Directional Input/Output Pin
AI/O: Analog Bi-Directional Input/Output Pin
P: Digital Power Pin
AP: Analog Power Pin
G: Digital Ground Pin
AG: Analog Ground Pin
IPU: Input Pin With Pull-Up Resistor;
(Typical Value approximately 75KΩ)
IPD: Input Pin With Pull-Down Resistor;
(Typical Value approximately 75KΩ)
I/OPU: IPU and OPU
OPU: Output Pin With Pull-Up Resistor;
(Typical Value approximately 75KΩ)
OPD: Output Pin With Pull-Down Resistor;
(Typical Value approximately 75KΩ)
I/OPD: IPD and OPD
6.4. Pin Assignments Table (RTL8324E)
Name
DVDD12
AVDD12
RXIP4
RXIN4
TXOP4
TXON4
AVDD33
TXON5
TXOP5
RXIN5
RXIP5
AVDD12
RXIP6
RXIN6
TXOP6
TXON6
AVDD33
Table 8. RTL8324E Pin Assignments Table (RTL8324E)
Pin No.
Type
Name
1
P
TXON7
2
AP
TXOP7
3
AI/O
RXIN7
4
AI/O
RXIP7
5
AI/O
AVDD12
6
AI/O
RXIP8
7
AP
RXIN8
8
AI/O
TXOP8
9
AI/O
TXON8
10
AI/O
AVDD33
11
AI/O
TXON9
12
AP
TXOP9
13
AI/O
RXIN9
14
AI/O
RXIP9
15
AI/O
AVDD12
16
AI/O
RXIP10
17
AP
RXIN10
Layer 2 16-Port & 24-Port 10/100M Switch Controllers
15
Pin No.
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Type
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
Track ID: JATR-8275-15 Rev. 1.0
RTL8316E/RTL8324E
Datasheet
Name
TXOP10
TXON10
AVDD33
DVDD12
AVDD33
TXON11
TXOP11
RXIN11
RXIP11
AVDD12
RXIP12
RXIN12
TXOP12
TXON12
AVDD33
TXON13
TXOP13
RXIN13
RXIP13
AVDD12
RXIP14
RXIN14
TXOP14
TXON14
AVDD33
TXON15
TXOP15
RXIN15
RXIP15
AVDD12
DVDD12
DVDD12
RESERVED
EEPROMTYPE
LED_MODE
LED_DEF
DVDD33
EN_ISL
DIS_FC
DVDD12
SAVDD12
SRXN
SRXP
AVSS
Pin No.
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
Type
AI/O
AI/O
AP
P
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
P
P
I/OPD
IPD
IPD
IPD
P
IPD
IPD
P
AP
AI
AI
AG
Layer 2 16-Port & 24-Port 10/100M Switch Controllers
Name
25M_CLKO
SAVDD12
STXP
STXN
AVSS
NC
GND_REXT
REXT
AVDD33_XTAL
XO
XI
GND_PLL
VDD12_PLL
DVDD12
MDC
MDIO
DVDD33
I2C_SDA
I2C_SCK
LED_DA
LED_CK
FDR#
RESET#
DVDD12
DVDD12
AVDD33
IBREF
AVDD12
RXIP0
RXIN0
TXOP0
TXON0
AVDD33
TXON1
TXOP1
RXIN1
RXIP1
AVDD12
RXIP2
RXIN2
TXOP2
TXON2
AVDD33
TXON3
16
Pin No.
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
Type
O
AP
AO
AO
AG
AG
AO
AP
AO
AI
AG
AP
P
OPU
I/OPU
P
I/OPU
I/OPU
I/OPU
OPU
IPU
AIPU
P
P
AP
AO
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
AI/O
AI/O
AI/O
AP
AI/O
Track ID: JATR-8275-15 Rev. 1.0
RTL8316E/RTL8324E
Datasheet
Name
TXOP3
RXIN3
RXIP3
AVDD12
Pin No.
123
124
125
126
Type
AI/O
AI/O
AI/O
AP
Name
DVDD12
DVDD12
DGND
Pin No.
127
128
EPAD
Type
P
P
G
6.5. Pin Descriptions (RTL8324E)
6.5.1.
Media Connection Pins (RTL8324E)
Pin Name
RXIP15/RXIN15
RXIP14/RXIN14
RXIP13/RXIN13
RXIP12/RXIN12
RXIP11/RXIN11
RXIP10/RXIN10
RXIP9/RXIN9
RXIP8/RXIN8
RXIP7/RXIN7
RXIP6/RXIN6
RXIP5/RXIN5
RXIP4/RXIN4
RXIP3/RXIN3
RXIP2/RXIN2
RXIP1/RXIN1
RXIP0/RXIN0
TXOP15/TXON15
TXOP14/TXON14
TXOP13/TXON13
TXOP12/TXON12
TXOP11/TXON11
TXOP10/TXON10
TXOP9/TXON9
TXOP8/TXON8
TXOP7/TXON7
TXOP6/TXON6
TXOP5/TXON5
TXOP4/TXON4
TXOP3/TXON3
TXOP2/TXON2
TXOP1/TXON1
TXOP0/TXON0
Table 9.
Pin No.
63, 62
55, 56
53, 52
45, 46
43, 42
33, 34
31, 30
23, 24
21, 20
13, 14
11, 10
3, 4
125, 124
117, 118
115, 114
107, 108
61, 60
57, 58
51, 50
47, 48
41, 40
35, 36
29, 28
25, 26
19, 18
15, 16
9, 8
5, 6
123, 122
119, 120
113, 112
109, 110
Media Connection Pins (RTL8324E)
Type
Drive (mA) Description
AI/O
Differential Receive Data Input:
Port0~15 supports 100Base-TX, 10Base-T
AI/O
Layer 2 16-Port & 24-Port 10/100M Switch Controllers
-
Differential Transmit Data Output:
Port0~15 supports 100Base-TX, 10Base-T
17
Track ID: JATR-8275-15 Rev. 1.0
RTL8316E/RTL8324E
Datasheet
6.5.2.
Serial LED Interface Pins (RTL8324E)
Pin Name
LED_CK
Pin No.
99
LED_DA
98
6.5.3.
Miscellaneous Interface Pins (RTL8324E)
Pin Name
I2C_SCK
I2C_SDA
MDC
MDIO
FDR#
XI
XO
RESET
IBREF
RESERVED
6.5.4.
Table 10. LED Interface Pins (RTL8324E)
Type
Drive (mA) Description
OPU
4
In Serial LED Mode:
Reference output clock for serial LED interface and Data is
latched on the rising of LEDCK.
In I2C-like LED Mode:
Reference output clock for I2C-like interface.
I/OPU
4
Serial LED Data Output.
In Serial LED Mode: Serial bit stream of link status info.
In I2C-like LED mode: The data written to LED IC.
Table 11. Miscellaneous Interface Pins (RTL8324E)
Pin No.
Type
Drive (mA) Description
97
I/OPU
4
I2C Interface Clock.
For normal mode (100KHz), one cycle time is 10µs. For fast
mode (400KHz), it is 2.5µs.
96
I/OPU
4
I2C Interface Data Input/Output.
94
OPU
8
MII Management Interface Clock Pin.
93
I/OPU
8
MII Management Interface Data Pin.
100
IPU
Factory Default Recovery Input Pin.
Takes effect when pulled down for at least 3 seconds.
89
AI
25MHz Crystal Clock Input and Feedback Pin.
88
AO
25MHz Crystal Clock Output Pin.
101
AIPU
System Pin Reset Input.
105
AO
Reference Resistor for the Chip.
A 2.49KΩ (1%) resistor should be connected between IBREF
and GND.
67
I/OPD
Reserved for internal use.
Configuration Strapping Pins (RTL8324E)
Pin Name
EEPROMTYPE
LED_MODE
Table 12. Configuration Strapping Pins (RTL8324E)
Pin No.
Type
Drive (mA) Description
68
IPD
Select EEPROM Auto-Load Address Byte Size.
0: 2-Byte (default)
1: 1-Byte
69
IPD
LED Mode Select.
0: Serial LED mode (default)
1: I2C-like LED mode
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Pin Name
LED_DEF
Pin No.
70
Type
IPD
Drive (mA) Description
LED Status Default Mode Select.
0: Select mode0 (default)
1: Select mode1
LED Group
Mode0
LED0
Link/Act
LED1
Speed100
LED2
Speed10
EN_ISL
72
IPD
-
DIS_FC
73
IPD
-
6.5.5.
Enable Port Isolation.
0: Disable port isolation (default)
1: Enable port isolation
Enable All Port Flow Control.
0: Enable (default)
1: Disable
XSMII Interface Pins (RTL8324E)
Pin Name
STXP/STXN
SRXP/SRXN
25M_CLKO
REXT
Pin No.
81, 82
77, 76
79
86
GND_REXT
85
6.5.6.
Mode1
Spd100Link/Act
Spd10Link/Act
Full Duplex
Table 13. XSMII Interface Pins (RTL8324E)
Type
Drive (mA) Description
AO
XSMII Interface Transmit Data Differential Output Pair.
AI
XSMII Interface Receive Data Differential Input Pair.
O
4
25MHz Clock Output.
AO
Reference Resistor for XSMII Bandgap.
A 12KΩ (1%) resistor should be connected between REXT and
GND.
AG
Ground for XSMII Bandgap.
Power and GND Pins (RTL8324E)
Table 14. Power and GND Pins (RTL8324E)
Pin Name
Pin No.
Type
AVDD33
7, 17, 27, 37, 39, 49,
59, 104, 111, 121
2, 12, 22, 32, 44, 54,
64, 106, 116, 126
71, 95
1, 38, 65, 66, 74, 92,
102, 103, 127, 128
91
90
87
75, 80
78
AP
Analog Power 3.3V.
AP
Analog Power 1.2V.
AVDD12
DVDD33
DVDD12
VDD12_PLL
GND_PLL
AVDD33_XTAL
SAVDD12
AVSS
P
P
AP
AG
AP
AP
AG
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Description
Digital Power 3.3V for IO Pad.
Digital Power 1.2V for Core Voltage.
Power for PLL.
Ground for PLL.
Analog Power for Crystal.
Analog Power for XSMII.
Analog Ground for XSMII.
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7. Physical Layer Functional Overview
7.1. MDI Interface
The RTL8316E/RTL8324E embeds 16 Fast Ethernet PHYs in one chip. Each port uses a single common
MDI interface to support 100Base-TX and 10Base-T. This interface consists of two signal pairs
RXIP/RXIN, and TXOP/TXON. The MDI interface has internal termination resistors for reduced BOM
cost and PCB complexity.
7.2. 100Base-TX Transmit Function
The 100Base-TX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling,
NRZ/NRZI conversion, and MLT-3 encoding. The 5-bit serial data stream after 4B/5B coding is then
scrambled as defined by the TP-PMD Stream Cipher function to flatten the power spectrum energy such
that EMI effects can be reduced significantly.
The scrambled seed is based on PHY addresses and is unique for each port. After scrambling, the bit
stream is driven into the network media in the form of MLT-3 signaling. The MLT-3 multi-level
signaling technology moves the power spectrum energy from high frequency to low frequency, which
also reduces EMI emissions.
7.3. 100Base-TX Receive Function
The receive path includes a receiver composed of an adaptive equalizer and DC restoration circuits (to
compensate for an incoming distorted MLT-3 signal), an MLT-3 to NRZI and NRZI to NRZ converter to
convert analog signals to digital bit-stream, and a PLL circuit to clock data bits with minimum bit error
rate. A De-scrambler, 5B/4B decoder, and serial-to-parallel conversion circuits are followed by the PLL
circuit. Finally, the converted parallel data is fed into the MAC.
7.4. 10Base-T Transmit Function
The output 10Base-T waveform is Manchester-encoded before it is driven onto the network media. The
internal filter shapes the driven signals to reduce EMI emissions, eliminating the need for an external
filter.
7.5. 10Base-T Receive Function
The Manchester decoder converts the incoming serial stream to NRZ data when the squelch circuit
detects the signal level is above squelch level.
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7.6. Auto-Negotiation for UTP
The RTL8316E/RTL8324E obtains the states of duplex, speed, and flow control ability for each port in
UTP mode through the auto-negotiation mechanism defined in the IEEE 802.3 specifications. During
auto-negotiation, each port advertises its ability to its link partner and compares its ability with
advertisements received from its link partner. By default, the RTL8316E/RTL8324E advertises full
capabilities (100Full, 100Half, 10Full, 10Half) together with flow control ability.
7.7. Crossover Detection and Auto Correction
During the link setup phase, the RTL8316E/RTL8324E checks whether it receives active signals on every
port in order to determine if a connection can be established. The RTL8316E/RTL8324E can identify the
type of connected cable and sets the port to MDI or MDIX. When in MDI mode, the
RTL8316E/RTL8324E uses TXOP/N as transmit pair; when in MDIX mode, the RTL8316E/RTL8324E
uses RXIP/N as transmit pair.
7.8. Polarity Correction
The RTL8316E/RTL8324E automatically corrects polarity errors on the receiver pairs in 10Base-T mode.
In 100Base-TX mode, the polarity does not matter.
+
RX _
TX
+
_
+
_
_
+
RTL8316D/8324D
Link Partner
In 10Base-T mode, polarity errors are corrected based on the detection of valid spaced link pulses. The
detection begins during the MDI crossover detection phase and locks when the 10Base-T link is up. The
polarity becomes unlocked when the link is down.
TX
+
_ RX
Figure 7. Conceptual Example of Polarity Correction
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8. Switch Function Description
8.1. Hardware Reset and Software Reset
8.1.1.
Hardware Reset
A hardware reset forces the RTL8316E/RTL8324E to start the initial power-on sequence. First hardware
will strap pins to give all default values when the ‘RESET’ signal terminates. Next the configuration is
auto-loaded from EEPROM (if EEPROM is detected), and then the complete SRAM BIST (Built-In Self
Test) process is run.
8.1.2.
Software Reset
The RTL8316E/RTL8324E supports a Switch Soft reset to reset the Switch packet buffer. All reset
signals are low active.
8.2. Layer 2 Learning and Forwarding
The RTL8316E/RTL8324E supports IVL (Independent VLAN Learning), SVL (Shared VLAN Learning),
and IVL/SVL (Both Independent and Shared VLAN Learning).
8.2.1.
Learning
The RTL8316E/RTL8324E features a Layer 2 hash table (8K-entry). It uses a 4-way hash structure to
store L2 entries. The L2 Unicast hash key is {MAC, FID/VID}.
8.2.2.
Forwarding
When the VLAN egress filtering option is enabled, a received unicast frame will be forwarded to its
destination port only if the destination port is in the same VLAN as the source port. If the destination port
belongs to a different VLAN, the frame will be discarded.
By default the received broadcast/multicast frame will flood to VLAN member ports only, except for the
source port.
8.2.3.
Address Table Aging
In a dynamic network topology, address aging allows the contents of the address table to always be the
most recent and correct. A learned source address entry will be cleared (aged out) if it is not updated by
the address learning process within an aging time period. The aging timer of the MAC address lookup
table can be configured to between 1~65535 seconds (default value is approximately 300s).
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8.3. Reserved Multicast Address Handling
The RTL8316E/RTL8324E supports Reserved Multicast Address (RMA) as defined in the IEEE 802.1
standard. For each RMA, the actions include Forward and Drop. The action priority is higher than the
results of a L2 Table lookup. Default actions are shown in Table 15.
Table 15. Reserved Multicast Address Default Actions
Name
Address
Bridge Group Address
01-80-C2-00-00-00
IEEE Std 802.3, 1988 Edition, Full Duplex PAUSE Operation
01-80-C2-00-00-01
IEEE Std 802.3ad Slow Protocols-Multicast Address
01-80-C2-00-00-02
IEEE Std 802.1X PAE Address
01-80-C2-00-00-03
Reserved for future protocol standards
01-80-C2-00-00-04~01-80-C2-00-00-0D,
01-80-C2-00-00-0F
01-80-C2-00-00-0E
LLDP IEEE Std 802.1AB Link Layer Discovery Protocol
Multicast Address
All LANs Bridge Management Group Address
01-80-C2-00-00-10
GMRP
01-80-C2-00-00-20
GVRP
01-80-C2-00-00-21
Reserved for use by Multiple Registration
01-80-C2-00-00-22~01-80-C2-00-00-2F
Protocol (MRP) applications
IEEE 802.1ag PDU CCM/LTM
01-80-C2-00-00-31~01-80-C2-00-00-3F
Default
Forward
Drop
Drop
Forward
Drop
Forward
Drop
Drop
Forward
Drop
Forward
8.4. IEEE 802.3x Flow Control
The RTL8316E/RTL8324E supports IEEE 802.3x full duplex flow control. If one port’s receive buffer is
over the pause-on threshold, a pause-on frame is sent to the link partner to stop the transmission. When
the port’s receive buffer drops below the pause-off threshold, it sends a pause-off frame. The pause frame
format is shown in Figure 8.
Figure 8. TX Pause Frame Format
The flow control mechanism of the RTL8316E/RTL8324E is implemented on the RX side. It counts the
received pages on the RX side in order to determine on which port it should send out Pause On/Off
packets.
When RTL8316E/RTL8324E flow control is enabled, the initial state is ‘Non_Congest’. The state is
monitored continuously. If a pause-on trigger condition occurs, it enters the ‘Congest’ state. When in the
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‘congest’ state, it is also continuously monitored. When a pause-off trigger condition occurs it re-enters
the ‘Non_Congest’ state. Figure 9 shows the flow control state machine.
Trigger Condition for Pause-Off
Initial state; Flow
Control Enabled
Non-Congest State
Congest State
Trigger Condition for Pause-On
Figure 9. Flow Control State Machine
8.5. Half Duplex Backpressure
There are two mechanisms for half-duplex backpressure: collision-based or carrier-based.
8.5.1.
Collision-Based Backpressure (Jam Mode)
If the input buffer is ready to overflow, this mechanism will force a collision. When the link partner
detects this collision, the transmission is rescheduled.
The Reschedule procedure is:
•
The RTL8316E/RTL8324E will drive TXEN to high and send a 4-byte Jam signal (pattern is 0x55).
The RTL8316E/RTL8324E will then drive TXEN to low.
•
When the link partner receives the Jam signal, it will feedback a 4-byte signal (pattern is 0xFF), then
it will drive RXDV to low.
•
The link partner waits for a random back-off time then re-sends the packet. The timing is shown in
Figure 10.
Figure 10. Collision-Based Backpressure Signal Timing
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8.5.2.
Carrier-Based Backpressure (Defer Mode)
If the input buffer is about to overflow, this mechanism will send a 0x55 pattern to defer the other
station’s transmission. The RTL8316E/RTL8324E will continuously send the defer signal until the input
buffer overflow is resolved.
8.6. IEEE 802.3az Energy Efficient Ethernet (EEE)
The RTL8316E/RTL8324E supports IEEE 802.3az Energy Efficient Ethernet (EEE) ability for 100BaseTX in full duplex operation, and supports 10Base-Te for 10Base-T in full/half duplex .The Energy
Efficient Ethernet (EEE) operational mode combines the IEEE 802.3 Media Access Control (MAC) Sublayer with a family of Physical Layers defined to support operation in Low Power Idle (LPI) Mode. When
the port is in LPI Mode, link partners of both sides can turn off the unnecessary TX/RX circuits to save
power consumption during periods of low link utilization.
The RTL8316E/RTL8324E EEE operational mode supports the IEEE 802.3 MAC operation at 100Mbps.
In addition, the RTL8316E/RTL8324E supports 10Mbps PHY with reduced transmit amplitude
requirements in EEE operational mode. This new PHY is fully interoperable with legacy 10Base-T PHY
over 100m of Class-D (Category 5) or better cabling.
8.7. Green Ethernet
8.7.1.
Link Down Power Saving
The RTL8316E/RTL8324E implements link-down power saving on a per-port basis, greatly cutting
power consumption when the network cable is disconnected. A port automatically enters link down power
saving mode ten seconds after the cable is disconnected from it. Once a port enters link down power
saving mode, it transmits normal link pulses on its TXOP/TXON pins and continues to monitor the
RXIP/RXIN pins to detect incoming signals, which might be 100Base-TX MLT-3 idle pattern, 10Base-T
link pulses, or Auto-Negotiation’s FLP (Fast Link Pulse). After it detects an incoming signal, it wakes up
from link down power saving mode and operates in normal mode according to the result of the
connection.
8.8. IEEE 802.1p and IEEE 802.1Q (VLAN)
The RTL8316E/RTL8324E supports IEEE 802.1p and 802.1Q tag-based, port-based VLAN. It provides a
512-entry VLAN table and 16-entry VLAN CAM table. VLAN table lookup applies a 4-Way hash
algorithm, and the CAM table is used to resolve hash collisions.
The RTL8316E/RTL8324E uses VID[0:6] as an index to the VLAN table. If the remaining 5-bit
VID[7:11] is matched in the entry, it means this entry lookup is a hit. If the VLAN table lookup fails, the
chip will perform a lookup in the 16-entry VLAN CAM table.
The RTL8316E/RTL8324E features an ingress filter function; packets from an input port that is not in the
member set will be dropped. This function can be enabled or disabled via register configuration.
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8.9. Loop Detection
The RTL8316E/RTL8324E periodically transmits a Realtek protocol frame to detect network loop faults.
If a port detects a loop, the LED corresponding to the looped port will blink until the loop is resolved. At
the same time, the loop event flag will be set.
8.10. Layer 2 Traffic Suppression (Storm Control)
The RTL8316E/RTL8324E supports the storm filter function for each port. The storm types are broadcast
storm, known multicast storm, unknown multicast storm, and unknown DA unicast storm. The
RTL8316E/RTL8324E can control the four storm types via one leaky bucket per port.
8.11. IEEE 802.3ad Link Aggregation Protocol
The RTL8316E/RTL8324E supports 802.3ad (Link Aggregation) for 4 groups of link aggregators with up
to 8 ports per-group. The chosen ports must be in full duplex mode and they must have the same
attributes (for example: All 100Mbps or all 10Mbps). The link aggregation group is regarded as one
logical port and has an ID (the lowest port number of the physically aggregated port members is used as
its ID).
8.12. Bandwidth Control
8.12.1. Input Bandwidth Control
The RTL8316E/RTL8324E has input bandwidth control per port. If the speed of received packets is faster
than the bandwidth setting of this port, the switch will send a pause frame to the link partner or drop
packets, according to its flow control setting.
8.12.2. Output Bandwidth Control
The RTL8316E/RTL8324E has output bandwidth control per port, and has output bandwidth control per
queue in WRR mode. The bandwidth granularity is 16Kbps.
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8.13. Quality of Service (QoS)
The RTL8316E/RTL8324E identifies the priority of packets based on three types of QOS priority
information:
•
Port-based
•
IEEE 802.1Q-based
•
DSCP-based
8.13.1. Priority Arbitration
The RTL8316E/RTL8324E has two priority arbitration weight tables to decide which type of priority
should be accepted when multiple types of priority exist. Each port can be set to its own Priority
arbitration weight.
8.13.2. Port-Based Priority Assignment
Port-based priority assignment specifies a 3-bit priority for each physical port. When a packet is received
from a physical port, it is assigned the 3-bit priority of that physical port.
8.13.3. IEEE 802.1Q-Based Priority Assignment
In IEEE 802.1Q-based priority assignment, when a packet is VLAN-tagged or priority-tagged, the 3-bit
priority is specified by tag. When a packet is untagged, the 802.1Q-based priority is assigned to the
default 3-bit priority information of a physical port. Each port must provide a default 3-bit priority (every
received packet must be assigned a 3-bit 1Q-Based Priority). When the priority comes from a packet, the
1Q-based priority is acquired by mapping 3-bit tag priority to 3-bit priority though a
RTL8316E/RTL8324E 1Q-based Priority Mapping Table. The 1Q-based priority can be disabled.
8.13.4. DSCP-Based Priority Assignment
The RTL8316E/RTL8324E has 2 tables to map 6-bit DSCP values to 3-bit internal priorities. Each table
has 64 entries. Each port can decide which table to use. The DSCP-based priority assignment can be
disabled by setting its weight to 0 in the Priority arbitration weight table.
8.13.5. Internal Priority to Queue ID Table
The RTL8316E/RTL8324E can transfer its internal priority to the output queue ID. Each port has a table
with 8 entries to map the 3-bit internal priority to 2-bit queue ID.
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8.14. Packet Scheduling (WRR and WFQ)
The RTL8316E/RTL8324E has four queues per port. The Packet Scheduler controls the multiple traffic
classes (i.e., controls the packet sending sequence of the priority queue). The RTL8316E/RTL8324E has
two scheduling algorithms: Weighted Round-Robin (WRR) and Weighted Fair-Queuing (WFQ). Note
that the Strict Priority queue is the highest priority of all queues, and overrides WFQ & WRR. A larger
strict priority queue ID indicates the priority is higher.
The Scheduler operates as follows:
•
Weighted Fair-Queuing (WFQ): Byte-count
•
Weighted Round-Robin (WRR): Packet-count
Note that WFQ and WRR cannot exist at the same time.
8.15. Egress Packet Remarking
RTL8316E/RTL8324E Remarking can be divided into 1p remarking and DSCP remarking. For 1p
remarking, there is an internal priority to user priority table that is used to configure the final user priority
value for the whole system. DSCP remarking also has an internal priority to DSCP priority table.
8.16. Ingress and Egress Port Mirror
If a frame meets the Ingress and Egress mirroring port conditions, the RTL8316E/RTL8324E duplicates
the packet to the mirroring port. The RTL8316E/RTL8324E has one mirror set, and the mirroring port
can monitor several mirrored ports simultaneously. For flow control, the mirroring port will send PAUSE
frames or backpressure signals to the mirrored port. The QoS output port drop function can be enabled by
software on the mirroring port.
8.17. Management Information Base (MIB)
The RTL8316E/RTL8324E MIB (Management Information Base) counters include:
•
RFC2819 – RMON MIB Group 1, 2, 3, 9
•
RFC3635 – Ethernet-like MIB
•
RFC2863 – Interface Group MIB
•
RFC1213 – MIB II
•
RFC4188 – Bridge MIB
•
RFC4363 – Bridge MIB Extension
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8.18. Realtek Cable Tester
The RTL8316E/RTL8324E features the Realtek Cable Tester (RTCT). The Cable Tester function can be
used to detect a short (two conductors of a pair have short-circuited) or open (a lack of continuity between
the pins at each end of the Ethernet cable, or a disconnected cable) in each differential pair, and report the
result in corresponding registers. The RTL8316E/RTL8324E also has an LED to indicate test status and
results.
8.19. EEPROM Configuration
The EEPROM can be divided into two sizes: 4Kb~8Kb and 32Kb~512Kb. Using the small size
EEPROM will reduce the time required to load code, as well as the cost. The address size of the small
size EEPROM is 8 bits, while the larger EEPROM size is 16 bits (addressable space up to 64K). The
small and large size EEPROM address timing waveform is different, and the auto-load size is shown in
the register.
•
Small Size EEPROM: Uses a control byte to define the EEPROM device address. Each block is 8-bit
addressable, and its size is 256*8-bits. A 4Kb EEPROM supports two blocks, and an 8Kb EEPROM
supports four blocks.
•
Large Size EEPROM: Uses a control byte to define a one-block EEPROM device address. This block
is addressable by 12~16 bits (i.e., 4K~64K range), and its size is 4K*8-bits =32Kb, to 64K*8-bits
=512Kb). 32Kb supports 12-bit addresses, and 512Kb supports 16-bit addresses.
The RTL8316E/RTL8324E supports an EEPROM Factory Default Reset function. This function can be
triggered by an input pin or FDR register. In order to prevent mis-operation, the FDR pin reset duration
should be longer than 3 seconds.
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9. Interface Descriptions
9.1. XSMII Interconnection
XSMII (Eight Serial Media Independent Interface) reduces PCB complexity and IC pin count. This
innovative serial interface provides an up to 5 inch MAC to PHY communication path. XSMII can carry
the half/full duplex Megabit Ethernet data streams of eight ports simultaneously, using only 4 pins.
Port 0
Port 1
MAC
PHY
TX
RX
Port 2
Port 3
Port 0
Port 1
Port 2
RS8MII
25MHz
RS8MII
Port 3
Port 4
Port 4
Port 5
Port 5
Port 6
TX
RX
Port 7
Port 6
Port 7
Figure 11. XSMII Interconnection
9.2. I2C-Like LED
The RTL8316E/RTL8324E supports I2C-like LED by connecting with an LED of the RTL8231, which
provides single-color and Bi-color scan LED and extended GPIOs.
When powered on or hardware reset, the RTL8316E/RTL8324E initializes the RTL8231, and then writes
the LED status to it to turn on/off LEDs. The external CPU can also access the RTL8231 to extend GPIOs
via indirect mode.
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9.3. Serial LED Connection
The RTL8316E/RTL8324E has 16/24 MAC ports and supports a serial LED interface to display the link
status. The serial LED interface, LED_SCK and LED_DATA provide clock and data to enable/disable
the external shift registers. A 74HC164 8-Bit Serial-In, Parallel-Out Shift Register captures the per-port
link status and diagnostic information.
LED_ DATA
3.3V
LED_ CLK
A
B
CLK
QA
QB
P24_ LED[1]
QC
P24_ LED[0]
QD
P23_ LED[2]
QE
P23_ LED[1]
QF
P23_ LED[0]
QG
P22_ LED[2]
QH
P22_ LED[1]
74HC164
LED_ DATA
3.3V
LED_ CLK
A
B
CLK
74HC164
LED_ DATA
3.3V
LED_ CLK
P24_ LED[2]
A
B
CLK
74HC164
QA
P22_ LED[0]
QB
P21_ LED[2]
QC
P21_ LED[1]
QD
P21_ LED[0]
QE
P20_ LED[2]
QF
P20_ LED[1]
QG
P20_ LED[0]
QH
P19_ LED[2]
QA
P2_LED[1]
QB
P2_LED[0]
QC
P1_LED[2]
QD
P1_LED[1]
QE
P1_LED[0]
QF
P0_LED[2]
QG
P0_LED[1]
QH
P0_LED[0]
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
Figure 12. Serial LED Connection
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9.4. Scan LED for RTL8316E (Not Supported in the RTL8324E)
In order to reduce the external LED circuits, the RTL8316E supports scan LED mode. It covers 16 port’s
link status with two LEDs, and provides six scan pins and six status pins to display the link status.
Figure 13. Scan LED Mode Connection
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9.5. I2C Master for EEPROM
The EEPROM can be divided into two sizes: 2Kb~8Kb and 32Kb~512Kb. The address of the small size
EEPROM is 8-bits, however the larger EEPROM has word-high addressing and word-low addressing,
and it is 16-bits (two bytes).
Figure 14. Large Size (32Kb~512Kb) EEPROM Read/Write Timing
Figure 15. Small Size (4Kb~8Kb) EEPROM Read/Write Timing
9.6. Serial CPU Interface
The RTL8316E/RTL8324E supports a serial CPU interface (Slave mode) to access the internal register. It
has two I/O pins (i.e., SDA and SCL). SDA is the access data signal, and SCL is the clock signal (typical
clock is 1~2MHz). The read/write data sequence is shown in Figure 16. It consists of a control byte (1
byte) + address bytes (2 bytes) + data bytes (4N pieces, N: integer, N≠0).
When the external CPU wants to read/write data to the RTL8316E/RTL8324E, it must set the read/write
bit (read is 1, and write is 0).
3 ADDRESS BYTES
1 CONTROL BYTE
S
1
0
1
0 A2 A1 A0
A
R/
C
W
K
Addr
[7:0]
A
A
Addr
Addr
C
C
[23:16]
[15:8]
K
K
LSB to MSB
4N DATA BYTES
A
C
K
Data
[7:0]
A
C
K
Data
[15:8]
N
O
A
A
A
Data
Data
C
C
C
[23:16]
[31:24]
K
K
K
P
Read
1 CONTROL BYTE
S
1
0
1
A
R/
0 A2 A1 A0
C
W
K
3 ADDRESS BYTES
Addr
[7:0]
A
A
Addr
Addr
C
C
[23:16]
[15:8]
K
K
LSB to MSB
4N DATA BYTES
A
C
K
Data
[7:0]
A
C
K
Data
[15:8]
A
A
Data
Data
C
C
[23:16]
[31:24]
K
K
A
C
K
P
Write
Figure 16. Serial CPU Interface Access Data Sequence
Layer 2 16-Port & 24-Port 10/100M Switch Controllers
33
Track ID: JATR-8275-15 Rev. 1.0
RTL8316E/RTL8324E
Datasheet
10. Electrical AC/DC Characteristics
10.1. Absolute Maximum Ratings
WARNING: Absolute maximum ratings are limits beyond which permanent damage may be caused to
the device, or device reliability will be affected. All voltages are specified reference to GND unless
otherwise specified.
Table 16. Absolute Maximum Ratings
Parameter
Min
Storage Temperature
-55
DVDD33, AVDD33, AVDD33_XTAL Supply Referenced to GND
GND-0.3
DVDD12, AVDD12, VDD12_PLL, SAVDD12 Supply Referenced to
GND-0.3
GND, GND_PLL, AVSS
Max
+150
+3.63
Units
°C
V
+1.32
V
10.2. Operating Range
Table 17. Recommended Operating Range
Parameter
Min
Ambient Operating Temperature (Ta)
0
DVDD33, AVDD33, AVDD33_XTAL Supply Voltage Range
3.135
DVDD12, AVDD12, VDD12_PLL, SAVDD12 Supply Voltage Range
1.14
Typical
3.3
1.2
Max
70
3.465
1.26
Units
°C
V
V
Typical
-
Max
0.8
0.4
Units
V
V
V
V
10.3. DC Characteristics
Table 18. DC Characteristics
Symbol
VIH
VIL
VOH
VOL
Parameter (VDDIO=3.3V)
TTL Input High Voltage
TTL Input Low Voltage
Output High Voltage
Output Low Voltage
Layer 2 16-Port & 24-Port 10/100M Switch Controllers
Min
2.0
2.4
-
34
Track ID: JATR-8275-15 Rev. 1.0
RTL8316E/RTL8324E
Datasheet
10.4. AC Characteristics
10.4.1. XSMII Transmitter Signal Electrical Characteristics
Table 19. XSMII Transmitter Signal Electrical Characteristics
Parameter
Min
Typical
Differential Peak-to-Peak Output Voltage
0.35
0.4
AC Coupling Capacitor
75
100
Transmit Length in PCB
-
Symbol
VTX-DIFFp-p
CTX
LTX
Max
0.8
200
5
Units
V
nF
Inch
Max
1.0
200
Units
V
nF
10.4.2. XSMII Receiver Signal Electrical Characteristics
Table 20. XSMII Receiver Signal Electrical Characteristics
Parameter
Min
Typical
Differential Peak-to-Peak Input Voltage
0.3
AC Coupling Capacitor
75
100
Symbol
VRX-DIFFp-p
CRX
10.4.3. Serial LED Signal Timing
32ms or 128ms
>600n
s
>600n
s
>600n
s
>600n
s
>600n
s
>600n
s
>600n
s
>600n
s
>600n
s
>600n
s
>600n
s
>600n
s
LED_CLK
1
2
3
4
5
6
73
74
75
1
2
3
LED_DATA
P0_LED0
P0_LED1
P0_LED2
P1_LED0
P1_LED1
P1_LED2
P24_LED1
P24_LED2
P0_LED0
P0_LED1
P0_LED2
P24_LED0
Figure 17. Serial LED Signal Timing
Layer 2 16-Port & 24-Port 10/100M Switch Controllers
35
Track ID: JATR-8275-15 Rev. 1.0
RTL8316E/RTL8324E
Datasheet
10.4.4. Scan LED Mode Signal Timing (RTL8316E)
600 usec
100 usec
LED_ SCAN0
LED_ SCAN1
100 usec
LED_ SCAN2
LED_ SCAN3
LED_ SCAN4
LED_ SCAN5
> 200ns
P0_ LED0
LED_ STA0
LED_ STA1
LED_ STA2
LED_ STA3
LED_ STA4
LED_ STA5
>200ns
P1_ LED0
P2_ LED0
P3_ LED0
P4_ LED0
P5_ LED0
98 usec
P0_ LED1
P6_ LED0
P1_ LED1
P7_ LED0
P2_ LED1
P8_ LED0
P3_ LED1
P4_ LED1
P5_ LED1
P6_ LED1
P7_ LED1
P8_ LED1
P9_ LED0
P9_ LED1
P10_ LED0
P10_ LED1
P11_ LED0
P12_ LED0
P13_ LED0
P14_ LED0
P15_ LED0
P12_ LED1
P13_ LED1
P11_ LED1
P14_ LED1
P15_ LED1
CPU_LED0
CPU_LED1
CPU_LED2
CPU_LED3
P0_ LED0
P1_ LED0
P2_ LED0
P3_ LED0
P4_ LED0
P5_ LED0
P0_ LED1
P1_ LED1
P2_ LED1
P3_ LED1
P4_ LED1
P5_ LED1
Figure 18. Scan LED Mode Signal Timing (RTL8316E)
10.4.5. I2C Master for EEPROM Timing
Figure 19. I2C Master Mode Timing
Layer 2 16-Port & 24-Port 10/100M Switch Controllers
36
Track ID: JATR-8275-15 Rev. 1.0
RTL8316E/RTL8324E
Datasheet
10.4.6. SCK/SDA Power on Timing
Figure 20. SCK/SDA Power on Timing
10.4.7. EEPROM Auto-Load Timing
Figure 21. EEPROM Auto-Load Timing
10.4.8. I2C Master Mode Timing Characteristics
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
Description
Table 21. I2C Master Mode Timing Characteristics
Min
Typical
SCK High Time
SCK Low Time
START Condition Setup Time
START Condition Hold Time
Data In Hold Time
Data In Setup Time
Data Output Hold Time
STOP Condition Setup Time
SCK/SDA Active From Power On
EEPROM Auto-Load Time (8K bit)
Layer 2 16-Port & 24-Port 10/100M Switch Controllers
4.9
4.9
4.9
4.9
0
250
2.4
4.9
97
97
37
5
5
5
5
2.5
5
100
100
Max
Units
2.6
185
185
µs
µs
µs
µs
µs
ns
µs
ms
ms
Track ID: JATR-8275-15 Rev. 1.0
RTL8316E/RTL8324E
Datasheet
10.4.9. Serial CPU Interface Timing
Figure 22. Serial CPU Interface Timing
10.4.10. Serial CPU Interface Timing Characteristics
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
Table 22. Serial CPU Interface Timing Characteristics
Description
Min
Typical
SCK High Time
4.0
SCK Low Time
4.0
START Condition Setup Time
4.0
START Condition Hold Time
4.0
Data Hold Time
0
Data Setup Time
250
Clock to Data Output Delay
9
STOP Condition Setup Time
4.0
-
Max
-
Units
µs
µs
µs
µs
µs
ns
ns
µs
10.5. SMI Timing Characteristics (RTL8324E Only)
Symbol
MDC
MDIO Setup Time
MDIO Hold Time
Table 23. SMI Timing Characteristics (RTL8324E Only)
Parameter
Min
Typical
MDC Clock Rate
548
Write Cycle
10
Write Cycle
10
-
Layer 2 16-Port & 24-Port 10/100M Switch Controllers
38
Max
-
Units
ns
ns
ns
Track ID: JATR-8275-15 Rev. 1.0
RTL8316E/RTL8324E
Datasheet
11. Mechanical Dimensions
Min
Dimension in mm
Nom
Max
Min
Dimension in inch
Nom
Max
A
—
—
1.60
—
—
0.063
A1
0.05
—
0.15
0.002
—
0.006
A2
1.35
1.40
1.45
0.053
0.055
0.057
b
0.17
0.2
0.27
0.007
0.009
0.011
Symbol
D
22.00BSC
0.866BSC
D1
20.00BSC
0.787BSC
D2 / E 2
5.60
6.85
7.50
0.220
0.270
E
16.00BSC
0.630BSC
E1
14.00BSC
0.551BSC
e
0.50BSC
0.020BSC
L
L1
0.45
0.60
0.75
0.018
1.00 REF
0.024
0.295
0.030
0.039 REF
Notes:
1. CONTROLLING DIMENSION: MILLIMETER (mm).
2. REFERENCE DOCUMENT: JEDEC MS-26.
Layer 2 16-Port & 24-Port 10/100M Switch Controllers
39
Track ID: JATR-8275-15 Rev. 1.0
RTL8316E/RTL8324E
Datasheet
12. Ordering Information
Table 24. Ordering Information
Part Number
Package
RTL8316E-CG
LQFP 128-Pin E-PAD ‘Green’ Package
RTL8324E-CG
LQFP 128-Pin E-PAD ‘Green’ Package
Note: See page 7 (RTL8316E-CG) and page 14 (RTL8324E-CG) for package identification.
Status
Production
Production
Realtek Semiconductor Corp.
Headquarters
No. 2, Innovation Road II, Hsinchu Science Park,
Hsinchu 300, Taiwan, R.O.C.
Tel: 886-3-5780211 Fax: 886-3-5776047
www.realtek.com
Layer 2 16-Port & 24-Port 10/100M Switch Controllers
40
Track ID: JATR-8275-15 Rev. 1.0
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