SSD2829QL9

SOLOMON SYSTECH SEMICONDUCTOR TECHNICAL DATA SSD2829 Advance Information MIPI D-PHY Tx Bridge Chip This document contains information on a new product. Specifications and information herein are subject to change without notice. http://www.solomon-systech.com SSD2829 Rev 1.2 P 1/159 Aug 2017 Copyright  2017 Solomon Systech Limited Appendix: IC Revision history of SSD2829 Specification Version 0.10 0.11 0.12 0.13 1.0 1.1 1.2 Change Items st 1 Release 1. Section 5.2 Pin Assignment Table (Draft), pins 109 to 128 were amended 2. Modified operating temperature from 125oC to 85 oC 3. Modified MIPI D-Phy AC and DC Characteristic 4. Added back 8-bit MCU mode 5. Modified pin assignment table 6. Modified MIPI DPHY Lane and Polarity Swap table 7. Added description for compressed stream data 1. Modified max. PCLK value 2. Modified pin assignment table 1. Modified Table of MIPI packet ID 2. Modified AVDD_CDR pin description 3. Updated Command table Updated to Advance Information 1. Removed 30-bit VPT_EXT 2. Change max. of phase difference of channel 0 and 1 from 1 to 2pclk 3. Changed data buffer from 5120 to 4128 4. Change PLL configuration, from 5MHz=0ms XTAL_IN >=1ms Input interface e.g. SPI PLL ON Leave ULP mode >=1ms Sleep out command PEN = 1 SLP = 0 VEN&HS = 1 Video mode ON >=1ms RGB signals Solomon Systech Aug 2017 P 106/159 Rev 1.2 SSD2829 13 POPWER OFF SEQUENCE VDDIO VCIP >=0ms AVDD VDD_CORE >=0ms RESB >=0ms XTAL_IN Video mode OFF Enter ULP mode PLL OFF >=10ms Sleep in command VEN&HS = 0 SLP = 1 PEN = 0 >=0ms RGB signals SSD2829 Rev 1.2 P 107/159 Aug 2017 Solomon Systech 14 MIPI DPHY CHARACTERISTICS Figure 14-1 D-PHY Signaling Levels Figure 14-2 DDR Clock Definition Solomon Systech Aug 2017 P 108/159 Rev 1.2 SSD2829 Table 14-1 : Clock Signal Specification SSD2829 Rev 1.2 P 109/159 Aug 2017 Solomon Systech 14.1 MIPI DPHY HS CHARACTERISTICS Table 14-2 HS Transmitter DC Specifications Table 14-3 HS Transmitter AC Specifications Solomon Systech Aug 2017 P 110/159 Rev 1.2 SSD2829 Table 14-4 LP Transmitter DC Specifications SSD2829 Rev 1.2 P 111/159 Aug 2017 Solomon Systech Table 14-5 LP Transmitter AC Specifications Solomon Systech Aug 2017 P 112/159 Rev 1.2 SSD2829 15 OPERATING MODE 15.1 Programming Model The table below shows the local register map summary in SSD2829. Table 15-1: SSD2829 Local Register Map Command Description 0xB0 – 0xDF Some of the commands would have additional data parameters added to support extension of certain register fields. For example VBP (Vertical back porch) is an 8bit field. With the extension of the number of data parameters, VBP can now become a 16-bit field. The original register fields’ location would be maintained in the first 2 data parameters for back-ward compatibility purpose. Only 2 data parameters would be added. This is the command for APB peripheral access (e.g. SCM) 0xE0 If all 6 data parameters are given, SSD2829 would issue APB write access with the APB_ADDR and APB_DATA. If only 2 data parameters are given, SSD2829 would store the APB_ADDR for read operation. Host can do a data read to read back the APB_DATA. Data Parameter 1 2 3 4 5 6 0xE1 – 0xFE SSD2829 Description APB_ADDR[7:0] APB_ADDR[15:8] APB_DATA[7:0] APB_DATA[15:8] APB_DATA[23:16] APB_DATA[31:24] Reserved Rev 1.2 P 113/159 Aug 2017 Solomon Systech 15.1.1 Access Local (non-APB) Registers The legacy registers (16-bit accessed) are accessed in term of 2 bytes per cycle for all MCU interfaces, except 8-bit format which requires 3 cycles to access (1 command, 2 data cycles) In the first write cycle, only 8-bit data are written into the SSD2829, as the address can only be 8-bit. No matter whether the interface is 8-bit, 16-bit and 24-bit lower 8 bits are used. Please refer to the table below. Interface types 24-bit, 16-bit, 8-bit Data pins D53-D30 D23-D16 D15-D8 D7-D0 Don’t care Don’t care Don’t care Address Table 15-2: MCU Interface Data Pin Mapping for Command Cycle for Legacy Registers In the sub-sequent read or write cycle, the data width is only 16-bit or 2 bytes no matter the interface width is selected, except for 8-bit format. Please refer to the table below. If there are 4 bytes in the legacy registers due to data parameters extension, there will be additional data cycles accordingly. Interface types Cycle 24-bit, 16-bit 8-bit Data pins Note D53-D30 D23-D16 D15-D8 D7-D0 1st Don’t care Don’t care Data Byte 1 Data Byte 0 (1) 2nd Don’t care Don’t care Data Byte 3 Data Byte 2 (2) 1st Don’t care Don’t care Don’t care Data Byte 0 (1) 2nd Don’t care Don’t care Don’t care Data Byte 1 (2) 3rd Don’t care Don’t care Don’t care Data Byte 2 (3) 4th Don’t care Don’t care Don’t care Data Byte 3 Table 15-3: MCU Interface Data Pin Mapping for Legacy Register Note: (1) If the local registers have 4 bytes of data, host can either write 2 bytes or 4 bytes of data. (2) If the local registers have only 2-bytes of data, any extra write will be ignored (3) For 8-bit interface, all writes must be in multiple of 2 cycles Solomon Systech Aug 2017 P 114/159 Rev 1.2 SSD2829 15.1.2 Access Local (APB) Registers for Write The APB peripheral’s registers are accessed by 0xE0. The data content of 0xE0 are 6 bytes and arranged in the order of {addr low, addr high, data0, data1, data2, data3}, where addr low is sent first. In the first write cycle, only 8-bit data are written into the SSD2829, as the address can only be 8-bit. No matter whether the interface is 8-bit, 16-bit and 24-bit, lower 8 bits are used. Please refer to the table below. Interface types 24-bit, 16-bit, 8-bit Data pins D53-D30 D23-D16 D15-D8 Don’t care Don’t care Don’t care D7-D0 0xE0 Table 15-4: MCU Interface Data Pin Mapping for Command Cycle for Extended Registers Write In the sub-sequent write cycle, the data width is only 16-bit or 2 bytes, no matter the interface width is selected, excepted for 8-bit format. Please refer to the table below. Interface types Cycle 24-bit, 16-bit 8-bit Data pins D53-D30 D23-D16 D15-D8 D7-D0 1st Don’t care Don’t care Addr High Addr Low 2nd Don’t care Don’t care Data Byte 1 Data Byte 0 3rd Don’t care Don’t care Data Byte 3 Data Byte 2 1st Don’t care Don’t care Don’t care Addr Low 2nd Don’t care Don’t care Don’t care Addr High 3rd Don’t care Don’t care Don’t care Data Byte 0 4th Don’t care Don’t care Don’t care Data Byte 1 5th Don’t care Don’t care Don’t care Data Byte 2 6th Don’t care Don’t care Don’t care Data Byte 3 Table 15-5: MCU Interface Data Pin Mapping for Extended Registers Write SSD2829 Rev 1.2 P 115/159 Aug 2017 Solomon Systech 15.1.3 Access APB Registers for Read The APB peripheral’s registers are accessed by 0xE0. The content of 0xE0 are 2 bytes and arranged in the order of {addr low, addr high}, where addr low is sent first. In the first write cycle, only 8-bit data are written into the SSD2829, as the address can only be 8-bit. No matter whether the interface is 8-bit, 16-bit or 24-bit, lower 8 bits are used. Please refer to the table below. Interface types 24-bit, 16-bit, 8-bit Data pins D53-D30 D23-D16 D15-D8 Don’t care Don’t care Don’t care D7-D0 0xE0 Table 15-6: MCU Interface Data Pin Mapping for Command Cycle for Extended Registers Read Prior to the read cycles, the host must set the address of the extended registers to be read through write 0xE1. In the sub-sequent write cycle, the data width is only 16-bit or 2 bytes no matter what interface width is selected, except for 8-bit format. Please refer to the table below. Interface types Cycle 24-bit, 16-bit 8-bit Data pins D53-D30 D23-D16 D15-D8 D7-D0 1st Don’t care Don’t care Addr High Addr Low 1st Don’t care Don’t care Don’t care Addr Low 2nd Don’t care Don’t care Don’t care Addr High Table 15-7: MCU Interface Data Pin Mapping for Extended Registers Address Set Solomon Systech Aug 2017 P 116/159 Rev 1.2 SSD2829 For the read cycles, the host read the data in 16-bit or 2 bytes format no matter what interface width is selected except for 8-bit format. Please refer to the table below. Please refer to the table below. Interface types Cycle 24-bit, 16-bit 8-bit Data pins D53-D30 D23-D16 D15-D8 D7-D0 1st Don’t care Don’t care Read Data 1 Read Data 0 nd Don’t care Don’t care Read Data 3 Read Data 2 1 st Don’t care Don’t care Don’t care Read Data 0 2nd Don’t care Don’t care Don’t care Read Data 1 3rd Don’t care Don’t care Don’t care Read Data 2 4th Don’t care Don’t care Don’t care Read Data 3 2 Table 15-8: MCU Interface Data Pin Mapping for Extended Registers Address Set SSD2829 Rev 1.2 P 117/159 Aug 2017 Solomon Systech 15.2 SPI Interface SSD2829 supports three types of SPI interface, 8-Bit 3 wire (type C option 1, DBI 2.0) 8-Bit 4 wire (type C option 3, DBI 2.0) 24-bit 3 wire The selection is controlled by ps[1:0] pins. The least significant byte should be written first 15.2.1 SPI Interface 8-Bit 4 Wire This interface consists of sdc, sck, sdin, sdout and csx. It only supports 8-Bit data. Each cycle contains 8-Bit data. The first cycle should be a command write cycle to specify the register address for access. The subsequent cycles are read or write cycles for read or write operations. The csx should be driven from 1 to 0 to start an operation and from 0 to 1 to end an operation. During 1 operation, the application processor can write or read multiple bytes. sdcx indicates whether the operation is for data or command. When sdcx is 1, the operation is for data. When sdcx is 0, the operation is for command. sdcx is sampled at every 8 th rising edge of sck during 1 operation. During write operation, sdin will be sampled by SSD2829 at the rising edge of sck. The first rising edge of sck after the falling edge of csx samples the bit 7 of the 8-Bit data. The second rising edge of sck samples the bit 6 of the 8-Bit data, and so on. The value of sdcx is sampled at the 8th rising edge of sck, together with bit 0 of the 8-Bit data. Please see the diagram below for illustration. Optionally, the csx can be driven to 1 in between cycles. Figure 15-1: SPI Interface 8-bit 4 wire for write Solomon Systech Aug 2017 P 118/159 Rev 1.2 SSD2829 Figure 15-2: SPI Interface 8-bit 4 wire for read SSD2829 Rev 1.2 P 119/159 Aug 2017 Solomon Systech 15.2.2 SPI Interface 8-Bit 3 Wire This interface consists of sck, sdin, sdout and csx. It only supports 8-Bit data. Each cycle contains 8-Bit data. The first cycle should be a write cycle to specify the register address for access. The subsequent cycles are read or write cycles for read or write operations. The csx should be driven from 1 to 0 to start an operation and from 0 to 1 to end an operation. During 1 operation, the application processor can write or read multiple bytes. Instead of sdcx, an sdcx bit is used to indicate whether the operation is for data or command. Each byte is associated with an sdcx bit. When sdcx is 1, the operation is for display data. When sdcx is 0, the operation is for command. The sdcx bit is sent priori to each byte. In other words, the sdcx bit is the first bit of every 9 bits during 1 operation. During write operation, sdin will be sampled by SSD2829 at the rising edge of sck. The first rising edge of sck after the falling edge of csx samples the sdcx bit. The second rising edge samples bit 7 of the 8-Bit data. The third rising edge of sck samples the bit 6 of the 8-Bit data, and so on. Please see the diagram below for illustration. Optionally, the csx can be driven to 1 in between cycles. Figure 15-3: SPI Interface 8-bit 3 wire for write Solomon Systech Aug 2017 P 120/159 Rev 1.2 SSD2829 Figure 15-4: SPI Interface 8-bit 3 wire for read SSD2829 Rev 1.2 P 121/159 Aug 2017 Solomon Systech 15.2.3 SPI Interface 24-Bit 3 Wire This interface consists of sck, sdin, sdout and csx. It only supports 16-bit data. Each cycle contains 16-bit data. The first cycle should be a write cycle to specify the register address for access. The subsequent cycles are read or write cycles for read or write operations. The csx should be driven from 1 to 0 to start cycle and from 0 to 1 to end a cycle. During 1 operation, the application processor can have multiple write or read cycles. However, the csx must go from 0 to 1 at the end of each cycle. Each cycle contains 24-bit data. Among the 24-bit data, the first 8-Bit are for control purpose and the next 16bit are the actual data. The first 6 bits are the ID bit for SSD2829, which must be 011100. If this field does not match, the cycle will not be taken in. The 7th bit is the sdcx bit which is the same as the 8-Bit 3 wire interface. The 8th bit is the RW bit which indicates whether the current cycle is a read or write cycle. When RW is 1, the cycle is a read cycle. When RW is 0, the cycle is a write cycle. Figure 15-5: SPI Interface 24-bit 3 wire for write Solomon Systech Aug 2017 P 122/159 Rev 1.2 SSD2829 Figure 15-6: SPI Interface 24-bit 3 wire for read SSD2829 Rev 1.2 P 123/159 Aug 2017 Solomon Systech 15.3 MCU Interface The SSD2829 supports three types of MCU interface, Type A, fixed E mode, DBI 2.0 Type A, clocked E mode, DBI 2.0 Type B, DBI 2.0 The selection is controlled by ps[4:2] pins. PS[4:2] is for the MCU interface  000: 8-Bit MCU interface (MIPI DBI type B)  001: 16-bit MCU interface (MIPI DBI type B)  010: 8-Bit MCU interface (MIPI DBI type A, fixed E or clocked E mode)  011: 16-bit MCU interface (MIPI DBI type A, fixed E or clocked E mode)  100: 24-bit MCU interface (MIPI DBI type B)  110: 24-bit MCU interface (MIPI DBI type A, fixed E or clocked E mode)  101: Reserved  111: Reserved MCU interfaces support 8-bit, 16-bit and 24-bit data bus. Below are the data pins used for each interface. For 8-Bit interface, the least significant byte should be written first. For 16 or 24-bit interfaces, the lease significant word should be written first.   data[15:0] for 16-bit interface data[23:0] for 24-bit interface The local registers are always accessed in 16-bit data word for the data phase of the MCU cycle, irrespective of any bus width selection. 15.3.1 MCU Interface Type A, fixed E mode This interface consists of data, rwx, dcx, e and csx. It supports 24-bit, 16-bit and 8-bit data bus. The first cycle should be a command write cycle to specify the register address for access. The subsequent cycles are read or write cycles for read or write operations. ‘e’ signal should be driven to 1 in this mode. rwx indicates whether the operation is a read or a write operation. When rwx is 1, the operation is a read operation. When rwx is 0, the operation is a write operation. During write operation, dcx indicates whether the operation is for data or command. When dcx is 1, the operation is for data. When dcx is 0, the operation is for command. During the read operation, the dcx should be 1. During the write operation, data are sampled at the rising edge of csx. During read operation, data are provided at the falling edge of csx and the application processor should use the rising edge of csx to sample. Solomon Systech Aug 2017 P 124/159 Rev 1.2 SSD2829 Figure 15-7: Illustration of Write Operation for Type A, Fixed E Mode Interface Figure 15-8: Illustration of Read Operation for Type A, Fixed E Mode Interface SSD2829 Rev 1.2 P 125/159 Aug 2017 Solomon Systech 15.3.2 MCU Interface Type A, Clocked E mode This interface consists of data, rwx, dcx, e and csx. It supports 24-bit, 16-bit and 8-bit data bus. The first cycle should be a command write cycle to specify the register address for access. The subsequent cycles are read or write cycles for read or write operations. csx should be driven to 0 in this mode. rwx indicates whether the operation is a read or a write operation. When rwx is 0, the operation is a write operation. When rwx is 1, the operation is a read operation. During write operation, dcx indicates whether the operation is for data or command. When dcx is 1, the operation is for data. When dcx is 0, the operation is for command. During the read operation, the dcx should be 1. During the write operation, data are sampled at the falling edge of E. During read operation, data[23:0] are provided at the rising edge of e and the application processor should use the falling edge of e to sample. Below is a diagram for illustration. Figure 15-9: Illustration of Write Operation for Type A, Clocked E Mode Interface Solomon Systech Aug 2017 P 126/159 Rev 1.2 SSD2829 Figure 15-10: Illustration of Read Operation for Type A, Clocked E Mode Interface SSD2829 Rev 1.2 P 127/159 Aug 2017 Solomon Systech 15.3.3 MCU Interface Type B This interface consists of data, rdx, wrx, dcx, and csx. It supports 24-bit,16-bit and 8-bit data bus. The first cycle should be a command write cycle to specify the register address for access. The subsequent cycles are read or write cycles for read or write operations. csx should be driven to 0 in this mode. When wrx is driven from 1 to 0 and 0 to 1, the operation is a write operation. When rdx is driven from 1 to 0 and 0 to 1, the operation is a read operation. During write operation, dcx indicates whether the operation is for data or command. When dcx is 1, the operation is for data. When dcx is 0, the operation is for command. During the read operation, the dcx should be 1. During the write operation, data are sampled at the rising edge of wrx. During read operation, data[23:0] are provided at the falling edge of rdx and the application processor should use the rising edge of rdx to sample. Below is a diagram for illustration. Figure 15-11: Illustration of Write Operation for Type B Interface Solomon Systech Aug 2017 P 128/159 Rev 1.2 SSD2829 Figure 15-12: Illustration of Read Operation for Type B Interface SSD2829 Rev 1.2 P 129/159 Aug 2017 Solomon Systech 15.3.4 MCU Interface for MIPI Command Packet Any write to the address ranges from 0x00 to 0xAF will be sent out as MIPI command packet. The type of packet, whether it is short or long packet, DCS or generic packet is determined by the SSD2829 local registers. Hence the user should program the local registers prior to any transmission at the MIPI link. If the host wants to send any addresses in the range of 0xB1 to 0xFF to external MIPI receiver, it can do so using packet drop command in the 0xBF register. In the first write cycle, only 8-Bit data are written into the SSD2829, as the command can only be 8-Bit. No matter whether the interface is 8-bit, 16-bit or 24-bit, lower 8-bits are used. Please refer to the table below. Interface types Data pins D53-D30 D23-D16 D15-D8 D7-D0 24-bit Don’t care Don’t care Don’t care Command 16-bit Don’t care Don’t care Don’t care Command 8-bit Don’t care Don’t care Don’t care Command Table 15-9: MCU Interface Data Pin Mapping for Command Cycle Solomon Systech Aug 2017 P 130/159 Rev 1.2 SSD2829 In the sub-sequent read or write cycles, command parameters can be written into the SSD2829. Depending on the interface width, different data pin mapping is adopted. Please refer to the table below. When the number of parameters is not an integer of the width of the interface type, the remaining bytes should be put on the lower data buses at the last data cycle. Interface types Cycle 24-bit 16-bit 8-Bit Data pins D53-D30 D23-D16 D15-D8 D7-D0 1st Don’t care Parameter 3 Parameter 2 Parameter 1 2nd Don’t care Parameter 6 Parameter 5 Parameter 4 3rd Don’t care Parameter 9 Parameter 8 Parameter 7 1st Don’t care Don’t care Parameter 2 Parameter 1 2nd Don’t care Don’t care Parameter 4 Parameter 3 3rd Don’t care Don’t care Parameter 6 Parameter 5 1st Don’t care Don’t care Don’t care Parameter 1 2nd Don’t care Don’t care Don’t care Parameter 2 3rd Don’t care Don’t care Don’t care Parameter 3 Table 15-10: MCU Interface Data Pin Mapping for Parameter Cycles 15.3.5 MCU Interface for Local Registers The local registers for SSD2829 resided in the range from 0xB1 to 0xFF. There are 2 types of local registers, legacy registers and extended registers. To expand certain field in the legacy registers, the data bits in that address is extended to 32-bit, or 4-bytes width from 2-bytes. The extended registers can be accessed by indirect addressing through the address location 0xE0. The content of 0xE0 defines the 16-bits addresses and 32-bits data for the extended registers. SSD2829 Rev 1.2 P 131/159 Aug 2017 Solomon Systech 15.4 RGB Interface SSD2829 supports RGB interface. The input is 48-bit wide and it supports 2-pixels per RGB module using SDR or DDR input pixel clock. To support different bpp settings, the following data pins are used. For all cases, Red component should be at the upper bits and Blue component should be at the lower bits. The type of video packets supported for each RGB interface is shown below. Data Bus RGB format [15:0] 16-bits per pixel for Pixel 1 [45:30] [17:0] 16-bits per pixel for Pixel 2 18 bits per pixel for Pixel 1 [47:30] 18 bits per pixel for Pixel 2 [23:0] 24-bits per pixel for Pixel 1 [53:30] 24-bits per pixel for Pixel 2 [23:0] Compressed Stream Data(lower) [53:30] Compressed Stream Data(Upper) User can also send command mode data through SPI interface, during the video mode transmission. The data will be sent during the horizontal or vertical blanking period. Since the RGB and SPI interface are completely separated, the two interfaces can operate independently. The RGB interface is used to provide display data for the video mode. The SPI interface is used to program the local registers of SSD2829, or to send command across the link to the MIPI receiver. 2 supporting data type for compressed stream data:  Compressed data - PPS (DT=0xA)  Compression Mode (DT=0x7) There is a register to be set if incoming MCU command bytes are to be packed as PPS, or Compression-Mode packet. All the parameters are carried in the PPS packet data, as defined by VESA standard. 15.5 Video Mode Use Cases 15.5.1 RGB + SPI For this mode, the user must set if_sel[1:0] to “00” to select the interface as a combination of RGB and SPI interface. The video data come from the RGB interface and the configuration is done through the SPI interface. The possible video paths (and non-video command paths) supported in this mode are shown below. The SPI interface can be used to program local registers or transmit command packets during video blanking to MIPI output. Solomon Systech Aug 2017 P 132/159 Rev 1.2 SSD2829 RGB Interface Input, Single MIPI Video Output RGB Interface 0 MIPI DPHY TX 0 SSD2829 SPI Interface Local registers RGB Interface Input, Dual MIPI Video Output This is either a split use case or a broadcast use case. For split use case, it can be either odd/even pixel split, or left/right image split RGB Interface 0 MIPI DPHY TX 0 SSD2829 MIPI DPHY TX 1 SPI Interface SSD2829 Rev 1.2 Local registers P 133/159 Aug 2017 Solomon Systech The user, first, needs to set the video parameters through registers programming with correct values. After programming those register fields, the user can turn on the RGB interface and enable the SSD2829 to start transmission. All three video mode sequence defined in the MIPI DSI specification are supported. The PLL multiplication factor should be set such that the serial link data rate is faster than the incoming data rate. Please refer to the table below for the PLL settings. Below is the diagram to illustrate the definition of all the fields. HSA Hsync DEN HACT HBP HFP Pclk MIPI_Data[23:0] VSA Vsync VACT VBP VFP Hsync Figure 15-13: Illustration of RGB Interface Parameters for Non-burst Mode with Sync Pulses Hsync DEN HACT HBP HFP Pclk MIPI_Data[23:0] Vsync VBP VACT VFP Hsync Figure 15-14: Illustration of RGB Interface Parameters for Non-burst Mode with Sync Events and Burst Mode Solomon Systech Aug 2017 P 134/159 Rev 1.2 SSD2829 15.5.1.1 Interleaving Non-Video Packets with Video Packets Non-video data can be transmitted during the vertical blanking of the video frames, or when nvb (in 0xB6 register) is set, during any BLLP period (including those in the horizontal blanking). It is recommended to send non-video data during vertical blanking. The nvd and bllp field (in 0xB6 command) determines how the non-video data is sent. See below table for illustration. NVD BLLP 0 0 Non-burst mode If there is no non-video data to send, the serial link will send blanking packet in HS mode during BLLP period. If there is non-video data to send, the non-video data will be sent in HS mode. Afterwards, the serial link will send blanking packet in HS mode for the remaining period of BLLP period. 0 1 If there is no non-video data to send, the serial link will enter LP mode during BLLP period. Burst mode If there is no non-video data to send, the serial link will enter LP mode during BLLP period. If there is non-video data to send, non-video data will be sent in HS mode. Afterwards, the serial link will enter LP mode for the remaining period of BLLP period. Same as non-burst mode. If there is non-video data to send, non-video data will be sent in HS mode. Afterwards, the serial link will enter LP mode for the remaining period of BLLP period. 1 SSD2829 x The serial link will enter LP mode for BLLP mode. If there is nonvideo data to send, the data will be sent in LP mode at the beginning of BLLP period. Rev 1.2 P 135/159 Aug 2017 Same as non-burst mode. Solomon Systech 15.5.2 Interrupt Operation An interrupt signal int has been provided to interrupt the application processor so that it does not need to poll the status all the time. This will save the processing time of the application processor. int can be programmed to active high or active low, when the event has happened. There are many sources that can be mapped to the interrupt signal. The user can select different source to perform different task. If more than 1 source is selected, the int signal will be asserted when the event for 1 of the sources has happened. In this case, the user needs to read the register ISR to determine what event has happened. The different sources can be enabled/disabled through register ICR. Below is the list of available interrupt sources and their usage. RDR To indicate that return data from one of the MIPI slave is available for read. BTAR To indicate whether the SSD2829 has the bus authority or not. It can be used after SSD2829 makes a BTA. If the MIPI slave has returned the bus authority back to SSD2829, the interrupt will be set to indicate so. Please note that, on power up, the bus authority is already on the SSD2829. Hence, the SSD2829 will show that it has the bus authority. ARR To indicate whether the SSD2829 has received the acknowledge response from the MIPI slave. The acknowledge response can either report error or not error. This is to be determined by the ATR bit. The above three interrupts are provided to the user to handle reading data from the MIPI slave or getting acknowledgement response from the MIPI slave. PLS To indicate whether the PLL has been locked or not. If the PLL is not locked, the programming speed at the external interface must be slow. After changing the PLL setting or changing the reference clock source, the user also needs to use this interrupt to determine the PLL status. On power up, only PLS interrupt is enabled. This is to let the user determine the programming speed before configuring the SSD2829. LPTO To indicate that there is LP RX time out. HSTO To indicate that there is HS TX time out. The above two interrupts are provided to the user for error handling. PO To indicate whether the SSD2829 is ready to accept any data from the user. The SSD2829 has several internal buffers to hold the data written by the user. When the user writes after than the serial link speed, those buffers will be full. If the user still writes data to SSD2829, those data will be lost. The length of the payload of the next packet that the user is going to write is determined by TDC, PST, and DCS fields. The SSD2829 will use these fields to decide whether the user can write the next packet or not. Hence, after programming the above mentioned fields, the user needs to check the interrupt status before writing. CBE, CBA, MLE, MLA All these interrupts (CBE = command buffer empty, CBA = command buffer available, MLE = MCU line buffer empty, MLA = MCU line buffer available) are provided to indicate the status of the internal data Solomon Systech Aug 2017 P 136/159 Rev 1.2 SSD2829 buffers. They are used if the user is familiar with the buffer management of the SSD2829. Otherwise, it is recommended to use the PO interrupt. One important thing to note is the interrupt latency. The output interrupt signal does not change immediately after an operation. This is due to the internal processing of the SSD2829. For example, after changing the interrupt source from one to another, the output int level will remain at the old level for a short period after the programming is done. Another example is that after programming the TDC field, the interrupt will take a short period to reflect the correct PO status on int. There is always a delay between the actual event and the interrupt. In order to guarantee that the user can get the correct interrupt, it is recommended that the user performs a read of any SSD2829 local register before taking in the interrupt signal or polling the interrupt status bits. The read operation will cover the interrupt latency period. Alternatively, the user can wait for certain amount of time to make sure the interrupt reflects the true status. Below is a diagram for illustration. Start of read operation Interrupt reflects true status Event happens End of read operation int Time SSD2829 Rev 1.2 P 137/159 Aug 2017 Solomon Systech 15.5.3 Internal Buffer Status There are 2 types of buffers inside the SSD2829, which are MCU interface line buffer (ML) and MCU/SPI command interface buffer (CB). The ML buffers are used to store the data (DCS command 0x2C and 0x3C) written through MCU interface when the if_sel is ‘01’. They are also used to store the video data written through RGB interface when the if_sel is ‘00’. However, since there is no flow control for the RGB interface video packets, the status is only valid for MCU interface. For CB buffers, all command packets will be stored into them. They can store multiple packets, up to 4096 bytes in total. Below is a list of possible packets  Generic Short Write Packet  Generic Read Packet  DCS Short Write Packet  DCS Read Packet  Generic Long Write Packet  DCS Long Write Packet In case of automatic partitioning, the packet length is determined by the PST field. It is not recommended to make the PST field so small. When the if_sel is “00”, the user can write the data through SPI interface. All packets will be written into the CB buffers. Hence, the user needs to check the corresponding interrupts. The usage of the interrupts is listed below. CBE To indicate that the Command buffer is empty. CBA To indicate that the Command buffer can hold at least 1 more packet. The user can write 1 such packet into CB buffer. MLE To indicate that MCU Long buffer is empty. Since the ML buffer can hold 2 packets, the user can write up to 2 such packets into ML buffer without needing to look at the interrupt status. MLA To indicate that the MCU Long buffer can hold at least 1 more packet. The user can write 1 such packet into ML buffer. The interrupts mentioned here can be used as flow control between the application processor and the SSD2829. However, it requires the user to know the buffer operation well. The PO interrupt is a combination of the eight. It makes decision according to the parameters provided by the user for the next packet to be written. Hence, the user does not need to know which buffer is going to be used and how the buffer status is. Solomon Systech Aug 2017 P 138/159 Rev 1.2 SSD2829 15.6 Command Mode Use Cases MCU interface supports 8-bit, 16-bit and 24-bit data bus. To support different bus width, the following data pins of each MCU interface are used.  data[7:0] for 8-bit interface.  data[15:0] for 16-bit interface.  data[23:0] for 24-bit interface. The address range for the SSD2829 local register is from 0xB1 to 0xFF. The user can access the registers in this range to configure and control the SSD2829. For Generic packet that starts from 0xB1 to 0xFF, it can be written through the Packet Drop register. When the user writes data to it, the data will be sent over the serial link to the MIPI slave. The data packet sent will either be DCS or generic packet. The following command mode use cases are possible: SSD2829 Rev 1.2 P 139/159 Aug 2017 Solomon Systech MCU Input, Single MIPI Command/Video Output To select MCU(s) input, if_sel[1:0] needs to “01”. MCU-0 MIPI DPHY TX 0 SSD2829 Local registers MCU Input, Dual MIPI Command Output This is a broadcast use case. To select MCU(s) input, if_sel[1:0] needs to “01”. MCU-0 MIPI DPHY TX 0 SSD2829 MIPI DPHY TX 1 Local registers Solomon Systech Aug 2017 P 140/159 Rev 1.2 SSD2829 15.6.1 Write Operation The SSD2829 can issue four kinds of packets for write operation, which are Generic Short Write Packet, Generic Long Write Packet, DCS Short Write Packet and DCS Long Write Packet. The VC ID of the outgoing packets can also be programmed through registers. The SSD2829 needs to know the payload size of the outgoing packets. Hence, the user needs to program the corresponding control registers prior to sending the MIPI data. To send a DCS or Generic Write Packet in address 0xB1 to 0xFF, the user needs to write the command/header and the payload to the Packet Data Drop register. If the size field is no more than 2 for Generic packet and 1 for DCS packet, the SSD2829 will send out DCS or Generic Short Write Packet with the correct type. Otherwise, DCS or Generic Long Write Packet will be sent out. For DCS Write Packet, partition is supported for 0x2C or 0x3C DCS command. This is because the DCS command 0x2C and 0x3C are to write display data into the LCD panel display memory. The payload will be partitioned into a few packets where the payload of each packet is determined by the Partition register. The first byte is the DCS command and the following partition bytes are the payload. Only the last packet might contain less payload, as the total payload might not be integer multiple of partition size. If the incoming DCS command is 0x2C, the DCS command for the first packet is 0x2C and the DCS command for all other packets is 0x3C. If the incoming DCS command is 0x3C, the DCS command of all the packets is 0x3C. For example, if the byte size field is 200 and partition field is 80, 3 packets will be sent. The first two have 80 bytes of payload. The last packet has 40 bytes of payload. After performing a write operation, the user can optionally make a BTA to let the MIPI slave report its status. The SSD2829 will automatically make a BTA after each write operation. SSD2829 Rev 1.2 P 141/159 Aug 2017 Solomon Systech 15.6.2 Read Operation The SSD2829 can issue two kinds of packets for read operation, which are Generic Read Packet, and DCS Read Packet. The bit DCS controls whether Generic Read Packet or DCS Read Packet will be sent out. The VC ID of the outgoing packets can also be programmed through registers. Before the read packet is sent out, the SSD2829 will always send out the Set Maximum Return Size Packet. This is to limit the Read Response Packet sent by the MIPI slave such that there is no over flow. Two factors determine the maximum size. One is the limit of the SSD2829 and the other is the limit of the application processor. The user should choose the smaller one among these two limits to use as the maximum return size. The parameter in the Set Maximum Return Size Packet is taken from local register. The user could program the Set Maximum Return Size Register before every read so that the correct value is sent through Set Maximum Return Size Packet. If the value is already the desired value, the user can choose not to program it. SSD2829 will always automatically send out Set Maximum Return Size Packet before the Read Packet. To send a DCS Read or Generic Read Packet, the user just needs to write the DCS (as there is no parameter for DCS read) or Generic command, or write to Packet Drop Data register when the address is from 0xB1 to 0xFF. Similar to the write operation, the Total Data Count Register field is used to determine the payload size of the outgoing packet. For DCS Read Packet, the payload is just the DCS command. There is no parameter associated. For Generic Read Packet, the SSD2829 will send out the correct packet type according to the Total Data Count value. After sending out the read packet, the SSD2829 will automatically perform a BTA to wait for the Read Response Packet from the MIPI slave. The return data will be stored in a data register. No matter what read packet is sent out, there is only one packet returning data. Therefore, no matter whether the read is DCS read or Generic read, no matter what command is used in DCS read, the return data is always stored in the same data register. The user can read the data out when the read valid status bit is set to 1. After seeing read valid status bit been set to 1, the user should first check the number of bytes returned by the MIPI slave. By using this information, the user will know how many data should be read out from data register. After all the return data are read out, the read valid status bit will be set to 0 by the SSD2829. Even the read valid status bit is set to 1, the user can choose not to read the data out from data register. The user can continue performing another operation. Once the user does so, the read valid status bit will be set to 0 by the SSD2829. There might be Acknowledge and Error Report Packet sent by the MIPI slave at the same time. Under certain circumstance, the MIPI slave might only send back Acknowledge and Error Report Packet without any data. Thus, the read valid status bit will not be set. Therefore, it is recommended that the user check the bus turnaround bit first. The bus turnaround bit is to indicate whether the MIPI slave has passed the bus authority back to the SSD2829 or not. Only when the bus turnaround is 1, there might be return data. If there is no return data, the user should follow Acknowledgement Operation to handle the acknowledgement. Solomon Systech Aug 2017 P 142/159 Rev 1.2 SSD2829 15.7 Video to Command Mode conversion The MIPI TX output of SSD2830 can convert video packets to command mode packets (i.e. 0x2C command for the first video line, and 0x3C commands for the subsequent video lines). SSD2829 Rev 1.2 P 143/159 Aug 2017 Solomon Systech 15.7.1 Example of switching sequence Note: For this feature, it is important to note that once Video-to-Command mode is turned on, the MIPI would be in HS link when there is active video input. It would remain in HS link until the mode is turned off. Since there is a HS timeout built-in SSD2830, user is recommended to switch off Video-to-command mode periodically (e.g. after a 2-3 frames of conversion) 15.8 State machine operation The state machine controls the sending and receiving of the data packet over the serial link. It is triggered by an event from the application processor or the received data. Once a complete packet is written into the SSD2829 buffer, it will send it out through the serial link. The user can write 1 to bit COP (cancel-operation) at any time to cancel all the current operations. When the SSD2829 is in high speed mode, the serial link is mainly used to send display data. If there is no data to send, it will send null packet to maintain the serial link timing. If the application processor does not have display data to send in a long period, it can turn the serial link into low power mode by setting the register bit HS to 0. When the SSD2829 is in low power mode, the serial link is mainly used to send command and configuration data. If there are no data to be sent, the SSD2829 will be idle in LP TX stop mode. The user can also enter sleep mode by writing 1 to SLP bit. Once the SLP bit is set to 1, the SSD2829 will automatically enter LP mode. If the HS bit is 1, the SSD2829 will clear the HS bit to 0 and switch from HS to LP mode. Afterwards, the SSD2829 will issue ULPS trigger message to the MIPI slave to enter Ultra Low Power State. During this state, the clock to SSD2829 can be switched off such that the SSD2829 only consumes leakage current. This will save the overall system power consumption. When exiting from the ULPS, the user can write 0 to SLP bit. However, the user should be aware that the time to exit from ULPS is relatively long. Hence, the user cannot perform any data transmission before the system exits from ULPS.64 Solomon Systech Aug 2017 P 144/159 Rev 1.2 SSD2829 During reception, the state machine will disassemble the incoming data packet and put the received register content into the internal buffer for reading out. Once all the data are put into the buffers, it will set the register bit RDY to 1 to indicate that the SSD2829 is ready for read. The total number of received bytes will also be stored in RDCR. After the reception is completed, the SSD2829 will perform a bus turn around to enter the transmission mode. It will always come back to the LP TX stop mode before it enters any other 15.9 PHY controller Operation PHY-controller controls the operation of the analog transceiver. It controls whether the serial link is in high speed or low power mode and whether it’s in transmit or receive mode. In transmit mode, the PHY controller will perform the handshaking procedure when switching between LP mode and HS mode according to the control from PCU. During HS mode, PHY controller will provide parallel data and clock to the analog transmitter for transmitting in differential signals serially. During LP mode, the PHY controller will provide the serial data to the analog transmitter. In receive mode, the PHY controller will detect the handshaking sequence in LP mode and inform the PCU. Once entering escape mode, it will collect the serial data from analog receiver and put them in parallel form for the PCU to process. Various timing parameter has been defined in MIPI DPHY specification. The timing parameters are a mixture of absolute time and cycle counts. Hence, for different operation speed, there is different timing requirement. The user can adjust the value in these registers to have different DPHY timing parameters. This gives maximum flexibility for different operation speed. 15.10 PLL Configuration The PLL output frequency is calculated by the equations below, f IN MS  f PRE * NS f PRE  f OUT where the f IN is the input reference clock frequency and f OUT is the output clock frequency of the PLL. The clock frequencies need to satisfy the constraint below. 5𝑀𝐻𝑧 < 𝑓𝐼𝑁 ≤ 40𝑀𝐻𝑧 5𝑀𝐻𝑧 < 𝑓𝑅𝐸𝐹 ≤ 100𝑀𝐻𝑧 62.5𝑀𝐻𝑧 < 𝑓𝑂𝑈𝑇 ≤ 1250𝑀𝐻𝑧 The value of FR, MS, and NS are controlled in the register PLCR. All the values of FR, MS and NS can only be modified when the PLL is turned off (PEN=0). Hence, the sequence for modification is to turn off PLL, modify register value, and turn on PLL. SSD2829 Rev 1.2 P 145/159 Aug 2017 Solomon Systech 15.11 Clock Source Example Pin XTAL_OUT Connection Open Solution 2 Solomon Systech Aug 2017 P 146/159 Rev 1.2 SSD2829 15.12 Acknowledgement Operation The SSD2829 can perform a BTA to give the bus authority to the MIPI slave and let it report its status. The BTA can be enabled by setting FBW bit to 1 and performing a write operation, or just performing a read operation. After the MIPI slave passes the bus authority back, the SDD2829 will set bit BTAR to 1. If there is no error on the slave side, the MIPI slave will return ACK trigger message, if the packet before BTA is a write packet. The MIPI slave will return Read Response Packet, if the packet before BTA is a read packet. In this case, after receiving the response from the MIPI slave, SSD2829 will set bit ARR and ATR bits to 1. ARR indicates that response has been received from MIPI slave. ATR indicates that the MIPI slave has reported no error with ACK trigger message. Consequently, the register ARSR will be cleared to 0. If there is error on the slave side, the MIPI slave will return Acknowledge and Error Report packet, if the packet before BTA is a write packet. The MIPI slave will return Read Response Packet (depending on the error type) and Acknowledge and Error Report Packet, if the packet before BTA is a read packet. In this case, after receiving the response from the MIPI slave, SSD2829 will set bit ARR bit to 1 and ATR bits to 0. ARR indicates that response has been received from MIPI slave. ATR indicates that the MIPI slave has sent Acknowledge and Error Report Packet instead of ACK trigger message. Therefore, the MIPI slave has reported error. The error reported by the MIPI slave will be stored in register ARSR. The user can read this register to see what error the MIPI slave has encountered. For the detailed description of each error bit, please refer to MIPI DSI specification. Below are the flow charts of handling the MIPI slave acknowledgement. They are just for reference. N BTAR == 1? Y ARR == 1? N Error! No Acknowledgement N Handle Slave Error Report Y ATR == 1? Y Slave has no error. Proceed SSD2829 Rev 1.2 P 147/159 Aug 2017 Solomon Systech N BTAR == 1? Y ARR == 1? N Error! No Acknowledgement N Handle Slave Error Report Y Slave has no error. Proceed RDR == 1? Y ATR == 1? Y N Correctable? Y N Y RDR == 1? N Read return data and Proceed Solomon Systech Error! No return data Error! Extra return data Proceed Aug 2017 P 148/159 Rev 1.2 SSD2829 15.13 Tearing Effect (TE) Operation 15.13.1Using IO Pins SSD2829 takes 1 TE_in pin, reshape them and output them to 1 TE_out pin. The programmable parameters are the pulse width, polarity, and delay. TE_out _0 Application Processor Pulse Modifier TE_in_ 0 Display Driver SSD2829 SSD2829 Rev 1.2 P 149/159 Aug 2017 Solomon Systech 15.13.2Using MIPI Escape Mode The TE operation is to perform a BTA following the previous BTA without transmitting anything in between. The bus is handed to the MIPI slave for providing TE information. After getting the TE event from display driver, the MIPI slave will pass the bus authority back to the SSD2829 by using BTA trigger message. The TE operation can be enabled by setting bit FBT and FBW to 1 before writing the last command to the MIPI slave. Afterwards, the application processor can instruct the SSD2829 to send out the last command in a write packet. Since FBW is 1, the SSD2829 will automatically perform a BTA after the write operation. The MIPI slave will response and pass the bus authority back. Since FBT is 1, the SSD2829 will perform another BTA without sending any data. This makes the MIPI slave enter TE mode. The MIPI slave will send a TE trigger message back when it gets the TE event. After getting the trigger message, the SSD2829 will set the TE pin to 1 to indicate that TE event has been received. At the same time, bit TER will be set to 1. The application processor can write 1 to this bit to clear it. As the TE trigger message only determines when the TE pin will be set to 1, a counter is used to determine when to set the TE pin to 0. The TE pin will be set to 0, once the counter reaches the value in TEC. The counter uses the reference clock to do counting. If the MIPI slave does not send back the TE trigger message but just perform a BTA to pass the bus back, the SSD2829 will automatically perform another BTA to pass the bus to the MIPI slave again. It will continue do so until the MIPI slave respond with the TE trigger message, or the FBT bit is set to 0, or the LP RX timer expires. If the MIPI slave does not send back the TE trigger message and still holds the bus, the user can set the bit FBC to 1 to force a bus contention. After bus contention is resolved, the slave will pass the bus back to SSD2829. SSD2829 supports dual MIPI TX port. Hence there would be 2 TE outputs accordingly. 15.14 Contention Detection and Timer Operation Two timers have been defined in SSD2829 to resolve the potential contention issue on the bus. The two timers are the HS TX timer and LP RX timer. Please see the register description for the detailed usage. Whenever the SSD2829 sees a contention being detected, it will reset the state machine and enter the default mode, which is LP TX idle mode. The data line will be kept at LP11. Solomon Systech Aug 2017 P 150/159 Rev 1.2 SSD2829 15.15 Video BIST SSD2829 supports the following pattern generation for video BIST. Parameter Required: 17 bytes Offset 0 7 6 5 3 2 vb_repeat_cnt_h vb_repeat_cnt_l vb_r1 vb_g1 vb_b1 vb_r2 vb_g2 vb_g2 vb_x_start_h vb_x_start_l vb_x_end_h vb_x_end_l vb_y_start_h vb_y_start_l vb_y_end_h vb_y_end_l Rev 1.2 1 0 Default R/W Description vb_cs vb_en 0x00 pf vb_mode 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SSD2829 4 P 151/159 Aug 2017 0x00 0x3C 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 vb_mode : VBIST test mode selection vb_cspf: Enable color 1 & 2 swapping on every frame. (Note: This feature is R/W intended to be used together with vb_mode=0xC. The usage in other vb_mode is not verified.) vb_en : VBIST enable R/W Repeat count R/W R/W R/W RGB value for color 1 R/W R/W R/W RGB value for color 2 R/W R/W R/W R/W R/W R/W R/W R/W R/W Solomon Systech MODE 0x0 Solid color loop in sequential order of 16 pre-defined color of (0XFF0000, 0X00FF00, 0X0000FF, 0X00FFFF, 0XFF00FF, 0XFFFF00, 0XFFFFFF, 0XDFDFDF, 0XBFBFBF, 0X9F9F9F, 0X7F7F7F, 0X5F5F5F, 0X3F3F3F, 0X1F1F1F, 0X0F0F0F, 0X000000) 1 9 2 10 3 11 4 12 5 13 6 14 7 15 8 16 MODE 0x1, 0x2 Vertical (mode 0x1) / Horizontal (mode 0x2) repeating 16 colors bars with configurable bar width. Color repeating order are (0XFF0000, 0X00FF00, 0X0000FF, 0X00FFFF, 0XFF00FF, 0XFFFF00, 0XFFFFFF, 0XDFDFDF, 0XBFBFBF, 0X9F9F9F, 0X7F7F7F, 0X5F5F5F, 0X3F3F3F, 0X1F1F1F, 0X0F0F0F, 0X000000) MODE 0x3 Checker box with configurable width (>= 2) and color. Solomon Systech 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Parameter vb_repeat_cnt_h vb_repeat_cnt_l vb_r1 vb_g1 vb_b1 vb_r2 vb_g2 vb_g2 vb_x_start_h vb_x_start_l vb_x_end_h vb_x_end_l vb_y_start_h vb_y_start_l vb_y_end_h vb_y_end_l Usage Number of frames pause between different colors 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Parameter vb_repeat_cnt_h vb_repeat_cnt_l vb_r1 vb_g1 vb_b1 vb_r2 vb_g2 vb_g2 vb_x_start_h vb_x_start_l vb_x_end_h vb_x_end_l vb_y_start_h vb_y_start_l vb_y_end_h vb_y_end_l Usage Color bar width in pixels (MODE 0x1 only : Must be even number) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Parameter vb_repeat_cnt_h vb_repeat_cnt_l vb_r1 vb_g1 vb_b1 vb_r2 vb_g2 vb_g2 vb_x_start_h vb_x_start_l vb_x_end_h vb_x_end_l vb_y_start_h vb_y_start_l vb_y_end_h vb_y_end_l Usage Box width (>=2, must be even number) Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used Color 1 RGB value Color 2 RGB value Not used Not used Not used Not used Aug 2017 P 152/159 Rev 1.2 SSD2829 MODE 0x4, 0x5 Horizontal (0x4) or vertical (0x5) gradient ramp with programmable line width and color increment value. 2 vb_repeat_cnt_l MODE 0x5 MODE 0x6 Solid filled rectangle with configurable position, size and foreground / background color Rev 1.2 Usage For Mode 0x4 - # of pixels for each color step. NOTE: It must be an even number. 0 – 1 pixel. 2 – 2 pixels. 4 – 4 pixels. … For Mode 0x5 - # of lines for each color step. 0 – 1 line. 1 – 1 line. 2 – 2 lines. … r1,g1,b1 = (0,0,0) r2,g2,b2 = (63,0,0) MODE 0x4 SSD2829 vb_repeat_cnt_h repeat_cnt 256 px r1,g1,b1 = (0,0,0) r2,g2,b2 = (1,1,1) repeat_cnt = 1 Parameter 1 P 153/159 Aug 2017 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vb_r1 vb_g1 vb_b1 vb_r2 vb_g2 vb_g2 vb_x_start_h vb_x_start_l vb_x_end_h vb_x_end_l vb_y_start_h vb_y_start_l vb_y_end_h vb_y_end_l 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Parameter vb_repeat_cnt_h vb_repeat_cnt_l vb_r1 vb_g1 vb_b1 vb_r2 vb_g2 vb_g2 vb_x_start_h vb_x_start_l vb_x_end_h vb_x_end_l vb_y_start_h vb_y_start_l vb_y_end_h vb_y_end_l Start color (common for mode 0x4, 0x5) Color increment value for each step (common for mode 0x4, 0x5) Not used Not used Not used Not used Usage Not used Foreground color Background color Rectangle’s left boundary (Must be even number) Rectangle’s right boundary (Must be even number) Rectangle’s top boundary Rectangle’s bottom boundary Solomon Systech MODE 0x7 Single pixel width full size rectangle with two 45° cross touching screen corners. Or single 45° diagonal line drawn from top left / top right corner. Foreground and background color are configurable. 0x0 0x1 0x2 MODE 0x8, 0x9 Vertical (0x8) or Horizontal (0x9) repeating color bars with width of 1 pixel per color. Color repeating order is [C1, !C2, !C1, C2] MODE 0xA Single pixel width vertical and horizontal line with configurable foreground and background color x_start y_start MODE 0xB This mode is not used. Solomon Systech Parameter Usage 0x0 : Original Box + Cross 0x1 : Line from (0,0) - (W,W) 0x2 : Line from (0,W) - (W,0) 1 vb_repeat_cnt_h 2 vb_repeat_cnt_l 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vb_r1 vb_g1 vb_b1 vb_r2 vb_g2 vb_g2 vb_x_start_h vb_x_start_l vb_x_end_h vb_x_end_l vb_y_start_h vb_y_start_l vb_y_end_h vb_y_end_l Parameter vb_repeat_cnt_h vb_repeat_cnt_l vb_r1 vb_g1 vb_b1 vb_r2 vb_g2 vb_g2 vb_x_start_h vb_x_start_l vb_x_end_h vb_x_end_l vb_y_start_h vb_y_start_l vb_y_end_h vb_y_end_l Usage 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Parameter vb_repeat_cnt_h vb_repeat_cnt_l vb_r1 vb_g1 vb_b1 vb_r2 vb_g2 vb_g2 vb_x_start_h vb_x_start_l vb_x_end_h vb_x_end_l vb_y_start_h vb_y_start_l vb_y_end_h vb_y_end_l Usage 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Parameter Usage 1 to 16 Foreground color RGB value Background color RGB value Not used Not used Not used Not used Not used Color 1 RGB value Color 2 RGB value Not used Not used Not used Not used No used Foreground color RGB value Background color RGB value x-coordinate of the vertical line Not used y-coordinate of the horizontal line Not used Not used Aug 2017 P 154/159 Rev 1.2 SSD2829 MODE 0xC Check box with configurable color, vertical offset and vertical repeat count. (Original single pixel checkbox can be obtained by setting offset=0 & repeat=0) Vertical Offset = 1 Vertical Repeat = 2 Vertical Repeat = 2 Vertical Repeat = 2 MODE 0xD, 0xE Vertical (0xD) or Horizontal (0xE) moving bar with configurable speed, width, step (with direction) and foreground / background color. MODE 0xF Full screen solid fill with configurable color. SSD2829 Rev 1.2 P 155/159 Aug 2017 1 Parameter vb_repeat_cnt_h 2 vb_repeat_cnt_l 3 4 5 6 7 8 9 10 11 12 13 vb_r1 vb_g1 vb_b1 vb_r2 vb_g2 vb_g2 vb_x_start_h vb_x_start_l vb_x_end_h vb_x_end_l vb_y_start_h 14 vb_y_start_l 15 16 vb_y_end_h vb_y_end_l 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Parameter vb_repeat_cnt_h vb_repeat_cnt_l vb_r1 vb_g1 vb_b1 vb_r2 vb_g2 vb_g2 vb_x_start_h vb_x_start_l vb_x_end_h vb_x_end_l vb_y_start_h vb_y_start_l vb_y_end_h vb_y_end_l Parameter vb_repeat_cnt_h vb_repeat_cnt_l vb_r1 vb_g1 vb_b1 vb_r2 vb_g2 vb_g2 vb_x_start_h vb_x_start_l vb_x_end_h vb_x_end_l vb_y_start_h vb_y_start_l vb_y_end_h vb_y_end_l Usage Vertical repeat in rows. 0: 1 line. 1: 2 lines. … Color 1 RGB value Color 2 RGB value Not used Not used Vertical Offset in rows. (Must be