nRF52811
Product Specification
v1.0
4454_140 v1.0 / 2019-02-26
Feature list
Features:
•
®
Bluetooth 5.1, IEEE 802.15.4-2006, 2.4 GHz transceiver
•
®
-97 dBm sensitivity in 1 Mbps Bluetooth low energy mode
Nordic SoftDevice ready
-104 dBm sensitivity in 125 kbps Bluetooth low energy mode (long range)
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Support for concurrent multi-protocol
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-20 to +4 dBm TX power, configurable in 4 dB steps
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12-bit, 200 ksps ADC - 8 configurable channels with programmable
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On-air compatible with nRF52, nRF51, nRF24L, and nRF24AP Series
•
Supported data rates:
®
gain
®
•
Bluetooth 5.1: 2 Mbps, 1 Mbps, 500 kbps, and 125 kbps
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IEEE 802.15.4-2006: 250 kbps
•
Proprietary 2.4 GHz: 2 Mbps, 1 Mbps
Angle-of-arrival (AoA) and angle-of-departure (AoD) direction finding using
®
Bluetooth .
•
Single-ended antenna output (on-chip balun)
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4.6 mA peak current in TX (0 dBm)
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4.6 mA peak current in RX
•
•
192 kB flash and 24 kB RAM
•
•
•
•
•
RSSI (1 dB resolution)
®
®
ARM Cortex -M4 32-bit processor, 64 MHz
®
•
144 EEMBC CoreMark score running from flash memory
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34.4 µA/MHz running CoreMark from flash memory
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32.8 µA/MHz running CoreMark from RAM memory
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Serial wire debug (SWD)
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64 level comparator
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Temperature sensor
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Up to 32 general purpose I/O pins
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4-channel pulse width modulator (PWM) unit with EasyDMA
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Digital microphone interface (PDM)
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3x 32-bit timer with counter mode
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2x SPI master/slave with EasyDMA
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I2C compatible 2-wire master/slave
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UART (CTS/RTS) with EasyDMA
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Programmable peripheral interconnect (PPI)
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Quadrature decoder (QDEC)
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AES HW encryption with EasyDMA
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2x real-time counter (RTC)
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Single crystal operation
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Package variants
Flexible power management
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1.7 V to 3.6 V supply voltage range
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Fully automatic LDO and DC/DC regulator system
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Fast wake-up using 64 MHz internal oscillator
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0.3 µA at 3 V in System OFF mode, no RAM retention
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0.5 µA at 3 V in System OFF mode with full 24 kB RAM retention
•
1.5 µA at 3 V in System ON mode, with full 24 kB RAM retention, wake on
•
QFN48 package, 6 x 6 mm
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QFN32 package, 5 x 5 mm
•
WLCSP package, 2.482 x 2.464 mm
RTC
•
1.4 µA at 3 V in System ON mode, no RAM retention, wake on RTC
Applications:
•
Computer peripherals and I/O devices
•
Health and medical
•
Mouse
•
Enterprise lighting
•
Keyboard
•
Industrial
•
Mobile HID
•
Commercial
•
Retail
•
CE remote controls
•
Network processor
•
Beacons
•
Wearables
•
Connectivity device in multi-chip solutions
•
Virtual reality headsets
4454_140 v1.0
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Contents
Feature list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
1
Revision history.
2
About this document.
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2.1 Document naming and status . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Peripheral naming and abbreviations . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Register tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.1 Fields and values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.1 DUMMY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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12
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3
Block diagram.
14
4
Core components.
5
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15
4.1 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.1 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.2 CPU and support module configuration . . . . . . . . . . . . . . . . . . . . .
4.2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.1 RAM - Random access memory . . . . . . . . . . . . . . . . . . . . . . . .
4.2.2 Flash - Non-volatile memory . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.3 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.4 Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 NVMC — Non-volatile memory controller . . . . . . . . . . . . . . . . . . . . . .
4.3.1 Writing to flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.2 Erasing a page in flash . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.3 Writing to user information configuration registers (UICR) . . . . . . . . . . . . .
4.3.4 Erasing user information configuration registers (UICR) . . . . . . . . . . . . . . .
4.3.5 Erase all . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.6 Partial erase of a page in flash . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.7 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.8 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 FICR — Factory information configuration registers . . . . . . . . . . . . . . . . . .
4.4.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 UICR — User information configuration registers . . . . . . . . . . . . . . . . . . .
4.5.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.1 EasyDMA error handling . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.2 EasyDMA array list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7 AHB multilayer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8 Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.1 DAP - Debug access port . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.2 CTRL-AP - Control access port . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.3 Debug interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.4 Real-time debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Power and clock management.
42
. . . . . . . . . . . . . . . . . . . . . . .
5.1 Power management unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.2 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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5.2.1 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 POWER — Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.1 Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.2 System OFF mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.3 System ON mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.4 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.5 RAM power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.6 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.7 Retained registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.8 Reset behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.9 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.10 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4 CLOCK — Clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.1 HFCLK clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.2 LFCLK clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.4 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Peripherals.
74
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6.1 Peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.1.1 Peripheral ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.1.2 Peripherals with shared ID . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.1.3 Peripheral registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
6.1.4 Bit set and clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.1.5 Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.1.6 Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.1.7 Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.1.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.2 AAR — Accelerated address resolver . . . . . . . . . . . . . . . . . . . . . . . . 77
6.2.1 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.2.2 Resolving a resolvable address . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.2.3 Use case example for chaining RADIO packet reception with address resolution using AAR . 78
6.2.4 IRK data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.2.5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.2.6 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3 BPROT — Block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.4 CCM — AES CCM mode encryption . . . . . . . . . . . . . . . . . . . . . . . . 85
6.4.1 Key-steam generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.4.2 Encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.4.3 Decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.4.4 AES CCM and RADIO concurrent operation . . . . . . . . . . . . . . . . . . . . 87
6.4.5 Encrypting packets on-the-fly in radio transmit mode . . . . . . . . . . . . . . . 87
6.4.6 Decrypting packets on-the-fly in radio receive mode . . . . . . . . . . . . . . . . 88
6.4.7 CCM data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.4.8 EasyDMA and ERROR event . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.4.9 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.4.10 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.5 COMP — Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.5.1 Differential mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.5.2 Single-ended mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.5.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.5.4 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.6 ECB — AES electronic codebook mode encryption . . . . . . . . . . . . . . . . . . 109
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6.6.1 Shared resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.2 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.3 ECB data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.5 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7 EGU — Event generator unit . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7.2 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.8 GPIO — General purpose input/output . . . . . . . . . . . . . . . . . . . . . .
6.8.1 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.8.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.8.3 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.9 GPIOTE — GPIO tasks and events . . . . . . . . . . . . . . . . . . . . . . . . .
6.9.1 Pin events and tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.9.2 Port event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.9.3 Tasks and events pin configuration . . . . . . . . . . . . . . . . . . . . . .
6.9.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.9.5 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10 PDM — Pulse density modulation interface . . . . . . . . . . . . . . . . . . . .
6.10.1 Master clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10.2 Module operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10.3 Decimation filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10.4 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10.5 Hardware example . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10.6 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10.7 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10.8 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.11 PPI — Programmable peripheral interconnect . . . . . . . . . . . . . . . . . . .
6.11.1 Pre-programmed channels . . . . . . . . . . . . . . . . . . . . . . . . .
6.11.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12 PWM — Pulse width modulation . . . . . . . . . . . . . . . . . . . . . . . .
6.12.1 Wave counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12.2 Decoder with EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12.3 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12.4 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12.5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13 QDEC — Quadrature decoder . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13.1 Sampling and decoding . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13.2 LED output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13.3 Debounce filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13.4 Accumulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13.5 Output/input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13.6 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13.7 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13.8 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14 RADIO — 2.4 GHz radio . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14.1 Packet configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14.2 Address configuration . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14.3 Data whitening . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14.4 CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14.5 Radio states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14.6 Transmit sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14.7 Receive sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14.8 Received signal strength indicator (RSSI) . . . . . . . . . . . . . . . . . . . .
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6.14.9 Interframe spacing (IFS) . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14.10 Device address match . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14.11 Bit counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14.12 Direction finding . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14.13 IEEE 802.15.4 operation . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14.14 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14.15 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14.16 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.15 RNG — Random number generator . . . . . . . . . . . . . . . . . . . . . . .
6.15.1 Bias correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.15.2 Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.15.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.15.4 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.16 RTC — Real-time counter . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.16.1 Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.16.2 Resolution versus overflow and the PRESCALER . . . . . . . . . . . . . . . . .
6.16.3 COUNTER register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.16.4 Overflow features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.16.5 TICK event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.16.6 Event control feature . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.16.7 Compare feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.16.8 TASK and EVENT jitter/delay . . . . . . . . . . . . . . . . . . . . . . . . .
6.16.9 Reading the COUNTER register . . . . . . . . . . . . . . . . . . . . . . .
6.16.10 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.16.11 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.17 SAADC — Successive approximation analog-to-digital converter . . . . . . . . . . . .
6.17.1 Shared resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.17.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.17.3 Digital output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.17.4 Analog inputs and channels . . . . . . . . . . . . . . . . . . . . . . . . .
6.17.5 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.17.6 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.17.7 Resistor ladder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.17.8 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.17.9 Acquisition time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.17.10 Limits event monitoring . . . . . . . . . . . . . . . . . . . . . . . . . .
6.17.11 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.17.12 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.17.13 Performance factors . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.18 SPI — Serial peripheral interface master . . . . . . . . . . . . . . . . . . . . .
6.18.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.18.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.18.3 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.19 SPIM — Serial peripheral interface master with EasyDMA . . . . . . . . . . . . . .
6.19.1 SPI master transaction sequence . . . . . . . . . . . . . . . . . . . . . . .
6.19.2 Master mode pin configuration . . . . . . . . . . . . . . . . . . . . . . .
6.19.3 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.19.4 Low power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.19.5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.19.6 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.20 SPIS — Serial peripheral interface slave with EasyDMA . . . . . . . . . . . . . . . .
6.20.1 Shared resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.20.2 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.20.3 SPI slave operation . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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6.20.4 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.20.5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.20.6 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.21 SWI — Software interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.21.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.22 TEMP — Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . .
6.22.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.22.2 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.23 TWI — I2C compatible two-wire interface . . . . . . . . . . . . . . . . . . . . .
6.23.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.23.2 Master mode pin configuration . . . . . . . . . . . . . . . . . . . . . . .
6.23.3 Shared resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.23.4 Master write sequence . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.23.5 Master read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.23.6 Master repeated start sequence . . . . . . . . . . . . . . . . . . . . . . .
6.23.7 Low power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.23.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.23.9 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.24 TIMER — Timer/counter . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.24.1 Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.24.2 Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.24.3 Task delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.24.4 Task priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.24.5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.25 TWIM — I2C compatible two-wire interface master with EasyDMA . . . . . . . . . . .
6.25.1 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.25.2 Master write sequence . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.25.3 Master read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.25.4 Master repeated start sequence . . . . . . . . . . . . . . . . . . . . . . .
6.25.5 Low power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.25.6 Master mode pin configuration . . . . . . . . . . . . . . . . . . . . . . .
6.25.7 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.25.8 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.25.9 Pullup resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.26 TWIS — I2C compatible two-wire interface slave with EasyDMA . . . . . . . . . . . .
6.26.1 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.26.2 TWI slave responding to a read command . . . . . . . . . . . . . . . . . . .
6.26.3 TWI slave responding to a write command . . . . . . . . . . . . . . . . . . .
6.26.4 Master repeated start sequence . . . . . . . . . . . . . . . . . . . . . . .
6.26.5 Terminating an ongoing TWI transaction . . . . . . . . . . . . . . . . . . . .
6.26.6 Low power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.26.7 Slave mode pin configuration . . . . . . . . . . . . . . . . . . . . . . . .
6.26.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.26.9 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.27 UART — Universal asynchronous receiver/transmitter . . . . . . . . . . . . . . . .
6.27.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.27.2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.27.3 Shared resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.27.4 Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.27.5 Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.27.6 Suspending the UART . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.27.7 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.27.8 Using the UART without flow control . . . . . . . . . . . . . . . . . . . . .
6.27.9 Parity and stop bit configuration . . . . . . . . . . . . . . . . . . . . . . .
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381
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383
6.27.10 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.27.11 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.28 UARTE — Universal asynchronous receiver/transmitter with EasyDMA . . . . . . . . .
6.28.1 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.28.2 Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.28.3 Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.28.4 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.28.5 Using the UARTE without flow control . . . . . . . . . . . . . . . . . . . .
6.28.6 Parity and stop bit configuration . . . . . . . . . . . . . . . . . . . . . . .
6.28.7 Low power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.28.8 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.28.9 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.28.10 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.29 WDT — Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.29.1 Reload criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.29.2 Temporarily pausing the watchdog . . . . . . . . . . . . . . . . . . . . . .
6.29.3 Watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.29.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.29.5 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
Hardware and layout.
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 Pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.1 QFN48 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.2 QFN32 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.3 WLCSP ball assignments . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.4 GPIO pins located near the radio . . . . . . . . . . . . . . . . . . . . . . .
7.2 Mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.1 QFN48 6 x 6 mm package . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.2 QFN32 5 x 5 mm package . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.3 WLCSP 2.482 x 2.464 mm package . . . . . . . . . . . . . . . . . . . . . .
7.3 Reference circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.1 Schematic QFAA QFN48 with internal LDO regulator setup . . . . . . . . . . . . .
7.3.2 Schematic QFAA QFN48 with DC/DC regulator setup . . . . . . . . . . . . . . .
7.3.3 Schematic QCAA QFN32 with internal LDO regulator setup . . . . . . . . . . . . .
7.3.4 Schematic QCAA QFN32 with DC/DC regulator setup . . . . . . . . . . . . . . .
7.3.5 Schematic CAAA WLCSP with internal LDO regulator setup . . . . . . . . . . . . .
7.3.6 Schematic CAAA WLCSP with DC/DC regulator setup . . . . . . . . . . . . . . .
7.3.7 Schematic CAAA WLCSP with two layers . . . . . . . . . . . . . . . . . . . .
7.3.8 PCB guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.9 PCB layout example . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
9
Recommended operating conditions.
383
392
392
393
393
394
396
396
396
396
397
397
410
410
411
411
411
411
415
416
416
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418
420
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423
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424
425
425
426
427
428
429
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432
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434
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436
8.1 WLCSP light sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
436
Absolute maximum ratings.
10 Ordering information.
10.1
10.2
10.3
10.4
10.5
. . . . . . . . . . . . . . . . . . . . . . . .
437
. . . . . . . . . . . . . . . . . . . . . . . . . . .
438
IC marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Box labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Code ranges and values . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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11 Legal notices.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.1 Liability disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.2 Life support applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.3 RoHS and REACH statement . . . . . . . . . . . . . . . . . . . . . . . . . .
11.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.5 Copyright notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Revision history
Date
Version
Description
February 2019
1.0
First release
4454_140 v1.0
10
2
About this document
This product specification is organized into chapters based on the modules and peripherals that are
available in this IC.
The peripheral descriptions are divided into separate sections that include the following information:
• A detailed functional description of the peripheral
• Register configuration for the peripheral
• Electrical specification tables, containing performance data which apply for the operating conditions
described in Recommended operating conditions on page 436.
2.1 Document naming and status
Nordic uses three distinct names for this document, which are reflecting the maturity and the status of the
document and its content.
Document name
Description
Objective Product Specification (OPS)
Applies to document versions up to 0.7.
This product specification contains target
specifications for product development.
Preliminary Product Specification (PPS)
Applies to document versions 0.7 and up to 1.0.
This product specification contains preliminary
data. Supplementary data may be published from
Nordic Semiconductor ASA later.
Product Specification (PS)
Applies to document versions 1.0 and higher.
This product specification contains final product
specifications. Nordic Semiconductor ASA reserves
the right to make changes at any time without
notice in order to improve design and supply the
best possible product.
Table 1: Defined document names
2.2 Peripheral naming and abbreviations
Every peripheral has a unique capitalized name or an abbreviation of its name, e.g. TIMER, used for
identification and reference. This name is used in chapter headings and references, and it will appear in
the ARM® Cortex® Microcontroller Software Interface Standard (CMSIS) hardware abstraction layer to
identify the peripheral.
The peripheral instance name, which is different from the peripheral name, is constructed using the
peripheral name followed by a numbered postfix, starting with 0, for example, TIMER0. A postfix is
normally only used if a peripheral can be instantiated more than once. The peripheral instance name is
also used in the CMSIS to identify the peripheral instance.
4454_140 v1.0
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About this document
2.3 Register tables
Individual registers are described using register tables. These tables are built up of two sections. The first
three colored rows describe the position and size of the different fields in the register. The following rows
describe the fields in more detail.
2.3.1 Fields and values
The Id (Field Id) row specifies the bits that belong to the different fields in the register. If a field has
enumerated values, then every value will be identified with a unique value id in the Value Id column.
A blank space means that the field is reserved and read as undefined, and it also must be written as 0
to secure forward compatibility. If a register is divided into more than one field, a unique field name is
specified for each field in the Field column. The Value Id may be omitted in the single-bit bit fields when
values can be substituted with a Boolean type enumerator range, e.g. true/false, disable(d)/enable(d), on/
off, and so on.
Values are usually provided as decimal or hexadecimal. Hexadecimal values have a 0x prefix, decimal
values have no prefix.
The Value column can be populated in the following ways:
• Individual enumerated values, for example 1, 3, 9.
• Range of values, e.g. [0..4], indicating all values from and including 0 and 4.
• Implicit values. If no values are indicated in the Value column, all bit combinations are supported, or
alternatively the field's translation and limitations are described in the text instead.
If two or more fields are closely related, the Value Id, Value, and Description may be omitted for all but
the first field. Subsequent fields will indicate inheritance with '..'.
A feature marked Deprecated should not be used for new designs.
2.4 Registers
Register
Offset
Description
DUMMY
0x514
Example of a register controlling a dummy feature
Table 2: Register overview
2.4.1 DUMMY
Address offset: 0x514
Example of a register controlling a dummy feature
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
D D D D
Reset 0x00050002
ID
Access
Field
A
RW FIELD_A
C C C
Value ID
Value
Description
Disabled
0
The example feature is disabled
NormalMode
1
The example feature is enabled in normal mode
ExtendedMode
2
The example feature is enabled along with extra
Example of a field with several enumerated values
functionality
4454_140 v1.0
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A A
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
12
About this document
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
D D D D
Reset 0x00050002
ID
Access
Field
B
RW FIELD_B
C
D
Value ID
Value
B
A A
Description
Disabled
0
The override feature is disabled
Enabled
1
The override feature is enabled
ValidRange
[2..7]
Example of a deprecated field
RW FIELD_C
Example of a field with a valid range of values
Example of allowed values for this field
RW FIELD_D
4454_140 v1.0
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0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Example of a field with no restriction on the values
13
Deprecated
Block diagram
This block diagram illustrates the overall system. Arrows with white heads indicate signals that share
physical pins with other signals.
CTRL-AP
NVIC
slave
slave
slave
CPU
ARM
CORTEX-M4
slave
AHB multilayer
AHB-AP
nRESET
P0
(P0.0 – P0.31)
GPIO
slave
RAM2
slave
SW-DP
RAM1
slave
SWCLK
SWDIO
RAM0
slave
nRF52811
master
AHB TO APB
BRIDGE
FICR
UICR
Flash
SysTick
NVMC
RNG
POWER
RTC [0..1]
TIMER [0..2]
WDT
TEMP
PPI
XC1
XC2
XL1
XL2
CLOCK
ANT
RADIO
ECB
master
EasyDMA
master
EasyDMA
master
mast AAR
er
EasyDMA
CCM
EasyDMA
master
APB0
3
P0
(P0.0 – P0.31)
SPIM
master
GPIOTE
COMP
AIN0 – AIN7
EasyDMA
LED
A
B
OUT[0] - OUT[3]
master
EasyDMA
master
EasyDMA
TWIM
master
QDEC
UARTE
PWM
EasyDMA
CLK
DIN
master
master
PDM
EasyDMA
master
Figure 1: Block diagram
14
SCL
SDA
SCL
SDA
RTS
CTS
TXD
RXD
EasyDMA
SPIS
master
4454_140 v1.0
EasyDMA
TWIS
SAADC
SCK
MOSI
MISO
EasyDMA
CSN
MISO
MOSI
SCK
4
Core components
4.1 CPU
The ARM® Cortex®-M4 processor has a 32-bit instruction set (Thumb®-2 technology) that implements a
superset of 16- and 32-bit instructions to maximize code density and performance.
This processor implements several features that enable energy-efficient arithmetic and high-performance
signal processing including:
•
•
•
•
Digital signal processing (DSP) instructions
Single-cycle multiply and accumulate (MAC) instructions
Hardware divide
8 and 16-bit single instruction multiple data (SIMD) instructions
The ARM Cortex Microcontroller Software Interface Standard (CMSIS) hardware abstraction layer for the
ARM Cortex processor series is implemented and available for the M4 CPU.
Real-time execution is highly deterministic in thread mode, to and from sleep modes, and when handling
events at configurable priority levels via the nested vectored interrupt controller (NVIC).
Executing code from flash will have a wait state penalty on the nRF52 Series. The section Electrical
specification on page 15 shows CPU performance parameters including wait states in different modes,
CPU current and efficiency, and processing power and efficiency based on the CoreMark® benchmark.
The ARM System Timer (SysTick) is present on the device. The SysTick's clock will only tick when the CPU is
running or when the system is in debug interface mode.
4.1.1 Electrical specification
4.1.1.1 CPU performance
The CPU clock speed is 64 MHz. Current and efficiency data is taken when in System ON and the CPU is
executing the CoreMark® benchmark. It includes power regulator and clock base currents. All other blocks
are IDLE.
Symbol
Description
Min.
WFLASH
CPU wait states, running from flash
0
Typ.
Max.
Units
WRAM
CPU wait states, running from RAM
CMFLASH
CoreMark1, running from flash
144
CoreMark
CMFLASH/MHz
CoreMark per MHz, running from flash
2.25
CoreMark/
CMFLASH/mA
CoreMark per mA, running from flash, DCDC 3V
65
2
0
MHz
CoreMark/
mA
4.1.2 CPU and support module configuration
The ARM® Cortex®-M4 processor has a number of CPU options and support modules implemented on the
device.
1
Using IAR v6.50.1.4452 with flags --endian=little --cpu=Cortex-M4 -e --fpu=VFPv4_sp –Ohs -no_size_constraints
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Core components
Option / Module
Description
Implemented
NVIC
Nested vector interrupt controller
30 vectors
PRIORITIES
Priority bits
3
WIC
Wakeup interrupt controller
NO
Endianness
Memory system endianness
Little endian
Bit-banding
Bit banded memory
NO
DWT
Data watchpoint and trace
NO
SysTick
System tick timer
YES
MPU
Memory protection unit
YES
FPU
Floating-point unit
NO
DAP
Debug access port
YES
ETM
Embedded trace macrocell
NO
ITM
Instrumentation trace macrocell
NO
TPIU
Trace port interface unit
NO
ETB
Embedded trace buffer
NO
FPB
Flash patch and breakpoint unit
YES
HTM
AMBA AHB trace macrocell
Core options
Modules
®
NO
4.2 Memory
The nRF52811 contains flash and RAM that can be used for code and data storage.
The amount of RAM and flash will vary depending on variant, see Memory variants on page 16.
Device name
RAM
Flash
nRF52811-QFAA
24 kB
192 kB
nRF52811-QCAA
24 kB
192 kB
nRF52811-CAAA
24 kB
192 kB
Comments
Table 3: Memory variants
The CPU and peripherals with EasyDMA can access memory via the AHB multilayer interconnect. The CPU
is also able to access peripherals via the AHB multilayer interconnect, as illustrated in Memory layout on
page 17.
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Core components
AHB2APB
APB
CPU
System bus
EasyDMA
ICODE
EasyDMA
DMA bus
Peripheral
DMA bus
Peripheral
DCODE
ARM Cortex-M4
Data RAM
System
Code RAM
ICODE/DCODE
RAM2
AHB slave
Section 1
0x20005000
0x00805000
Section 0
0x20004000
0x00804000
RAM1
AHB slave
Section 1
0x20003000
0x00803000
Section 0
0x20002000
0x00802000
RAM0
AHB slave
Section 1
0x20001000
0x00801000
Section 0
0x20000000
0x00800000
AHB multilayer interconnect
NVMC
DCODE
AHB
slave
ICODE
AHB
AHB
slave
Page 47
Flash
ICODE/DCODE
0x0002F000
Page 3..46
0x00003000
Page 2
Page 1
Page 0
0x00002000
0x00001000
Block 7
0x00000E00
Block 2..6
0x00000400
Block 1
0x00000200
Block 0
0x00000000
Figure 2: Memory layout
See AHB multilayer on page 37 and EasyDMA on page 35 for more information about the AHB
multilayer interconnect and the EasyDMA.
The same physical RAM is mapped to both the Data RAM region and the Code RAM region. It is up to the
application to partition the RAM within these regions so that one does not corrupt the other.
4.2.1 RAM - Random access memory
The RAM interface is divided into multiple RAM AHB slaves.
Each RAM AHB slave is connected to two 4-kilobyte RAM sections, see Section 0 and Section 1 in Memory
layout on page 17.
Each of the RAM sections have separate power control for System ON and System OFF mode operation,
which is configured via RAM register (see the POWER — Power supply on page 48).
4.2.2 Flash - Non-volatile memory
The flash can be read an unlimited number of times by the CPU, but it has restrictions on the number of
times it can be written and erased, and also on how it can be written.
Writing to flash is managed by the non-volatile memory controller (NVMC), see NVMC — Non-volatile
memory controller on page 19.
The flash is divided into multiple 4 kB pages that can be accessed by the CPU via both the ICODE and
DCODE buses as shown in, Memory layout on page 17. Each page is divided into 8 blocks.
4.2.3 Memory map
The complete memory map is shown in Memory map on page 18. As described in Memory on page
16, Code RAM and Data RAM are the same physical RAM.
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Core components
Cortex M4 system address map
0xFFFFFFFF
0xE0100000
0xE0000000
Private peripheral bus
0x5FFFFFFF
AHB peripherals
0x50000000
APB peripherals
0x1FFFFFFF
0x10002000
0x40000000
UICR
0x10001000
FICR
0x10000000
0x00806000
Code RAM
0x00800000
0x00030000
Peripheral
0.5GB
SRAM
0.5GB
Code
0.5GB
0x3FFFFFFF
0x20006000
Data RAM
Flash
0x20000000
0x00000000
Figure 3: Memory map
4.2.4 Instantiation
ID
Base address
Peripheral
Instance
Description
0
0x40000000
BPROT
BPROT
Block protect
0
0x40000000
CLOCK
CLOCK
Clock control
0
0x40000000
POWER
POWER
Power control
0
0x50000000
GPIO
P0
General purpose input and output
1
0x40001000
RADIO
RADIO
2.4 GHz radio
2
0x40002000
UART
UART0
Universal asynchronous receiver/transmitter
2
0x40002000
UARTE
UARTE0
Universal asynchronous receiver/transmitter with EasyDMA
3
0x40003000
SPI
SPI1
SPI master 1
3
0x40003000
SPIM
SPIM1
SPI master 1
3
0x40003000
SPIS
SPIS1
SPI slave 1
3
0x40003000
TWI
TWI0
Two-wire interface master
3
0x40003000
TWIM
TWIM0
Two-wire interface master
3
0x40003000
TWIS
TWIS0
Two-wire interface slave
4
0x40004000
SPI
SPI0
SPI master 0
4
0x40004000
SPIM
SPIM0
SPI master 0
4
0x40004000
SPIS
SPIS0
SPI slave 0
6
0x40006000
GPIOTE
GPIOTE
GPIO tasks and events
7
0x40007000
SAADC
SAADC
Analog-to-digital converter
8
0x40008000
TIMER
TIMER0
Timer 0
9
0x40009000
TIMER
TIMER1
Timer 1
10
0x4000A000
TIMER
TIMER2
Timer 2
11
0x4000B000
RTC
RTC0
Real-time counter 0
12
0x4000C000
TEMP
TEMP
Temperature sensor
13
0x4000D000
RNG
RNG
Random number generator
14
0x4000E000
ECB
ECB
AES Electronic Codebook (ECB) mode block encryption
15
0x4000F000
AAR
AAR
Accelerated address resolver
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Deprecated
Deprecated
Deprecated
Deprecated
Core components
ID
Base address
Peripheral
Instance
Description
15
0x4000F000
CCM
CCM
AES CCM mode encryption
16
0x40010000
WDT
WDT
Watchdog timer
17
0x40011000
RTC
RTC1
Real-time counter 1
18
0x40012000
QDEC
QDEC
Quadrature decoder
19
0x40013000
COMP
COMP
General purpose comparator
20
0x40014000
EGU
EGU0
Event generator unit 0
20
0x40014000
SWI
SWI0
Software interrupt 0
21
0x40015000
EGU
EGU1
Event generator unit 1
21
0x40015000
SWI
SWI1
Software interrupt 1
22
0x40016000
SWI
SWI2
Software interrupt 2
23
0x40017000
SWI
SWI3
Software interrupt 3
24
0x40018000
SWI
SWI4
Software interrupt 4
25
0x40019000
SWI
SWI5
Software interrupt 5
28
0x4001C000
PWM
PWM0
Pulse-width modulation unit 0
29
0x4001D000
PDM
PDM
Pulse-density modulation (digital microphone interface)
30
0x4001E000
NVMC
NVMC
Non-volatile memory controller
31
0x4001F000
PPI
PPI
Programmable peripheral interconnect
N/A
0x10000000
FICR
FICR
Factory information configuration
N/A
0x10001000
UICR
UICR
User information configuration
Table 4: Instantiation table
4.3 NVMC — Non-volatile memory controller
The non-volatile memory controller (NVMC) is used for writing and erasing of the internal flash memory
and the UICR (user information configuration registers).
The CONFIG on page 21 is used to enable the NVMC for writing (CONFIG.WEN) and erasing
(CONFIG.EEN). The user must make sure that writing and erasing are not enabled at the same time. Having
both enabled at the same time may result in unpredictable behavior.
The CPU must be halted before initiating a NVMC operation from the debug system.
4.3.1 Writing to flash
When writing is enabled, full 32-bit words are written to word-aligned addresses in flash.
As illustrated in Memory on page 16, the flash is divided into multiple pages. The same 32-bit word in
the flash can only be written nWRITE number of times before a page erase must be performed.
The NVMC is only able to write 0 to bits in the flash that are erased (set to 1). It cannot rewrite a bit back
to 1. Only full 32-bit words can be written to flash using the NVMC interface. To write less than 32 bits,
write the data as a full 32-bit word and set all the bits that should remain unchanged in the word to 1.
Note that the restriction on the number of writes (nWRITE) still applies in this case.
Only word-aligned writes are allowed. Byte or half-word-aligned writes will result in a hard fault.
The time it takes to write a word to flash is specified by tWRITE. The CPU is halted while the NVMC is writing
to the flash.
4.3.2 Erasing a page in flash
When erase is enabled, the flash memory can be erased page by page using the ERASEPAGE on page
21.
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Core components
After erasing a flash page, all bits in the page are set to 1. The time it takes to erase a page is specified
by tERASEPAGE. The CPU is halted if the CPU executes code from the flash while the NVMC is writing to the
flash.
See Partial erase of a page in flash on page 20 for information on dividing the page erase time into
shorter chunks.
4.3.3 Writing to user information configuration registers (UICR)
User information configuration registers (UICR) are written in the same way as flash. After UICR has been
written, the new UICR configuration will take effect after a reset.
UICR can only be written nWRITE number of times before an erase must be performed using ERASEUICR on
page 23 or ERASEALL on page 22. The time it takes to write a word to UICR is specified by tWRITE.
The CPU is halted while the NVMC is writing to the UICR.
4.3.4 Erasing user information configuration registers (UICR)
When erase is enabled, UICR can be erased using the ERASEUICR on page 23.
After erasing UICR all bits in UICR are set to 1. The time it takes to erase UICR is specified by tERASEPAGE. The
CPU is halted if the CPU executes code from the flash while the NVMC performs the erase operation.
4.3.5 Erase all
When erase is enabled, flash and UICR can be erased completely in one operation by using ERASEALL on
page 22. This operation will not erase the factory information configuration registers (FICR).
The time it takes to perform an ERASEALL command is specified by tERASEALL. The CPU is halted if the CPU
executes code from the flash while the NVMC performs the erase operation.
4.3.6 Partial erase of a page in flash
Partial erase is a feature in the NVMC to split a page erase time into shorter chunks, so this can be used to
prevent longer CPU stalls in time-critical applications. Partial erase is only applicable to the code area in
the flash and does not work with UICR.
When erase is enabled, the partial erase of a flash page can be started by writing to ERASEPAGEPARTIAL
on page 23. The duration of a partial erase can be configured in ERASEPAGEPARTIALCFG on page
23. A flash page is erased when its erase time reaches tERASEPAGE. Use ERASEPAGEPARTIAL N number
of times so that N * ERASEPAGEPARTIALCFG ≥ tERASEPAGE, where N * ERASEPAGEPARTIALCFG gives the
cumulative (total) erase time. Every time the cumulative erase time reaches tERASEPAGE, it counts as one
erase cycle.
After the erase is done, all bits in the page are set to '1'. The CPU is halted if the CPU executes code from
the flash while the NVMC performs the partial erase operation.
The bits in the page are undefined if the flash page erase is incomplete, i.e. if a partial erase has started
but the total erase time is less than tERASEPAGE.
4.3.7 Registers
Base address
Peripheral
Instance
Description
0x4001E000
NVMC
NVMC
Non-volatile memory controller
Configuration
Table 5: Instances
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Register
Offset
Description
READY
0x400
Ready flag
CONFIG
0x504
Configuration register
ERASEPAGE
0x508
Register for erasing a page in code area
ERASEPCR1
0x508
Register for erasing a page in code area. Equivalent to ERASEPAGE.
ERASEALL
0x50C
Register for erasing all non-volatile user memory
ERASEPCR0
0x510
Register for erasing a page in code area. Equivalent to ERASEPAGE.
ERASEUICR
0x514
Register for erasing user information configuration registers
ERASEPAGEPARTIAL
0x518
Register for partial erase of a page in code area
ERASEPAGEPARTIALCFG
0x51C
Register for partial erase configuration
Deprecated
Deprecated
Table 6: Register overview
4.3.7.1 READY
Address offset: 0x400
Ready flag
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000001
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Value ID
Value
Description
Busy
0
NVMC is busy (ongoing write or erase operation)
Ready
1
NVMC is ready
READY
NVMC is ready or busy
4.3.7.2 CONFIG
Address offset: 0x504
Configuration register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A
Reset 0x00000000
ID
Access
Field
A
RW WEN
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Program memory access mode. It is strongly recommended
to activate erase and write modes only when they are
actively used.
Ren
0
Read only access
Wen
1
Write enabled
Een
2
Erase enabled
4.3.7.3 ERASEPAGE
Address offset: 0x508
Register for erasing a page in code area
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Core components
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID
Access
Field
A
RW ERASEPAGE
Value ID
Value
Description
Register for starting erase of a page in code area.
The value is the address to the page to be erased (addresses
of first word in page). Note that the erase must be enabled
using CONFIG.WEN before the page can be erased.
Attempts to erase pages that are outside the code area may
result in undesirable behavior, e.g. the wrong page may be
erased.
4.3.7.4 ERASEPCR1 ( Deprecated )
Address offset: 0x508
Register for erasing a page in code area. Equivalent to ERASEPAGE.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID
Access
Field
A
RW ERASEPCR1
Value ID
Value
Description
Register for erasing a page in code area. Equivalent to
ERASEPAGE.
4.3.7.5 ERASEALL
Address offset: 0x50C
Register for erasing all non-volatile user memory
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW ERASEALL
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Erase all non-volatile memory including UICR registers. Note
that the erase must be enabled using CONFIG.WEN before
the non-volatile memory can be erased.
NoOperation
0
No operation
Erase
1
Start erase of chip
4.3.7.6 ERASEPCR0 ( Deprecated )
Address offset: 0x510
Register for erasing a page in code area. Equivalent to ERASEPAGE.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
RW ERASEPCR0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Register for starting erase of a page in code area. Equivalent
to ERASEPAGE.
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Core components
4.3.7.7 ERASEUICR
Address offset: 0x514
Register for erasing user information configuration registers
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW ERASEUICR
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Register starting erase of all user information configuration
registers. Note that the erase must be enabled using
CONFIG.WEN before the UICR can be erased.
NoOperation
0
No operation
Erase
1
Start erase of UICR
4.3.7.8 ERASEPAGEPARTIAL
Address offset: 0x518
Register for partial erase of a page in code area
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
RW ERASEPAGEPARTIAL
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Register for starting partial erase of a page in code area
The value is the address to the page to be partially erased
(address of the first word in page). Note that the erase must
be enabled using CONFIG.WEN before every erase page
partial and disabled using CONFIG.WEN after every erase
page partial. Attempts to erase pages that are outside the
code area may result in undesirable behaviour, e.g. the
wrong page may be erased.
4.3.7.9 ERASEPAGEPARTIALCFG
Address offset: 0x51C
Register for partial erase configuration
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A
Reset 0x0000000A
ID
Access
Field
A
RW DURATION
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0
Value ID
Value
Description
Duration of the partial erase in milliseconds
The user must ensure that the total erase time is long
enough for a complete erase of the flash page.
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Core components
4.3.8 Electrical specification
4.3.8.1 Flash programming
Symbol
Description
nWRITE
Number of times a 32-bit word can be written before erase
Min.
nENDURANCE
Erase cycles per page
tWRITE
Time to write one 32-bit word
tERASEPAGE
Time to erase one page
tERASEALL
Time to erase all flash
Typ.
Max.
Units
2
10000
µs
412
ms
2
85
169
tERASEPAGEPARTIAL,acc Accuracy of the partial page erase duration. Total
2
ms
1.052
execution time for one partial page erase is defined as
ERASEPAGEPARTIALCFG * tERASEPAGEPARTIAL,acc.
4.4 FICR — Factory information configuration registers
Factory information configuration registers (FICR) are pre-programmed in factory and cannot be erased by
the user. These registers contain chip-specific information and configuration.
4.4.1 Registers
Base address
Peripheral
Instance
Description
Configuration
0x10000000
FICR
FICR
Factory information configuration
Table 7: Instances
Register
Offset
Description
CODEPAGESIZE
0x010
Code memory page size
CODESIZE
0x014
Code memory size
DEVICEID[0]
0x060
Device identifier
DEVICEID[1]
0x064
Device identifier
ER[0]
0x080
Encryption root, word 0
ER[1]
0x084
Encryption root, word 1
ER[2]
0x088
Encryption root, word 2
ER[3]
0x08C
Encryption root, word 3
IR[0]
0x090
Identity root, word 0
IR[1]
0x094
Identity root, word 1
IR[2]
0x098
Identity root, word 2
IR[3]
0x09C
Identity root, word 3
DEVICEADDRTYPE
0x0A0
Device address type
DEVICEADDR[0]
0x0A4
Device address 0
DEVICEADDR[1]
0x0A8
Device address 1
INFO.PART
0x100
Part code
INFO.VARIANT
0x104
Part variant, hardware version and production configuration
INFO.PACKAGE
0x108
Package option
INFO.RAM
0x10C
RAM variant
INFO.FLASH
0x110
Flash variant
INFO.UNUSED8[0]
0x114
2
Reserved
HFXO is used here
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Register
Offset
Description
INFO.UNUSED8[1]
0x118
INFO.UNUSED8[2]
0x11C
TEMP.A0
0x404
Slope definition A0
TEMP.A1
0x408
Slope definition A1
TEMP.A2
0x40C
Slope definition A2
TEMP.A3
0x410
Slope definition A3
TEMP.A4
0x414
Slope definition A4
TEMP.A5
0x418
Slope definition A5
TEMP.B0
0x41C
Y-intercept B0
TEMP.B1
0x420
Y-intercept B1
TEMP.B2
0x424
Y-intercept B2
TEMP.B3
0x428
Y-intercept B3
TEMP.B4
0x42C
Y-intercept B4
TEMP.B5
0x430
Y-intercept B5
TEMP.T0
0x434
Segment end T0
TEMP.T1
0x438
Segment end T1
TEMP.T2
0x43C
Segment end T2
TEMP.T3
0x440
Segment end T3
TEMP.T4
0x444
Segment end T4
Reserved
Reserved
Table 8: Register overview
4.4.1.1 CODEPAGESIZE
Address offset: 0x010
Code memory page size
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00001000
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
CODEPAGESIZE
Code memory page size
4.4.1.2 CODESIZE
Address offset: 0x014
Code memory size
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000030
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0
Value ID
Value
Description
CODESIZE
Code memory size in number of pages
Total code space is: CODEPAGESIZE * CODESIZE
4.4.1.3 DEVICEID[n] (n=0..1)
Address offset: 0x060 + (n × 0x4)
Device identifier
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID
Access
Field
A
R
Value ID
Value
Description
DEVICEID
64 bit unique device identifier
DEVICEID[0] contains the least significant bits of the device
identifier. DEVICEID[1] contains the most significant bits of
the device identifier.
4.4.1.4 ER[n] (n=0..3)
Address offset: 0x080 + (n × 0x4)
Encryption root, word n
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
ID
Access
Field
A
R
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value ID
Value
Description
ER
Encryption root, word n
4.4.1.5 IR[n] (n=0..3)
Address offset: 0x090 + (n × 0x4)
Identity root, word n
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID
Access
Field
A
R
Value ID
Value
Description
IR
Identity root, word n
4.4.1.6 DEVICEADDRTYPE
Address offset: 0x0A0
Device address type
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0xFFFFFFFF
ID
Access
Field
A
R
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value ID
Value
Description
DEVICEADDRTYPE
Device address type
Public
0
Public address
Random
1
Random address
4.4.1.7 DEVICEADDR[n] (n=0..1)
Address offset: 0x0A4 + (n × 0x4)
Device address n
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26
Core components
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID
Access
Field
A
R
Value ID
Value
Description
DEVICEADDR
48 bit device address
DEVICEADDR[0] contains the least significant bits of
the device address. DEVICEADDR[1] contains the most
significant bits of the device address. Only bits [15:0] of
DEVICEADDR[1] are used.
4.4.1.8 INFO.PART
Address offset: 0x100
Part code
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00052811
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 1
Value ID
Value
Description
N52810
0x52810
nRF52810
N52811
0x52811
nRF52811
Unspecified
0xFFFFFFFF
Unspecified
PART
Part code
4.4.1.9 INFO.VARIANT
Address offset: 0x104
Part variant, hardware version and production configuration
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID
Access
Field
A
R
Value ID
Value
Description
VARIANT
Part variant, hardware version and production
configuration, encoded as ASCII
AAAA
0x41414141
AAAA
AAA0
0x41414130
AAA0
AABA
0x41414241
AABA
AABB
0x41414242
AABB
AAB0
0x41414230
AAB0
AACA
0x41414341
AACA
AACB
0x41414342
AACB
AAC0
0x41414330
AAC0
Unspecified
0xFFFFFFFF
Unspecified
4.4.1.10 INFO.PACKAGE
Address offset: 0x108
Package option
4454_140 v1.0
27
Core components
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID
Access
Field
A
R
Value ID
Value
Description
QF
0x2000
QFxx - 48-pin QFN
QC
0x2003
QCxx - 32-pin QFN
CA
0x2004
CAxx - WLCSP
Unspecified
0xFFFFFFFF
Unspecified
PACKAGE
Package option
4.4.1.11 INFO.RAM
Address offset: 0x10C
RAM variant
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000018
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0
Value ID
Value
Description
K24
0x18
24 kByte RAM
Unspecified
0xFFFFFFFF
Unspecified
RAM
RAM variant
4.4.1.12 INFO.FLASH
Address offset: 0x110
Flash variant
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x000000C0
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0
Value ID
Value
Description
K192
0xC0
192 kByte flash
Unspecified
0xFFFFFFFF
Unspecified
FLASH
Flash variant
4.4.1.13 TEMP.A0
Address offset: 0x404
Slope definition A0
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A
Reset 0x00000320
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0
Value ID
Value
Description
A
A (slope definition) register
4.4.1.14 TEMP.A1
Address offset: 0x408
Slope definition A1
4454_140 v1.0
28
Core components
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A
Reset 0x00000343
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 1 1
Value ID
Value
Description
A
A (slope definition) register
4.4.1.15 TEMP.A2
Address offset: 0x40C
Slope definition A2
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A
Reset 0x0000035D
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 1 1 0 1
Value ID
Value
Description
A
A (slope definition) register
4.4.1.16 TEMP.A3
Address offset: 0x410
Slope definition A3
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A
Reset 0x00000400
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
A
A (slope definition) register
4.4.1.17 TEMP.A4
Address offset: 0x414
Slope definition A4
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A
Reset 0x00000452
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0
Value ID
Value
Description
A
A (slope definition) register
4.4.1.18 TEMP.A5
Address offset: 0x418
Slope definition A5
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A
Reset 0x0000037B
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 0 1 1
Value ID
Value
Description
A
4454_140 v1.0
A (slope definition) register
29
Core components
4.4.1.19 TEMP.B0
Address offset: 0x41C
Y-intercept B0
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A
Reset 0x00003FCC
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 0
Value ID
Value
Description
B
B (y-intercept)
4.4.1.20 TEMP.B1
Address offset: 0x420
Y-intercept B1
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A
Reset 0x00003F98
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1 0 0 0
Value ID
Value
Description
B
B (y-intercept)
4.4.1.21 TEMP.B2
Address offset: 0x424
Y-intercept B2
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A
Reset 0x00003F98
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1 0 0 0
Value ID
Value
Description
B
B (y-intercept)
4.4.1.22 TEMP.B3
Address offset: 0x428
Y-intercept B3
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A
Reset 0x00000012
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0
Value ID
Value
Description
B
B (y-intercept)
4.4.1.23 TEMP.B4
Address offset: 0x42C
Y-intercept B4
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30
Core components
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A
Reset 0x0000004D
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 1
Value ID
Value
Description
B
B (y-intercept)
4.4.1.24 TEMP.B5
Address offset: 0x430
Y-intercept B5
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A
Reset 0x00003E10
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 0
Value ID
Value
Description
B
B (y-intercept)
4.4.1.25 TEMP.T0
Address offset: 0x434
Segment end T0
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A
Reset 0x000000E2
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0
Value ID
Value
Description
T
T (segment end) register
4.4.1.26 TEMP.T1
Address offset: 0x438
Segment end T1
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
T
T (segment end) register
4.4.1.27 TEMP.T2
Address offset: 0x43C
Segment end T2
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A
Reset 0x00000014
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0
Value ID
Value
Description
T
4454_140 v1.0
T (segment end) register
31
Core components
4.4.1.28 TEMP.T3
Address offset: 0x440
Segment end T3
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A
Reset 0x00000019
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1
Value ID
Value
Description
T
T (segment end) register
4.4.1.29 TEMP.T4
Address offset: 0x444
Segment end T4
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A
Reset 0x00000050
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0
Value ID
Value
Description
T
T (segment end) register
4.5 UICR — User information configuration registers
The user information configuration registers (UICRs) are non-volatile memory (NVM) registers for
configuring user-specific settings.
For information on writing UICR registers, see the NVMC — Non-volatile memory controller on page
19 and Memory on page 16 chapters.
4.5.1 Registers
Base address
Peripheral
Instance
Description
0x10001000
UICR
UICR
User information configuration
Configuration
Table 9: Instances
Register
Offset
UNUSED0
0x000
Reserved
UNUSED1
0x004
Reserved
UNUSED2
0x008
Reserved
UNUSED3
0x010
NRFFW[0]
0x014
Reserved for Nordic firmware design
NRFFW[1]
0x018
Reserved for Nordic firmware design
NRFFW[2]
0x01C
Reserved for Nordic firmware design
NRFFW[3]
0x020
Reserved for Nordic firmware design
NRFFW[4]
0x024
Reserved for Nordic firmware design
NRFFW[5]
0x028
Reserved for Nordic firmware design
NRFFW[6]
0x02C
Reserved for Nordic firmware design
NRFFW[7]
0x030
Reserved for Nordic firmware design
4454_140 v1.0
Description
Reserved
32
Core components
Register
Offset
Description
NRFFW[8]
0x034
Reserved for Nordic firmware design
NRFFW[9]
0x038
Reserved for Nordic firmware design
NRFFW[10]
0x03C
Reserved for Nordic firmware design
NRFFW[11]
0x040
Reserved for Nordic firmware design
NRFFW[12]
0x044
Reserved for Nordic firmware design
NRFHW[0]
0x050
Reserved for Nordic hardware design
NRFHW[1]
0x054
Reserved for Nordic hardware design
NRFHW[2]
0x058
Reserved for Nordic hardware design
NRFHW[3]
0x05C
Reserved for Nordic hardware design
NRFHW[4]
0x060
Reserved for Nordic hardware design
NRFHW[5]
0x064
Reserved for Nordic hardware design
NRFHW[6]
0x068
Reserved for Nordic hardware design
NRFHW[7]
0x06C
Reserved for Nordic hardware design
NRFHW[8]
0x070
Reserved for Nordic hardware design
NRFHW[9]
0x074
Reserved for Nordic hardware design
NRFHW[10]
0x078
Reserved for Nordic hardware design
NRFHW[11]
0x07C
Reserved for Nordic hardware design
CUSTOMER[0]
0x080
Reserved for customer
CUSTOMER[1]
0x084
Reserved for customer
CUSTOMER[2]
0x088
Reserved for customer
CUSTOMER[3]
0x08C
Reserved for customer
CUSTOMER[4]
0x090
Reserved for customer
CUSTOMER[5]
0x094
Reserved for customer
CUSTOMER[6]
0x098
Reserved for customer
CUSTOMER[7]
0x09C
Reserved for customer
CUSTOMER[8]
0x0A0
Reserved for customer
CUSTOMER[9]
0x0A4
Reserved for customer
CUSTOMER[10]
0x0A8
Reserved for customer
CUSTOMER[11]
0x0AC
Reserved for customer
CUSTOMER[12]
0x0B0
Reserved for customer
CUSTOMER[13]
0x0B4
Reserved for customer
CUSTOMER[14]
0x0B8
Reserved for customer
CUSTOMER[15]
0x0BC
Reserved for customer
CUSTOMER[16]
0x0C0
Reserved for customer
CUSTOMER[17]
0x0C4
Reserved for customer
CUSTOMER[18]
0x0C8
Reserved for customer
CUSTOMER[19]
0x0CC
Reserved for customer
CUSTOMER[20]
0x0D0
Reserved for customer
CUSTOMER[21]
0x0D4
Reserved for customer
CUSTOMER[22]
0x0D8
Reserved for customer
CUSTOMER[23]
0x0DC
Reserved for customer
CUSTOMER[24]
0x0E0
Reserved for customer
CUSTOMER[25]
0x0E4
Reserved for customer
CUSTOMER[26]
0x0E8
Reserved for customer
CUSTOMER[27]
0x0EC
Reserved for customer
CUSTOMER[28]
0x0F0
Reserved for customer
CUSTOMER[29]
0x0F4
Reserved for customer
CUSTOMER[30]
0x0F8
Reserved for customer
CUSTOMER[31]
0x0FC
Reserved for customer
PSELRESET[0]
0x200
Mapping of the nRESET function (see POWER chapter for details)
PSELRESET[1]
0x204
Mapping of the nRESET function (see POWER chapter for details)
APPROTECT
0x208
Access port protection
Table 10: Register overview
4454_140 v1.0
33
Core components
4.5.1.1 NRFFW[n] (n=0..12)
Address offset: 0x014 + (n × 0x4)
Reserved for Nordic firmware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
ID
Access
Field
A
RW NRFFW
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value ID
Value
Description
Reserved for Nordic firmware design
4.5.1.2 NRFHW[n] (n=0..11)
Address offset: 0x050 + (n × 0x4)
Reserved for Nordic hardware design
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID
Access
Field
A
RW NRFHW
Value ID
Value
Description
Reserved for Nordic hardware design
4.5.1.3 CUSTOMER[n] (n=0..31)
Address offset: 0x080 + (n × 0x4)
Reserved for customer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF
ID
Access
Field
A
RW CUSTOMER
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value ID
Value
Description
Reserved for customer
4.5.1.4 PSELRESET[n] (n=0..1)
Address offset: 0x200 + (n × 0x4)
Mapping of the nRESET function (see POWER chapter for details)
All PSELRESET registers have to contain the same value for a pin mapping to be valid. If values are not
the same, there will be no nRESET function exposed on a GPIO. As a result, the device will always start
independently of the levels present on any of the GPIOs.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
C
Reset 0xFFFFFFFF
ID
Access
Field
A
RW PIN
C
RW CONNECT
4454_140 v1.0
A A A A A
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value ID
Value
Description
21
GPIO pin number onto which nRESET is exposed
Connection
Disconnected
1
Disconnect
Connected
0
Connect
34
Core components
4.5.1.5 APPROTECT
Address offset: 0x208
Access port protection
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A
Reset 0xFFFFFFFF
ID
Access
Field
A
RW PALL
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value ID
Value
Description
Enable or disable access port protection.
See Debug on page 38 for more information.
Disabled
0xFF
Disable
Enabled
0x00
Enable
4.6 EasyDMA
EasyDMA is a module implemented by some peripherals to gain direct access to Data RAM.
EasyDMA is an AHB bus master similar to CPU and is connected to the AHB multilayer interconnect for
direct access to Data RAM. EasyDMA is not able to access flash.
A peripheral can implement multiple EasyDMA instances to provide dedicated channels. For example,
for reading and writing of data between the peripheral and RAM. This concept is illustrated in EasyDMA
example on page 35.
RAM
AHB multilayer
Peripheral
READER
RAM
RAM
AHB
WRITER
AHB
Figure 4: EasyDMA example
4454_140 v1.0
EasyDMA
35
EasyDMA
Peripheral
core
Core components
An EasyDMA channel is implemented in the following way, but some variations may occur:
READERBUFFER_SIZE 5
WRITERBUFFER_SIZE 6
uint8_t readerBuffer[READERBUFFER_SIZE]
__at__ 0x20000000;
uint8_t writerBuffer[WRITERBUFFER_SIZE]
__at__ 0x20000005;
// Configuring the READER channel
MYPERIPHERAL->READER.MAXCNT = READERBUFFER_SIZE;
MYPERIPHERAL->READER.PTR = &readerBuffer;
// Configure the WRITER channel
MYPERIPHERAL->WRITER.MAXCNT = WRITEERBUFFER_SIZE;
MYPERIPHERAL->WRITER.PTR = &writerBuffer;
This example shows a peripheral called MYPERIPHERAL that implements two EasyDMA channels - one for
reading called READER, and one for writing called WRITER. When the peripheral is started, it is assumed
that the peripheral will:
• Read 5 bytes from the readerBuffer located in RAM at address 0x20000000.
• Process the data.
• Write no more than 6 bytes back to the writerBuffer located in RAM at address 0x20000005.
The memory layout of these buffers is illustrated in EasyDMA memory layout on page 36.
0x20000000
readerBuffer[0]
readerBuffer[1]
readerBuffer[2]
readerBuffer[3]
0x20000004
readerBuffer[4]
writerBuffer[0]
writerBuffer[1]
writerBuffer[2]
0x20000008
writerBuffer[3]
writerBuffer[4]
writerBuffer[5]
Figure 5: EasyDMA memory layout
The WRITER.MAXCNT register should not be specified larger than the actual size of the buffer
(writerBuffer). Otherwise, the channel would overflow the writerBuffer.
Once an EasyDMA transfer is completed, the AMOUNT register can be read by the CPU to see how many
bytes were transferred. For example, CPU can read MYPERIPHERAL->WRITER.AMOUNT register to see how
many bytes WRITER wrote to RAM.
Note that the PTR register of a READER or WRITER must point to a valid memory region before use. The
reset value of a PTR register is not guaranteed to point to valid memory. See Memory on page 16 for
more information about the different memory regions and EasyDMA connectivity.
4.6.1 EasyDMA error handling
Some errors may occur during DMA handling.
If READER.PTR or WRITER.PTR is not pointing to a valid memory region, an EasyDMA transfer may result
in a HardFault or RAM corruption. See Memory on page 16 for more information about the different
memory regions.
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If several AHB bus masters try to access the same AHB slave at the same time, AHB bus congestion might
occur. An EasyDMA channel is an AHB master. Depending on the peripheral, the peripheral may either stall
and wait for access to be granted, or lose data.
4.6.2 EasyDMA array list
EasyDMA is able to operate in Array List mode.
The Array List mode is implemented in channels where the LIST register is available.
The array list does not provide a mechanism to explicitly specify where the next item in the list is located.
Instead, it assumes that the list is organized as a linear array where items are located one after the other
in RAM.
The EasyDMA Array List can be implemented by using the data structure ArrayList_type as illustrated in
the code example below using a READER EasyDMA channel as an example:
#define BUFFER_SIZE
4
typedef struct ArrayList
{
uint8_t buffer[BUFFER_SIZE];
} ArrayList_type;
ArrayList_type ReaderList[3]
__at__ 0x20000000;
MYPERIPHERAL->READER.MAXCNT = BUFFER_SIZE;
MYPERIPHERAL->READER.PTR = &ReaderList;
MYPERIPHERAL->READER.LIST = MYPERIPHERAL_READER_LIST_ArrayList;
The data structure only includes a buffer with size equal to the size of READER.MAXCNT register. EasyDMA
uses the READER.MAXCNT register to determine when the buffer is full.
READER.PTR = &ReaderList
0x20000000 : ReaderList[0]
buffer[0]
buffer[1]
buffer[2]
buffer[3]
0x20000004 : ReaderList[1]
buffer[0]
buffer[1]
buffer[2]
buffer[3]
0x20000008 : ReaderList[2]
buffer[0]
buffer[1]
buffer[2]
buffer[3]
Figure 6: EasyDMA array list
4.7 AHB multilayer
AHB multilayer enables parallel access paths between multiple masters and slaves in a system. Access is
resolved using priorities.
Each bus master is connected to the slave devices using an interconnection matrix. The bus masters are
assigned priorities. Priorities are used to resolve access when two (or more) bus masters request access to
the same slave device. The following applies:
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• If two (or more) bus masters request access to the same slave device, the master with the highest
priority is granted the access first.
• Bus masters with lower priority are stalled until the higher priority master has completed its
transaction.
• If the higher priority master pauses at any point during its transaction, the lower priority master in
queue is temporarily granted access to the slave device until the higher priority master resumes its
activity.
• Bus masters that have the same priority are mutually exclusive, thus cannot be used concurrently.
Below is a list of bus masters in the system and their priorities.
Bus master name
Description
CPU
SPIM0/SPIS0
Same priority and mutually exclusive
RADIO
CCM/ECB/AAR
Same priority and mutually exclusive
SAADC
UARTE0
TWIM0/TWIS0
Same priority and mutually exclusive
PDM
PWM
Table 11: AHB bus masters (listed in priority order, highest to lowest)
Defined bus masters are the CPU and the peripherals with implemented EasyDMA, and the available
slaves are RAM AHB slaves. How the bus masters and slaves are connected using the interconnection
matrix is illustrated in Memory on page 16.
4.8 Debug
Debug system offers a flexible and powerful mechanism for non-intrusive debugging.
DAP
SWDCLK
External
debugger
CTRL-AP
NVMC
SW-DP
APPROTECT.PALL
SWDIO
UICR
DAP bus
interconnect
AHB
AHB-AP
CxxxPWRUPREQ
CxxxPWRUPRACK
POWER
Power
CPU
ARM Cortex-M4
APB/AHB
Figure 7: Overview
The main features of the debug system are:
• Two-pin serial wire debug (SWD) interface
• Flash patch and breakpoint (FPB) unit supports:
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Core components
• Two literal comparators
• Six instruction comparators
4.8.1 DAP - Debug access port
An external debugger can access the device via the DAP.
The debug access port (DAP) implements a standard ARM® CoreSight™ serial wire debug port (SW-DP),
which implements the serial wire debug protocol (SWD). SWD is a two-pin serial interface, see SWDCLK
and SWDIO in Overview on page 38.
In addition to the default access port in CPU (AHB-AP), the DAP includes a custom control access port
(CTRL-AP). The CTRL-AP is described in more detail in CTRL-AP - Control access port on page 39.
Note:
• The SWDIO line has an internal pull-up resistor.
• The SWDCLK line has an internal pull-down resistor.
4.8.2 CTRL-AP - Control access port
The control access port (CTRL-AP) is a custom access port that enables control of the device when other
access ports in the DAP are disabled by the access port protection.
Access port protection blocks the debugger from read and write access to all CPU registers and memorymapped addresses. See the UICR register APPROTECT on page 35 for more information on enabling
access port protection.
Control access port has the following features:
• Soft reset, see Reset on page 52 for more information
• Disabling of access port protection, which is the reason why CTRL-AP allows control of the device even
when all other access ports in the DAP are disabled by the access port protection
Access port protection is disabled by issuing an ERASEALL command via CTRL-AP. This command will erase
the flash, UICR, and RAM.
4.8.2.1 Registers
Register
Offset
Description
RESET
0x000
Soft reset triggered through CTRL-AP
ERASEALL
0x004
Erase all
ERASEALLSTATUS
0x008
Status register for the ERASEALL operation
APPROTECTSTATUS
0x00C
Status register for access port protection
IDR
0x0FC
CTRL-AP identification register, IDR
Table 12: Register overview
4.8.2.1.1 RESET
Address offset: 0x000
Soft reset triggered through CTRL-AP
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW RESET
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Soft reset triggered through CTRL-AP. See Reset behavior in
POWER chapter for more details.
NoReset
0
Reset is not active
Reset
1
Reset is active. Device is held in reset.
4.8.2.1.2 ERASEALL
Address offset: 0x004
Erase all
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
NoOperation
0
No operation
Erase
1
Erase all flash and RAM
ERASEALL
Erase all flash and RAM
4.8.2.1.3 ERASEALLSTATUS
Address offset: 0x008
Status register for the ERASEALL operation
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Ready
0
ERASEALL is ready
Busy
1
ERASEALL is busy (on-going)
ERASEALLSTATUS
Status register for the ERASEALL operation
4.8.2.1.4 APPROTECTSTATUS
Address offset: 0x00C
Status register for access port protection
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
APPROTECTSTATUS
Status register for access port protection
Enabled
0
Access port protection enabled
Disabled
1
Access port protection not enabled
4.8.2.1.5 IDR
Address offset: 0x0FC
CTRL-AP identification register, IDR
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
E E E E D D D D C C C C C C C B B B B
Reset 0x02880000
0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID
Access
Field
A
R
APID
Value ID
Value
AP identification
B
R
CLASS
Access port (AP) class
A A A A A A A A
Description
NotDefined
0x0
No defined class
MEMAP
0x8
Memory access port
C
R
JEP106ID
JEDEC JEP106 identity code
D
R
JEP106CONT
JEDEC JEP106 continuation code
E
R
REVISION
Revision
4.8.2.2 Electrical specification
4.8.2.2.1 Control access port
Symbol
Description
Rpull
Internal SWDIO and SWDCLK pull up/down resistance
fSWDCLK
SWDCLK frequency
Min.
Typ.
Max.
13
0.125
Units
kΩ
8
MHz
4.8.3 Debug interface mode
Before an external debugger can access either CPU's access port (AHB-AP) or the control access port
(CTRL-AP), the debugger must first request the device to power up via CxxxPWRUPREQ in the SWJ-DP.
If the device is in System OFF when power is requested via CxxxPWRUPREQ, the system will wake up and
the DIF flag in RESETREAS on page 57 will be set. The device is in the debug interface mode as long
as the debugger is requesting power via CxxxPWRUPREQ. Once the debugger stops requesting power
via CxxxPWRUPREQ, the device is back in normal mode. Some peripherals behave differently in Debug
Interface mode compared to normal mode. These differences are described in more detail in the chapters
of the peripherals that are affected.
When a debug session is over, the external debugger must make sure to put the device back into normal
mode since the overall power consumption is higher in debug interface mode than in normal mode.
For details on how to use the debug capabilities, read the debug documentation of your IDE.
4.8.4 Real-time debug
The nRF52811 supports real-time debugging.
Real-time debugging allows interrupts to execute to completion in real time when breakpoints are set
in thread mode or lower priority interrupts. This enables developers to set breakpoints and single-step
through the code without the risk of real-time event-driven threads running at higher priority failing.
For example, this enables the device to continue to service the high-priority interrupts of an external
controller or sensor without failure or loss of state synchronization while the developer steps through
code in a low-priority thread.
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5
Power and clock management
5.1 Power management unit (PMU)
Power and clock management in nRF52811 is designed to automatically ensure maximum power
efficiency.
The core of the power and clock management system is the power management unit (PMU) illustrated in
Power management unit on page 42.
MCU
CPU
External
power sources
Internal
voltage
regulators
PMU
Memory
External
crystals
Internal
oscillators
Peripheral
Figure 8: Power management unit
The PMU automatically detects which power and clock resources are required by the different
components in the system at any given time. It will then start/stop and choose operation modes in supply
regulators and clock sources, without user interaction, to achieve the lowest power consumption possible.
5.2 Current consumption
As the system is being constantly tuned by the Power management unit (PMU) on page 42, estimating
the current consumption of an application can be challenging if the designer is not able to perform
measurements directly on the hardware. To facilitate the estimation process, a set of current consumption
scenarios are provided to show the typical current drawn from the VDD supply.
Each scenario specifies a set of operations and conditions applying to the given scenario. Current
consumption scenarios, common conditions on page 43 shows a set of common conditions used in
all scenarios, unless otherwise stated in the description of a given scenario. All scenarios are listed in
Electrical specification on page 43.
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Power and clock management
Condition
Value
VDD
3V
Temperature
25°C
CPU
WFI (wait for interrupt)/WFE (wait for event) sleep
Peripherals
All idle
Clock
Not running
Regulator
LDO
RAM
Full 24 kB retention
Compiler3
GCC v4.9.3 20150529 (arm-none-eabi-gcc).
Compiler flags: -O0 -falign-functions=16 -fno-strictaliasing -mcpu=cortex-m4 -mfloat-abi=soft -msoftfloat -mthumb.
32 MHz crystal4
SMD 2520, 32 MHz, 10 pF +/- 10 ppm
Table 13: Current consumption scenarios, common conditions
5.2.1 Electrical specification
5.2.1.1 CPU running
Symbol
Description
ICPU0
CPU running CoreMark @64 MHz from flash, Clock = HFXO,
Min.
Typ.
Max.
Units
2.2
mA
Regulator = DCDC
ICPU1
CPU running CoreMark @64 MHz from flash, Clock = HFXO
4.2
mA
ICPU2
CPU running CoreMark @64 MHz from RAM, Clock = HFXO,
2.1
mA
Regulator = DCDC
ICPU3
CPU running CoreMark @64 MHz from RAM, Clock = HFXO
4
mA
ICPU4
CPU running CoreMark @64 MHz from flash, Clock = HFINT,
2
mA
Regulator = DCDC
3
4
Applying only when CPU is running
Applying only when HFXO is running
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Power and clock management
5.2.1.2 Radio transmitting/receiving
Symbol
Description
IRADIO_TX0
Radio transmitting @ 4 dBm output power, 1 Mbps
Min.
Typ.
Max.
Units
8
mA
5.8
mA
3.4
mA
6.1
mA
10.5
mA
5.1
mA
10.8
mA
Bluetooth low energy mode, Clock = HFXO, Regulator =
DCDC
IRADIO_TX1
Radio transmitting @ 0 dBm output power, 1 Mbps
Bluetooth low energy mode, Clock = HFXO, Regulator =
DCDC
IRADIO_TX2
Radio transmitting @ -40 dBm output power, 1 Mbps
Bluetooth low energy mode, Clock = HFXO, Regulator =
DCDC
IRADIO_RX0
Radio receiving @ 1 Mbps Bluetooth low energy mode,
Clock = HFXO, Regulator = DCDC
IRADIO_TX3
Radio transmitting @ 0 dBm output power, 1 Mbps
Bluetooth low energy mode, Clock = HFXO
IRADIO_TX4
Radio transmitting @ -40 dBm output power, 1 Mbps
Bluetooth low energy mode, Clock = HFXO
IRADIO_RX1
Radio receiving @ 1 Mbps Bluetooth low energy mode,
Clock = HFXO
15
14
Current consumption [mA]
13
12
11
10
9
8
7
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
Supply voltage [V]
-40 ºC
25 ºC
85 ºC
Figure 9: Radio transmitting @ 4 dBm output power, 1 Mbps Bluetooth
low energy mode, Clock = HFXO, Regulator = DCDC (typical values)
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3.6
Power and clock management
10
9.5
9
Current consumption [mA]
8.5
8
7.5
7
6.5
6
5.5
5
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Supply voltage [V]
-40 ºC
25 ºC
85 ºC
Figure 10: Radio transmitting @ 0 dBm output power, 1 Mbps Bluetooth
low energy mode, Clock = HFXO, Regulator = DCDC (typical values)
5.2.1.3 Sleep
Symbol
Description
ION_RAMOFF_EVENT
System ON, No RAM retention, Wake on any event
Min.
Typ.
0.6
Max.
Units
µA
ION_RAMON_EVENT
System ON, Full 24 kB RAM retention, Wake on any event
0.8
µA
ION_RAMON_POF
System ON, Full 24 kB RAM retention, Wake on any event,
0.8
µA
3.3
µA
0.8
µA
1.5
µA
1.4
µA
1.1
µA
1.0
µA
Power fail comparator enabled
ION_RAMON_GPIOTE
System ON, Full 24 kB RAM retention, Wake on GPIOTE input
(Event mode)
ION_RAMON_GPIOTEPORTSystem ON, Full 24 kB RAM retention, Wake on GPIOTE
PORT event
ION_RAMON_RTC
System ON, Full 24 kB RAM retention, Wake on RTC (running
from LFRC clock)
ION_RAMOFF_RTC
System ON, No RAM retention, Wake on RTC (running from
LFRC clock)
ION_RAMON_RTC_LFXO System ON, Full 24 kB RAM retention, Wake on RTC (running
from LFXO clock)
ION_RAMOFF_RTC_LFXO System ON, No RAM retention, Wake on RTC (running from
LFXO clock)
IOFF_RAMOFF_RESET
System OFF, No RAM retention, Wake on reset
0.3
µA
IOFF_RAMON_RESET
System OFF, Full 24 kB RAM retention, Wake on reset
0.5
µA
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Power and clock management
2.5
Current consumption [µA]
2
1.5
1
0.5
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Supply voltage [V]
-40 ºC
25 ºC
85 ºC
Figure 11: System OFF, No RAM retention, Wake on reset (typical values)
16
14
Current consumption [µA]
12
10
8
6
4
2
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Supply voltage [V]
-40 ºC
25 ºC
85 ºC
Figure 12: System ON, Full 24 kB RAM retention, Wake on any event (typical values)
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Power and clock management
5.2.1.4 Compounded
Symbol
Description
IS0
CPU running CoreMark from flash, Radio transmitting @ 0
Min.
Typ.
Max.
Units
7.4
mA
7.6
mA
13.8
mA
14.2
mA
dBm output power, 1 Mbps Bluetooth low energy mode,
Clock = HFXO, Regulator = DCDC
IS1
CPU running CoreMark from flash, Radio receiving @ 1
Mbps Bluetooth low energy mode, Clock = HFXO, Regulator
= DCDC
IS2
CPU running CoreMark from flash, Radio transmitting @ 0
dBm output power, 1 Mbps Bluetooth low energy mode,
Clock = HFXO
IS3
CPU running CoreMark from flash, Radio receiving @ 1
Mbps Bluetooth low energy mode, Clock = HFXO
5.2.1.5 TIMER running
Symbol
Description
ITIMER0
One TIMER instance running @ 1 MHz, Clock = HFINT
Min.
Typ.
432
Max.
Units
µA
ITIMER1
Two TIMER instances running @ 1 MHz, Clock = HFINT
432
µA
ITIMER2
One TIMER instance running @ 1 MHz, Clock = HFXO
730
µA
ITIMER3
One TIMER instance running @ 16 MHz, Clock = HFINT
495
µA
ITIMER4
One TIMER instance running @ 16 MHz, Clock = HFXO
792
µA
5.2.1.6 RNG active
Symbol
Description
IRNG0
RNG running
Min.
Typ.
Max.
539
Units
µA
5.2.1.7 TEMP active
Symbol
Description
ITEMP0
TEMP started
Min.
Typ.
Max.
998
Units
µA
5.2.1.8 SAADC active
Symbol
Description
ISAADC,RUN
SAADC sampling @ 16 ksps, Acquisition time = 20 µs, Clock =
Min.
Typ.
Max.
1.1
Units
mA
HFXO, Regulator = DCDC
5.2.1.9 COMP active
Symbol
Description
ICOMP,LP
COMP enabled, low power mode
17.2
µA
ICOMP,NORM
COMP enabled, normal mode
21
µA
ICOMP,HS
COMP enabled, high-speed mode
28.7
µA
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47
Typ.
Max.
Units
Power and clock management
5.2.1.10 WDT active
Symbol
Description
IWDT,STARTED
WDT started
Min.
Typ.
Max.
1.3
Units
µA
5.3 POWER — Power supply
This device has the following power supply features:
•
•
•
•
•
•
On-chip LDO and DC/DC regulators
Global System ON/OFF modes with individual RAM section power control
Analog or digital pin wakeup from System OFF
Supervisor HW to manage power on reset, brownout, and power fail
Auto-controlled refresh modes for LDO and DC/DC regulators to maximize efficiency
Automatic switching between LDO and DC/DC regulator based on load to maximize efficiency
Note: Two additional external passive components are required to use the DC/DC regulator.
5.3.1 Regulators
The following internal power regulator alternatives are supported:
• Internal LDO regulator
• Internal DC/DC regulator
The LDO is the default regulator.
The DC/DC regulator can be used as an alternative to the LDO regulator and is enabled through the
DCDCEN on page 59 register. Using the DC/DC regulator will reduce current consumption compared to
when using the LDO regulator, but the DC/DC regulator requires an external LC filter to be connected, as
shown in DC/DC regulator setup on page 49.
POWER
DCDCEN
REG
Supply
LDO
1.3V System power
VDD
DC/DC
DCC
DEC4
Figure 13: LDO regulator setup
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GND
Power and clock management
POWER
DCDCEN
REG
Supply
LDO
1.3V System power
VDD
DC/DC
DCC
DEC4
GND
Figure 14: DC/DC regulator setup
5.3.2 System OFF mode
System OFF is the deepest power saving mode the system can enter. In this mode, the system’s core
functionality is powered down and all ongoing tasks are terminated.
The device can be put into System OFF mode using the register SYSTEMOFF on page 57. When in
System OFF mode, the device can be woken up through one of the following signals:
1. The DETECT signal, optionally generated by the GPIO peripheral
2. A reset
When the system wakes up from System OFF mode, it gets reset. For more details, see Reset behavior on
page 53.
One or more RAM sections can be retained in System OFF mode, depending on the settings in the
RAM[n].POWER registers.
RAM[n].POWER are retained registers, see Reset behavior. Note that these registers are usually
overwritten by the startup code provided with the nRF application examples.
Before entering System OFF mode, the user must make sure that all on-going EasyDMA transactions have
been completed. This is usually accomplished by making sure that the EasyDMA enabled peripheral is not
active when entering System OFF.
5.3.2.1 Emulated System OFF mode
If the device is in debug interface mode, System OFF will be emulated to secure that all required resources
needed for debugging are available during System OFF.
See Debug on page 38 for more information. Required resources needed for debugging include the
following key components: Debug on page 38, CLOCK — Clock control on page 61, POWER — Power
supply on page 48, NVMC — Non-volatile memory controller on page 19, CPU, Flash, and RAM. Since
the CPU is kept on in an emulated System OFF mode, it is recommended to add an infinite loop directly
after entering System OFF, to prevent the CPU from executing code that normally should not be executed.
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5.3.3 System ON mode
System ON is the default state after power-on reset. In System ON, all functional blocks such as the CPU or
peripherals can be in IDLE or RUN mode, depending on the configuration set by the software and the state
of the application executing.
Register RESETREAS on page 57 provides information about the source causing the wakeup or reset.
The system can switch the appropriate internal power sources on and off, depending on how much power
is needed at any given time. The power requirement of a peripheral is directly related to its activity level,
and the activity level of a peripheral is usually raised and lowered when specific tasks are triggered or
events are generated.
5.3.3.1 Sub power modes
In System ON mode, when both the CPU and all the peripherals are in IDLE mode, the system can reside in
one of the two sub power modes.
The sub power modes are:
• Constant Latency
• Low-power
In Constant Latency mode, the CPU wakeup latency and the PPI task response are constant and kept at
a minimum. This is secured by forcing a set of basic resources to be turned on while in sleep. Having a
constant and predictable latency is at the cost of having increased power consumption. The Constant
Latency mode is selected by triggering the CONSTLAT task.
In Low-power mode, the automatic power management system described in System ON mode on page
50 ensures that the most efficient supply option is chosen to save most power. Having the lowest
power possible is at the cost of having a varying CPU wakeup latency and PPI task response. The Lowpower mode is selected by triggering the LOWPWR task.
When the system enters System ON mode, it is by default in Low-power sub power mode.
5.3.4 Power supply supervisor
The power supply supervisor initializes the system at power-on and provides an early warning of
impending power failure.
In addition, the power supply supervisor puts the system in a reset state if the supply voltage is too low for
safe operation (brownout). The power supply supervisor is illustrated in Power supply supervisor on page
51.
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Power and clock management
VDD
C
Power on reset
R
VBOR
POFCON
Brownout reset
1.7V
...........
MUX
POFWARN
Vpof
2.8V
Figure 15: Power supply supervisor
5.3.4.1 Power-fail comparator
The power-fail comparator (POF) can provide the CPU with an early warning of impending power failure. It
will not reset the system, but give the CPU time to prepare for an orderly power-down.
The comparator features a hysteresis of VHYST, as illustrated in Power-fail comparator (BOR = Brownout
reset) on page 51. The threshold VPOF is set in register POFCON on page 58. If the POF is enabled
and the supply voltage falls below VPOF, the POFWARN event will be generated. This event will also be
generated if the supply voltage is already below VPOF at the time the POF is enabled, or if VPOF is reconfigured to a level above the supply voltage.
If power-fail warning is enabled and the supply voltage is below VPOF the power-fail comparator will
prevent the NVMC from performing write operations to the NVM. See NVMC — Non-volatile memory
controller on page 19 for more information about the NVMC.
VDD
VPOF+VHYST
VPOF
1.7V
POFWARN
POFWARN
MCU
t
BOR
Figure 16: Power-fail comparator (BOR = Brownout reset)
To save power, the power-fail comparator is not active in System OFF or in System ON when HFCLK is not
running.
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5.3.5 RAM power control
The RAM power control registers are used for configuring the following:
• The RAM sections to be retained during System OFF
• The RAM sections to be retained and accessible during System ON
In System OFF, retention of a RAM section is configured in the RETENTION field of the corresponding
RAM[n] register.
In System ON, retention and accessibility for a RAM section is configured in the RETENTION and POWER
fields of the corresponding RAM[n] register.
The following table summarizes the behavior of these registers.
Configuration
RAM section status
System on/off
RAM[n].POWER.POWER
RAM[n].POWER.RETENTION
Accessible
Retained
Off
x
Off
No
No
Off
x
On
No
Yes
On
Off
Off
No
No
On
Off1
On
No
Yes
On
On
x
Yes
Yes
Table 14: RAM section configuration. x = don't care.
The advantage of not retaining RAM contents is that the overall current consumption is reduced.
See chapter Memory on page 16 for more information on RAM sections.
5.3.6 Reset
There are multiple sources that may trigger a reset.
After a reset has occurred, register RESETREAS can be read to determine which source generated the
reset.
5.3.6.1 Power-on reset
The power-on reset generator initializes the system at power-on.
The system is held in reset state until the supply has reached the minimum operating voltage and the
internal voltage regulators have started.
A step increase in supply voltage of 300 mV or more, with rise time of 300 ms or less, within the valid
supply range, may result in a system reset.
5.3.6.2 Pin reset
A pin reset is generated when the physical reset pin on the device is asserted.
Pin reset is configured via the PSELRESET[n] registers.
Note: Pin reset is not available on all pins.
5.3.6.3 Wakeup from System OFF mode reset
The device is reset when it wakes up from System OFF mode.
1
Not useful setting. RAM section power off gives negligible reduction in current consumption when
retention is on.
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The debug access port (DAP) is not reset following a wake up from System OFF mode if the device is in
Debug Interface mode. See chapter Debug on page 38 for more information.
5.3.6.4 Soft reset
A soft reset is generated when the SYSRESETREQ bit of the Application Interrupt and Reset Control
Register (AIRCR register) in the ARM® core is set.
Refer to ARM documentation for more details.
A soft reset can also be generated via the RESET on page 39 register in the CTRL-AP.
5.3.6.5 Watchdog reset
A Watchdog reset is generated when the watchdog times out.
See chapter WDT — Watchdog timer on page 410 for more information.
5.3.6.6 Brown-out reset
The brown-out reset generator puts the system in reset state if the supply voltage drops below the
brownout reset (BOR) threshold.
Refer to section Power fail comparator on page 61 for more information.
5.3.7 Retained registers
A retained register is a register that will retain its value in System OFF mode and through a reset,
depending on reset source. See individual peripheral chapters for information of which registers are
retained for the various peripherals.
5.3.8 Reset behavior
Reset source
Reset target
CPU
Peripherals
GPIO
Debuga
SWJ-DP
RAM
WDT
Retained
RESETREAS
registers
CPU lockup 5
x
x
x
Soft reset
x
x
x
Wakeup from System OFF
x
x
Watchdog reset 8
x
x
Pin reset
x
Brownout reset
x
Power on reset
x
x6
x7
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
mode reset
Note: The RAM is never reset, but depending on reset source, RAM content may be corrupted.
a
5
6
7
8
All debug components excluding SWJ-DP. See Debug on page 38 chapter for more information about
the different debug components in the system.
Reset from CPU lockup is disabled if the device is in debug interface mode. CPU lockup is not possible
in System OFF.
The Debug components will not be reset if the device is in debug interface mode.
RAM is not reset on wakeup from OFF mode, but depending on settings in the RAM register parts, or
the whole RAM, may not be retained after the device has entered System OFF mode.
Watchdog reset is not available in System OFF.
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5.3.9 Registers
Base address
Peripheral
Instance
Description
Configuration
0x40000000
POWER
POWER
Power control
For 24 kB RAM variant, only RAM[0].x to
RAM[2].x registers are in use.
Table 15: Instances
Register
Offset
Description
TASKS_CONSTLAT
0x078
Enable Constant Latency mode
TASKS_LOWPWR
0x07C
Enable Low-power mode (variable latency)
EVENTS_POFWARN
0x108
Power failure warning
EVENTS_SLEEPENTER
0x114
CPU entered WFI/WFE sleep
EVENTS_SLEEPEXIT
0x118
CPU exited WFI/WFE sleep
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
RESETREAS
0x400
Reset reason
SYSTEMOFF
0x500
System OFF register
POFCON
0x510
Power failure comparator configuration
GPREGRET
0x51C
General purpose retention register
GPREGRET2
0x520
General purpose retention register
DCDCEN
0x578
DC/DC enable register
RAM[0].POWER
0x900
RAM0 power control register. The RAM size will vary depending on product variant, and the
RAM0 register will only be present if the corresponding RAM AHB slave is present on the
device.
RAM[0].POWERSET
0x904
RAM0 power control set register
RAM[0].POWERCLR
0x908
RAM0 power control clear register
RAM[1].POWER
0x910
RAM1 power control register. The RAM size will vary depending on product variant, and the
RAM1 register will only be present if the corresponding RAM AHB slave is present on the
device.
RAM[1].POWERSET
0x914
RAM1 power control set register
RAM[1].POWERCLR
0x918
RAM1 power control clear register
RAM[2].POWER
0x920
RAM2 power control register. The RAM size will vary depending on product variant, and the
RAM2 register will only be present if the corresponding RAM AHB slave is present on the
device.
RAM[2].POWERSET
0x924
RAM2 power control set register
RAM[2].POWERCLR
0x928
RAM2 power control clear register
RAM[3].POWER
0x930
RAM3 power control register. The RAM size will vary depending on product variant, and the
RAM3 register will only be present if the corresponding RAM AHB slave is present on the
device.
RAM[3].POWERSET
0x934
RAM3 power control set register
RAM[3].POWERCLR
0x938
RAM3 power control clear register
RAM[4].POWER
0x940
RAM4 power control register. The RAM size will vary depending on product variant, and the
RAM4 register will only be present if the corresponding RAM AHB slave is present on the
device.
RAM[4].POWERSET
0x944
RAM4 power control set register
RAM[4].POWERCLR
0x948
RAM4 power control clear register
RAM[5].POWER
0x950
RAM5 power control register. The RAM size will vary depending on product variant, and the
RAM5 register will only be present if the corresponding RAM AHB slave is present on the
device.
RAM[5].POWERSET
0x954
RAM5 power control set register
RAM[5].POWERCLR
0x958
RAM5 power control clear register
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Register
Offset
Description
RAM[6].POWER
0x960
RAM6 power control register. The RAM size will vary depending on product variant, and the
RAM6 register will only be present if the corresponding RAM AHB slave is present on the
device.
RAM[6].POWERSET
0x964
RAM6 power control set register
RAM[6].POWERCLR
0x968
RAM6 power control clear register
RAM[7].POWER
0x970
RAM7 power control register. The RAM size will vary depending on product variant, and the
RAM7 register will only be present if the corresponding RAM AHB slave is present on the
device.
RAM[7].POWERSET
0x974
RAM7 power control set register
RAM[7].POWERCLR
0x978
RAM7 power control clear register
Table 16: Register overview
5.3.9.1 TASKS_CONSTLAT
Address offset: 0x078
Enable Constant Latency mode
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Trigger
1
Description
TASKS_CONSTLAT
Enable Constant Latency mode
Trigger task
5.3.9.2 TASKS_LOWPWR
Address offset: 0x07C
Enable Low-power mode (variable latency)
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Trigger
1
Description
TASKS_LOWPWR
Enable Low-power mode (variable latency)
Trigger task
5.3.9.3 EVENTS_POFWARN
Address offset: 0x108
Power failure warning
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_POFWARN
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Value ID
Value
Description
Power failure warning
NotGenerated
0
Event not generated
Generated
1
Event generated
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Power and clock management
5.3.9.4 EVENTS_SLEEPENTER
Address offset: 0x114
CPU entered WFI/WFE sleep
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_SLEEPENTER
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
NotGenerated
0
Event not generated
Generated
1
Event generated
CPU entered WFI/WFE sleep
5.3.9.5 EVENTS_SLEEPEXIT
Address offset: 0x118
CPU exited WFI/WFE sleep
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_SLEEPEXIT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
NotGenerated
0
Event not generated
Generated
1
Event generated
CPU exited WFI/WFE sleep
5.3.9.6 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
C B
Reset 0x00000000
ID
Access
Field
A
RW POFWARN
B
C
Value ID
Value
Description
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Write '1' to enable interrupt for event POFWARN
RW SLEEPENTER
Write '1' to enable interrupt for event SLEEPENTER
RW SLEEPEXIT
Write '1' to enable interrupt for event SLEEPEXIT
5.3.9.7 INTENCLR
Address offset: 0x308
Disable interrupt
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0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Power and clock management
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
C B
Reset 0x00000000
ID
Access
Field
A
RW POFWARN
B
C
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Write '1' to disable interrupt for event POFWARN
RW SLEEPENTER
Write '1' to disable interrupt for event SLEEPENTER
RW SLEEPEXIT
Write '1' to disable interrupt for event SLEEPEXIT
5.3.9.8 RESETREAS
Address offset: 0x400
Reset reason
Unless cleared, the RESETREAS register will be cumulative. A field is cleared by writing '1' to it. If none
of the reset sources are flagged, this indicates that the chip was reset from the on-chip reset generator,
which will indicate a power-on-reset or a brownout reset.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
F
Reset 0x00000000
ID
Access
Field
A
RW RESETPIN
B
C
D
E
E
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
NotDetected
0
Not detected
Detected
1
Detected
Reset from pin-reset detected
RW DOG
Reset from watchdog detected
NotDetected
0
Not detected
Detected
1
Detected
NotDetected
0
Not detected
Detected
1
Detected
NotDetected
0
Not detected
Detected
1
Detected
RW SREQ
Reset from soft reset detected
RW LOCKUP
Reset from CPU lock-up detected
RW OFF
Reset due to wake up from System OFF mode when wakeup
is triggered from DETECT signal from GPIO
F
NotDetected
0
Not detected
Detected
1
Detected
RW DIF
Reset due to wake up from System OFF mode when wakeup
is triggered from entering into debug interface mode
NotDetected
0
Not detected
Detected
1
Detected
5.3.9.9 SYSTEMOFF
Address offset: 0x500
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Power and clock management
System OFF register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
SYSTEMOFF
Enable System OFF mode
Enter
1
Enable System OFF mode
5.3.9.10 POFCON
Address offset: 0x510
Power failure comparator configuration
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
B B B B A
Reset 0x00000000
ID
Access
Field
A
RW POF
B
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Disabled
0
Disable
Enabled
1
Enable
V17
4
Set threshold to 1.7 V
V18
5
Set threshold to 1.8 V
V19
6
Set threshold to 1.9 V
V20
7
Set threshold to 2.0 V
V21
8
Set threshold to 2.1 V
V22
9
Set threshold to 2.2 V
V23
10
Set threshold to 2.3 V
V24
11
Set threshold to 2.4 V
V25
12
Set threshold to 2.5 V
V26
13
Set threshold to 2.6 V
V27
14
Set threshold to 2.7 V
V28
15
Set threshold to 2.8 V
Enable or disable power failure comparator
RW THRESHOLD
Power failure comparator threshold setting
5.3.9.11 GPREGRET
Address offset: 0x51C
General purpose retention register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
RW GPREGRET
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
General purpose retention register
This register is a retained register
5.3.9.12 GPREGRET2
Address offset: 0x520
General purpose retention register
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
RW GPREGRET
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
General purpose retention register
This register is a retained register
5.3.9.13 DCDCEN
Address offset: 0x578
DC/DC enable register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW DCDCEN
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Disabled
0
Disable
Enabled
1
Enable
Enable or disable DC/DC converter
5.3.9.14 RAM[n].POWER (n=0..7)
Address offset: 0x900 + (n × 0x10)
RAMn power control register. The RAM size will vary depending on product variant, and the RAMn register
will only be present if the corresponding RAM AHB slave is present on the device.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
D C
Reset 0x0000FFFF
ID
Access
Field
A-B
RW S[i]POWER (i=0..1)
Value ID
Value
Description
Keep RAM section Si ON or OFF in System ON mode.
RAM sections are always retained when ON, but can
also be retained when OFF dependent on the settings in
SiRETENTION. All RAM sections will be OFF in System OFF
mode.
C-D
Off
0
Off
On
1
On
RW S[i]RETENTION (i=0..1)
Keep retention on RAM section Si when RAM section is in
OFF
Off
0
Off
On
1
On
5.3.9.15 RAM[n].POWERSET (n=0..7)
Address offset: 0x904 + (n × 0x10)
RAMn power control set register
When read, this register will return the value of the POWER register.
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Power and clock management
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
D C
Reset 0x0000FFFF
ID
Access
Field
A-B
W
C-D
W
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value ID
Value
On
1
Description
S[i]POWER (i=0..1)
Keep RAM section Si of RAMn on or off in System ON mode
On
S[i]RETENTION (i=0..1)
Keep retention on RAM section Si when RAM section is
switched off
On
1
On
5.3.9.16 RAM[n].POWERCLR (n=0..7)
Address offset: 0x908 + (n × 0x10)
RAMn power control clear register
When read, this register will return the value of the POWER register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
D C
Reset 0x0000FFFF
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID
Access
Field
Value ID
A-B
W
S[i]POWER (i=0..1)
C-D
W
S[i]RETENTION (i=0..1)
Value
Description
Keep RAM section Si of RAMn on or off in System ON mode
Off
1
Off
Keep retention on RAM section Si when RAM section is
switched off
Off
1
Off
5.3.10 Electrical specification
5.3.10.1 Device startup times
Symbol
Description
tPOR
Time in Power on Reset after VDD reaches 1.7 V for all
Min.
Typ.
Max.
Units
supply voltages and temperatures. Dependent on supply rise
time. 9
tPOR,10us
VDD rise time 10us
1
ms
tPOR,10ms
VDD rise time 10ms
9
ms
tPOR,60ms
VDD rise time 60ms
23
ms
tPINR
If a GPIO pin is configured as reset, the maximum time
taken to pull up the pin and release reset after power on
reset. Dependent on the pin capacitive load (C)10: t=5RC, R
= 13kOhm
tPINR,500nF
C = 500nF
32.5
ms
tPINR,10uF
C = 10uF
650
ms
tR2ON
Time from reset to ON (CPU execute)
tR2ON,NOTCONF
If reset pin not configured
tPOR
ms
tR2ON,CONF
If reset pin configured
tPOR +
ms
tPINR
9
10
A step increase in supply voltage of 300 mV or more, with rise time of 300 ms or less, within the valid
supply range, may result in a system reset.
To decrease maximum time a device could hold in reset, a strong external pullup resistor can be
used.
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Symbol
Description
Min.
Typ.
Max.
Units
tOFF2ON
Time from OFF to CPU execute
16.5
µs
tIDLE2CPU
Time from IDLE to CPU execute
3.0
µs
tEVTSET,CL1
Time from HW event to PPI event in Constant Latency
0.0625
µs
0.0625
µs
System ON mode
tEVTSET,CL0
Time from HW event to PPI event in Low Power System ON
mode
5.3.10.2 Power fail comparator
Symbol
Description
Min.
VPOF
Nominal power level warning thresholds (falling supply
1.7
Typ.
Max.
Units
2.8
V
±5
%
voltage). Levels are configurable between Min. and Max. in
100mV increments.
VPOFTOL
Threshold voltage tolerance
±1
VPOFHYST
Threshold voltage hysteresis
50
VBOR,OFF
Brown out reset voltage range SYSTEM OFF mode
1.2
1.7
V
VBOR,ON
Brown out reset voltage range SYSTEM ON mode
1.48
1.7
V
mV
5.4 CLOCK — Clock control
The clock control system can source the system clocks from a range of internal or external high and low
frequency oscillators and distribute them to modules based upon a module’s individual requirements.
Clock distribution is automated and grouped independently by module to limit current consumption in
unused branches of the clock tree.
Listed here are the main features for CLOCK:
•
•
•
•
•
•
•
64 MHz on-chip oscillator
64 MHz crystal oscillator, using external 32 MHz crystal
32.768 kHz +/-500 ppm RC oscillator
32.768 kHz crystal oscillator, using external 32.768 kHz crystal
32.768 kHz oscillator synthesized from 64 MHz oscillator
Firmware (FW) override control of oscillator activity for low latency start up
Automatic oscillator and clock control, and distribution for ultra-low power
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HFCLKSTART
HFCLKSTOP
LFCLKSTART
LFCLKSTOP
CLOCK
HFINT
Internal oscillator
PCLK1M
PCLK16M
XC1
PCLK32M
HFCLK
Clock control
HFXO
Crystal oscillator
32 MHz
HCLK64M
XC2
LFRC
RC oscillator
CAL
SYNT
XL1
LFXO
Crystal oscillator
32.768 kHz
LFCLK
Clock control
PCLK32KI
XL2
HFCLKSTARTED
LFCLKSTARTED
Figure 17: Clock control
5.4.1 HFCLK clock controller
The HFCLK clock controller provides the following clocks to the system.
•
•
•
•
HCLK64M: 64 MHz CPU clock
PCLK1M: 1 MHz peripheral clock
PCLK16M: 16 MHz peripheral clock
PCLK32M: 32 MHz peripheral clock
The HFCLK controller supports the following high frequency clock (HFCLK) sources:
• 64 MHz internal oscillator (HFINT)
• 64 MHz crystal oscillator (HFXO)
For illustration, see Clock control on page 62.
When the system requests one or more clocks from the HFCLK controller, the HFCLK controller will
automatically provide them. If the system does not request any clocks provided by the HFCLK controller,
the controller will enter a power saving mode.
These clocks are only available when the system is in ON mode. When the system enters ON mode, the
internal oscillator (HFINT) clock source will automatically start to be able to provide the required HFCLK
clock(s) for the system.
The HFINT will be used when HFCLK is requested and HFXO has not been started. The HFXO is started by
triggering the HFCLKSTART task and stopped using the HFCLKSTOP task. A HFCLKSTARTED event will be
generated when the HFXO has started and its frequency is stable.
The HFXO must be running to use the RADIO or the calibration mechanism associated with the 32.768 kHz
RC oscillator.
5.4.1.1 64 MHz crystal oscillator (HFXO)
The 64 MHz crystal oscillator (HFXO) is controlled by a 32 MHz external crystal
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The crystal oscillator is designed for use with an AT-cut quartz crystal in parallel resonant mode. To achieve
correct oscillation frequency, the load capacitance must match the specification in the crystal data sheet.
Circuit diagram of the 64 MHz crystal oscillator on page 63 shows how the 32 MHz crystal is connected
to the 64 MHz crystal oscillator.
XC1
XC2
C1
C2
32 MHz
crystal
Figure 18: Circuit diagram of the 64 MHz crystal oscillator
The load capacitance (CL) is the total capacitance seen by the crystal across its terminals and is given by:
C1 and C2 are ceramic SMD capacitors connected between each crystal terminal and ground. For more
information, see Reference circuitry on page 425. Cpcb1 and Cpcb2 are stray capacitances on the PCB. Cpin
is the pin input capacitance on the XC1 and XC2 pins. See table 64 MHz crystal oscillator (HFXO) on page
72. The load capacitors C1 and C2 should have the same value.
For reliable operation, the crystal load capacitance, shunt capacitance, equivalent series resistance, and
drive level must comply with the specifications in table 64 MHz crystal oscillator (HFXO) on page 72. It
is recommended to use a crystal with lower than maximum load capacitance and/or shunt capacitance. A
low load capacitance will reduce both start up time and current consumption.
5.4.2 LFCLK clock controller
The system supports several low frequency clock sources.
As illustrated in Clock control on page 62, the system supports the following low frequency clock
sources:
• 32.768 kHz RC oscillator (LFRC)
• 32.768 kHz crystal oscillator (LFXO)
• 32.768 kHz synthesized from HFCLK (LFSYNT)
The LFCLK clock is started by first selecting the preferred clock source in register LFCLKSRC on page 71
and then triggering the LFCLKSTART task. If the LFXO is selected as the clock source, the LFCLK will initially
start running from the 32.768 kHz LFRC while the LFXO is starting up and automatically switch to using the
LFXO once this oscillator is running. The LFCLKSTARTED event will be generated when the LFXO has been
started.
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The LFCLK clock is stopped by triggering the LFCLKSTOP task.
It is not allowed to write to register LFCLKSRC on page 71 when the LFCLK is running.
A LFCLKSTOP task will stop the LFCLK oscillator. However, the LFCLKSTOP task can only be triggered after
the STATE field in register LFCLKSTAT on page 71 indicates a 'LFCLK running' state.
The LFCLK clock controller and all of the LFCLK clock sources are always switched off when in OFF mode.
5.4.2.1 32.768 kHz RC oscillator (LFRC)
The default source of the low frequency clock (LFCLK) is the 32.768 kHz RC oscillator (LFRC).
The LFRC frequency will be affected by variation in temperature. The LFRC oscillator can be calibrated to
improve accuracy by using the HFXO as a reference oscillator during calibration. See Table 32.768 kHz RC
oscillator (LFRC) on page 73 for details on the default and calibrated accuracy of the LFRC oscillator.
The LFRC oscillator does not require additional external components.
5.4.2.2 Calibrating the 32.768 kHz RC oscillator
After the 32.768 kHz RC oscillator is started and running, it can be calibrated by triggering the CAL task. In
this case, the HFCLK will be temporarily switched on and used as a reference.
A DONE event will be generated when calibration has finished. The calibration mechanism will only work
as long as HFCLK is generated from the HFCLK crystal oscillator, it is therefore necessary to explicitly start
this crystal oscillator before calibration can be started, see HFCLKSTART task.
It is not allowed to stop the LFRC during an ongoing calibration.
5.4.2.3 Calibration timer
The calibration timer can be used to time the calibration interval of the 32.768 kHz RC oscillator.
The calibration timer is started by triggering the CTSTART task and stopped by triggering the CTSTOP task.
The calibration timer will always start counting down from the value specified in CTIV and generate a CTTO
timeout event when it reaches 0. The Calibration timer will stop by itself when it reaches 0.
CTSTART
CTSTOP
Calibration
timer
CTIV
CTTO
Figure 19: Calibration timer
Due to limitations in the calibration timer, only one task related to calibration, that is, CAL, CTSTART and
CTSTOP, can be triggered for every period of LFCLK.
5.4.2.4 32.768 kHz crystal oscillator (LFXO)
For higher LFCLK accuracy the low frequency crystal oscillator (LFXO) must be used.
The following external clock sources are supported:
• Low swing clock signal applied to the XL1 pin. The XL2 pin shall then be grounded.
• Rail-to-rail clock signal applied to the XL1 pin. The XL2 pin shall then be grounded or left unconnected.
The LFCLKSRC on page 71 register controls the clock source, and its allowed swing. The truth table for
various situations is as follows:
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SRC
EXTERNAL
BYPASS
Comment
0
0
0
Normal operation, RC is source
0
0
1
DO NOT USE
0
1
X
DO NOT USE
1
0
0
Normal XTAL operation
1
1
0
Apply external low swing signal to XL1, ground XL2
1
1
1
Apply external full swing signal to XL1, leave XL2 grounded or unconnected
1
0
1
DO NOT USE
2
0
0
Normal operation, synth is source
2
0
1
DO NOT USE
2
1
X
DO NOT USE
Table 17: LFCLKSRC configuration depending on clock source
To achieve correct oscillation frequency, the load capacitance must match the specification in the crystal
data sheet. Circuit diagram of the 32.768 kHz crystal oscillator on page 65 shows the LFXO circuitry.
XL1
XL2
C1
C2
32.768 kHz
crystal
Figure 20: Circuit diagram of the 32.768 kHz crystal oscillator
The load capacitance (CL) is the total capacitance seen by the crystal across its terminals and is given by:
C1 and C2 are ceramic SMD capacitors connected between each crystal terminal and ground. Cpcb1 and
Cpcb2 are stray capacitances on the PCB. Cpin is the pin input capacitance on the XC1 and XC2 pins (see
32.768 kHz crystal oscillator (LFXO) on page 73). The load capacitors C1 and C2 should have the same
value.
For more information, see Reference circuitry on page 425.
5.4.2.5 32.768 kHz synthesized from HFCLK (LFSYNT)
LFCLK can also be synthesized from the HFCLK clock source. The accuracy of LFCLK will then be the
accuracy of the HFCLK.
Using the LFSYNT clock avoids the requirement for a 32.768 kHz crystal, but increases average power
consumption as the HFCLK will need to be requested in the system.
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5.4.3 Registers
Base address
Peripheral
Instance
Description
0x40000000
CLOCK
CLOCK
Clock control
Configuration
Table 18: Instances
Register
Offset
Description
TASKS_HFCLKSTART
0x000
Start HFCLK crystal oscillator
TASKS_HFCLKSTOP
0x004
Stop HFCLK crystal oscillator
TASKS_LFCLKSTART
0x008
Start LFCLK source
TASKS_LFCLKSTOP
0x00C
Stop LFCLK source
TASKS_CAL
0x010
Start calibration of LFRC oscillator
TASKS_CTSTART
0x014
Start calibration timer
TASKS_CTSTOP
0x018
Stop calibration timer
EVENTS_HFCLKSTARTED
0x100
HFCLK oscillator started
EVENTS_LFCLKSTARTED
0x104
LFCLK started
EVENTS_DONE
0x10C
Calibration of LFCLK RC oscillator complete event
EVENTS_CTTO
0x110
Calibration timer timeout
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
HFCLKRUN
0x408
Status indicating that HFCLKSTART task has been triggered
HFCLKSTAT
0x40C
HFCLK status
LFCLKRUN
0x414
Status indicating that LFCLKSTART task has been triggered
LFCLKSTAT
0x418
LFCLK status
LFCLKSRCCOPY
0x41C
Copy of LFCLKSRC register, set when LFCLKSTART task was triggered
LFCLKSRC
0x518
Clock source for the LFCLK
CTIV
0x538
Calibration timer interval
Retained
Table 19: Register overview
5.4.3.1 TASKS_HFCLKSTART
Address offset: 0x000
Start HFCLK crystal oscillator
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Trigger
1
Description
TASKS_HFCLKSTART
Start HFCLK crystal oscillator
Trigger task
5.4.3.2 TASKS_HFCLKSTOP
Address offset: 0x004
Stop HFCLK crystal oscillator
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Trigger
1
Description
TASKS_HFCLKSTOP
Stop HFCLK crystal oscillator
Trigger task
5.4.3.3 TASKS_LFCLKSTART
Address offset: 0x008
Start LFCLK source
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Trigger
1
Description
TASKS_LFCLKSTART
Start LFCLK source
Trigger task
5.4.3.4 TASKS_LFCLKSTOP
Address offset: 0x00C
Stop LFCLK source
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Trigger
1
Description
TASKS_LFCLKSTOP
Stop LFCLK source
Trigger task
5.4.3.5 TASKS_CAL
Address offset: 0x010
Start calibration of LFRC oscillator
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
TASKS_CAL
Start calibration of LFRC oscillator
Trigger
1
Trigger task
5.4.3.6 TASKS_CTSTART
Address offset: 0x014
Start calibration timer
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Trigger
1
Description
TASKS_CTSTART
Start calibration timer
Trigger task
5.4.3.7 TASKS_CTSTOP
Address offset: 0x018
Stop calibration timer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Trigger
1
Description
TASKS_CTSTOP
Stop calibration timer
Trigger task
5.4.3.8 EVENTS_HFCLKSTARTED
Address offset: 0x100
HFCLK oscillator started
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_HFCLKSTARTED
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
NotGenerated
0
Event not generated
Generated
1
Event generated
HFCLK oscillator started
5.4.3.9 EVENTS_LFCLKSTARTED
Address offset: 0x104
LFCLK started
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_LFCLKSTARTED
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
NotGenerated
0
Event not generated
Generated
1
Event generated
LFCLK started
5.4.3.10 EVENTS_DONE
Address offset: 0x10C
Calibration of LFCLK RC oscillator complete event
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_DONE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
NotGenerated
0
Event not generated
Generated
1
Event generated
Calibration of LFCLK RC oscillator complete event
5.4.3.11 EVENTS_CTTO
Address offset: 0x110
Calibration timer timeout
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_CTTO
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
NotGenerated
0
Event not generated
Generated
1
Event generated
Calibration timer timeout
5.4.3.12 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
D C
Reset 0x00000000
ID
Access
Field
A
RW HFCLKSTARTED
B
C
D
Value ID
Value
Description
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Write '1' to enable interrupt for event HFCLKSTARTED
RW LFCLKSTARTED
Write '1' to enable interrupt for event LFCLKSTARTED
RW DONE
Write '1' to enable interrupt for event DONE
RW CTTO
Write '1' to enable interrupt for event CTTO
5.4.3.13 INTENCLR
Address offset: 0x308
Disable interrupt
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0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Power and clock management
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
D C
Reset 0x00000000
ID
Access
Field
A
RW HFCLKSTARTED
B
C
D
B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Write '1' to disable interrupt for event HFCLKSTARTED
RW LFCLKSTARTED
Write '1' to disable interrupt for event LFCLKSTARTED
RW DONE
Write '1' to disable interrupt for event DONE
RW CTTO
Write '1' to disable interrupt for event CTTO
5.4.3.14 HFCLKRUN
Address offset: 0x408
Status indicating that HFCLKSTART task has been triggered
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
STATUS
HFCLKSTART task triggered or not
NotTriggered
0
Task not triggered
Triggered
1
Task triggered
5.4.3.15 HFCLKSTAT
Address offset: 0x40C
HFCLK status
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
B
Reset 0x00000000
ID
Access
Field
A
R
B
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
SRC
Source of HFCLK
RC
0
64 MHz internal oscillator (HFINT)
Xtal
1
64 MHz crystal oscillator (HFXO)
NotRunning
0
HFCLK not running
Running
1
HFCLK running
STATE
HFCLK state
5.4.3.16 LFCLKRUN
Address offset: 0x414
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Status indicating that LFCLKSTART task has been triggered
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
STATUS
LFCLKSTART task triggered or not
NotTriggered
0
Task not triggered
Triggered
1
Task triggered
5.4.3.17 LFCLKSTAT
Address offset: 0x418
LFCLK status
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
B
Reset 0x00000000
ID
Access
Field
A
R
B
R
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
SRC
Source of LFCLK
RC
0
32.768 kHz RC oscillator
Xtal
1
32.768 kHz crystal oscillator
Synth
2
32.768 kHz synthesized from HFCLK
STATE
LFCLK state
NotRunning
0
LFCLK not running
Running
1
LFCLK running
5.4.3.18 LFCLKSRCCOPY
Address offset: 0x41C
Copy of LFCLKSRC register, set when LFCLKSTART task was triggered
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A
Reset 0x00000000
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
SRC
Clock source
RC
0
32.768 kHz RC oscillator
Xtal
1
32.768 kHz crystal oscillator
Synth
2
32.768 kHz synthesized from HFCLK
5.4.3.19 LFCLKSRC
Address offset: 0x518
Clock source for the LFCLK
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
C B
Reset 0x00000000
ID
Access
Field
A
RW SRC
B
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
RC
0
32.768 kHz RC oscillator
Xtal
1
32.768 kHz crystal oscillator
Synth
2
32.768 kHz synthesized from HFCLK
Clock source
RW BYPASS
Enable or disable bypass of LFCLK crystal oscillator with
external clock source
C
Disabled
0
Disable (use with Xtal or low-swing external source)
Enabled
1
Enable (use with rail-to-rail external source)
Disabled
0
Disable external source (use with Xtal)
Enabled
1
Enable use of external source instead of Xtal (SRC needs to
RW EXTERNAL
Enable or disable external source for LFCLK
be set to Xtal)
5.4.3.20 CTIV ( Retained )
Address offset: 0x538
This register is a retained register
Calibration timer interval
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A
Reset 0x00000000
ID
Access
Field
A
RW CTIV
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Calibration timer interval in multiple of 0.25 seconds.
Range: 0.25 seconds to 31.75 seconds.
5.4.4 Electrical specification
5.4.4.1 64 MHz internal oscillator (HFINT)
Symbol
Description
fNOM_HFINT
Nominal output frequency
Min.
Typ.
64
fTOL_HFINT
Frequency tolerance
VIN-)
READY
DOWN
CROSS
UP
Figure 33: Comparator overview
Once enabled (using the ENABLE register), the comparator is started by triggering the START task and
stopped by triggering the STOP task. After a start-up time of tCOMP,START, the comparator will generate a
READY event to indicate that it is ready for use and that its output is correct. When the COMP module is
started, events will be generated every time VIN+ crosses VIN-.
Operation modes
The comparator can be configured to operate in two main operation modes, differential mode and singleended mode. See the MODE register for more information. In both operation modes, the comparator can
operate in different speed and power consumption modes (low-power, normal and high-speed). Highspeed mode will consume more power compared to low-power mode, and low-power mode will result in
slower response time compared to high-speed mode.
Use the PSEL register to select any of the AIN0-AIN6 pins (or VDD/2) as VIN+ input, irregardless of the
operation mode selected for the comparator. The source of VIN- depends on which operation mode is
used:
• Differential mode: Derived directly from AIN0 to AIN7
• Single-ended mode: Derived from VREF. VREF can be derived from VDD, AIN0-AIN7 or internal 1.2 V,
1.8 V and 2.4 V references.
The selected analog pins will be acquired by the comparator once it is enabled.
An optional hysteresis on VIN+ and VIN- can be enabled when the module is used in differential mode
through the HYST register. In single-ended mode, VUP and VDOWN thresholds can be set to implement
a hysteresis using the reference ladder (see Comparator in single-ended mode on page 100). This
hysteresis is in the order of magnitude of 30 mV, and shall prevent noise on the signal to create unwanted
events. See Hysteresis example where VIN+ starts below VUP on page 101 for illustration of the effect of
an active hysteresis on a noisy input signal.
An upward crossing will generate an UP event and a downward crossing will generate a DOWN event. The
CROSS event will be generated every time there is a crossing, independent of direction.
The immediate value of the comparator can be sampled to RESULT register by triggering the SAMPLE task.
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6.5.1 Differential mode
In differential mode, the reference input VIN- is derived directly from one of the AINx pins.
Before enabling the comparator via the ENABLE register, the following registers must be configured for the
differential mode:
MUX
PSEL
EXTREFSEL
AIN7
AIN6
AIN5
AIN4
AIN3
AIN2
AIN1
AIN0
AIN6
VDD/2
AIN5
AIN4
AIN3
AIN2
AIN1
AIN0
• PSEL
• MODE
• EXTREFSEL
MUX
SAMPLE
STOP
START
VIN+
+
VIN-
Comparator
core
MODE
RESULT
Output
0 = BELOW (VIN+ < VIN-)
1 = ABOVE (VIN+ > VIN-)
READY
DOWN
UP
CROSS
Figure 34: Comparator in differential mode
Restriction: Depending on the device, not all the analog inputs may be available for each MUX. See
definitions for PSEL and EXTREFSEL for more information about which analog pins are available on a
particular device.
When HYST register is turned on while in this mode, the output of the comparator (and associated events)
will change from ABOVE to BELOW whenever VIN+ becomes lower than VIN- - (VDIFFHYST / 2). It will also
change from BELOW to ABOVE whenever VIN+ becomes higher than VIN- + (VDIFFHYST / 2). This behavior is
illustrated in Hysteresis enabled in differential mode on page 99.
VIN+
VIN- + (VDIFFHYST / 2)
VIN- - (VDIFFHYST / 2)
t
Output
ABOVE
(VIN+ > (VIN- + VDIFFHYST /2))
BELOW
(VIN+ < (VIN- - VDIFFHYST /2))
ABOVE
(VIN+ > (VIN- + VDIFFHYST /2))
Figure 35: Hysteresis enabled in differential mode
6.5.2 Single-ended mode
In single-ended mode, VIN- is derived from the reference ladder.
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Peripherals
Before enabling the comparator via the ENABLE register, the following registers must be configured for the
single-ended mode:
•
•
•
•
•
PSEL
MODE
REFSEL
EXTREFSEL
TH
MUX
PSEL
TH
EXTREFSEL
AIN7
AIN6
AIN5
AIN4
AIN2
AIN3
MUX
SAMPLE
STOP
START
VIN+
+
-
VIN-
0
MUX
1
Comparator
core
MODE
REFSEL
AIN1
AIN0
AIN6
VDD/2
AIN5
AIN4
AIN3
AIN2
AIN1
AIN0
The reference ladder uses the reference voltage (VREF) to derive two new voltage references, VUP and
VDOWN. VUP and VDOWN are configured using THUP and THDOWN respectively in the TH register. VREF
can be derived from any of the available reference sources, configured using the EXTREFSEL and REFSEL
registers as illustrated in Comparator in single-ended mode on page 100. When AREF is selected in
the REFSEL register, the EXTREFSEL register is used to select one of the AIN0-AIN7 analog input pins as
reference input. The selected analog pins will be acquired by the comparator once it is enabled.
AREF
VDOWN
HYST
RESULT
VDD
VUP
Reference
ladder
VREF
MUX
1V2
1V8
2V4
Output
0 = BELOW (VIN+ < VIN-)
1 = ABOVE (VIN+ > VIN-)
READY
DOWN
UP
CROSS
Figure 36: Comparator in single-ended mode
Restriction: Depending on the device, not all the analog inputs may be available for each MUX. See
definitions for PSEL and EXTREFSEL for more information about which analog pins are available on a
particular device.
When the comparator core detects that VIN+ > VIN-, i.e. ABOVE as per the RESULT register, VIN- will switch
to VDOWN. When VIN+ falls below VIN- again, VIN- will be switched back to VUP. By specifying VUP larger
than VDOWN, a hysteresis can be generated as illustrated in Hysteresis example where VIN+ starts below
VUP on page 101 and Hysteresis example where VIN+ starts above VUP on page 101.
Writing to HYST has no effect in single-ended mode, and the content of this register is ignored.
4454_140 v1.0
100
Peripherals
VIN+
VUP
VDOWN
Output
ABOVE (VIN+ > VIN-)
BELOW
VUP
VDOWN
VUP
RESULT
BELOW ( VIN+ < VIN-)
VIN-
t
UP
3
2
START
SAMPLE
SAMPLE
1
CPU
DOWN
ABOVE
READY
BELOW
Figure 37: Hysteresis example where VIN+ starts below VUP
VIN+
VUP
VDOWN
Output
BELOW ( VIN+ < VIN-)
ABOVE (VIN+ > VIN-)
BELOW
VDOWN
VUP
VDOWN
VUP
BELOW
3
2
SAMPLE
START
SAMPLE
1
CPU
ABOVE
UP
DOWN
READY
ABOVE
DOWN
RESULT
ABOVE (VIN+ > VIN-)
VIN-
t
Figure 38: Hysteresis example where VIN+ starts above VUP
6.5.3 Registers
Base address
Peripheral
Instance
Description
Configuration
0x40013000
COMP
COMP
General purpose comparator
Table 30: Instances
Register
Offset
Description
TASKS_START
0x000
Start comparator
4454_140 v1.0
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Peripherals
Register
Offset
Description
TASKS_STOP
0x004
Stop comparator
TASKS_SAMPLE
0x008
Sample comparator value
EVENTS_READY
0x100
COMP is ready and output is valid
EVENTS_DOWN
0x104
Downward crossing
EVENTS_UP
0x108
Upward crossing
EVENTS_CROSS
0x10C
Downward or upward crossing
SHORTS
0x200
Shortcuts between local events and tasks
INTEN
0x300
Enable or disable interrupt
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
RESULT
0x400
Compare result
ENABLE
0x500
COMP enable
PSEL
0x504
Pin select
REFSEL
0x508
Reference source select for single-ended mode
EXTREFSEL
0x50C
External reference select
TH
0x530
Threshold configuration for hysteresis unit
MODE
0x534
Mode configuration
HYST
0x538
Comparator hysteresis enable
Table 31: Register overview
6.5.3.1 TASKS_START
Address offset: 0x000
Start comparator
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Trigger
1
Description
TASKS_START
Start comparator
Trigger task
6.5.3.2 TASKS_STOP
Address offset: 0x004
Stop comparator
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Trigger
1
Description
TASKS_STOP
Stop comparator
Trigger task
6.5.3.3 TASKS_SAMPLE
Address offset: 0x008
Sample comparator value
4454_140 v1.0
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Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Trigger
1
Description
TASKS_SAMPLE
Sample comparator value
Trigger task
6.5.3.4 EVENTS_READY
Address offset: 0x100
COMP is ready and output is valid
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_READY
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
NotGenerated
0
Event not generated
Generated
1
Event generated
COMP is ready and output is valid
6.5.3.5 EVENTS_DOWN
Address offset: 0x104
Downward crossing
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_DOWN
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
NotGenerated
0
Event not generated
Generated
1
Event generated
Downward crossing
6.5.3.6 EVENTS_UP
Address offset: 0x108
Upward crossing
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_UP
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
NotGenerated
0
Event not generated
Generated
1
Event generated
Upward crossing
6.5.3.7 EVENTS_CROSS
Address offset: 0x10C
Downward or upward crossing
4454_140 v1.0
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Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_CROSS
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
NotGenerated
0
Event not generated
Generated
1
Event generated
Downward or upward crossing
6.5.3.8 SHORTS
Address offset: 0x200
Shortcuts between local events and tasks
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
E D C B A
Reset 0x00000000
ID
Access
Field
A
RW READY_SAMPLE
B
C
D
E
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
Shortcut between event READY and task SAMPLE
RW READY_STOP
Shortcut between event READY and task STOP
RW DOWN_STOP
Shortcut between event DOWN and task STOP
RW UP_STOP
Shortcut between event UP and task STOP
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW CROSS_STOP
Shortcut between event CROSS and task STOP
6.5.3.9 INTEN
Address offset: 0x300
Enable or disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
D C B A
Reset 0x00000000
ID
Access
Field
A
RW READY
B
C
D
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Disabled
0
Disable
Enabled
1
Enable
Disabled
0
Disable
Enabled
1
Enable
Disabled
0
Disable
Enabled
1
Enable
Enable or disable interrupt for event READY
RW DOWN
Enable or disable interrupt for event DOWN
RW UP
Enable or disable interrupt for event UP
RW CROSS
Enable or disable interrupt for event CROSS
Disabled
4454_140 v1.0
0
Disable
104
Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
D C B A
Reset 0x00000000
ID
Access
Field
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Enabled
1
Enable
6.5.3.10 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
D C B A
Reset 0x00000000
ID
Access
Field
A
RW READY
B
C
D
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Write '1' to enable interrupt for event READY
RW DOWN
Write '1' to enable interrupt for event DOWN
RW UP
Write '1' to enable interrupt for event UP
RW CROSS
Write '1' to enable interrupt for event CROSS
6.5.3.11 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
D C B A
Reset 0x00000000
ID
Access
Field
A
RW READY
B
C
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Write '1' to disable interrupt for event READY
RW DOWN
Write '1' to disable interrupt for event DOWN
RW UP
4454_140 v1.0
Write '1' to disable interrupt for event UP
105
Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
D C B A
Reset 0x00000000
ID
Access
Field
D
RW CROSS
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Write '1' to disable interrupt for event CROSS
6.5.3.12 RESULT
Address offset: 0x400
Compare result
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
RESULT
Result of last compare. Decision point SAMPLE task.
Below
0
Input voltage is below the threshold (VIN+ < VIN-)
Above
1
Input voltage is above the threshold (VIN+ > VIN-)
6.5.3.13 ENABLE
Address offset: 0x500
COMP enable
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A
Reset 0x00000000
ID
Access
Field
A
RW ENABLE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Disabled
0
Disable
Enabled
2
Enable
Enable or disable COMP
6.5.3.14 PSEL
Address offset: 0x504
Pin select
4454_140 v1.0
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Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A
Reset 0x00000000
ID
Access
Field
A
RW PSEL
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
AnalogInput0
0
AIN0 selected as analog input
AnalogInput1
1
AIN1 selected as analog input
AnalogInput2
2
AIN2 selected as analog input
AnalogInput3
3
AIN3 selected as analog input
AnalogInput4
4
AIN4 selected as analog input
AnalogInput5
5
AIN5 selected as analog input
AnalogInput6
6
AIN6 selected as analog input
VddDiv2
7
VDD/2 selected as analog input
Analog pin select
6.5.3.15 REFSEL
Address offset: 0x508
Reference source select for single-ended mode
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A
Reset 0x00000004
ID
Access
Field
A
RW REFSEL
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
Value ID
Value
Description
Int1V2
0
VREF = internal 1.2 V reference (VDD >= 1.7 V)
Int1V8
1
VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V)
Int2V4
2
VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V)
VDD
4
VREF = VDD
ARef
5
VREF = AREF (VDD >= VREF >= AREFMIN)
Reference select
6.5.3.16 EXTREFSEL
Address offset: 0x50C
External reference select
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A
Reset 0x00000000
ID
Access
Field
A
RW EXTREFSEL
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
External analog reference select
AnalogReference0
0
Use AIN0 as external analog reference
AnalogReference1
1
Use AIN1 as external analog reference
AnalogReference2
2
Use AIN2 as external analog reference
AnalogReference3
3
Use AIN3 as external analog reference
AnalogReference4
4
Use AIN4 as external analog reference
AnalogReference5
5
Use AIN5 as external analog reference
AnalogReference6
6
Use AIN6 as external analog reference
AnalogReference7
7
Use AIN7 as external analog reference
6.5.3.17 TH
Address offset: 0x530
4454_140 v1.0
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Peripherals
Threshold configuration for hysteresis unit
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
B B B B B B
Reset 0x00000000
A A A A A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID
Access
Field
Value ID
Value
Description
A
RW THDOWN
[63:0]
VDOWN = (THDOWN+1)/64*VREF
B
RW THUP
[63:0]
VUP = (THUP+1)/64*VREF
6.5.3.18 MODE
Address offset: 0x534
Mode configuration
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
B
Reset 0x00000000
ID
Access
Field
A
RW SP
B
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Low
0
Low-power mode
Normal
1
Normal mode
High
2
High-speed mode
SE
0
Single-ended mode
Diff
1
Differential mode
Speed and power modes
RW MAIN
Main operation modes
6.5.3.19 HYST
Address offset: 0x538
Comparator hysteresis enable
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW HYST
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
NoHyst
0
Comparator hysteresis disabled
Hyst50mV
1
Comparator hysteresis enabled
Comparator hysteresis
6.5.4 Electrical specification
6.5.4.1 COMP Electrical Specification
Symbol
Description
tPROPDLY,LP
Propagation delay, low-power modea
tPROPDLY,N
Min.
a
Propagation delay, normal mode
tPROPDLY,HS
Propagation delay, high-speed mode
VDIFFHYST
Optional hysteresis applied to differential input
a
a
Propagation delay is with 10 mV overdrive.
4454_140 v1.0
108
Typ.
Max.
Units
0.6
µS
0.2
µS
0.1
µS
30
mV
Peripherals
Symbol
Description
Min.
VVDD-VREF
Required difference between VDD and a selected VREF, VDD
0.3
Typ.
Max.
Units
V
> VREF
tINT_REF,START
Startup time for the internal bandgap reference
EINT_REF
Internal bandgap reference error
-3
50
VINPUTOFFSET
Input offset
-10
tCOMP,START
Startup time for the comparator core
80
µS
3
%
10
mV
3
µS
6.6 ECB — AES electronic codebook mode encryption
The AES electronic codebook mode encryption (ECB) can be used for a range of cryptographic functions
like hash generation, digital signatures, and keystream generation for data encryption/decryption. The ECB
encryption block supports 128 bit AES encryption (encryption only, not decryption).
AES ECB operates with EasyDMA access to system Data RAM for in-place operations on cleartext
and ciphertext during encryption. ECB uses the same AES core as the CCM and AAR blocks and is an
asynchronous operation which may not complete if the AES core is busy.
AES ECB features:
•
•
•
•
128 bit AES encryption
Supports standard AES ECB block encryption
Memory pointer support
DMA data transfer
AES ECB performs a 128 bit AES block encrypt. At the STARTECB task, data and key is loaded into the
algorithm by EasyDMA. When output data has been written back to memory, the ENDECB event is
triggered.
AES ECB can be stopped by triggering the STOPECB task.
6.6.1 Shared resources
The ECB, CCM, and AAR share the same AES module. The ECB will always have lowest priority and if there
is a sharing conflict during encryption, the ECB operation will be aborted and an ERRORECB event will be
generated.
6.6.2 EasyDMA
The ECB implements an EasyDMA mechanism for reading and writing to the Data RAM. This DMA cannot
access the program memory or any other parts of the memory area except RAM.
If the ECBDATAPTR is not pointing to the Data RAM region, an EasyDMA transfer may result in a HardFault
or RAM corruption. See Memory on page 16 for more information about the different memory regions.
The EasyDMA will have finished accessing the Data RAM when the ENDECB or ERRORECB is generated.
6.6.3 ECB data structure
Input to the block encrypt and output from the block encrypt are stored in the same data structure.
ECBDATAPTR should point to this data structure before STARTECB is initiated.
Property
Address offset
Description
KEY
0
16 byte AES key
CLEARTEXT
16
16 byte AES cleartext input block
CIPHERTEXT
32
16 byte AES ciphertext output block
Table 32: ECB data structure overview
4454_140 v1.0
109
Peripherals
6.6.4 Registers
Base address
Peripheral
Instance
Description
Configuration
0x4000E000
ECB
ECB
AES Electronic Codebook (ECB) mode
block encryption
Table 33: Instances
Register
Offset
Description
TASKS_STARTECB
0x000
Start ECB block encrypt
TASKS_STOPECB
0x004
Abort a possible executing ECB operation
EVENTS_ENDECB
0x100
ECB block encrypt complete
EVENTS_ERRORECB
0x104
ECB block encrypt aborted because of a STOPECB task or due to an error
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
ECBDATAPTR
0x504
ECB block encrypt memory pointers
Table 34: Register overview
6.6.4.1 TASKS_STARTECB
Address offset: 0x000
Start ECB block encrypt
If a crypto operation is already running in the AES core, the STARTECB task will not start a new encryption
and an ERRORECB event will be triggered
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
TASKS_STARTECB
Start ECB block encrypt
If a crypto operation is already running in the AES core,
the STARTECB task will not start a new encryption and an
ERRORECB event will be triggered
Trigger
1
Trigger task
6.6.4.2 TASKS_STOPECB
Address offset: 0x004
Abort a possible executing ECB operation
If a running ECB operation is aborted by STOPECB, the ERRORECB event is triggered.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
TASKS_STOPECB
Abort a possible executing ECB operation
If a running ECB operation is aborted by STOPECB, the
ERRORECB event is triggered.
Trigger
4454_140 v1.0
1
Trigger task
110
Peripherals
6.6.4.3 EVENTS_ENDECB
Address offset: 0x100
ECB block encrypt complete
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_ENDECB
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
NotGenerated
0
Event not generated
Generated
1
Event generated
ECB block encrypt complete
6.6.4.4 EVENTS_ERRORECB
Address offset: 0x104
ECB block encrypt aborted because of a STOPECB task or due to an error
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_ERRORECB
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
ECB block encrypt aborted because of a STOPECB task or
due to an error
NotGenerated
0
Event not generated
Generated
1
Event generated
6.6.4.5 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
B A
Reset 0x00000000
ID
Access
Field
A
RW ENDECB
B
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Write '1' to enable interrupt for event ENDECB
RW ERRORECB
Write '1' to enable interrupt for event ERRORECB
6.6.4.6 INTENCLR
Address offset: 0x308
Disable interrupt
4454_140 v1.0
111
Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
B A
Reset 0x00000000
ID
Access
Field
A
RW ENDECB
B
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Write '1' to disable interrupt for event ENDECB
RW ERRORECB
Write '1' to disable interrupt for event ERRORECB
6.6.4.7 ECBDATAPTR
Address offset: 0x504
ECB block encrypt memory pointers
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID
Access
Field
Value ID
A
RW ECBDATAPTR
Value
Description
Pointer to the ECB data structure (see Table 1 ECB data
structure overview)
6.6.5 Electrical specification
6.6.5.1 ECB Electrical Specification
Symbol
Description
tECB
Run time per 16 byte block in all modes
Min.
Typ.
6
Max.
Units
µs
6.7 EGU — Event generator unit
The Event generator unit (EGU) provides support for inter-layer signaling. This means support for atomic
triggering of both CPU execution and hardware tasks from both firmware (by CPU) and hardware (by PPI).
This feature can, for instance, be used for triggering CPU execution at a lower priority execution from
a higher priority execution, or to handle a peripheral's ISR execution at a lower priority for some of its
events. However, triggering any priority from any priority is possible.
Listed here are the main EGU features:
• Enables SW triggering of interrupts
• Separate interrupt vectors for every EGU instance
• Up to 16 separate event flags per interrupt for multiplexing
Each instance of The EGU implements a set of tasks which can individually be triggered to generate the
corresponding event, i.e., the corresponding event for TASKS_TRIGGER[n] is EVENTS_TRIGGERED[n].
Refer to Instances on page 113 for a list of the various EGU instances
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6.7.1 Registers
Base address
Peripheral
Instance
Description
Configuration
0x40014000
EGU
EGU0
Event generator unit 0
0x40015000
EGU
EGU1
Event generator unit 1
Table 35: Instances
Register
Offset
Description
TASKS_TRIGGER[0]
0x000
Trigger 0 for triggering the corresponding TRIGGERED[0] event
TASKS_TRIGGER[1]
0x004
Trigger 1 for triggering the corresponding TRIGGERED[1] event
TASKS_TRIGGER[2]
0x008
Trigger 2 for triggering the corresponding TRIGGERED[2] event
TASKS_TRIGGER[3]
0x00C
Trigger 3 for triggering the corresponding TRIGGERED[3] event
TASKS_TRIGGER[4]
0x010
Trigger 4 for triggering the corresponding TRIGGERED[4] event
TASKS_TRIGGER[5]
0x014
Trigger 5 for triggering the corresponding TRIGGERED[5] event
TASKS_TRIGGER[6]
0x018
Trigger 6 for triggering the corresponding TRIGGERED[6] event
TASKS_TRIGGER[7]
0x01C
Trigger 7 for triggering the corresponding TRIGGERED[7] event
TASKS_TRIGGER[8]
0x020
Trigger 8 for triggering the corresponding TRIGGERED[8] event
TASKS_TRIGGER[9]
0x024
Trigger 9 for triggering the corresponding TRIGGERED[9] event
TASKS_TRIGGER[10]
0x028
Trigger 10 for triggering the corresponding TRIGGERED[10] event
TASKS_TRIGGER[11]
0x02C
Trigger 11 for triggering the corresponding TRIGGERED[11] event
TASKS_TRIGGER[12]
0x030
Trigger 12 for triggering the corresponding TRIGGERED[12] event
TASKS_TRIGGER[13]
0x034
Trigger 13 for triggering the corresponding TRIGGERED[13] event
TASKS_TRIGGER[14]
0x038
Trigger 14 for triggering the corresponding TRIGGERED[14] event
TASKS_TRIGGER[15]
0x03C
Trigger 15 for triggering the corresponding TRIGGERED[15] event
EVENTS_TRIGGERED[0]
0x100
Event number 0 generated by triggering the corresponding TRIGGER[0] task
EVENTS_TRIGGERED[1]
0x104
Event number 1 generated by triggering the corresponding TRIGGER[1] task
EVENTS_TRIGGERED[2]
0x108
Event number 2 generated by triggering the corresponding TRIGGER[2] task
EVENTS_TRIGGERED[3]
0x10C
Event number 3 generated by triggering the corresponding TRIGGER[3] task
EVENTS_TRIGGERED[4]
0x110
Event number 4 generated by triggering the corresponding TRIGGER[4] task
EVENTS_TRIGGERED[5]
0x114
Event number 5 generated by triggering the corresponding TRIGGER[5] task
EVENTS_TRIGGERED[6]
0x118
Event number 6 generated by triggering the corresponding TRIGGER[6] task
EVENTS_TRIGGERED[7]
0x11C
Event number 7 generated by triggering the corresponding TRIGGER[7] task
EVENTS_TRIGGERED[8]
0x120
Event number 8 generated by triggering the corresponding TRIGGER[8] task
EVENTS_TRIGGERED[9]
0x124
Event number 9 generated by triggering the corresponding TRIGGER[9] task
EVENTS_TRIGGERED[10]
0x128
Event number 10 generated by triggering the corresponding TRIGGER[10] task
EVENTS_TRIGGERED[11]
0x12C
Event number 11 generated by triggering the corresponding TRIGGER[11] task
EVENTS_TRIGGERED[12]
0x130
Event number 12 generated by triggering the corresponding TRIGGER[12] task
EVENTS_TRIGGERED[13]
0x134
Event number 13 generated by triggering the corresponding TRIGGER[13] task
EVENTS_TRIGGERED[14]
0x138
Event number 14 generated by triggering the corresponding TRIGGER[14] task
EVENTS_TRIGGERED[15]
0x13C
Event number 15 generated by triggering the corresponding TRIGGER[15] task
INTEN
0x300
Enable or disable interrupt
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
Table 36: Register overview
6.7.1.1 TASKS_TRIGGER[n] (n=0..15)
Address offset: 0x000 + (n × 0x4)
Trigger n for triggering the corresponding TRIGGERED[n] event
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
TASKS_TRIGGER
Trigger n for triggering the corresponding TRIGGERED[n]
event
Trigger
1
Trigger task
6.7.1.2 EVENTS_TRIGGERED[n] (n=0..15)
Address offset: 0x100 + (n × 0x4)
Event number n generated by triggering the corresponding TRIGGER[n] task
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_TRIGGERED
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Event number n generated by triggering the corresponding
TRIGGER[n] task
NotGenerated
0
Event not generated
Generated
1
Event generated
6.7.1.3 INTEN
Address offset: 0x300
Enable or disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
P O N M L K J I H G F E D C B A
Reset 0x00000000
ID
Access
Field
A-P
RW TRIGGERED[i] (i=0..15)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Enable or disable interrupt for event TRIGGERED[i]
Disabled
0
Disable
Enabled
1
Enable
6.7.1.4 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
P O N M L K J I H G F E D C B A
Reset 0x00000000
ID
Access
Field
A-P
RW TRIGGERED[i] (i=0..15)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Write '1' to enable interrupt for event TRIGGERED[i]
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
6.7.1.5 INTENCLR
Address offset: 0x308
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Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
P O N M L K J I H G F E D C B A
Reset 0x00000000
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID
Access
Field
Value ID
A-P
RW TRIGGERED[i] (i=0..15)
Value
Description
Write '1' to disable interrupt for event TRIGGERED[i]
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
6.7.2 Electrical specification
6.7.2.1 EGU Electrical Specification
Symbol
Description
tEGU,EVT
Latency between setting an EGU event flag and the system
Min.
Typ.
1
Max.
Units
cycles
setting an interrupt
6.8 GPIO — General purpose input/output
The general purpose input/output pins (GPIOs) are grouped as one or more ports with each port having up
to 32 GPIOs.
The number of ports and GPIOs per port might vary with product variant and package. Refer to Registers
on page 117 and Pin assignments on page 416 for more information about the number of GPIOs that
are supported.
GPIO has the following user-configurable features:
•
•
•
•
•
•
•
•
•
Up to 32 GPIO pins per GPIO port
Configurable output drive strength
Internal pull-up and pull-down resistors
Wake-up from high or low level triggers on all pins
Trigger interrupt on state changes on any pin
All pins can be used by the PPI task/event system
One or more GPIO outputs can be controlled through PPI and GPIOTE channels
All pins can be individually mapped to interface blocks for layout flexibility
GPIO state changes captured on SENSE signal can be stored by LATCH register
The GPIO port peripheral implements up to 32 pins, PIN0 through PIN31. Each of these pins can be
individually configured in the PIN_CNF[n] registers (n=0..31).
The following parameters can be configured through these registers:
•
•
•
•
•
•
Direction
Drive strength
Enabling of pull-up and pull-down resistors
Pin sensing
Input buffer disconnect
Analog input (for selected pins)
The PIN_CNF registers are retained registers. See POWER — Power supply on page 48 chapter for more
information about retained registers.
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6.8.1 Pin configuration
Pins can be individually configured, through the SENSE field in the PIN_CNF[n] register, to detect either a
high level or a low level on their input.
When the correct level is detected on any such configured pin, the sense mechanism will set the DETECT
signal high. Each pin has a separate DETECT signal. Default behavior, defined by the DETECTMODE register,
is that the DETECT signals from all pins in the GPIO port are combined into one common DETECT signal
that is routed throughout the system, which then can be utilized by other peripherals. This mechanism
is functional in both System ON mode and System OFF mode. See GPIO port and the GPIO pin details on
page 116.
LDETECT
PIN0
ANAEN
GPIO port
DIR_OVERRIDE
DETECTMODE
DETECT
PIN[0].CNF.DRIVE
OUT_OVERRIDE
LATCH
PIN0
OUT
PIN[0].OUT
PIN0.DETECT
PIN[0].IN
PIN[0].CNF
PIN[0].CNF.DIR
Sense
PIN1.DETECT
PIN[0].CNF.SENSE
..
PIN[0].CNF.PULL
PIN[0].CNF.INPUT
PIN31.DETECT
PIN[0].IN
I
PIN31
IN
PIN[31].OUT
PIN[31].IN
PIN[31].CNF
INPUT_OVERRIDE
ANAIN
O: output buffer
I: input buffer
Figure 39: GPIO port and the GPIO pin details
GPIO port and the GPIO pin details on page 116 illustrates the GPIO port containing 32 individual pins,
where PIN0 is illustrated in more detail as a reference. All signals on the left side in the illustration are
used by other peripherals in the system and therefore not directly available to the CPU.
Make sure that a pin is in a level that cannot trigger the sense mechanism before enabling it. The DETECT
signal will go high immediately if the SENSE condition configured in the PIN_CNF registers is met when the
sense mechanism is enabled. This will trigger a PORT event if the DETECT signal was low before enabling
the sense mechanism. See GPIOTE — GPIO tasks and events on page 123.
See the following peripherals for more information about how the DETECT signal is used:
• POWER: uses the DETECT signal to exit from System OFF mode.
• GPIOTE: uses the DETECT signal to generate the PORT event.
When a pin's PINx.DETECT signal goes high, a flag will be set in the LATCH register. For example, when
the PIN0.DETECT signal goes high, bit 0 in the LATCH register will be set to '1'. If the CPU performs a clear
operation on a bit in the LATCH register when the associated PINx.DETECT signal is high, the bit in the
LATCH register will not be cleared. The LATCH register will only be cleared if the CPU explicitly clears it by
writing a '1' to the bit that shall be cleared, i.e. the LATCH register will not be affected by a PINx.DETECT
signal being set low.
The LDETECT signal will be set high when one or more bits in the LATCH register are '1'. The LDETECT signal
will be set low when all bits in the LATCH register are successfully cleared to '0'.
If one or more bits in the LATCH register are '1' after the CPU has performed a clear operation on the
LATCH registers, a rising edge will be generated on the LDETECT signal. This is illustrated in DETECT signal
behavior on page 117.
Important: The CPU can read the LATCH register at any time to check if a SENSE condition has been
met on one or more of the the GPIO pins, even if that condition is no longer met at the time the
CPU queries the LATCH register. This mechanism will work even if the LDETECT signal is not used as
the DETECT signal.
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PIN[0].OUT
O
116
PIN31
Peripherals
The LDETECT signal is by default not connected to the GPIO port's DETECT signal, but via the DETECTMODE
register it is possible to change from default behavior to DETECT signal being derived directly from the
LDETECT signal instead. See GPIO port and the GPIO pin details on page 116. DETECT signal behavior on
page 117 illustrates the DETECT signal behavior for these two alternatives.
PIN31.DETECT
PIN1.DETECT
PIN0.DETECT
DETECT
(Default mode)
LATCH.31
LATCH.1
LATCH.0
3
4
LATCH = (1 = 2.7
V
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Symbol
Description
Min.
IOH,HDL
Current at VDD-0.4 V, output set high, high drive, VDD >= 1.7
3
Typ.
Max.
Units
mA
V
tRF,15pF
Rise/fall time, standard drive mode, 10-90%, 15 pF load1
9
ns
tRF,25pF
Rise/fall time, standard drive mode, 10-90%, 25 pF load1
13
ns
tRF,50pF
1
25
ns
tHRF,15pF
1
Rise/Fall time, high drive mode, 10-90%, 15 pF load
4
ns
tHRF,25pF
Rise/Fall time, high drive mode, 10-90%, 25 pF load1
5
ns
tHRF,50pF
Rise/Fall time, high drive mode, 10-90%, 50 pF load1
8
ns
RPU
Pull-up resistance
11
13
16
kΩ
RPD
Pull-down resistance
11
13
16
kΩ
CPAD
Pad capacitance
Rise/fall time, standard drive mode, 10-90%, 50 pF load
3
pF
6.9 GPIOTE — GPIO tasks and events
The GPIO tasks and events (GPIOTE) module provides functionality for accessing GPIO pins using tasks and
events. Each GPIOTE channel can be assigned to one pin.
A GPIOTE block enables GPIOs to generate events on pin state change which can be used to carry out tasks
through the PPI system. A GPIO can also be driven to change state on system events using the PPI system.
Low power detection of pin state changes is possible when in System ON or System OFF.
Instance
Number of GPIOTE channels
GPIOTE
8
Table 39: GPIOTE properties
Up to three tasks can be used in each GPIOTE channel for performing write operations to a pin. Two tasks
are fixed (SET and CLR), and one (OUT) is configurable to perform following operations:
• Set
• Clear
• Toggle
An event can be generated in each GPIOTE channel from one of the following input conditions:
• Rising edge
• Falling edge
• Any change
6.9.1 Pin events and tasks
The GPIOTE module has a number of tasks and events that can be configured to operate on individual
GPIO pins.
The tasks (SET[n], CLR[n] and OUT[n]) can be used for writing to individual pins, and the events (IN[n]) can
be generated from changes occurring at the inputs of individual pins.
The SET task will set the pin selected in CONFIG[n].PSEL to high.
The CLR task will set the pin low.
The effect of the OUT task on the pin is configurable in CONFIG[n].POLARITY , and can either set the pin
high, set it low, or toggle it.
1
Rise and fall times based on simulations
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The tasks and events are configured using the CONFIG[n] registers. Every set of SET, CLR and OUT[n] tasks
and IN[n] events has one CONFIG[n] register associated with it.
As long as a SET[n], CLR[n] and OUT[n] task or an IN[n] event is configured to control a pin n, the pin's
output value will only be updated by the GPIOTE module. The pin's output value as specified in the GPIO
will therefore be ignored as long as the pin is controlled by GPIOTE. Attempting to write a pin as a normal
GPIO pin will have no effect. When the GPIOTE is disconnected from a pin, see MODE field in CONFIG[n]
register, the associated pin will get the output and configuration values specified in the GPIO module.
When conflicting tasks are triggered simultaneously (i.e. during the same clock cycle) in one channel, the
precedence of the tasks will be as described in Task priorities on page 124.
Priority
Task
1
OUT
2
CLR
3
SET
Table 40: Task priorities
When setting the CONFIG[n] registers, MODE=Disabled does not have the same effect as MODE=Task and
POLARITY=None. In the latter case, a CLR or SET task occurring at the exact same time as OUT will end up
with no change on the pin, according to the priorities described in the table above.
When a GPIOTE channel is configured to operate on a pin as a task, the initial value of that pin is
configured in the OUTINIT field of CONFIG[n].
6.9.2 Port event
PORT is an event that can be generated from multiple input pins using the GPIO DETECT signal.
The event will be generated on the rising edge of the DETECT signal. See GPIO — General purpose input/
output on page 115 for more information about the DETECT signal.
Putting the system into System ON IDLE while DETECT is high will not cause DETECT to wake the system
up again. Make sure to clear all DETECT sources before entering sleep. If the LATCH register is used as a
source, if any bit in LATCH is still high after clearing all or part of the register (for instance due to one of
the PINx.DETECT signal still high), a new rising edge will be generated on DETECT, see Pin configuration on
page 116.
Trying to put the system to System OFF while DETECT is high will cause a wakeup from System OFF reset.
This feature is always enabled although the peripheral itself appears to be IDLE, that is, no clocks or
other power intensive infrastructure have to be requested to keep this feature enabled. This feature can
therefore be used to wake up the CPU from a WFI or WFE type sleep in System ON with all peripherals and
the CPU idle, that is, lowest power consumption in System ON mode.
In order to prevent spurious interrupts from the PORT event while configuring the sources, the user
shall first disable interrupts on the PORT event (through INTENCLR.PORT), then configure the sources
(PIN_CNF[n].SENSE), clear any potential event that could have occurred during configuration (write '0' to
EVENTS_PORT), and finally enable interrupts (through INTENSET.PORT).
6.9.3 Tasks and events pin configuration
Each GPIOTE channel is associated with one physical GPIO pin through the CONFIG.PSEL field.
When Event mode is selected in CONFIG.MODE, the pin specified by CONFIG.PSEL will be configured
as an input, overriding the DIR setting in GPIO. Similarly, when Task mode is selected in CONFIG.MODE,
the pin specified by CONFIG.PSEL will be configured as an output overriding the DIR setting and OUT
value in GPIO. When Disabled is selected in CONFIG.MODE, the pin specified by CONFIG.PSEL will use its
configuration from the PIN[n].CNF registers in GPIO.
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Only one GPIOTE channel can be assigned to one physical pin. Failing to do so may result in unpredictable
behavior.
6.9.4 Registers
Base address
Peripheral
Instance
Description
0x40006000
GPIOTE
GPIOTE
GPIO tasks and events
Configuration
Table 41: Instances
Register
Offset
Description
TASKS_OUT[0]
0x000
Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is configured in
TASKS_OUT[1]
0x004
TASKS_OUT[2]
0x008
TASKS_OUT[3]
0x00C
TASKS_OUT[4]
0x010
TASKS_OUT[5]
0x014
TASKS_OUT[6]
0x018
TASKS_OUT[7]
0x01C
TASKS_SET[0]
0x030
Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it high.
TASKS_SET[1]
0x034
Task for writing to pin specified in CONFIG[1].PSEL. Action on pin is to set it high.
TASKS_SET[2]
0x038
Task for writing to pin specified in CONFIG[2].PSEL. Action on pin is to set it high.
TASKS_SET[3]
0x03C
Task for writing to pin specified in CONFIG[3].PSEL. Action on pin is to set it high.
TASKS_SET[4]
0x040
Task for writing to pin specified in CONFIG[4].PSEL. Action on pin is to set it high.
TASKS_SET[5]
0x044
Task for writing to pin specified in CONFIG[5].PSEL. Action on pin is to set it high.
TASKS_SET[6]
0x048
Task for writing to pin specified in CONFIG[6].PSEL. Action on pin is to set it high.
TASKS_SET[7]
0x04C
Task for writing to pin specified in CONFIG[7].PSEL. Action on pin is to set it high.
TASKS_CLR[0]
0x060
Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it low.
TASKS_CLR[1]
0x064
Task for writing to pin specified in CONFIG[1].PSEL. Action on pin is to set it low.
TASKS_CLR[2]
0x068
Task for writing to pin specified in CONFIG[2].PSEL. Action on pin is to set it low.
TASKS_CLR[3]
0x06C
Task for writing to pin specified in CONFIG[3].PSEL. Action on pin is to set it low.
TASKS_CLR[4]
0x070
Task for writing to pin specified in CONFIG[4].PSEL. Action on pin is to set it low.
TASKS_CLR[5]
0x074
Task for writing to pin specified in CONFIG[5].PSEL. Action on pin is to set it low.
TASKS_CLR[6]
0x078
Task for writing to pin specified in CONFIG[6].PSEL. Action on pin is to set it low.
TASKS_CLR[7]
0x07C
Task for writing to pin specified in CONFIG[7].PSEL. Action on pin is to set it low.
EVENTS_IN[0]
0x100
Event generated from pin specified in CONFIG[0].PSEL
EVENTS_IN[1]
0x104
Event generated from pin specified in CONFIG[1].PSEL
EVENTS_IN[2]
0x108
Event generated from pin specified in CONFIG[2].PSEL
EVENTS_IN[3]
0x10C
Event generated from pin specified in CONFIG[3].PSEL
EVENTS_IN[4]
0x110
Event generated from pin specified in CONFIG[4].PSEL
EVENTS_IN[5]
0x114
Event generated from pin specified in CONFIG[5].PSEL
EVENTS_IN[6]
0x118
Event generated from pin specified in CONFIG[6].PSEL
EVENTS_IN[7]
0x11C
Event generated from pin specified in CONFIG[7].PSEL
EVENTS_PORT
0x17C
Event generated from multiple input GPIO pins with SENSE mechanism enabled
INTENSET
0x304
Enable interrupt
CONFIG[0].POLARITY.
Task for writing to pin specified in CONFIG[1].PSEL. Action on pin is configured in
CONFIG[1].POLARITY.
Task for writing to pin specified in CONFIG[2].PSEL. Action on pin is configured in
CONFIG[2].POLARITY.
Task for writing to pin specified in CONFIG[3].PSEL. Action on pin is configured in
CONFIG[3].POLARITY.
Task for writing to pin specified in CONFIG[4].PSEL. Action on pin is configured in
CONFIG[4].POLARITY.
Task for writing to pin specified in CONFIG[5].PSEL. Action on pin is configured in
CONFIG[5].POLARITY.
Task for writing to pin specified in CONFIG[6].PSEL. Action on pin is configured in
CONFIG[6].POLARITY.
Task for writing to pin specified in CONFIG[7].PSEL. Action on pin is configured in
CONFIG[7].POLARITY.
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Register
Offset
Description
INTENCLR
0x308
Disable interrupt
CONFIG[0]
0x510
Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event
CONFIG[1]
0x514
Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event
CONFIG[2]
0x518
Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event
CONFIG[3]
0x51C
Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event
CONFIG[4]
0x520
Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event
CONFIG[5]
0x524
Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event
CONFIG[6]
0x528
Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event
CONFIG[7]
0x52C
Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event
Table 42: Register overview
6.9.4.1 TASKS_OUT[n] (n=0..7)
Address offset: 0x000 + (n × 0x4)
Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
TASKS_OUT
Task for writing to pin specified in CONFIG[n].PSEL. Action
on pin is configured in CONFIG[n].POLARITY.
Trigger
1
Trigger task
6.9.4.2 TASKS_SET[n] (n=0..7)
Address offset: 0x030 + (n × 0x4)
Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
TASKS_SET
Task for writing to pin specified in CONFIG[n].PSEL. Action
on pin is to set it high.
Trigger
1
Trigger task
6.9.4.3 TASKS_CLR[n] (n=0..7)
Address offset: 0x060 + (n × 0x4)
Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
TASKS_CLR
Task for writing to pin specified in CONFIG[n].PSEL. Action
on pin is to set it low.
Trigger
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Trigger task
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Peripherals
6.9.4.4 EVENTS_IN[n] (n=0..7)
Address offset: 0x100 + (n × 0x4)
Event generated from pin specified in CONFIG[n].PSEL
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_IN
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
NotGenerated
0
Event not generated
Generated
1
Event generated
Event generated from pin specified in CONFIG[n].PSEL
6.9.4.5 EVENTS_PORT
Address offset: 0x17C
Event generated from multiple input GPIO pins with SENSE mechanism enabled
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_PORT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Event generated from multiple input GPIO pins with SENSE
mechanism enabled
NotGenerated
0
Event not generated
Generated
1
Event generated
6.9.4.6 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
I
Reset 0x00000000
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID
Access
Field
A-H
RW IN[i] (i=0..7)
I
H G F E D C B A
Value ID
Value
Description
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Write '1' to enable interrupt for event IN[i]
RW PORT
Write '1' to enable interrupt for event PORT
6.9.4.7 INTENCLR
Address offset: 0x308
Disable interrupt
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Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
I
Reset 0x00000000
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID
Access
Field
A-H
RW IN[i] (i=0..7)
I
H G F E D C B A
Value ID
Value
Description
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Write '1' to disable interrupt for event IN[i]
RW PORT
Write '1' to disable interrupt for event PORT
6.9.4.8 CONFIG[n] (n=0..7)
Address offset: 0x510 + (n × 0x4)
Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
E
Reset 0x00000000
ID
Access
Field
A
RW MODE
D D
B B B B B
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Mode
Disabled
0
Event
1
Disabled. Pin specified by PSEL will not be acquired by the
GPIOTE module.
Event mode
The pin specified by PSEL will be configured as an input and
the IN[n] event will be generated if operation specified in
POLARITY occurs on the pin.
Task
3
Task mode
The GPIO specified by PSEL will be configured as an output
and triggering the SET[n], CLR[n] or OUT[n] task will
perform the operation specified by POLARITY on the pin.
When enabled as a task the GPIOTE module will acquire the
pin and the pin can no longer be written as a regular output
pin from the GPIO module.
B
RW PSEL
D
RW POLARITY
[0..31]
GPIO number associated with SET[n], CLR[n] and OUT[n]
tasks and IN[n] event
When In task mode: Operation to be performed on output
when OUT[n] task is triggered. When In event mode:
Operation on input that shall trigger IN[n] event.
None
0
Task mode: No effect on pin from OUT[n] task. Event mode:
no IN[n] event generated on pin activity.
LoToHi
1
HiToLo
2
Task mode: Set pin from OUT[n] task. Event mode: Generate
IN[n] event when rising edge on pin.
Task mode: Clear pin from OUT[n] task. Event mode:
Generate IN[n] event when falling edge on pin.
Toggle
3
Task mode: Toggle pin from OUT[n]. Event mode: Generate
IN[n] when any change on pin.
E
RW OUTINIT
When in task mode: Initial value of the output when the
GPIOTE channel is configured. When in event mode: No
effect.
Low
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0
Task mode: Initial value of pin before task triggering is low
128
Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
E
Reset 0x00000000
ID
Access
Field
D D
B B B B B
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
High
1
Task mode: Initial value of pin before task triggering is high
6.9.5 Electrical specification
6.10 PDM — Pulse density modulation interface
The pulse density modulation (PDM) module enables input of pulse density modulated signals from
external audio frontends, for example, digital microphones. The PDM module generates the PDM clock
and supports single-channel or dual-channel (Left and Right) data input. Data is transferred directly to
RAM buffers using EasyDMA.
Listed here are the main features for PDM:
•
•
•
•
Up to two PDM microphones configured as a Left/Right pair using the same data input
16 kHz output sample rate, 16-bit samples
EasyDMA support for sample buffering
HW decimation filters
The PDM module illustrated in PDM module on page 129 is interfacing up to two digital microphones
with the PDM interface. It implements EasyDMA, which relieves real-time requirements associated with
controlling the PDM slave from a low priority CPU execution context. It also includes all the necessary
digital filter elements to produce PCM samples. The PDM module allows continuous audio streaming.
CLK
Band-pass and
Decimation (left)
PDM to PCM
Band-pass and
Decimation (right)
RAM
PDM to PCM
EasyDMA
Sampling
DIN
Master clock
generator
Figure 41: PDM module
6.10.1 Master clock generator
The FREQ field in the master clock's PDMCLKCTRL register allows adjusting the PDM clock's frequency.
The master clock generator does not add any jitter to the HFCLK source chosen. It is recommended (but
not mandatory) to use the Xtal as HFCLK source.
6.10.2 Module operation
By default, bits from the left PDM microphone are sampled on PDM_CLK falling edge, bits for the right are
sampled on the rising edge of PDM_CLK, resulting in two bitstreams. Each bitstream is fed into a digital
filter which converts the PDM stream into 16-bit PCM samples, and filters and down-samples them to
reach the appropriate sample rate.
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The EDGE field in the MODE register allows swapping Left and Right, so that Left will be sampled on rising
edge, and Right on falling.
The PDM module uses EasyDMA to store the samples coming out from the filters into one buffer in RAM.
Depending on the mode chosen in the OPERATION field in the MODE register, memory either contains
alternating left and right 16-bit samples (Stereo), or only left 16-bit samples (Mono).
To ensure continuous PDM sampling, it is up to the application to update the EasyDMA destination
address pointer as the previous buffer is filled.
The continuous transfer can be started or stopped by sending the START and STOP tasks. STOP becomes
effective after the current frame has finished transferring, which will generate the STOPPED event. The
STOPPED event indicates that all activity in the module are finished, and that the data is available in RAM
(EasyDMA has finished transferring as well). Attempting to restart before receiving the STOPPED event
may result in unpredictable behaviour.
6.10.3 Decimation filter
In order to convert the incoming data stream into PCM audio samples, a decimation filter is included in
the PDM interface module.
The input of the filter is the two-channel PDM serial stream (with left channel on clock high, right channel
on clock low), its output is 2 × 16-bit PCM samples at a sample rate 64 times lower than the PDM clock
rate.
The filter stage of each channel is followed by a digital volume control, to attenuate or amplify the output
samples in a range of -20 dB to +20 dB around the default (reset) setting, defined by GPDM,default. The gain
is controlled by the GAINL and GAINR registers.
As an example, if the goal is to achieve 2500 RMS output samples (16 bit) with a 1 kHz 90 dBA signal
into a -26 dBFS sensitivity PDM microphone, the user will have to sum the PDM module's default gain
( GPDM,default ) and the gain introduced by the microphone and acoustic path of his implementation (an
attenuation would translate into a negative gain), and adjust GAINL and GAINR by this amount. Assuming
that only the PDM module influences the gain, GAINL and GAINR must be set to -GPDM,default dB to achieve
the requirement.
With GPDM,default=3.2 dB, and as GAINL and GAINR are expressed in 0.5 dB steps, the closest value to
program would be 3.0 dB, which can be calculated as:
GAINL = GAINR = (DefaultGain - (2 * 3))
Remember to check that the resulting values programmed into GAINL and GAINR fall within MinGain and
MaxGain.
6.10.4 EasyDMA
Samples will be written directly to RAM, and EasyDMA must be configured accordingly.
The address pointer for the EasyDMA channel is set in SAMPLE.PTR register. If the destination address set
in SAMPLE.PTR is not pointing to the Data RAM region, an EasyDMA transfer may result in a HardFault or
RAM corruption. See Memory on page 16 for more information about the different memory regions.
DMA supports Stereo (Left+Right 16-bit samples) and Mono (Left only) data transfer, depending on setting
in the OPERATION field in the MODE register. The samples are stored little endian.
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MODE.OPERATION
Bits per sample
Stereo
32 (2x16)
Mono
16
Result stored per RAM
Physical RAM allocated
Result boundary indexes Note
word
(32 bit words)
in RAM
L+R
ceil(SAMPLE.MAXCNT/2) R0=[31:16]; L0=[15:0]
2xL
ceil(SAMPLE.MAXCNT/2) L1=[31:16]; L0=[15:0]
Default
Table 43: DMA sample storage
The destination buffer in RAM consists of one block, the size of which is set in SAMPLE.MAXCNT register.
Format is number of 16-bit samples. The physical RAM allocated is always:
(RAM allocation, in bytes) = SAMPLE.MAXCNT * 2;
(but the mapping of the samples depends on MODE.OPERATION.
If OPERATION=Stereo, RAM will contain a succession of Left and Right samples.
If OPERATION=Mono, RAM will contain a succession of mono samples.
For a given value of SAMPLE.MAXCNT, the buffer in RAM can contain half the stereo sampling time as
compared to the mono sampling time.
The PDM acquisition can be started by the START task, after the SAMPLE.PTR and SAMPLE.MAXCNT
registers have been written. When starting the module, it will take some time for the filters to start
outputting valid data. Transients from the PDM microphone itself may also occur. The first few samples
(typically around 50) might hence contain invalid values or transients. It is therefore advised to discard the
first few samples after a PDM start.
As soon as the STARTED event is received, the firmware can write the next SAMPLE.PTR value (this register
is double-buffered), to ensure continuous operation.
When the buffer in RAM is filled with samples, an END event is triggered. The firmware can start
processing the data in the buffer. Meanwhile, the PDM module starts acquiring data into the new buffer
pointed to by SAMPLE.PTR, and sends a new STARTED event, so that the firmware can update SAMPLE.PTR
to the next buffer address.
6.10.5 Hardware example
Connect the microphone clock to CLK, and data to DIN.
Vdd
L/R
nRFxxxxx
CLK
CLK
DATA
DIN
CLK
DIN
Figure 42: Example of a single PDM microphone, wired as left
Vdd
L/R
nRFxxxxx
CLK
CLK
DATA
DIN
CLK
DIN
Figure 43: Example of a single PDM microphone, wired as right
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Peripherals
Note that in a single-microphone (mono) configuration, depending on the microphone’s implementation,
either the left or the right channel (sampled at falling or rising CLK edge respectively) will contain reliable
data. If two microphones are used, one of them has to be set as left, the other as right (L/R pin tied high or
to GND on the respective microphone). It is strongly recommended to use two microphones of exactly the
same brand and type so that their timings in left and right operation match.
Vdd
L/R
nRFxxxxx
CLK
CLK
DATA
DIN
Vdd
CLK
L/R
DATA
CLK
DIN
Figure 44: Example of two PDM microphones
6.10.6 Pin configuration
The CLK and DIN signals associated to the PDM module are mapped to physical pins according to the
configuration specified in the PSEL.CLK and PSEL.DIN registers respectively. If the CONNECT field in any
PSEL register is set to Disconnected, the associated PDM module signal will not be connected to the
required physical pins, and will not operate properly.
The PSEL.CLK and PSEL.DIN registers and their configurations are only used as long as the PDM module is
enabled, and retained only as long as the device is in System ON mode. See POWER — Power supply on
page 48 for more information about power modes. When the peripheral is disabled, the pins will behave
as regular GPIOs, and use the configuration in their respective OUT bit field and PIN_CNF[n] register.
To ensure correct behaviour in the PDM module, the pins used by the PDM module must be configured
in the GPIO peripheral as described in GPIO configuration before enabling peripheral on page 132
before enabling the PDM module. This is to ensure that the pins used by the PDM module are driven
correctly if the PDM module itself is temporarily disabled or the device temporarily enters System OFF.
This configuration must be retained in the GPIO for the selected I/Os as long as the PDM module is
supposed to be connected to an external PDM circuit.
Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in
unpredictable behaviour.
PDM signal
PDM pin
Direction
Output value
CLK
As specified in PSEL.CLK
Output
0
DIN
As specified in PSEL.DIN
Input
Not applicable
Table 44: GPIO configuration before enabling peripheral
6.10.7 Registers
Base address
Peripheral
Instance
Description
0x4001D000
PDM
PDM
Pulse-density modulation (digital
Configuration
microphone interface)
Table 45: Instances
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Comment
Peripherals
Register
Offset
Description
TASKS_START
0x000
Starts continuous PDM transfer
TASKS_STOP
0x004
Stops PDM transfer
EVENTS_STARTED
0x100
PDM transfer has started
EVENTS_STOPPED
0x104
PDM transfer has finished
EVENTS_END
0x108
The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a
INTEN
0x300
Enable or disable interrupt
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
ENABLE
0x500
PDM module enable register
PDMCLKCTRL
0x504
PDM clock generator control
MODE
0x508
Defines the routing of the connected PDM microphones' signals
GAINL
0x518
Left output gain adjustment
GAINR
0x51C
Right output gain adjustment
PSEL.CLK
0x540
Pin number configuration for PDM CLK signal
PSEL.DIN
0x544
Pin number configuration for PDM DIN signal
SAMPLE.PTR
0x560
RAM address pointer to write samples to with EasyDMA
SAMPLE.MAXCNT
0x564
Number of samples to allocate memory for in EasyDMA mode
STOP task has been received) to Data RAM
Table 46: Register overview
6.10.7.1 TASKS_START
Address offset: 0x000
Starts continuous PDM transfer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Trigger
1
Description
TASKS_START
Starts continuous PDM transfer
Trigger task
6.10.7.2 TASKS_STOP
Address offset: 0x004
Stops PDM transfer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Trigger
1
Description
TASKS_STOP
Stops PDM transfer
Trigger task
6.10.7.3 EVENTS_STARTED
Address offset: 0x100
PDM transfer has started
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_STARTED
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
NotGenerated
0
Event not generated
Generated
1
Event generated
PDM transfer has started
6.10.7.4 EVENTS_STOPPED
Address offset: 0x104
PDM transfer has finished
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_STOPPED
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
NotGenerated
0
Event not generated
Generated
1
Event generated
PDM transfer has finished
6.10.7.5 EVENTS_END
Address offset: 0x108
The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task
has been received) to Data RAM
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_END
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
The PDM has written the last sample specified by
SAMPLE.MAXCNT (or the last sample after a STOP task has
been received) to Data RAM
NotGenerated
0
Event not generated
Generated
1
Event generated
6.10.7.6 INTEN
Address offset: 0x300
Enable or disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
C B A
Reset 0x00000000
ID
Access
Field
A
RW STARTED
B
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Disabled
0
Disable
Enabled
1
Enable
Disabled
0
Disable
Enabled
1
Enable
Enable or disable interrupt for event STARTED
RW STOPPED
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Enable or disable interrupt for event STOPPED
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Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
C B A
Reset 0x00000000
ID
Access
Field
C
RW END
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Disabled
0
Disable
Enabled
1
Enable
Enable or disable interrupt for event END
6.10.7.7 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
C B A
Reset 0x00000000
ID
Access
Field
A
RW STARTED
B
C
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Write '1' to enable interrupt for event STARTED
RW STOPPED
Write '1' to enable interrupt for event STOPPED
RW END
Write '1' to enable interrupt for event END
6.10.7.8 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
C B A
Reset 0x00000000
ID
Access
Field
A
RW STARTED
B
C
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Write '1' to disable interrupt for event STARTED
RW STOPPED
Write '1' to disable interrupt for event STOPPED
RW END
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Write '1' to disable interrupt for event END
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Peripherals
6.10.7.9 ENABLE
Address offset: 0x500
PDM module enable register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW ENABLE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Disabled
0
Disable
Enabled
1
Enable
Enable or disable PDM module
6.10.7.10 PDMCLKCTRL
Address offset: 0x504
PDM clock generator control
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x08400000
0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID
Access
Field
A
RW FREQ
Value ID
Value
Description
1000K
0x08000000
PDM_CLK = 32 MHz / 32 = 1.000 MHz
Default
0x08400000
PDM_CLK = 32 MHz / 31 = 1.032 MHz
1067K
0x08800000
PDM_CLK = 32 MHz / 30 = 1.067 MHz
PDM_CLK frequency
6.10.7.11 MODE
Address offset: 0x508
Defines the routing of the connected PDM microphones' signals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
B A
Reset 0x00000000
ID
Access
Field
A
RW OPERATION
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Stereo
0
Mono
1
Description
Mono or stereo operation
Sample and store one pair (Left + Right) of 16bit samples
per RAM word R=[31:16]; L=[15:0]
Sample and store two successive Left samples (16 bit each)
per RAM word L1=[31:16]; L0=[15:0]
B
RW EDGE
Defines on which PDM_CLK edge Left (or mono) is sampled
LeftFalling
0
Left (or mono) is sampled on falling edge of PDM_CLK
LeftRising
1
Left (or mono) is sampled on rising edge of PDM_CLK
6.10.7.12 GAINL
Address offset: 0x518
Left output gain adjustment
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A
Reset 0x00000028
ID
Access
Field
A
RW GAINL
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0
Value ID
Value
Description
Left output gain adjustment, in 0.5 dB steps, around the
default module gain (see electrical parameters)
0x00 -20 dB gain adjust
0x01 -19.5 dB gain adjust
(...)
0x27 -0.5 dB gain adjust
0x28 0 dB gain adjust
0x29 +0.5 dB gain adjust
(...)
0x4F +19.5 dB gain adjust
0x50 +20 dB gain adjust
MinGain
0x00
-20dB gain adjustment (minimum)
DefaultGain
0x28
0dB gain adjustment ('2500 RMS' requirement)
MaxGain
0x50
+20dB gain adjustment (maximum)
6.10.7.13 GAINR
Address offset: 0x51C
Right output gain adjustment
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A
Reset 0x00000028
ID
Access
Field
A
RW GAINR
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0
Value ID
Value
Description
Right output gain adjustment, in 0.5 dB steps, around the
default module gain (see electrical parameters)
MinGain
0x00
-20dB gain adjustment (minimum)
DefaultGain
0x28
0dB gain adjustment ('2500 RMS' requirement)
MaxGain
0x50
+20dB gain adjustment (maximum)
6.10.7.14 PSEL.CLK
Address offset: 0x540
Pin number configuration for PDM CLK signal
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
B
Reset 0xFFFFFFFF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID
Access
Field
A
RW PIN
B
RW CONNECT
4454_140 v1.0
Value ID
A A A A A
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
137
Peripherals
6.10.7.15 PSEL.DIN
Address offset: 0x544
Pin number configuration for PDM DIN signal
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
B
Reset 0xFFFFFFFF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID
Access
Field
A
RW PIN
Value ID
B
RW CONNECT
A A A A A
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
6.10.7.16 SAMPLE.PTR
Address offset: 0x560
RAM address pointer to write samples to with EasyDMA
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID
Access
Field
A
RW SAMPLEPTR
Value ID
Value
Description
Address to write PDM samples to over DMA
6.10.7.17 SAMPLE.MAXCNT
Address offset: 0x564
Number of samples to allocate memory for in EasyDMA mode
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A
Reset 0x00000000
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID
Access
Field
Value ID
A
RW BUFFSIZE
Value
Description
[0..32767]
Length of DMA RAM allocation in number of samples
6.10.8 Electrical specification
6.10.8.1 PDM Electrical Specification
Symbol
Description
fPDM,CLK
PDM clock speed
tPDM,JITTER
Jitter in PDM clock output
TdPDM,CLK
PDM clock duty cycle
tPDM,DATA
tPDM,cv
tPDM,ci
Allowed (other) clock edge to data invalid
0
ns
tPDM,s
Data setup time at fPDM,CLK=1.024 MHz
65
ns
tPDM,h
Data hold time at fPDM,CLK=1.024 MHz
0
GPDM,default
Default (reset) absolute gain of the PDM module
4454_140 v1.0
Min.
Typ.
Max.
1.032
Units
MHz
20
ns
60
%
Decimation filter delay
5
ms
Allowed clock edge to data valid
125
ns
40
50
ns
3.2
138
dB
Peripherals
tPDM,CLK
CLK
tPDM,cv
tPDM,s
tPDM,h=tPDM,ci
DIN (L)
tPDM,cv
tPDM,s tPDM,h=tPDM,ci
DIN(R)
Figure 45: PDM timing diagram
6.11 PPI — Programmable peripheral interconnect
The programmable peripheral interconnect (PPI) enables peripherals to interact autonomously with each
other using tasks and events independent of the CPU. The PPI allows precise synchronization between
peripherals when real-time application constraints exist and eliminates the need for CPU activity to
implement behavior which can be predefined using PPI.
CH[1].EEP
CH[0].EEP
Peripheral 1
Peripheral 2
CH[n].EEP
Event 1
Event 2
Event 1
Event 2
Event 3
0
0
0
1
1
1
n
n
n
CHEN
CHG[0] ... CHG[m]
16MHz
Task 1
Task 1
Task 2
Task 3
CH[0].TEP
Peripheral 1
Peripheral 2
FORK[0].TEP
Figure 46: PPI block diagram
The PPI system has, in addition to the fully programmable peripheral interconnections, a set of channels
where the event end point (EEP) and task end points (TEP) are fixed in hardware. These fixed channels can
be individually enabled, disabled, or added to PPI channel groups (see CHG[n] registers), in the same way
as ordinary PPI channels.
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Instance
Channel
Number of channels
PPI
0-19
20
PPI (fixed)
20-31
12
Table 47: Configurable and fixed PPI channels
The PPI provides a mechanism to automatically trigger a task in one peripheral as a result of an event
occurring in another peripheral. A task is connected to an event through a PPI channel. The PPI channel
is composed of three end point registers, one EEP and two TEPs. A peripheral task is connected to a TEP
using the address of the task register associated with the task. Similarly, a peripheral event is connected to
an EEP using the address of the event register associated with the event.
On each PPI channel, the signals are synchronized to the 16 MHz clock, to avoid any internal violation
of setup and hold timings. As a consequence, events that are synchronous to the 16 MHz clock will be
delayed by one clock period, while other asynchronous events will be delayed by up to one 16 MHz clock
period.
Note that shortcuts (as defined in the SHORTS register in each peripheral) are not affected by this 16 MHz
synchronization, and are therefore not delayed.
Each TEP implements a fork mechanism that enables a second task to be triggered at the same time as the
task specified in the TEP is triggered. This second task is configured in the task end point register in the
FORK registers groups, e.g. FORK.TEP[0] is associated with PPI channel CH[0].
There are two ways of enabling and disabling PPI channels:
• Enable or disable PPI channels individually using the CHEN, CHENSET, and CHENCLR registers.
• Enable or disable PPI channels in PPI channel groups through the groups’ ENABLE and DISABLE tasks.
Prior to these tasks being triggered, the PPI channel group must be configured to define which PPI
channels belong to which groups.
Note that when a channel belongs to two groups m and n, and the tasks CHG[m].EN and CHG[n].DIS occur
simultaneously (m and n can be equal or different), the CHG[m].EN on that channel has priority.
PPI tasks (for example, CHG[0].EN) can be triggered through the PPI like any other task, which means they
can be hooked to a PPI channel as a TEP. One event can trigger multiple tasks by using multiple channels
and one task can be triggered by multiple events in the same way.
6.11.1 Pre-programmed channels
Some of the PPI channels are pre-programmed. These channels cannot be configured by the CPU, but can
be added to groups and enabled and disabled like the general purpose PPI channels. The FORK TEP for
these channels are still programmable and can be used by the application.
For a list of pre-programmed PPI channels, see the table below.
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Peripherals
Channel
EEP
TEP
20
TIMER0->EVENTS_COMPARE[0]
RADIO->TASKS_TXEN
21
TIMER0->EVENTS_COMPARE[0]
RADIO->TASKS_RXEN
22
TIMER0->EVENTS_COMPARE[1]
RADIO->TASKS_DISABLE
23
RADIO->EVENTS_BCMATCH
AAR->TASKS_START
24
RADIO->EVENTS_READY
CCM->TASKS_KSGEN
25
RADIO->EVENTS_ADDRESS
CCM->TASKS_CRYPT
26
RADIO->EVENTS_ADDRESS
TIMER0->TASKS_CAPTURE[1]
27
RADIO->EVENTS_END
TIMER0->TASKS_CAPTURE[2]
28
RTC0->EVENTS_COMPARE[0]
RADIO->TASKS_TXEN
29
RTC0->EVENTS_COMPARE[0]
RADIO->TASKS_RXEN
30
RTC0->EVENTS_COMPARE[0]
TIMER0->TASKS_CLEAR
31
RTC0->EVENTS_COMPARE[0]
TIMER0->TASKS_START
Table 48: Pre-programmed channels
6.11.2 Registers
Base address
Peripheral
Instance
Description
Configuration
0x4001F000
PPI
PPI
Programmable peripheral interconnect
Table 49: Instances
Register
Offset
Description
TASKS_CHG[0].EN
0x000
Enable channel group 0
TASKS_CHG[0].DIS
0x004
Disable channel group 0
TASKS_CHG[1].EN
0x008
Enable channel group 1
TASKS_CHG[1].DIS
0x00C
Disable channel group 1
TASKS_CHG[2].EN
0x010
Enable channel group 2
TASKS_CHG[2].DIS
0x014
Disable channel group 2
TASKS_CHG[3].EN
0x018
Enable channel group 3
TASKS_CHG[3].DIS
0x01C
Disable channel group 3
TASKS_CHG[4].EN
0x020
Enable channel group 4
TASKS_CHG[4].DIS
0x024
Disable channel group 4
TASKS_CHG[5].EN
0x028
Enable channel group 5
TASKS_CHG[5].DIS
0x02C
Disable channel group 5
CHEN
0x500
Channel enable register
CHENSET
0x504
Channel enable set register
CHENCLR
0x508
Channel enable clear register
CH[0].EEP
0x510
Channel 0 event end-point
CH[0].TEP
0x514
Channel 0 task end-point
CH[1].EEP
0x518
Channel 1 event end-point
CH[1].TEP
0x51C
Channel 1 task end-point
CH[2].EEP
0x520
Channel 2 event end-point
CH[2].TEP
0x524
Channel 2 task end-point
CH[3].EEP
0x528
Channel 3 event end-point
CH[3].TEP
0x52C
Channel 3 task end-point
CH[4].EEP
0x530
Channel 4 event end-point
CH[4].TEP
0x534
Channel 4 task end-point
CH[5].EEP
0x538
Channel 5 event end-point
CH[5].TEP
0x53C
Channel 5 task end-point
CH[6].EEP
0x540
Channel 6 event end-point
CH[6].TEP
0x544
Channel 6 task end-point
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Peripherals
Register
Offset
Description
CH[7].EEP
0x548
Channel 7 event end-point
CH[7].TEP
0x54C
Channel 7 task end-point
CH[8].EEP
0x550
Channel 8 event end-point
CH[8].TEP
0x554
Channel 8 task end-point
CH[9].EEP
0x558
Channel 9 event end-point
CH[9].TEP
0x55C
Channel 9 task end-point
CH[10].EEP
0x560
Channel 10 event end-point
CH[10].TEP
0x564
Channel 10 task end-point
CH[11].EEP
0x568
Channel 11 event end-point
CH[11].TEP
0x56C
Channel 11 task end-point
CH[12].EEP
0x570
Channel 12 event end-point
CH[12].TEP
0x574
Channel 12 task end-point
CH[13].EEP
0x578
Channel 13 event end-point
CH[13].TEP
0x57C
Channel 13 task end-point
CH[14].EEP
0x580
Channel 14 event end-point
CH[14].TEP
0x584
Channel 14 task end-point
CH[15].EEP
0x588
Channel 15 event end-point
CH[15].TEP
0x58C
Channel 15 task end-point
CH[16].EEP
0x590
Channel 16 event end-point
CH[16].TEP
0x594
Channel 16 task end-point
CH[17].EEP
0x598
Channel 17 event end-point
CH[17].TEP
0x59C
Channel 17 task end-point
CH[18].EEP
0x5A0
Channel 18 event end-point
CH[18].TEP
0x5A4
Channel 18 task end-point
CH[19].EEP
0x5A8
Channel 19 event end-point
CH[19].TEP
0x5AC
Channel 19 task end-point
CHG[0]
0x800
Channel group 0
CHG[1]
0x804
Channel group 1
CHG[2]
0x808
Channel group 2
CHG[3]
0x80C
Channel group 3
CHG[4]
0x810
Channel group 4
CHG[5]
0x814
Channel group 5
FORK[0].TEP
0x910
Channel 0 task end-point
FORK[1].TEP
0x914
Channel 1 task end-point
FORK[2].TEP
0x918
Channel 2 task end-point
FORK[3].TEP
0x91C
Channel 3 task end-point
FORK[4].TEP
0x920
Channel 4 task end-point
FORK[5].TEP
0x924
Channel 5 task end-point
FORK[6].TEP
0x928
Channel 6 task end-point
FORK[7].TEP
0x92C
Channel 7 task end-point
FORK[8].TEP
0x930
Channel 8 task end-point
FORK[9].TEP
0x934
Channel 9 task end-point
FORK[10].TEP
0x938
Channel 10 task end-point
FORK[11].TEP
0x93C
Channel 11 task end-point
FORK[12].TEP
0x940
Channel 12 task end-point
FORK[13].TEP
0x944
Channel 13 task end-point
FORK[14].TEP
0x948
Channel 14 task end-point
FORK[15].TEP
0x94C
Channel 15 task end-point
FORK[16].TEP
0x950
Channel 16 task end-point
FORK[17].TEP
0x954
Channel 17 task end-point
FORK[18].TEP
0x958
Channel 18 task end-point
FORK[19].TEP
0x95C
Channel 19 task end-point
FORK[20].TEP
0x960
Channel 20 task end-point
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Peripherals
Register
Offset
Description
FORK[21].TEP
0x964
Channel 21 task end-point
FORK[22].TEP
0x968
Channel 22 task end-point
FORK[23].TEP
0x96C
Channel 23 task end-point
FORK[24].TEP
0x970
Channel 24 task end-point
FORK[25].TEP
0x974
Channel 25 task end-point
FORK[26].TEP
0x978
Channel 26 task end-point
FORK[27].TEP
0x97C
Channel 27 task end-point
FORK[28].TEP
0x980
Channel 28 task end-point
FORK[29].TEP
0x984
Channel 29 task end-point
FORK[30].TEP
0x988
Channel 30 task end-point
FORK[31].TEP
0x98C
Channel 31 task end-point
Table 50: Register overview
6.11.2.1 TASKS_CHG[n].EN (n=0..5)
Address offset: 0x000 + (n × 0x8)
Enable channel group n
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
EN
Enable channel group n
Trigger
1
Trigger task
6.11.2.2 TASKS_CHG[n].DIS (n=0..5)
Address offset: 0x004 + (n × 0x8)
Disable channel group n
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Trigger
1
Description
DIS
Disable channel group n
Trigger task
6.11.2.3 CHEN
Address offset: 0x500
Channel enable register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
f
Reset 0x00000000
ID
Access
Field
A-f
RW CH[i] (i=0..31)
4454_140 v1.0
e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Disabled
0
Disable channel
Enabled
1
Enable channel
Enable or disable channel i
143
Peripherals
6.11.2.4 CHENSET
Address offset: 0x504
Channel enable set register
Read: reads value of CH{i} field in CHEN register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
f
Reset 0x00000000
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID
Access
Field
A-f
RW CH[i] (i=0..31)
e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A
Value ID
Value
Description
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Set
1
Write: Enable channel
Channel i enable set register. Writing '0' has no effect
6.11.2.5 CHENCLR
Address offset: 0x508
Channel enable clear register
Read: reads value of CH{i} field in CHEN register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
f
Reset 0x00000000
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID
Access
Field
A-f
RW CH[i] (i=0..31)
e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A
Value ID
Value
Description
Disabled
0
Read: channel disabled
Enabled
1
Read: channel enabled
Clear
1
Write: disable channel
Channel i enable clear register. Writing '0' has no effect
6.11.2.6 CH[n].EEP (n=0..19)
Address offset: 0x510 + (n × 0x8)
Channel n event end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID
Access
Field
A
RW EEP
Value ID
Value
Description
Pointer to event register. Accepts only addresses to registers
from the Event group.
6.11.2.7 CH[n].TEP (n=0..19)
Address offset: 0x514 + (n × 0x8)
Channel n task end-point
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Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID
Access
Field
A
RW TEP
Value ID
Value
Description
Pointer to task register. Accepts only addresses to registers
from the Task group.
6.11.2.8 CHG[n] (n=0..5)
Address offset: 0x800 + (n × 0x4)
Channel group n
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
f
Reset 0x00000000
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID
Access
Field
A-f
RW CH[i] (i=0..31)
e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A
Value ID
Value
Description
Excluded
0
Exclude
Included
1
Include
Include or exclude channel i
6.11.2.9 FORK[n].TEP (n=0..31)
Address offset: 0x910 + (n × 0x4)
Channel n task end-point
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
RW TEP
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Pointer to task register
6.12 PWM — Pulse width modulation
The pulse with modulation (PWM) module enables the generation of pulse width modulated signals
on GPIO. The module implements an up or up-and-down counter with four PWM channels that drive
assigned GPIOs.
The following are the main features of a PWM module:
•
•
•
•
•
Programmable PWM frequency
Up to four PWM channels with individual polarity and duty cycle values
Edge or center-aligned pulses across PWM channels
Multiple duty cycle arrays (sequences) defined in RAM
Autonomous and glitch-free update of duty cycle values directly from memory through EasyDMA (no
CPU involvement)
• Change of polarity, duty cycle, and base frequency possibly on every PWM period
• RAM sequences can be repeated or connected into loops
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Peripherals
Sequence 0
DATA RAM
STARTED
STOPPED
EasyDMA
START
Sequence 1
PWM
STOP
SEQSTART[0]
SEQSTART[1]
SEQ[n].REFRESH
SEQSTARTED[0]
SEQSTARTED[1]
SEQEND[0]
SEQEND[1]
Decoder
NEXTSTEP
Carry/Reload
COMP0
PSEL.OUT[0]
COMP1
PSEL.OUT[1]
COMP2
PSEL.OUT[2]
COMP3
PSEL.OUT[3]
Wave Counter
PWM_CLK
COUNTERTOP
PRESCALER
Figure 47: PWM module
6.12.1 Wave counter
The wave counter is responsible for generating the pulses at a duty cycle that depends on the compare
values, and at a frequency that depends on COUNTERTOP.
There is one common 15-bit counter with four compare channels. Thus, all four channels will share the
same period (PWM frequency), but can have individual duty cycle and polarity. The polarity is set by a
value read from RAM (see figure Decoder memory access modes on page 149). Whether the counter
counts up, or up and down, is controlled by the MODE register.
The timer top value is controlled by the COUNTERTOP register. This register value, in conjunction with the
selected PRESCALER of the PWM_CLK, will result in a given PWM period. A COUNTERTOP value smaller
than the compare setting will result in a state where no PWM edges are generated. OUT[n] is held high,
given that the polarity is set to FallingEdge. All compare registers are internal and can only be configured
through decoder presented later. COUNTERTOP can be safely written at any time.
Sampling follows the START task. If DECODER.LOAD=WaveForm, the register value is ignored and taken
from RAM instead (see section Decoder with EasyDMA on page 149 for more details). If DECODER.LOAD
is anything else than the WaveForm, it is sampled following a STARTSEQ[n] task and when loading a new
value from RAM during a sequence playback.
The following figure shows the counter operating in up mode (MODE=PWM_MODE_Up), with three PWM
channels with the same frequency but different duty cycle:
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Peripherals
COUNTERTOP
COMP1
COMP0
OUT[0]
OUT[1]
Figure 48: PWM counter in up mode example - FallingEdge polarity
The counter is automatically reset to zero when COUNTERTOP is reached and OUT[n] will invert. OUT[n]
is held low if the compare value is 0 and held high if set to COUNTERTOP, given that the polarity is set to
FallingEdge. Counter running in up mode results in pulse widths that are edge-aligned. The following is the
code for the counter in up mode example:
uint16_t pwm_seq[4] = {PWM_CH0_DUTY, PWM_CH1_DUTY, PWM_CH2_DUTY, PWM_CH3_DUTY};
NRF_PWM0->PSEL.OUT[0] = (first_pin PSEL.OUT[0] = (first_pin PSEL.OUT[0] = (first_pin DECODER
= (PWM_LOOP_CNT_Disabled SEQ[0].PTR
= (PWM_DECODER_LOAD_Common SEQ[0].CNT
(PWM_DECODER_MODE_RefreshCount TASKS_SEQSTART[0] = 1;
To completely stop the PWM generation and force the associated pins to a defined state, a STOP task can
be triggered at any time. A STOPPED event is generated when the PWM generation has stopped at the
end of currently running PWM period, and the pins go into their idle state as defined in GPIO OUT register.
PWM generation can then only be restarted through a SEQSTART[n] task. SEQSTART[n] will resume PWM
generation after having loaded the first value from the RAM buffer defined in the SEQ[n].PTR register.
The table below indicates when specific registers get sampled by the hardware. Care should be taken
when updating these registers to avoid that values are applied earlier than expected.
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Peripherals
Register
Taken into account by hardware
Recommended (safe) update
SEQ[n].PTR
When sending the SEQSTART[n] task
After having received the SEQSTARTED[n] event
SEQ[n].CNT
When sending the SEQSTART[n] task
After having received the SEQSTARTED[n] event
SEQ[0].ENDDELAY
When sending the SEQSTART[0] task
Before starting sequence [0] through a SEQSTART[0] task
Every time a new value from sequence [0] has been loaded from
When no more value from sequence [0] gets loaded from RAM
RAM and gets applied to the Wave Counter (indicated by the
(indicated by the SEQEND[0] event)
PWMPERIODEND event)
At any time during sequence [1] (which starts when the
SEQSTARTED[1] event is generated)
SEQ[1].ENDDELAY
When sending the SEQSTART[1] task
Before starting sequence [1] through a SEQSTART[1] task
Every time a new value from sequence [1] has been loaded from
When no more value from sequence [1] gets loaded from RAM
RAM and gets applied to the Wave Counter (indicated by the
(indicated by the SEQEND[1] event)
PWMPERIODEND event)
At any time during sequence [0] (which starts when the
SEQSTARTED[0] event is generated)
SEQ[0].REFRESH
When sending the SEQSTART[0] task
Before starting sequence [0] through a SEQSTART[0] task
Every time a new value from sequence [0] has been loaded from
At any time during sequence [1] (which starts when the
RAM and gets applied to the Wave Counter (indicated by the
SEQSTARTED[1] event is generated)
PWMPERIODEND event)
SEQ[1].REFRESH
When sending the SEQSTART[1] task
Before starting sequence [1] through a SEQSTART[1] task
Every time a new value from sequence [1] has been loaded from
At any time during sequence [0] (which starts when the
RAM and gets applied to the Wave Counter (indicated by the
SEQSTARTED[0] event is generated)
PWMPERIODEND event)
COUNTERTOP
MODE
In DECODER.LOAD=WaveForm: this register is ignored.
Before starting PWM generation through a SEQSTART[n] task
In all other LOAD modes: at the end of current PWM period
After a STOP task has been triggered, and the STOPPED event has
(indicated by the PWMPERIODEND event)
been received.
Immediately
Before starting PWM generation through a SEQSTART[n] task
After a STOP task has been triggered, and the STOPPED event has
been received.
DECODER
Immediately
Before starting PWM generation through a SEQSTART[n] task
After a STOP task has been triggered, and the STOPPED event has
been received.
PRESCALER
Immediately
Before starting PWM generation through a SEQSTART[n] task
After a STOP task has been triggered, and the STOPPED event has
been received.
LOOP
Immediately
Before starting PWM generation through a SEQSTART[n] task
After a STOP task has been triggered, and the STOPPED event has
been received.
PSEL.OUT[n]
Immediately
Before enabling the PWM instance through the ENABLE register
Table 51: When to safely update PWM registers
Note: SEQ[n].REFRESH and SEQ[n].ENDDELAY are ignored at the end of a complex sequence,
indicated by a LOOPSDONE event. The reason for this is that the last value loaded from RAM
is maintained until further action from software (restarting a new sequence, or stopping PWM
generation).
A more complex example, where LOOP.CNT>0, is shown in the following figure:
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Peripherals
SEQ[0].CNT=2, SEQ[1].CNT=3, SEQ[0].REFRESH=1, SEQ[1].REFRESH=0, SEQ[0].ENDDELAY=1, SEQ[1].ENDDELAY=0, LOOP.CNT=1
SEQ[0].PTR
P
O COMPARE
L
PWM clock period
Event/Tasks
SEQSTART[0]
P
O COMPARE
L
(continued below)
SEQSTARTED[0]
SEQEND[0]
SEQ[1].PTR
1 PWM period
SEQ[0].ENDDELAY=1
(continuation)
P
O COMPARE
L
P
O COMPARE
L
PWM generation maintains
last played value
Event/Tasks
SEQSTARTED[1]
SEQEND[1]
LOOPSDONE
Figure 52: Example using two sequences
In this case, an automated playback takes place, consisting of SEQ[0], delay 0, SEQ[1], delay 1, then again
SEQ[0], etc. The user can choose to start a complex playback with SEQ[0] or SEQ[1] through sending the
SEQSTART[0] or SEQSTART[1] task. The complex playback always ends with delay 1.
The two sequences 0 and 1 are defined by the addresses of value tables in RAM (pointed to by
SEQ[n].PTR) and the buffer size (SEQ[n].CNT). The rate at which a new value is loaded is defined
individually for each sequence by SEQ[n].REFRESH. The chaining of sequence 1 following the sequence 0 is
implicit, the LOOP.CNT register allows the chaining of sequence 1 to sequence 0 for a determined number
of times. In other words, it allows to repeat a complex sequence a number of times in a fully automated
way.
In the following code example, sequence 0 is defined with SEQ[0].REFRESH set to 1, meaning that a
new PWM duty cycle is pushed every second PWM period. This complex sequence is started with the
SEQSTART[0] task, so SEQ[0] is played first. Since SEQ[0].ENDDELAY=1 there will be one PWM period delay
between last period on sequence 0 and the first period on sequence 1. Since SEQ[1].ENDDELAY=0 there
is no delay 1, so SEQ[0] would be started immediately after the end of SEQ[1]. However, as LOOP.CNT is
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Peripherals
1, the playback stops after having played SEQ[1] only once, and both SEQEND[1] and LOOPSDONE are
generated (their order is not guaranteed in this case).
NRF_PWM0->PSEL.OUT[0] = (first_pin DECODER
= (1 SEQ[0].PTR
= (PWM_DECODER_LOAD_Common SEQ[0].CNT
(PWM_DECODER_MODE_RefreshCount SEQ[1].PTR
NRF_PWM0->SEQ[1].CNT
= ((uint32_t)(seq1_ram) SEQ[1].ENDDELAY = 0;
NRF_PWM0->TASKS_SEQSTART[0] = 1;
The decoder can also be configured to asynchronously load new PWM duty cycle. If the DECODER.MODE
register is set to NextStep, then the NEXTSTEP task will cause an update of internal compare registers on
the next PWM period.
The following figures provide an overview of each part of an arbitrary sequence, in various modes
(LOOP.CNT=0 and LOOP.CNT>0). In particular, the following are represented:
•
•
•
•
•
Initial and final duty cycle on the PWM output(s)
Chaining of SEQ[0] and SEQ[1] if LOOP.CNT>0
Influence of registers on the sequence
Events generated during a sequence
DMA activity (loading of next value and applying it to the output(s))
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Figure 54: Complex sequence (LOOP.CNT>0) starting with SEQ[0]
SEQ[1].ENDDELA
Y
SEQ[1].CNT
SEQ[0].ENDDELA
Y
SEQ[0].CNT
SEQ[1].CNT
(LOOP.CNT - 1) ...
EVENTS_SEQSTARTED[1]
EVENTS_SEQEND[1]
EVENTS_LOOPSDONE
EVENTS_SEQEND[0]
EVENTS_SEQSTARTED[0]
EVENTS_SEQSTARTED[1]
EVENTS_SEQEND[1]
SEQ[0].ENDDELA
Y
SEQ[0].CNT
SEQ[1].ENDDELA
Y
SEQ[1].CNT
LOOP.CNT
EVENTS_SEQEND[0]
EVENTS_SEQSTARTED[0]
EVENTS_SEQSTARTED[1]
EVENTS_SEQEND[1]
SEQ[0].ENDDELA
Y
SEQ[0].CNT
Loop counter
EVENTS_SEQEND[0]
TASKS_SEQSTART[0]
EVENTS_SEQSTARTED[0]
EVENTS_SEQEND[0]
TASKS_SEQSTART[0]
EVENTS_SEQSTARTED[0]
SEQ[0].ENDDELA
Y
SEQ[0].CNT
Peripherals
100% duty cycle
last loaded
duty cycle
maintained
Previously
loaded duty
cycle
New value load
0% duty cycle
Figure 53: Single shot (LOOP.CNT=0)
Note: The single-shot example also applies to SEQ[1]. Only SEQ[0] is represented for simplicity.
1
100% duty cycle
Previously
loaded duty
cycle
last loaded
duty cycle
maintained
New value load
0% duty cycle
Peripherals
SEQ[1].ENDDELA
Y
SEQ[1].CNT
SEQ[0].ENDDELA
Y
1
SEQ[0].CNT
SEQ[1].CNT
SEQ[0].ENDDELA
Y
(LOOP.CNT - 1) ...
SEQ[0].CNT
SEQ[1].CNT
SEQ[1].ENDDELA
Y
LOOP.CNT
Loop counter
100% duty cycle
Previously
loaded
duty cycle
last loaded
duty cycle
maintained
0% duty cycle
EVENTS_SEQSTARTED[1]
EVENTS_SEQEND[1]
EVENTS_LOOPSDONE
EVENTS_SEQEND[0]
EVENTS_SEQSTARTED[0]
EVENTS_SEQSTARTED[1]
EVENTS_SEQEND[1]
EVENTS_SEQEND[0]
EVENTS_SEQSTARTED[0]
TASKS_SEQSTART[1]
EVENTS_SEQSTARTED[1]
EVENTS_SEQEND[1]
New value load
Figure 55: Complex sequence (LOOP.CNT>0) starting with SEQ[1]
Note: If a sequence is in use in a simple or complex sequence, it must have a length of SEQ[n].CNT
> 0.
6.12.3 Limitations
Previous compare value is repeated if the PWM period is shorter than the time it takes for the EasyDMA
to retrieve from RAM and update the internal compare registers. This is to ensure a glitch-free operation
even for very short PWM periods.
6.12.4 Pin configuration
The OUT[n] (n=0..3) signals associated with each PWM channel are mapped to physical pins according to
the configuration of PSEL.OUT[n] registers. If PSEL.OUT[n].CONNECT is set to Disconnected, the associated
PWM module signal will not be connected to any physical pins.
The PSEL.OUT[n] registers and their configurations are used as long as the PWM module is enabled and
the PWM generation active (wave counter started). They are retained only as long as the device is in
System ON mode (see section POWER for more information about power modes).
To ensure correct behavior in the PWM module, the pins that are used must be configured in the GPIO
peripheral in the following way before the PWM module is enabled:
PWM signal
PWM pin
Direction
Output value
Comment
OUT[n]
As specified in PSEL.OUT[n]
Output
0
Idle state defined in GPIO OUT
(n=0..3)
register
Table 52: Recommended GPIO configuration before starting PWM generation
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The idle state of a pin is defined by the OUT register in the GPIO module, to ensure that the pins used by
the PWM module are driven correctly. If PWM generation is stopped by triggering a STOP task, the PWM
module itself is temporarily disabled or the device temporarily enters System OFF. This configuration must
be retained in the GPIO for the selected pins (I/Os) for as long as the PWM module is supposed to be
connected to an external PWM circuit.
Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in
unpredictable behavior.
6.12.5 Registers
Base address
Peripheral
Instance
Description
0x4001C000
PWM
PWM0
Pulse-width modulation unit 0
Configuration
Table 53: Instances
Register
Offset
Description
TASKS_STOP
0x004
Stops PWM pulse generation on all channels at the end of current PWM period, and stops
TASKS_SEQSTART[0]
0x008
sequence playback
Loads the first PWM value on all enabled channels from sequence 0, and starts playing
that sequence at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM
generation to start if not running.
TASKS_SEQSTART[1]
0x00C
Loads the first PWM value on all enabled channels from sequence 1, and starts playing
that sequence at the rate defined in SEQ[1]REFRESH and/or DECODER.MODE. Causes PWM
generation to start if not running.
TASKS_NEXTSTEP
0x010
Steps by one value in the current sequence on all enabled channels if
EVENTS_STOPPED
0x104
Response to STOP task, emitted when PWM pulses are no longer generated
EVENTS_SEQSTARTED[0]
0x108
First PWM period started on sequence 0
EVENTS_SEQSTARTED[1]
0x10C
First PWM period started on sequence 1
EVENTS_SEQEND[0]
0x110
Emitted at end of every sequence 0, when last value from RAM has been applied to wave
EVENTS_SEQEND[1]
0x114
DECODER.MODE=NextStep. Does not cause PWM generation to start if not running.
counter
Emitted at end of every sequence 1, when last value from RAM has been applied to wave
counter
EVENTS_PWMPERIODEND
0x118
Emitted at the end of each PWM period
EVENTS_LOOPSDONE
0x11C
Concatenated sequences have been played the amount of times defined in LOOP.CNT
SHORTS
0x200
Shortcuts between local events and tasks
INTEN
0x300
Enable or disable interrupt
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
ENABLE
0x500
PWM module enable register
MODE
0x504
Selects operating mode of the wave counter
COUNTERTOP
0x508
Value up to which the pulse generator counter counts
PRESCALER
0x50C
Configuration for PWM_CLK
DECODER
0x510
Configuration of the decoder
LOOP
0x514
Number of playbacks of a loop
SEQ[0].PTR
0x520
Beginning address in RAM of this sequence
SEQ[0].CNT
0x524
Number of values (duty cycles) in this sequence
SEQ[0].REFRESH
0x528
Number of additional PWM periods between samples loaded into compare register
SEQ[0].ENDDELAY
0x52C
Time added after the sequence
SEQ[1].PTR
0x540
Beginning address in RAM of this sequence
SEQ[1].CNT
0x544
Number of values (duty cycles) in this sequence
SEQ[1].REFRESH
0x548
Number of additional PWM periods between samples loaded into compare register
SEQ[1].ENDDELAY
0x54C
Time added after the sequence
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Register
Offset
Description
PSEL.OUT[0]
0x560
Output pin select for PWM channel 0
PSEL.OUT[1]
0x564
Output pin select for PWM channel 1
PSEL.OUT[2]
0x568
Output pin select for PWM channel 2
PSEL.OUT[3]
0x56C
Output pin select for PWM channel 3
Table 54: Register overview
6.12.5.1 TASKS_STOP
Address offset: 0x004
Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence
playback
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
TASKS_STOP
Stops PWM pulse generation on all channels at the end of
current PWM period, and stops sequence playback
Trigger
1
Trigger task
6.12.5.2 TASKS_SEQSTART[n] (n=0..1)
Address offset: 0x008 + (n × 0x4)
Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence
at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not
running.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
TASKS_SEQSTART
Loads the first PWM value on all enabled channels from
sequence n, and starts playing that sequence at the rate
defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes
PWM generation to start if not running.
Trigger
1
Trigger task
6.12.5.3 TASKS_NEXTSTEP
Address offset: 0x010
Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does
not cause PWM generation to start if not running.
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
TASKS_NEXTSTEP
Steps by one value in the current sequence on all enabled
channels if DECODER.MODE=NextStep. Does not cause
PWM generation to start if not running.
Trigger
1
Trigger task
6.12.5.4 EVENTS_STOPPED
Address offset: 0x104
Response to STOP task, emitted when PWM pulses are no longer generated
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_STOPPED
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Response to STOP task, emitted when PWM pulses are no
longer generated
NotGenerated
0
Event not generated
Generated
1
Event generated
6.12.5.5 EVENTS_SEQSTARTED[n] (n=0..1)
Address offset: 0x108 + (n × 0x4)
First PWM period started on sequence n
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_SEQSTARTED
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
NotGenerated
0
Event not generated
Generated
1
Event generated
First PWM period started on sequence n
6.12.5.6 EVENTS_SEQEND[n] (n=0..1)
Address offset: 0x110 + (n × 0x4)
Emitted at end of every sequence n, when last value from RAM has been applied to wave counter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_SEQEND
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Emitted at end of every sequence n, when last value from
RAM has been applied to wave counter
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NotGenerated
0
Event not generated
Generated
1
Event generated
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Peripherals
6.12.5.7 EVENTS_PWMPERIODEND
Address offset: 0x118
Emitted at the end of each PWM period
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID
Access
Field
A
RW EVENTS_PWMPERIODEND
Value ID
Value
Description
Emitted at the end of each PWM period
NotGenerated
0
Event not generated
Generated
1
Event generated
6.12.5.8 EVENTS_LOOPSDONE
Address offset: 0x11C
Concatenated sequences have been played the amount of times defined in LOOP.CNT
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_LOOPSDONE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Concatenated sequences have been played the amount of
times defined in LOOP.CNT
NotGenerated
0
Event not generated
Generated
1
Event generated
6.12.5.9 SHORTS
Address offset: 0x200
Shortcuts between local events and tasks
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
E D C B A
Reset 0x00000000
ID
Access
Field
A
RW SEQEND0_STOP
B
C
D
E
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
Shortcut between event SEQEND[0] and task STOP
RW SEQEND1_STOP
Shortcut between event SEQEND[1] and task STOP
RW LOOPSDONE_SEQSTART0
Shortcut between event LOOPSDONE and task SEQSTART[0]
RW LOOPSDONE_SEQSTART1
Shortcut between event LOOPSDONE and task SEQSTART[1]
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW LOOPSDONE_STOP
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Shortcut between event LOOPSDONE and task STOP
160
Peripherals
6.12.5.10 INTEN
Address offset: 0x300
Enable or disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
H G F E D C B
Reset 0x00000000
ID
Access
Field
B
RW STOPPED
C-D
E-F
G
H
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Disabled
0
Disable
Enabled
1
Enable
Disabled
0
Disable
Enabled
1
Enable
Disabled
0
Disable
Enabled
1
Enable
Enable or disable interrupt for event STOPPED
RW SEQSTARTED[i] (i=0..1)
Enable or disable interrupt for event SEQSTARTED[i]
RW SEQEND[i] (i=0..1)
Enable or disable interrupt for event SEQEND[i]
RW PWMPERIODEND
Enable or disable interrupt for event PWMPERIODEND
Disabled
0
Disable
Enabled
1
Enable
Disabled
0
Disable
Enabled
1
Enable
RW LOOPSDONE
Enable or disable interrupt for event LOOPSDONE
6.12.5.11 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
H G F E D C B
Reset 0x00000000
ID
Access
Field
B
RW STOPPED
C-D
E-F
G
H
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Set
1
Enable
Disabled
0
Read: Disabled
Write '1' to enable interrupt for event STOPPED
RW SEQSTARTED[i] (i=0..1)
Write '1' to enable interrupt for event SEQSTARTED[i]
RW SEQEND[i] (i=0..1)
Write '1' to enable interrupt for event SEQEND[i]
RW PWMPERIODEND
Write '1' to enable interrupt for event PWMPERIODEND
RW LOOPSDONE
4454_140 v1.0
Write '1' to enable interrupt for event LOOPSDONE
161
Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
H G F E D C B
Reset 0x00000000
ID
Access
Field
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Enabled
1
Read: Enabled
6.12.5.12 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
H G F E D C B
Reset 0x00000000
ID
Access
Field
B
RW STOPPED
C-D
E-F
G
H
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Write '1' to disable interrupt for event STOPPED
RW SEQSTARTED[i] (i=0..1)
Write '1' to disable interrupt for event SEQSTARTED[i]
RW SEQEND[i] (i=0..1)
Write '1' to disable interrupt for event SEQEND[i]
RW PWMPERIODEND
Write '1' to disable interrupt for event PWMPERIODEND
RW LOOPSDONE
Write '1' to disable interrupt for event LOOPSDONE
6.12.5.13 ENABLE
Address offset: 0x500
PWM module enable register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW ENABLE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Disabled
0
Disabled
Enabled
1
Enable
Enable or disable PWM module
6.12.5.14 MODE
Address offset: 0x504
Selects operating mode of the wave counter
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW UPDOWN
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Up
0
Up counter, edge-aligned PWM duty cycle
UpAndDown
1
Up and down counter, center-aligned PWM duty cycle
Selects up mode or up-and-down mode for the counter
6.12.5.15 COUNTERTOP
Address offset: 0x508
Value up to which the pulse generator counter counts
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A
Reset 0x000003FF
ID
Access
Field
A
RW COUNTERTOP
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
Value ID
Value
Description
[3..32767]
Value up to which the pulse generator counter counts. This
register is ignored when DECODER.MODE=WaveForm and
only values from RAM are used.
6.12.5.16 PRESCALER
Address offset: 0x50C
Configuration for PWM_CLK
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A
Reset 0x00000000
ID
Access
Field
A
RW PRESCALER
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
DIV_1
0
Divide by 1 (16 MHz)
DIV_2
1
Divide by 2 (8 MHz)
DIV_4
2
Divide by 4 (4 MHz)
DIV_8
3
Divide by 8 (2 MHz)
DIV_16
4
Divide by 16 (1 MHz)
DIV_32
5
Divide by 32 (500 kHz)
DIV_64
6
Divide by 64 (250 kHz)
DIV_128
7
Divide by 128 (125 kHz)
Prescaler of PWM_CLK
6.12.5.17 DECODER
Address offset: 0x510
Configuration of the decoder
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
B
Reset 0x00000000
ID
Access
Field
A
RW LOAD
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
How a sequence is read from RAM and spread to the
compare register
Common
0
1st half word (16-bit) used in all PWM channels 0..3
Grouped
1
1st half word (16-bit) used in channel 0..1; 2nd word in
Individual
2
1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3
WaveForm
3
1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in
channel 2..3
COUNTERTOP
B
RW MODE
Selects source for advancing the active sequence
RefreshCount
0
NextStep
1
SEQ[n].REFRESH is used to determine loading internal
compare registers
NEXTSTEP task causes a new value to be loaded to internal
compare registers
6.12.5.18 LOOP
Address offset: 0x514
Number of playbacks of a loop
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
RW CNT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Disabled
0
Description
Number of playbacks of pattern cycles
Looping disabled (stop at the end of the sequence)
6.12.5.19 SEQ[n].PTR (n=0..1)
Address offset: 0x520 + (n × 0x20)
Beginning address in RAM of this sequence
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
RW PTR
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Beginning address in RAM of this sequence
Note: See the memory chapter for details about
which memories are available for EasyDMA.
6.12.5.20 SEQ[n].CNT (n=0..1)
Address offset: 0x524 + (n × 0x20)
Number of values (duty cycles) in this sequence
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
RW CNT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Disabled
0
Description
Number of values (duty cycles) in this sequence
Sequence is disabled, and shall not be started as it is empty
6.12.5.21 SEQ[n].REFRESH (n=0..1)
Address offset: 0x528 + (n × 0x20)
Number of additional PWM periods between samples loaded into compare register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000001
ID
Access
Field
A
RW CNT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Value ID
Value
Description
Number of additional PWM periods between samples
loaded into compare register (load every REFRESH.CNT+1
PWM periods)
Continuous
0
Update every PWM period
6.12.5.22 SEQ[n].ENDDELAY (n=0..1)
Address offset: 0x52C + (n × 0x20)
Time added after the sequence
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
RW CNT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Time added after the sequence in PWM periods
6.12.5.23 PSEL.OUT[n] (n=0..3)
Address offset: 0x560 + (n × 0x4)
Output pin select for PWM channel n
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
C
Reset 0xFFFFFFFF
ID
Access
Field
A
RW PIN
C
RW CONNECT
A A A A A
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value ID
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
6.13 QDEC — Quadrature decoder
The Quadrature decoder (QDEC) provides buffered decoding of quadrature-encoded sensor signals. It is
suitable for mechanical and optical sensors.
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The sample period and accumulation are configurable to match application requirements. The QDEC
provides the following:
•
•
•
•
Decoding of digital waveform from off-chip quadrature encoder.
Sample accumulation eliminating hard real-time requirements to be enforced on application.
Optional input de-bounce filters.
Optional LED output signal for optical encoders.
ACCREAD
ACCDBLREAD
ACC
ACCDBL
+
+
SAMPLE
Quadrature decoder
IO router
On-chip
Off-chip
Phase A
Phase B
LED
Mechanical to electrical
Mechanical
device
Quadrature Encoder
Figure 56: Quadrature decoder configuration
6.13.1 Sampling and decoding
The QDEC decodes the output from an incremental motion encoder by sampling the QDEC phase input
pins (A and B).
The off-chip quadrature encoder is an incremental motion encoder outputting two waveforms, phase
A and phase B. The two output waveforms are always 90 degrees out of phase, meaning that one
always changes level before the other. The direction of movement is indicated by which of these two
waveforms that changes level first. Invalid transitions may occur, that is when the two waveforms switch
simultaneously. This may occur if the wheel rotates too fast relative to the sample rate set for the decoder.
The QDEC decodes the output from the off-chip encoder by sampling the QDEC phase input pins (A and B)
at a fixed rate as specified in the SAMPLEPER register.
If the SAMPLEPER value needs to be changed, the QDEC shall be stopped using the STOP task. SAMPLEPER
can be then changed upon receiving the STOPPED event, and QDEC can be restarted using the START task.
Failing to do so may result in unpredictable behaviour.
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It is good practice to change other registers (LEDPOL, REPORTPER, DBFEN and LEDPRE) only when the
QDEC is stopped.
When started, the decoder continuously samples the two input waveforms and decodes these by
comparing the current sample pair (n) with the previous sample pair (n-1).
The decoding of the sample pairs is described in the table below.
Previous
Current
SAMPLE
sample pair(n samples
register
- 1)
ACC operation ACCDBL
Description
operation
pair(n)
A
B
A
B
0
0
0
0
0
No change
No change
No movement
0
0
0
1
1
Increment
No change
Movement in positive direction
0
0
1
0
-1
Decrement
No change
Movement in negative direction
0
0
1
1
2
No change
Increment
Error: Double transition
0
1
0
0
-1
Decrement
No change
Movement in negative direction
0
1
0
1
0
No change
No change
No movement
0
1
1
0
2
No change
Increment
Error: Double transition
0
1
1
1
1
Increment
No change
Movement in positive direction
1
0
0
0
1
Increment
No change
Movement in positive direction
1
0
0
1
2
No change
Increment
Error: Double transition
1
0
1
0
0
No change
No change
No movement
1
0
1
1
-1
Decrement
No change
Movement in negative direction
1
1
0
0
2
No change
Increment
Error: Double transition
1
1
0
1
-1
Decrement
No change
Movement in negative direction
1
1
1
0
1
Increment
No change
Movement in positive direction
1
1
1
1
0
No change
No change
No movement
Table 55: Sampled value encoding
6.13.2 LED output
The LED output follows the sample period, and the LED is switched on a given period before sampling and
switched off immediately after the inputs are sampled. The period the LED is switched on before sampling
is given in the LEDPRE register.
The LED output pin polarity is specified in the LEDPOL register.
For using off-chip mechanical encoders not requiring a LED, the LED output can be disabled by writing
value 'Disconnected' to the CONNECT field of the PSEL.LED register. In this case the QDEC will not acquire
access to a LED output pin and the pin can be used for other purposes by the CPU.
6.13.3 Debounce filters
Each of the two-phase inputs have digital debounce filters.
When enabled through the DBFEN register, the filter inputs are sampled at a fixed 1 MHz frequency during
the entire sample period (which is specified in the SAMPLEPER register), and the filters require all of the
samples within this sample period to equal before the input signal is accepted and transferred to the
output of the filter.
As a result, only input signal with a steady state longer than twice the period specified in SAMPLEPER are
guaranteed to pass through the filter, and any signal with a steady state shorter than SAMPLEPER will
always be suppressed by the filter. (This is assumed that the frequency during the debounce period never
exceeds 500 kHz (as required by the Nyquist theorem when using a 1 MHz sample frequency).
The LED will always be ON when the debounce filters are enabled, as the inputs in this case will be
sampled continuously.
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Note that when when the debounce filters are enabled, displacements reported by the QDEC peripheral
are delayed by one SAMPLEPER period.
6.13.4 Accumulators
The quadrature decoder contains two accumulator registers, ACC and ACCDBL, that accumulate
respectively valid motion sample values and the number of detected invalid samples (double transitions).
The ACC register will accumulate all valid values (1/-1) written to the SAMPLE register. This can be useful
for preventing hard real-time requirements from being enforced on the application. When using the
ACC register the application does not need to read every single sample from the SAMPLE register, but
can instead fetch the ACC register whenever it fits the application. The ACC register will always hold the
relative movement of the external mechanical device since the previous clearing of the ACC register.
Sample values indicating a double transition (2) will not be accumulated in the ACC register.
An ACCOF event will be generated if the ACC receives a SAMPLE value that would cause the register
to overflow or underflow. Any SAMPLE value that would cause an ACC overflow or underflow will be
discarded, but any samples not causing the ACC to overflow or underflow will still be accepted.
The accumulator ACCDBL accumulates the number of detected double transitions since the previous
clearing of the ACCDBL register.
The ACC and ACCDBL registers can be cleared by the READCLRACC and subsequently read using the
ACCREAD and ACCDBLREAD registers.
The ACC register can be separately cleared by the RDCLRACC and subsequently read using the ACCREAD
registers.
The ACCDBL register can be separately cleared by the RDCLRDBL and subsequently read using the
ACCDBLREAD registers.
The REPORTPER register allows automating the capture of several samples before it can send out a
REPORTRDY event in case a non-null displacement has been captured and accumulated, and a DBLRDY
event in case one or more double-displacements have been captured and accumulated. The REPORTPER
field in this register selects after how many samples the accumulators contents are evaluated to send (or
not) REPORTRDY and DBLRDY events.
Using the RDCLRACC task (manually sent upon receiving the event, or using the DBLRDY_RDCLRACC
shortcut), ACCREAD can then be read.
In case at least one double transition has been captured and accumulated, a DBLRDY event is sent. Using
the RDCLRDBL task (manually sent upon receiving the event, or using the DBLRDY_RDCLRDBL shortcut),
ACCDBLREAD can then be read.
6.13.5 Output/input pins
The QDEC uses a three-pin interface to the off-chip quadrature encoder.
These pins will be acquired when the QDEC is enabled in the ENABLE register. The pins acquired by the
QDEC cannot be written by the CPU, but they can still be read by the CPU.
The pin numbers to be used for the QDEC are selected using the PSEL.n registers.
6.13.6 Pin configuration
The Phase A, Phase B, and LED signals are mapped to physical pins according to the configuration specified
in the PSEL.A, PSEL.B, and PSEL.LED registers respectively.
If the CONNECT field value 'Disconnected' is specified in any of these registers, the associated signal will
not be connected to any physical pin. The PSEL.A, PSEL.B, and PSEL.LED registers and their configurations
are only used as long as the QDEC is enabled, and retained only as long as the device is in ON mode.
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When the peripheral is disabled, the pins will behave as regular GPIOs, and use the configuration in their
respective OUT bit field and PIN_CNF[n] register.
To secure correct behavior in the QDEC, the pins used by the QDEC must be configured in the GPIO
peripheral as described in GPIO configuration before enabling peripheral on page 169 before enabling
the QDEC. This configuration must be retained in the GPIO for the selected IOs as long as the QDEC is
enabled.
Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in
unpredictable behavior.
QDEC signal
QDEC pin
Direction
Output value
Phase A
As specified in PSEL.A
Input
Not applicable
Phase B
As specified in PSEL.B
Input
Not applicable
LED
As specified in PSEL.LED
Input
Not applicable
Comment
Table 56: GPIO configuration before enabling peripheral
6.13.7 Registers
Base address
Peripheral
Instance
Description
Configuration
0x40012000
QDEC
QDEC
Quadrature decoder
Table 57: Instances
Register
Offset
Description
TASKS_START
0x000
Task starting the quadrature decoder
TASKS_STOP
0x004
Task stopping the quadrature decoder
TASKS_READCLRACC
0x008
Read and clear ACC and ACCDBL
TASKS_RDCLRACC
0x00C
Read and clear ACC
TASKS_RDCLRDBL
0x010
Read and clear ACCDBL
EVENTS_SAMPLERDY
0x100
Event being generated for every new sample value written to the SAMPLE register
EVENTS_REPORTRDY
0x104
Non-null report ready
EVENTS_ACCOF
0x108
ACC or ACCDBL register overflow
EVENTS_DBLRDY
0x10C
Double displacement(s) detected
EVENTS_STOPPED
0x110
QDEC has been stopped
SHORTS
0x200
Shortcuts between local events and tasks
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
ENABLE
0x500
Enable the quadrature decoder
LEDPOL
0x504
LED output pin polarity
SAMPLEPER
0x508
Sample period
SAMPLE
0x50C
Motion sample value
REPORTPER
0x510
Number of samples to be taken before REPORTRDY and DBLRDY events can be generated
ACC
0x514
Register accumulating the valid transitions
ACCREAD
0x518
Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task
PSEL.LED
0x51C
Pin select for LED signal
PSEL.A
0x520
Pin select for A signal
PSEL.B
0x524
Pin select for B signal
DBFEN
0x528
Enable input debounce filters
LEDPRE
0x540
Time period the LED is switched ON prior to sampling
ACCDBL
0x544
Register accumulating the number of detected double transitions
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Register
Offset
Description
ACCDBLREAD
0x548
Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task
Table 58: Register overview
6.13.7.1 TASKS_START
Address offset: 0x000
Task starting the quadrature decoder
When started, the SAMPLE register will be continuously updated at the rate given in the SAMPLEPER
register.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
TASKS_START
Task starting the quadrature decoder
When started, the SAMPLE register will be continuously
updated at the rate given in the SAMPLEPER register.
Trigger
1
Trigger task
6.13.7.2 TASKS_STOP
Address offset: 0x004
Task stopping the quadrature decoder
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Trigger
1
Description
TASKS_STOP
Task stopping the quadrature decoder
Trigger task
6.13.7.3 TASKS_READCLRACC
Address offset: 0x008
Read and clear ACC and ACCDBL
Task transferring the content of ACC to ACCREAD and the content of ACCDBL to ACCDBLREAD, and then
clearing the ACC and ACCDBL registers. These read-and-clear operations will be done atomically.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
TASKS_READCLRACC
Read and clear ACC and ACCDBL
Task transferring the content of ACC to ACCREAD and the
content of ACCDBL to ACCDBLREAD, and then clearing the
ACC and ACCDBL registers. These read-and-clear operations
will be done atomically.
Trigger
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6.13.7.4 TASKS_RDCLRACC
Address offset: 0x00C
Read and clear ACC
Task transferring the content of ACC to ACCREAD, and then clearing the ACC register. This read-and-clear
operation will be done atomically.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
TASKS_RDCLRACC
Read and clear ACC
Task transferring the content of ACC to ACCREAD, and then
clearing the ACC register. This read-and-clear operation will
be done atomically.
Trigger
1
Trigger task
6.13.7.5 TASKS_RDCLRDBL
Address offset: 0x010
Read and clear ACCDBL
Task transferring the content of ACCDBL to ACCDBLREAD, and then clearing the ACCDBL register. This readand-clear operation will be done atomically.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
TASKS_RDCLRDBL
Read and clear ACCDBL
Task transferring the content of ACCDBL to ACCDBLREAD,
and then clearing the ACCDBL register. This read-and-clear
operation will be done atomically.
Trigger
1
Trigger task
6.13.7.6 EVENTS_SAMPLERDY
Address offset: 0x100
Event being generated for every new sample value written to the SAMPLE register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_SAMPLERDY
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Event being generated for every new sample value written
to the SAMPLE register
NotGenerated
0
Event not generated
Generated
1
Event generated
6.13.7.7 EVENTS_REPORTRDY
Address offset: 0x104
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Non-null report ready
Event generated when REPORTPER number of samples has been accumulated in the ACC register and the
content of the ACC register is not equal to 0. (Thus, this event is only generated if a motion is detected
since the previous clearing of the ACC register).
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_REPORTRDY
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Non-null report ready
Event generated when REPORTPER number of samples has
been accumulated in the ACC register and the content of
the ACC register is not equal to 0. (Thus, this event is only
generated if a motion is detected since the previous clearing
of the ACC register).
NotGenerated
0
Event not generated
Generated
1
Event generated
6.13.7.8 EVENTS_ACCOF
Address offset: 0x108
ACC or ACCDBL register overflow
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_ACCOF
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
NotGenerated
0
Event not generated
Generated
1
Event generated
ACC or ACCDBL register overflow
6.13.7.9 EVENTS_DBLRDY
Address offset: 0x10C
Double displacement(s) detected
Event generated when REPORTPER number of samples has been accumulated and the content of the
ACCDBL register is not equal to 0. (Thus, this event is only generated if a double transition is detected
since the previous clearing of the ACCDBL register).
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_DBLRDY
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Double displacement(s) detected
Event generated when REPORTPER number of samples has
been accumulated and the content of the ACCDBL register
is not equal to 0. (Thus, this event is only generated if a
double transition is detected since the previous clearing of
the ACCDBL register).
NotGenerated
0
Event not generated
Generated
1
Event generated
6.13.7.10 EVENTS_STOPPED
Address offset: 0x110
QDEC has been stopped
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_STOPPED
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
QDEC has been stopped
NotGenerated
0
Event not generated
Generated
1
Event generated
6.13.7.11 SHORTS
Address offset: 0x200
Shortcuts between local events and tasks
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
G F E D C B A
Reset 0x00000000
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID
Access
Field
A
RW REPORTRDY_READCLRACC
B
C
D
E
F
Value ID
Value
Description
Shortcut between event REPORTRDY and task READCLRACC
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
RW SAMPLERDY_STOP
Shortcut between event SAMPLERDY and task STOP
RW REPORTRDY_RDCLRACC
Shortcut between event REPORTRDY and task RDCLRACC
RW REPORTRDY_STOP
Shortcut between event REPORTRDY and task STOP
RW DBLRDY_RDCLRDBL
Shortcut between event DBLRDY and task RDCLRDBL
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
Disabled
0
RW DBLRDY_STOP
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Shortcut between event DBLRDY and task STOP
Disable shortcut
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Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
G F E D C B A
Reset 0x00000000
ID
G
Access
Field
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Enabled
1
Enable shortcut
RW SAMPLERDY_READCLRACC
Shortcut between event SAMPLERDY and task READCLRACC
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
6.13.7.12 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
E D C B A
Reset 0x00000000
ID
Access
Field
A
RW SAMPLERDY
B
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Write '1' to enable interrupt for event SAMPLERDY
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW REPORTRDY
Write '1' to enable interrupt for event REPORTRDY
Event generated when REPORTPER number of samples has
been accumulated in the ACC register and the content of
the ACC register is not equal to 0. (Thus, this event is only
generated if a motion is detected since the previous clearing
of the ACC register).
C
D
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ACCOF
Write '1' to enable interrupt for event ACCOF
RW DBLRDY
Write '1' to enable interrupt for event DBLRDY
Event generated when REPORTPER number of samples has
been accumulated and the content of the ACCDBL register
is not equal to 0. (Thus, this event is only generated if a
double transition is detected since the previous clearing of
the ACCDBL register).
E
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW STOPPED
Write '1' to enable interrupt for event STOPPED
6.13.7.13 INTENCLR
Address offset: 0x308
Disable interrupt
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
E D C B A
Reset 0x00000000
ID
Access
Field
A
RW SAMPLERDY
B
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Write '1' to disable interrupt for event SAMPLERDY
RW REPORTRDY
Write '1' to disable interrupt for event REPORTRDY
Event generated when REPORTPER number of samples has
been accumulated in the ACC register and the content of
the ACC register is not equal to 0. (Thus, this event is only
generated if a motion is detected since the previous clearing
of the ACC register).
C
D
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW ACCOF
Write '1' to disable interrupt for event ACCOF
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW DBLRDY
Write '1' to disable interrupt for event DBLRDY
Event generated when REPORTPER number of samples has
been accumulated and the content of the ACCDBL register
is not equal to 0. (Thus, this event is only generated if a
double transition is detected since the previous clearing of
the ACCDBL register).
E
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
RW STOPPED
Write '1' to disable interrupt for event STOPPED
6.13.7.14 ENABLE
Address offset: 0x500
Enable the quadrature decoder
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW ENABLE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Enable or disable the quadrature decoder
When enabled the decoder pins will be active. When
disabled the quadrature decoder pins are not active and can
be used as GPIO .
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0
Disable
Enabled
1
Enable
175
Peripherals
6.13.7.15 LEDPOL
Address offset: 0x504
LED output pin polarity
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW LEDPOL
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
ActiveLow
0
Led active on output pin low
ActiveHigh
1
Led active on output pin high
LED output pin polarity
6.13.7.16 SAMPLEPER
Address offset: 0x508
Sample period
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A
Reset 0x00000000
ID
Access
Field
A
RW SAMPLEPER
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Sample period. The SAMPLE register will be updated for
every new sample
128us
0
128 us
256us
1
256 us
512us
2
512 us
1024us
3
1024 us
2048us
4
2048 us
4096us
5
4096 us
8192us
6
8192 us
16384us
7
16384 us
32ms
8
32768 us
65ms
9
65536 us
131ms
10
131072 us
6.13.7.17 SAMPLE
Address offset: 0x50C
Motion sample value
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
R
SAMPLE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
[-1..2]
Last motion sample
The value is a 2's complement value, and the sign gives the
direction of the motion. The value '2' indicates a double
transition.
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6.13.7.18 REPORTPER
Address offset: 0x510
Number of samples to be taken before REPORTRDY and DBLRDY events can be generated
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A
Reset 0x00000000
ID
Access
Field
A
RW REPORTPER
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Specifies the number of samples to be accumulated in the
ACC register before the REPORTRDY and DBLRDY events can
be generated
The report period in [us] is given as: RPUS = SP * RP Where
RPUS is the report period in [us/report], SP is the sample
period in [us/sample] specified in SAMPLEPER, and RP is the
report period in [samples/report] specified in REPORTPER .
10Smpl
0
10 samples / report
40Smpl
1
40 samples / report
80Smpl
2
80 samples / report
120Smpl
3
120 samples / report
160Smpl
4
160 samples / report
200Smpl
5
200 samples / report
240Smpl
6
240 samples / report
280Smpl
7
280 samples / report
1Smpl
8
1 sample / report
6.13.7.19 ACC
Address offset: 0x514
Register accumulating the valid transitions
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
ACC
Value
Description
[-1024..1023]
Register accumulating all valid samples (not double
transition) read from the SAMPLE register
Double transitions ( SAMPLE = 2 ) will not be accumulated
in this register. The value is a 32 bit 2's complement value.
If a sample that would cause this register to overflow or
underflow is received, the sample will be ignored and
an overflow event ( ACCOF ) will be generated. The ACC
register is cleared by triggering the READCLRACC or the
RDCLRACC task.
6.13.7.20 ACCREAD
Address offset: 0x518
Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID
Access
Field
A
R
Value ID
ACCREAD
Value
Description
[-1024..1023]
Snapshot of the ACC register.
The ACCREAD register is updated when the READCLRACC or
RDCLRACC task is triggered
6.13.7.21 PSEL.LED
Address offset: 0x51C
Pin select for LED signal
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
C
Reset 0xFFFFFFFF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID
Access
Field
A
RW PIN
C
RW CONNECT
Value ID
A A A A A
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
6.13.7.22 PSEL.A
Address offset: 0x520
Pin select for A signal
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
C
Reset 0xFFFFFFFF
ID
Access
Field
A
RW PIN
C
RW CONNECT
A A A A A
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value ID
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
6.13.7.23 PSEL.B
Address offset: 0x524
Pin select for B signal
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
C
Reset 0xFFFFFFFF
ID
Access
Field
A
RW PIN
C
RW CONNECT
4454_140 v1.0
A A A A A
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value ID
Value
Description
[0..31]
Pin number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
178
Peripherals
6.13.7.24 DBFEN
Address offset: 0x528
Enable input debounce filters
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW DBFEN
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Disabled
0
Debounce input filters disabled
Enabled
1
Debounce input filters enabled
Enable input debounce filters
6.13.7.25 LEDPRE
Address offset: 0x540
Time period the LED is switched ON prior to sampling
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A
Reset 0x00000010
ID
Access
Field
A
RW LEDPRE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Value ID
Value
Description
[1..511]
Period in us the LED is switched on prior to sampling
6.13.7.26 ACCDBL
Address offset: 0x544
Register accumulating the number of detected double transitions
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A
Reset 0x00000000
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
ACCDBL
Value
Description
[0..15]
Register accumulating the number of detected double or
illegal transitions. ( SAMPLE = 2 ).
When this register has reached its maximum value the
accumulation of double / illegal transitions will stop. An
overflow event ( ACCOF ) will be generated if any double
or illegal transitions are detected after the maximum
value was reached. This field is cleared by triggering the
READCLRACC or RDCLRDBL task.
6.13.7.27 ACCDBLREAD
Address offset: 0x548
Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A
Reset 0x00000000
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
ACCDBLREAD
Value
Description
[0..15]
Snapshot of the ACCDBL register. This field is updated when
the READCLRACC or RDCLRDBL task is triggered.
6.13.8 Electrical specification
6.13.8.1 QDEC Electrical Specification
Symbol
Description
Min.
tSAMPLE
Time between sampling signals from quadrature decoder
tLED
Time from LED is turned on to signals are sampled
Typ.
Max.
Units
128
131072
µs
0
511
µs
6.14 RADIO — 2.4 GHz radio
The 2.4 GHz radio transceiver is compatible with multiple radio standards such as 1 Mbps, 2 Mbps and
long range Bluetooth® low energy. IEEE 802.15.4 250 kbps mode is fully supported as well as Nordic's
proprietary 1 Mbps and 2 Mbps modes of operation.
Listed here are main features for the RADIO:
• Multidomain 2.4 GHz radio transceiver
• 1 Mbps, 2 Mbps, and long range (125 kbps and 500 kbps mode) Bluetooth® low energy modes
• Angle-of-arrival (AoA) and angle-of-departure (AoD) direction finding using Bluetooth® low energy
• 250 kbps IEEE 802.15.4 mode
• 1 Mbps and 2 Mbps Nordic proprietary modes
• Best in class link budget and low power operation
• Efficient data interface with EasyDMA support
• Automatic address filtering and pattern matching
EasyDMA, in combination with an automated packet assembler, packet disassembler, automated CRC
generator and CRC checker, makes it easy to configure and use the RADIO. See the following figure for
details.
RAM
RADIO
PACKETPTR
Device
address
match
Packet synch
S0
CRC
Packet
disassembler
L
RSSI
Address
match
Dewhitening
2.4 GHz
receiver
S1
Payload
EasyDMA
IFS
control unit
Bit counter
S0
ANT1
L
Packet
assembler
S1
Payload
CRC
MAXLEN
Figure 57: RADIO block diagram
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2.4 GHz
transmitter
Peripherals
The RADIO includes a device address match unit and an interframe spacing control unit that can be utilized
to simplify address whitelisting and interframe spacing respectively in Bluetooth® low energy and similar
applications.
The RADIO also includes a received signal strength indicator (RSSI) and a bit counter. The bit counter
generates events when a preconfigured number of bits are sent or received by the RADIO.
6.14.1 Packet configuration
A RADIO packet contains the following fields: PREAMBLE, ADDRESS, S0, LENGTH, S1, PAYLOAD, and CRC.
PREFIX
CI
TERM1
S0
LENGTH
LSByte
S1
PAYLOAD
LSByte
CRC
LSBit
BASE
MSBit
PREAMBLE
LSBit
LSBit
LSBit
The content of a RADIO packet is illustrated in the figure below. The RADIO sends the fields in the packet
according to the order illustrated in the following figure, starting on the left.
TERM
2
MSByte
ADDRESS
Figure 58: On-air packet layout
Not shown in the figure is the static payload add-on (the length of which is defined in PCNF1.STATLEN, and
which is 0 bytes in a standard BLE packet). The static payload add-on is sent between PAYLOAD and CRC
fields. The RADIO sends the different fields in the packet in the order they are illustrated above, from left
to right. The preamble will be sent with least significant bit first on air.
PREAMBLE is sent with least significant bit first on air. The size of the PREAMBLE depends on the mode
selected in the MODE register:
• The PREAMBLE is one byte for MODE = Ble_1Mbit as well as all Nordic proprietary operating modes
(MODE = Nrf_1Mbit and MODE = Nrf_2Mbit), and PCNF0.PLEN has to be set accordingly. If the first bit
of the ADDRESS is 0, the preamble will be set to 0xAA. Otherwise the PREAMBLE will be set to 0x55.
• For MODE = Ble_2Mbit, the PREAMBLE must be set to 2 byte through PCNF0.PLEN. If the first bit of the
ADDRESS is 0, the preamble will be set to 0xAAAA. Otherwise the PREAMBLE will be set to 0x5555.
• For MODE = Ble_LR125Kbit and MODE = Ble_LR500Kbit, the PREAMBLE is 10 repetitions of 0x3C.
• For MODE = Ieee802154_250Kbit, the PREAMBLE is 4 bytes and set to all zeros.
Radio packets are stored in memory inside instances of a RADIO packet data structure as illustrated below.
The PREAMBLE, ADDRESS, CI, TERM1, TERM2, and CRC fields are omitted in this data structure. Fields S0,
LENGTH, and S1 are optional.
S0
0
LENGTH
S1
PAYLOAD
LSByte
n
Figure 59: In-RAM representation of RADIO packet
The byte ordering on air is always least significant byte first for the ADDRESS and PAYLOAD fields, and
most significant byte first for the CRC field. The ADDRESS fields are always transmitted and received least
significant bit first. The CRC field is always transmitted and received most significant bit first. The bitendian, i.e. the order in which the bits are sent and received, of the S0, LENGTH, S1, and PAYLOAD fields
can be configured via PCNF1.ENDIAN.
The sizes of the S0, LENGTH and S1 fields can be individually configured via S0LEN, LFLEN, and S1LEN in
PCNF0 respectively. If any of these fields are configured to be less than 8 bits, the least significant bits of
the fields are used.
If S0, LENGTH, or S1 are specified with zero length, their fields will be omitted in memory. Otherwise each
field will be represented as a separate byte, regardless of the number of bits in their on-air counterpart.
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Independent of the configuration of PCNF1.MAXLEN, the combined length of S0, LENGTH, S1, and
PAYLOAD cannot exceed 258 bytes.
6.14.2 Address configuration
The on-air radio ADDRESS field is composed of two parts, the base address field and the address prefix
field.
The size of the base address field is configurable via PCNF1.BALEN. The base address is truncated from the
least significant byte if the PCNF1.BALEN is less than 4. See Definition of logical addresses on page 182.
Logical address
Base address
Prefix byte
0
BASE0
PREFIX0.AP0
1
BASE1
PREFIX0.AP1
2
BASE1
PREFIX0.AP2
3
BASE1
PREFIX0.AP3
4
BASE1
PREFIX1.AP4
5
BASE1
PREFIX1.AP5
6
BASE1
PREFIX1.AP6
7
BASE1
PREFIX1.AP7
Table 59: Definition of logical addresses
The on-air addresses are defined in the BASE0/BASE1 and PREFIX0/PREFIX1 registers. It is only when
writing these registers that the user must relate to the actual on-air addresses. For other radio address
registers, such as the TXADDRESS, RXADDRESSES, and RXMATCH registers, logical radio addresses ranging
from 0 to 7 are being used. The relationship between the on-air radio addresses and the logical addresses
is described in Definition of logical addresses on page 182.
6.14.3 Data whitening
The RADIO is able to do packet whitening and de-whitening, enabled in PCNF1.WHITEEN. When enabled,
whitening and de-whitening will be handled by the RADIO automatically as packets are sent and received.
The whitening word is generated using polynomial g(D) = D7+ D4 + 1, which then is XORed with the data
packet that is to be whitened, or de-whitened. See the figure below.
D0
D4
D7
+
Position
0
1
2
3
Data out
+
4
5
6
Data in
Figure 60: Data whitening and de-whitening
Whitening and de-whitening will be performed over the whole packet (except for the preamble and the
address field).
The linear feedback shift register in the figure above is initialized via register DATAWHITEIV on page 228.
6.14.4 CRC
The CRC generator in the RADIO calculates the CRC over the whole packet excluding the preamble. If
desirable, the address field can be excluded from the CRC calculation as well.
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See CRCCNF register for more information.
The CRC polynomial is configurable as illustrated in the following figure, where bit 0 in the CRCPOLY
register corresponds to X0 and bit 1 corresponds to X1 etc. See CRCPOLY on page 227 for more
information.
Xn-1
Xn
X2
X1
X0
Packet
(Clocked in serially)
+
+
+
bn
+
+
b0
Figure 61: CRC generation of an n bit CRC
The figure shows that the CRC is calculated by feeding the packet serially through the CRC generator.
Before the packet is clocked through the CRC generator, the CRC generator's latches b0 through bn will
be initialized with a predefined value specified in the CRCINIT register. After the whole packet has been
clocked through the CRC generator, b0 through bn will hold the resulting CRC. This value will be used by the
RADIO during both transmission and reception. Latches b0 through bn are not available to be read by the
CPU at any time. However, a received CRC can be read by the CPU via the RXCRC register.
The length (n) of the CRC is configurable, see CRCCNF for more information.
Once the entire packet, including the CRC, has been received and no errors were detected, the RADIO
generates a CRCOK event. If CRC errors were detected, a CRCERROR event is generated.
The status of the CRC check can be read from the CRCSTATUS register after a packet has been received.
6.14.5 Radio states
Tasks and events are used to control the operating state of the RADIO.
The RADIO can enter the states described the table below.
State
Description
DISABLED
No operations are going on inside the RADIO and the power consumption is at a minimum
RXRU
The RADIO is ramping up and preparing for reception
RXIDLE
The RADIO is ready for reception to start
RX
Reception has been started and the addresses enabled in the RXADDRESSES register are being monitored
TXRU
The RADIO is ramping up and preparing for transmission
TXIDLE
The RADIO is ready for transmission to start
TX
The RADIO is transmitting a packet
RXDISABLE
The RADIO is disabling the receiver
TXDISABLE
The RADIO is disabling the transmitter
Table 60: RADIO state diagram
A state diagram showing an overview of the RADIO is shown in the following figure.
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DISABLE
Address sent
/ ADDRESS
START
TXDISABLE
TXRU
/ DISABLED
Ramp-up
complete
/ READY
TXIDLE
TX
STOP
Packet sent / END
TXEN
TXEN
Payload sent
[payload length >=0]
/ PAYLOAD
Last bit sent / PHYEND
DISABLED
RXEN
Packet received / END
/ DISABLED
RXDISABLE
RXRU
Ramp-up
complete
/ READY
Address received
[Address match]
/ ADDRESS
START
RXIDLE
RX
STOP
Payload received
[payload length >=0]
/ PAYLOAD
DISABLE
Figure 62: Radio states
This figure shows how the tasks and events relate to the RADIO's operation. The RADIO does not prevent
a task from being triggered from the wrong state. If a task is triggered from the wrong state, for example
if the RXEN task is triggered from the RXDISABLE state, this may lead to incorrect behavior. The PAYLOAD
event is always generated even if the payload is zero.
The END to START shortcut should not be used with Ble_LR125Kbit, Ble_LR500Kbit, and
Ieee802154_250Kbit modes. Rather the PHYEND to START shortcut.
6.14.6 Transmit sequence
Before the RADIO is able to transmit a packet, it must first ramp-up in TX mode. See TXRU in Radio states
on page 184 and Transmit sequence on page 185. A TXRU ramp-up sequence is initiated when the
TXEN task is triggered. After the RADIO has successfully ramped up it will generate the READY event
indicating that a packet transmission can be initiated. A packet transmission is initiated by triggering the
START task. The START task can first be triggered after the RADIO has entered into the TXIDLE state.
The following figure illustrates a single packet transmission where the CPU manually triggers the different
tasks needed to control the flow of the RADIO, i.e. no shortcuts are used. If shortcuts are not used, a
certain amount of delay caused by CPU execution is expected between READY and START, and between
END and DISABLE. As illustrated in Transmit sequence on page 185 the RADIO will by default transmit
'1's between READY and START, and between END and DISABLED. What is transmitted can be programmed
through the DTX field in the MODECNF0 register.
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TX
PAYLOAD
CRC
(carrier)
2
DISABLE
3
TXEN
START
1
TXDISABLE
DISABLED
S0 L S1
ADDRESS
Lifeline
READY
A
END
P
(carrier)
TXIDLE
PHYEND
TXIDLE
Transmitter
TXRU
PAYLOAD
State
Peripherals
Figure 63: Transmit sequence
TX
CRC
(carrier)
DISABLED
PAYLOAD
PAYLOAD
Lifeline
S0 L S1
PHYEND
A
READY
P
TXDISABLE
ADDRESS
Transmitter
TXRU
END
State
The following figure shows a slightly modified version of the transmit sequence where the RADIO is
configured to use shortcuts between READY and START, and between END and DISABLE, which means that
no delay is introduced.
1
TXEN
START
DISABLE
2
Figure 64: Transmit sequence using shortcuts to avoid delays
A
S0 L S1
CRC
(carrier)
6.14.7 Receive sequence
185
DISABLE
3
START
START
2
Figure 65: Transmission of multiple packets
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PAYLOAD
DISABLED
P
PHYEND
(carrier)
END
CRC
ADDRESS
PAYLOAD
END
S0 L S1
TXDISABLE
TX
PHYEND
A
1
TXEN
Lifeline
READY
P
TXIDLE
PAYLOAD
TX
ADDRESS
Transmitter
TXRU
PAYLOAD
State
The RADIO is able to send multiple packets one after the other without having to disable and re-enable
the RADIO between packets, as illustrated in the following figure.
Peripherals
Before the RADIO is able to receive a packet, it must first ramp up in RX mode, see RXRU in Radio states on
page 184 and Receive sequence on page 186.
An RXRU ramp up sequence is initiated when the RXEN task is triggered. After the RADIO has successfully
ramped up it will generate the READY event indicating that a packet reception can be initiated. A packet
reception is initiated by triggering the START task. As illustrated in Radio states on page 184, the START
task can first be triggered after the RADIO has entered into the RXIDLE state.
RX
PAYLOAD
CRC
ADDRESS
S0 L S1
2
DISABLE
3
START
1
RXEN
Lifeline
READY
A
RXDISABLE
DISABLED
P
’X’
RXIDLE
END
RXIDLE
Reception
RXRU
PAYLOAD
State
The following figure shows a single packet reception where the CPU manually triggers the different tasks
needed to control the flow of the RADIO, i.e. no shortcuts are used. If shortcuts are not used, a certain
amount of delay caused by CPU execution is expected between READY and START, and between END and
DISABLE. The RADIO will be listening and possibly receiving undefined data, represented with an 'X', from
START and until a packet with valid preamble (P) is received.
Figure 66: Receive sequence
RX
S0 L S1
PAYLOAD
CRC
DISABLED
A
END
P
RXDISABLE
1
2
DISABLE
START
RXEN
Lifeline
READY
’X’
ADDRESS
Reception
RXRU
PAYLOAD
State
The following figure shows a slightly modified version of the receive sequence, where the RADIO is
configured to use shortcuts between READY and START, and between END and DISABLE, which means that
no delay is introduced.
Figure 67: Receive sequence using shortcuts to avoid delays
The RADIO is able to receive consecutive packets without having to disable and re-enable the RADIO
between packets, as illustrated in the figure below.
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’X’ P
A
S0 L S1
PAYLOAD
CRC
DISABLED
CRC
END
PAYLOAD
RXDISABLE
RX
ADDRESS
S0 L S1
ADDRESS
A
START
3
DISABLE
2
START
1
RXEN
Lifeline
READY
’X’ P
RXIDLE
PAYLOAD
RX
END
Receiver
RXRU
PAYLOAD
State
Peripherals
Figure 68: Reception of multiple packets
6.14.8 Received signal strength indicator (RSSI)
The RADIO implements a mechanism for measuring the power in the received signal. This feature is called
received signal strength indicator (RSSI).
The RSSI is measured continuously and the value filtered using a single-pole IIR filter. After a signal level
change, the RSSI will settle after approximately RSSISETTLE.
Sampling of the received signal strength is started by using the RSSISTART task. The sample can be read
from the RSSISAMPLE register.
The sample period of the RSSI is defined by RSSIPERIOD. The RSSISAMPLE will hold the pre-filtered received
signal strength after this sample period.
For the RSSI sample to be valid, the RADIO has to be enabled in receive mode (RXEN task) and the
reception has to be started (READY event followed by START task).
6.14.9 Interframe spacing (IFS)
Interframe spacing (IFS) is defined as the time, in microseconds, between two consecutive packets,
starting from when the end of the last bit of the previous packet is received, to the beginning of the first
bit of the subsequent packet that is transmitted. The RADIO is able to enforce this interval, as specified in
the TIFS register, as long as the TIFS is not specified to be shorter than the RADIO's turnaround time, i.e.
the time needed to switch off the receiver, and then switch the transmitter back on. The TIFS register can
be written any time before the last bit on air is received.
This timing is illustrated in the figure below.
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Change to MODE OK
TXRU
TX
P
READY
DISABLED
CRC
END
A
S0 L S1
PAYLOAD
START
DISABLE
TIFS
TXEN
PAYLOAD
RXDISABLE
ADDRESS
RX
PAYLOAD
Lifeline
On air
State
Change to SHORTS and
TIFS OK
Figure 69: IFS timing detail
The TIFS duration starts after the last bit on air (just before the END event), and elapses with first bit being
transmitted on air (just after READY event).
TIFS is only enforced if the shortcuts END-to-DISABLE and DISABLED-to-TXEN or END-to-DISABLE and
DISABLED-to-RXEM are enabled. TIFS is qualified for use when MODE is either Ble_1Mbit, Ble_2Mbit,
Ble_LR125Kbit, Ble_LR500Kbit, or Ieee802154_250Kbit, using the default ramp-up mode. SHORTS and TIFS
are not double-buffered, and can be updated at any point in time before the last bit on air is received. The
MODE register is double-buffered and sampled at the TXEN or RXEN task.
6.14.10 Device address match
The device address match feature is tailored for address whitelisting in Bluetooth® low energy and similar
implementations.
This feature enables on-the-fly device address matching while receiving a packet on air. This feature only
works in receive mode and when the RADIO is configured for little endian, see PCNF1.ENDIAN.
The device address match unit assumes that the first 48 bits of the payload are the device address and
that bit number 6 in S0 is the TxAdd bit. See the Bluetooth® Core Specification for more information about
device addresses, TxAdd, and whitelisting.
The RADIO is able to listen for eight different device addresses at the same time. These addresses are
specified in a DAB/DAP register pair, one pair per address, in addition to a TxAdd bit configured in the
DACNF register. The DAB register specifies the 32 least significant bits of the device address, while the DAP
register specifies the 16 most significant bits of the device address.
Each of the device addresses can be individually included or excluded from the matching mechanism. This
is configured in the DACNF register.
6.14.11 Bit counter
The RADIO implements a simple counter that can be configured to generate an event after a specific
number of bits have been transmitted or received.
By using shortcuts, this counter can be started from different events generated by the RADIO and count
relative to these.
The bit counter is started by triggering the BCSTART task, and stopped by triggering the BCSTOP task. A
BCMATCH event will be generated when the bit counter has counted the number of bits specified in the
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BCC register. The bit counter will continue to count bits until the DISABLED event is generated or until the
BCSTOP task is triggered. The CPU can therefore, after a BCMATCH event, reconfigure the BCC value for
new BCMATCH events within the same packet.
The bit counter can only be started after the RADIO has received the ADDRESS event.
The bit counter will stop and reset on either the BCSTOP, STOP, or DISABLE task, or the END event.
RX
DISABLE
3
BCC = 12 + 16
BCSTART
START
CRC
DISABLED
BCMATCH
BCMATCH
READY
2
PAYLOAD
2
BCC = 12
1
RXEN
1
S0 L S1
BCSTOP
Lifeline
Assuming that the
combined length
of S0, length (L)
and S1 is 12 bits.
A
ADDRESS
Reception
0
’X’ P
RXDISABLE
END
RXRU
PAYLOAD
State
The figure below illustrates how the bit counter can be used to generate a BCMATCH event in the
beginning of the packet payload, and again generate a second BCMATCH event after sending 2 bytes (16
bits) of the payload.
Figure 70: Bit counter example
6.14.12 Direction finding
The RADIO implements the Angle-of-Arrival (AoA) and Angle-of-Departure (AoD) Bluetooth Low Energy
feature, which can be used to determine the direction of a peer device. The feature is available for the BLE
1 Mbps and BLE 2 Mbps modes.
When using this feature, the transmitter sends a packet with a continuous tone extension (CTE) appended
to the packet, after the CRC. During the CTE, the receiver can take IQ samples of the incoming signal.
An antenna array is employed at the transmitter (AoD) or at the receiver (AoA). The AoD transmitter, or
AoA receiver, switches between the antennas, in order to collect IQ samples from the different antenna
pairs. The IQ samples can be used to calculate the relative path lengths between the antenna pairs, which
can be used to estimate the direction of the transmitter.
6.14.12.1 CTE format
The CTE is from 16 µs to 160 µs and consists of an unwhitened sequence of 1's, equivalent to a continuous
tone nominally offset from the carrier by +250 kHz for the 1 Mbps PHY and +500 kHz for the 2 Mbps BLE
PHYs. The format of the CTE, when switching and/or sampling, is shown below.
GUARD
PERIOD
REFERENCE PERIOD
SWITCH
SLOT
SAMPLE
SLOT
4 µs
8 µs
1 or 2 µs
1 or 2 µs
SWITCH
SLOT
SAMPLE
SLOT
...
SWITCH
SLOT
SAMPLE
SLOT
16-160 µs
Figure 71: Constant tone extension (CTE) structure
Antenna switching is performed during switch slots and the guard period. The AoA/AoD feature requires
that one IQ sample is taken for each microsecond within the reference period, and once for each sample
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slot. Oversampling is possible by changing the sample spacing as described in IQ sampling on page 193.
The switch slot and sample slot durations are either 1 or 2 µs, but must be equal. The format of the CTE
and switching and sampling procedures may be configured prior to, or during, packet transmission and
reception. Alternatively, during packet reception, these operations can be configured by reading specific
fields of the packet contents.
6.14.12.2 Mode
Depending on the DFEMODE, the device performs the following procedures:
DFEMODE
AOA
TX
Generating and transmitting CTE
AoA/AoD Procedure
AOD
RX
x
TX
RX
x
Receiving, interpreting, and sampling CTE
x
Antenna switching
x
x
x
Table 61: AoA/AoD Procedures performed as a function of DFEMODE and TX/RX mode
6.14.12.3 Inline configuration
When inline configuration is enabled during RX, further configuration of the AoA/AoD procedures
is performed based on the values of the CP bit and the CTEInfo octet within the packet. This
is enabled by setting CTEINLINECONF.CTEINLINECTRLEN. The CTEInfo octet is present only if
the CP bit is set. The position of the CP bit and CTEInfo octet depends on whether the packet
has a Data Channel PDU (CTEINLINECONF.CTEINFOINS1=InS1), or an Advertising Channel PDU
(CTEINLINECONF.CTEINFOINS1=NotInS1).
Data channel PDU
For Data Channel PDUs, PCNF0.S0LEN must be 1 byte, and PCNF0.LFLEN must be 8 bits. To determine if S1
is present, the registers CTEINLINECONF.S0MASK and CTEINLINECONF.S0CONF forms a bitwise mask-andtest for the S0 field. If the bitwise AND between S0 and S0MASK equals S0CONF, then S1 is determined to
be present. When present, the value of PCNF0.S1LEN will be ignored, as this is decided by the CP bit in the
the following figure.
S0
LENGTH
S1
...
CP
...
Length
CTEInfo
5 bits
1
bit
2
bits
8 bits
0 or 8
bits
Figure 72: Data channel PDU header
When encrypting and decrypting BLE packets using the CCM peripheral, it is also required to set
PCNF0.S1INCL=1. The CCM mode must be configured to use an 8-bit length field. The value of the CP bit is
included in the calculation of the MIC, while the S1 field is ignored by the CCM calculation.
Advertising channel PDU
For advertising channel PDUs, the CTEInfo Flag replaces the CP bit. The CTEInfo Flag is within the extended
header flag field in some of the advertising PDUs that employ the common extended advertising payload
format (i.e. AUX_SYNC_IND, AUX_CHAIN_IND). The format of such packets is shown in the following
figure.
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S0
LENGTH
PAYLOAD
PDU Type
...
Length
Extended
Header Length
AdvMode
...
CTEInfo
flag
...
AdvA
TargetA
CTEInfo
...
4 bits
4 bits
8 bits
6 bits
2 bits
2
bits
1 bit
5
bits
6 octets
6 octets
8 bits
...
CRC
CTE
Extended Header Flags
Figure 73: Advertising channel PDU header
The CTEINLINECONF.S0CONF and CTEINLINECONF.S0MASK fields can be configured to accept only certain
advertising PDU Types. If the extended header length is non-zero, the CTEInfo extended header flag is
checked to determine whether CTEInfo is present. If a bit before the CTEInfo flag within the extended
header flags is set, then the CTEInfo position is postponed 6 octets.
CTEInfo parsing
The CTEInfo field is shown in the following figure.
CTETime
RFU
CTEType
5 bits
1 bit
2 bits
Figure 74: CTEInfo field
The CTETIME field defines the length of the CTE in 8 µs units. The valid upper bound of values can
be adjusted using CTEINLINECONF.CTETIMEVALIDRANGE, including allowing use of the RFU bit
within this field. If the CTETIME field is an invalid value of either 0 or 1, the CTE is assumed to be
the minimum valid length of 16 µs. The slot duration is determined by the CTEType field. In RX this
determines whether the sample spacing as defined in CTEINLINECONF.CTEINLINERXMODE1US or
CTEINLINECONF.CTEINLINERXMODE2US is used.
CTEType
Description
TX switch spacing
RX sample spacing during
Sample spacing RX during
reference period
reference period
-
TSAMPLESPACING1
TSAMPLESPACING2
0
AoA, no switching
1
AoD, 1 µs slots
2 µs
TSAMPLESPACING1
CTEINLINERXMODE1US
2
AoD, 2 µs slots
4 µs
TSAMPLESPACING1
CTEINLINERXMODE2US
3
Reserved for future use
Table 62: Switching and sampling spacing based on CTEType
6.14.12.4 Manual configuration
If CTEINLINECONF.CTEINLINECTRLEN is not set, then the packet is not parsed to determine the CTE
parameters, and the antenna switching and sampling is controlled by other registers, see Antenna
switching on page 192. The length of the CTE is given in 8 µs units by DFECTRL1.NUMBEROF8US. The
start of the antenna switching and/or sampling (denoted as an AoA/AoD procedure), can be configured
to start at some trigger with an additional offset. Using DFECTRL1.DFEINEXTENSION, the trigger can be
configured to be the end of the CRC, or alternatively, the ADDRESS event. The additional offset for antenna
switching is configured using DFECTRL2.TSWITCHOFFSET. Similarly, the additional offset for antenna
sampling is configured using DFECTRL2.TSAMPLEOFFSET.
6.14.12.5 Receive- and transmit sequences
The addition of the CTE to the transmitted packet is illustrated in the following figure.
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PAYLOAD
ADDRESS
CTE
(carrier)
2
3
TXEN
START
1
CRC
DISABLE
Lifeline
S0 L S1
TXDISABLE
DISABLED
A
TXIDLE
PHYEND
P
READY
(carrier)
TX
END
TXIDLE
Transmitter
TXRU
PAYLOAD
State
Peripherals
Figure 75: Transmit sequence with DFE
RX
CRC
CTE
2
DISABLE
3
START
RXEN
RXDISABLE
DISABLED
PAYLOAD
PAYLOAD
S0 L S1
ADDRESS
Lifeline
1
A
CTEWARNING
P
READY
’X’
RXIDLE
END
RXIDLE
Reception
RXRU
CTEPRESENT
State
The prescence of CTE within a received packet is signalled by the CTEPRESENT and CTEWARNING events
illustrated in the figure below.
Figure 76: Receive sequence with DFE
6.14.12.6 Antenna switching
The RADIO can control up to 8 GPIO pins in order to control external antenna switches used in direction
finding.
Pin configuration
The eight antenna selection signals are mapped to physical pins according to the pin numbers specified
in the PSEL.DFEGPIO[n] registers. Only pins that have the PSEL.DFEGPIO[n].CONNECTED field set to
Connected will be controlled by the RADIO. Pins that are Disconnected will be controlled by GPIO.
During transmission in AoD TX mode or reception in AoA RX mode, the RADIO automatically acquires the
pins as needed. At times when the RADIO does not use the pin, the pin is released to its default state and
controlled by the GPIO configuration. Thus, the pin must be configured using the GPIO peripheral.
Pin acquired by RADIO
Direction
Yes
Output
No
Specified by GPIO
Value
Comment
Specified in SWITCHPATTERN Pin acquired by RADIO, and in use for DFE.
Specified by GPIO
DFE not in progress. Pin has not been acquired by RADIO, but is available for
DFE use.
Table 63: Pin configuration matrix for a connected and enabled pin [n]
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Switch pattern configuration
The values of the GPIOs while switching during the CTE are configured by writing successively to the
SWITCHPATTERN register. The first write to SWITCHPATTERN is the GPIO pattern applied from the call
of TASKS_TXEN or TASKS_RXEN until the first antenna switch is triggered. The second write sets the
pattern for the reference period and is applied at the start of the guard period. The following writes
set the pattern for the remaining switch slots and are applied at the start of each switch slot. If writing
beyond the total number of antenna slots, the pattern will wrap to SWITCHPATTERN[2] and start over
again. During operation, when the end of the SWITCHPATTERN buffer is reached, the RADIO cycles
back to SWITCHPATTERN[2]. At the end of the AoA/AoD procedure, SWITCHPATTERN[0] is applied to
DFECTRL1.TSWITCHSPACING after the previous antenna switch. The SWITCHPATTERN buffer can be
erased/cleared using CLEARPATTERN.
A minimum number of three patterns must be written to the SWITCHPATTERN register.
If CTEINLINECONF.CTEINLINECTRLEN is not set, then the antenna switch spacing is determined by
DFECTRL1.TSWITCHSPACING (otherwise described by Switching and sampling spacing based on CTEType
on page 191). DFECTRL2.TSWITCHOFFSET determines the position of the first switch compared to the
configurable start of CTE (see DFECTRL1.DFEINEXTENSION).
6.14.12.7 IQ sampling
The RADIO uses DMA to write IQ samples recorded during the CTE to RAM. Alternatively, the magnitude
and phase of the samples can be recorded using the DFECTRL1.SAMPLETYPE field. The samples are
written to the location in RAM specified by DFEPACKET.PTR. The maximum number of samples to
transfer are specified by DFEPACKET.MAXCNT and the number of samples transferred are given in
DFEPACKET.AMOUNT. The IQ samples are recorded with respect to the RX carrier frequency. The format of
the samples is provided in the following table.
SAMPLETYPE
Field
Bits
Description
0: I_Q (default)
Q
31:16
12 bits signed, sign extended to 16 bits
I
15:0
reserved
31:29
Always zero
magnitude
28:16
13 bits unsigned. Equals 1.646756*sqrt(I^2+Q^2)
phase
15:0
9 bits signed, sign extended to 16 bits. Equals 64*atan2(Q, I) in the range [-201,201]
1: MagPhase
Table 64: Format of samples
Oversampling is configured separately for the reference period and for the time after the reference period.
During the reference period, the sample spacing is determined by DFECTRL1.TSAMPLESPACINGREF.
DFECTRL2.TSAMPLEOFFSET determines the position of the first sample relative to the end of the last bit of
the CRC.
For the time after the reference period, if CTEINLINECONF.CTEINLINECTRLEN is disabled, the sample
spacing is set in DFECTRL1.TSAMPLESPACING. However, when CTEINLINECONF.CTEINLINECTRLEN is
enabled, the sample spacing are determined by two different registers, depending on whether the device
is in AoA or AoD RX-mode, as follows.
For AoD RX mode, the sample spacing after the reference period is determined by the CTEType in the
packet, as listed in the table below.
CTEType
Sample spacing
AoD 1 µs slots
CTEINLINECONF.CTEINLINERXMODE1US
AoD 2 µs slots
CTEINLINECONF.CTEINLINERXMODE2US
Other
DFECTRL1.TSAMPLESPACING
Table 65: Sample spacing when CTEINLINECONF.CTEINLINECTRLEN is set and the device is in AoD RX mode
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For AoA RX mode, the sample spacing after the reference period is determined by
DFECTRL1.TSWITCHSPACING, as listed in the table below.
DFECTRL1.TSWITCHSPACING
Sample spacing
2 µs
CTEINLINECONF.CTEINLINERXMODE1US
4 µs
CTEINLINECONF.CTEINLINERXMODE2US
Other
DFECTRL1.TSAMPLESPACING
Table 66: Sample spacing when CTEINLINECONF.CTEINLINECTRLEN is set and the device is in AoA RX mode
For the reference- and switching periods, DFECTRL1.TSAMPLESPACINGREF and
DFECTRL1.TSAMPLESPACING can be used to achieve oversampling.
6.14.13 IEEE 802.15.4 operation
With the MODE=Ieee802154_250kbit the RADIO will comply with the IEEE 802.15.4-2006 standard
implementing its 250 kbps, 2450 MHz, O-QPSK PHY.
The IEEE 802.15.4 standard differs from Nordic's proprietary and Bluetooth® low energy modes. Notable
differences include modulation scheme, channel structure, packet structure, security, and medium access
control.
The main features of the IEEE 802.15.4 mode are:
•
•
•
•
Ultra-low power 250 kbps, 2450 MHz, IEEE 802.15.4-2006 compliant link
Clear channel assessment
Energy detection scan
CRC generation
6.14.13.1 Packet structure
The IEEE 802.15.4 standard defines an on-the-air frame/packet that is different from what is used in BLE
mode.
The following figure provides an overview of the physical frame structure and its timing.
160 µs
Preamble sequence
32 µs
PHY protocol data unit (PPDU)
SFD
Length
5 octets synchronization header (SHR)
1 octet
(PHR)
0
Include
1
Always include S1 field in RAM independent of S1LEN
G
RW CILEN
Length of code indicator - long range
H
RW PLEN
Length of preamble on air. Decision point: TASKS_START task
I
J
8bit
0
8-bit preamble
16bit
1
16-bit preamble
32bitZero
2
32-bit zero preamble - used for IEEE 802.15.4
LongRange
3
Preamble - used for BLE long range
Exclude
0
LENGTH does not contain CRC
Include
1
LENGTH includes CRC
RW CRCINC
Indicates if LENGTH field contains CRC or not
RW TERMLEN
Length of TERM field in Long Range operation
6.14.15.52 PCNF1
Address offset: 0x518
Packet configuration register 1
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Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
E D
Reset 0x00000000
ID
Access
Field
A
RW MAXLEN
C C C B B B B B B B B A A A A A A A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
[0..255]
Maximum length of packet payload. If the packet payload is
larger than MAXLEN, the radio will truncate the payload to
MAXLEN.
B
RW STATLEN
[0..255]
Static length in number of bytes
The static length parameter is added to the total length
of the payload when sending and receiving packets, e.g. if
the static length is set to N the radio will receive or send N
bytes more than what is defined in the LENGTH field of the
packet.
C
RW BALEN
[2..4]
Base address length in number of bytes
The address field is composed of the base address and the
one byte long address prefix, e.g. set BALEN=2 to get a total
address of 3 bytes.
D
RW ENDIAN
On-air endianness of packet, this applies to the S0, LENGTH,
S1, and the PAYLOAD fields.
E
Little
0
Least significant bit on air first
Big
1
Most significant bit on air first
Disabled
0
Disable
Enabled
1
Enable
RW WHITEEN
Enable or disable packet whitening
6.14.15.53 BASE0
Address offset: 0x51C
Base address 0
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
RW BASE0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Base address 0
6.14.15.54 BASE1
Address offset: 0x520
Base address 1
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID
Access
Field
A
RW BASE1
Value ID
Value
Description
Base address 1
6.14.15.55 PREFIX0
Address offset: 0x524
Prefixes bytes for logical addresses 0-3
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Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A
Reset 0x00000000
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID
Access
Field
A-D
RW AP[i] (i=0..3)
Value ID
Value
Description
Address prefix i.
6.14.15.56 PREFIX1
Address offset: 0x528
Prefixes bytes for logical addresses 4-7
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A
Reset 0x00000000
ID
Access
Field
A-D
RW AP[i] (i=4..7)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Address prefix i.
6.14.15.57 TXADDRESS
Address offset: 0x52C
Transmit address select
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A
Reset 0x00000000
ID
Access
Field
A
RW TXADDRESS
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Transmit address select
Logical address to be used when transmitting a packet
6.14.15.58 RXADDRESSES
Address offset: 0x530
Receive address select
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
H G F E D C B A
Reset 0x00000000
ID
Access
Field
A-H
RW ADDR[i] (i=0..7)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Disabled
0
Disable
Enabled
1
Enable
Enable or disable reception on logical address i.
6.14.15.59 CRCCNF
Address offset: 0x534
CRC configuration
4454_140 v1.0
226
Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
B B
Reset 0x00000000
ID
Access
Field
A
RW LEN
A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
[1..3]
CRC length in number of bytes.
Note: For MODE Ble_LR125Kbit and
Ble_LR500Kbit, only LEN set to 3 is supported
B
Disabled
0
CRC length is zero and CRC calculation is disabled
One
1
CRC length is one byte and CRC calculation is enabled
Two
2
CRC length is two bytes and CRC calculation is enabled
Three
3
CRC length is three bytes and CRC calculation is enabled
RW SKIPADDR
Include or exclude packet address field out of CRC
calculation.
Include
0
CRC calculation includes address field
Skip
1
CRC calculation does not include address field. The CRC
Ieee802154
2
calculation will start at the first byte after the address.
CRC calculation as per 802.15.4 standard. Starting at first
byte after length field.
6.14.15.60 CRCPOLY
Address offset: 0x538
CRC polynomial
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
RW CRCPOLY
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
CRC polynomial
Each term in the CRC polynomial is mapped to a bit in this
register which index corresponds to the term's exponent.
The least significant term/bit is hardwired internally to
1, and bit number 0 of the register content is ignored by
the hardware. The following example is for an 8 bit CRC
polynomial: x8 + x7 + x3 + x2 + 1 = 1 1000 1101 .
6.14.15.61 CRCINIT
Address offset: 0x53C
CRC initial value
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
RW CRCINIT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
CRC initial value
Initial value for CRC calculation
6.14.15.62 TIFS
Address offset: 0x544
4454_140 v1.0
227
Peripherals
Interframe spacing in µs
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
RW TIFS
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Interframe spacing in µs
Interframe space is the time interval between two
consecutive packets. It is defined as the time, in
microseconds, from the end of the last bit of the previous
packet to the start of the first bit of the subsequent packet.
6.14.15.63 RSSISAMPLE
Address offset: 0x548
RSSI sample
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A
Reset 0x00000000
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
RSSISAMPLE
Value
Description
[0..127]
RSSI sample
RSSI sample result. The value of this register is read as a
positive value while the actual received signal strength is a
negative value. Actual received signal strength is therefore
as follows: received signal strength = -A dBm
6.14.15.64 STATE
Address offset: 0x550
Current radio state
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A
Reset 0x00000000
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
STATE
Current radio state
Disabled
0
RADIO is in the Disabled state
RxRu
1
RADIO is in the RXRU state
RxIdle
2
RADIO is in the RXIDLE state
Rx
3
RADIO is in the RX state
RxDisable
4
RADIO is in the RXDISABLED state
TxRu
9
RADIO is in the TXRU state
TxIdle
10
RADIO is in the TXIDLE state
Tx
11
RADIO is in the TX state
TxDisable
12
RADIO is in the TXDISABLED state
6.14.15.65 DATAWHITEIV
Address offset: 0x554
Data whitening initial value
4454_140 v1.0
228
Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A
Reset 0x00000040
ID
Access
Field
A
RW DATAWHITEIV
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
Value ID
Value
Description
Data whitening initial value. Bit 6 is hardwired to '1', writing
'0' to it has no effect, and it will always be read back and
used by the device as '1'.
Bit 0 corresponds to Position 6 of the LSFR, Bit 1 to Position
5, etc.
6.14.15.66 BCC
Address offset: 0x560
Bit counter compare
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
RW BCC
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Bit counter compare
Bit counter compare register
6.14.15.67 DAB[n] (n=0..7)
Address offset: 0x600 + (n × 0x4)
Device address base segment n
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
RW DAB
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Device address base segment n
6.14.15.68 DAP[n] (n=0..7)
Address offset: 0x620 + (n × 0x4)
Device address prefix n
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
RW DAP
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Device address prefix n
6.14.15.69 DACNF
Address offset: 0x640
Device address match configuration
4454_140 v1.0
229
Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
P O N M L K J I H G F E D C B A
Reset 0x00000000
ID
Access
Field
A-H
RW ENA[i] (i=0..7)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Enable or disable device address matching using device
address i
I-P
Disabled
0
Disabled
Enabled
1
Enabled
RW TXADD[i] (i=0..7)
TxAdd for device address i
6.14.15.70 MHRMATCHCONF
Address offset: 0x644
Search pattern configuration
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
RW MHRMATCHCONF
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Search pattern configuration
6.14.15.71 MHRMATCHMAS
Address offset: 0x648
Pattern mask
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID
Access
Field
A
RW MHRMATCHMAS
Value ID
Value
Description
Pattern mask
6.14.15.72 MODECNF0
Address offset: 0x650
Radio mode configuration register 0
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
C C
Reset 0x00000200
ID
Access
Field
A
RW RU
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
Value ID
Value
Default
0
Fast
1
Description
Radio ramp-up time
Default ramp-up time (tRXEN and tTXEN), compatible with
firmware written for nRF51
Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical
specification for more information
When enabled, TIFS is not enforced by hardware and
software needs to control when to turn on the Radio.
4454_140 v1.0
A
230
Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
C C
Reset 0x00000200
ID
Access
Field
C
RW DTX
A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Default TX value
Specifies what the RADIO will transmit when it is not
started, i.e. between:
RADIO.EVENTS_READY and RADIO.TASKS_START
RADIO.EVENTS_END and RADIO.TASKS_START
RADIO.EVENTS_END and RADIO.EVENTS_DISABLED
Note: For 802.15.4 and BLE LR mode, only
Center is a valid setting
B1
0
Transmit '1'
B0
1
Transmit '0'
Center
2
Transmit center frequency
When tuning the crystal for center frequency, the RADIO
must be set in DTX = Center mode to be able to achieve the
expected accuracy
6.14.15.73 SFD
Address offset: 0x660
IEEE 802.15.4 start of frame delimiter
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A
Reset 0x000000A7
ID
Access
Field
A
RW SFD
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1
Value ID
Value
Description
IEEE 802.15.4 start of frame delimiter
6.14.15.74 EDCNT
Address offset: 0x664
IEEE 802.15.4 energy detect loop count
Number of iterations to perform an ED scan. If set to 0 one scan is performed, otherwise the specified
number + 1 of ED scans will be performed and the max ED value tracked in EDSAMPLE.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
RW EDCNT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
IEEE 802.15.4 energy detect loop count
6.14.15.75 EDSAMPLE
Address offset: 0x668
IEEE 802.15.4 energy detect level
4454_140 v1.0
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Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
RW EDLVL
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
[0..127]
IEEE 802.15.4 energy detect level
Register value must be converted to IEEE 802.15.4 range by
an 8-bit saturating multiplication by factor ED_RSSISCALE, as
shown in the code example for ED sampling
6.14.15.76 CCACTRL
Address offset: 0x66C
IEEE 802.15.4 clear channel assessment control
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
D D D D D D D D C C C C C C C C B B B B B B B B
Reset 0x052D0000
ID
Access
Field
A
RW CCAMODE
A A A
0 0 0 0 0 1 0 1 0 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
CCA mode of operation
EdMode
0
Energy above threshold
Will report busy whenever energy is detected above
CCAEDTHRES
CarrierMode
1
Carrier seen
Will report busy whenever compliant IEEE 802.15.4 signal is
seen
CarrierAndEdMode
2
Energy above threshold AND carrier seen
CarrierOrEdMode
3
Energy above threshold OR carrier seen
EdModeTest1
4
Energy above threshold test mode that will abort when first
ED measurement over threshold is seen. No averaging.
B
RW CCAEDTHRES
CCA energy busy threshold. Used in all the CCA modes
except CarrierMode.
Must be converted from IEEE 802.15.4 range by dividing by
factor ED_RSSISCALE - similar to EDSAMPLE register
C
RW CCACORRTHRES
D
RW CCACORRCNT
CCA correlator busy threshold. Only relevant to
CarrierMode, CarrierAndEdMode, and CarrierOrEdMode.
Limit for occurances above CCACORRTHRES. When not
equal to zero the corrolator based signal detect is enabled.
6.14.15.77 DFEMODE
Address offset: 0x900
Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD)
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A
Reset 0x00000000
ID
Access
Field
A
RW DFEOPMODE
4454_140 v1.0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Disabled
0
Direction finding mode disabled
AoD
2
Direction finding mode set to AoD
AoA
3
Direction finding mode set to AoA
Direction finding operation mode
232
Peripherals
6.14.15.78 CTEINLINECONF
Address offset: 0x904
Configuration for CTE inline mode
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
I
Reset 0x00002800
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0
ID
Access
Field
A
RW CTEINLINECTRLEN
Value ID
I I I I I I I H H H H H H H H G G G F F F
Value
E E
C B
Description
Enable parsing of CTEInfo from received packet in BLE
modes
B
C
E
Enabled
1
Parsing of CTEInfo is enabled
Disabled
0
Parsing of CTEInfo is disabled
InS1
1
CTEInfo is in S1 byte (data PDU)
NotInS1
0
CTEInfo is NOT in S1 byte (advertising PDU)
Yes
1
Sampling and antenna switching also when CRC is not OK
No
0
No sampling and antenna switching when CRC is not OK
RW CTEINFOINS1
CTEInfo is S1 byte or not
RW CTEERRORHANDLING
Sampling/switching if CRC is not OK
RW CTETIMEVALIDRANGE
Max range of CTETime
Note: Valid range is 2-20 in BLE core spec. If
larger than 20, it can be an indication of an error
in the received packet.
20
0
20 in 8us unit (default)
31
1
31 in 8us unit
63
2
63 in 8us unit
Set to 20 if parsed CTETime is larger han 20
F
RW CTEINLINERXMODE1US
Spacing between samples for the samples in the
SWITCHING period when CTEINLINEMODE is set
When the device is in AoD mode, this is used when the
received CTEType is "AoD 1 us". When in AoA mode, this is
used when TSWITCHSPACING is 2 us.
G
4us
1
4us
2us
2
2us
1us
3
1us
500ns
4
0.5us
250ns
5
0.25us
125ns
6
0.125us
RW CTEINLINERXMODE2US
Spacing between samples for the samples in the
SWITCHING period when CTEINLINEMODE is set
When the device is in AoD mode, this is used when the
received CTEType is "AoD 2 us". When in AoA mode, this is
used when TSWITCHSPACING is 4 us.
4454_140 v1.0
4us
1
4us
2us
2
2us
1us
3
1us
500ns
4
0.5us
250ns
5
0.25us
125ns
6
0.125us
233
A
Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
I
Reset 0x00002800
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0
ID
Access
Field
H
RW S0CONF
Value ID
I I I I I I I H H H H H H H H G G G F F F
Value
E E
C B
A
Description
S0 bit pattern to match
The least significant bit always corresponds to the first bit of
S0 received.
I
RW S0MASK
S0 bit mask to set which bit to match
The least significant bit always corresponds to the first bit of
S0 received.
6.14.15.79 DFECTRL1
Address offset: 0x910
Various configuration for Direction finding
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
I I I I
Reset 0x00023282
ID
Access
Field
A
RW NUMBEROF8US
G G G F E E E
C C C B
A A A A A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 0 0 0 1 0
Value ID
Value
Description
Length of the AoA/AoD procedure in number of 8 us units
Always used in TX mode, but in RX mode only when
CTEINLINECTRLEN is 0
B
RW DFEINEXTENSION
Add CTE extension and do antenna switching/sampling in
this extension
C
CRC
1
AoA/AoD procedure triggered at end of CRC
Payload
0
Antenna switching/sampling is done in the packet payload
RW TSWITCHSPACING
Interval between every time the antenna is changed in the
SWITCHING state
E
F
G
4us
1
4us
2us
2
2us
1us
3
1us
4us
1
4us
2us
2
2us
1us
3
1us
500ns
4
0.5us
250ns
5
0.25us
125ns
6
0.125us
IQ
0
Complex samples in I and Q
MagPhase
1
Complex samples as magnitude and phase
RW TSAMPLESPACINGREF
Interval between samples in the REFERENCE period
RW SAMPLETYPE
Whether to sample I/Q or magnitude/phase
RW TSAMPLESPACING
Interval between samples in the SWITCHING period when
CTEINLINECTRLEN is 0
Note: Not used when CTEINLINECTRLEN is
set. Then either CTEINLINERXMODE1US or
CTEINLINERXMODE2US are used.
4454_140 v1.0
4us
1
4us
2us
2
2us
1us
3
1us
500ns
4
0.5us
234
Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
I I I I
Reset 0x00023282
ID
I
Access
Field
G G G F E E E
C C C B
A A A A A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 0 0 0 1 0
Value ID
Value
Description
250ns
5
0.25us
125ns
6
0.125us
RW AGCBACKOFFGAIN
Gain will be lowered by the specified number of gain steps
at the start of CTE
Note: First LNAGAIN gain drops, then MIXGAIN,
then AAFGAIN
6.14.15.80 DFECTRL2
Address offset: 0x914
Start offset for Direction finding
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
B B B B B B B B B B B B
Reset 0x00000000
ID
Access
Field
A
RW TSWITCHOFFSET
B
RW TSAMPLEOFFSET
A A A A A A A A A A A A A
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Signed value offset after the end of the CRC before starting
switching in number of 16M cycles
Signed value offset before starting sampling in number of
16M cycles relative to the beginning of the REFERENCE state
- 12 us after switching start
6.14.15.81 SWITCHPATTERN
Address offset: 0x928
GPIO patterns to be used for each antenna
Maximum 8 GPIOs can be controlled. To secure correct signal levels on the pins, the pins must be
configured in the GPIO peripheral as described in Pin configuration.
If, during switching, the total number of antenna slots is bigger than the number of written patterns, the
RADIO loops back to the pattern used after the reference pattern.
A minimum number of 3 patterns must be written.
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
RW SWITCHPATTERN
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Fill array of GPIO patterns for antenna control
The GPIO pattern array size is 40 entries.
When written, bit n corresponds to the GPIO configured in
PSEL.DFEGPIO[n].
When read, returns the number of GPIO patterns
written since the last time the array was cleared. Use
CLEARPATTERN to clear the array.
4454_140 v1.0
235
Peripherals
6.14.15.82 CLEARPATTERN
Address offset: 0x92C
Clear the GPIO pattern array for antenna control
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW CLEARPATTERN
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Clear
1
Description
Clears GPIO pattern array for antenna control
Clear the GPIO pattern
6.14.15.83 PSEL.DFEGPIO[n] (n=0..7)
Address offset: 0x930 + (n × 0x4)
Pin select for DFE pin n
Must be set before enabling the radio
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
C
Reset 0xFFFFFFFF
ID
Access
Field
A
B
C
RW CONNECT
B A A A A A
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Value ID
Value
Description
RW PIN
[0..31]
Pin number
RW PORT
[0..1]
Port number
Connection
Disconnected
1
Disconnect
Connected
0
Connect
6.14.15.84 DFEPACKET.PTR
Address offset: 0x950
Data pointer
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID
Access
Field
A
RW PTR
Value ID
Value
Description
Data pointer
Note: See the memory chapter for details about
which memories are available for EasyDMA.
6.14.15.85 DFEPACKET.MAXCNT
Address offset: 0x954
Maximum number of buffer words to transfer
4454_140 v1.0
236
Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A
Reset 0x00001000
ID
Access
Field
A
RW MAXCNT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Maximum number of buffer words to transfer
6.14.15.86 DFEPACKET.AMOUNT
Address offset: 0x958
Number of samples transferred in the last transaction
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
AMOUNT
Number of samples transferred in the last transaction
6.14.15.87 POWER
Address offset: 0xFFC
Peripheral power control
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000001
ID
Access
Field
A
RW POWER
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Value ID
Value
Description
Peripheral power control. The peripheral and its registers
will be reset to its initial state by switching the peripheral
off and then back on again.
Disabled
0
Peripheral is powered off
Enabled
1
Peripheral is powered on
6.14.16 Electrical specification
6.14.16.1 General radio characteristics
Symbol
Description
Min.
fOP
Operating frequencies
2360
Typ.
Max.
Units
2500
MHz
fPLL,CH,SP
PLL channel spacing
1
MHz
fDELTA,1M
Frequency deviation @ 1 Mbps
±170
kHz
fDELTA,BLE,1M
Frequency deviation @ BLE 1 Mbps
±250
kHz
fDELTA,2M
Frequency deviation @ 2 Mbps
±320
kHz
fDELTA,BLE,2M
Frequency deviation @ BLE 2 Mbps
fskBPS
On-the-air data rate
fchip, IEEE 802.15.4
Chip rate in IEEE 802.15.4 mode
±500
125
kHz
2000
2000
kbps
kchip/
s
6.14.16.2 Radio current consumption (transmitter)
Symbol
Description
ITX,PLUS4dBM,DCDC
TX only run current (DC/DC, 3 V) PRF = +4 dBm
4454_140 v1.0
Min.
Typ.
7.0
237
Max.
Units
mA
Peripherals
Symbol
Description
Min.
ITX,PLUS4dBM
TX only run current PRF = +4 dBm
15.4
mA
ITX,0dBM,DCDC
TX only run current (DC/DC, 3 V)PRF = 0 dBm
4.6
mA
ITX,0dBM
TX only run current PRF = 0 dBm
10.1
mA
ITX,MINUS4dBM,DCDC
TX only run current DC/DC, 3 V PRF = -4 dBm
3.6
mA
ITX,MINUS4dBM
TX only run current PRF = -4 dBm
7.8
mA
ITX,MINUS8dBM,DCDC
TX only run current DC/DC, 3 V PRF = -8 dBm
3.2
mA
ITX,MINUS8dBM
TX only run current PRF = -8 dBm
6.8
mA
ITX,MINUS12dBM,DCDC TX only run current DC/DC, 3 V PRF = -12 dBm
2.9
mA
ITX,MINUS12dBM
TX only run current PRF = -12 dBm
Typ.
Max.
Units
6.2
mA
ITX,MINUS16dBM,DCDC TX only run current DC/DC, 3 V PRF = -16 dBm
2.7
mA
ITX,MINUS16dBM
5.7
mA
ITX,MINUS20dBM,DCDC TX only run current DC/DC, 3 V PRF = -20 dBm
2.5
mA
ITX,MINUS20dBM
TX only run current PRF = -16 dBm
5.4
mA
ITX,MINUS40dBM,DCDC TX only run current DC/DC, 3 V PRF = -40 dBm
TX only run current PRF = -20 dBm
2.1
mA
ITX,MINUS40dBM
TX only run current PRF = -40 dBm
4.3
ISTART,TX,DCDC
TX start-up current DC/DC, 3 V, PRF = 4 dBm
..
..
..
mA
ISTART,TX
TX start-up current, PRF = 4 dBm
..
..
..
mA
Min.
Typ.
Max.
Units
mA
6.14.16.3 Radio current consumption (Receiver)
Symbol
Description
IRX,1M,DCDC
RX only run current (DC/DC, 3 V) 1 Mbps/1 Mbps BLE
4.6
mA
IRX,1M
RX only run current (LDO, 3 V) 1 Mbps/1 Mbps BLE
10.0
mA
IRX,2M,DCDC
RX only run current (DC/DC, 3 V) 2 Mbps/2 Mbps BLE
5.2
mA
IRX,2M
RX only run current (LDO, 3 V) 2 Mbps/2 Mbps BLE
11.2
mA
ISTART,RX,1M,DCDC
RX start-up current (DC/DC, 3 V) 1 Mbps/1 Mbps BLE
3.5
mA
ISTART,RX,1M
RX start-up current 1 Mbps/1 Mbps BLE
6.7
mA
6.14.16.4 Transmitter specification
Symbol
Description
Min.
PRF
Maximum output power
4.0
PRFC
RF power control range
24
PRFCR
RF power accuracy
PRF1,1
1st Adjacent Channel Transmit Power 1 MHz (1 Mbps)
-25
dBc
PRF2,1
2nd Adjacent Channel Transmit Power 2 MHz (1 Mbps)
-50
dBc
PRF1,2
1st Adjacent Channel Transmit Power 2 MHz (2 Mbps)
-25
dBc
PRF2,2
2nd Adjacent Channel Transmit Power 4 MHz (2 Mbps)
-50
dBc
Evm
Max.
Error vector magnitude IEEE 802.15.4
12
%rms
-45
dBm
Pharm3rd, IEEE 802.15.4 3rd harmonics in IEEE 802.15.4
Units
dBm
dB
±4
Pharm2nd, IEEE 802.15.4 2nd harmonics in IEEE 802.15.4 mode
4454_140 v1.0
Typ.
dB
dBm
238
Peripherals
6
5.5
Output power [dBm]
5
4.5
4
3.5
3
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.4
3.6
Supply voltage [V]
-40 ºC
25 ºC
85 ºC
Figure 85: Output power, 1 Mbps Bluetooth low energy
mode, at maximum TXPOWER setting (typical values)
2.5
2
Output power [dBm]
1.5
1
0.5
0
-0.5
-1
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
Supply voltage [V]
-40 ºC
25 ºC
85 ºC
Figure 86: Output power, 1 Mbps Bluetooth low energy mode, at 0 dBm TXPOWER setting (typical values)
4454_140 v1.0
239
Peripherals
6.14.16.5 Receiver operation
Symbol
Description
PRX,MAX
Maximum received signal strength at < 0.1% PER
Min.
Typ.
Max.
Units
0
dBm
PSENS,IT,1M
14
Sensitivity, 1 Mbps nRF mode ideal transmitter
-94
dBm
PSENS,IT,2M
Sensitivity, 2 Mbps nRF mode ideal transmitter15
-91
dBm
PSENS,IT,SP,1M,BLE
Sensitivity, 1 Mbps BLE ideal transmitter, packet length ≤ 37
-97
dBm
-96
dBm
-94
dBm
bytes BER=1E-316
PSENS,IT,LP,1M,BLE
Sensitivity, 1 Mbps BLE ideal transmitter, packet length ≥ 128
bytes BER=1E-4 17
PSENS,IT,SP,2M,BLE
Sensitivity, 2 Mbps BLE ideal transmitter, packet length ≤ 37
bytes
PSENS,IT,BLE LE125k
Sensitivity, 125 kbps BLE mode
-104
dBm
PSENS,IT,BLE LE500k
Sensitivity, 500 kbps BLE mode
-100
dBm
PSENS,IEEE 802.15.4
Sensitivity in IEEE 802.15.4 mode
-101
dBm
-95.5
-96
Sensitivity [dBm]
-96.5
-97
-97.5
-98
-98.5
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Supply voltage [V]
-40 ºC
25 ºC
85 ºC
Figure 87: Sensitivity, 1 Mbps Bluetooth low energy mode, Regulator = LDO (typical values)
6.14.16.6 RX selectivity
RX selectivity with equal modulation on interfering signal18
14
15
16
17
18
Typical sensitivity applies when ADDR0 is used for receiver address correlation. When ADDR[1...7]
are used for receiver address correlation, the typical sensitivity for this mode is degraded by 3 dB.
Typical sensitivity applies when ADDR0 is used for receiver address correlation. When ADDR[1..7] are
used for receiver address correlation, the typical sensitivity for this mode is degraded by 3 dB.
As defined in the Bluetooth Core Specification v4.0 Volume 6: Core System Package (Low Energy
Controller Volume)
Equivalent BER limit < 10E-04
Desired signal level at PIN = -67 dBm. One interferer is used, having equal modulation as the desired
signal. The input power of the interferer where the sensitivity equals BER = 0.1% is presented
4454_140 v1.0
240
Peripherals
Symbol
Description
Min.
Typ.
Max.
Units
C/I1M,co-channel
1Mbps mode, Co-Channel interference
9
dB
C/I1M,-1MHz
1 Mbps mode, Adjacent (-1 MHz) interference
-2
dB
C/I1M,+1MHz
1 Mbps mode, Adjacent (+1 MHz) interference
-10
dB
C/I1M,-2MHz
1 Mbps mode, Adjacent (-2 MHz) interference
-19
dB
C/I1M,+2MHz
1 Mbps mode, Adjacent (+2 MHz) interference
-42
dB
C/I1M,-3MHz
1 Mbps mode, Adjacent (-3 MHz) interference
-38
dB
C/I1M,+3MHz
1 Mbps mode, Adjacent (+3 MHz) interference
-48
dB
C/I1M,±6MHz
1 Mbps mode, Adjacent (≥6 MHz) interference
-50
dB
C/I1MBLE,co-channel
1 Mbps BLE mode, Co-Channel interference
6
dB
C/I1MBLE,-1MHz
1 Mbps BLE mode, Adjacent (-1 MHz) interference
-2
dB
C/I1MBLE,+1MHz
1 Mbps BLE mode, Adjacent (+1 MHz) interference
-9
dB
C/I1MBLE,-2MHz
1 Mbps BLE mode, Adjacent (-2 MHz) interference
-22
dB
C/I1MBLE,+2MHz
1 Mbps BLE mode, Adjacent (+2 MHz) interference
-46
dB
C/I1MBLE,>3MHz
1 Mbps BLE mode, Adjacent (≥3 MHz) interference
-50
dB
C/I1MBLE,image
Image frequency interference
-22
dB
C/I1MBLE,image,1MHz
Adjacent (1 MHz) interference to in-band image frequency
-35
dB
C/I2M,co-channel
2 Mbps mode, Co-Channel interference
10
dB
C/I2M,-2MHz
2 Mbps mode, Adjacent (-2 MHz) interference
6
dB
C/I2M,+2MHz
2 Mbps mode, Adjacent (+2 MHz) interference
-14
dB
C/I2M,-4MHz
2 Mbps mode, Adjacent (-4 MHz) interference
-20
dB
C/I2M,+4MHz
2 Mbps mode, Adjacent (+4 MHz) interference
-44
dB
C/I2M,-6MHz
2 Mbps mode, Adjacent (-6 MHz) interference
-42
dB
C/I2M,+6MHz
2 Mbps mode, Adjacent (+6 MHz) interference
-47
dB
C/I2M,≥12MHz
2 Mbps mode, Adjacent (≥12 MHz) interference
-52
dB
C/I2MBLE,co-channel
2 Mbps BLE mode, Co-Channel interference
6
dB
C/I2MBLE,±2MHz
2 Mbps BLE mode, Adjacent (±2 MHz) interference
-2
dB
C/I2MBLE,±4MHz
2 Mbps BLE mode, Adjacent (±4 MHz) interference
-48
dB
C/I2MBLE,≥6MHz
2 Mbps BLE mode, Adjacent (≥6 MHz) interference
-50
dB
C/I2MBLE,image
Image frequency interference
-29
dB
C/I2MBLE,image, 2MHz Adjacent (2 MHz) interference to in-band image frequency
-44
dB
C/I125k BLE LR,co-
125 kbps BLE LR mode, Co-Channel interference
4
dB
C/I125k BLE LR,-1MHz
125 kbps BLE LR mode, Adjacent (-1 MHz) interference
-9
dB
C/I125k BLE LR,+1MHz
125 kbps BLE LR mode, Adjacent (+1 MHz) interference
-16
dB
C/I125k BLE LR,-2MHz
125 kbps BLE LR mode, Adjacent (-2 MHz) interference
-30
dB
C/I125k BLE LR,+2MHz
125 kbps BLE LR mode, Adjacent (+2 MHz) interference
-50
dB
C/I125k BLE LR,>3MHz
125 kbps BLE LR mode, Adjacent (≥3 MHz) interference
-55
dB
C/I125k BLE LR,image
Image frequency interference
-30
dB
C/IIEEE 802.15.4,-5MHz IEEE 802.15.4 mode, Adjacent (-5 MHz) rejection
33
dB
C/IIEEE 802.15.4,+5MHz IEEE 802.15.4 mode, Adjacent (+5 MHz) rejection
38
dB
C/IIEEE 802.15.4,|
48
dB
channel
IEEE 802.15.4 mode, Alternate (10 MHz) rejection
10MHz|
6.14.16.7 RX intermodulation
RX intermodulation19
19
Desired signal level at PIN = -64 dBm. Two interferers with equal input power are used. The interferer
closest in frequency is not modulated, the other interferer is modulated equal with the desired
signal. The input power of the interferers where the sensitivity equals BER = 0.1% is presented.
4454_140 v1.0
241
Peripherals
Symbol
Description
Min.
PIMD,5TH,1M
IMD performance, 1 Mbps, 5th offset channel, packet length
Typ.
Max.
Units
-33
dBm
-30
dBm
-33
dBm
-31
dBm
≤ 37 bytes
PIMD,5TH,1M,BLE
IMD performance, BLE 1 Mbps, 5th offset channel, packet
length ≤ 37 bytes
PIMD,5TH,2M
IMD performance, 2 Mbps, 5th offset channel, packet length
≤ 37 bytes
PIMD,5TH,2M,BLE
IMD performance, BLE 2 Mbps, 5th offset channel, packet
length ≤ 37 bytes
6.14.16.8 Radio timing
Symbol
Description
Min.
Max.
Units
tTXEN,BLE,1M
Time between TXEN task and READY event after channel
140
Typ.
140
µs
40
40
µs
6
6
µs
140
140
µs
40
40
µs
0
0
µs
4
4
µs
0
0
µs
130
130
µs
40
40
µs
21
21
µs
130
130
µs
40
40
µs
0.5
0.5
µs
FREQUENCY configured (1 Mbps BLE and 150 µs TIFS)
tTXEN,FAST,BLE,1M
Time between TXEN task and READY event after channel
FREQUENCY configured (1 Mbps BLE with fast ramp-up and
150 µs TIFS)
tTXDIS,BLE,1M
When in TX, delay between DISABLE task and DISABLED
event for MODE = Nrf_1Mbit and MODE = Ble_1Mbit
tRXEN,BLE,1M
Time between the RXEN task and READY event after channel
FREQUENCY configured (1 Mbps BLE)
tRXEN,FAST,BLE,1M
Time between the RXEN task and READY event after channel
FREQUENCY configured (1 Mbps BLE with fast ramp-up)
tRXDIS,BLE,1M
When in RX, delay between DISABLE task and DISABLED
event for MODE = Nrf_1Mbit and MODE = Ble_1Mbit
tTXDIS,BLE,2M
When in TX, delay between DISABLE task and DISABLED
event for MODE = Nrf_2Mbit and MODE = Ble_2Mbit
tRXDIS,BLE,2M
When in RX, delay between DISABLE task and DISABLED
event for MODE = Nrf_2Mbit and MODE = Ble_2Mbit
tTXEN,IEEE 802.15.4
Time between TXEN task and READY event after channel
FREQUENCY configured (IEEE 802.15.4)
tTXEN,FAST,IEEE 802.15.4 Time between TXEN task and READY event after channel
FREQUENCY configured (IEEE 802.15.4 with fast ramp-up)
tTXDIS,IEEE 802.15.4
When in TX, delay between DISABLE task and DISABLED
event (IEEE 802.15.4)
tRXEN,IEEE 802.15.4
Time between the RXEN task and READY event after channel
FREQUENCY configured (IEEE 802.15.4)
tRXEN,FAST,IEEE 802.15.4 Time between the RXEN task and READY event after channel
FREQUENCY configured (IEEE 802.15.4 with fast ramp-up)
tRXDIS,IEEE 802.15.4
When in RX, delay between DISABLE task and DISABLED
event (IEEE 802.15.4)
tRX-to-TX turnaround
Maximum TX-to-RX or RX-to-TX turnaround time in IEEE
40
µs
802.15.4 mode
6.14.16.9 Received signal strength indicator (RSSI) specifications
Symbol
Description
RSSIACC
RSSI accuracy valid range -90 to -20 dBm
±2
dB
RSSIRESOLUTION
RSSI resolution
1
dB
RSSIPERIOD
RSSI sampling time from RSSI_START task
0.25
µs
RSSISETTLE
RSSI settling time after signal level change
15
µs
4454_140 v1.0
Min.
242
Typ.
Max.
Units
Peripherals
6.14.16.10 Jitter
Symbol
Description
tDISABLEDJITTER
Jitter on DISABLED event relative to END event when
Min.
Typ.
Max.
Units
0.25
µs
0.25
µs
shortcut between END and DISABLE is enabled
tREADYJITTER
Jitter on READY event relative to TXEN and RXEN task
6.14.16.11 IEEE 802.15.4 energy detection constants
Symbol
Description
Min.
Typ.
Max.
ED_RSSISCALE
Scaling value when converting between hardware-reported
4
4
4
-92
-92
-92
Units
value and dBm
ED_RSSIOFFS
Offset value when converting between hardware-reported
value and dBm
6.15 RNG — Random number generator
The Random number generator (RNG) generates true non-deterministic random numbers based on
internal thermal noise that are suitable for cryptographic purposes. The RNG does not require a seed
value.
START
STOP
Random number
generator
VALRDY
VALUE
Figure 88: Random number generator
The RNG is started by triggering the START task and stopped by triggering the STOP task. When started,
new random numbers are generated continuously and written to the VALUE register when ready. A
VALRDY event is generated for every new random number that is written to the VALUE register. This means
that after a VALRDY event is generated the CPU has the time until the next VALRDY event to read out the
random number from the VALUE register before it is overwritten by a new random number.
6.15.1 Bias correction
A bias correction algorithm is employed on the internal bit stream to remove any bias toward '1' or '0'. The
bits are then queued into an eight-bit register for parallel readout from the VALUE register.
It is possible to enable bias correction in the CONFIG register. This will result in slower value generation,
but will ensure a statistically uniform distribution of the random values.
6.15.2 Speed
The time needed to generate one random byte of data is unpredictable, and may vary from one byte to
the next. This is especially true when bias correction is enabled.
4454_140 v1.0
243
Peripherals
6.15.3 Registers
Base address
Peripheral
Instance
Description
Configuration
0x4000D000
RNG
RNG
Random number generator
Table 70: Instances
Register
Offset
Description
TASKS_START
0x000
Task starting the random number generator
TASKS_STOP
0x004
Task stopping the random number generator
EVENTS_VALRDY
0x100
Event being generated for every new random number written to the VALUE register
SHORTS
0x200
Shortcuts between local events and tasks
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
CONFIG
0x504
Configuration register
VALUE
0x508
Output random number
Table 71: Register overview
6.15.3.1 TASKS_START
Address offset: 0x000
Task starting the random number generator
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Trigger
1
Description
TASKS_START
Task starting the random number generator
Trigger task
6.15.3.2 TASKS_STOP
Address offset: 0x004
Task stopping the random number generator
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Trigger
1
Description
TASKS_STOP
Task stopping the random number generator
Trigger task
6.15.3.3 EVENTS_VALRDY
Address offset: 0x100
Event being generated for every new random number written to the VALUE register
4454_140 v1.0
244
Peripherals
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW EVENTS_VALRDY
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Event being generated for every new random number
written to the VALUE register
NotGenerated
0
Event not generated
Generated
1
Event generated
6.15.3.4 SHORTS
Address offset: 0x200
Shortcuts between local events and tasks
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW VALRDY_STOP
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Shortcut between event VALRDY and task STOP
Disabled
0
Disable shortcut
Enabled
1
Enable shortcut
6.15.3.5 INTENSET
Address offset: 0x304
Enable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW VALRDY
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Write '1' to enable interrupt for event VALRDY
Set
1
Enable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
6.15.3.6 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW VALRDY
4454_140 v1.0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
Write '1' to disable interrupt for event VALRDY
245
Peripherals
6.15.3.7 CONFIG
Address offset: 0x504
Configuration register
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A
Reset 0x00000000
ID
Access
Field
A
RW DERCEN
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
Value
Description
Disabled
0
Disabled
Enabled
1
Enabled
Bias correction
6.15.3.8 VALUE
Address offset: 0x508
Output random number
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
A A A A A A A A
Reset 0x00000000
ID
Access
Field
A
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Value ID
VALUE
Value
Description
[0..255]
Generated random number
6.15.4 Electrical specification
6.15.4.1 RNG Electrical Specification
Symbol
Description
tRNG,START
Time from setting the START task to generation begins.
Min.
Typ.
Max.
Units
128
µs
30
µs
120
µs
This is a one-time delay on START signal and does not apply
between samples.
tRNG,RAW
Run time per byte without bias correction. Uniform
distribution of 0 and 1 is not guaranteed.
tRNG,BC
Run time per byte with bias correction. Uniform distribution
of 0 and 1 is guaranteed. Time to generate a byte cannot be
guaranteed.
6.16 RTC — Real-time counter
The Real-time counter (RTC) module provides a generic, low power timer on the low-frequency clock
source (LFCLK).
4454_140 v1.0
246
Peripherals
32.768 kHz
START
STOP
CLEAR
TRIGOVRFLW
task
PRESCALER
event
TICK
event
OVRFLW
event
COMPARE[0..N]
COUNTER
task
RTC
task
task
CC[0:3]
Figure 89: RTC block schematic
The RTC module features a 24-bit COUNTER, a 12-bit (1/X) prescaler, capture/compare registers, and a tick
event generator for low power, tickless RTOS implementation.
6.16.1 Clock source
The RTC will run off the LFCLK.
The COUNTER resolution will therefore be 30.517 μs. Depending on the source, the RTC is able to run
while the HFCLK is OFF and PCLK16M is not available.
The software has to explicitely start LFCLK before using the RTC.
See CLOCK — Clock control on page 61 for more information about clock sources.
6.16.2 Resolution versus overflow and the PRESCALER
Counter increment frequency:
fRTC [kHz] = 32.768 / (PRESCALER + 1 )
The PRESCALER register is read/write when the RTC is stopped. The PRESCALER register is read-only once
the RTC is STARTed. Writing to the PRESCALER register when the RTC is started has no effect.
The PRESCALER is restarted on START, CLEAR and TRIGOVRFLW, that is, the prescaler value is latched to an
internal register () on these tasks.
Examples:
1. Desired COUNTER frequency 100 Hz (10 ms counter period)
PRESCALER = round(32.768 kHz / 100 Hz) - 1 = 327
fRTC = 99.9 Hz
10009.576 μs counter period
2. Desired COUNTER frequency 8 Hz (125 ms counter period)
PRESCALER = round(32.768 kHz / 8 Hz) – 1 = 4095
fRTC = 8 Hz
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125 ms counter period
Prescaler
Counter resolution
Overflow
0
30.517 μs
512 seconds
28-1
7812.5 μs
131072 seconds
125 ms
582.542 hours
12
2 -1
Table 72: RTC resolution versus overflow
6.16.3 COUNTER register
The COUNTER increments on LFCLK when the internal PRESCALER register () is 0x00.
is reloaded from the PRESCALER register. If enabled, the TICK event occurs on each increment
of the COUNTER. The TICK event is disabled by default.
SysClk
LFClk
TICK
PRESC
COUNTER
0x000
0x000
0x000
0x000
0x000
0x000000
0x000001
0x000002
0x000003
Figure 90: Timing diagram - COUNTER_PRESCALER_0
SysClk
LFClk
TICK
PRESC
0x001
0x000
COUNTER
0x001
0x000000
0x000
0x001
0x000001
Figure 91: Timing diagram - COUNTER_PRESCALER_1
6.16.4 Overflow features
The TRIGOVRFLW task sets the COUNTER value to 0xFFFFF0 to allow SW test of the overflow condition.
OVRFLW occurs when COUNTER overflows from 0xFFFFFF to 0.
Important: The OVRFLW event is disabled by default.
6.16.5 TICK event
The TICK event enables low power "tick-less" RTOS implementation as it optionally provides a regular
interrupt source for a RTOS without the need to use the ARM® SysTick feature.
Using the RTC TICK event rather than the SysTick allows the CPU to be powered down while still keeping
RTOS scheduling active.
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Important: The TICK event is disabled by default.
6.16.6 Event control feature
To optimize RTC power consumption, events in the RTC can be individually disabled to prevent PCLK16M
and HFCLK being requested when those events are triggered. This is managed using the EVTEN register.
For example, if the TICK event is not required for an application, this event should be disabled as it is
frequently occurring and may increase power consumption if HFCLK otherwise could be powered down for
long durations.
This means that the RTC implements a slightly different task and event system compared to the standard
system described in Peripheral interface on page 74. The RTC task and event system is illustrated in
Tasks, events and interrupts in the RTC on page 249.
Task signal from PPI
RTC
write
TASK
OR
task
RTC
core
event
EVTEN
m
INTEN
m
EVENT m
IRQ signal to NVIC
Event signal to PPI
Figure 92: Tasks, events and interrupts in the RTC
6.16.7 Compare feature
There are a number of Compare registers.
For more information, see Registers on page 254.
When setting a compare register, the following behavior of the RTC compare event should be noted:
• If a CC register value is 0 when a CLEAR task is set, this will not trigger a COMPARE event.
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SysClk
LFClk
PRESC
0x000
COUNTER
X
0x000000
CLEAR
CC[0]
0x000000
COMPARE[0]
0
Figure 93: Timing diagram - COMPARE_CLEAR
• If a CC register is N and the COUNTER value is N when the START task is set, this will not trigger a
COMPARE event.
SysClk
LFClk
PRESC
0x000
COUNTER
N-1
N
N+1
START
CC[0]
N
COMPARE[0]
0
Figure 94: Timing diagram - COMPARE_START
• COMPARE occurs when a CC register is N and the COUNTER value transitions from N-1 to N.
SysClk
LFClk
PRESC
COUNTER
0x000
N-2
N-1
CC[0]
COMPARE[0]
N
N+1
N
0
1
Figure 95: Timing diagram - COMPARE
• If the COUNTER is N, writing N+2 to a CC register is guaranteed to trigger a COMPARE event at N+2.
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SysClk
LFClk
PRESC
COUNTER
0x000
N-1
N
N+1
N+2
> 62.5 ns
CC[0]
X
N+2
COMPARE[0]
0
1
Figure 96: Timing diagram - COMPARE_N+2
• If the COUNTER is N, writing N or N+1 to a CC register may not trigger a COMPARE event.
SysClk
LFClk
PRESC
COUNTER
0x000
N-2
N-1
N
N+1
>= 0
CC[0]
X
N+1
COMPARE[0]
0
Figure 97: Timing diagram - COMPARE_N+1
• If the COUNTER is N and the current CC register value is N+1 or N+2 when a new CC value is written, a
match may trigger on the previous CC value before the new value takes effect. If the current CC value
greater than N+2 when the new value is written, there will be no event due to the old value.
SysClk
LFClk
PRESC
COUNTER
CC[0]
0x000
N-2
N-1
N
N+1
>= 0
N
X
COMPARE[0]
0
1
Figure 98: Timing diagram - COMPARE_N-1
6.16.8 TASK and EVENT jitter/delay
Jitter or delay in the RTC is due to the peripheral clock being a low frequency clock (LFCLK) which is not
synchronous to the faster PCLK16M.
Registers in the peripheral interface, part of the PCLK16M domain, have a set of mirrored registers in the
LFCLK domain. For example, the COUNTER value accessible from the CPU is in the PCLK16M domain and
is latched on read from an internal register called COUNTER in the LFCLK domain. COUNTER is the register
which is actually modified each time the RTC ticks. These registers must be synchronised between clock
domains (PCLK16M and LFCLK).
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The following is a summary of the jitter introduced on tasks and events. Figures illustrating jitter follow.
Task
Delay
CLEAR, STOP, START, TRIGOVRFLOW
+15 to 46 μs
Table 73: RTC jitter magnitudes on tasks
Operation/Function
Jitter
START to COUNTER increment
COMPARE to COMPARE
+/- 15 μs
+/- 62.5 ns
20
Table 74: RTC jitter magnitudes on events
1. CLEAR and STOP (and TRIGOVRFLW; not shown) will be delayed as long as it takes for the peripheral to
clock a falling edge and rising of the LFCLK. This is between 15.2585 μs and 45.7755 μs – rounded to 15
μs and 46 μs for the remainder of the section.
SysClk
CLEAR
LFClk
PRESC
COUNTER
CLEARa
0x000
X
X+1
0x000000
0x000001
0 or more SysClk after
= ~15 us
1 or more SysClk before
CLEARb
Figure 99: Timing diagram - DELAY_CLEAR
SysClk
STOP
LFClk
PRESC
COUNTER
STOPa
STOPb
0x000
X
X+1
0 or more SysClk after
= ~15 us
1 or more SysClk before
Figure 100: Timing diagram - DELAY_STOP
2. The START task will start the RTC. Assuming that the LFCLK was previously running and stable, the
first increment of COUNTER (and instance of TICK event) will be typically after 30.5 μs +/-15 μs. In
some cases, in particular if the RTC is STARTed before the LFCLK is running, that timing can be up to
~250 μs. The software should therefore wait for the first TICK if it has to make sure the RTC is running.
20
Assumes RTC runs continuously between these events.
Note: 32.768 kHz clock jitter is additional to the numbers provided above.
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Sending a TRIGOVRFLW task sets the COUNTER to a value close to overflow. However, since the update
of COUNTER relies on a stable LFCLK, sending this task while LFCLK is not running will start LFCLK,
but the update will then be delayed by the same amount of time of up to ~250 us. The figures show
the smallest and largest delays to on the START task which appears as a +/-15 μs jitter on the first
COUNTER increment.
SysClk
First tick
LFClk
PRESC
0x000
COUNTER
X
X+1
X+2
X+3
>= ~15 us
0 or more SysClk before
START
Figure 101: Timing diagram - JITTER_STARTSysClk
First tick
LFClk
PRESC
0x000
COUNTER
X
X+1
X+2
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