74HC4053M/TR

74HC4053/ 74HCT4053 Triple 2-channel analog multiplexer/demultiplexer 1. General description The 74HC4053; 74HCT4053 is a high-speed Si-gate CMOS device and is pin compatible with the HEF4053B. It is specified in compliance with JEDEC standard no. 7A. The 74HC4053; 74HCT4053 is triple 2-channel analog multiplexer/demultiplexer with a common enable input (E). Each multiplexer/demultiplexer has two independent inputs/outputs (nY0 and nY1), a common input/output (nZ) and three digital select inputs (Sn). With E LOW, one of the two switches is selected (low-impedance ON-state) by S1 to S3. With E HIGH, all switches are in the high-impedance OFF-state, independent of S1 to S3. VCC and GND are the supply voltage pins for the digital control inputs (S0 to S2, and E). The VCC to GND ranges are 2.0 V to 10.0 V for 74HC4053 and 4.5 V to 5.5 V for 74HCT4053. The analog inputs/outputs (nY0 to nY1, and nZ) can swing between VCC as a positive limit and VEE as a negative limit. VCC  VEE may not exceed 10.0 V. For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically ground). 2. Features and benefits  Wide analog input voltage range from 5 V to +5 V  Low ON resistance: 80  (typical) at VCC  VEE = 4.5 V 70  (typical) at VCC  VEE = 6.0 V 60  (typical) at VCC  VEE = 9.0 V  Logic level translation: to enable 5 V logic to communicate with 5 V analog signals  Typical ‘break before make’ built-in  ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V  Multiple package options  Specified from 40 C to +85 C and 40 C to +125 C 3. Applications  Analog multiplexing and demultiplexing  Digital multiplexing and demultiplexing  Signal gating http://www.hgsemi.com.cn 1 2018 AUG 74HC4053/ 74HCT4053 4. Functional diagram E 6 VCC 16 13 1Y1 S1 11 LOGIC LEVEL CONVERSION 12 1Y0 DECODER 14 1Z 1 2Y1 S2 10 LOGIC LEVEL CONVERSION 2 2Y0 15 2Z 3 3Y1 S3 9 LOGIC LEVEL CONVERSION 5 3Y0 4 3Z 8 GND Fig 1. 7 VEE 001aak341 Functional diagram 6 11 S1 1Y0 12 10 S2 1Y1 13 9 S3 1Z 14 11 2Y0 2 14 2Y1 1 2Z 6 E 10 15 EN # MUX/DMUX 0 0 1 × 0/1 1 # 5 3Y1 3 9 3Z 4 4 13 2 1 15 3Y0 12 5 # 3 001aae125 001aae126 Fig 2. Logic symbol http://www.hgsemi.com.cn Fig 3. 2 IEC logic symbol 2018 AUG 74HC4053/ 74HCT4053 Y VCC VEE VCC VCC VCC VEE VEE from logic Z 001aad544 Fig 4. Schematic diagram (one switch) 5. Pinning information 5.1 Pinning 74HC4053 74HCT4053 14 1Z 3Z 4 13 1Y1 3Y0 5 12 1Y0 E 6 11 S1 VEE 7 GND 8 10 S2 9 S3 001aae127 16 VCC 15 2Z 3 2Y0 2 15 2Z 3Y1 3 14 1Z 3Z 4 13 1Y1 3Y0 5 E 6 VEE 7 12 1Y0 VCC(1) 11 S1 10 S2 9 2 3Y1 S3 2Y0 terminal 1 index area 1 16 VCC 8 1 GND 2Y1 2Y1 74HC4053 74HCT4053 001aae128 Transparent top view (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to VCC. Fig 5. Pin configuration DIP16, SO16, and (T)SSOP16 http://www.hgsemi.com.cn Fig 6. 3 Pin configuration DHVQFN16 2018 AUG 74HC4053/ 74HCT4053 5.2 Pin description Table 2. Pin description Symbol Pin Description E 6 enable input (active LOW) VEE 7 supply voltage GND 8 ground supply voltage S1, S2, S3 11, 10, 9 select input 1Y0, 2Y0, 3Y0 12, 2, 5 independent input or output 1Y1, 2Y1, 3Y1 13, 1, 3 independent input or output 1Z, 2Z, 3Z 14, 15, 4 common output or input VCC 16 supply voltage 6. Functional description Table 3. Function table [1] Inputs Channel on E Sn L L nY0 to nZ L H nY1 to nZ H X switches off [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground). Symbol Parameter VCC supply voltage Conditions [1] Min Max Unit 0.5 +11.0 V IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V - 20 mA ISK switch clamping current VSW < 0.5 V or VSW > VCC + 0.5 V - 20 mA ISW switch current 0.5 V < VSW < VCC + 0.5 V - 25 mA IEE supply current - 20 mA ICC supply current - 50 mA IGND ground current - 50 mA Tstg storage temperature Ptot P total power dissipation power dissipation 65 +150 C DIP16 package [2] - 750 mW SO16, (T)SSOP16, and DHVQFN16 package [3] - 500 mW - 100 mW per switch [1] To avoid drawing VCC current out of terminal nZ, when switch current flows into terminals nYn, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no VCC current will flow out of terminals nYn, and in this case there is no limit for the voltage drop across the switch, but the voltages at nYn and nZ may not exceed VCC or VEE. [2] For DIP16 packages: above 70 C the value of Ptot derates linearly with 12 mW/K. http://www.hgsemi.com.cn 4 2018 AUG 74HC4053/ 74HCT4053 For SO16 packages: above 70 C the value of Ptot derates linearly with 8 mW/K. [3] For SSOP16 and TSSOP16 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K. For DHVQFN16 packages: above 60 C the value of Ptot derates linearly with 4.5 mW/K. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions supply voltage VCC 74HC4053 74HCT4053 Unit Min Typ Max Min Typ Max VCC  GND 2.0 5.0 10.0 4.5 5.0 5.5 V VCC  VEE 2.0 5.0 10.0 2.0 5.0 10.0 V see Figure 7 and Figure 8 VI input voltage GND - VCC GND - VCC V VSW switch voltage VEE - VCC VEE - VCC V Tamb ambient temperature t/V input transition rise and fall rate 40 +25 +125 40 +25 +125 VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V VCC = 10.0 V - - 31 - - - ns/V 001aad545 10 001aad546 10 VCC − GND (V) C VCC − GND (V) 8 8 6 6 operating area operating area 4 4 2 2 0 0 0 Fig 7. 2 4 6 8 10 VCC − VEE (V) 0 Guaranteed operating area as a function of the supply voltages for 74HC4053 http://www.hgsemi.com.cn Fig 8. 5 2 4 6 8 10 VCC − VEE (V) Guaranteed operating area as a function of the supply voltages for 74HCT4053 2018 AUG 74HC4053/ 74HCT4053 9. Static characteristics Table 6. RON resistance per switch for 74HC4053 and 74HCT4053 VI = VIH or VIL; for test circuit see Figure 9. Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input. Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output. For 74HC4053: VCC  GND or VCC  VEE = 2.0 V, 4.5 V, 6.0 V and 9.0 V. For 74HCT4053: VCC  GND = 4.5 V and 5.5 V, VCC  VEE = 2.0 V, 4.5 V, 6.0 V and 9.0 V. Symbol Parameter Conditions Min Typ Max Unit - - -  VCC = 4.5 V; VEE = 0 V; ISW = 1000 A - 100 180  VCC = 6.0 V; VEE = 0 V; ISW = 1000 A - 90 160  VCC = 4.5 V; VEE = 4.5 V; ISW = 1000 A - 70 130  - 150 -  VCC = 4.5 V; VEE = 0 V; ISW = 1000 A - 80 140  VCC = 6.0 V; VEE = 0 V; ISW = 1000 A - 70 120  VCC = 4.5 V; VEE = 4.5 V; ISW = 1000 A - 60 105  - 150 -  VCC = 4.5 V; VEE = 0 V; ISW = 1000 A - 90 160  VCC = 6.0 V; VEE = 0 V; ISW = 1000 A - 80 140  VCC = 4.5 V; VEE = 4.5 V; ISW = 1000 A - 65 120  Tamb = 25 C RON(peak) ON resistance (peak) Vis = VCC to VEE VCC = 2.0 V; VEE = 0 V; ISW = 100 A RON(rail) ON resistance (rail) [1] Vis = VEE VCC = 2.0 V; VEE = 0 V; ISW = 100 A [1] Vis = VCC VCC = 2.0 V; VEE = 0 V; ISW = 100 A RON ON resistance mismatch between channels [1] Vis = VCC to VEE - - -  VCC = 4.5 V; VEE = 0 V - 9 -  VCC = 6.0 V; VEE = 0 V - 8 -  VCC = 4.5 V; VEE = 4.5 V - 6 -  - - -  VCC = 4.5 V; VEE = 0 V; ISW = 1000 A - - 225  VCC = 6.0 V; VEE = 0 V; ISW = 1000 A - - 200  VCC = 4.5 V; VEE = 4.5 V; ISW = 1000 A - - 165  VCC = 2.0 V; VEE = 0 V [1] Tamb = 40 C to +85 C RON(peak) ON resistance (peak) Vis = VCC to VEE VCC = 2.0 V; VEE = 0 V; ISW = 100 A http://www.hgsemi.com.cn 6 [1] 2018 AUG 74HC4053/ 74HCT4053 Table 6. RON resistance per switch for 74HC4053 and 74HCT4053 …continued VI = VIH or VIL; for test circuit see Figure 9. Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input. Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output. For 74HC4053: VCC  GND or VCC  VEE = 2.0 V, 4.5 V, 6.0 V and 9.0 V. For 74HCT4053: VCC  GND = 4.5 V and 5.5 V, VCC  VEE = 2.0 V, 4.5 V, 6.0 V and 9.0 V. Symbol Parameter Conditions Min Typ Max Unit RON(rail) ON resistance (rail) Vis = VEE - - -  VCC = 4.5 V; VEE = 0 V; ISW = 1000 A - - 175  VCC = 6.0 V; VEE = 0 V; ISW = 1000 A - - 150  VCC = 4.5 V; VEE = 4.5 V; ISW = 1000 A - - 130  VCC = 2.0 V; VEE = 0 V; ISW = 100 A [1] Vis = VCC VCC = 2.0 V; VEE = 0 V; ISW = 100 A - - -  VCC = 4.5 V; VEE = 0 V; ISW = 1000 A - - 200  VCC = 6.0 V; VEE = 0 V; ISW = 1000 A - - 175  VCC = 4.5 V; VEE = 4.5 V; ISW = 1000 A - - 150  - - -  VCC = 4.5 V; VEE = 0 V; ISW = 1000 A - - 270  VCC = 6.0 V; VEE = 0 V; ISW = 1000 A - - 240  VCC = 4.5 V; VEE = 4.5 V; ISW = 1000 A - - 195  - - -  VCC = 4.5 V; VEE = 0 V; ISW = 1000 A - - 210  VCC = 6.0 V; VEE = 0 V; ISW = 1000 A - - 180  VCC = 4.5 V; VEE = 4.5 V; ISW = 1000 A - - 160  [1] Tamb = 40 C to +125 C RON(peak) ON resistance (peak) Vis = VCC to VEE VCC = 2.0 V; VEE = 0 V; ISW = 100 A RON(rail) ON resistance (rail) [1] Vis = VEE VCC = 2.0 V; VEE = 0 V; ISW = 100 A [1] Vis = VCC VCC = 2.0 V; VEE = 0 V; ISW = 100 A [1] - - -  VCC = 4.5 V; VEE = 0 V; ISW = 1000 A - - 240  VCC = 6.0 V; VEE = 0 V; ISW = 1000 A - - 210  VCC = 4.5 V; VEE = 4.5 V; ISW = 1000 A - - 180  [1] When supply voltages (VCC  VEE) near 2.0 V the analog switch ON resistance becomes extremely non-linear. When using a supply of 2 V, it is recommended to use these devices only for transmitting digital signals. http://www.hgsemi.com.cn 7 2018 AUG 74HC4053/ 74HCT4053 mnb047 110 (1) RON (Ω) 90 70 (2) Vsw V (3) 50 VCC from select input Sn Vis 30 nZ nYn GND VEE Isw 10 0 1.8 3.6 5.4 7.2 9.0 Vis (V) 001aah826 Vis = 0 V to (VCC  VEE). Vis = 0 V to (VCC  VEE). (1) VCC = 4.5 V V sw R ON = -------I sw (2) VCC = 6 V (3) VCC = 9 V Fig 9. Test circuit for measuring RON Fig 10. Typical RON as a function of input voltage Vis Table 7. Static characteristics for 74HC4053 Voltages are referenced to GND (ground = 0 V). Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input. Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output. Symbol Parameter Conditions Min Typ Max Unit VCC = 2.0 V 1.5 1.2 - V VCC = 4.5 V 3.15 2.4 - V Tamb = 25 C VIH VIL II IS(OFF) IS(ON) HIGH-level input voltage LOW-level input voltage input leakage current OFF-state leakage current ON-state leakage current http://www.hgsemi.com.cn VCC = 6.0 V 4.2 3.2 - V VCC = 9.0 V 6.3 4.7 - V VCC = 2.0 V - 0.8 0.5 V VCC = 4.5 V - 2.1 1.35 V VCC = 6.0 V - 2.8 1.8 V VCC = 9.0 V - 4.3 2.7 V VCC = 6.0 V - - 0.1 A VCC = 10.0 V - - 0.2 A per channel - - 0.1 A all channels - - 0.1 A - - 0.1 A VEE = 0 V; VI = VCC or GND VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL; VSW = VCC  VEE; see Figure 11 VI = VIH or VIL; VSW = VCC  VEE; VCC = 10.0 V; VEE = 0 V; see Figure 12 8 2018 AUG 74HC4053/ 74HCT4053 Table 7. Static characteristics for 74HC4053 …continued Voltages are referenced to GND (ground = 0 V). Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input. Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output. Symbol Parameter Conditions ICC supply current VEE = 0 V; VI = VCC or GND; Vis = VEE or VCC; Vos = VCC or VEE CI input capacitance Csw switch capacitance Min Typ Max Unit VCC = 6.0 V - - 8.0 A VCC = 10.0 V - - 16.0 A - 3.5 - pF independent pins nYn - 5 - pF common pins nZ - 8 - pF Tamb = 40 C to +85 C VIH VIL II IS(OFF) HIGH-level input voltage LOW-level input voltage input leakage current OFF-state leakage current VCC = 2.0 V 1.5 - - V VCC = 4.5 V 3.15 - - V VCC = 6.0 V 4.2 - - V VCC = 9.0 V 6.3 - - V VCC = 2.0 V - - 0.5 V VCC = 4.5 V - - 1.35 V VCC = 6.0 V - - 1.8 V VCC = 9.0 V - - 2.7 V VCC = 6.0 V - - 1.0 A VCC = 10.0 V - - 2.0 A per channel - - 1.0 A all channels - - 1.0 A - - 1.0 A VCC = 6.0 V - - 80.0 A VCC = 10.0 V - - 160.0 A VCC = 2.0 V 1.5 - - V VCC = 4.5 V 3.15 - - V VCC = 6.0 V 4.2 - - V VCC = 9.0 V 6.3 - - V VCC = 2.0 V - - 0.5 V VCC = 4.5 V - - 1.35 V VCC = 6.0 V - - 1.8 V VCC = 9.0 V - - 2.7 V VEE = 0 V; VI = VCC or GND VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL; VSW = VCC  VEE; see Figure 11 IS(ON) ON-state leakage current VI = VIH or VIL; VSW = VCC  VEE; VCC = 10.0 V; VEE = 0 V; see Figure 12 ICC supply current VEE = 0 V; VI = VCC or GND; Vis = VEE or VCC; Vos = VCC or VEE Tamb = 40 C to +125 C VIH VIL HIGH-level input voltage LOW-level input voltage http://www.hgsemi.com.cn 9 2018 AUG 74HC4053/ 74HCT4053 Table 7. Static characteristics for 74HC4053 …continued Voltages are referenced to GND (ground = 0 V). Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input. Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output. Symbol Parameter Conditions II input leakage current VEE = 0 V; VI = VCC or GND IS(OFF) OFF-state leakage current Min Typ Max Unit VCC = 6.0 V - - 1.0 A VCC = 10.0 V - - 2.0 A per channel - - 1.0 A all channels - - 1.0 A - - 1.0 A VCC = 6.0 V - - 160.0 A VCC = 10.0 V - - 320.0 A Conditions Min Typ Max Unit VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL; VSW = VCC  VEE; see Figure 11 IS(ON) ON-state leakage current VI = VIH or VIL; VSW = VCC  VEE; VCC = 10.0 V; VEE = 0 V; see Figure 12 ICC supply current VEE = 0 V; VI = VCC or GND; Vis = VEE or VCC; Vos = VCC or VEE Table 8. Static characteristics for 74HCT4053 Voltages are referenced to GND (ground = 0 V). Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input. Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output. Symbol Parameter Tamb = 25 C VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 V II input leakage current VI = VCC or GND; VCC = 5.5 V; VEE = 0 V - - 0.1 A IS(OFF) OFF-state leakage current VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL; VSW = VCC  VEE; see Figure 11 per channel - - 0.1 A all channels - - 0.1 A - - 0.1 A IS(ON) ON-state leakage current VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL; VSW = VCC  VEE; see Figure 12 ICC supply current VI = VCC or GND; Vis = VEE or VCC; Vos = VCC or VEE ICC additional supply current CI input capacitance Csw switch capacitance http://www.hgsemi.com.cn VCC = 5.5 V; VEE = 0 V - - 8.0 A VCC = 5.0 V; VEE = 5.0 V - - 16.0 A - 50 180 A per input; VI = VCC  2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; VEE = 0 V - 3.5 - pF independent pins nYn - 5 - pF common pins nZ - 8 - pF 10 2018 AUG 74HC4053/ 74HCT4053 Table 8. Static characteristics for 74HCT4053 …continued Voltages are referenced to GND (ground = 0 V). Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input. Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output. Symbol Parameter Conditions Min Typ Max Unit Tamb = 40 C to +85 C VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 V II input leakage current VI = VCC or GND; VCC = 5.5 V; VEE = 0 V - - 1.0 A IS(OFF) OFF-state leakage current VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL; VSW = VCC  VEE; see Figure 11 per channel - - 1.0 A all channels - - 1.0 A - - 1.0 A VCC = 5.5 V; VEE = 0 V - - 80.0 A VCC = 5.0 V; VEE = 5.0 V - - 160.0 A per input; VI = VCC  2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; VEE = 0 V - - 225 A IS(ON) ON-state leakage current VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL; VSW = VCC  VEE; see Figure 12 ICC supply current VI = VCC or GND; Vis = VEE or VCC; Vos = VCC or VEE ICC additional supply current Tamb = 40 C to +125 C VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 V II input leakage current VI = VCC or GND; VCC = 5.5 V; VEE = 0 V - - 1.0 A IS(OFF) OFF-state leakage current VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL; VSW = VCC  VEE; see Figure 11 per channel - - 1.0 A all channels - - 1.0 A - - 1.0 A IS(ON) ON-state leakage current VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL; VSW = VCC  VEE; see Figure 12 ICC supply current VI = VCC or GND; Vis = VEE or VCC; Vos = VCC or VEE ICC additional supply current http://www.hgsemi.com.cn VCC = 5.5 V; VEE = 0 V - - 160.0 A VCC = 5.0 V; VEE = 5.0 V - - 320.0 A - - 245 A per input; VI = VCC  2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; VEE = 0 V 11 2018 AUG 74HC4053/ 74HCT4053 VCC from select input Sn Isw A Isw nZ nYn GND Vis A VEE Vos 001aah827 Vis = VCC and Vos = VEE. Vis = VEE and Vos = VCC. Fig 11. Test circuit for measuring OFF-state current VCC HIGH from select input Sn Isw A nZ nYn GND Vis Vos VEE 001aah828 Vis = VCC and Vos = open-circuit. Vis = VEE and Vos = open-circuit. Fig 12. Test circuit for measuring ON-state current 10. Dynamic characteristics Table 9. Dynamic characteristics for 74HC4053 GND = 0 V; tr = tf = 6 ns; CL = 50 pF; for test circuit see Figure 15. Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input. Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output. Symbol Parameter Conditions Min Typ Max Unit VCC = 2.0 V; VEE = 0 V - 15 60 ns VCC = 4.5 V; VEE = 0 V - 5 12 ns VCC = 6.0 V; VEE = 0 V - 4 10 ns VCC = 4.5 V; VEE = 4.5 V - 4 8 ns Tamb = 25 C tpd propagation delay Vis to Vos; RL =  ; see Figure 13 http://www.hgsemi.com.cn 12 [1] 2018 AUG 74HC4053/ 74HCT4053 Table 9. Dynamic characteristics for 74HC4053 …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; for test circuit see Figure 15. Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input. Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output. Symbol ton Parameter Conditions Min Typ Max Unit turn-on time E to Vos; RL =  ; see Figure 14 VCC = 2.0 V; VEE = 0 V - 60 220 ns VCC = 4.5 V; VEE = 0 V - 20 44 ns VCC = 5.0 V; VEE = 0 V; CL = 15 pF - 17 - ns [2] VCC = 6.0 V; VEE = 0 V - 16 37 ns VCC = 4.5 V; VEE = 4.5 V - 15 31 ns VCC = 2.0 V; VEE = 0 V - 75 220 ns VCC = 4.5 V; VEE = 0 V - 25 44 ns VCC = 5.0 V; VEE = 0 V; CL = 15 pF - 21 - ns VCC = 6.0 V; VEE = 0 V - 20 37 ns - 15 31 ns VCC = 2.0 V; VEE = 0 V - 63 210 ns VCC = 4.5 V; VEE = 0 V - 21 42 ns VCC = 5.0 V; VEE = 0 V; CL = 15 pF - 18 - ns Sn to Vos; RL =  ; see Figure 14 [2] VCC = 4.5 V; VEE = 4.5 V toff turn-off time E to Vos; RL = 1 k; see Figure 14 [3] VCC = 6.0 V; VEE = 0 V - 17 36 ns VCC = 4.5 V; VEE = 4.5 V - 15 29 ns VCC = 2.0 V; VEE = 0 V - 60 210 ns VCC = 4.5 V; VEE = 0 V - 20 42 ns VCC = 5.0 V; VEE = 0 V; CL = 15 pF - 17 - ns VCC = 6.0 V; VEE = 0 V - 16 36 ns - 15 29 ns - 36 - pF VCC = 2.0 V; VEE = 0 V - - 75 ns VCC = 4.5 V; VEE = 0 V - - 15 ns VCC = 6.0 V; VEE = 0 V - - 13 ns VCC = 4.5 V; VEE = 4.5 V - - 10 ns Sn to Vos; RL = 1 k; see Figure 14 [3] VCC = 4.5 V; VEE = 4.5 V CPD [4] power dissipation per switch; VI = GND to VCC capacitance Tamb = 40 C to +85 C tpd propagation delay Vis to Vos; RL =  ; see Figure 13 http://www.hgsemi.com.cn 13 [1] 2018 AUG 74HC4053/ 74HCT4053 Table 9. Dynamic characteristics for 74HC4053 …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; for test circuit see Figure 15. Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input. Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output. Symbol ton Parameter Conditions Min Typ Max Unit turn-on time E to Vos; RL =  ; see Figure 14 VCC = 2.0 V; VEE = 0 V - - 275 ns VCC = 4.5 V; VEE = 0 V - - 55 ns VCC = 6.0 V; VEE = 0 V - - 47 ns - - 39 ns VCC = 2.0 V; VEE = 0 V - - 275 ns VCC = 4.5 V; VEE = 0 V - - 55 ns VCC = 6.0 V; VEE = 0 V - - 47 ns VCC = 4.5 V; VEE = 4.5 V - - 39 ns VCC = 2.0 V; VEE = 0 V - - 265 ns VCC = 4.5 V; VEE = 0 V - - 53 ns VCC = 6.0 V; VEE = 0 V - - 45 ns - - 36 ns VCC = 2.0 V; VEE = 0 V - - 265 ns VCC = 4.5 V; VEE = 0 V - - 53 ns VCC = 6.0 V; VEE = 0 V - - 45 ns VCC = 4.5 V; VEE = 4.5 V - - 36 ns VCC = 2.0 V; VEE = 0 V - - 90 ns VCC = 4.5 V; VEE = 0 V - - 18 ns VCC = 6.0 V; VEE = 0 V - - 15 ns VCC = 4.5 V; VEE = 4.5 V - - 12 ns VCC = 2.0 V; VEE = 0 V - - 330 ns VCC = 4.5 V; VEE = 0 V - - 66 ns VCC = 6.0 V; VEE = 0 V - - 56 ns - - 47 ns VCC = 2.0 V; VEE = 0 V - - 330 ns VCC = 4.5 V; VEE = 0 V - - 66 ns VCC = 6.0 V; VEE = 0 V - - 56 ns VCC = 4.5 V; VEE = 4.5 V - - 47 ns [2] VCC = 4.5 V; VEE = 4.5 V Sn to Vos; RL =  ; see Figure 14 toff turn-off time E to Vos; RL = 1 k; see Figure 14 [2] [3] VCC = 4.5 V; VEE = 4.5 V Sn to Vos; RL = 1 k; see Figure 14 [3] Tamb = 40 C to +125 C tpd ton propagation delay Vis to Vos; RL =  ; see Figure 13 turn-on time E to Vos; RL =  ; see Figure 14 [1] [2] VCC = 4.5 V; VEE = 4.5 V Sn to Vos; RL =  ; see Figure 14 http://www.hgsemi.com.cn 14 [2] 2018 AUG 74HC4053/ 74HCT4053 Table 9. Dynamic characteristics for 74HC4053 …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; for test circuit see Figure 15. Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input. Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output. Symbol toff Parameter turn-off time Conditions Min Typ Max Unit VCC = 2.0 V; VEE = 0 V - - 315 ns VCC = 4.5 V; VEE = 0 V - - 63 ns VCC = 6.0 V; VEE = 0 V - - 54 ns - - 44 ns VCC = 2.0 V; VEE = 0 V - - 315 ns VCC = 4.5 V; VEE = 0 V - - 63 ns VCC = 6.0 V; VEE = 0 V - - 54 ns VCC = 4.5 V; VEE = 4.5 V - - 44 ns Min Typ Max Unit - 5 12 ns - 4 8 ns VCC = 4.5 V; VEE = 0 V - 27 48 ns VCC = 5.0 V; VEE = 0 V; CL = 15 pF - 23 - ns - 16 34 ns VCC = 4.5 V; VEE = 0 V - 25 48 ns VCC = 5.0 V; VEE = 0 V; CL = 15 pF - 21 - ns VCC = 4.5 V; VEE = 4.5 V - 16 34 ns E to Vos; RL = 1 k; see Figure 14 [3] VCC = 4.5 V; VEE = 4.5 V Sn to Vos; RL = 1 k; see Figure 14 [1] tpd is the same as tPHL and tPLH. [2] ton is the same as tPZH and tPZL. [3] toff is the same as tPHZ and tPLZ. [4] [3] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + {(CL + Csw)  VCC2  fo} where: fi = input frequency in MHz; fo = output frequency in MHz; N = number of inputs switching; {(CL + Csw)  VCC2  fo} = sum of outputs; CL = output load capacitance in pF; Csw = switch capacitance in pF; VCC = supply voltage in V. Table 10. Dynamic characteristics for 74HCT4053 GND = 0 V; tr = tf = 6 ns; CL = 50 pF; for test circuit see Figure 15. Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input. Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output. Symbol Parameter Conditions Tamb = 25 C tpd propagation delay Vis to Vos; RL =  ; see Figure 13 [1] VCC = 4.5 V; VEE = 0 V VCC = 4.5 V; VEE = 4.5 V ton turn-on time E to Vos; RL = 1 k; see Figure 14 [2] VCC = 4.5 V; VEE = 4.5 V Sn to Vos; RL = 1 k; see Figure 14 http://www.hgsemi.com.cn 15 [2] 2018 AUG 74HC4053/ 74HCT4053 Table 10. Dynamic characteristics for 74HCT4053 …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; for test circuit see Figure 15. Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input. Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output. Symbol toff Parameter turn-off time Conditions Min Typ Max Unit VCC = 4.5 V; VEE = 0 V - 24 44 ns VCC = 5.0 V; VEE = 0 V; CL = 15 pF - 20 - ns - 15 31 ns VCC = 4.5 V; VEE = 0 V - 22 44 ns VCC = 5.0 V; VEE = 0 V; CL = 15 pF - 19 - ns - 15 31 ns - 36 - pF E to Vos; RL = 1 k; see Figure 14 [3] VCC = 4.5 V; VEE = 4.5 V Sn to Vos; RL = 1 k; see Figure 14 [3] VCC = 4.5 V; VEE = 4.5 V CPD power dissipation per switch; VI = GND to VCC  1.5 V capacitance [4] Tamb = 40 C to +85 C tpd ton propagation delay Vis to Vos; RL =  ; see Figure 13 turn-on time [1] VCC = 4.5 V; VEE = 0 V - - 15 ns VCC = 4.5 V; VEE = 4.5 V - - 10 ns - - 60 ns - - 43 ns - - 60 ns - - 43 ns - - 55 ns - - 39 ns E to Vos; RL = 1 k; see Figure 14 [2] VCC = 4.5 V; VEE = 0 V VCC = 4.5 V; VEE = 4.5 V Sn to Vos; RL = 1 k; see Figure 14 [2] VCC = 4.5 V; VEE = 0 V VCC = 4.5 V; VEE = 4.5 V toff turn-off time E to Vos; RL = 1 k; see Figure 14 [3] VCC = 4.5 V; VEE = 0 V VCC = 4.5 V; VEE = 4.5 V Sn to Vos; RL = 1 k; see Figure 14 [3] VCC = 4.5 V; VEE = 0 V - - 55 ns VCC = 4.5 V; VEE = 4.5 V - - 39 ns Tamb = 40 C to +125 C tpd ton propagation delay Vis to Vos; RL =  ; see Figure 13 turn-on time [1] VCC = 4.5 V; VEE = 0 V - - 18 ns VCC = 4.5 V; VEE = 4.5 V - - 12 ns - - 72 ns - - 51 ns VCC = 4.5 V; VEE = 0 V - - 72 ns VCC = 4.5 V; VEE = 4.5 V - - 51 ns E to Vos; RL = 1 k; see Figure 14 [2] VCC = 4.5 V; VEE = 0 V VCC = 4.5 V; VEE = 4.5 V Sn to Vos; RL = 1 k; see Figure 14 http://www.hgsemi.com.cn 16 [2] 2018 AUG 74HC4053/ 74HCT4053 Table 10. Dynamic characteristics for 74HCT4053 …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; for test circuit see Figure 15. Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input. Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output. Symbol toff Parameter turn-off time Conditions E to Vos; RL = 1 k; see Figure 14 VCC = 4.5 V; VEE = 0 V VCC = 4.5 V; VEE = 4.5 V Sn to Vos; RL = 1 k; see Figure 14 [1] tpd is the same as tPHL and tPLH. [2] ton is the same as tPZH and tPZL. [3] toff is the same as tPHZ and tPLZ. [4] Min Typ Max Unit - - 66 ns - - 47 ns [3] [3] VCC = 4.5 V; VEE = 0 V - - 66 ns VCC = 4.5 V; VEE = 4.5 V - - 47 ns CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + {(CL + Csw)  VCC2  fo} where: fi = input frequency in MHz; fo = output frequency in MHz; N = number of inputs switching; {(CL + Csw)  VCC2  fo} = sum of outputs; CL = output load capacitance in pF; Csw = switch capacitance in pF; VCC = supply voltage in V. Vis input 50 % tPLH Vos output tPHL 50 % 001aad555 Fig 13. Input (Vis) to output (Vos) propagation delays http://www.hgsemi.com.cn 17 2018 AUG 74HC4053/ 74HCT4053 VI VM E, Sn inputs 0V tPLZ tPZL 50 % Vos output 10 % tPHZ tPZH 90 % 50 % Vos output switch ON switch ON switch OFF 001aad556 For 74HC4053: VM = 0.5  VCC. For 74HCT4053: VM = 1.3 V. Fig 14. Turn-on and turn-off times VI tW 90 % negative pulse VM 0V VI tf tr tr tf 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC Vis PULSE GENERATOR VI VCC Vos RL RT S1 open DUT CL GND VEE 001aae382 Definitions for test circuit; see Table 11: RT = termination resistance should be equal to the output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. RL = load resistance. S1 = Test selection switch. Fig 15. Test circuit for measuring AC performance http://www.hgsemi.com.cn 18 2018 AUG 74HC4053/ 74HCT4053 Table 11. Test data Test Input VI Load Vis t r , tf S1 position CL RL at fmax other[1] tPHL, tPLH [2] pulse < 2 ns 6 ns 50 pF 1 k open tPZH, tPHZ [2] VCC < 2 ns 6 ns 50 pF 1 k VEE tPZL, tPLZ [2] VEE < 2 ns 6 ns 50 pF 1 k VCC [1] [2] tr = tf = 6 ns; when measuring fmax, there is no constraint to tr and tf with 50 % duty factor. VI values: a) For 74HC4053: VI = VCC b) For 74HCT4053: VI = 3 V 10.1 Additional dynamic characteristics Table 12. Additional dynamic characteristics Recommended conditions and typical values; GND = 0 V; Tamb = 25 C; CL = 50 pF. Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input. Vos is the output voltage at pins nYn or nZ, whichever is assigned as an output. Symbol Parameter Conditions dsin sine-wave distortion fi = 1 kHz; RL = 10 k; see Figure 16 Min Typ Max Unit Vis = 4.0 V (p-p); VCC = 2.25 V; VEE = 2.25 V - 0.04 - % Vis = 8.0 V (p-p); VCC = 4.5 V; VEE = 4.5 V - 0.02 - % Vis = 4.0 V (p-p); VCC = 2.25 V; VEE = 2.25 V - 0.12 - % Vis = 8.0 V (p-p); VCC = 4.5 V; VEE = 4.5 V - 0.06 - % fi = 10 kHz; RL = 10 k; see Figure 16 iso isolation (OFF-state) Xtalk crosstalk crosstalk voltage Vct f(3dB) 3 dB frequency response RL = 600 ; fi = 1 MHz; see Figure 17 VCC = 2.25 V; VEE = 2.25 V [1] - 50 - dB VCC = 4.5 V; VEE = 4.5 V [1] - 50 - dB VCC = 2.25 V; VEE = 2.25 V [1] - 60 - dB VCC = 4.5 V; VEE = 4.5 V [1] - 60 - dB VCC = 4.5 V; VEE = 0 V - 110 - mV VCC = 4.5 V; VEE = 4.5 V - 220 - mV between two switches/multiplexers; RL = 600 ; fi = 1 MHz; see Figure 18 peak-to-peak value; between control and any switch; RL = 600 ; fi = 1 MHz; E or Sn square wave between VCC and GND; tr = tf = 6 ns; see Figure 19 RL = 50 ; see Figure 20 VCC = 2.25 V; VEE = 2.25 V [2] - 160 - MHz VCC = 4.5 V; VEE = 4.5 V [2] - 170 - MHz [1] Adjust input voltage Vis to 0 dBm level (0 dBm = 1 mW into 600 ). [2] Adjust input voltage Vis to 0 dBm level at Vos for 1 MHz (0 dBm = 1 mW into 50 ). http://www.hgsemi.com.cn 19 2018 AUG 74HC4053/ 74HCT4053 VCC Sn 10 μF Vis nYn/nZ nZ/nYn VEE GND RL Vos CL dB 001aah829 Fig 16. Test circuit for measuring sine-wave distortion VCC Sn 0.1 μF Vis nYn/nZ nZ/nYn VEE GND RL Vos CL dB 001aah871 VCC = 4.5 V; GND = 0 V; VEE = 4.5 V; RL = 600 ; RS = 1 k. a. Test circuit 001aae332 0 αiso (dB) −20 −40 −60 −80 −100 10 102 103 104 105 106 fi (kHz) b. Isolation (OFF-state) as a function of frequency Fig 17. Test circuit for measuring isolation (OFF-state) http://www.hgsemi.com.cn 20 2018 AUG 74HC4053/ 74HCT4053 VCC Sn 0.1 μF Vis RL nYn/nZ nZ/nYn VEE GND RL CL VCC Sn nYn/nZ nZ/nYn VEE RL GND RL Vos CL dB 001aah873 Fig 18. Test circuits for measuring crosstalk between any two switches/multiplexers 2RL 2RL VCC Sn, E Vct nYn G 2RL nZ VEE GND 2RL oscilloscope 001aah913 Fig 19. Test circuit for measuring crosstalk between control input and any switch http://www.hgsemi.com.cn 21 2018 AUG 74HC4053/ 74HCT4053 VCC Sn 10 μF Vis nYn/nZ nZ/nYn VEE GND RL Vos CL dB 001aah829 VCC = 4.5 V; GND = 0 V; VEE = 4.5 V; RL = 50 ; RS = 1 k. a. Test circuit 001aad551 5 Vos (dB) 3 1 −1 −3 −5 10 102 103 104 105 106 f (kHz) b. Typical frequency response Fig 20. Test circuit for frequency response http://www.hgsemi.com.cn 22 2018 AUG