GD32FFPRTGU6

GigaDevice Semiconductor Inc. GD32FFPRTGU6 ARM® Cortex®-M4 32-bit MCU Datasheet GD32FFPRTGU6 Table of Contents List of Figures ............................................................................................................................. 3 List of Tables ............................................................................................................................... 4 1 General description ......................................................................................................... 5 2 Device overview ............................................................................................................... 6 2.1 Device information .............................................................................................................................. 6 2.2 Block diagram ...................................................................................................................................... 7 2.3 Pinouts and pin assignment .............................................................................................................. 8 2.4 Memory map ........................................................................................................................................ 9 2.5 Clock tree ........................................................................................................................................... 13 2.6 Pin definitions .................................................................................................................................... 14 Functional description .................................................................................................. 16 3 3.1 ARM® Cortex®-M4 core .................................................................................................................... 16 3.2 On-chip memory................................................................................................................................ 17 3.3 Clock, reset and supply management ........................................................................................... 17 3.4 Boot modes ........................................................................................................................................ 18 3.5 Power saving modes ........................................................................................................................ 18 3.6 Analog to digital converter (ADC) ................................................................................................... 19 3.7 DMA .................................................................................................................................................... 19 3.8 General-purpose inputs/outputs (GPIOs) ...................................................................................... 19 3.9 Timers and PWM generation........................................................................................................... 20 3.10 Real time clock (RTC) ...................................................................................................................... 21 3.11 Inter-integrated circuit (I2C) ............................................................................................................. 21 3.12 Serial peripheral interface (SPI)...................................................................................................... 22 3.13 Universal synchronous asynchronous receiver transmitter (USART) ....................................... 22 3.14 Universal serial bus full-speed (USB 2.0 FS) ............................................................................... 22 3.15 Debug mode ...................................................................................................................................... 23 3.16 Package and operation temperature.............................................................................................. 23 Electrical characteristics .............................................................................................. 24 4 4.1 Absolute maximum ratings .............................................................................................................. 24 4.2 Recommended DC characteristics ................................................................................................. 24 4.3 Power consumption .......................................................................................................................... 25 4.4 EMC characteristics .......................................................................................................................... 26 4.5 Power supply supervisor characteristics ....................................................................................... 27 4.6 Electrical sensitivity........................................................................................................................... 27 4.7 External clock characteristics .......................................................................................................... 28 4.8 Internal clock characteristics ........................................................................................................... 29 4.9 PLL characteristics ........................................................................................................................... 30 4.10 Memory characteristics .................................................................................................................... 31 1 / 40 GD32FFPRTGU6 4.11 GPIO characteristics......................................................................................................................... 32 4.12 ADC characteristics .......................................................................................................................... 33 4.13 DAC characteristics .......................................................................................................................... 35 4.14 SPI characteristics ............................................................................................................................ 36 4.15 I2C characteristics ............................................................................................................................ 36 4.16 USART characteristics ..................................................................................................................... 36 Package information ..................................................................................................... 37 5 5.1 QFN package outline dimensions .................................................................................................. 37 6 Ordering Information ..................................................................................................... 38 7 Revision History............................................................................................................. 39 2 / 40 GD32FFPRTGU6 List of Figures Figure 1. GD32FFPRTGU6 block diagram .............................................................................................................. 7 Figure 2. GD32FFPRTGU6 QFN36 pinouts ............................................................................................................ 8 Figure 3. GD32FFPRTGU6 memory map ............................................................................................................... 9 Figure 4. GD32FFPRTGU6 clock tree .................................................................................................................... 13 Figure 5. QFN package outline ................................................................................................................................ 37 3 / 40 GD32FFPRTGU6 List of Tables Table 1. GD32FFPRTGU6 device features and peripheral list ............................................................................. 6 Table 2. GD32FFPRTGU6 pin definitions .............................................................................................................. 14 Table 3. Absolute maximum ratings ........................................................................................................................ 24 Table 4. DC operating conditions ............................................................................................................................ 24 Table 5. Power consumption characteristics ......................................................................................................... 25 Table 6. EMS characteristics ................................................................................................................................... 26 Table 7. EMI characteristics ..................................................................................................................................... 26 Table 8. Power supply supervisor characteristics ................................................................................................. 27 Table 9. ESD characteristics .................................................................................................................................... 27 Table 10. Static latch-up characteristics ................................................................................................................ 27 Table 11. High speed external clock (HXTAL) generated from a crystal/ceramic characteristics.................. 28 Table 12. Low speed external clock (LXTAL) generated from a crystal/ceramic characteristics ................... 28 Table 13. High speed internal clock (IRC8M) characteristics .............................................................................. 29 Table 14. High speed internal clock (IRC48M) characteristics ........................................................................... 29 Table 15. Low speed internal clock (IRC32K) characteristics ............................................................................. 30 Table 16. PLL characteristics ................................................................................................................................... 30 Table 17. PLL2/3 characteristics ............................................................................................................................. 30 Table 18. Flash memory characteristics ................................................................................................................. 31 Table 19. I/O port characteristics ............................................................................................................................. 32 Table 20. ADC characteristics .................................................................................................................................. 33 Table 21. ADC RAIN max for fADC=40MHz ................................................................................................................. 33 Table 22. ADC dynamic accuracy at fADC = 30 MHz ............................................................................................. 34 Table 23. ADC dynamic accuracy at fADC = 30 MHz ............................................................................................. 34 Table 24. ADC dynamic accuracy at fADC = 36 MHz ............................................................................................. 34 Table 25. ADC dynamic accuracy at fADC = 40 MHz ............................................................................................. 34 Table 26. ADC static accuracy at fADC = 15 MHz .................................................................................................. 34 Table 27. DAC characteristics ................................................................................................................................. 35 Table 28. SPI characteristics .................................................................................................................................... 36 Table 29. I2C characteristics .................................................................................................................................... 36 Table 30. USART characteristics ............................................................................................................................ 36 Table 31. QFN package dimensions ....................................................................................................................... 37 Table 32. Part ordering code for GD32FFPRTGU6 device ................................................................................. 38 Table 33. Revision history......................................................................................................................................... 39 4 / 40 GD32FFPRTGU6 1 General description The GD32FFPRTGU6 device belongs to the specific line of GD32 MCU Family. It is a new 32-bit general-purpose microcontroller based on the ARM® Cortex®-M4 RISC core with best cost-performance ratio in terms of enhanced processing capacity, reduced power consumption and peripheral set. The Cortex®-M4 core features implements a full set of DSP instructions to address digital signal control markets that demand an efficient, easy-to-use blend of control and signal processing capabilities. Its single precision FPU (floating point unit) speeds up software development. It also provides a Memory Protection Unit (MPU) and powerful trace technology for enhanced application security and advanced debug support. The GD32FFPRTGU6 device incorporates the ARM® Cortex®-M4 32-bit processor core operating at 168 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up to 1024 KB on-chip Flash memory and 128 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The device offer four general-purpose 16-bit timers, a 16-bit advanced-control timer, two 12-bit 2.6M SPS ADCs, as well as standard and advanced communication interfaces: two USARTs, two SPIs, an I2C and an USB 2.0 FS. The device operates from a 2.6 to 3.6 V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications. The above features make GD32FFPRTGU6 device specifically suitable for advanced fingerprint recognition application. 5 / 40 GD32FFPRTGU6 2 Device overview 2.1 Device information Table 1. GD32FFPRTGU6 device features and peripheral list Flash Part Number Code Area (KB) 256 Data Area (KB) 768 Total (KB) 1024 Timers SRAM (KB) Connectivity GD32FFPRTGU6 128 16-bit GPTM 4 Adv. 16-bit TM 1 SysTick 1 Watchdog 2 RTC 1 USART 2 I2C 1 SPI 2 USB 2.0 FS 1 GPIO 26 EXMC 0 EXTI 16 ADC Unit (CHs) 2(10) Package QFN36 6 / 40 GD32FFPRTGU6 2.2 Block diagram Figure 1. GD32FFPRTGU6 block diagram SW/JTAG TPIU NVIC Flash Memory Controller Ibus Flash Memory PLL F max : 120MHz Dbus FMC Master GP DMA 12 chs Master AHB Matrix ICode DCode System ARM Cortex-M4 Processor Fmax:168MHz POR/ PDR EXMC Slave Slave CRC LDO 1.2V RCU AHB Peripherals Slave Slave SDIO SRAM Controller AHB to APB Bridge2 IRC 8MHz SRAM HXTAL 4-16MHz AHB to APB Bridge1 LVD Interrput request Powered By VDDA USART0 Slave 12-bit SAR ADC Slave SPI0 WWDGT ADC0~1 TIMER1~3 EXTI SPI2 GPIOA USART1 Powered By V DDA APB1: Fmax = 84MHz APB2: Fmax = 168MHz GPIOB I2C0 USB FS FWDGT RTC TIMER4 7 / 40 GD32FFPRTGU6 2.3 Pinouts and pin assignment Figure 2. GD32FFPRTGU6 QFN36 pinouts PA14 PA15 PB3 PB4 PB5 PB6 PB7 BOOT0 VSS_3 36 35 34 33 32 31 30 29 28 1 27 2 26 VDD_2 OSC_OUT/PD1 NRST VSSA 3 25 PA13 4 24 PA12 5 23 PA11 VDDA 6 22 PA10 PA0-WKUP 7 21 PA9 PA1 8 20 9 19 10 11 12 13 14 15 16 17 18 PA8 VDD_3 OSC_IN/PD0 PA2 QFN36 VSS_2 VDD_1 VSS_1 PB2 PB1 PB0 PA7 PA6 PA5 PA4 PA3 8 / 40 GD32FFPRTGU6 2.4 Memory map Figure 3. GD32FFPRTGU6 memory map Pre-defined Regions Bus External device AHB3 External RAM Peripheral AHB1 Address Peripherals 0xA000 0000 - 0xA000 0FFF Reserved 0x9000 0000 - 0x9FFF FFFF Reserved 0x7000 0000 - 0x8FFF FFFF Reserved 0x6000 0000 - 0x6FFF FFFF Reserved 0x5000 0000 - 0x5003 FFFF Reserved 0x4008 0000 - 0x4FFF FFFF Reserved 0x4004 0000 - 0x4007 FFFF Reserved 0x4002 BC00 - 0x4003 FFFF Reserved 0x4002 B000 - 0x4002 BBFF Reserved 0x4002 A000 - 0x4002 AFFF Reserved 0x4002 8000 - 0x4002 9FFF Reserved 0x4002 6800 - 0x4002 7FFF Reserved 0x4002 6400 - 0x4002 67FF Reserved 0x4002 6000 - 0x4002 63FF Reserved 0x4002 5000 - 0x4002 5FFF Reserved 0x4002 4000 - 0x4002 4FFF Reserved 0x4002 3C00 - 0x4002 3FFF Reserved 0x4002 3800 - 0x4002 3BFF Reserved 0x4002 3400 - 0x4002 37FF Reserved 0x4002 3000 - 0x4002 33FF CRC 0x4002 2C00 - 0x4002 2FFF Reserved 0x4002 2800 - 0x4002 2BFF Reserved 0x4002 2400 - 0x4002 27FF Reserved 0x4002 2000 - 0x4002 23FF FMC 0x4002 1C00 - 0x4002 1FFF Reserved 0x4002 1800 - 0x4002 1BFF Reserved 0x4002 1400 - 0x4002 17FF Reserved 0x4002 1000 - 0x4002 13FF RCU 0x4002 0C00 - 0x4002 0FFF Reserved 0x4002 0800 - 0x4002 0BFF Reserved 0x4002 0400 - 0x4002 07FF DMA1 0x4002 0000 - 0x4002 03FF DMA0 0x4001 8400 - 0x4001 FFFF Reserved 0x4001 8000 - 0x4001 83FF Reserved 9 / 40 GD32FFPRTGU6 Pre-defined Regions Bus APB2 APB1 Address Peripherals 0x4001 7C00 - 0x4001 7FFF Reserved 0x4001 7800 - 0x4001 7BFF Reserved 0x4001 7400 - 0x4001 77FF Reserved 0x4001 7000 - 0x4001 73FF Reserved 0x4001 6C00 - 0x4001 6FFF Reserved 0x4001 6800 - 0x4001 6BFF Reserved 0x4001 5C00 - 0x4001 67FF Reserved 0x4001 5800 - 0x4001 5BFF Reserved 0x4001 5400 - 0x4001 57FF Reserved 0x4001 5000 - 0x4001 53FF Reserved 0x4001 4C00 - 0x4001 4FFF Reserved 0x4001 4800 - 0x4001 4BFF Reserved 0x4001 4400 - 0x4001 47FF Reserved 0x4001 4000 - 0x4001 43FF Reserved 0x4001 3C00 - 0x4001 3FFF Reserved 0x4001 3800 - 0x4001 3BFF USART0 0x4001 3400 - 0x4001 37FF Reserved 0x4001 3000 - 0x4001 33FF SPI0 0x4001 2C00 - 0x4001 2FFF Reserved 0x4001 2800 - 0x4001 2BFF ADC1 0x4001 2400 - 0x4001 27FF ADC0 0x4001 2000 - 0x4001 23FF Reserved 0x4001 1C00 - 0x4001 1FFF Reserved 0x4001 1800 - 0x4001 1BFF Reserved 0x4001 1400 - 0x4001 17FF Reserved 0x4001 1000 - 0x4001 13FF Reserved 0x4001 0C00 - 0x4001 0FFF GPIOB 0x4001 0800 - 0x4001 0BFF GPIOA 0x4001 0400 - 0x4001 07FF EXTI 0x4001 0000 - 0x4001 03FF AFIO 0x4000 CC00 - 0x4000 FFFF Reserved 0x4000 C800 - 0x4000 CBFF Reserved 0x4000 C400 - 0x4000 C7FF Reserved 0x4000 C000 - 0x4000 C3FF Reserved 0x4000 8000 - 0x4000 BFFF Reserved 0x4000 7C00 - 0x4000 7FFF Reserved 0x4000 7800 - 0x4000 7BFF Reserved 0x4000 7400 - 0x4000 77FF Reserved 0x4000 7000 - 0x4000 73FF PMU 0x4000 6C00 - 0x4000 6FFF BKP 10 / 40 GD32FFPRTGU6 Pre-defined Regions SRAM Bus AHB Address Peripherals 0x4000 6800 - 0x4000 6BFF Reserved 0x4000 6400 - 0x4000 67FF Reserved 0x4000 6000 - 0x4000 63FF USBD SRAM 512 bytes 0x4000 5C00 - 0x4000 5FFF USBD 0x4000 5800 - 0x4000 5BFF Reserved 0x4000 5400 - 0x4000 57FF I2C0 0x4000 5000 - 0x4000 53FF Reserved 0x4000 4C00 - 0x4000 4FFF Reserved 0x4000 4800 - 0x4000 4BFF Reserved 0x4000 4400 - 0x4000 47FF USART1 0x4000 4000 - 0x4000 43FF Reserved 0x4000 3C00 - 0x4000 3FFF SPI2 0x4000 3800 - 0x4000 3BFF Reserved 0x4000 3400 - 0x4000 37FF Reserved 0x4000 3000 - 0x4000 33FF FWDGT 0x4000 2C00 - 0x4000 2FFF WWDGT 0x4000 2800 - 0x4000 2BFF RTC 0x4000 2400 - 0x4000 27FF Reserved 0x4000 2000 - 0x4000 23FF Reserved 0x4000 1C00 - 0x4000 1FFF Reserved 0x4000 1800 - 0x4000 1BFF Reserved 0x4000 1400 - 0x4000 17FF Reserved 0x4000 1000 - 0x4000 13FF Reserved 0x4000 0C00 - 0x4000 0FFF TIMER4 0x4000 0800 - 0x4000 0BFF TIMER3 0x4000 0400 - 0x4000 07FF TIMER2 0x4000 0000 - 0x4000 03FF TIMER1 0x2007 0000 - 0x3FFF FFFF Reserved 0x2006 0000 - 0x2006 FFFF Reserved 0x2003 0000 - 0x2005 FFFF Reserved 0x2002 0000 - 0x2002 FFFF Reserved 0x2001 C000 - 0x2001 FFFF Reserved 0x2001 8000 - 0x2001 BFFF 0x2000 5000 - 0x2001 7FFF SRAM 0x2000 0000 - 0x2000 4FFF Code AHB 0x1FFF F810 - 0x1FFF FFFF Reserved 0x1FFF F800 - 0x1FFF F80F Option Bytes 0x1FFF F000 - 0x1FFF F7FF 0x1FFF C010 - 0x1FFF EFFF Boot loader 0x1FFF C000 - 0x1FFF C00F 11 / 40 GD32FFPRTGU6 Pre-defined Regions Bus Address Peripherals 0x1FFF B000 - 0x1FFF BFFF 0x1FFF 7A10 - 0x1FFF AFFF Reserved 0x1FFF 7800 - 0x1FFF 7A0F Reserved 0x1FFF 0000 - 0x1FFF 77FF Reserved 0x1FFE C010 - 0x1FFE FFFF Reserved 0x1FFE C000 - 0x1FFE C00F Reserved 0x1001 0000 - 0x1FFE BFFF Reserved 0x1000 0000 - 0x1000 FFFF Reserved 0x083C 0000 - 0x0FFF FFFF Reserved 0x0830 0000 - 0x083B FFFF Reserved 0x0810 0000 - 0x082F FFFF 0x0802 0000 - 0x080F FFFF Main Flash 0x0800 0000 - 0x0801 FFFF 0x0030 0000 - 0x07FF FFFF Reserved 0x0010 0000 - 0x002F FFFF 0x0002 0000 - 0x000F FFFF 0x0000 0000 - 0x0001 FFFF Aliased to Main Flash or Boot loader 12 / 40 GD32FFPRTGU6 2.5 Clock tree Figure 4. GD32FFPRTGU6 clock tree CTC CK_IRC48M CK_CTC 48 MHz IRC48M 48 MHz CK48MSEL USBD Prescaler 1,1.5,2,2.5 3,3.5,4 1 SCS[1:0] CK_USBD 0 (to USBD) CK_I2S CK_IRC8M 8 MHz IRC8M 1 I2S enable (by hardware) 00 0 /2 1 PLLPRESEL CK_IRC48M 1 ×2,3,4 …63 PLL PLLSEL PLLMF CK_PLL 10 CK_SYS 120 MHz max AHB Prescaler ÷1,2...512 CK_AHB 120 MHz max (to I2S1,2) CK_EXMC EXMC enable (by hardware) (to EXMC) HCLK 01 AHB enable (to AHB bus,Cortex-M4,SRAM,DMA,FMC) /1 or /2 CK_CST Clock Monitor 0 4-16 MHz HXTAL ÷8 (to Cortex-M4 SysTick) PREDV0 FCLK (free running clock) CK_HXTAL CK_SDIO SDIO enable (by hardware) APB1 Prescaler ÷1,2,4,8,16 (to SDIO) CK_APB1 PCLK1 to APB1 peripherals 60 MHz max Peripheral enable /128 TIMER1,2,3,4,5,6, 11,12,13 if(APB1 prescale =1)x1 else x 2 11 32.768 KHz LXTAL CK_TIMERx TIMERx enable to TIMER1,2,3,4, 5,6,11,12,13 CK_RTC 01 (to RTC) 10 APB2 Prescaler ÷1,2,4,8,16 CK_APB2 PCLK2 to APB2 peripherals 120 MHz max Peripheral enable RTCSRC[1:0] 40 KHz IRC40K CK_FWDGT (to FWDGT) CK_OUT0 0xx 100 101 110 111 NO CLK CK_SYS CK_IRC8M CK_HXTAL /2 CK_PLL CKOUT0SEL[2:0] TIMER0,7,8,9,10 if(APB2 prescale =1)x1 else x 2 ADC Prescaler ÷2,4,6,8,12,1 6 ADC Prescaler ÷5,6,10,20 CK_TIMERx TIMERx enable to TIMER0,7,8,9,10 ADCPSC[3] 0 1 CK_ADCx to ADC0,1,2 40 MHz max Legend: HXTAL: High speed crystal oscillator LXTAL: Low speed crystal oscillator IRC8M: Internal 8M RC oscillators IRC48M: Internal 48M RC oscillators IRC32K: Internal 32K RC oscillator 13 / 40 GD32FFPRTGU6 2.6 Pin definitions Pin Name Pins Pin Type(1) I/O(2) Level Table 2. GD32FFPRTGU6 pin definitions OSC_IN 2 I Default: OSC_IN OSC_OUT 3 O Default: OSC_OUT NRST 4 I/O Default: NRST VSSA 5 P Default: VSSA VDDA 6 P Default: VDDA Functions description Default: PA0 PA0-WKUP 7 I/O Alternate: WKUP, USART1_CTS, ADC012_IN0, TIMER1_CH0_ETI, TIMER4_CH0 PA1 8 I/O PA2 9 I/O PA3 10 I/O Default: PA1 Alternate: USART1_RTS, ADC012_IN1, TIMER1_CH1, TIMER4_CH1 Default: PA2 Alternate: USART1_TX, ADC012_IN2, TIMER1_CH2, TIMER4_CH2, SPI0_IO2 Default: PA3 Alternate: USART1_RX, ADC012_IN3, TIMER1_CH3, TIMER4_CH3, SPI0_IO3 Default: PA4 PA4 11 I/O Alternate: SPI0_NSS, USART1_CK, ADC01_IN4 Remap:SPI2_NSS PA5 12 I/O Default: PA5 Alternate: SPI0_SCK, ADC01_IN5 Default: PA6 PA6 13 I/O Alternate: SPI0_MISO, ADC01_IN6, TIMER2_CH0 Remap: TIMER0_BKIN Default: PA7 PA7 14 I/O Alternate: SPI0_MOSI, ADC01_IN7, TIMER2_CH1 Remap: TIMER0_CH0_ON Default: PB0 PB0 15 I/O Alternate: ADC01_IN8, TIMER2_CH2 Remap: TIMER0_CH1_ON Default: PB1 PB1 16 I/O Alternate: ADC01_IN9, TIMER2_CH3 Remap: TIMER0_CH2_ON I/O 5VT Default: PB2, BOOT1 PB2 17 VSS_1 18 P Default: VSS_1 VDD_1 19 P Default: VDD_1 PA8 20 I/O 5VT PA9 21 I/O 5VT Default: PA8 Alternate: USART0_CK, TIMER0_CH0, CK_OUT0, VCORE, CTC_SYNC Default: PA9 Alternate: USART0_TX, TIMER0_CH1 14 / 40 Pin Name Pins Pin Type(1) I/O(2) Level GD32FFPRTGU6 PA10 22 I/O 5VT PA11 23 I/O 5VT PA12 24 I/O 5VT PA13 25 I/O 5VT VSS_2 26 P Default: VSS_2 VDD_2 27 P Default: VDD_2 PA14 28 I/O 5VT Functions description Default: PA10 Alternate: USART0_RX, TIMER0_CH2 Default: PA11 Alternate: USART0_CTS, USBDM, TIMER0_CH3 Default: PA12 Alternate: USART0_RTS, TIMER0_ETI, USBDP Default: JTMS, SWDIO Remap: PA13 Default: JTCK, SWCLK Remap: PA14 Default: JTDI PA15 29 I/O 5VT Alternate: SPI2_NSS Remap: TIMER1_CH0_ETI, PA15, SPI0_NSS Default: JTDO PB3 30 I/O 5VT Alternate:SPI2_SCK Remap: PB3, TRACESWO, TIMER1_CH1, SPI0_SCK Default: NJTRST PB4 31 I/O 5VT Alternate: SPI2_MISO Remap: TIMER2_CH0, PB4, SPI0_MISO Default: PB5 PB5 32 I/O Alternate: I2C0_SMBA, SPI2_MOSI, I2S2_SD Remap: TIMER2_CH1, SPI0_MOSI Default: PB6 PB6 33 I/O 5VT Alternate: I2C0_SCL, TIMER3_CH0 Remap: USART0_TX, SPI0_IO2 Default: PB7 I/O 5VT Alternate: I2C0_SDA , TIMER3_CH1 PB7 34 BOOT0 35 I Default: BOOT0 VSS_3 36 P Default: VSS_3 VDD_3 1 P Default: VDD_3 Remap: USART0_RX, SPI0_IO3 Notes: 1. Type: I = input, O = output, P = power. 2. I/O Level: 5VT = 5 V tolerant. 15 / 40 GD32FFPRTGU6 3 Functional description 3.1 ARM® Cortex®-M4 core The ARM® Cortex®-M4 processor is a high performance embedded processor with DSP instructions which allow efficient signal processing and complex algorithm execution. It brings an efficient, easy-to-use blend of control and signal processing capabilities to meet the digital signal control markets demand. The processor is highly configurable enabling a wide range of implementations from those requiring memory protection and powerful trace technology to cost sensitive device requiring minimal area, while delivering outstanding computational performance and an advanced system response to interrupts. 32-bit ARM® Cortex®-M4 processor core  Up to 168 MHz operation frequency  Single-cycle multiplication and hardware divider  Floating Point Unit (FPU)  Integrated DSP instructions  Integrated Nested Vectored Interrupt Controller (NVIC)  24-bit SysTick timer The Cortex®-M4 processor is based on the ARMv7-M architecture and supports both Thumb and Thumb-2 instruction sets. Some system peripherals listed below are also provided by Cortex®-M4:  Internal Bus Matrix connected with ICode bus, DCode bus, system bus, Private Peripheral Bus (PPB) and debug accesses (AHB-AP)  Nested Vectored Interrupt Controller (NVIC)  Flash Patch and Breakpoint (FPB)  Data Watchpoint and Trace (DWT)  Instrument Trace Macrocell (ITM)  Memory Protection Unit (MPU)  Serial Wire JTAG Debug Port (SWJ-DP)  Trace Port Interface Unit (TPIU) 16 / 40 GD32FFPRTGU6 3.2 On-chip memory  Up to 1024 Kbytes of Flash memory, including code Flash and data Flash  Up to 128 KB of SRAM The ARM® Cortex®-M4 processor is structured in Harvard architecture which can use separate buses to fetch instructions and load/store data. 1024 Kbytes of inner Flash at most, which includes code Flash that available for storing programs and data, and accessed (R/W) at CPU clock speed with zero wait states. An extra data Flash is also included for storing data mainly. The Figure of GD32FFPRTGU6 memory map shows the memory of the GD32FFPRTGU6 series of device, including Flash, SRAM, peripheral, and other pre-defined regions. 3.3 Clock, reset and supply management  Internal 8 MHz factory-trimmed RC and external 4 to 32 MHz crystal oscillator  Internal 48 MHz RC oscillator  Internal 32 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator  2.6 to 3.6 V application supply and I/Os  Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage detector (LVD) The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These include internal RC oscillator and external crystal oscillator, high speed and low speed two types. Several prescalers allow the frequency configuration of the AHB and two APB domains. The maximum frequency of the two AHB domains are 120 MHz. The maximum frequency of the two APB domains including APB1 is 60 MHz and APB2 is 120 MHz. See Figure 6 for details on the clock tree. The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from/down to 2.6 V. The device remains in reset mode when VDD is below a specified threshold. The embedded low voltage detector (LVD) monitors the power supply, compares it to the voltage threshold and generates an interrupt as a warning message for leading the MCU into security. Power supply schemes:  VDD range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator. Provided externally through VDD pins.  VSSA, VDDA range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.  VBAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. 17 / 40 GD32FFPRTGU6 3.4 Boot modes At startup, boot pins are used to select one of three boot options:  Boot from main flash memory (default)  Boot from system memory  Boot from on-chip SRAM The boot loader is located in the internal boot ROM memory (system memory). It is used to reprogram the Flash memory by using USART0, USART1 in device mode. It also can be used to transfer and update the Flash memory code, the data and the vector table sections. In default condition, boot from bank 1 of Flash memory is selected. It also supports to boot from bank 2 of Flash memory by setting a bit in option bytes. 3.5 Power saving modes The MCU supports three kinds of power saving modes to achieve even lower power consumption. They are Sleep mode, Deep-sleep mode, and Standby mode. These operating modes reduce the power consumption and allow the application to achieve the best balance between the CPU operating time, speed and power consumption.  Sleep mode In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and any interrupt/event can wake up the system.  Deep-sleep mode In Deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed crystal oscillator (IRC8M, HXTAL) and PLL are disabled. Only the contents of SRAM and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the system from the Deep-sleep mode including the 23 external lines, the RTC alarm, the LVD output, and USB wakeup. When exiting the Deep-sleep mode, the IRC8M is selected as the system clock.  Standby mode In Standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of IRC8M, HXTAL and PLL are disabled. The contents of SRAM and registers (except Backup Registers) are lost. There are four wakeup sources for the Standby mode, including the external reset from NRST pin, the RTC, the FWDG reset, and the rising edge on WKUP pin. 18 / 40 GD32FFPRTGU6 3.6 Analog to digital converter (ADC)  12-bit SAR ADC's conversion rate is up to 2.6MSPS  12-bit, 10-bit, 8-bit or 6-bit configurable resolution  Hardware oversampling ratio adjustable from 2 to 256x improves resolution to 16-bit  Input voltage range: VSSA to VDDA (2.6 to 3.6 V)  Temperature sensor Two 12-bit 2.6MSPS multi-channel ADCs are integrated in the device. It has a total of 12 multiplexed channels: 10 external channels, 1 channel for internal temperature sensor (VSENSE), 1 channel for internal reference voltage (VREFINT). The input voltage range is between 2.6 V and 3.6 V. An on-chip hardware oversampling scheme improves performance while offloading the related computational burden from the CPU. An analog watchdog block can be used to detect the channels, which are required to remain within a specific threshold window. A configurable channel management block can be used to perform conversions in single, continuous, scan or discontinuous mode to support more advanced use. The ADC can be triggered from the events generated by the general-purpose level 0 timers (TMx) and the advanced-control timers (TM0) with internal connection. The temperature sensor can be used to generate a voltage that varies linearly with temperature. It is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage in a digital value. 3.7 DMA  7 channel DMA 0 controller and 5 channel DMA 1 controller  Peripherals supported: Timers, ADC, SPIs, I2C, USARTs The flexible general-purpose DMA controllers provide a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Four types of access method are supported: peripheral to peripheral, peripheral to memory, memory to peripheral, memory to memory Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel requests are determined by software configuration and hardware channel number. Transfer size of source and destination are independent and configurable. 3.8 General-purpose inputs/outputs (GPIOs)  Up to 26 fast GPIOs, all mappable on 16 external interrupt vectors (EXTI)  Analog input/output configurable  Alternate function input/output configurable There are up to 26 general purpose I/O pins (GPIO) in GD32FFPRTGU6, named PA0 ~ PA15 19 / 40 GD32FFPRTGU6 and PB0 ~ PB7, to implement logic input/output functions. Each of the GPIO ports has related control and configuration registers to satisfy the requirements of specific applications. The external interrupts on the GPIO pins of the device have related control and configuration registers in the External Interrupt Control Unit (EXTI). The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility on the package pins. Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current capable except for analog inputs. 3.9 Timers and PWM generation  A 16-bit advanced-control timer (TM0), four 16-bit general-purpose timers (TM1 ~ TM4)  Up to 4 independent channels of PWM, output compare or input capture for each generalpurpose timer (GPTM) and external trigger input  16-bit, motor control PWM advanced-control timer with programmable dead-time generation for output match  Encoder interface controller with two inputs using quadrature decoder  24-bit SysTick timer down counter  2 watchdog timers (Free watchdog and window watchdog) The advanced-control timer (TM0) can be used as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable dead-time generation. It can also be used as a complete general-purpose timer. The 4 independent channels can be used for input capture, output compare, PWM generation (edge- or center-aligned counting modes) and single pulse mode output. If configured as a general-purpose 16-bit timer, it has the same functions as the TMx timer. It can be synchronized with external signals or to interconnect with other GPTMs together which have the same architecture and features. The general-purpose timer (GPTM), can be used for a variety of purposes including general time, input signal pulse width measurement or output waveform generation such as a single pulse generation or PWM output, up to 4 independent channels for input capture/output compare. TM1 ~ TM4 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. The GPTM also supports an encoder interface with two inputs using quadrature decoder. The GD32FFPRTGU6 have two watchdog peripherals, Independent watchdog and window watchdog. They offer a combination of high safety level, flexibility of use and timing accuracy. The independent watchdog timer includes a 12-bit down-counting counter and a 8-bit prescaler, It is clocked from an independent 40 kHz internal RC and as it operates independently of the main clock, it can operate in stop and standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. The window watchdog is based on a 7-bit down counter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the 20 / 40 GD32FFPRTGU6 main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. The SysTick timer is dedicated for OS, but could also be used as a standard down counter. It features: 3.10  A 24-bit down counter  Auto reload capability  Maskable system interrupt generation when the counter reaches 0  Programmable clock source Real time clock (RTC)  32-bit up-counter with a programmable 20-bit prescaler  Alarm function  Interrupt and wake-up event The real time clock is an independent timer which provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and an expected interrupt. The RTC features a 32-bit programmable counter for long-term measurement using the compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz from external crystal oscillator. 3.11 Inter-integrated circuit (I2C)  An I2C bus interfaces can support both master and slave mode with a frequency up to 1 MHz (Fast mode plus)  Provide arbitration function, optional PEC (packet error checking) generation and checking  Supports 7-bit and 10-bit addressing mode and general call addressing mode The I2C interface is an internal circuit allowing communication with an external I2C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line (SCL). The I2C module provides several data transfer rates: 100 KHz of standard mode, 400 KHz of the fast mode and 1 MHz of the fast mode plus . The I2C module also has an arbitration detect function to prevent the situation where more than one master attempts to transmit data to the I2C bus at the same time. A CRC-8 calculator is also provided in I2C interface to perform packet error checking for I2C data. 21 / 40 GD32FFPRTGU6 3.12 Serial peripheral interface (SPI)  Two SPI interfaces with a frequency of up to 30 MHz  Support both master and slave mode  Hardware CRC calculation and transmit automatic CRC error checking The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO & MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by the DMA controller. The SPI interface may be used for a variety of purposes, including simplex synchronous transfers on two lines with a possible bidirectional data line or reliable communication using CRC checking. 3.13 Universal synchronous asynchronous receiver transmitter (USART)  Two USARTs with operating frequency up to 10.5 MHz  Supports both asynchronous and clocked synchronous serial communication modes  IrDA SIR encoder and decoder support  LIN break generation and detection  USARTs support ISO 7816-3 compliant smart card interface The USARTs (USART0, USART1) are used to translate data between parallel and serial interfaces, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232 standard communication. The USART includes a programmable baud rate generator which is capable of dividing the system clock to produce a dedicated clock for the USART transmitter and receiver. The USART also supports DMA function for high speed data communication. 3.14 Universal serial bus full-speed (USB 2.0 FS)  One full-speed USB Interface with frequency up to 12 Mbit/s  Internal 48 MHz oscillator support crystal-less operation  Internal main PLL for USB CLK compliantly The Universal Serial Bus (USB) is a 4-wire bus with 4 bidirectional endpoints. The device controller enables 12 Mbit/s data exchange with integrated transceivers. Transaction formatting is performed by the hardware, including CRC generation and checking. It supports device modes. Transaction formatting is performed by the hardware, including CRC generation and checking. The status of a completed USB transfer or error condition is indicated by status registers. An interrupt is also generated if enabled. The required precise 48 MHz clock which can be generated from the internal main PLL (the clock source must use an HXTAL crystal oscillator) or by the internal 48 MHz oscillator in automatic trimming mode that allows crystal-less operation. 22 / 40 GD32FFPRTGU6 3.15 Debug mode  Serial wire JTAG debug port (SWJ-DP) The ARM® SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. 3.16 Package and operation temperature  QFN36  Operation temperature range: -40°C to +85°C (industrial level) 23 / 40 GD32FFPRTGU6 4 Electrical characteristics 4.1 Absolute maximum ratings The maximum ratings are the limits to which the device can be subjected without permanently damaging the device. Note that the device is not guaranteed to operate properly at the maximum ratings. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Table 3. Absolute maximum ratings Symbol Min Max Unit VDD External voltage range VSS - 0.3 VSS + 3.6 V VDDA External analog supply voltage VSSA - 0.3 VSSA + 3.6 V VBAT External battery supply voltage VSS - 0.3 VSS + 3.6 V Input voltage on 5V tolerant pin VSS - 0.3 VDD + 4.0 V Input voltage on other I/O VSS - 0.3 4.0 V Variations between different VDD power pins — 50 mV Variations between different ground pins — 50 mV IIO Maximum current for GPIO pins — 25 mA TA Operating temperature range -40 +85 °C Storage temperature range -55 +150 °C Maximum junction temperature — 125 °C VIN |ΔVDDx| |VSSX −VSS| TSTG TJ 4.2 Parameter Recommended DC characteristics Table 4. DC operating conditions Symbol Parameter Conditions Min Typ Max Unit VDD Supply voltage — 2.6 3.3 3.6 V VDDA Analog supply voltage Same as VDD 2.6 3.3 3.6 V VBAT Battery supply voltage — 1.8 — 3.6 V 24 / 40 GD32FFPRTGU6 4.3 Power consumption The power measurements specified in the tables represent that code with data executing from on-chip Flash with the following specifications. Table 5. Power consumption characteristics Symbol Parameter Conditions VDD=VDDA=3.3V, HXTAL=25MHz, System Min Typ Max Unit — 64.0 — mA — 33.5 — mA -— 42.5 — mA — 22.5 — mA — 44.9 — mA — 13.86 — mA — 208 — μA — 180 — μA — 5.10 — μA — 4.90 — μA — 4.30 — μA — 1.78 — μA — 1.48 — μA — 1.16 — μA — 1.11 — μA clock=168MHz, All peripherals enabled VDD=VDDA=3.3V, HXTAL =25MHz, System Supply current clock =168MHz, All peripherals disabled (Run mode) VDD=VDDA=3.3V, HXTAL =25MHz, System clock =108MHz, All peripherals enabled VDD=VDDA=3.3V, HXTAL =25MHz, System Clock =108MHz, All peripherals disabled VDD=VDDA=3.3V, HXTAL =25MHz, CPU clock off, System clock=168MHz, All Supply current peripherals enabled (Sleep mode) VDD=VDDA=3.3V, HXTAL =25MHz, CPU clock off, System clock=168MHz, All IDD peripherals disabled VDD=VDDA=3.3V, Regulator in run mode, Supply current (Deep-Sleep mode) IRC32K on, RTC on, All GPIOs analog mode VDD=VDDA=3.3V, Regulator in low power mode, IRC32K on, RTC on, All GPIOs analog mode VDD=VDDA=3.3V, LXTAL off, IRC32K on, RTC on Supply current VDD=VDDA=3.3V, LXTAL off, IRC32K on, (Standby mode) RTC off VDD=VDDA=3.3V, LXTAL off, IRC32K off, RTC off VDD not available, VBAT=3.6 V, LXTAL on with external crystal, RTC on, Higher driving VDD not available, VBAT=3.3 V, LXTAL on with external crystal, RTC on, Higher IBAT Battery supply current driving VDD not available, VBAT=2.6 V, LXTAL on with external crystal, RTC on, Higher driving VDD not available, VBAT=3.6 V, LXTAL on with external crystal, RTC on, Lower driving 25 / 40 GD32FFPRTGU6 Symbol Parameter Conditions Min Typ — 0.83 — μA — 0.51 — μA VDD not available, VBAT=3.3 V, LXTAL on with external crystal, RTC on, Lower driving VDD not available, VBAT=2.6 V, LXTAL on with external crystal, RTC on, Lower driving 4.4 Max Unit EMC characteristics EMS (electromagnetic susceptibility) includes ESD (Electrostatic discharge, positive and negative) and FTB (Burst of Fast Transient voltage, positive and negative) testing result is given in the following table, based on the EMS levels and classes compliant with IEC 61000 series standard. Table 6. EMS characteristics Symbol VESD Parameter Conditions Voltage applied to all device pins to VDD = 3.3 V, TA = +25 °C induce a functional disturbance conforms to IEC 61000-4-2 Fast transient voltage burst applied to VFTB induce a functional disturbance through 100 pF on VDD and VSS pins Level/Class 3B VDD = 3.3 V, TA = +25 °C 4A conforms to IEC 61000-4-4 EMI (Electromagnetic Interference) emission testing result is given in the following table, compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 7. EMI characteristics Symbol Parameter Conditions VDD = 5.0 V, SEMI Peak level TA = +25 °C, compliant with IEC 61967-2 Tested frequency band Conditions Unit 24M 48M 0.1 to 2 MHz