SILICON CONTENT
TECHNOLOGY
SCT2339
3.8V-32V Vin, 3A Synchronous Step-down DCDC Converter with EMI Reduction
FEATURES
DESCRIPTION
EMI Reduction with Switching Node Ringing-free
400kHz Switching Frequency
Pulse Skipping Mode PSM with 20uA Quiescent
Current in Light Load Condition
3.8V-32V Wide Input Voltage Range
Up to 3A Continuous Output Load Current
0.8V ±1% Feedback Reference Voltage
Fully Integrated 80mΩ Rdson High Side MOSFET
and 42mΩ Rdson Low Side MOSFET
1uA Shut-down Current
80ns Minimum On-time
Precision Enable Threshold for Programmable
UVLO Threshold and Hysteresis
Low Drop out (LDO) Mode Operation
4ms Built-in Soft Start Time
Output Over Voltage Protection
Thermal Shutdown Protection at 160°C
Available in TSOT23-6L Package
The SCT2339 is 3A synchronous buck converters with
up to 32V wide input voltage range, which fully
integrates an 80mΩ high-side MOSFET and a 42mΩ
low-side MOSFET to provide high efficiency step-down
DCDC conversion. The SCT2339 adopts peak current
mode control with the integrated compensation
network, which makes SCT2339 easily to be used by
minimizing the off-chip component count. The
SCT2339 supports the Pulse Skipping Modulation
(PSM) with typical 20uA Ultra-Low Quiescent.
The SCT2339 offers output over-voltage protection,
cycle-by-cycle peak current limit, and thermal
shutdown protection. The device is available in a lowprofile TSOT23-6 package.
APPLICATIONS
White Goods, Home Appliance
Surveillance
Audio, WiFi Speaker
Printer, Charging Station
DTV, STB, Monitor/LCD Display
TYPICAL APPLICATION
100
R1
90
FB
R2
ON
OFF
VIN
BST
C2
L1
VOUT
EN
SW
VIN
GND
C3
C1
Efficiency (%)
80
R3
70
60
50
40
12VIN,3.3VOUT
30
12VIN, 5VOUT
20
24VIN, 3.3VOUT
10
24VIN, 5VOUT
0
1
10
100
1,000
10,000
Output Current (mA)
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1
SCT2339
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Revision 1.0: Release to Market
DEVICE ORDER INFORMATION
PART NUMBER
PACKAGE MARKING
PACKAGE DISCRIPTION
SCT2339TVB
2339
TSOT23-6L
1)
For Tape & Reel, Add Suffix R (e.g. SCT2339TVBR)
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
Over operating free-air temperature unless otherwise noted(1)
(1)
(2)
DESCRIPTION
MIN
MAX
UNIT
BST
-0.3
40
V
VIN, SW, EN
-0.3
34
VS, FB
-0.3
Operating junction temperature(2)
Storage temperature TSTG
FB
1
6
BST
V
EN
2
5
SW
5.5
V
VIN
3
4
GND
-40
125
C
-65
150
C
Top View: TSOT23-6L, Plastic
Stresses beyond those listed under Absolute Maximum Rating may cause device permanent damage. The device is not guaranteed to
function outside of its Recommended Operation Conditions.
The IC includes over temperature protection to protect the device during overload conditions. Junction temperature will exceed 150°C
when over temperature protection is active. Continuous operation above the specified maximum operating junction temperature will
reduce lifetime.
PIN FUNCTIONS
NAME
NO.
FB
1
Buck converter output feedback sensing voltage. Connect a resistor divider from
VOUT to FB to set up output voltage. The device regulates FB to the internal
reference of 0.8V typical.
EN
2
Enable logic input. Floating the pin enables the device. This pin supports high voltage
input up to VIN supply to be connected VIN directly to enable the device
automatically. The device has precision enable thresholds 1.18V rising / 1.1V falling
for programmable UVLO threshold and hysteresis.
VIN
3
Power supply input. Must be locally bypassed.
GND
4
Power ground. Must be soldered directly to ground plane.
SW
5
Switching node of the buck converter.
BST
6
Power supply for the high-side power MOSFET gate driver. Must connect a 0.1uF or
greater ceramic capacitor between BST pin and SW node.
2
PIN FUNCTION
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SCT2339
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range unless otherwise noted
PARAMETER
DEFINITION
VIN
TJ
Input voltage range
Operating junction temperature
MIN
MAX
UNIT
3.8
-40
32
125
V
°C
MIN
MAX
UNIT
-2
+2
kV
-0.5
+0.5
kV
ESD RATINGS
PARAMETER
DEFINITION
Human Body Model(HBM), per ANSI-JEDEC-JS-0012014 specification, all pins(1)
Charged Device Model(CDM), per ANSI-JEDEC-JS-0022014specification, all pins(1)
VESD
(1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.
THERMAL INFORMATION
PARAMETER
RθJA
RθJC
THERMAL METRIC
TSOT23-6L
Junction to ambient thermal resistance(1)
Junction to case thermal
UNIT
89
resistance(1)
°C/W
39
(1) SCT provides RθJA and RθJC numbers only as reference to estimate junction temperatures of the devices. RθJA and RθJC are not a
characteristic of package itself, but of many other system level characteristics such as the design and layout of the printed circuit
board (PCB) on which the SCT2339 is mounted. The PCB board is a heat sink that is soldered to the leads and thermal pad of the
SCT2339. Changing the design or configuration of the PCB board changes the efficiency of the heat sink and therefore the actual RθJA
and RθJC.
ELECTRICAL CHARACTERISTICS
VIN=12V, TJ=-40°C~125°C, typical value is tested under 25°C.
SYMBOL
PARAMETER
TEST CONDITION
Power Supply and Output
VIN
Operating input voltage
ISD
Input UVLO
Hysteresis
Shutdown current
IQ
Quiescent current
VIN_UVLO
MIN
TYP
3.8
VIN rising
3.5
420
1
EN=0, No load, VIN=12V
EN=floating, No load, No
switching. VIN=12V. BSTSW=5V
1.18
Enable low threshold
IEN
Enable pin input current
EN=1V
IEN_HYS
Enable pin hysteresis current
EN=1.5V
1.03
1.1
1
1.5
UNIT
32
V
3.7
V
mV
uA
3
20
Enable, Soft Start and Working Modes
VEN_H
Enable high threshold
VEN_L
MAX
uA
1.25
V
V
2
uA
4
uA
Power MOSFETs
RDSON_H
High side FET on-resistance
80
mΩ
RDSON_L
42
mΩ
Low side FET on-resistance
Feedback and Error Amplifier
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3
SCT2339
SYMBOL
PARAMETER
VFB
Feedback Voltage
TEST CONDITION
Current Limit
ILIM_HSD
HSD peak current limit
ILIM_LSD
LSD valley current limit
Switching Frequency
FSW
Switching frequency
tON_MIN
VIN=12V, VOUT=5V
Minimum on-time
MIN
TYP
MAX
UNIT
0.792
0.8
0.808
V
4
4.5
5
A
3.2
4
4.8
A
360
400
440
kHz
80
ns
4
ms
Soft Start Time
tSS
Internal soft-start time
Protection
VOVP
THIC_W
THIC_R
TSD
4
Output OVP threshold
Hysteresis
OCP hiccup wait time
OCP hiccup restart time
Thermal shutdown threshold
Hysteresis
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VOUT rising
TJ rising
110
5
512
8192
160
25
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%
%
Cycles
Cycles
°C
SCT2339
TYPICAL CHARACTERISTICS
100
100
90
90
80
80
70
Efficiency (%)
Efficiency (%)
70
60
50
40
60
50
40
30
30
20
10
24VIN, 3.3VOUT
20
12VIN,3.3VOUT
24VIN, 5VOUT
10
12VIN, 5VOUT
0
0
1
10
100
1,000
1
10,000
10
100
Output Current (mA)
10,000
Figure 2. Efficiency vs Load Current, Vin=12V
Figure 1. Efficiency vs Load Current, Vin=24V
2.0
50
40
Iq (uA)
1.5
I_SD (uA))
1,000
Output Current (mA)
1.0
0.5
30
20
10
0.0
0
-50
0
50
100
150
-50
0
50
Temperature (°C)
100
150
Temperature (°C)
Figure 4. Quiescent Current vs Temperature
Figure 3. Shut-down Current vs Temperature
0.900
5.0
0.850
VREF (V)
4.0
0.800
3.0
0.750
ILIM HSD
ILIM LSD
0.700
2.0
-50
0
50
100
150
-50
Temperature (°C)
0
50
100
Temperature (°C)
Figure 5. Reference Voltage vs Temperature
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Figure 6.Peak Current Limit vs Temperature
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5
SCT2339
0
3.60
-1
-2
Ien (uA)
VIN (V)
3.40
3.20
-3
Ien_1V
Ien_1.5V
-4
3.00
-5
UVLO RISING
UVLO FALLING
-6
2.80
-50
0
50
100
-50
150
0
50
100
150
Temperature (°C)
Temperature (°C)
Figure 8. EN Pull-up Current vs Temperature
Figure 7． VIN UVLO vs Temperature
3.35
5.05
Output Voltage (V)
Output Voltage (V)
5.00
3.30
3.25
4.95
4.90
4.85
3.20
0
500
1,000
1,500
2,000
2,500
3,000
Figure 9. Load Regulation, Vout=3.3V
6
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5
10
15
20
25
30
Input Voltage (V)
Output Current (mA)
Figure 10. Line Regulation, Iout=3A
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35
SCT2339
FUNCTIONAL BLOCK DIAGRAM
VIN
3
4uA
1.5uA
UVLO
20K
EN
2
+
VIN UVLO
and LDO
EN
VCC
1.21V
VCC
HS MOSFET
Current Limit
BOOT
UVLO
Ramp
SS/4ms
+
+ GM
0.8V
FB
1
COMP
BOOT
Strap
PWM
+
6
BST
5
SW
4
GND
Q1
18k
PWM and Dead
Time Control
Logic
7.6nF
+
OVP
0.88V
Q2
Oscillator
with PLL
CLK
Thermal
Protection
LS MOSFET
Current Limit
Figure 11. Functional Block Diagram
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7
SCT2339
OPERATION
Overview
The SCT2339 device is 3.8V-32V input, 3A output, EMI friendly, fully integrated synchronous buck converters. The
device employs fixed frequency peak current mode control. An internal clock with 400kHz frequency initiates turning
on the integrated high-side power MOSFET Q1 in each cycle, then inductor current rises linearly and the converter
charges output cap. When sensed voltage on high-side MOSFET peak current rising above the voltage of internal
COMP (see functional block diagram), the device turns off high-side MOSFET Q1 and turns on low-side MOSFET
Q2. The inductor current decreases when MOSFET Q2 is ON. In the next rising edge of clock cycle, the low-side
MOSFET Q2 turns off. This repeats on cycle-by-cycle based.
The peak current mode control with the internal loop compensation network and the built-in 4ms soft-start simplify
the SCT2339 footprints and minimize the off-chip component counts.
The error amplifier serves the COMP node by comparing the voltage on the FB pin with an internal 0.8V reference
voltage. When the load current increases, a reduction in the feedback voltage relative to the reference raises COMP
voltage till the average inductor current matches the increased load current. This feedback loop well regulates the
output voltage. The device also integrates an internal slope compensation circuitry to prevent sub-harmonic
oscillation when duty cycle is greater than 50% for a fixed frequency peak current mode control.
The quiescent current of SCT2339 is 20uA typical under no-load condition and no switching. When disabling the
device, the supply shut down current is only 1μA. The SCT2339 works at Pulse Skipping Mode PSM to further
increase the power efficiency in light load condition, hence the power efficiency can be achieved up to 88% at 5mA
load condition.
The hiccup mode minimizes power dissipation during prolonged output overcurrent or short conditions. The hiccup
wait time is 512 cycles and the hiccup restart time is 8192 cycles. The SCT2339 device also features protections
including cycle-by-cycle high-side MOSFET peak current limit, over-voltage protection, and over-temperature
protection.
VIN Power
The SCT2339 is designed to operate from an input voltage supply range between 3.8V to 32V, at least 0.1uF
decoupling ceramic cap is recommended to bypass the supply noise. If the input supply locates more than a few
inches from the converter, an additional electrolytic or tantalum bulk capacitor or with recommended 22uF may be
required in addition to the local ceramic bypass capacitors.
Under Voltage Lockout UVLO
The SCT2339 Under Voltage Lock Out (UVLO) default startup threshold is typical 3.5V with VIN rising and shutdown
threshold is 3.1V with VIN falling. The more accurate UVLO threshold can be programmed through the precision
enable threshold of EN pin.
Enable and Start up
When applying a voltage higher than the EN high threshold (typical 1.18V/rise), the SCT2339 enables all functions
and the device starts soft-start phase. The SCT2339 has the built in 4ms soft-start time to prevent the output
overshoot and inrush current. When EN pin is pulled low, the internal SS net will be discharged to ground. Buck
operation is disabled when EN voltage falls below its lower threshold (typically 1.1V/fall).
An internal 1.5uA pull up current source connected from internal LDO power rail to EN pin guarantees that floating
EN pin automatically enables the device. For the application requiring higher VIN UVLO voltage than the default
setup, there is a 4uA hysteresis pull up current source on EN pin which configures the VIN UVLO voltage with an
8
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SCT2339
off-chip resistor divider R3 and R4, shown in Figure 12. The resistor divider R3 and R4 are calculated by equation
(1) and (2).
EN pin is a high voltage pin and can be directly connected to VIN to automatically start up the device with VIN rising
to its internal UVLO threshold.
VIN
I2
4uA
I1
1.5uA
R3
20K
EN
+
EN
1.21V
R4
Figure 12. Adjustable VIN UVLO
𝑅3 =
𝑅4 =
𝑉𝑆𝑡𝑎𝑟𝑡 (
𝑉𝐸𝑁𝐹
) − 𝑉𝑆𝑡𝑜𝑝
𝑉𝐸𝑁𝑅
𝑉𝐸𝑁𝐹
𝐼1 (1 −
𝑉𝐸𝑁𝑅
) + 𝐼2
𝑅3 × 𝑉𝐸𝑁𝐹
𝑉𝑆𝑡𝑜𝑝 − 𝑉𝐸𝑁𝐹 + 𝑅3 (𝐼1 + 𝐼2 )
(1)
(2)
Where:
Vstart: Vin rise threshold to enable the device
Vstop: Vin fall threshold to disable the device
I1=1.5uA
I2=4uA
VENR=1.18V
VEMF=1.1V
EMI Reduction with Frequency Spread Spectrum and Switching Node Ringing-free
In buck converter, the switching node ringing amplitude and cycles are critical especially related to the high
frequency radiation EMI noise. The SCT2339 implements the multi-level gate driver speed technique to achieve the
switching node ringing-free without scarifying the switching node rise/fall slew rate and power efficiency of the
converter. The switching node ringing amplitude and cycles are damped by the built-in MOSFETs gate driving
technique (SCT Patented Proprietary Design). The switching node zoomed in wave form is shown in Figure 13.
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SCT2339
5.5
Vout (V)
5.0
0-A
4.5
1-A
2-A
4.0
3-A
3.5
4
Figure 13. SCT2339 Switching Node Waveform
4.5
5
Vin (V)
5.5
6
6.5
Figure 14. SCT2339 LDO Mode Waveform
Peak Current Limit and Hiccup Mode
The SCT2339 has cycle-by-cycle peak current limit with sensing the internal high side MOSFET Q1 current during
overcurrent condition. While the Q1 turns on, its conduction current is monitored by the internal sensing circuitry.
Once the high-side MOSFET Q1 current exceeds the limit, it turns off immediately. If the Q1 over current time
exceeds 512 switching cycles (hiccup waiting time), the buck converter enters hiccup mode and shuts down. After
8192 cycles off, the buck converter restarts to power up. The hiccup modes reduce the power dissipation in over
current condition.
Over Voltage Protection and Minimum On-time
Both SCT2339 features buck converter output over voltage protection (OVP). If the output feedback pin voltage
exceeds110% of feedback reference voltage (0.8V), the converter stops switching immediately. When the output
feedback pin voltage drops below 105% of feedback reference voltage, the converter resumes to switching. The
OVP function prevents the connected output circuitry damaged from un-predictive overvoltage. Featured feedback
overvoltage protection also prevents dynamic voltage spike to damage the circuitry at load during fast loading
transient.
The high-side MOSFET Q1 has minimum on-time 80ns typical limitation. While the device operates at minimum ontime, further increasing VIN results in pushing output voltage beyond regulation point. With output feedback over
voltage protection, the converter skips pulse by turning off high-side MOSFET Q1 and prevents output running away
higher to damage the load.
PSM Working Modes
In heavy load condition, the SCT2339 forces the device operating at forced Pulse Width Modulation (PWM) mode.
When the load current decreasing, the internal COMP net voltage decreases as the inductor current down. With the
load current further decreasing, the COMP net voltage decreases and be clamped at a voltage corresponding to
the 600mA peak inductor current. When the load current approaches zero, the SCT2339 enter Pulse Skipping Mode
(PSM) mode to increase the converter power efficiency at light load condition. When the inductor current decreases
to zero, zero-cross detection circuitry on high-side MOSFET Q1 forces the Q1 off till the beginning of the next
switching cycle. The buck converter does not sink current from the load when the output load is light and converter
works in PSM mode.
Bootstrap Voltage Regulator
An external bootstrap capacitor between BST and SW pin powers floating high-side power MOSFET gate driver.
The bootstrap capacitor voltage is charged from an integrated voltage regulator when high-side power MOSFET is
off and low-side power MOSFET is on.
10
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SCT2339
The floating supply (BST to SW) UVLO threshold is 2.7V rising and hysteresis of 350mV. When the converter
operates with high duty cycle or prolongs in sleep mode for certain long time, the required time interval to recharging
bootstrap capacitor is too long to keep the voltage at bootstrap capacitor sufficient. When the voltage across
bootstrap capacitor drops below 2.35V, BST UVLO occurs. The SCT2339 intervenes to turn on low side MOSFET
periodically to refresh the voltage of bootstrap capacitor to guarantee operation over a wide duty range.
Low Drop-out Regulation
To support the application of small voltage-difference between Vout and Vin, the Low Drop Out (LDO) Operation is
implemented by the SCT2339. The Low Drop Out Operation is triggered automatic when the off time of the highside power MOSFET exceeds the minimum off time limitation.
In low drop out operation, high-side MOSFET remains ON as long as the BST pin to SW pin voltage is higher than
BST UVLO threshold. When the voltage from BST to SW drops below 2.35V, the high-side MOSFET turns off and
low-side MOSFET turns on to recharge bootstrap capacitor periodically in the following several switching cycles.
Only 100ns of low side MOSFET turning on in each refresh cycle minimizes the output voltage ripple. Low-side
MOSFET may turn on for several times till bootstrap voltage is charged to higher than 2.7V for high-side
MOSFET working normally. Then high-side MOSFET turns on and remains on until bootstrap voltage drops to
trigger bootstrap UVLO again. Thus, the effective duty cycle of the switching regulator during Low Drop-out LDO
operation can be very high even approaching 100% as shown in Figure 14.
During ultra-low voltage difference of input and output voltages, i.e. the input voltage ramping down to power down,
the output can track input closely thanks to LDO operation mode.
Thermal Shutdown
Once the junction temperature in the SCT2339 exceeds 160°C, the thermal sensing circuit stops converter
switching and restarts with the junction temperature falling below 125°C. Thermal shutdown prevents the damage
on device during excessive heat and power dissipation condition.
.
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SCT2339
APPLICATION INFORMATION
Typical Application
C5
330pF
R1
158k
R3
2k
C4
0.1uF
R2
30k
ON
OFF
VIN=3.8V~32V
C1
10uF
FB
BST
EN
SW
VIN
GND
L1
10uH
VOUT=5V
C3
3 x 22uF
C2
0.1uF
Figure 15. 24V Input, 5V/3A Output
Design Parameters
12
Design Parameters
Example Value
Input Voltage
24V
Output Voltage
5V
Output Current
3A
Output voltage ripple (peak to peak)
±0.3V
Switching Frequency
400kHz
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SCT2339
Input Capacitor Selection
For good input voltage filtering, choose low-ESR ceramic capacitors. A ceramic capacitor 10μF is recommended
for the decoupling capacitor anda0.1μF ceramic bypass capacitor is recommended to be placed as close as
possible to the VIN pin of the SCT2339.
Use Equation (3) to calculate the input voltage ripple:
∆𝑉𝐼𝑁 =
𝐼𝑂𝑈𝑇
VOUT
𝑉𝑂𝑈𝑇
×
× (1 −
)
𝐶𝐼𝑁 × 𝑓𝑆𝑊
VIN
𝑉𝐼𝑁
(3)
Where:
CIN is the input capacitor value
fsw is the converter switching frequency
IOUT is the maximum load current
Due to the inductor current ripple, the input voltage changes if there is parasitic inductance and resistance between
the power supply and the VIN pin. It is recommended to have enough input capacitance to make the input voltage
ripple less than 100mV. Generally, a 35V/10uF input ceramic capacitor is recommended for most of applications.
Choose the right capacitor value carefully with considering high-capacitance ceramic capacitors DC bias effect,
which has a strong influence on the final effective capacitance.
Inductor Selection
The performance of inductor affects the power supply’s steady state operation, transient behavior, loop stability,
and buck converter efficiency. The inductor value, DC resistance (DCR), and saturation current influences both
efficiency and the magnitude of the output voltage ripple. Larger inductance value reduces inductor current ripple
and therefore leads to lower output voltage ripple. For a fixed DCR, a larger value inductor yields higher efficiency
via reduced RMS and core losses. However, a larger inductor within a given inductor family will generally have a
greater series resistance, thereby counteracting this efficiency advantage.
Inductor values can have ±20% or even ±30% tolerance with no current bias. When the inductor current approaches
saturation level, its inductance can decrease 20% to 35% from the value at 0-A current depending on how the
inductor vendor defines saturation. When selecting an inductor, choose its rated current especially the saturation
current larger than its peak current during the operation.
To calculate the current in the worst case, use the maximum input voltage, minimum output voltage, maxim load
current and minimum switching frequency of the application, while considering the inductance with -30% tolerance
and low-power conversion efficiency.
For a buck converter, calculate the inductor minimum value as shown in equation (4).
𝐿𝐼𝑁𝐷𝑀𝐼𝑁 =
(4)
𝑉𝑂𝑈𝑇 × (𝑉𝐼𝑁𝑀𝐴𝑋 − 𝑉𝑂𝑈𝑇 )
𝑉𝐼𝑁𝑀𝐴𝑋 × 𝐾𝐼𝑁𝐷 × 𝐼𝑂𝑈𝑇 × 𝑓𝑆𝑊
Where:
KIND is the coefficient of inductor ripple current relative to the maximum output current.
Therefore, the peak switching current of inductor, I LPEAK, is calculated as in equation (5).
𝐼𝐿𝑃𝐸𝐴𝐾 = 𝐼𝑂𝑈𝑇 + 𝐾𝐼𝑁𝐷 ×
𝐼𝑂𝑈𝑇
2
(5)
Set the current limit of the SCT2339 higher than the peak current ILPEAK and select the inductor with the saturation
current higher than the current limit. The inductor’s DC resistance (DCR) and the core loss significantly affect the
efficiency of power conversion. Core loss is related to the core material and different inductors have different core
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13
SCT2339
loss. For a certain inductor, larger current ripple generates higher DCR and ESR conduction losses and higher core
loss.
Output Capacitor Selection
For buck converter, the output capacitor value determines the regulator pole, the output voltage ripple, and how the
regulator responds to a large change in load current. The output capacitance needs to be selected based on the
most stringent of these three criteria.
For small output voltage ripple, choose a low-ESR output capacitor like a ceramic capacitor, for example, X5R and
X7R family. Typically, 1～3x 22μF ceramic output capacitors work for most applications. Higher capacitor values
can be used to improve the load transient response. Due to a capacitor’s de-rating under DC bias, the bias can
significantly reduce capacitance. Ceramic capacitors can lose most of their capacitance at rated voltage. Therefore,
leave margin on the voltage rating to ensure adequate effective capacitance.
From the required output voltage ripple, use the equation (6) to calculate the minimum required effective
capacitance, COUT.
𝐶𝑂𝑈𝑇 =
∆𝐼𝐿𝑃𝑃
8 × 𝑉𝑂𝑈𝑇𝑅𝑖𝑝𝑝𝑙𝑒 × 𝑓𝑆𝑊
(6)
Where
VOUTRipple is output voltage ripple caused by charging and discharging of the output capacitor.
ΔILPP is the inductor peak to peak ripple current, equal to kIND * IOUT.
ƒSW is the converter switching frequency.
The allowed maximum ESR of the output capacitor is calculated by the equation (7).
𝑅𝐸𝑆𝑅 =
𝑉𝑂𝑈𝑇𝑅𝑖𝑝𝑝𝑙𝑒
∆𝐼𝐿𝑃𝑃
(7)
The output capacitor affects the crossover frequency ƒC. Considering the loop stability and effect of the internal loop
1
compensation parameters, choose the crossover frequency less than 55 kHz (10 × fSW ) without considering the feedforward capacitor. A simple estimation for the crossover frequency without feed forward capacitor is shown in
equation (8), assuming COUT has small ESR.
𝐶𝑂𝑈𝑇 >
18𝑘 × 𝐺𝑀 × 𝐺𝑀𝑃 × 0.8𝑉
2𝜋 × 𝑉𝑂𝑈𝑇 × 𝑓𝐶
(8)
Where
GM is the transfer conductance of the error amplifier (300uS).
GMP is the gain from internal COMP to inductor current, which is 5A/V.
fC is the cross over frequency.
Additional capacitance de-rating for aging, temperature and DC bias should be factored in which increases this
minimum value. Capacitors generally have limits to the amount of ripple current they can handle without failing or
producing excess heat. An output capacitor that can support the inductor ripple current must be specified. The
capacitor data sheets specify the RMS (Root Mean Square) value of the maximum ripple current. Equation (9) can
be used to calculate the RMS ripple current the output capacitor needs to support.
𝐼𝐶𝑂𝑈𝑇𝑅𝑀𝑆 =
𝑉𝑂𝑈𝑇 ∙ (𝑉𝐼𝑁 − 𝑉𝑂𝑈𝑇 )
√12 ∙ 𝑉𝐼𝑁 ∙ 𝐿𝐼𝑁𝐷 ∙ 𝑓𝑆𝑊
(9)
Output Feed-Forward Capacitor Selection
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SCT2339
The SCT2339 has the internal integrated loop compensation as shown in the function block diagram. The
compensation network includes a 18k resistor and a 7.6nF capacitor. Usually, the type II compensation network has
a phase margin between 60 and 90 degree. However, if the output capacitor has ultra-low ESR, the converter
results in low phase margin. To increase the converter phase margin, a feed-forward cap Cff is used to boost the
phase margin at the converter cross-over frequency fc. Equation (10) is used to calculate the feed-forward capacitor.
𝐶𝑓𝑓 =
1
2𝜋 ∙ 𝑓𝐶 × 𝑅1
(10)
Output Feedback Resistor Divider Selection
The SCT2339 features external programmable output voltage by using a resistor divider network R1 and R2 as
shown in the typical application circuit Figure15. Use equation (11) to calculate the resistor divider values.
𝑅1 =
(𝑉𝑂𝑈𝑇 − 𝑉𝑟𝑒𝑓 ) × 𝑅2
𝑉𝑟𝑒𝑓
(11)
Set the resistor R2 value to be approximately 30k. Slightly increasing or decreasing R1 can result in closer output
voltage matching when using standard value resistors.
Table 1. Recommended External Components
Vout
L1
COUT
R1
R2
R3
Cf
3.3V
6.5uH
3*22uF
93.5k
30k
2k
330p
5V
10uH
3*22uF
158k
30k
2k
330p
12V
22uH
3*22uF
422k
30k
2k
330p
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15
SCT2339
Application Waveforms
Figure 16. SW node waveform and Output Ripple
VIN=24V, IOUT=3A
Figure 17. SW node Waveform and Output Ripple
VIN=24V, IOUT=10mA
Figure 18. Power Up
VIN=24V, VOUT=5V, IOUT=3A
Figure 19. Power Down
VIN=24V, VOUT=5V, IOUT=3A
Figure 20. Load Transient
VOUT=5V, IOUT=0.3A to 2.7A, SR=250mA/us
16
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Figure 21. Load Transient
VOUT=5V, IOUT=0.75A to 2.25 A, SR=250mA/us
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SCT2339
Layout Guideline
The regulator could suffer from instability and noise problems without carefully layout of PCB. Radiation of highfrequency noise induces EMI, so proper layout of the high-frequency switching path is essential. Minimize the length
and area of all traces connected to the SW pin, and always use a ground plane under the switching regulator to
minimize coupling. The input capacitor needs to be very close to the VIN pin and GND pin to reduce the input supply
ripple. Place the capacitor as close to VIN pin as possible to reduce high frequency ringing voltage on SW pin as
well. Figure 22 is the recommended PCB layout of SCT2339.
The layout needs be done with well consideration of the thermal. A large top layer ground plate using multiple
thermal vias is used to improve the thermal dissipation. The bottom layer is a large ground plane connected to the
top layer ground by vias.
FB
BST
EN
SW
VIN
GND
Via
VOUT
Via
Figure 22. PCB Layout Example
Thermal Considerations
The maximum IC junction temperature should be restricted to 125°C under normal operating conditions. Calculate
the maximum allowable dissipation, PD(max), and keep the actual power dissipation less than or equal to PD(max) . The
maximum-power-dissipation limit is determined using Equation (12).
𝑃𝐷(𝑀𝐴𝑋) =
125 − 𝑇𝐴
𝑅θJA
(12)
where
TA is the maximum ambient temperature for the application.
RθJA is the junction-to-ambient thermal resistance given in the Thermal Information table.
The real junction-to-ambient thermal resistance RθJA of the package greatly depends on the PCB type, layout,
thermal pad connection and environmental factor. Using thick PCB copper and soldering the GND to a large ground
plate enhance the thermal performance. Using more vias connects the ground plate on the top layer and bottom
layer around the IC without solder mask also enhance the thermal capability.
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17
SCT2339
PACKAGE INFORMATION
TOP VIEW
BOTTOM VIEW
SYMBOL
SIDE VIEW
NOTE:
1.
2.
3.
4.
5.
6.
Drawing proposed to be made a JEDEC package outline MO220 variation.
Drawing not to scale.
All linear dimensions are in millimeters.
Thermal pad shall be soldered on the board.
Dimensions of exposed pad on bottom of package do not
include mold flash.
Contact PCB board fabrication for minimum solder mask web
tolerances between the pins.
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A
A1
A2
D
E
E1
b
c
e
L
ɵ
Unit: Millimeter
MIN
TYP
MAX
------1.10
0.000
0.10
0.70
1.00
2.85
2.95
2.65
2.95
1.55
1.65
0.30
0.50
0.08
0.20
0.95(BSC)
0.30
0.60
0º
8º
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SCT2339
TAPE AND REEL INFORMATION
Feeding Direction
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19
SCT2339
RELATED PARTS
PN
SCT2320
SCT2321
DESCRIPTION
COMMENTS
3.8V-32V Vin, 2A Synchronous
Step-down DCDC Converter with
EMI Reduction
SCT2323
SCT2325
3.8V-32V Vin, 2A Synchronous
Step-down DCDC Converter with
EMI Reduction
SCT2330
3.8V-32V Vin, 3A Synchronous
Step-down DCDC Converter with
EMI Reduction
SCT2331
3.8V-32V Vin, 3A Synchronous
Step-down DCDC Converter with
EMI Reduction
500KHz switching frequency
2A Continuous output current
EMI reduction with switching node ringing-free.
Ultra-low quiescent current. High efficiency PFM at
light load (SCT2320)
Frequency Spread Spectrum (SCT2320)
Fixed PWM mode for lower output ripple (SCT2321)
1100KHz switching frequency
Fixed output 3.3V (SCT2323)/5V (SCT2325)
2A Continuous output current
EMI reduction with switching node ringing-free.
Ultra-low quiescent current. High efficiency PFM at
light load
Frequency Spread Spectrum
400KHz switching frequency
3A Continuous output current
Ultra-low quiescent current. High efficiency PFM at
light load
EMI reduction with switching node ringing-free.
Frequency Spread Spectrum
400KHz switching frequency
3A Continuous output current
EMI reduction with switching node ringing-free.
Fixed PWM mode for lower output ripple
VS
BST
EN
SW
VIN
GND
C2
0.1uF
L1
10uH
VOUT=5V
ON
OFF
VIN=4V-28V
C1
10uF
C3
22uF
C2
0.1uF
Figure 23. SCT2325 Typical Application
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee the third
party Intellectual Property rights are not infringed upon when integrating Silicon Content Technology (SCT) products into any
application. SCT will not assume any legal responsibility for any said applications.
20
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