SILICON CONTENT
TECHNOLOGY
SCT52240
Rev 1.0 - 2018
Up to 24V Supply, 4-A Dual Channel High Speed Low Side Driver
FEATURES
DESCRIPTION
Wide Supply Voltage Range: 4.5V - 24V
4A Peak Source Current and 4A Peak Sink
Current
Stackable Output for Higher Driving Capability
Negative Input Voltage Capability: Down to -5V
TTL Compatible Input Logic Threshold
Propagation Delay: 13ns
Typical Rising and Falling Times: 8ns
Typical Delay Matching: 1ns
Low Quiescent Current: 55uA
Output Low When Input Floating
Independent Enable Logic for Each Channel
Thermal Shutdown Protection: 170°C
Available in SOP-8 Package
APPLICATIONS
IGBT/MOSFET Gate Driver
Variable Frequency-Drive (VFD)
Switching Power Supply
Motor Control
Solar Power Inverter
The SCT52240 is a wide supply, dual channel, high
speed, low side gate drivers for both power MOSFET
and IGBT. Each channel can source and sink 4A peak
current along with rail-to-rail output capability. The 24V
power supply rail enhances the driver output ringing
endurance during the power device transition.
The minimum 13ns input to output propagation delay
enables the SCT52240 suitable for high frequency
power converter application.
The SCT52240 features wide input hysteresis that is
compatible for TTL low voltage logic. The SCT52240
has the capability to handle negative input down to -5V,
which increases the input noise immunity.
The SCT52240 has very low quiescent current that
reduces the stand-by loss in the power converter. The
SCT52240 each channel driver adopts non-overlap
driver design to avoid the shoot-through of output
stage. The two channels INA and INB have critical
propagation delay matching and artificial dead time
implemented in output stage, which enable stackable
output available when the system needs higher driving
capability.
The SCT52240 features 170°C thermal shut down. The
SCT52240 is available in SOP-8 package
TYPICAL APPLICATION
SCT52240 Typical Application
Application Waveform
RGA
ENA
ENB
INA
OUTA
GND
INB
VDD
VDD
RGB
OUTB
C1
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1
SCT52240
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Revision 1.0 Released to Production.
DEVICE ORDER INFORMATION
PART NUMBER
PACKAGE MARKING
PACKAGE DISCRIPTION
SCT52240STD
2240
SOP-8
1）For Tape & Reel, Add Suffix R (e.g. SCT52240STDR).
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
Over operating free-air temperature unless otherwise noted(1)
Top View: SOP-8pin
Plastic
DESCRIPTION
MIN
MAX
UNIT
ENA, ENB
-0.3
26
V
ENA
1
8
ENB
INA, INB
-5
26
V
INA
2
7
OUTA
OUTA, OUTB
-0.3
26
V
VDD
-0.3
26
V
GND
3
6
VDD
Operating junction temperature TJ (2)
-40
150
°C
INB
4
5
OUTB
Storage temperature TSTG
-65
150
°C
(1)
(2)
Stresses beyond those listed under Absolut Maximum Rating may cause device permanent damage. The device is not guaranteed to
function outside of its Recommended Operation Conditions.
The IC includes over temperature protection to protect the device during overload conditions. Junction temperature will exceed 150°C
when over temperature protection is active. Continuous operation above the specified maximum operating junction temperature will
reduce lifetime
PIN FUNCTIONS
NAME
2
NO.
PIN FUNCTION
ENA
1
Channel A enable logic input, TTL compatible. Floating logic high.
INA
2
Channel A logic input, TTL compatible. Floating logic low.
GND
3
Power ground. Must be soldered directly to ground plane for thermal performance
improvement and electrical contact.
INB
4
Channel B logic input, TTL compatible. Floating logic low.
OUTB
5
Channel B gate driver output
VDD
6
Power Supply, must be locally bypassed by the ceramic cap.
OUTA
7
Channel A gate driver output
ENB
8
Channel B enable logic input, TTL compatible. Floating logic high.
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SCT52240
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range unless otherwise noted
PARAMETER
VDD
VINA,INB
TJ
DEFINITION
Supply voltage range
Input voltage range
Operating junction temperature
MIN
MAX
UNIT
4.5
-5
-40
24
24
150
V
°C
MIN
MAX
UNIT
-2
+2
kV
-0.5
+0.5
kV
ESD RATINGS
PARAMETER
VESD
DEFINITION
Human Body Model (HBM), per ANSI-JEDEC-JS-0012014 specification, all pins (1)
Charged Device Model (CDM), per ANSI-JEDEC-JS-0022014specification, all pins (1)
(1) HBM and CDM stressing are done in accordance with the ANSI/ESDA/JEDEC JS-001-2014 specification
THERMAL INFORMATION
PARAMETER
RθJA
RθJC
THERMAL METRIC
SOP-8L
Junction to ambient thermal resistance (1)
Junction to case thermal resistance
(1)
90
39
UNIT
°C/W
(1) SCT provides RθJA and RθJC numbers only as reference to estimate junction temperatures of the devices. RθJA and RθJC are not a
characteristic of package itself, but of many other system level characteristics such as the design and layout of the printed circuit
board (PCB) on which the SCT52240 is mounted, and external environmental factors. The PCB board is a heat sink that is soldered
to the leads and thermal pad of the SCT52240. Changing the design or configuration of the PCB board changes the efficiency of the
heat sink and therefore the actual RθJA and RθJC.
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SCT52240
ELECTRICAL CHARACTERISTICS
VDD=12V, TJ=-40°C~150°C, typical values are tested under 25°C.
SYMBOL
PARAMETER
TEST CONDITION
TYP
MAX
24
V
4.5
EN=VDD=3.5V, INA=INB=GND
4.2
300
55
V
mV
uA
EN=VDD=12V, INA=INB=GND
120
Power Supply and Output
VDD
Operating supply voltage
VDD_UVLO
Input UVLO
Hysteresis
IQ
Supply current
INPUTS
VINA,INB_H
Input logic high threshold
VINA,INB_L
Input logic low threshold
VIN_Hys
MIN
4.5
VDD rising
2.1
uA
2.4
V
1
V
Hysteresis
1.1
V
VENA,ENB_H
Enable logic high threshold
2.1
VENA,ENB_L
Enable logic low threshold
VEN_Hys
Hysteresis
OUTPUTS
VDD_VOH
Output – output high voltage
IOUT= - 10mA
150
mV
VOL
Output low voltage
IOUT= 10mA
10
mV
ISINK/SRC
CLoad=10nF, FSW=1kHz
4
A
IOUT= - 10mA
9
Ω
ROL
Output sink/source peak current
Output pull high resistance (only
PMOS ON)
Output pull low resistance
0.6
Ω
Timing
TR
Output rising time
CLoad=1nF
8
20
ns
CLoad=1nF
8
20
ns
13
25
ns
13
25
TM_IN
Output falling time
Input to output propagation delay,
Rising edge
Input to output propagation delay,
Falling edge
Input to output delay matching
1
4
ns
TMIN_ON
Minimum input pulse width
CLoad=1nF
20
30
ns
Thermal shutdown threshold
TJ rising
170
°C
25
°C
ROH
TF
TD_IN
0.8
UNIT
0.8
IOUT= 10mA
2.4
V
1
V
1.1
V
Protection
TSD
4
Hysteresis
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SCT52240
TYPICAL CHARACTERISTICS
4.5
200.0
4.4
180.0
4.3
160.0
Supply Current (uA)
Supply Voltage (v)
VIN=12V, TA= 25°C.
4.2
4.1
4.0
3.9
3.8
3.7
UVLO_Rise
3.6
UVLO_Fall
140.0
120.0
100.0
80.0
60.0
VDD=3.4V
VDD=12V
40.0
20.0
3.5
-50
0
50
100
-50
150
0
Temperature (ºC)
2.0
2.0
Enable Voltage (v)
Input Voltage (v)
2.5
1.5
1.0
0.5
Input High
Input Low
1.5
1.0
0.5
Enable High
Enable Low
0.0
50
100
0.0
150
-50
0
Temperature (ºC)
50
100
150
Temperature (ºC)
Figure 3. Input Threshold vs Temperature
Figure 4. Enable Threshold vs Temperature
10.0
10.0
9.0
9.0
8.0
8.0
Falling Time (ns)
Rising Time (ns)
150
Figure 2. Start-up current vs Temperature
2.5
0
100
Temperature (ºC)
Figure 1. UVLO vs Temperature
-50
50
7.0
6.0
5.0
7.0
6.0
5.0
COUT=1nF
COUT=1nF
4.0
4.0
-50
0
50
100
150
-50
Temperature (ºC)
Figure 5 Output Rising Time vs Temperature
0
50
100
150
Temperature (ºC)
Figure 6. Output Falling Time vs Temperature
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5
20.0
15.0
18.0
13.0
Pull Up Resistance (Ω)
Delay Time (ns)
SCT52240
16.0
14.0
12.0
10.0
Input to Output High
Input to Output Low
8.0
11.0
9.0
7.0
ROH
5.0
-50
0
50
100
150
-50
0
Temperature (ºC)
50
100
150
Temperature (ºC)
Figure 8. ROH vs Temperature
Figure 7. Input to Output Propagation Delay vs Temperature
60
2.0
VDD=4.5V
1.5
Supply Current (mA)
Pull Down Resistance (Ω)
50
1.0
0.5
ROL
VDD=12V
VDD=24V
40
30
20
10
0
0.0
-50
0
50
100
0
150
Figure 9. ROL vs Temperature
6
200
400
600
800
1000
Frequency (kHz)
Temperature (ºC)
Figure 10. Operation Supply Current vs Frequency, COUT=1nF
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SCT52240
FUNCTIONAL BLOCK DIAGRAM
VDD
VDD
400k
ENA
1
INA
2
400k
8
ENB
7
OUTA
6
VDD
5
OUTB
VDD
1M
500k
GND
3
UVLO
INB
4
Thermal
Sensor
VDD
500k
1M
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SCT52240
OPERATION
Overview
The SCT52240 is a dual-channel non-invertible high-speed low side driver with supporting up to 24V wide supply
for both power MOSFET and IGBT. Each channel can source and sink 4A peak current along with the minimum
propagation delay 13ns from input to output. The 1ns delay matching and the stackable output characteristics
support higher driving capability demanding in high power converter application. The ability to handle -5V DC input
increases the noise immunity of driver input stage, the 24V rail-to-rail output improves the SCT52240 output stage
robustness during switching load fast transition. The SCT52240 has flexible input and enable pin configuration,
table 1 shows the device output logic truth table.
. Table 1: the SCT52240 Device Logic.
ENA
ENB
INA
INB
OUTA
OUTB
H
H
L
L
L
L
H
H
L
H
L
H
H
H
H
L
H
L
H
H
H
H
H
H
L
L
Any
Any
L
L
Any
Any
Floating
Floating
L
L
Floating
Floating
L
L
L
L
Floating
Floating
L
H
L
H
Floating
Floating
H
L
H
L
Floating
Floating
H
H
H
H
VDD Power Supply
The SCT52240 operates under a supply voltage range between 4.5V to 24V. For the best high-speed circuit
performance, two VDD bypass capacitors in parallel are recommended to prevent noise problems on supply VDD.
A 0.1-μF surface mount ceramic capacitor must be located as close as possible to the VDD to GND pins of the
SCT52240. In addition, a larger capacitor (such as 1-μF or 10uF) with relatively low ESR must be connected in
parallel, in order to help avoid the unexpected VDD supply glitch. The parallel combination of capacitors presents
a low impedance characteristic for the expected current levels and switching frequencies in the application.
Under Voltage Lockout (UVLO)
SCT52240 device Under Voltage Lock Out (UVLO) rising threshold is typically 4.2 V with 300-mV typical hysteresis.
When VDD is rising and the level is still below UVLO threshold, this circuit holds the output low regardless of the
status of the inputs. The hysteresis prevents output bouncing when low VDD supply voltages have noise from the
power supply. The capability to operate at low voltage below 5 V, is especially suited for driving new emerging wide
band gap power device like GaN. For example, at power up, the driver output remains low until the VDD voltage
reaches the UVLO threshold if enable pin is active or floating. The magnitude of the OUT signal rises with VDD until
steady state VDD reached.
The non-inverting operation in Figure 11 shows that the output remains low until the UVLO threshold reached, and
then the output is in-phase with the input.
8
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SCT52240
VDD
UVLO
IN
OUT
Figure 11. SCT52240 Output Vs VDD
Enable Function
SCT52240 provides independent enable pins ENA and ENB for external control of each channel operation. The
enable pins are based on a TTL compatible input-threshold logic that is independent of the supply voltage and is
effectively controlled with logic signals from 3.3-V and 5-V microcontrollers. When applying a voltage higher than
the high threshold (typical 2.1V) the pin, the SCT52240 enables all functions and starts gate driver operation. Driver
operation is disabled when ENx voltage falls below its lower threshold (typical 1.1V). The ENx pins are internally
pulled up to VDD with 400k pullup resistors. Hence, the ENx pins are left floating or Not Connected (N/C) for
standard operation, where the enable feature is not required.
Input Stage
The input of SCT52240 is compatible on TTL input-threshold logic that is independent of the VDD supply voltage.
With typically high threshold = 2.1 V and typically low threshold = 1 V, the logic level thresholds are conveniently
driven with PWM control signals derived from 3.3-V and 5-V digital power-controller devices. Wider hysteresis offers
enhanced noise immunity compared to traditional TTL logic implementations, where the hysteresis is typically less
than 0.5V. SCT52240 also features tight control of the input pin threshold voltage that ensures stable operation
across temperature. The very low input parasitic capacitance on the input pins increases switching speed and
reduces the propagation delay.
Output Stage
The SCT52240 output stage features the pull up structure with P-type MOSFET PM1 and N-type MOSFET NM1 in
parallel, as shown in Figure 12. PM1 provides the pull up capability when OUT approaches VDD and the NM1 holds
off state, which guarantees the driver output is up to VDD rail. The measurable on-resistance ROH in steady state is
the conduction resistance of PM1. NM1 provides a narrow instant peak sourcing current up to 4A to eliminate the
turn on time and delay. During the output turn on transition, the equivalent hybrid pull on transient resistance is
1.5ROL, which is much lower than the DC measured ROH.
The N-type MOSFET NM2 composes the output stage pull down structure; the ROL is the DC measurement and
represents the pull down impedance. The output stage of SCT52240 provides rail-to-rail operation, and is able to
supply 4A sourcing and 4A sinking peak current. The presence of the MOSFET-body diodes also offers low
impedance to switching overshoots and undershoots. The outputs of the dual channel drivers are designed to
withstand 500-mA reverse current without either damaging the device or logic malfunction.
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SCT52240
VDD+5V
6
VDD
5
OUT
VDD
BootStrap
NM1
Input Logic
Anti-shoot
through and
Dead time
PM1
ROH
1M
NM2
ROL
Figure 12. SCT52240 Output Stage
Stackable Output
The SCT52240 features 1ns (typical) delay matching between dual channels, which enables dual channel outputs
be stackable when the driven power device required higher driving capability. For example, in a Boost Power Factor
Correction converter, there are 2 power MOSFET in parallel to support higher power output capability. The two
power MOSFET are preferred to be driven by a common gate control signal. By using SCT52240, the OUTA and
OUTB can be connected together to provide the higher driving capability, so does the INA and INB. As a result, a
single input signal controls the stacked output combination. To support the stackable output, each channel output
stage artificially implements up to 5ns dead-time to avoid the possible shoot-through between two channels as
shown Figure 13.
Due to the rising and falling threshold mismatch between INA and INB, cautions must be taken when implementing
stackable output of OUTA and OUTB together. The maximum mismatch between INA and INB input threshold is
up to 10mV (maximum cross temperature), as a result the allowed minimum slew rate of input logic signal is 2V/us.
The following suggestions are recommended when INA and INB connected together and along with the OUTA and
OUTB:
1.
Apply the fast slew rate dv/dt on input (2 V/us or greater) to avoid the possible shoot-through between OUTA
and OUTB output stage.
2.
INA and INB must be connected as close to the pins as possible.
10
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SCT52240
6
VDD
Ishort
INA
NM1
2
7
VINA_R
VINB_R
OUTA
1M
NM2
Slow Input
500k
GND
3
INB
4
VDD
NM1
500k
5
OUTB
1M
NM2
Figure 13. SCT52240 Stackable output
The Figure 14 and Figure 15 shows the stackable output with 2V/us input signal.
Figure 14. Driver Switching ON
Figure 15. Driver Switching OFF
Thermal Shutdown
Once the junction temperature in the SCT52240 exceeds 170ºC, the thermal sensing circuit stops switching until
the junction temperature falling below 145ºC, and the device restarts. Thermal shutdown prevents the damage on
device during excessive heat and power dissipation condition.
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SCT52240
APPLICATION INFORMATION
Typical Application
RGA
ENA
INA
GND
INB
ENB
OUTA
VDD
VDD
RGB
OUTB
C1
C2
Figure 16. Dual Channel Driver Typical Application
Driver Power Dissipation
Generally, the power dissipated in the SCT52240 depends on the gate charge required of the power device (Qg),
switching frequency, and use of external gate resistors. The SCT52240 features very low quiescent currents and
internal logic to eliminate any shoot-through in the output driver stage, their effect on the power dissipation within
the gate driver is negligible.
For the pure capacitive load, the power loss of each channel in SCT52240 is:
2
𝑃𝐺 = 𝐶𝐿𝑜𝑎𝑑 ∗ 𝑉𝐷𝐷
∗ 𝑓𝑆𝑊
(1)
Where
VDD is supply voltage
CLoad is the output capacitance
FSW is the switching frequency
For the the switching load of power MOSFET, the power loss of each channel in the SCT52240 is shown in equation
(2), where charging a capacitor is determined by using the equivalence Q g = CLOADVDD. The gate charge includes
the effects of the input capacitance plus the added charge needed to swing the drain voltage of the power device
as it switches between the ON and OFF states. Manufacturers provide specifications that provide the typical and
maximum gate charge, in nC, to switch the device under specified conditions.
𝑃𝐺
Where
= 𝑄𝑔 ∗ 𝑉𝐷𝐷 ∗ 𝑓𝑆𝑊
(2)
Qg is the gate charge of the power device
fSW is the switching frequency
VDD is the supply voltage
If RG applied between driver and gate of power device to slow down the power device transition, the power
dissipation of the driver shows as below:
12
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SCT52240
𝑃𝐺 =
1
𝑅𝑂𝐿
𝑅𝑂𝐻
∗ 𝑄𝑔 ∗ 𝑉𝐷𝐷 ∗ 𝑓𝑆𝑊 ∗ （
+
）
2
𝑅𝑂𝐿 + 𝑅𝐺 𝑅𝑂𝐻 + 𝑅𝐺
(3)
Where
ROH is the equivalent pull up resistance of SCT52240
ROL is the pull down resistance of SCT52240
RG is the gate resistance between driver output and gate of power device.
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SCT52240
Application Waveforms
14
Figure 17. Driver Switching ON
Figure 18. Driver Switching OFF
Figure 19. Delay Matching Rise
Figure 20. Delay Matching Fall
Figure 21. Stackable Output Rise
Figure 22. Stackable Output Fall
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SCT52240
Layout Guideline
The SCT52240 provides the 4A output driving current and features very short rising and falling time at the power
devices gate. The high di/dt causes driver output unexpected ringing when the driver output loop is not designed
well. The regulator could suffer from malfunction and EMI noise problems if the power device gate has serious
ringing. Below are the layout recommendations with using SCT52240 and Figure 23 is the layout example.
Put the SCT52240 as close as possible to the power device to minimize the gate driving loop including the driver
output and power device gate. The power supply decoupling capacitors needs to be close to the VDD pin and GND
pin to reduce the supply ripple. For the output stackable application, the driver input loop of two-channel input must
be strictly symmetrical to ensure the input propagation delay is the same.
Star-point grounding is recommend to minimize noise coupling from one current loop to the other. The GND of the
driver connects to the other circuit nodes such as source of power MOSFET or ground of PWM controller at single
point. The connected paths must be as short as possible to reduce parasitic inductance. A ground plane is to provide
noise shielding and thermal dissipation as well.
NMOS
S
D
ENA
1
INA
2
SCT52240
8
ENB
7
OUTA
GND
3
6
VDD
INB
4
5
OUTB
GND
G
G
VDD
D
S
NMOS
Figure 23. SCT52240 PCB Layout Example
Thermal Considerations
The maximum IC junction temperature should be restricted to 150°C under normal operating conditions. Calculate
the maximum allowable dissipation, PD(max) , and keep the actual power dissipation less than or equal to P D(max) .
The maximum-power-dissipation limit is determined using Equation (4).
𝑃𝐷(𝑀𝐴𝑋) =
150 − 𝑇𝐴
𝑅θJA
(4)
where
TA is the maximum ambient temperature for the application.
RθJA is the junction-to-ambient thermal resistance given in the Thermal Information table.
The real junction-to-ambient thermal resistance RθJA of the package greatly depends on the PCB type, layout, and
environmental factor. Soldering the ground pin to a large ground plate enhance the thermal performance. Using
more vias connects the ground plate on the top layer and bottom layer around the IC without solder mask also
improves the thermal capability.
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SCT52240
PACKAGE INFORMATION
TOP VIEW
BOTTOM VIEW
SYMBOL
SIDE VIEW
NOTE:
1.
2.
3.
4.
5.
6.
16
Drawing proposed to be made a JEDEC package outline MO220 variation.
Drawing not to scale.
All linear dimensions are in millimeters.
Thermal pad shall be soldered on the board.
Dimensions of exposed pad on bottom of package do not
include mold flash.
Contact PCB board fabrication for minimum solder mask web
tolerances between the pins.
A
A1
A2
b
c
D
E
E1
e
L
ɵ
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Unit: Millimeter
MIN
TYP
MAX
1.35
--1.75
0.1
--0.25
1.35
--1.55
0.33
--0.51
0.17
--0.25
4.7
5.1
5.8
6.2
3
1.27BSC
0.4
0.8
0°
8°
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SCT52240
TAPE AND REEL INFORMATION
Feeding Direction
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17
SCT52240
TYPICAL APPLICATION
Single Channel, Non-Inverting MOSFET Gate Drive
Typical Application
RG
VDD
VDD
C1
Typical Application Waveform
OUT
C2
GND
IN+
IN-
RELATED PARTS
PART NUMBERS
SCT51240
DESCRIPTION
COMMENTS
Up to 24V Supply, 4-A Single
Channel High Speed Low
Side Driver
Compatible for both Inverting and Non-inverting
application
Supporting down to -5V input
RG
VDD
C1
VDD
OUT
C2
GND
IN+
IN-
Figure 24. SCT51240 Inverting MOSFET Gate Drive Typical Application
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