GD32F105RCT6

GigaDevice Semiconductor Inc. GD32F105xx ARM® Cortex™-M3 32-bit MCU Datasheet GD32F105xx Table of Contents List of Figures ............................................................................................................................. 3 List of Tables ............................................................................................................................... 4 1 General description ......................................................................................................... 5 2 Device overview ............................................................................................................... 6 2.1 Device information .............................................................................................................................. 6 2.2 Block diagram ...................................................................................................................................... 8 2.3 Pinouts and pin assignment .............................................................................................................. 9 2.4 Memory map ...................................................................................................................................... 12 2.5 Clock tree ........................................................................................................................................... 13 2.6 Pin definitions .................................................................................................................................... 14 Functional description .................................................................................................. 22 3 ® 3.1 ARM Cortex™-M3 core .................................................................................................................. 22 3.2 On-chip memory................................................................................................................................ 22 3.3 Clock, reset and supply management ........................................................................................... 23 3.4 Boot modes ........................................................................................................................................ 23 3.5 Power saving modes ........................................................................................................................ 24 3.6 Analog to digital converter (ADC) ................................................................................................... 24 3.7 Digital to analog converter (DAC) ................................................................................................... 25 3.8 DMA .................................................................................................................................................... 25 3.9 General-purpose inputs/outputs (GPIOs) ...................................................................................... 25 3.10 Timers and PWM generation........................................................................................................... 26 3.11 Real time clock (RTC) ...................................................................................................................... 27 3.12 Inter-integrated circuit (I2C) ............................................................................................................. 27 3.13 Serial peripheral interface (SPI)...................................................................................................... 28 3.14 Universal synchronous asynchronous receiver transmitter (USART) ....................................... 28 3.15 Inter-IC sound (I2S) .......................................................................................................................... 28 3.16 Universal serial bus on-the-go full-speed (USB OTG FS) .......................................................... 29 3.17 Controller area network (CAN) ........................................................................................................ 29 3.18 External memory controller (EXMC) .............................................................................................. 29 3.19 Debug mode ...................................................................................................................................... 30 3.20 Package and operation temperature.............................................................................................. 30 Electrical characteristics .............................................................................................. 31 4 4.1 Absolute maximum ratings .............................................................................................................. 31 4.2 Recommended DC characteristics ................................................................................................. 31 4.3 Power consumption .......................................................................................................................... 32 4.4 EMC characteristics .......................................................................................................................... 33 4.5 Power supply supervisor characteristics ....................................................................................... 33 4.6 Electrical sensitivity........................................................................................................................... 34 4.7 External clock characteristics .......................................................................................................... 34 1 / 43 GD32F105xx 4.8 Internal clock characteristics ........................................................................................................... 35 4.9 PLL characteristics ........................................................................................................................... 36 4.10 Memory characteristics .................................................................................................................... 36 4.11 GPIO characteristics......................................................................................................................... 36 4.12 ADC characteristics .......................................................................................................................... 37 4.13 DAC characteristics .......................................................................................................................... 37 4.14 I2C characteristics ............................................................................................................................ 37 4.15 SPI characteristics ............................................................................................................................ 38 5 Package information ..................................................................................................... 39 6 Ordering Information ..................................................................................................... 41 7 Revision History............................................................................................................. 42 2 / 43 GD32F105xx List of Figures Figure 1. GD32F105xx block diagram ...................................................................................................................... 8 Figure 2. GD32F105Zx LQFP144 pinouts ............................................................................................................... 9 Figure 3. GD32F105Vx LQFP100 pinouts ............................................................................................................. 10 Figure 4. GD32F105Rx LQFP64 pinouts ............................................................................................................... 11 Figure 6. GD32F105xx memory map ..................................................................................................................... 12 Figure 7. GD32F105xx clock tree............................................................................................................................ 13 Figure 8. LQFP package outline .............................................................................................................................. 39 3 / 43 GD32F105xx List of Tables Table 1. GD32F105xx devices features and peripheral list................................................................................... 6 Table 2. GD32F105xx pin definitions ...................................................................................................................... 14 Table 3. Absolute maximum ratings ........................................................................................................................ 31 Table 4. DC operating conditions ............................................................................................................................ 31 Table 5. Power consumption characteristics ......................................................................................................... 32 Table 6. EMS characteristics ................................................................................................................................... 33 Table 7. EMI characteristics ..................................................................................................................................... 33 Table 8. Power supply supervisor characteristics ................................................................................................. 33 Table 9. ESD characteristics .................................................................................................................................... 34 Table 10. Static latch-up characteristics ................................................................................................................ 34 Table 11. High speed external clock (HSE) generated from a crystal/ceramic characteristics ...................... 34 Table 12. Low speed external clock (LSE) generated from a crystal/ceramic characteristics ....................... 35 Table 13. High speed internal clock (HSI) characteristics ................................................................................... 35 Table 14. Low speed internal clock (LSI) characteristics ..................................................................................... 35 Table 15. PLL characteristics ................................................................................................................................... 36 Table 16. Flash memory characteristics ................................................................................................................. 36 Table 17. I/O port characteristics ............................................................................................................................. 36 Table 18. ADC characteristics .................................................................................................................................. 37 Table 19. DAC characteristics ................................................................................................................................. 37 Table 20. I2C characteristics .................................................................................................................................... 37 Table 21. SPI characteristics .................................................................................................................................... 38 Table 22. LQFP package dimensions ..................................................................................................................... 40 Table 23. Part ordering code for GD32F105xx devices ....................................................................................... 41 Table 24. Revision history......................................................................................................................................... 42 4 / 43 GD32F105xx 1 General description The GD32F105xx device belongs to the connectivity line of GD32 MCU Family. It is a 32-bit ® general-purpose microcontroller based on the ARM Cortex™-M3 RISC core with enhanced connectivity performance and best ratio in terms of processing power, reduced power consumption and peripheral set. The Cortex™-M3 is a next generation processor core which is tightly coupled with a Nested Vectored Interrupt Controller (NVIC), SysTick timer and advanced debug support. The GD32F105xx device incorporates the ARM ® Cortex™-M3 32-bit processor core operating at 108 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up to 1 MB on-chip Flash memory and up to 96 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up to three 12-bit ADCs, up to two 12-bit DACs, up to ten general-purpose 16-bit timers, two basic timers plus two PWM advanced-control timer, as well as standard 2 and advanced communication interfaces: up to three SPIs, two I Cs, three USARTs, two 2 UARTs, two I Ss, two CANs, an USB OTG FS. The device operates from a 2.6 to 3.6 V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications. The above features make the GD32F105xx devices suitable for a wide range of applications, especially in areas such as industrial control, motor drives, power monitor and alarm systems, consumer and handheld equipment, POS, vehicle GPS, LED display and so on. 5 / 43 GD32F105xx 2 Device overview 2.1 Device information Table 1. GD32F105xx devices features and peripheral list GD32F105xx Part Number RB RC RD RE RF RG V8 VB Flash (KB) 64 128 256 384 512 768 1024 64 128 SRAM (KB) 64 64 96 96 96 96 96 64 64 GPTM 4 4 4 4 4 10 10 4 4 Advanced TM 1 1 1 2 2 2 2 1 1 SysTick 1 1 1 1 1 1 1 1 1 Basic TM 2 2 2 2 2 2 2 2 2 Watchdog 2 2 2 2 2 2 2 2 2 RTC 1 1 1 1 1 1 1 1 1 U(S)ART 5 5 5 5 5 5 5 5 5 I2C 2 2 2 2 2 2 2 2 2 SPI 3 3 3 3 3 3 3 3 3 I2S 2 2 2 2 2 2 2 2 2 CAN 2.0B 2 2 2 2 2 2 2 2 2 USB OTG FS 1 1 1 1 1 1 1 1 1 GPIO 51 51 51 51 51 51 51 80 80 EXMC 0 0 0 0 0 0 0 1 1 EXTI 16 16 16 16 16 16 16 16 16 Units 3 3 3 3 3 3 3 3 3 Channels 16 16 16 16 16 16 16 16 16 DAC 2 2 2 2 2 2 2 2 2 ADC Connectivity Timers R8 Package LQFP64 LQFP100 6 / 43 GD32F105xx Table 1. GD32F105xx devices features and peripheral list (continued) GD32F105xx ADC Connectivity Timers Part Number VC VD VE VF VG ZC ZD ZE ZF ZG Flash (KB) 256 384 512 768 1024 256 384 512 768 1024 SRAM (KB) 96 96 96 96 96 96 96 96 96 96 GPTM 4 4 4 10 10 4 4 4 10 10 Advanced TM 1 2 2 2 2 2 2 2 2 2 SysTick 1 1 1 1 1 1 1 1 1 1 Basic TM 2 2 2 2 2 2 2 2 2 2 Watchdog 2 2 2 2 2 2 2 2 2 2 RTC 1 1 1 1 1 1 1 1 1 1 U(S)ART 5 5 5 5 5 5 5 5 5 5 I2C 2 2 2 2 2 2 2 2 2 2 SPI 3 3 3 3 3 3 3 3 3 3 I2S 2 2 2 2 2 2 2 2 2 2 CAN 2.0B 2 2 2 2 2 2 2 2 2 2 USB OTG FS 1 1 1 1 1 1 1 1 1 1 GPIO 80 80 80 80 80 112 112 112 112 112 EXMC 1 1 1 1 1 1 1 1 1 1 EXTI 16 16 16 16 16 16 16 16 16 16 Units 3 3 3 3 3 3 3 3 3 3 Channels 16 16 16 16 16 21 21 21 21 21 DAC 2 2 2 2 2 2 2 2 2 2 Package LQFP100 LQFP144 7 / 43 GD32F105xx 2.2 Block diagram Figure 1. GD32F105xx block diagram POR/PDR TPIU SW/JTAG GP DMA 1 7chs GP DMA 2 5chs Ibus Dbus Flash Memory Flash Memory Controller 2 Flash Memory FMC Control Registers Master AHB Matrix NVIC ICode DCode System ARM Cortex-M3 Processor Fmax: 108MHz PLL Fmax: 144MHz Flash Memory Controller 1 LDO 1.2V HSI 8MHz RST/CLK Control Registers AHB Peripherals Slave HSE 4-16MHz EXMC Slave Slave LVD SRAM Controller SRAM Master Master Powered By V DDA Slave AHB to APB Bridge 2 AHB to APB Bridge 1 USB OTG FS Interrput request CAN1 USART1 Slave SPI1 Slave WDG GP TM2 ADC1 12-bit SAR ADC GPIOB GPIOC APB1: Fmax = 54MHz GPIOA GP TM4 APB2: Fmax = 108MHz ADC3 Powered By V DDA GP TM3 ADC2 GP TM5 GP TM12 GP TM13 GP TM14 GPIOD SPI2/I2S2 GPIOE SPI3/I2S3 GPIOF USART2 GPIOG USART3 ADV TM1 UART4 ADV TM8 UART5 GP TM9 I2C1 GP TM10 BSC TM6 I2C2 GP TM11 BSC TM7 DAC1 EXTI DAC2 CAN2 8 / 43 GD32F105xx 2.3 Pinouts and pin assignment Figure 2. GD32F105Zx LQFP144 pinouts PA14 PA15 PC10 PC11 PC12 PD0 PD1 PD2 PD3 PD4 PD5 VSS_10 VDD_10 PD6 PD7 PG9 PG10 PG11 PG12 PG13 PG14 VSS_11 VDD_11 PG15 PB4 PB3 PB5 PB6 PB7 BOOT0 PB8 PB9 PE0 PE1 VSS_3 VDD_3 PE2 1 144143142141140139138137136135134133 132131130129128127126125124123122121120 119118117116115114113112111110109 108 PE3 PE4 2 107 VSS_2 3 NC PE5 PE6 4 106 105 5 104 VBAT 6 103 PA12 PA11 PC13-TAMPER-RTC PC14-OSC32_IN 7 102 PA10 8 PA9 PC15-OSC32_OUT 9 101 100 10 99 PC9 PF1 11 98 PC8 PF2 12 97 PC7 PF3 PF4 PF5 13 96 PC6 14 95 VDD_9 15 94 VSS_9 93 PG8 VDD_5 16 17 PF6 18 PF7 19 PF8 PF9 20 21 PF10 22 PF0 VSS_5 GigaDevice GD32F105Zx LQFP144 VDD_2 PA13 PA8 92 PG7 91 90 PG6 89 PG4 PG5 88 PG3 87 PG2 OSC_IN 23 86 PD15 OSC_OUT 24 85 PD14 NRST 25 84 VDD_8 PC0 26 83 VSS_8 PC1 27 28 82 PD13 PD12 PC3 VSSA 29 80 79 PD11 VREFVREF+ 31 32 78 PD9 77 PD8 VDDA 33 76 PB15 PA0_WKUP 34 75 PB14 PA1 35 74 PB13 PA2 36 73 PB12 PC2 81 30 PD10 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 VDD_1 VSS_1 PB11 PB10 PE15 PE13 PE14 PE12 PE11 VDD_7 PE10 VSS_7 PE8 PE9 PE7 PG1 PG0 PF15 PF14 VDD_6 PF13 VSS_6 PF12 PB2 PF11 PB1 PC5 PB0 PA7 PC4 PA6 PA5 VDD_4 PA4 VSS_4 PA3 9 / 43 GD32F105xx Figure 3. GD32F105Vx LQFP100 pinouts PA14 PA15 PC10 PC11 PC12 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PB4 PB3 PB5 PB6 PB7 BOOT0 PB8 PB9 PE0 PE1 VSS_3 VDD_3 PE2 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 PE3 PE4 2 74 VSS_2 3 NC PE5 PE6 4 73 72 5 71 VBAT 6 PC13-TAMPER-RTC PC14-OSC32_IN 7 70 69 PC15-OSC32_OUT VSS_5 PA13 PA12 PA11 PA10 PA9 9 68 67 10 66 PC9 8 PA8 65 PC8 64 PC7 63 PC6 14 62 PD15 15 61 PD14 16 17 60 PD13 59 PD12 18 58 57 PD11 56 PD9 VDD_5 11 OSC_IN 12 OSC_OUT NRST PC0 13 PC1 PC2 PC3 VDD_2 GigaDevice GD32F105Vx LQFP100 VSSA 19 VREFVREF+ 20 21 55 PD8 VDDA 22 54 PB15 PD10 PA0-WKUP 23 53 PA1 24 52 PB14 PB13 PA2 25 51 PB12 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VSS_1 VDD_1 PB11 PB10 PE15 PE14 PE13 PE11 PE12 PE10 PE9 PE8 PE7 PB2 PB1 PC5 PB0 PA7 PC4 PA6 PA5 PA4 VDD_4 PA3 VSS_4 10 / 43 GD32F105xx Figure 4. GD32F105Rx LQFP64 pinouts PA14 PA15 PC10 PC11 PD2 PC12 PB3 PB4 PB5 PB6 PB7 PB8 BOOT0 PB9 VSS_3 VDD_3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VBAT 1 48 VDD_2 PC13-TAMPER-RTC 2 47 VSS_2 PC14-OSC32_IN 3 46 PA13 PC15-OSC32_OUT PD0-OSC_IN 4 45 PA12 5 44 PA11 PD1 OSC_OUT 6 43 PA10 NRST PC0 7 8 42 PA9 PC1 9 PC2 PC3 VSSA 10 11 12 37 PC6 VDDA 13 36 PB15 PA0-WKUP 14 35 PA1 15 34 PB14 PB13 PA2 16 33 PB12 GigaDevice GD32F105Rx LQFP64 41 PA8 40 39 PC9 38 PC7 PC8 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD_1 VSS_1 PB11 PB10 PB2 PB1 PC5 PB0 PA7 PC4 PA6 PA5 PA4 VDD_4 VSS_4 PA3 11 / 43 GD32F105xx 2.4 Memory map Figure 5. GD32F105xx memory map 0x 5FFF FFFF 0x 5000 0400 0x 5000 0000 0x 4002 3400 0x 4002 3000 0x 4002 2400 0x 4002 2000 0x 4002 1400 DMA2 0x 4002 0000 DMA1 reserved 0x 4001 5000 0x 4001 4C00 0x 4001 4000 0x 4001 3C00 0x 4001 3800 0x 4001 3400 0x 4001 3000 0x 4001 2C00 0x 4001 2800 0x 4001 2400 0x 4001 2000 0x 4001 1C00 0x 4001 1800 0x1FFF FFFF 0x1FFF F80F reserved Option Bytes 0x 4001 1400 0x1FFF F000 0x 4001 0C00 0x 4001 0800 0xE000 0000 0x 4001 0400 6 0x 4000 7800 0x 4001 0000 reserved 0x 4000 7400 0x 4000 7000 0xC000 0000 System memory 0x 4001 1000 0xE010 0000 0x1FFF F800 0x 4000 6C00 5 EXMC register 0x 4000 6800 0xA000 1000 0x 4000 6400 0xA000 0000 0x 4000 5C00 0x 4000 5800 reserved 4 reserved 0x8000 0000 EXMC bank 3 reserved 0x 4000 5400 0x 4000 5000 0x 4000 4C00 0x 4000 4800 0x 4000 4400 0x 4000 4000 0x 4000 3C00 0x6000 0000 2 0x 4000 3800 reserved 0x 4000 3400 0x 4000 3000 0x 4000 2C00 0x4000 0000 0x0810 0000 0x0808 0000 0x0800 0000 Peripherals Flash memory bank 2 (512KB) 1 Flash memory bank 1 (512KB) 0x2001 8000 0x2000 0000 SRAM (96KB) 0 reserved reserved 0x0010 0000 Aliased to Flash or system memory according to BOOT 0x0000 0000 pins configuration 0x0000 0000 reserved Flash Interface reserved 0x 4002 0400 0x 4001 5400 7 CRC reserved RCC reserved 0x 4001 5800 Cortex-M3 Internal Peripherals reserved 0x 4002 0800 0x 4002 1000 0xFFFF FFFF reserved USB OTG FS 0x 4000 2800 0x 4000 2400 0x 4000 2000 0x 4000 1C00 0x 4000 1800 0x 4000 1400 0x 4000 1000 0x 4000 0C00 0x 4000 0800 0x 4000 0400 0x 4000 0000 TM11 TM10 TM9 reserved ADC3 USART1 TM8 SPI1 TM1 ADC2 ADC1 Port G Port F Port E Port D Port C Port B Port A EXTI AFIO reserved DAC PWR BKP bxCAN2 bxCAN1 reserved I2C2 I2C1 UART5 UART4 USART3 USART2 reserved SPI3/I2S3 SPI2/I2S2 reserved IWDG WWDG RTC reserved TM14 TM13 TM12 TM7 TM6 TM5 TM4 TM3 TM2 12 / 43 GD32F105xx 2.5 Clock tree Figure 6. GD32F105xx clock tree USB ÷Prescaler (1,1.5,2) CK_USB (to USB) I2S2CLK (to I2S2) enable I2S3CLK (to I2S3) enable CK_FMCU SCS[1:0] FMCU enable (by hardware) (to FMCU) CK_EXMC CK_HSI EXMC enable 00 8 MHz HSI RC 0 /2 PLLPREDV 1 PLL × 2...32 PLLSEL PLLEN CK_PLL 10 CK_SYS 108 MHz max AHB ÷Prescaler (1,2...512) (to EXMC) CK_AHB 108 MHz max HCLK AHB enable (to AHB bus,Cortex-M3,SRAM,DMA) 01 CK_CST ÷8 (to Cortex-M3 SysTick) /2 4-16 MHz HSE XTAL 1 Clock Monitor 0 CK_HSE /128 32.768 KHz LSE OSC FCLK (free running clock) TM2,3,4 × 1 or × 2 to TM2,3,4 11 01 (to RTC) APB1 ÷Prescaler (1,2,4,8,16) CK_IWDG TM1 × 1 or × 2 CK_RTC RTCSRC[1:0] CK_APB1 PCLK1 54 MHz max Peripheral enable 10 40 KHz LSI RC CK_TMX TMX enable CK_TM1 TM1 enable to TM1 (to IWDG) CK_SYS APB2 ÷Prescaler (1,2,4,8,16) CK_HSI CK_APB2 PCLK2 108 MHz max Peripheral enable CK_OUT to APB1 peripherals to APB2 peripherals CK_HSE CK_PLL/2 ADC ÷Prescaler (2,4,8,12,16) CK_ADCX to ADC1,ADC2 14 MHz max Legend: HSE = High speed external clock HSI = High speed internal clock LSE = Low speed external clock LSI = Low speed internal clock 13 / 43 GD32F105xx 2.6 Pin definitions LQFP100 LQFP64 Pin Type PE2 1 1 - I/O 5VT PE3 2 2 - I/O 5VT PE4 3 3 - I/O 5VT Functions description I/O Pin Name (2) LQFP144 (1) Pins Level Table 2. GD32F105xx pin definitions Default: PE2 Alternate: TRACECK, EXMC_A23 Default: PE3 Alternate: TRACED0, EXMC_A19 Default: PE4 Alternate:TRACED1, EXMC_A20 Default: PE5 PE5 4 4 - I/O 5VT Alternate:TRACED2, EXMC_A21 Remap: TM9_CH1 (4) Default: PE6 PE6 5 5 - I/O 5VT Alternate:TRACED3, EXMC_A22 Remap: TM9_CH2 VBAT PC13-TAMPE R-RTC PC14-OSC32 _IN PC15OSC32_OUT PF0 PF1 6 6 1 P 7 7 2 I/O 8 8 3 I/O 9 9 4 I/O 10 - - I/O 11 - - I/O Default: VBAT Default: PC13 Alternate: TAMPER-RTC Default: PC14 Alternate: OSC32_IN Default: PC15 Alternate: OSC32_OUT 5VT 5VT Default: PF0 (3) Alternate: EXMC_A0 Default: PF1 Alternate: EXMC_A1 Default: PF2 - - I/O 5VT PF3 13 - - I/O 5VT PF4 14 - - I/O 5VT PF5 15 - - I/O 5VT VSS_5 16 10 - P Default: VSS_5 VDD_5 17 11 - P Default: VDD_5 Alternate: EXMC_A2 18 - - I/O 19 - - I/O (3) (3) (3) (3) Alternate: ADC3_IN4 , EXMC_NIORD Remap: TM10_CH1 PF7 (3) (3) Alternate: EXMC_A5 Default: PF6 (3) (3) Alternate: EXMC_A4 Default: PF5 (3) (3) Alternate: EXMC_A3 Default: PF4 (3) (3) 12 Default: PF3 (3) (3) PF2 PF6 (4) Default: PF7 (4) (3) (3) (3) Alternate: ADC3_IN5 , EXMC_NREG 14 / 43 (2) Functions description I/O (1) Pin Type LQFP64 LQFP100 Pin Name LQFP144 Pins Level GD32F105xx Remap: TM11_CH1 Default: PF8 PF8 20 - - I/O (3) Default: PF9 21 - - I/O (3) Alternate: ADC3_IN6 , EXMC_NIOWR Remap: TM13_CH1 PF9 (4) (3) (4) (3) (3) (3) Alternate: ADC3_IN7 , EXMC_CD Remap: TM14_CH1 (4) (3) Default: PF10 PF10 22 - - I/O OSC_IN 23 12 5 I OSC_OUT 24 13 6 O NRST 25 14 7 I/O PC0 26 15 8 I/O PC1 27 16 9 I/O PC2 28 17 10 I/O PC3 29 18 11 I/O VSSA 30 19 12 P Default: VSSA VREF- 31 20 - P Default: VREF- VREF+ 32 21 - P Default: VREF+ VDDA 33 22 13 P Default: VDDA (3) (3) Alternate: ADC3_IN8 , EXMC_INTR Default: OSC_IN Remap: PD0 (4) Default: OSC_OUT Remap: PD1 (4) Default: NRST Default: PC0 Alternate: ADC_IN10 Default: PC1 Alternate: ADC_IN11 Default: PC2 Alternate: ADC_IN12 Default: PC3 Alternate: ADC_IN13 Default: PA0 PA0-WKUP 34 23 14 I/O Alternate: WKUP, USART2_CTS, ADC_IN0, TM2_CH1_ETR, (3) (3) TM5_CH1 , TM8_ETR Default: PA1 PA1 35 24 15 I/O PA2 36 25 16 I/O PA3 37 26 17 I/O VSS_4 38 27 18 P Default: VSS_4 VDD_4 39 28 19 P Default: VDD_4 PA4 40 29 20 I/O Alternate: USART2_RTS, ADC_IN1, TM2_CH2, TM5_CH2 (3) Default: PA2 Alternate: USART2_TX, ADC_IN2, TM2_CH3, TM5_CH3 (3) , TM9_CH1 (4) (3) , TM9_CH2 Default: PA3 Alternate: USART2_RX, ADC_IN3, TM2_CH4, TM5_CH4 (4) Default: PA4 Alternate: SPI1_NSS, USART2_CK, ADC12_IN4; DAC_OUT1 (3) (3) (3) Remap: SPI3_NSS , I2S3_WS PA5 41 30 21 I/O Default: PA5 Alternate: SPI1_SCK, ADC12_IN5, DAC_OUT2 (3) 15 / 43 (2) Functions description I/O (1) Pin Type LQFP64 LQFP100 Pin Name LQFP144 Pins Level GD32F105xx Default: PA6 (3) PA6 42 31 22 Alternate: SPI1_MISO, ADC12_IN6, TM3_CH1, TM8_BKIN , I/O TM13_CH1 (4) Remap: TM1_BKIN Default: PA7 (3) PA7 43 32 23 Alternate: SPI1_MOSI, ADC12_IN7, TM3_CH2, TM8_CH1N , I/O TM14_CH1 (4) Remap: TM1_CH1N PC4 44 33 24 I/O PC5 45 34 25 I/O PB0 46 35 26 I/O Default: PC4 Alternate: ADC12_IN14 Default: PC5 Alternate: ADC12_IN15 Default: PB0 (3) Alternate: ADC12_IN8, TM3_CH3, TM8_CH2N Remap: TM1_CH2N Default: PB1 PB1 47 36 27 (3) Alternate: ADC12_IN9, TM3_CH4, TM8_CH3N I/O Remap: TM1_CH3N PB2 48 37 28 I/O 5VT Default: PB2/BOOT1 PF11 49 - - I/O 5VT PF12 50 - - I/O 5VT VSS_6 51 - - P Default: VSS_6 VDD_6 52 - - P Default: VDD_6 PF13 53 - - I/O 5VT PF14 54 - - I/O 5VT PF15 55 - - I/O 5VT PG0 56 - - I/O 5VT PG1 57 - - I/O 5VT (3) Default: PF11 Alternate: EXMC_NIOS16 (3) (3) Default: PF12 Alternate: EXMC_A6 (3) (3) Default: PF13 Alternate: EXMC_A7 (3) (3) Default: PF14 Alternate: EXMC_A8 (3) (3) Default: PF15 Alternate: EXMC_A9 Default: PG0 (3) (3) Alternate: EXMC_A10 Default: PG1 (3) (3) Alternate: EXMC_A11 (3) Default: PE7 PE7 58 38 - I/O 5VT Alternate: EXMC_D4 Remap: TM1_ETR Default: PE8 PE8 59 39 - I/O 5VT Alternate: EXMC_D5 Remap: TM1_CH1N PE9 60 40 - I/O 5VT Default: PE9 Alternate: EXMC_D6 16 / 43 (2) Functions description I/O (1) Pin Type LQFP64 LQFP100 Pin Name LQFP144 Pins Level GD32F105xx Remap: TM1_CH1 VSS_7 61 - - P Default: VSS_7 VDD_7 62 - - P Default: VDD_7 Default: PE10 PE10 63 41 - I/O 5VT Alternate: EXMC_D7 Remap: TM1_CH2N Default: PE11 PE11 64 42 - I/O 5VT Alternate: EXMC_D8 Remap: TM1_CH2 Default: PE12 PE12 65 43 - I/O 5VT Alternate: EXMC_D9 Remap: TM1_CH3N Default: PE13 PE13 66 44 - I/O 5VT Alternate: EXMC_D10 Remap: TM1_CH3 Default: PE14 PE14 67 45 - I/O 5VT Alternate: EXMC_D11 Remap: TM1_CH4 Default: PE15 PE15 68 46 - I/O 5VT Alternate: EXMC_D12 Remap: TM1_BKIN Default: PB10 PB10 69 47 29 I/O 5VT Alternate: I2C2_SCL, USART3_TX Remap: TM2_CH3 Default: PB11 PB11 70 48 30 I/O 5VT Alternate: I2C2_SDA, USART3_RX Remap: TM2_CH4 VSS_1 71 49 31 P Default: VSS_1 VDD_1 72 50 32 P Default: VDD_1 Default: PB12 PB12 73 51 33 I/O 5VT Alternate: SPI2_NSS, I2C2_SMBAI, USART3_CK, TM1_BKIN, (3) I2S2_WS , CAN2_RX PB13 74 52 34 I/O 5VT PB14 75 53 35 I/O 5VT PB15 76 54 36 I/O 5VT Default: PB13 (3) Alternate: SPI2_SCK, USART3_CTS, TM1_CH1N, I2S2_CK , CAN2_TX Default: PB14 Alternate: SPI2_MISO, USART3_RTS, TM1_CH2N, TM12_CH1 (4) Default: PB15 (3) Alternate: SPI2_MOSI, TM1_CH3N, I2S2_SD , TM12_CH2 (4) Default: PD8 PD8 77 55 - I/O 5VT Alternate: EXMC_D13 Remap: USART3_TX PD9 78 56 - I/O 5VT Default: PD9 Alternate: EXMC_D14 17 / 43 (2) Functions description I/O (1) Pin Type LQFP64 LQFP100 Pin Name LQFP144 Pins Level GD32F105xx Remap: USART3_RX Default: PD10 PD10 79 57 - I/O 5VT Alternate: EXMC_D15 Remap: USART3_CK Default: PD11 PD11 80 58 - I/O 5VT Alternate: EXMC_A16 Remap: USART3_CTS Default: PD12 PD12 81 59 - I/O 5VT Alternate: EXMC_A17 Remap: TM4_CH1, USART3_RTS Default: PD13 5VT Alternate: EXMC_A18 PD13 82 60 - I/O VSS_8 83 - - P Default: VSS_8 VDD_8 84 - - P Default: VDD_8 PD14 85 61 - I/O Remap: TM4_CH2 Default: PD14 5VT Alternate: EXMC_D0 Remap: TM4_CH3 Default: PD15 PD15 86 62 - I/O 5VT Alternate: EXMC_D1 Remap: TM4_CH4 PG2 87 - - I/O 5VT PG3 88 - - I/O 5VT PG4 89 - - I/O 5VT Default: PG2 (3) Alternate: EXMC_A12 Default: PG3 (3) Alternate: EXMC_A13 Default: PG4 (3) (3) PG5 90 - - I/O 5VT PG6 91 - - I/O 5VT PG7 92 - - I/O 5VT PG8 93 - - I/O 5VT Default: PG8 VSS_9 94 - - P Default: VSS_9 VDD_9 95 - - P Default: VDD_9 PC6 96 63 37 I/O Alternate: EXMC_A15 Default: PG6 (3) (3) Alternate: EXMC_A14 Default: PG5 (3) (3) (3) Alternate: EXMC_INT2 Default: PG7 (3) (3) Alternate: EXMC_INT3 (3) (3) Default: PC6 (3) (3) (3) (3) 5VT Alternate: I2S2_MCK ; TM8_CH1 Remap: TM3_CH1 Default: PC7 PC7 97 64 38 I/O 5VT Alternate: I2S3_MCK ; TM8_CH2 Remap: TM3_CH2 PC8 98 65 39 I/O 5VT Default: PC8 18 / 43 (2) Functions description I/O (1) Pin Type LQFP64 LQFP100 Pin Name LQFP144 Pins Level GD32F105xx Alternate: TM8_CH3 (3) Remap: TM3_CH3 Default: PC9 PC9 99 66 40 I/O 5VT Alternate: TM8_CH4 (3) Remap: TM3_CH4 PA8 100 67 41 I/O 5VT PA9 101 68 42 I/O 5VT PA10 102 69 43 I/O 5VT PA11 103 70 44 I/O 5VT PA12 104 71 45 I/O 5VT PA13 105 72 46 I/O 5VT NC 106 73 - Default: PA8 Alternate: USART1_CK, TM1_CH1, MCO Default: PA9 Alternate: USART1_TX, TM1_CH2, OTG_FS_VBUS Default: PA10 Alternate: USART1_RX, TM1_CH3, OTG_FS_ID Default: PA11 Alternate: USART1_CTS, CANRX, OTG_FS_DM, TM1_CH4 Default: PA12 , Alternate: USART1_RTS, OTG_FS_DP, CAN1_TX TM1_ETR Default: JTMS, SWDIO Remap: PA13 - VSS_2 107 74 47 P Default: VSS_2 VDD_2 108 75 48 P Default: VDD_2 PA14 109 76 49 I/O 5VT Default: JTCK, SWCLK Remap: PA14 Default: JTDI PA15 110 77 50 I/O (3) (3) 5VT Alternate: SPI3_NSS , I2S3_WS Remap: TM2_CH1_ETR, PA15, SPI1_NSS Default: PC10 PC10 111 78 51 I/O (3) 5VT Alternate: UART4_TX (3) (3) Remap: USART3_TX, SPI3_SCK , I2S3_CK Default: PC11 PC11 112 79 52 I/O (3) 5VT Alternate: UART4_RX (3) Remap: USART3_RX, SPI3_MISO Default: PC12 PC12 113 80 53 I/O (3) 5VT Alternate: UART5_TX (3, (3) Remap: USART3_CK, SPI3_MOSI I2S3_SD Default: PD0 PD0 114 81 5 I/O 5VT Alternate: EXMC_D2 Remap: CAN1_RX, OSC_IN Default: PD1 PD1 115 82 6 I/O 5VT Alternate: EXMC_D3 Remap: CAN1_TX, OSC_OUT Default: PD2 PD2 116 83 54 I/O 5VT PD3 117 84 - I/O 5VT Default: PD3 (3) Alternate: TM3_ETR, UART5_RX 19 / 43 (2) Functions description I/O (1) Pin Type LQFP64 LQFP100 Pin Name LQFP144 Pins Level GD32F105xx Alternate: EXMC_CLK Remap: USART2_CTS Default: PD4 PD4 118 85 - I/O 5VT Alternate: EXMC_NOE Remap: USART2_RTS Default: PD5 PD5 119 86 - I/O 5VT Alternate: EXMC_NWE Remap: USART2_TX VSS_10 120 - - Default: VSS_10 VDD_10 121 - - Default: VDD_10 Default: PD6 PD6 122 87 - I/O 5VT Alternate: EXMC_NWAIT Remap: USART2_RX Default: PD7 PD7 123 88 - I/O 5VT Alternate: EXMC_NE1/EXMC_NCE2 Remap: USART2_CK PG9 124 - - I/O 5VT Default: PG9 (3) (3) Alternate: EXMC_NE2 , EXMC_NCE3 Default: PG10 (3) (3) PG10 125 - - I/O 5VT PG11 126 - - I/O 5VT PG12 127 - - I/O 5VT PG13 128 - - I/O 5VT PG14 129 - - I/O 5VT VSS_11 130 - - P Default: VSS_10 VDD_11 131 - - P Default: VDD_10 PG15 132 - - I/O 5VT Default: PG15 55 I/O 5VT Alternate:SPI3_SCK , I2S3_CK (3) Alternate: EXMC_NCE4_1 , EXMC_NE3 Default: PG11 (3) Alternate: EXMC_NCE4_2 Default: PG12 (3) (3) Alternate: EXMC_A24 Default: PG14 (3) (3) Alternate: EXMC_NE4 Default: PG13 (3) (3) (3) Alternate: EXMC_A25 (3) Default: JTDO PB3 133 89 (3) (3) Remap: PB3, TRACESWO, TM2_CH2, SPI1_SCK Default: NJTRST PB4 134 90 56 I/O (3) 5VT Alternate: SPI3_MISO Remap: TM3_CH1, PB4, SPI1_MISO Default: PB5 PB5 135 91 57 I/O (3) (3) Alternate: I2C1_SMBAI, SPI3_MOSI , I2S3_SD Remap: TM3_CH2, SPI1_MOSI, CAN2_RX Default: PB6 PB6 136 92 58 I/O 5VT Alternate: I2C1_SCL, TM4_CH1, Remap: USART1_TX, CAN2_TX 20 / 43 (1) Functions description I/O (2) Pin Type LQFP64 LQFP100 Pin Name LQFP144 Pins Level GD32F105xx Default: PB7 PB7 137 93 59 I/O (3) 5VT Alternate: I2C1_SDA , TM4_CH2, EXMC_NADV Remap: USART1_RX BOOT0 138 94 60 I PB8 139 95 61 I/O Default: BOOT0 Default: PB8 5VT Alternate: TM4_CH3, TM10_CH1 (4) Remap: I2C1_SCL, CAN1_RX Default: PB9 PB9 140 96 62 I/O 5VT Alternate: TM4_CH4, TM11_CH1 (4) Remap: I2C1_SDA, CAN1_TX Default: PE0 PE0 141 97 - I/O 5VT PE1 142 98 - I/O 5VT VSS_3 143 99 63 P Default: VSS_3 VDD_3 144 100 64 P Default: VDD_3 Alternate: TM4_ETR, EXMC_NBL0 Default: PE1 Alternate: EXMC_NBL1 Notes: 1. Type: I = input, O = output, P = power. 2. I/O Level: 5VT = 5 V tolerant. 3. Functions are available in GD32F105xC, GD32F105xD, GD32F105xE, GD32F105xF, GD32F105xG devices. 4. Functions are available in GD32F105xF, GD32F105xG devices. 21 / 43 GD32F105xx 3 Functional description 3.1 ARM® Cortex™-M3 core ® The Cortex™-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. ®  32-bit ARM Cortex™-M3 processor core  Up to 108 MHz operation frequency  Single-cycle multiplication and hardware divider  Integrated Nested Vectored Interrupt Controller (NVIC)  24-bit SysTick timer The Cortex™-M3 processor is based on the ARMv7 architecture and supports both Thumb and Thumb-2 instruction sets. Some system peripherals listed below are also provided by Cortex™-M3:  Internal Bus Matrix connected with ICode bus, DCode bus, system bus, Private Peripheral Bus (PPB) and debug accesses (AHB-AP) 3.2  Nested Vectored Interrupt Controller (NVIC)  Flash Patch and Breakpoint (FPB)  Data Watchpoint and Trace (DWT)  Instrument Trace Macrocell (ITM)  Memory Protection Unit (MPU)  Serial Wire JTAG Debug Port (SWJ-DP)  Trace Port Interface Unit (TPIU) On-chip memory  Up to 1024 Kbytes of Flash memory  Up to 96 Kbytes of SRAM ® The ARM ™ Cortex -M3 processor is structured in Harvard architecture which can use separate buses to fetch instructions and load/store data. 1024 Kbytes of inner Flash and 96 Kbytes of inner SRAM at most is available for storing programs and data, both accessed (R/W) at CPU clock speed with zero wait states. The Figure 6. GD32F105xx memory map shows the memory map of the GD32F105xx series of devices, including code, SRAM, peripheral, and other pre-defined regions. 22 / 43 GD32F105xx 3.3 Clock, reset and supply management  Internal 8 MHz factory-trimmed RC and external 4 to 16 MHz crystal oscillator  Internal 40 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator  Integrated system clock PLL  2.6 to 3.6 V application supply and I/Os  Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage detector (LVD) The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These include speed internal RC oscillator and external crystal oscillator, high speed and low speed two types. Several prescalers allow the configuration of the AHB frequency, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and the high-speed APB domains is 108 MHz. The maximum allowed frequency of the low-speed APB domain is 54 MHz. See Figure 7 for details on the clock tree. The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from/down to 2.6 V. The device remains in reset mode when VDD is below a specified threshold. The embedded low voltage detector (LVD) monitors the power supply, compares it to the voltage threshold and generates an interrupt as a warning message for leading the MCU into security. Power supply schemes:  VDD range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator. Provided externally through VDD pins.  VSSA, VDDA range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.  VBAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. 3.4 Boot modes At startup, boot pins are used to select one of three boot options:  Boot from main flash memory (default)  Boot from system memory  Boot from on-chip SRAM The boot loader is located in the internal boot ROM memory (system memory). It is used to reprogram the Flash memory by using USART1, USART2, CAN2, USB OTG FS in device mode. It also can be used to transfer and update the Flash memory code, the data and the vector table sections. In default condition, boot from bank 1 of Flash memory is selected. It also supports to boot from bank 2 of Flash memory by setting a bit in option bytes. 23 / 43 GD32F105xx 3.5 Power saving modes The MCU supports three kinds of power saving modes to achieve even lower power consumption. They are Sleep mode, Deep-sleep mode, and Standby mode. These operating modes reduce the power consumption and allow the application to achieve the best balance between the CPU operating time, speed and power consumption.  Sleep mode In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and any interrupt/event can wake up the system.  Deep-sleep mode In Deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed crystal oscillator (HSI, HSE) and PLL are disabled. Only the contents of SRAM and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the system from the Deep-sleep mode including the 16 external lines, the RTC alarm, the LVD output, and USB wakeup. When exiting the Deep-sleep mode, the HSI is selected as the system clock.  Standby mode In Standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of HSI, HSE and PLL are disabled. The contents of SRAM and registers (except Backup Registers) are lost. There are four wakeup sources for the Standby mode, including the external reset from NRST pin, the RTC alarm, the IWDG reset, and the rising edge on WKUP pin. 3.6 Analog to digital converter (ADC)  12-bit SAR ADC engine  Up to 1 MSPS conversion rate  Conversion range: VSSA to VDDA (2.6 to 3.6 V)  Temperature sensor Up to three 12-bit 1 μs multi-channel ADCs are integrated in the device. Each is a total of up to 21 multiplexed external channels. An analog watchdog block can be used to detect the channels, which are required to remain within a specific threshold window. A configurable channel management block of analog inputs also can be used to perform conversions in single, continuous, scan or discontinuous mode to support more advanced usages. The ADCs can be triggered from the events generated by the general-purpose timers (TMx) and the advanced-control timers (TM1 and TM8) with internal connection. The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2.6 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value. 24 / 43 GD32F105xx 3.7 Digital to analog converter (DAC)  Two 12-bit DAC converters of independent output channel  8-bit or 12-bit mode in conjunction with the DMA controller The two 12-bit buffered DAC channels are used to generate variable analog outputs. The DACs are designed with integrated resistor strings structure. The DAC channels can be triggered by the timer update outputs or EXTI with DMA support. In dual DAC channel operation, conversions could be done independently or simultaneously. The maximum output value of the DAC is VREF+. 3.8 DMA  7 channel DMA 1 controller and 5 channel DMA 2 controller  Peripherals supported: Timers, ADC, SPIs, I Cs, USARTs, DAC, I S 2 2 The flexible general-purpose DMA controllers provide a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Four types of access method are supported: peripheral to peripheral, peripheral to memory, memory to peripheral, memory to memory Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel requests are determined by software configuration and hardware channel number. Transfer size of source and destination are independent and configurable. 3.9 General-purpose inputs/outputs (GPIOs)  Up to 112 fast GPIOs, all mappable on 16 external interrupt vectors (EXTI)  Analog input/output configurable  Alternate function input/output configurable There are up to 112 general purpose I/O pins (GPIO) in GD32F105xx, named PA0 ~ PA15 and PB0 ~ PB15, PC0 ~ PC15, PD0 ~ PD15, PE0 ~ PE15, PF0-PF15, PG0-PG15 to implement logic input/output functions. Each of the GPIO ports has related control and configuration registers to satisfy the requirements of specific applications. The external interrupts on the GPIO pins of the device have related control and configuration registers in the External Interrupt Control Unit (EXTI). The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility on the package pins. Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current capable except for analog inputs. 25 / 43 GD32F105xx 3.10 Timers and PWM generation  Up to two 16-bit advanced-control timer (TM1 & TM8), ten 16-bit general-purpose timers (GPTM), and two 16-bit basic timer (TM6 & TM7)  Up to 4 independent channels of PWM, output compare or input capture for each GPTM and external trigger input  16-bit, motor control PWM advanced-control timer with programmable dead-time generation for output match  Encoder interface controller with two inputs using quadrature decoder  24-bit SysTick timer down counter  2 watchdog timers (Independent watchdog and window watchdog) The advanced-control timer (TM1 & TM8) can be seen as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable dead-time generation. It can also be used as a complete general-purpose timer. The 4 independent channels can be used for  Input capture  Output compare  PWM generation (edge- or center-aligned counting modes)  Single pulse mode output If configured as a general-purpose 16-bit timer, it has the same functions as the TMx timer. It can be synchronized with external signals or to interconnect with other GPTMs together which have the same architecture and features. The general-purpose timer (GPTM), known as TM2 ~ TM5, TM9 ~ TM11, TM12 ~ TM14 can be used for a variety of purposes including general time, input signal pulse width measurement or output waveform generation such as a single pulse generation or PWM output, up to 4 independent channels for input capture/output compare. The GPTM also supports an encoder interface with two inputs using quadrature decoder. The basic timer, known as TM6 and TM7 are mainly used for DAC trigger generation. They can also be used as a simple 16-bit time base. The GD32F105xx have two watchdog peripherals, Independent watchdog and window watchdog. They offer a combination of high safety level, flexibility of use and timing accuracy. The independent watchdog timer includes a 12-bit down-counting counter and a 8-bit prescaler, It is clocked from an independent 40 kHz internal RC and as it operates independently of the main clock, it can operate in stop and standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. The window watchdog is based on a 7-bit down counter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in 26 / 43 GD32F105xx debug mode. The SysTick timer is dedicated for OS, but could also be used as a standard down counter. It features: 3.11  A 24-bit down counter  Auto reload capability  Maskable system interrupt generation when the counter reaches 0  Programmable clock source Real time clock (RTC)  32-bit up-counter with a programmable 20-bit prescaler  Alarm function  Interrupt and wake-up event The real time clock is an independent timer which provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and an expected interrupt. The RTC features a 32-bit programmable counter for long-term measurement using the compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz from external crystal oscillator. 3.12 Inter-integrated circuit (I2C)  Up to two I2C bus interfaces can support both master and slave mode with a frequency up to 400 kHz  Provide arbitration function, optional PEC (packet error checking) generation and checking  Supports 7-bit and 10-bit addressing mode and general call addressing mode The I2C interface is an internal circuit allowing communication with an external I2C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line (SCL). The I2C module provides two data transfer rates: 100 kHz of standard mode or 400 kHz of the fast mode. The I2C module also has an arbitration detect function to prevent the situation where more than one master attempts to transmit data to the I2C bus at the same time. A CRC-8 calculator is also provided in I2C interface to perform packet error checking for I2C data. 27 / 43 GD32F105xx 3.13 Serial peripheral interface (SPI)  Up to two SPI interfaces with a frequency of up to 18 MHz  Support both master and slave mode  Hardware CRC calculation and transmit automatic CRC error checking The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO & MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by the DMA controller. The SPI interface may be used for a variety of purposes, including simplex synchronous transfers on two lines with a possible bidirectional data line or reliable communication using CRC checking. 3.14 Universal synchronous asynchronous receiver transmitter (USART)  Up to three USARTs with operating frequency up to 4.5 MHz  Supports both asynchronous and clocked synchronous serial communication modes  IrDA SIR encoder and decoder support  LIN break generation and detection  USARTs support ISO 7816-3 compliant smart card interface The USART (USART1, USART2 and USART3) are used to translate data between parallel and serial interfaces, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232 standard communication. The USART includes a programmable baud rate generator which is capable of dividing the system clock to produce a dedicated clock for the USART transmitter and receiver. The USART also supports DMA function for high speed data communication except UART5. 3.15 Inter-IC sound (I2S)  Two I2S bus Interfaces with sampling frequency from 8 kHz to 192 kHz  Support either master or slave mode The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio applications by 3-wire serial lines. GD32F105xx contain two I2S-bus interfaces that can be operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI2 and SPI3. The audio sampling frequency from 8 kHz to 192 kHz is supported with less than 0.5% accuracy error. 28 / 43 GD32F105xx 3.16 Universal serial bus on-the-go full-speed (USB OTG FS)  One USB device/host/OTG full-speed Interface with frequency up to 12 Mbit/s  Internal main PLL for USB CLK compliantly The Universal Serial Bus (USB) is a 4-wire bus with 4 bidirectional endpoints. The device controller enables 12 Mbit/s data exchange with integrated transceivers in device/host/OTG mode. Full-speed peripheral is compliant with the USB 2.0 specification. Transaction formatting is performed by the hardware, including CRC generation and checking. The status of a completed USB transfer or error condition is indicated by status registers. An interrupt is also generated if enabled. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator) and the operating frequency divided from APB1 should be 12 MHz above. 3.17 Controller area network (CAN)  Two CAN2.0B interface with communication frequency up to 1 Mbit/s  Internal main PLL for USB CLK compliantly Controller area network (CAN) is a method for enabling serial communication in field bus. The CAN protocol has been used extensively in industrial automation and automotive applications. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three mailboxes for transmission and two FIFOs of three message deep for reception. It also provides 14 scalable/configurable identifier filter banks for selecting the incoming messages needed and discarding the others. 3.18 External memory controller (EXMC)  Supported external memory: SRAM, PSRAM, ROM and NOR-Flash, NAND Flash and CF card  Up to 16-bit data bus  Support to interface with Motorola 6800 and Intel 8080 type LCD directly External memory controller (EXMC) is an abbreviation of external memory controller. It is divided in to several sub-banks for external device support, each sub-bank has its own chip selection signal but at one time, only one bank can be accessed. The EXMC support code execution from external memory except NAND Flash and CF card. The EXMC also can be configured to interface with the most common LCD module of Motorola 6800 and Intel 8080 series and reduce the system cost and complexity. 29 / 43 GD32F105xx 3.19 Debug mode  Serial wire JTAG debug port (SWJ-DP) ® The ARM SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. 3.20 Package and operation temperature  LQFP144 (GD32F105Zx), LQFP100 (GD32F105Vx), LQFP64 (GD32F105Rx)  Operation temperature range: -40°C to +85°C (industrial level) 30 / 43 GD32F105xx 4 Electrical characteristics 4.1 Absolute maximum ratings The maximum ratings are the limits to which the device can be subjected without permanently damaging the device. Note that the device is not guaranteed to operate properly at the maximum ratings. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Table 3. Absolute maximum ratings Symbol Min Max Unit VDD External voltage range VSS - 0.3 VSS + 3.6 V VDDA External analog supply voltage VSSA - 0.3 VSSA + 3.6 V VBAT External battery supply voltage VSS - 0.3 VSS + 3.6 V Input voltage on 5V tolerant pin VSS - 0.3 VDD + 4.0 V Input voltage on other I/O VSS - 0.3 4.0 V VIN IIO Maximum current for GPIO pins — 25 mA TA Operating temperature range -40 +85 °C Storage temperature range -55 +150 °C Maximum junction temperature — 125 °C TSTG TJ 4.2 Parameter Recommended DC characteristics Table 4. DC operating conditions Symbol Parameter Conditions Min Typ Max Unit VDD Supply voltage — 2.6 3.3 3.6 V VDDA Analog supply voltage Same as VDD 2.6 3.3 3.6 V VBAT Battery supply voltage — 1.8 — 3.6 V 31 / 43 GD32F105xx 4.3 Power consumption The power measurements specified in the tables represent that code with data executing from on-chip Flash with the following specifications. Table 5. Power consumption characteristics Symbol Parameter Conditions VDD=VBAT=3.3V, HSE=8MHz, System Min Typ Max Unit — 45.2 — mA — 36.0 — mA -— 32.4 — mA — 26.1 — mA — 23.2 — mA — 13.9 — mA — 0.65 1.4 mA — 20.5 — μA — 10.1 — μA — 6.8 — μA clock=108 MHz, All peripherals enabled VDD=VBAT=3.3V, HSE=8MHz, System clock Supply current =108 MHz, All peripherals disabled (Run mode) VDD=VBAT=3.3V, HSE=8MHz, System clock =72MHz, All peripherals enabled VDD=VBAT=3.3V, HSE=8MHz, System Clock =72 MHz, All peripherals disabled VDD=VBAT=3.3V, HSE=8MHz, CPU clock IDD Supply current (Sleep mode) off, All peripherals enabled VDD=VBAT=3.3V, HSE=8MHz, CPU clock off, All peripherals disabled Supply current (Deep-Sleep mode) Supply current VDD=VBAT=3.3V, All clock off, LSI on, RTC on, All GPIOs analog mode VDD=VBAT=3.3V, LDO off, LSE off, LSI on, (Standby mode) RTC on Battery supply IBAT current (Standby mode) VDD not available, VBAT=3.3V, LDO off, LSE on, LSI off, RTC on VDD not available, VBAT=3.3 V, LDO off, LSE off, LSI on, RTC on 32 / 43 GD32F105xx 4.4 EMC characteristics EMS (electromagnetic susceptibility) includes ESD (Electrostatic discharge, positive and negative) and FTB (Burst of Fast Transient voltage, positive and negative) testing result is given in the following table, based on the EMS levels and classes compliant with IEC 61000 series standard. Table 6. EMS characteristics Symbol VESD Parameter Conditions Voltage applied to all device pins to VDD = 3.3 V, TA = +25 °C induce a functional disturbance conforms to IEC 61000-4-2 Fast transient voltage burst applied to VFTB Level/Class induce a functional disturbance through 100 pF on VDD and VSS pins 3A VDD = 3.3 V, TA = +25 °C 4A conforms to IEC 61000-4-4 EMI (Electromagnetic Interference) emission testing result is given in the following table, compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 7. EMI characteristics Symbol Parameter Conditions VDD = 3.3 V, SEMI Peak level TA = +25 °C, compliant with IEC 61967-2 4.5 Conditions Tested frequency band Unit 56M 72M 108M 0.1 to 2 MHz