eMMC 32GB
MKEV032GCB-SS510
Specification
V1.0
May 10, 2019
MKEV032GCB-SS510
Contents
1. Foreword ..................................................................................................................................... 6
2. Revision History ....................................................................................................................... 7
3. Statement of Scope ................................................................................................................ 8
4. General Description ................................................................................................................ 9
4.1.
Product list ..................................................................................................................... 9
4.2.
Feature ............................................................................................................................ 9
5. Functional Description ......................................................................................................... 11
6. Product Specifications ......................................................................................................... 12
6.1.
Performance (Typical Value) ................................................................................. 12
6.2.
Electrical Characteristics......................................................................................... 12
6.3.
Product Architecture ................................................................................................ 14
6.4.
Operational Environment ....................................................................................... 15
7. Package Configurations ....................................................................................................... 17
7.1.
eMMC 153 Ball Array view ..................................................................................... 17
7.2.
eMMC Pin Description .............................................................................................. 18
7.3.
eMMC Pin Assignment ............................................................................................. 18
7.4.
153 Ball Pin Configuration ..................................................................................... 20
8. Usage Overview ..................................................................................................................... 21
8.1.
General Description .................................................................................................. 21
8.2.
Partition Management ............................................................................................. 21
8.3.
Boot operation mode ............................................................................................... 23
8.4.
Device identification mode .................................................................................... 25
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MKEV032GCB-SS510
8.5.
Interrupt mode ........................................................................................................... 25
8.6.
Data transfer mode .................................................................................................. 26
8.7.
High Priority Interrupt ............................................................................................. 28
8.8.
High-speed mode selection ................................................................................... 28
8.9.
HS200 timing mode selection .............................................................................. 29
8.10. HS400 timing mode selection .............................................................................. 29
8.11. Bus width selection ................................................................................................... 30
9. Timing ........................................................................................................................................ 31
9.1.
Time Out ....................................................................................................................... 31
9.2.
Bus Timing ................................................................................................................... 31
9.3.
High-Speed e•MMC interface timing.................................................................. 32
9.4.
Backward compatible e•MMC interface timing .............................................. 32
9.5.
Bus Timing for DAT Signals During 2X Data Rate Operation ................... 34
9.6.
Bus Timing Specification in HS200 mode ........................................................ 35
9.7.
Bus Timing Specification in HS400 mode ........................................................ 38
9.8.
H/W Reset operation ................................................................................................ 42
9.9.
Power-up sequence .................................................................................................. 43
10. Device Register ...................................................................................................................... 44
10.1. CID Register ................................................................................................................ 44
10.2. OCR Register ............................................................................................................... 44
10.3. CSD Register ............................................................................................................... 45
10.4. Extended CSD Register ........................................................................................... 46
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MKEV032GCB-SS510
List of Figures
FIGURE 6- 1 BUS SIGNAL LEVELS......................................................................................13
FIGURE 6- 2 PRODUCT ARCHITECTURE ..............................................................................14
FIGURE 7- 1 EMMC 153 BALL ARRAY VIEW (TOP VIEW) ........................................................17
FIGURE 7- 2 EMMC 153 BALL PIN CONFIGURATION..............................................................20
FIGURE 8- 1 DEVICE POWER DIAGRAM ..............................................................................21
FIGURE 8- 2 PARTITIONS AND USER DATA AREA CONFIGUATION ..........................................22
FIGURE 8- 3 BOOT OPERATION MODE ................................................................................23
FIGURE 8- 4 STATE DIAGRAM (ALTERNATIVE BOOT MODE) ...................................................24
FIGURE 8- 5 STATE DIAGRAM (BOOT MODE) .......................................................................24
FIGURE 8- 6 STATE DIAGRAM (CARD IDENTIFICATION MODE)...............................................25
FIGURE 8- 7 STATE TRANSITION DIAGRAM, INTERRUPT MODE ..............................................26
FIGURE 8- 8 STATE DIAGRAM (DATA TRANSFER MODE) ........................................................27
FIGURE 9- 1 TIMING DIAGRAM: DATA INPUT/OUTPUT ..........................................................31
FIGURE 9- 2 OUTPUT TIMING ...........................................................................................33
FIGURE 9- 3 TIMING DIAGRAM: DATA INPUT/OUTPUT IN DUAL DATA RATE MODE ....................34
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List of Table
TABLE 4- 1 EMMC PRODUCT LIST ................................................................................................................................ 9
TABLE 6- 1 PERFORMANCE (TYPICAL VALUE) ....................................................................................................... 12
TABLE 6- 2 ELECTRICAL CHARACTERISTICS- GENERAL ................................................................................... 12
TABLE 6- 3 POWER SUPPLY VOLTAGE ....................................................................................................................... 13
TABLE 6- 4 SUPPLY CURRENT ...................................................................................................................................... 13
TABLE 6- 5 INTERNAL RESISTANCE AND DEVICE CAPACITANCE .................................................................. 13
TABLE 6- 6 BUS SIGNAL LEVELS ................................................................................................................................ 14
TABLE 6- 7 PRODUCT ARCHITECTURE ..................................................................................................................... 15
TABLE 6- 8 OPERATIONAL ENVIRONMENT.............................................................................................................. 15
TABLE 7- 1 EMMC PIN DESCRIPTION ....................................................................................................................... 18
TABLE 7- 2 EMMC PIN ASSIGNMENT ........................................................................................................................ 18
TABLE 8- 1 PARTITION CONFIGURATION TABLE .................................................................................................. 23
TABLE 9- 1 TIME OUT TABLE ........................................................................................................................................ 31
TABLE 9- 2 HIGH SPEED MODE TIMING .................................................................................................................. 32
TABLE 9- 3 BACKWARD-COMPATIBLE DEVICE MODE TIMING ........................................................................ 32
TABLE 9- 4 HIGH-SPEED DUAL DATA RATE INTERFACE TIMINGS ................................................................. 34
TABLE 10- 1 CID TABLE.................................................................................................................................................. 44
TABLE 10- 2 OCR TABLE ................................................................................................................................................ 45
TABLE 10- 3 CSD TABLE................................................................................................................................................. 45
TABLE 10- 4 EXTENDED CSD TABLE ......................................................................................................................... 47
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MKEV032GCB-SS510
1. Foreword
This document has been produced by MKEV032GCB-SS510 , should the company
modifies the contents of this specification, it will be re-released with an identifying change of
release date and an increase in revision number as follows:
Revision mn.xy, where:
mn the first two digit are incremented for major changes of substance, e.g., functional
changes.
xy the second two digits are incremented when minor changes have been incorporated
into the specification, i.e., enhancements, corrections, updates, etc.
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MKEV032GCB-SS510
2. Revision History
Revision
Date
Modified By
1.0
2019/05/10
Ian Lin
Description
Initial release
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MKEV032GCB-SS510
3. Statement of Scope
This Datasheet document is described the eMMC MKEV032GCB-SS510 of methods and
abstractions of reliability. The contents include the concept and measurement methodologies.
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MKEV032GCB-SS510
4. General Description
MKEV032GCB-SS510 e•MMC is an embedded storage solution designed in a BGA package form.
The operation of e•MMC is compatible with e•MMC 5.1 which is an industry standard.
The e•MMC consists of NAND flash and a controller. 3.3V supply voltage is required for the NAND
area (VCC)， whereas 1.8V or 3.3V dual supply voltage is supported for the interface.
There are several advantages of e•MMC. It is easy to be used on the standard interface, which
allows the easy and widely used integration with general CPU. Any revision or amendment of
NAND is invisible to the host as the embedded e•MMC controller insulates NAND technology from
the host. It means that the host can support the newest processing flash without updating its
hardware or software.
MKEV032GCB-SS510 e•MMC has high performance at a competitive-cost, high quality and low power
consumption. e•MMC provides capacities from 4GB to 64GB.
4.1. Product list
Table 4- 1 eMMC product list
Capacities
Part Number
Flash Type
User Density
32GB
MKEV032GCB-
256Gb TLCx1
91.5 %
Package Size
Package
(mm)
Type
11.5x13x1.0
153FBGA
SS510
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4.2. Feature
Compatible to JEDEC Embedded Multi-Media Card (e•MMC) Electrical Standard (5.1)
Data bus width: 1bit, 4bit and 8bit.
Power-down safeguard
Hardware ECC engine
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Unique firmware backup mechanism
Global wear leveling to expend NAND flash endurance
IDA（Initial Data Accelerating）
Backward Compatible with JEDEC standard
Supports HS400 mode
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MKEV032GCB-SS510
5. Functional Description
MKEV032GCB-SS510 e•MMC with powerful L2P NAND Flash management algorithm provides unique
functions:
Host independence from details of operating NAND flash.
Internal ECC to correct defect in NAND flash.
Power-down safeguard.
To prevent from false operating, a mechanism named power-down safeguard is added in the
e•MMC. In the case of sudden power-losing, the e•MMC would work properly when it gets
power again.
Global wear leveling.
To achieve the best stability and device endurance, this e•MMC equips the Global Wear
Leveling algorithm. It ensures that not only normal area, but also the frequently accessed
area, such as FAT, would be programmed and erased evenly.
IDA（Initial Data Accelerating）
IDA may accelerate the Initial data written to the e•MMC, saving the time up to 50% off in
the downloading process.
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MKEV032GCB-SS510
6. Product Specifications
6.1. Performance (Typical Value)
Table 6- 1 Performance (Typical Value)
Part Number
MKEV032GCBSS510
Capacity
32GB
Interleave
Mode
Operation
I0
SLC
Sustained
Sequential
Sequential
Write
(MB/s)
HS400
(MB/s)
Read
Write
120
260
18
Test Condition: Bus width x8, 200MHz DDR, 512KB data transfer, w/o file system overhead,
measured on internal board.
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6.2. Electrical Characteristics
General
Table 6- 2 Electrical Characteristics- General
Parameter
Peak voltage on all lines
Symbol
Test
Conditions
Min.
Max.
Unit
-
-
-0.5
VCCQ+0.5
V
-
-
-100
100
µA
-
-
-2
2
µA
-
-100
100
µA
-
-2
2
µA
All Inputs
Input Leakage Current (before initialization
sequence1 and/or the internal pull up
resistors connected)
Input Leakage Current (after initialization
sequence and the internal pull up resistors
disconnected)
All Outputs
Output Leakage Current (before initialization
sequence)
Output Leakage Current (after initialization
sequence)
Note*：
Initialization sequence is defined in Power-Up chapter of JEDEC/MMCA Standard.
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MKEV032GCB-SS510
Power Supply Voltage
Table 6- 3 Power Supply Voltage
Parameter
Symbol
Min.
Max.
Unit
Supply voltage 1 (NAND)
VCC
2.7
3.6
V
Supply voltage 2 (I/O)
VCCQ
2.7
1.7
3.6
1.95
V
Remark
Supply Current
Table 6- 4 Supply Current
Parameter
Symbol
Interleave
VccQ
ICCQ
(Max)
1.8V
3.3V
1.8V
3.3V
1.8V
100
100
115
120
150
250
60
60
75
80
120
mA
HS200
1.8V
1.8V
3.3V
1.8V
3.3V
1.8V
HS400
1.8V
120
mA
Mode
SDR
Read
IROP
Non
Interleave
DDR
HS200
HS400
Operation
(RMS)
SDR
Write
IWOP
Non
Interleave
DDR
Unit
mA
mA
mA
mA
mA
mA
Internal resistance and Device capacitance
Table 6- 5 Internal resistance and Device capacitance
Parameter
Symbol
Single device capacitance
CDEVICE
Internal pull up resistance DAT1 – DAT7
RINT
Test
Min
10
Bus Signal Levels
Figure 6- 1 Bus Signal Levels
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Max
Unit
6
pF
150
KΩ
MKEV032GCB-SS510
Table 6- 6 Bus Signal Levels
Parameter
Symbol
Test
Conditions
Min.
Max.
Unit
Open-Drain Mode Bus Signal Level
Output HIGH voltage
VOH
IOH = -100uA
Output LOW voltage
VOL
IOL = 2mA
VccQ - 0.2
V
0.3
V
Push-Pull Mode Bus Signal Level (High-Voltage)
Output HIGH voltage
VOH
Output LOW voltage
VOL
Input HIGH voltage
VIH
Input LOW voltage
VIL
IOH = -100uA @
VDD min
IOL = 100uA @
VDD min
0.75*VCCQ
V
0.125* VCCQ
V
0.625* VCCQ
VCCQ + 0.3
V
VSS - 0.3
0.25* VCCQ
V
Push-Pull Mode Bus Signal Level (Dual-Voltage)
Output HIGH voltage
VOH
Output LOW voltage
VOL
Input HIGH voltage
VIH
Input LOW voltage
VIL
IOH = -2mA @
VDD min
IOL = 2mA @
VDD min
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6.3. Product Architecture
Figure 6- 2 Product Architecture
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VCCQ - 0.45
V
0.45
V
0.65* VCCQ
VCCQ + 0.3
V
VSS - 0.3
0.35* VCCQ
V
MKEV032GCB-SS510
Table 6- 7 Product Architecture
Parameter
Symbol
Unit
Min.
Typ.
Max.
VDDi capacitor value
CREG
uF
0.1
1
2.2
VCC capacitor value
CVCC
uF
-
2.2+0.1
-
VCCQ capacitor value
CVCCQ
uF
-
2.2+0.1
-
Note*：
e•MMC recommends that the minimum value should be usually applied as the value of CREG; CREG
shall be compliant with X5R/X7R of EIA standard or B of JIS standard.
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6.4. Operational Environment
Table 6- 8 Operational Environment
Mode
Temperature
Operating
-25℃ to 85℃
Storage without operation
-40℃ to 85℃
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7. Package Configurations
7.1. eMMC 153 Ball Array view
Figure 7- 1 eMMC 153 ball Array view (Top view)
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MKEV032GCB-SS510
7.2. eMMC Pin Description
Table 7- 1 eMMC Pin Description
Pin
Number
Name
Pin
Number
Name
Pin
Number
Name
Pin
Number
Name
A3
DAT0
C2
VDDi
J5
VSS
N4
VCCQ
A4
DAT1
C4
VSSQ
J10
VCC
N5
VSSQ
A5
DAT2
C6
VCCQ
K5
RSTN
P3
VCCQ
A6
VSS
E6
VCC
K8
VSS
P4
VSSQ
B2
DAT3
E7
VSS
K9
VCC
P5
VCCQ
B3
DAT4
F5
VCC
M4
VCCQ
P6
VSSQ
B4
DAT5
G5
VSS
M5
CMD
B5
DAT6
H5
DS
M6
CLK
B6
DAT7
H10
VSS
N2
VSSQ
Note*：
NC: No Connect, can be connected to ground or left floating.
RFU: Reserved for Future Use, should be left floating for future use.
VSF: Vendor Specific Function, shall be left floating.
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7.3. eMMC Pin Assignment
Table 7- 2 eMMC Pin Assignment
Signal
CLOCK
(CLK)
Description
Each cycle of the clock directs a transfer on the command line and on the data
lines. The frequency can vary between the minimum and the maximum clock
frequency.
This signal is a bidirectional command channel used for device initialization and
command transfer.
COMMAND
(CMD)
The CMD Signal has 2 operation modes: open drain, for initialization, and pushpull, for command transfer.
Commands are sent from the host to the device, and responses are sent from
the device to the host.
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MKEV032GCB-SS510
These are bidirectional data signal. The DAT signals operate in push-pull
mode.
By default, after power-up or RESET, only DAT0 is used for data transfer. The
controller can configure a wider data bus for data transfer withers using DAT
DATA
(DAT0-DAT7)
[3:0] (4bit mode) or DAT [7:0] (8bit mode).
Includes internal pull-up resistors for data lines DAT [7:1]. Immediately after
entering the 4-bit mode, the device disconnects the internal pull-up resistors
on the DAT1 and DAT2 lines.(The DAT3 line internal pull-up is left
connected.)Upon entering the 8bit mode, the device disconnects the internal
pull-up on the DAT1, DAT2, and DAT[7:4] lines.
RESET
(RSTN)
DS
VCCQ
VCC
VDDi
VSS,VSSQ
Hardware Reset Input
Data Strobe: Return Clock signal used in HS400 mode
VCCQ is the power supply line for host interface, have two power mode: High
power mode:2.7V~3.6V; Lower power mode:1.7V~1.95V
VCC is the power supply line for internal flash memory, its power voltage range
is:2.7V~3.6V
VDDi is internal power node, not the power supply. Connect 0.1uF or 1uF
capacitor VDDi to ground
Ground lines.
Note*： All other pins are not connected [NC] and can be connected to GND or left floating.
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MKEV032GCB-SS510
7.4. 153 Ball Pin Configuration
Figure 7- 2 eMMC 153 ball Pin Configuration
Unit: mm
11.5mm×13mm×1.0mm Package Dimension
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MKEV032GCB-SS510
8. Usage Overview
8.1. General Description
The e•MMC can be operated in 1, 4, or 8-bit mode. NAND flash memory is managed by a
controller inside, which manages ECC, wear leveling and bad block management. e•MMC provides
easy integration with the host process that all flash management hassles are invisible to the host.
Figure 8- 1 Device Power Diagram
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8.2. Partition Management
The embedded device offers also the possibility of configuring by the host additional split local
memory partitions with independent addressable space starting from logical address 0x00000000
for different usage models. Default size of each Boot Area Partition is 128 KB and can be changed
by Vendor Command as multiple of 128KB. Boot area partition size is calculated as (128KB *
BOOT_SIZE_MULTI) The size of Boot Area Partition 1 and 2 cannot be set independently and is set
as same value Boot area partition which is enhanced partition. Therefore memory block area scan
is classified as follows:
Factory configuration supplies boot partitions.
The host is free to configure one segment in the User Data Area to be implemented as
enhanced storage media, and to specify its starting location and size in terms of Write
Protect Groups. The attributes of this Enhanced User Data Area can be programmed only
once during the device life-cycle (one-time programmable).
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MKEV032GCB-SS510
Up to four General Purpose Area Partitions can be configured to store user data or sensitive
data, or for other host usage models. The size of these partitions is a multiple of the write
protect group. Size and attributes can be programmed once in device life-cycle (one-time
programmable). Each of the General Purpose Area Partitions can be implemented with
enhanced technological features.
Figure 8- 2 Partitions and user data area configuation
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MKEV032GCB-SS510
Table 8- 1 Partition Configuration Table
Boot1 Size
Boot2 Size
RPMB Size
4MB
4MB
4MB
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8.3. Boot operation mode
In boot operation mode, the master can read boot data from the slave (device) by keeping CMD
line low or sending CMD0 with argument + 0xFFFFFFFA, before issuing CMD1. The data can be
read from either boot area or user area depending on register setting.
Figure 8- 3 Boot operation mode
State diagram (boot mode)
Boot operation complete Clock = 400 kHz
(Compatible with the description which ≤400kHz)
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MKEV032GCB-SS510
Figure 8- 4 State diagram (alternative boot mode)
Figure 8- 5 State diagram (boot mode)
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MKEV032GCB-SS510
8.4. Device identification mode
While in device identification mode the host resets the device, validates operation voltage range
and access mode, identifies the device and assigns a Relative device Address (RCA) to the device
on the bus. All data communication in the Device Identification Mode uses the command line
(CMD) only.
Figure 8- 6 State diagram (card identification mode)
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8.5. Interrupt mode
The interrupt mode on the system enables the master (host) to grant the transmission allowance
to the slaves (card) simultaneously. This mode reduces the polling load for the host and hence,
the power consumption of the system, while maintaining adequate responsiveness of the host to a
card request for service. Supporting interrupt mode is an option, both for the host and the card.
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MKEV032GCB-SS510
Figure 8- 7 State transition diagram, interrupt mode
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8.6. Data transfer mode
All data communication in the Data Transfer Mode is point-to point between the host and the
selected card (using addressed commands). All addressed commands get acknowledged by a
response on the CMD line.
While the card is in Stand-by State, CMD7 is used to select the card and put it into the Transfer
State by including card‘s relative address in the argument. If the card was previously selected and
was in Transfer State its connection with the host is released and it will move back to the Standby State when deselected by CMD7 with any address in the argument that is not equal to card‘s
own relative address. When CMD7 is issued with the reserved relative card address “0x0000”, the
card is put back to Stand-by State. Reception of CMD7 with card‘s own relative address while the
card is in Transfer State is ignored by the card and may be treated as an Illegal Command. After
the card is assigned an RCA it will not respond to identification commands — CMD1, CMD2, or
CMD3.
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MKEV032GCB-SS510
While the card is in Disconnect State, CMD7 is used to select the card and put it into the
Programming State by including card‘s relative address in the argument. If the card was
previously selected and was in Programming State its connection with the host is released and it
will move back to the Disconnect State when deselected by CMD7 with any address in the
argument that is not equal to card‘s own relative address. Reception of CMD7 with card‘s own
relative address while the card is in Programming State is ignored by the card and may be treated
as an Illegal Command.
Figure 8- 8 State diagram (data transfer mode)
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MKEV032GCB-SS510
8.7. High Priority Interrupt
The high priority interrupt (HPI) mechanism enables servicing high priority requests, by allowing
the device to interrupt a lower priority operation before it is actually completed, within
OUT_OF_INTERRUPT _TIME timeout. Host may need to repeat the interrupted operation or part of
it to complete the original request. The HPI command may have one of two implementations in
the device:
CMD12 – based on STOP_TRANSMISSION command when the HPI bit in its argument is set.
CMD13 – based on SEND_STATUS command when the HPI bit in its argument is set.
Host shall check the read-only HPI_IMPLEMENTATION bit in HPI_FEATURES (EXT_CSD byte [503])
and use the appropriate command index accordingly.
CMD Index
Name
Is interruptible?
CMD24
WRITE_BLOCK
Yes
CMD25
WRITE_MULTIPLE_BLOCK
Yes
CMD38
ERASE
Yes
CMD6
SWITCH, byte BKOPS_START, any value
Yes
CMD6
Yes
CMD6
SWITCH, byte SANITIZE_START, any value
SWITCH, byte POWER_OFF_NOTIFICATION, value
POWER_OFF_LONG or SLEEP_NOTIFICATION
SWITCH, byte POWER_OFF_NOTIFICATION, other values
CMD6
CACHE_CTRL when used for turning the cache OFF
Yes
CMD6
FLUSH_CACHE
Yes
CMD6
SWITCH, other bytes, any value
No
CMD6
All others
Yes
No
No
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8.8. High-speed mode selection
After the host verifies that the Device complies with version 4.0, or higher, of this standard, it has
to enable the high speed mode timing in the Device, before changing the clock frequency to a
frequency between 26MHz and 52MHz. For the host to change to a higher clock frequency, it has
to enable the high speed interface timing. The host uses the SWITCH command to write 0x01 to
the HS_TIMING byte, in the Modes segment of the EXT_CSD register. If the host tries to write an
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MKEV032GCB-SS510
invalid value, the HS_TIMING byte is not changed, the high speed interface timing is not enabled,
and the SWITCH_ERROR bit is set.
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8.9. HS200 timing mode selection
HS200 is valid only at VCCQ= 1.8 V.
The bus width is set to SDR 4bit or SDR 8bit in HS200 mode.
After the host initializes the device, it must verify that the device supports the HS200 mode
by reading the DEVICE_TYPE field in the Extended CSD register. Then it may enable the
HS200 timing mode in the device, before changing the clock frequency to a frequency higher
than 52MHz.
After power-on or software reset(CMD0), the interface timing of the device is set as the
default “Backward Compatible Timing “. Device shall select HS200 Timing mode if required
and perform the Tuning process if needed.
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8.10. HS400 timing mode selection
The valid IO Voltage for HS400 is 1.8V for VCCQ.
The bus width is set to only DDR 8bit in HS400 mode.
HS400 supports the same commands as DDR52.
After the host initializes the device, host check whether the device supports the HS400 mode by
reading the DEVICE_TYPE field in the Extended CSD register. Then it enables the HS400 mode in
the device before changing the clock frequency to a frequency higher than 52 MHz. After poweron or software reset (CMD0), the interface timing of the device is set as the default “Backward
Compatible Timing”.
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MKEV032GCB-SS510
8.11. Bus width selection
After the host has verified the functional pins on the bus it should change the bus width
configuration accordingly, using the SWITCH command. The bus width configuration is
changed by writing to the BUS_WIDTH byte in the Modes Segment of the EXT_CSD register
(using the SWITCH command to do so). After power-on, or software reset, the contents of the
BUS_WIDTH byte is 0x00.
If the host tries to write an invalid value, the BUS_WIDTH byte is not changed and the
SWITCH_ERROR bit is set. This register is written only.
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MKEV032GCB-SS510
9. Timing
9.1. Time Out
Table 9- 1 Time Out Table
Timing parameter
Value
Read timeout
100 ms
Write timeout
350 ms
Erase timeout
600 ms
Force erase timeout
3 min
Trim timeout
300 ms
Partition switching time out (after init )
30 ms
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9.2. Bus Timing
Figure 9- 1 Timing diagram: data input/output
Data must always be sampled on the rising edge of the clock
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MKEV032GCB-SS510
9.3. High-Speed e•MMC interface timing
Table 9- 2 High speed mode timing
Parameter
Symbol
Min.
Max.
Unit
Remark
fPP
0
52
MHz
CL ≤ 30pF
Tolerance:
+100KHz
0
400
KHz
Tolerance: +20KHz
6.5
-
ns
CL ≤ 30pF
-
3
ns
CL ≤ 30pF
Clock CLK(1)
Clock frequency Data Transfer
Mode (PP) (2)
Clock frequency Identification
FOD
Mode(OD)
Clock low time / Clock high
tWL/tWH
time
Clock rise time / Clock fall
tTLH/tTHL
time
Inputs CMD, DAT (referenced to CLK)
(3)
Input set-up time
tISU
3
-
ns
CL ≤ 30pF
Input hold time
tIH
3
-
ns
CL ≤ 30pF
Outputs CMD, DAT (referenced to CLK)
Output delay time during data
tODLY
-
13.7
ns
CL ≤ 30pF
Output hold time
tOH
2.5
-
ns
CL ≤ 30pF
trise
-
3
ns
CL ≤ 30pF
tfall
-
3
ns
CL ≤ 30pF
Signal rise time
(5)
Signal fall time
Note*：
1)
CLK timing is measured at 50% of VccQ.
2)
e•MMC shall support the full frequency range from 0-26MHz, or 0-52MHz.
3)
e•MMC can operate as high-speed interface timing at 26MHz clock frequency.
4)
CLK rise and fall times are measured by min(VIH) and max(VIL).
5)
Inputs CMD,DAT rise and fall times area measured by min(VIH) and max(VIL), and outputs CMD,
DAT rise and fall times are measured by min(VOH) and max(VOL).
Top page
9.4. Backward compatible e•MMC interface timing
Table 9- 3 backward-compatible device mode timing
Parameter
Symbol
Min.
Max.
Unit
Remark
fPP
0
26
MHz
CL ≤ 30pF
fOD
0
400
KHz
Clock CLK(2)
Clock frequency Data Transfer
Mode (PP) (3)
Clock frequency Identification
Mode(OD)
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MKEV032GCB-SS510
Parameter
Clock low time / Clock high
time
Clock rise time / Clock fall
time
Symbol
Min.
Max.
Unit
Remark
tWL/tWH
10
-
ns
CL ≤ 30pF
tTLH/tTHL
-
10
ns
CL ≤ 30pF
Inputs CMD, DAT (referenced to CLK)
Input set-up time
tISU
3
-
ns
CL ≤ 30pF
Input hold time
tIH
3
-
ns
CL ≤ 30pF
Outputs CMD, DAT (referenced to CLK)
Output set‐up time
tOSU
-
13.7
ns
CL ≤ 30pF
Output hold time
tOH
2.5
-
ns
CL ≤ 30pF
Note*：
1)
The e•MMC must always start with the backward-compatible interface timing. The timing mode
can be switched to high-speed interface timing by the host sending the SWITCH command (CMD6)
with the argument for high-speed interface select.
2)
CLK timing is measured at 50% of VccQ
3)
For compatibility with e•MMCs that support the v4.2 standard or earlier, host should not use
>26MHz before switching to high-speed interface timing.
4)
tosu and tOH are defined as values from clock rising edge. However, the e•MMC device will utilize
clock falling edge to output data in backward compatibility mode. Therefore, it is recommended for
hosts either to set tWL value as long as possible within the range which will not go over tCK-tOH(min)
in the system or to use slow clock frequency, so that host could have data set up margin for the
device.
use slow clock frequency, so that host could have data set up margin for the device.
MKEV032GCB-SS510 e•MMC device utilize clock falling edge to output data in backward
compatibility mode.
Host should optimize the timing in order to have data set up margin as follows.
Figure 9- 2 Output timing
Top page
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MKEV032GCB-SS510
9.5. Bus Timing for DAT Signals During 2X Data Rate Operation
These timings applies to the DAT [7:0] signals only when the device is configured for dual data
mode operation. In this dual data mode, the DAT signals operates synchronously of both the rising
and the falling edges of CLK. the CMD signal still operates synchronously of the rising edge of CLK
and therefore complies with the bus timing specified in High-speed interface timing or Backwardcompatible interface timing.
Figure 9- 3 Timing diagram: data input/output in dual data rate mode
Table9- 4 High-speed dual data rate interface timings
Parameter
Symbol
Min.
Max.
Unit
Remark
45
55
%
Includes jitter, phase
noise
Clock CLK(1)
Clock duty cycle
Inputs DAT (referenced to CLK‐DDR mode)
Input set‐up time
tISUDDR
2.5
-
ns
CL ≤ 20 pF
Input hold time
tIHDDR
2.5
-
ns
CL ≤ 20 pF
Outputs DAT (referenced to CLK‐DDR mode)
Output delay time during data
transfer
tODLYDDR
1.5
7
ns
CL ≤ 20 pF
Signal rise time(all signal)(2)
tRISE
-
2
ns
CL ≤ 20 pF
Signal fall time (all signal)
tFALL
-
2
ns
CL ≤ 20 pF
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MKEV032GCB-SS510
Note*：
1) CLK timing is measured at 50% of VccQ.
2) Inputs CMD, DAT rise and fall times are measured by min (VIH) and max (VIL), and outputs CMD,
DAT rise and fall times are measured by min (VOH) and max (VOL).
Top page
9.6. Bus Timing Specification in HS200 mode
HS200 Clock Timing
Host CLK Timing in HS200 mode shall conform to the timing specified in following figure and
Table. CLK input shall satisfy the clock timing over all possible operation and environment
conditions. CLK input parameters should be measured while CMD and DAT lines are stable high or
low, as close as possible to the Device. The maximum frequency of HS200 is 200MHz. Hosts can
use any frequency up to the maximum that HS200 mode allows.
NOTE 1
VIH denote VIH(min.) and VIL denotes VIL(max.).
NOTE 2
VT=0.975V - Clock Threshold, indicates clock reference point for timing measurements.
Symbol
Min.
tPERIOD
5
Max.
Unit
ns
Remark
200MHz (Max.), between rising edges
tTLH, tTHL
tTLH,
tTHL
Duty Cycle
30
0.2 *
tPERIOD
ns
70
%
< 1ns (max.) at 200MHz,
CDEVICE=6pF,The absolute maximum
value of tTLH, tTHL is 10ns regardless
of clock frequency.
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MKEV032GCB-SS510
HS200 Device Input Timing
NOTE1 tISU and tIH are measured at VIL(max.)and VIH(min.)
NOTE2 VIH denote VIH(min.) and VIL denotes VIL(max.).
Symbol
t
ISU
t
IH
Min.
Max.
Unit
Remark
1.40
ns
CDEVICE ≤ 6pF
0.8
ns
CDEVICE ≤ 6pF
HS200 Device Output Timing
tPH parameter is defined to allow device output delay to be longer than tPERIOD. After
initialization, the tPH may have random phase relation to the clock. The Host is responsible to
find the optimal sampling point for the Device outputs, while switching to the HS200 mode.
While setting the sampling point of data, a long term drift, which mainly depends on temperature
drift, should be considered. The temperature drift is expressed by ΔTPH. Output valid data window
(tVW) is available regardless of the drift (ΔTPH) but position of data window varies by the drift.
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MKEV032GCB-SS510
NOTE
Symbol
tPH
ΔTPH
tVW
VOH denotes VOH(min.) and VOL denotes VOL(max.).
Min.
Max.
Unit
0
2
UI
-350
+1550
(ΔT = 90 °C)
ps
(ΔT = -20 °C)
0.575
UI
Remark
Device output momentary phase from
CLK input to CMD or DAT lines output.
Does not include a long term
temperature drift.
Delay variation due to temperature
change after tuning. Total allowable
shift of output valid window (TVW) from
last system Tuning procedure ΔTPH is
2600ps for ΔT from -25 °C to 125 °C
during operation.
tVW =2.88ns at 200MHz Using test
circuit in following figure including skew
among CMD and DAT lines created by
the Device. Host path may add Signal
Integrity induced noise,skews, etc.
Expected tVW at Host input is larger
than 0.475UI.
ΔTPH consideration
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MKEV032GCB-SS510
Implementation Guide:
Host should design to avoid sampling errors that may be caused by the ΔTPH drift.
It is recommended to perform tuning procedure while Device wakes up, after sleep. One simple way
to overcome the ΔTPH drift is by reduction of operating frequency.
Top page
9.7. Bus Timing Specification in HS400 mode
HS400 Input Timing
The CMD input timing for HS400 mode is the same as CMD input timing for HS200 mode.
Note : VIH denote VIH(min) and VIL denotes VIL(max)
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MKEV032GCB-SS510
Parameter
Symbol
Min.
Max.
Unit
Remark
Cycle time data
transfer mode
tPERIOD
5
-
ns
200MHz(Max), between rising edges
With respect to VT
Slew rate
SR
1.125
-
V/ns
Duty cycle
distortion
tCKDCD
0.0
0.3
ns
Allowable deviation from an ideal
50% duty cycle. With respect to VT
Includes jitter, phase noise
Minimum pulse
width
tCKMPW
2.2
-
ns
With respect to VT
Input CLK
With respect to VIH /VIL
Input DAT(referenced to CLK)
Input set-up
time
tISUddr
0.4
-
ns
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